MCIMX7U3CVP06SD [NXP]
i.MX 7ULP Applications Processor-Industrial;型号: | MCIMX7U3CVP06SD |
厂家: | NXP |
描述: | i.MX 7ULP Applications Processor-Industrial |
文件: | 总112页 (文件大小:1954K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
IMX7ULPIECB2
Rev. 1, 07/2021
i.MX 7ULP Applications
Processor—Industrial
MCIMX7U5CVP06SD
MCIMX7U3CVP06SD
The i.MX 7ULP product family members are optimized for power-
sensitive applications benefiting from NXP's Heterogeneous
Multicore Processing (HMP) architecture. Achieving an efficient
balance between processing power and deterministic processing
needs, the i.MX 7ULP is an asymmetric processor consisting of
two separate processing domains: an application domain and a
real-time domain. The application domain is built around an
ARM® Cortex®-A7 processor with an ARM NEON™ SIMD
engine and floating point unit (FPU) and is optimized for rich OS
based applications. The real-time domain is built around an ARM
Cortex-M4 processor (with FPU) optimized for lowest possible
leakage. Both domains are completely independent, with
separate power, clocking, and peripheral domains, but the bus
Plastic package: BGA 14x14mm, 0.5mm pitch
fabric of each domain is tightly integrated for efficient communication. The part is streamlined to minimize pin
count, enabling small packages and simple system integration.
i.MX 7ULP features
Feature type
Application processor domain
Real-time processor domain
ARM Processor
Cortex®-A7
Cortex®-M4
• Nominal (RUN) frequency: 500 MHz
• Overdrive (HSRUN) frequency: 650
MHz
• Nominal (RUN) frequency: 120 MHz
• Overdrive (HSRUN) frequency: 200
MHz
• Very Low Power Run (VLPR)
frequency: 48 MHz
• Very Low Power Run (VLPR)
frequency: 48 MHz
Optimized for lowest leakage current
32 KB instruction and data caches
256 KB L2 cache
NEON™ SIMD engine
FPU
FPU
MPU
—
—
On-chip memory
256 KB of RAM
256 KB of tightly coupled RAM allocated into
32 KB switchable blocks
—
8 KB of OTP memory
External memory
interfaces
16/32-bit LPDDR2/LPDDR3 interface
running at 271.5 MHz
Serial flash interface supporting x4 and x8
IOs
eMMC 5.0 interface
Secure boot
—
Security
Secure boot
Table continues on the next page...
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
i.MX 7ULP features (continued)
Feature type
Application processor domain
Real-time processor domain
Signing and encrypt/decrypt engines
(CAAM)
Encrypt/decrypt engines (LTC)
Simple tamper detection
Four I2C Fast mode plus
SD 3.0/MMC 5.0
—
Serial peripherals
Four I2C Fast mode plus
FlexI/O
Four UARTs with flow control
Two LPSPI peripherals
Four UARTs with flow control
Two LPSPI peripherals
Timers
Four 32-bit general-purpose timers with
capture and compare; one 64-bit timer
Four 32-bit general purpose-timers with
capture and compare; one 64-bit timer
Watchdog timer
Watchdog timer
2
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
NXP Semiconductors
i.MX 7ULP
Application Domain
A7 Connectivity
Timers
32 bit Timer x4
UART x 4
I2C x4
Arm Cortex -A7
System timers
Watch Dog
32KB I-cache
32KB D-cache
SPI x 2
3.3V/1.8V GPIO
256KB L2 cache
DMA
USB2.0 OTG
(w/ PHY)
USB2.0 HOST
(w/ HSIC)
Internal Memory
FPU
ETM
NEON
256K RAM
Trust Zone
32K Secure
Memory
Graphics
FlexIO
GC320
Composition
GC7000
NanoULTRA
Security
Crypto / TRNG
External Memory
16/32-bit LPDDR2/3
Camera
Display
HAB– Secure Boot
Secure Fuse
MMC5.0/SDIO x 2
FlexBUS
MIPI DSI
VIU
Clock and Power
Management System
Security – Batt Domain
Key
Storage
Tamper
Detection
Secure
RTC
Power
Manager
Clock/Reset
PLL/OSC
Real Time Domain
Timers
M4 Connectivity
UART x 4
32 bit Timer x4
System timers
Watch Dog
I2C x4
Arm Cortex -
-
M4
DSP Extensions
- cache
SPI x2
3.3V/1.8V GPIO
Access and IPC
8KB I/D
XRDC
I2S x 2
DAP
MPU
FPU
Secure JTAG
FlexIO
SEMA4 / Msg Unit
External Memory
Analog
Security
uHAB– Secure Boot
Quad SPI (OTFAD)
2x 12 bit ADC 2x 12 -bit DAC
Analog Comparators
Internal Memory
eFuses / OTP
Crypto / TRNG
256K RAM
Figure 1. i.MX 7ULP Block Diagram
The following table provides examples of orderable sample part numbers covered by this data sheet.
Ordering information
Part Number
Options Cortex- Cortex- Qualification
Junction
Temperature
Range
Package
A7
M4
Tier
Speed
Grade
Speed
Grade
MCIMX7U5CVP06SD GPU-2D, 650 MHz 200 MHz Industrial
-40 to +105 °C 14 mm x 14 mm, 0.5 mm
pitch BGA, Package code
"VP"
GPU-3D
supported
MCIMX7U3CVP06SD No GPU 650 MHz 200 MHz Industrial
-40 to +105 °C 14 mm x 14 mm, 0.5 mm
pitch BGA, Package code
"VP"
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
3
NXP Semiconductors
The following figure describes the part number nomenclature so users can identify the characteristics of the
specific part number.
Figure 2. i.MX 7 Family Part Number Definition
Related Resources
Type
Description
Reference Manual The i.MX 7ULP Applications Processor Reference Manual contains a comprehensive description of
the structure and function (operation) of the SoC.
Data Sheet
Chip Errata
The Data Sheet includes electrical characteristics and signal connections.
The chip mask set errata provides additional or corrective information for a particular device mask
set.
Package drawing
Package dimensions are provided in Package information and contact assignments
The power mode acronyms used throughout this document are defined as follows.
Power mode acronym table
Power mode acronym
Power mode name
HSRUN
RUN
High-speed run mode
Nominal speed run mode
Very low power run mode
Partial stop mode
VLPR
PSTOP
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i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
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NXP Semiconductors
Power mode acronym table (continued)
Power mode acronym
Power mode name
STOP
VLPS
LLS
Stop mode
Very low power stop mode
Low leakage stop mode
VLLS
Very low leakage stop mode
For details on each of these operating modes, see the i.MX 7ULP Applications Processor Reference Manual
(IMX7ULPRM).
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
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NXP Semiconductors
Table of Contents
1
2
i.MX 7ULP modules list.........................................................7
7.1.4
7.1.5
Absolute maximum ratings............................34
Recommended operating conditions—
Clocking................................................................................ 21
2.1 Introduction..................................................................21
2.2 Clock distribution......................................................... 22
2.3 External clock sources.................................................23
2.4 Oscillators....................................................................23
2.5 Internal clock sources..................................................23
Application domain (implementing ARM Cortex-A7).............24
3.1 Memory system—application domain..........................24
system...........................................................35
Estimated maximum supply currents............ 39
7.1.6
7.2 System clocks..............................................................40
7.2.1
7.2.2
Clock modules...............................................40
Core, platform, and system bus clock
3
frequency limitations..................................... 43
Peripheral clock frequencies.........................44
PLL PFD output.............................................47
Audio tunable clock.......................................48
7.2.3
7.2.4
7.2.5
3.1.1
3.1.2
3.1.3
Internal memory (application domain)...........24
Multi Mode DDR Controller (MMDC).............24
eMMC............................................................25
7.3 Power sequencing—system........................................ 49
3.2 Peripherals—application domain.................................25
7.3.1
7.3.2
Power-on sequencing................................... 49
Power-off sequencing................................... 50
3.2.1
Graphics processor human machine
interfaces.......................................................25
Security—application domain........................26
Timers—application domain..........................27
Connectivity and communications—
7.4 Requirements for unused interfaces............................50
7.5 Electrical Characteristics and Thermal Specifications.51
3.2.2
3.2.3
3.2.4
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
AC electrical characteristics..........................51
Nonswitching electrical characteristics..........52
Switching electrical characteristics................53
Debug and trace modules.............................55
Thermal specifications.................................. 59
applications domain...................................... 27
4
Real-time domain (implementing ARM Cortex-M4).............. 28
4.1 Memory system—real-time domain.............................28
4.1.1
4.1.2
Internal memory—real-time domain..............28
QuadSPI flash...............................................28
8
Specifications—application domain...................................... 60
8.1 Peripheral operating requirements and behaviors.......60
4.2 Peripherals—real-time domain.................................... 28
8.1.1
8.1.2
DDR timing—application domain.................. 60
Ultra-high-speed SD/SDIO/MMC host
4.2.1
4.2.2
Analog—real-time domain.............................28
Connectivity and communications—real-
interface (uSDHC) AC timing—application
domain.......................................................... 60
Flexbus switching specifications................... 66
Display, Video, and Audio Interfaces............ 69
Timer specifications—application domain.....70
Connectivity and communications
time domain...................................................29
5
System control modules........................................................29
5.1 JTAG—system control.................................................29
5.2 JTAG device identification register.............................. 29
5.3 Oscillators and PLLs....................................................30
8.1.3
8.1.4
8.1.5
8.1.6
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
System oscillator (SYS OSC)........................30
Real-Time Clock Oscillator (RTC OSC)........30
USB PLL....................................................... 30
Fixed Frequency PLL (Fixed-freq PLL).........30
Fractional-N PLL (FracN PLL).......................31
specifications—application domain...............70
9
Specifications—real-time domain..........................................79
9.1 Power sequencing—real-time domain.........................79
9.2 Peripheral operating requirements and behaviors—
real-time domain..........................................................80
5.4 Power Management.................................................... 31
9.2.1
9.2.2
9.2.3
9.2.4
QuadSPI AC specifications...........................80
Analog modules............................................ 84
Timer specifications—real-time domain........92
Connectivity and communications
5.4.1
5.4.2
Digital PMC................................................... 31
Analog power management controller
(Analog PMC)................................................31
6
7
i.MX 7ULP LDO Bypass versus LDO-enabled modes..........32
6.1 Real-time domain LDO Enabled mode........................32
6.2 Application domain LDO Enabled mode......................32
6.3 Application domain LDO BYPASS mode.................... 32
System specifications............................................................33
7.1 Ratings........................................................................ 33
specifications—real-time domain.................. 92
10 Package information and contact assignments.....................96
10.1 BGA, 14 x 14 mm, 0.5 mm pitch (VP suffix)................ 96
10.1.1 14 x 14 mm package case outline.................96
10.1.2 14 x 14 mm, 0.5 mm pitch, ball map............. 98
10.1.3 14 x 14 mm power supply and functional
7.1.1
7.1.2
7.1.3
Thermal handling ratings...............................33
Moisture handling ratings..............................33
ESD handling ratings.................................... 33
contact assignments..................................... 100
11 Revision History.................................................................... 108
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i.MX 7ULP modules list
1 i.MX 7ULP modules list
The i.MX 7ULP applications processor contains a variety of digital and analog
modules. The following table describes these modules in alphabetical order.
In the Domain column in this table:
• AD = Application Power Domain (primarily controlled by the Cortex-A7)
• RT = Real-Time Power Domain (primarily controlled by the Cortex-M4)
• VBAT = RTC/VBAT power domain Real-Time Domain
• DGO = “always-on” DGO power domain
• SYS = system-level functions that are implemented separately from the domains
listed above.
Table 1. i.MX 7ULP modules list
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
AMBA Network
Interconnect
Crossbar
NIC0-1
DMA and Bus Fabrics AD
The AMBA Network Interconnect
Crossbar (NIC) is a highly configurable
and high performance AMBA-compliant
network infrastructure which arbitrates
between multiple AXI or AHB masters to
grant access to internal or external
memories or other slave devices. It
supports connectivity between several
slave and master ports for parallel
processing. It uses a hybrid round-robin
arbitration scheme and contains
frequency converters, data width
converters, bus protocol converter, and
AXI channel buffers.
Analog PMC
Analog PMC
Power Management
SYS
The Analog PMC consists of voltage/
current references, core logic supply
regulators, memory supply regulators,
Back and Forward Biasing regulators,
monitors and power switches, etc.
There are two Analog PMC subsystems
in i.MX 7ULP, one associated with the
M4 power domain and the other with the
A7 power domain.
Analog-to-Digital
Converter
ADC0-1
Analog
RT
Analog-to-Digital Converter (ADC) is a
12-bit resolution, successive
approximation analog to digital
converter. The ADC module supports
up to 16 single-ended external analog
inputs. It outputs 12-bit, 10-bit, or 8-bit
digital signal in right-justified unsigned
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
format. The ADC can achieve 1
microsecond conversion rate.
Asynchronous
Wakeup Interrupt
Controller
AWIC
BME
System Control
RT
The Asynchronous Wakeup Interrupt
Controller (AWIC) module is capable of
interrupt detection and wake-up of a
processor when it is in low power mode.
Bit Manipulation
Engine
Multicore peripherals RT
and resource domain
control submodules
The Bit Manipulation Engine (BME)
provides hardware support for atomic
read-modify-write memory operations to
the peripheral address space. This
architectural capability is also known as
"decorated storage" as it defines a
mechanism for providing additional
semantics for load and store operations
to memory-mapped peripherals beyond
just the reading and writing of data
values to the addressed memory
locations.
Comparator
CMP0-1
Analog
Debug
DGO
The (CMP) module provides a circuit for
comparing two analog input voltages.
The comparator circuit is designed to
operate across the full range of the
supply voltage (rail to rail operation).
Cross Trigger Matrix CTM
RT
Cross Trigger Matrix (CTM) is a
component of the Embedded Cross
Trigger (ECT), which is key in the
multicore debug strategy. The CTM
receives signals from various sources
(i.e. cores and peripherals) and
propagates or routes them to the
different debug resources of the SoC.
Those debug resources can include
time stamping capability, real-time
trace, triggers and debug interrupts.
Cryptographic
Acceleration and
Assurance
CAAM
Security
AD
Cryptographic Acceleration and
Assurance Module (CAAM) is a
multifunction accelerator that supports
the cryptographic functions common in
many security protocols. This includes
AES128, AES256, DES, 3DES, SHA1,
SHA224, SHA256, and a random
number generator with a true entropic
seed. CAAM includes a DMA engine
that is descriptor based to reduce
processor-accelerator interaction.
Security feature clear keys and
memories when on-chip security
monitor detects tampering. The Secure
RAM is implemented and provides
secure storage of sensitive information
Table continues on the next page...
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i.MX 7ULP modules list
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
both in on-chip RAM and in off-chip,
nonvolatile memory. For details, see the
i.MX 7ULP Security Reference Manual.
Cyclic Redundancy
Check
CRC
Connectivity and
Communications
RT
The Cyclic Redundancy Check (CRC)
module is a hardware CRC generator
circuit using 16/32-bit shift register. The
CRC module supports error detection
for all single, double, odd, and most
multi-bits errors, programmable initial
seed value, and optional feature to
transpose input data and CRC result via
transpose register.
Debug Access Port
DAP
Debug
RT
Debug Port Access (DAP) provides
debugger access to on-chip system
resources via the SWJ-DP port. The
DAP provides internal system access to
A7 Debug Port, M4 Debug Port, System
Bus, JTAG controller, and SoC Control
and Status. The DAP also enables
system access to CoreSight debug
subsystem through the APBIC port.
Digital PMC
Digital PMC
Power Management
SYS
The Digital PMC module allows user
software to control power modes of the
chip and to optimize power consumption
for the level of functionality needed.
There are two instances of Digital PMC
on this device, one for each main power
domain.
Digital-to-Analog
Converter
DAC0-1
Analog
RT
Digital-to-Analog Converter (DAC) is the
12-bit resolution digital-to-analog
converters with programmable
reference generator output. The output
of the DAC can be placed on an
external pin or set as one of the inputs
to the analog comparator or ADC. The
DAC is capable of achieving 1 ms
conversion rate for high-speed signals
and 2 ms conversion rate for low-speed
signals.
Direct Memory
Access
DMA0-1
DMA and Bus Fabrics AD, RT
Direct Memory Access (DMA) is
capable of performing complex data
transfers with minimal intervention from
a host processor. Each DMA module
supports 32 DMA channels. The
transfer control descriptors for each of
the 32 channels locate in system
memory. DMA0 is in the real-time
domain. DMA1 is in the application
domain.
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
Direct Memory
Access Multiplexer
DMAMUX0-1
DMA and Bus Fabrics AD, RT
The Direct Memory Access Multiplexer
(DMAMUX) module routes DMA
sources, called slots, to any of the
supported DMA channels. DMAMUX0 is
in the real-time domain. DMAMUX1 is in
the application domain.
Embedded Trace
FIFO
ETF
Debug
RT
The Embedded Trace FIFO (ETF)
consists of a formatter, control, and the
trace RAM. It is a configuration of the
Trace Memory Controller (TMC). The
ETF will have a memory size of
16Kbytes. The ETF and associated
memory should be connected in the
system such that it will retain the
information though a warm or cold reset
of the system. This is to allow for debug
information to be retained for debugging
problems that may arise and cause a
reset of the system.
Embedded Trace
Router
ETR
Debug
RT
The ETR is a trace sink that redirects
the trace stream onto the AXI bus to
external storage. It can utilize a single
contiguous region or a scattered
allocation of blocks for a circular buffer.
Reading of the AXI based trace buffer
can either be done directly over AXI
from a normal bus master. The ETR is a
configuration option of the TMC as is
the ETF.
Extended Resource XRDC
Domain Controller
Multicore Peripherals AD, RT
and Resource Domain
Control submodules
The Extended Resource Domain
Controller (XRDC) provides an
integrated, scalable architectural
framework for access control, system
memory protection and peripheral
isolation. It allows software to assign
chip resources (like processor cores,
non-core bus masters, memory regions
and slave peripherals) to processing
domains, to support enforcement of
robust operational environments. The
XRDC implementation is distributed
across multiple submodules instantiated
throughout the device.
External Bus
Interface
FlexBus
Memories and
Memory Controllers
AD
The External Bus Interface (FlexBus)
module provides external memory
expansion and provides connection to
external peripherals with a parallel,
memory-mapped interface. The FlexBus
supports asynchronous and
synchronous interface to external ROM,
NOR flash, SRAM, PSRAM,
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i.MX 7ULP modules list
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
programmable logic devices and other
memory-mapped slave devices.
External Watchdog
Monitor
EWM
Timers
RT
The External Watchdog Monitor (EWM)
module is designed to monitor external
circuits, as well as the software flow.
This provides a back-up mechanism to
the internal WDOG that can reset the
system. The EWM differs from the
internal WDOG in that it does not reset
the system. The EWM, if allowed to
time-out, provides an independent
trigger pin that when asserted resets or
places an external circuit into a safe
mode.
Fast Internal
Reference Clock
FIRC
Clock Sources and
Control
SYS
SYS
The Fast Internal Reference Clock
(FIRC) module is an internal oscillator
that can generate a reference clock in
the range from 48 MHz to 60 MHz. The
FIRC output clock is used as a
reference to the SCG module, and it is
also used as a clock option to most on-
chip modules.
Fixed-frequency PLL Fixed-Freq PLL
(PLL0)
Clock Sources and
Control
The Fixed-frequency PLL is the same
as the USB PLL. In addition to the main
clock output, this PLL also includes 4
Phase Fractional Dividers (PFDs) that
can generate other clock frequencies.
There is one instance of the Fixed-freq
PLL (PLL0) provides clocks for M4 core
and buses and peripherals in the Real-
time domains.
Flexible Input/Output FLEXIO0-1
Connectivity and
Communications
AD, RT
The Flexible Input/Output (FlexIO)
module is capable of supporting a wide
range of protocols including, but not
limited to: UART, I2C, SPI, I2S, camera
interface, display interface, PWM
waveform generation, etc. FlexIO0 is in
the real-time domain. FlexIO1 is in the
application domain.
Fractional-N PLL
Frac-N PLL
(PLL1-3)
Clock Sources and
Control
SYS
The Fractional-N (Frac-N) PLL can
generate an output clock of 528 MHz
from a supported reference clock. In
addition to the main clock output, this
PLL also includes up to 4 Phase
Fractional Dividers (PFDs) that can
generate other clock frequencies. This
PLL also supports tunable clock for
audio applications.
GC320 Composition GPU-2D
Processing Core
Multimedia
AD
Vivante GC320 is a Composition
Processing Core (CPC) GPU. It
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
supports user interface rendering and
performs functions like blending,
filtering, rotation, overlay, resizing,
transparency, and other dynamic
effects.
GC7000 Nano Ultra GPU-3D
Graphic Processing
Unit
Multimedia
AD
i.MX 7ULP integrates the Vivante
GC7000 Nano Ultra Graphic Processing
Unit (GPU-3D). supporting OpenGL
ES2.0/1.1, Desktop OpenGL 2.1,
OpenVG1.1, and GLSL shading
language support.
Hardware
Semaphore
SEMA42_0 and
SEMA42_1
Multicore Peripherals AD, RT
and Resource Domain
Control submodules
The Hardware Semaphore (SEMA42)
module provides the hardware support
needed in multicore systems for
implementing semaphores and provide
a simple mechanism to achieve "lock/
unlock" operations via a single write
access. SEMA42_0 is in the real-time
domain. SEMA42_1 is in the application
domain.
Input/Output
Multiplexing
Controller
IOMUXC0-1 &
IOMUXC_DDR
System Control
AD, RT
The Input/Output Multiplexing Controller
(IOMUXC) enables the chip to share
one pad for multiple signals from
different peripheral interfaces. This pad
sharing mechanism is done by
multiplexing the pad's input and output
signals. The IOMUXC also controls the
pads setting parameters and digital filter
functions of the pad. In addition, the
IOMUXC controls input multiplexing
logic for input signals multiplexed at
multiple locations. IOMUXC0 is in the
real-time domain. IOMUXC1 and
IOMUXC_DDR are in the application
domain.
Internal Reference
Clock 1kHz
IRC1K
Clock Sources and
Control
SYS
RT
The Internal Reference Clock 1kHz
(IRC1K) module is an internal oscillator
that can generate a reference clock of
1kHz. The IRC1K clock is enabled in all
modes of operation, including all low
power modes.
Joint Test Action
Group Controller
JTAGC
Debug
Joint Test Action Group Controller
(JTAGC) provides the means to test
chip functionality and connectivity while
remaining transparent to system logic
when not in test mode. Testing is
performed via a boundary scan
technique, as defined in the IEEE
1149.1-2001 standard.
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i.MX 7ULP modules list
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
LCD Interface
Controller
LCDIF
Multimedia
AD
The LCDIF is a general purpose display
controller used to drive a wide range of
display devices varying in size and
capabilities. The LCDIF is used as a
bridge between the DSI controller and
the NIC0 crossbar.
Low-Leakage Wake- LLWU
Up Unit
System Control
DGO
The Low-Leakage Wake-Up Unit
(LLWU) module allows user to select up
to 32 external pin sources and up to 8
internal modules as a wakeup source
from low leakage power modes.
Low Power Inter-
Integrated Circuit
LPI2C0-7
Connectivity and
Communications
AD, RT
The Low Power Inter-Integrated Circuit
(LPI2C) module implements an efficient
interface to an I2C bus as a master. The
LPI2C can continue operating while the
processor is in stop mode provided an
appropriate peripheral clock is available.
This module is designed for low CPU
overhead with DMA offloading of FIFO
register accesses. LPI2C0 - LPI2C3 are
in the real-time domain. LPI2C4 -
LPI2C7 are in the application domain.
Low Power Periodic LPIT0-1
Interrupt Timer
Timers
AD, RT
AD, RT
RT
Low Power Periodic Interrupt Timer
(LPIT) is a multichannel timer module
that can generate independent pre-
trigger and trigger outputs. These timer
channels can operate individually or can
be chained together. The pre-trigger
and trigger outputs can be used to
trigger other modules on the device.
The LPIT can also operate in low power
modes. LPIT0 is in the real-time
domain. LPIT1 is in the application
domain.
Low Power Serial
LPSPI0-3
Connectivity and
Communications
The Low Power Serial Peripheral
Peripheral Interface
Interface (LPSPI) module implements
an efficient interface to an SPI bus as a
master and/or a slave. The LPSPI can
continue operating while the processor
is in stop mode if an appropriate
peripheral clock is available. This
module is designed for low CPU
overhead with DMA offloading of FIFO
register accesses. LPSPI0 and LPSPI1
are in the real-time domain. LPSPI2 and
LPSPI3 are in the application domain.
Low-power Trusted
Cryptography
LTC
Security
Low-power Trusted Cryptography is an
architecture that allows multiple
cryptographic hardware accelerator
engines to be instantiated and share
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
common registers. This version of LTC
supports 128-bit AES. For details, see
the i.MX 7ULP Security Reference
Manual.
Low Power Universal LPUART0-7
Asynchronous
Receiver/Transmitter
Connectivity and
Communications
AD, RT
The Low Power Universal
Asynchronous Receiver/Transmitter
(LPUART) module provides
asynchronous, serial communication
capability with external devices.
LPUART supports non-return-to-zero
(NRZ) encoding format and IrDA-
compatible infrared (low-speed) SIR
format. The LPUART can continue
operating while the processor is in stop
mode if an appropriate peripheral clock
is available. This module is designed for
low CPU overhead with DMA offloading
of FIFO register accesses. LPUART0 –
LPUART3 are in the real-time domain.
LPUART4 – LPUART7 are in the
application domain.
Low Power Timer
LPTMR0-1
MMCAU
Timers
DGO
The Low Power Timer (LPTMR) module
is a 16-bit timer which operates as real-
time interrupt or pulse accumulator. This
LPTMR module can remain functional
when the chip is in low power modes,
provided the reference clock to this
timer is active.
Memory-Mapped
Cryptographic
Acceleration Unit
Security
RT
Memory-Mapped Cryptographic
Acceleration Unit (MMCAU) is an
optimized security accelerator that
supports the cryptographic functions
common in many security protocols.
This includes DES, 3DES, AES, MD5,
SHA-1, SHA-256 algorithms via simple
C calls to optimized security functions.
Messaging Unit
MU
Multicore Peripherals RT
and Resource Domain
Control submodules
Messaging Unit (MU) is a shared
peripheral with a 32-bit IP bus interface
and interrupt request signals to each
host processor. The MU exposes a set
of registers to each processor which
facilitate inter-processor communication
via 32-bit words, interrupts and flags.
Interrupts may be independently
masked by each processor to allow
polled-mode operation.
MIPI Display Serial
Interface Controller
DSI Controller
Multimedia
AD
The MIPI Display Serial Interface
Controller (DSI Controller) is
responsible for serializing display data
from the GPU. Data can come from
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i.MX 7ULP modules list
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
either the GPU or the processor/DMA
controller.
MIPI Display Serial
Interface Physical
Layer
DSI PHY
Multimedia
AD
The MIPI Display Serial Interface
Physical Layer (DSI PHY) is a two-lane
interface that supports up to 1 Gbps of
data on each lane. DSI PHY includes a
PLL which output clock is dedicated DSI
uses.
Multicore System
Mode Controller
MSMC
System Control
DGO
Multicore System Mode Controller
(MSMC) is responsible for sequencing
the system into and out of all low power
Stop and Run modes. MSMC monitors
events to trigger transitions between
power modes, while controlling the
power, clocks, and memories of the
system to achieve the power
consumption and functionality of that
mode.
Multi Mode DDR
Controller
MMDC
Memories and
Memory Controllers
AD
The Multi Mode DDR Controller
(MMDC) is a configurable DDR
controller that provides interface to
LPDDR2 or LPDDR3 memory. The
MMDC consists of a core and PHY. The
core is responsible for communication
with the system through AXI interface,
DDR commands generation, DDR
command optimizations, and read/ write
data path. The PHY performs timing
adjustment using special calibration
mechanisms to ensure data capture
margin at the supported clock rate.
On-The-Fly AES
Decryption
OTFAD
Security
RT
The On-The-Fly AES Decryption
(OTFAD) module provides an advanced
hardware implementation that
minimizes any incremental cycles of
latency introduced by the decryption in
the overall external memory access
time. The OTFAD engine also includes
complete hardware support for a
standard AES key unwrap mechanism
to decrypt a key BLOB data instruction
containing the parameters needed for
up to 4 unique AES contexts.
Peripheral Clock
Control
PCC0-3
Clock Sources and
Control
AD, RT
The Peripheral Clock Control (PCC)
module is responsible for clock
selection, optional division and clock
gating mode for peripherals in their
respected power domain. PCC0 and
PCC1 are in the real-time domain.
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
PCC2 and PCC3 are in the application
domain.
Reset Mode
Controller
RMC
System Control
System Control
DGO
Reset Mode Controller (RMC)
implements reset modes and reset
functions of the chip.
On-Chip One-Time- OCOTP_CTRL
Programmable
Controller
RT
The On-Chip One-Time-Programmable
Controller (OCOTP_CTRL) module
provides an interface for reading,
programming and/or overriding
identification and control information
stored in on-chip fuse elements. The
module supports electrically-
programmable poly fuses. The
OCOTP_CTRL also provides a set of
volatile software-accessible signals
which can be used for software control
of hardware elements, not requiring
non-volatility.
Peripheral Trigger
Multiplexing
TRGMUX0-1
PCTL_A-F
System Control
System Control
AD, RT
AD, RT
Peripheral Trigger Multiplexing
(TRGMUX) TRGMUX0 is in the real-
time domain. TRGMUX1 is in the
application domain.
Port Control
The Port Control (PCTL) module
provides control for GPIO interrupt
function. GPIO interrupt can be
configured independently for each pin in
the 32-bit port. There is one instance of
the PCTL module for each port.
PCTL_A and PCTL_B are in the real-
time domain. PCTL_C - PCTL_F are in
the application domain.
Quad Serial
Peripheral Interface
QSPI
Memories and
Memory Controllers
RT
The Quad Serial Peripheral Interface
(QSPI) module provides an interface to
various types of serial flash memory.
The QSPI interface allows one serial
flash connection. It supports 1-bit, 4-bit
and 8-bit SPI bus width.
Rapid General-
Purpose Input and
Output
RGPIO2P0-1
System Control
AD, RT
The Rapid General-Purpose Input and
Output with 2 Ports (RGPIO2P) is
similar to the RGPIO module, except it
has an AHB-lite port, in addition to the
IPS port, for faster access. RGPIO2P0
is in the real-time domain. RGPIO2P1 is
in the application domain.
Read-only memory
Controller
ROMCP0/1
Memories and
Memory Controllers
AD, RT
A ROM controller and boot ROM are
present in for both the A7 and M4 CPU
cores. ROMCP0 and a 64 kB ROM are
in the real-time domain. ROMCP1 and a
96 kB ROM are in the application
domain.
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i.MX 7ULP modules list
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
Real Time Clock
Oscillator
RTC OSC
Clock Sources and
Control
VBAT
The Real Time Clock Oscillator (RTC
OSC) module provides the clock source
for the Real-Time Clock module. The
RTC OSC module, in conjunction with
an external crystal, generates a 32.678
kHz reference clock for the RTC.
Single Wire Output
SWO
Debug
Debug
RT
RT
Single Wire Output (SWO) is a trace
data drain that acts as bridge between
the on-chip trace data to a data stream
that is captured by the Trace Port
Analyzer. It is a TPIU-like device that
supports a limited subset of the full
TPIU functionality for a simple debug
solution.
Secure JTAG
Controller
SJC
The Secure JTAG Controller (SJC) is an
authenticated debug module that
implements a challenge/response
mechanism using a standard
cryptographic algorithm. This allows
post production silicon debug without
compromising security requirements.
The SJC is connected in parallel with
the JTAGC module, but it is only used
for authenticated debug.
Secure Non-Volatile SNVS
Storage
Security
VBAT
The Secure Non-Volatile Storage
(SNVS) module is designed to safely
hold security-related data such as
cryptographic key, time counter,
monotonic counter, and general
purpose security information. A part of
the SNVS module belongs to the VBAT
domain that has its own dedicated
power supply which is always on. This
enables SNVS to keep this data valid
and continue to increment the time
counter when the power goes down in
the rest of the SoC. SNVS includes the
Real-Time Clock (RTC) module, which
provides 64-bit monotonic counter with
roll-over protection, 32-bit seconds
counter with roll-over protection and 32-
bit alarm.
Slow Internal
Reference Clock
SIRC
Clock Sources and
Control
SYS
The Slow Internal Reference Clock
(SIRC) module is an internal oscillator
that can generate a reference clock of
16 MHz. The SIRC output clock is used
as a reference to the SCG module, and
it is also used as a clock option to most
on-chip modules.
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
Synchronous Audio
Interface
SAI0-1
Multimedia
RT
The Synchronous Audio Interface (SAI)
module implements full-duplex serial
interfaces with frame synchronization
such as I2S, AC97, and CODEC/DSP
interfaces.
System Clock
Generation
SCG0-1
Clock Sources and
Control
AD, RT
The System Clock Generation (SCG)
module is responsible for clock
generation and distribution across this
device. Functions performed by the
SCG include: clock reference selection,
generation of clock used to derive
processor, system, peripheral bus and
external memory interface clocks;
source selection for peripheral clocks;
and, control of power saving clock
gating mode. SCG0 is in the real-time
domain. SCG1 is in the application
domain.
System Integration
Module
SIM
System Control
AD, RT
SYS
The System Integration Module (SIM)
provides system control and chip
configuration registers. The SIM
includes the TSTMR module.
System Oscillator
SYS OSC
Clock Sources and
Control
The System Oscillator (SYS OSC)
module is a crystal oscillator. The SYS
OSC, in conjunction with an external
crystal or resonator, generates a
reference clock for this device. It also
optionally supports an external input
clock provided to EXTAL signal directly.
Tightly-Coupled
Memory
TCM
Memories and
Memory Controllers
RT
Tightly Coupled Memory (TCM) RAM.
This RAM is tightly integrated to the M4
processor. M4 accesses this memory
with zero wait-state. There is a
backdoor port that allows M4 DMA and
other bus masters in the SoC to access
this memory.
Timer/Pulse Width
Modulation
LPTPM0-7
Timers
AD, RT
The Timer/Pulse Width Modulation
Module (TPM) is a multichannel timer
module that supports input capture,
output compare, and the generation of
PWM signals. The counter, compare
and capture registers are clocked by an
asynchronous clock that can remain
enabled in low power modes. LPTPM0
– LPTPM3 are in the real-time domain.
LPTPM4 – LPTPM7 are in the
application domain.
TimeStamp
Components
TimeStamp
Components
Debug
RT
The timestamp components generate
and distribute a consistent timestamp
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i.MX 7ULP modules list
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
value for multiple processors and other
blocks in a SoC.
Timestamp timer
TSTMR
Timers
AD, RT
The TSTMR module is a free running
incrementing counter that starts running
after system reset de-assertion and can
be read at any time by the software for
determining the software ticks. The
TSTMR is a 64-bit clock cycle counter.
It runs off the 1 MHz clock and resets
on every system reset. The counter only
stops when the clock to the TSTMR is
disabled.
Trace Funnel
FUNL
Debug
Debug
RT
RT
The Trace Funnel (FUNL) is used when
there is more than one trace source.
The Trace Funnel combines multiple
trace streams onto a single ATB bus.
The Trace Funnel includes an arbiter
that determines the priority of the ATB
inputs.
Trace Port Interface TPIU
Unit
Trace Port Interface Unit (TPIU) acts as
a bridge between on-chip trace data, ID
distinguishable, and a TPA. It receives
ATB trace data and sends it off chip via
ARM’s standard trace interface. The
TPIU includes ATB interface, APB
interface, Formatter, Asynchronous
FIFO, Register bank, Trace out
serializer, and a pattern generator.
Trace Replicator
Replicator
Debug
RT
RT
The Trace Replicator (Replicator)
enables two trace sinks (TPIU and
TMC) to be wired together and receive
ATB trace data from the same trace
source. It takes incoming data from a
single source and replicates it to two
master ports.
True Random
Number Generator
TRNG
Security
The True Random Number Generator
(TRNG) module is to generate high
quality, cryptographically secure,
random data. The TRNG module is
capable of generating its own entropy
using an integrated ring oscillator. In
addition, the module’s NIST certifiable
Pseudo-Random Number Generator
(PRNG) provides accelerated
processing of pseudo-random data.
ultra Secured Digital uSDHC0/1
Host Controller
Memories and
Memory Controllers
AD
The ultra Secured Digital Host
Controller (uSDHC) provides the
interface between the host system and
SD, SDIO or eMMC cards. The uSDHC
acts as a bridge, passing host bus
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i.MX 7ULP modules list
Block Name
Table 1. i.MX 7ULP modules list (continued)
Block Mnemonic
Subsystem
Power
Brief description
Domain
transactions to the cards by sending
commands and performing data
accesses to/from the cards or devices.
It handles SD, SDIO and eMMC
protocol at transmission level.
Universal Serial Bus HSIC-PHY
High-Speed Inter
Chip Physical Layer
Connectivity and
Communications
AD
USB High-Speed Inter Chip Physical
Layer (HSIC-PHY) is a complete digital
IP designed to implement USB 2.0
HSIC connectivity interface.
Universal Serial Bus USB-OTG
On-The-Go
Connectivity and
Communications
AD
The Universal System Bus On-The-Go
(USB-OTG) module is a USB 2.0-
compliant implementation. The registers
and data structures of this USB
controller are based on the Enhanced
Host Controller Interface Specification
for Universal Serial Bus (EHCI). This
module can act as a host, a device or
an On-The-Go negotiable host/device
on the USB bus.
Universal Serial Bus USB PLL
Phase Locked Loop
Clock Sources and
Control
AD
USB Phase Locked Loop (USB PLL) is
embedded in the USB transceiver block.
This PLL allows an exact 480 MHz to be
generated from a supported reference
clock of 24 MHz. The output of this PLL
is primarily used for PLL operation. The
USB PLL clock is also made available
as a clock source for other peripherals
in the SoC.
Universal Serial Bus USB-PHY
Physical Layer
Connectivity and
Communications
AD
AD
The Universal System Bus Physical
Layer (USB-PHY) implements USB
physical layer connecting to USB host/
device systems at low-speed, full-
speed, and high-speed. USB-PHY
provides a standard UTMI interface for
connection to the USB-OTG controller.
Video Input Unit
VIU
Multimedia
The Video Input Unit (VIU) provides a
parallel interface for digital video. The
VIU accepts various types of digital
video input on its parallel interface,
decodes it and optionally performs
processes such as down-scaling,
horizontal up-scaling, brightness and
contrast adjustment, pixel format
conversion, deinterlacing and horizontal
mirroring. The resultant video stream is
then stored to system memory for
subsequent post-processing and
display.
Wakeup Unit
WKPU
System Control
AD
Wakeup Unit (WKPU) module is
capable of interrupt detection and wake-
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Clocking
Table 1. i.MX 7ULP modules list (continued)
Block Name
Block Mnemonic
Subsystem
Power
Brief description
Domain
up of the Cortex-A processor when it is
in low power mode.
Watchdog Timer
WDOG0-2
Timers
AD, RT
The Watchdog Timer (WDOG) module
keeps a watch on the system
functioning and resets it in case of its
failure. Reasons for failure include run-
away software code and the stoppage
of the system clock that in a safety
critical system can lead to serious
consequences. In such cases, the
WDOG brings the system into a safe
state of operation. The WDOG monitors
the operation of the system by
expecting periodic communication from
the software, generally known as
servicing or refreshing the WDOG. If
this periodic refreshing does not occur,
the WDOG resets the system. WDOG0
is in the real-time domain. WDOG1 and
WDOG2 are in the application domain.
XRDC Manager
MGR
Multicore Peripherals RT
and Resource Domain
Control submodules
The XRDC Manager (MGR) submodule
coordinates all programming model
reads and writes.
XRDC Master
Domain Assignment
Controller
MDAC
Multicore Peripherals AD, RT
and Resource Domain
Control submodules
The XRDC Master Domain Assignment
Controller (MDAC) submodule handles
resource assignments and generation of
the domain identifiers.
XRDC Memory
Region Controller
MRC
PAC
Multicore Peripherals AD, RT
and Resource Domain
Control submodules
The XRDC Memory Region Controller
(MRC) submodule implements the
access controls for slave memories
based on the pre-programmed region
descriptor registers.
XRDC Peripheral
Access Controller
Multicore Peripherals AD, RT
and Resource Domain
Control submodules
The XRDC Peripheral Access Controller
(PAC) implements the access controls
for slave peripherals based on the pre-
programmed domain access control
registers.
2 Clocking
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Clocking
2.1 Introduction
This section details the clock sources, distribution and management within the i.MX
7ULP. These functions are under joint control of the System Clock Generation (SCG)
modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)
blocks.
NOTE
References in this chapter to “Core 0” or “Processor A”
correspond to the Cortex M4 core. References in this chapter
to “Core 1” or “Processor B” correspond to the Cortex A7
core.
The clocking scheme provides clear separation between M4 domain and A7 domain.
Except for a few clock sources shared between two domains, such as the System
Oscillator clock, the Slow IRC (SIRC), and the Fast IRC clock (FIRC), clock sources
and clock management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
2.2 Clock distribution
The SCG modules generate and distribute clocks on the device. SCG functions include:
• clock reference selection
• generation of clock used to derive processor, system, peripheral bus and external
memory interface clocks
• source selection for peripheral clocks
• control of power-saving clock-gating mode
PCC modules control clock selection, optional division and clock gating mode for
peripherals.
NOTE
• To bypass system oscillator and directly apply clock from
pin, SCG_SOSCCFG[EREFS] should be set to 0. The
direct clock should be applied on the EXTAL pin.
• For using oscillator reference,
SCG_SOSCCSR[SOSCEN] and
SCG_SOSCCFG[EREFS] should both be set to 1.
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Clocking
2.3 External clock sources
In normal functional mode, this device operates off two primary external reference
clocks: System oscillator clock (SOSC) and RTC oscillator clock (ROSC):
• System oscillator clock is a high frequency reference clock with a frequency in
the range of 16 MHz to 32 MHz. This clock is used as a reference clock to the on-
chip PLLs which generate all the required high frequency clocks.
• RTC oscillator clock is the 32.768 kHz constant frequency, real-time clock.
2.4 Oscillators
The system oscillator, in conjunction with an external crystal or resonator, generates a
reference clock for the device. The system oscillator module supports 16-32 MHz
crystals or resonators. It also provides the option for an external input clock to
EXTAL signal directly.
The RTC oscillator is in the VBAT domain. The RTC oscillator module, in
conjunction with an external crystal, generates a 32.768 kHz real-time reference clock
for the RTC and will always be enabled and supplying clock to SRTC. This is the
default clock source.
2.5 Internal clock sources
This device is capable of generating these internal reference clocks:
• The FIRC is the fast IRC clock with nominal frequency in the range from 48 to 60
MHz. In addition, the FIRC provides a clock selection option for peripherals.
• The SIRC is the slow IRC clock with nominal frequency of 16 MHz. The SIRC
provides a clock selection option for peripherals.
• The IRC1K generates 1 kHz clock that is enabled in all modes of operation,
including all low power modes.
• The RTC OSC has the capability to provide nominal 32 kHz (not recommended
for accurate clock and normal operation) IRC in absence of the external OSC
reference clock if the VBAT domain is enabled.
NOTE
The internal oscillator is automatically multiplexed in the
clocking system when the system detects a loss of clock.
The internal oscillator will provide clocks to the same on-
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Application domain (implementing ARM Cortex-A7)
chip modules as the external 32 kHz oscillator. The internal
oscillator is not precise relative to a crystal. While it will
provide a clock to the system, it generally will not be precise
enough for long-term time keeping. The internal oscillator is
anticipated to be useful for quicker start-up times and
tampering prevention, but should not be used as the exclusive
source for the 32 kHz clocks. An external 32 kHz clock
source must be used for production systems.
3 Application domain (implementing ARM Cortex-A7)
The application domain is built around an ARM Cortex-A7 processor optimized to run
nominally at 500 MHz, supported by a 32 KB L1 instruction and data cache, a large L2
cache, and an LPDDR2/LPDDR3 memory interface. The Cortex-A7 processor is a
high-performance low-power processor that implements the ARMv7-A architecture. It
uses the generic interrupt controller (GIC), generic 64-bit OS timer, FPU and the ARM
NEON SIMD engine. Additionally, all the optional debug features are included.
3.1 Memory system—application domain
3.1.1 Internal memory (application domain)
3.1.2 Multi Mode DDR Controller (MMDC)
The Multi Mode DDR Controller is a dedicated interface to LPDDR2/LPDDR3
SDRAM.
The i.MX 7ULP MMDC is compatible with the following JEDEC-compliant memory
types:
• LPDDR2 SDRAM compliant to JESD209-2F LPDDR2 JEDEC standard released
June, 2013
• LPDDR3 SDRAM compliant to JESD209-3C JEDEC standard released August,
2015
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Application domain (implementing ARM Cortex-A7)
MMDC operation with the standards stated above is contingent upon the board DDR
design adherence to the DDR design and layout requirements stated in the Hardware
Development Guide for the i.MX 7ULP Applications Processor (IMX7ULPHDG).
NOTE
For more information on MMDC, please refer to the
following Engineering Bulletin: EB00913 - LPDDR2/
LPDDR3 Parameter Optimizations for i.MX 7ULP.
The table below shows the supported LPDDR2/LPDDR3 configurations:
Table 2. i.MX 7ULP supported LPDDR2/LPDDR3 configurations
Parameter
Clock frequency
Bus width
LPDDR2
LPDDR3
up to 271.5 MHz
x16/x32
Channel
Single
Chip select
Up to two
3.1.3 eMMC
eMMC is a managed NAND device.
See Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC timing—
application domain.
3.2 Peripherals—application domain
3.2.1 Graphics processor human machine interfaces
The i.MX 7ULP Application Domain implements the following graphics processor
human machine interfaces:
• 3D graphics processing unit (GPU-3D)
• 2D graphics processing unit (GPU-2D)
• MIPI Display Serial Interface Controller (MIPI DSI)
• Video Interface Unit (VIU)
See the i.MX 7ULP modules list for more details.
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Application domain (implementing ARM Cortex-A7)
3.2.2 Security—application domain
3.2.2.1 True Random Number Generator (TRNG)
The TRNG module is used to generate high quality, cryptographically secure, random
data. The TRNG module is capable of generating its own entropy using an integrated
ring oscillator. In addition, the module’s Pseudo-Random Number Generator (PRNG)
provides accelerated processing of pseudo-random data.
3.2.2.2 Real-Time Clock (RTC)
The RTC module provides 64-bit monotonic counter with roll-over protection, 32-bit
seconds counter with roll-over protection and 32-bit alarm. This timer module is
extremely low power that allows it to operate on a backup power supply when the main
power supply is cut off. The RTC remains functional in all low power modes and can
generate an interrupt to exit any low power mode.
3.2.2.3 High Assurance Boot (HAB)
The High Assurance Boot (HAB) component of the ROM protects against the potential
threat of attackers modifying areas of code or data in programmable memory to make it
behave in an incorrect manner. The HAB also prevents attempts to gain access to
features which should not be available.
The integration of the HAB feature with the ROM code ensures that the chip does not
enter an operational state if the existing hardware security blocks have detected a
condition that may be a security threat or areas of memory deemed to be important have
been modified. The HAB uses RSA digital signatures to enforce these policies.
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Application domain (implementing ARM Cortex-A7)
CAAM
Flash
RAM
Core Processor
Figure 3. Secure Boot Components
NOTE
NXP provides a reference Code Signing Tool (CST) for key
generation, certificate generation and code signing for use
with the HAB library. The CST can be found by searching
for "IMX_CST_TOOL" at http://www.nxp.com.
NOTE
For further details on making use of the secure boot feature
using HAB, contact your local NXP representative.
3.2.3 Timers—application domain
The i.MX 7ULP Application Domain implements the following timers:
• Low Power Periodic Interrupt Timer (LPIT)
• Timer/PWM Module (LPTPM)
• Low Power Timer (LPTMR)
• External Watchdog Monitor (EWM)
• Time stamp timer module (TSTMR)
• WDOG (Watchdog Timer)
See i.MX 7ULP modules list for more details.
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Real-time domain (implementing ARM Cortex-M4)
3.2.4 Connectivity and communications—applications domain
The i.MX 7ULP Application Domain implements the following connectivity and
communications peripherals:
• Secure Digital (SD) Interface via the uSDHC
• Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
• Low Power Inter-Integrated Circuit (LPI2C)
• Low Power Serial Peripheral Interface (LPSPI)
• Universal System Bus On-The-Go (USB-OTG)
• USB High-Speed Inter-Chip Physical Layer (HSIC-PHY)
See i.MX 7ULP modules list for more details.
4 Real-time domain (implementing ARM Cortex-M4)
The real-time domain is built around an ARM Cortex-M4 processor that contains a
floating-point unit and is optimized for lowest possible leakage.
4.1 Memory system—real-time domain
4.1.1 Internal memory—real-time domain
The real-time domain contains 256 kB of SRAM organized in sub-blocks of 32 kB
each. Each sub-block can be power-gated under software control to optimize power
consumption.
4.1.2 QuadSPI flash
The Quad Serial Peripheral Interface (QSPI) module provides an interface to various
types of serial flash memory. It allows one serial flash connection and supports 1-bit, 4-
bit and 8-bit SPI bus width.
4.2 Peripherals—real-time domain
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System control modules
4.2.1 Analog—real-time domain
The i.MX 7ULP Real-Time Domain implements the following analog peripherals:
• 12-bit Analog to Digital Converter
• 12-bit Digital to Analog Converter
• Comparators
See i.MX 7ULP modules list for more details.
4.2.2 Connectivity and communications—real-time domain
The i.MX 7ULP Real-Time Domain implements the following connectivity and
communications peripherals:
• Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
• Low Power Inter-Integrated Circuit (LPI2C)
• Low Power Serial Peripheral Interface (LPSPI)
• Rapid General-Purpose Input and Output with 2 Ports (RGPIO2P)
• Flexible Input/Output (FlexIO)
See the i.MX 7ULP modules list for more details.
5 System control modules
5.1 JTAG—system control
Joint Test Action Group Controller (JTAGC) provides the means to test chip
functionality and connectivity while remaining transparent to system logic when not
in test mode. Testing is performed via a boundary scan technique, as defined in the
IEEE 1149.1-2001 standard.
5.2 JTAG device identification register
The device identification register (JTAG ID) allows the revision number and part
number to be read through the TAP. See the device identification register section of
the i.MX 7ULP Applications Processor Reference Manual for details. This table
shows the Part Identification Number (PIN) and the Part Revision Number (PRN) for
each i.MX 7ULP silicon revision.
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System control modules
Table 3. JTAG device identification register information
Silicon Revision
Part Identification Number (PIN)
10'b0011100001
Part Revision Number (PRN)
4’b0000
A0
B0
B1
B2
10'b0011100001
4’b0001
4’b0010
4’b0011
10'b0011100001
10'b0011100001
The contents of the JTAD ID register are also mirrored in a SIM register called
JTAG_ID_REG (address 0x410A_308C).
5.3 Oscillators and PLLs
5.3.1 System oscillator (SYS OSC)
The system oscillator (SYS OSC) is a crystal oscillator. The SYS OSC, in conjunction
with an external crystal or resonator, generates a reference clock for this chip. It also
provides the option for an external input clock to EXTAL signal directly.
5.3.2 Real-Time Clock Oscillator (RTC OSC)
The RTC OSC module provides the clock source for the Real-Time Clock module. The
RTC OSC module, in conjunction with an external crystal, generates a 32.678 kHz
reference clock for the RTC.
5.3.3 USB PLL
The USB PLL is embedded in the USB transceiver block. This PLL allows an exact 480
MHz to be generated from a supported reference clock of 24 MHz. The output of this
PLL is primarily used for USB operations. The USB PLL clock is also made available
as a clock source for other peripherals in the SoC.
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5.3.4 Fixed Frequency PLL (Fixed-freq PLL)
In addition to the main clock output, this PLL also includes 4 Phase Fractional
Dividers (PFDs) that can generate other clock frequencies. There is one instance of the
Fixed-freq PLL (PLL0), which provides clocks for the M4 core, buses, and
peripherals in the real-time domain.
5.3.5 Fractional-N PLL (FracN PLL)
The Fractional-N (Frac-N) PLL can generate an output clock 528 MHz from a
supported reference clock. In addition to the main clock output, this PLL also includes
up to four Phase Fractional Dividers (PFDs) that can generate other clock frequencies.
This PLL also supports a tunable clock for audio applications.
5.4 Power Management
The i.MX 7ULP implements multiple options minimizing application power
consumption:
• On-chip power management including regulators, drivers and switches for
flexible power supplies, efficient power consumption and short wake up time
• Multiple power domains and ultra-low power modes allow flexible power saving
• Voltage and frequency scaling in dynamic operating modes
• Software-controlled clock gating for cores and peripherals
• Dynamic Process Monitor (DPM)
5.4.1 Digital PMC
The digital PMC module allows user software to control power modes and of the chip
and to optimize power consumption for the level of functionality needed. There are
two instances of digital PMC on this chip, one for each main power domain.
5.4.2 Analog power management controller (Analog PMC)
The Analog PMC consists of voltage/current references, core logic supply regulators,
memory supply regulators, back and forward biasing regulators, monitors and power
switches, etc. There are two Analog PMC subsystems, one associated with the M4
power domain and the other with the A7 power domain.
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i.MX 7ULP LDO Bypass versus LDO-enabled modes
6 i.MX 7ULP LDO Bypass versus LDO-enabled modes
i.MX 7ULP has internal low-dropout (LDO) regulators to power certain sections of the
core logic. In LDO Enabled mode, the internal LDO is used to regulate the core logic
voltage under software control. In LDO Bypass mode, the internal LDO is disabled and
the core logic supply voltage is provided externally.
The Real-time domain only supports LDO Enabled mode. The Application Domain
supports either mode. The LDO modes require specific board-level connections. LDO
Bypass vs. Enabled mode must be chosen prior to board design because the physical
connection is different.
6.1 Real-time domain LDO Enabled mode
A 1.8 V nominal voltage supply is provided externally to the VDD_PMC18_DIG0
supply. The internal LDO output is routed to VDD_PMC11_DIG0_CAP.
VDD_PMC11_DIG0_CAP must be routed back to VDD_DIG0 at the board-level with
appropriate bypass capacitors to VSS. This connection has a maximum board routing
impedance requirement. See parameter RDIG0 in Table 5.
See the i.MX 7ULP Hardware Development Guide (IMX7ULPHDG) for details on the
required bypass capacitors.
6.2 Application domain LDO Enabled mode
A 1.2 V nominal voltage supply is provided externally to the VDD_PMC12_DIG1
supply. The internal LDO output is routed to VDD_PMC11_DIG1_CAP.
VDD_PMC11_DIG1_CAP must be routed back to VDD_DIG1 at the board-level with
appropriate bypass capacitors to VSS. This connection has a maximum board routing
impedance requirement. See parameter RDIG1 in Table 5.
See the i.MX 7ULP Hardware Development Guide (IMX7ULPHDG) for details on the
required bypass capacitors.
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System specifications
6.3 Application domain LDO BYPASS mode
The desired core logic supply voltage is provided externally to the
VDD_PMC12_DIG1, VDD_PMC11_DIG1_CAPand VDD_DIG1 which are all tied
together.
See the i.MX 7ULP Hardware Development Guide (IMX7ULPHDG) for details on
the required bypass capacitors.
7 System specifications
7.1 Ratings
7.1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
-55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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System specifications
7.1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-1000
-250
Max.
+1000
+250
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
7.1.4 Absolute maximum ratings
CAUTION
Stresses beyond those listed under this table may cause
permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other
conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect
device reliability.
Table 4. Absolute maximum ratings
Parameter Description
SNVS domain LDO supply input
Symbol
VDD_VBAT42
Min
-0.3
Max
4.25
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
M4/A7 PMC and PMC IO supply input
VDD_PMC18
VDD18_IOREF
VDD_PMC18_DIG0
VDD_DIG0
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
1.98
1.98
1.98
1.155
1.65
1.155
1.155
3.96
1.98
3.96
3.96
3.96
3.96
1.98
1.98
1.8V IO supply reference and A7 supply reference input
M4 domain LDO and internal memory LDO supply input
M4 domain core and logic supply input
A7 domain core and logic supply inputs
VDD_PMC12_DIG1
VDD_PMC11_DIG1_CAP1
VDD_DIG1
GPIO Port A supply input
GPIO Port B supply input
GPIO Port C supply input
GPIO Port D supply input
GPIO Port E supply input
GPIO Port F supply input
HSIC supply input
VDD_PTA
VDD_PTB
VDD_PTC
VDD_PTD
VDD_PTE
VDD_PTF
VDD_HSIC
HSIC 1.8V pre-driver supply input
VDD18_HSIC
Table continues on the next page...
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System specifications
Table 4. Absolute maximum ratings (continued)
Parameter Description
Symbol
Min
Max
1.98
Unit
DDR I/O supply input
VDD_DDR
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
V
V
V
V
V
V
V
V
V
V
V
DDR 1.8V pre-driver supply input
MIPI DSI 1.1V supply input
MIPI DSI 1.8V supply input
USB PHY 3.3V supply input
USB PHY 1.8V supply input
USB0 VBUS detection
VDD18_DDR
VDD_DSI11
VDD_DSI18
VDD_USB33
VDD_USB18
USB0_VBUS
VDD_PLL18
VREFH_ANA18
VDD_ANA18
VDD_ANA33
1.98
1.155
1.98
3.6
1.98
5.6
PLL analog supply input
1.98
1.98
1.98
3.96
ADC high reference supply input
ADC analog and IO 1.8V supply input
ADC analog and IO 3.3V supply input
1. When used as an input in LDO Bypass Mode
7.1.5 Recommended operating conditions—system
NOTE
All supply inputs shown represent the voltage at the package
ball.
Table 5. Recommended operating conditions
Symbol
Description
Conditions
Min
Typ
Max Units
SNVS (Always On) Domain Supply Voltage Requirements
VDD_VBAT42
VDD_VBAT18_CAP
SNVS domain LDO supply
input
—
—
2.4
—
3.0
1.8
4.2
V
V
SNVS domain LDO output
—
Real Time Domain (M4 domain) Supply Voltage Requirements (LDO-Enabled Mode only supported)
VDD_PMC181
M4/A7 PMC and PMC IO
supply input
—
1.71 1.8
1.89
V
V
VDD18_IOREF1
1.8V IO supply reference
and A7 supply reference
input
—
1.71 1.8
1.89
VDD_PMC18_DIG02
M4 domain LDO and internal HSRUN mode not
1.14 1.2
1.89
1.89
1.1
V
V
V
memory LDO supply input
supported
HSRUN mode
supported
1.2
1.8
—
VDD_PMC11_DIG0_CAP3, 4 M4 domain LDO supply
output
—
0.65
Real Time Domain (M4 domain) PMC 0 Register Configuration Requirements
Table continues on the next page...
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System specifications
Table 5. Recommended operating conditions (continued)
Symbol
PMC0_HSRUN
[COREREGVL]
Description
Conditions
HSRUN mode
Min
Typ
Max Units
PMC0 HSRUN mode LDO
configuration requirements
—
101010b
(1.05 V)
—
—
FBB= 0.3 V5
PMC0_RUN [COREREGVL] PMC0 RUN mode LDO
configuration requirements
RUN mode No bias
—
—
011100b
(0.90 V)
—
—
—
—
PMC0_VLPR
PMC0 VLPR mode LDO
configuration requirements
VLPR mode
011100b
(0.90 V)
[COREREGVL]
RBB=+/-1.0 V
(optional)6
PMC0_STOP
[COREREGVL]
PMC0 STOP mode LDO
configuration requirements
STOP mode
—
—
011100b
(0.90 V)
—
—
—
—
PMC0_VLPS
[COREREGVL]
PMC0 VLPS mode LDO
configuration requirements
VLPS mode
011100b
(0.90 V)
RBB=+/-1.0 V
(optional)6
PMC0_LLS [COREREGVL] PMC0 LLS mode LDO
configuration requirements
LLS mode
—
—
001101b
(0.73V)
—
—
RBB=+/-1.0 V
(optional)6
RDIG0
External board routing
impedance from
—
—
50
mΩ
VDD_PMC11_DIG0_CAP to
VDD_DIG0
Application Domain (A7 domain) supply voltage requirements for LDO Bypass mode7
VDD_PMC12_DIG1
VDD_PMC11_DIG1_CAP
VDD_DIG1
A7 domain core and logic
supply inputs
HSRUN mode;
1.09
—
1.15
V
FBB = 0.3V, 9, 10
MIPI DSI 1.1V supply input
RUN mode; No Bias 1.00
—
—
—
—
1.15
1.15
1.15
1.15
V
V
V
V
VDD_DSI118.
VLPR mode
WAIT mode
0.87
1.00
1.00
STOP mode (CA7
halted and
peripherals running
at full rated speed)
STOP mode (CA7
halted and
0.87
—
1.15
V
peripherals running
at VLPR speeds)
VLPS mode11
0.73
0.73
0.73
—
—
—
1.15
1.15
1.15
V
V
V
LLS Mode
VLLS Mode12
Application Domain (A7 domain) PMC1 register configuration requirements for LDO Enabled mode13
VDD_PMC12_DIG1
A7 domain LDO and internal
memory LDO supply input
—
1.14 1.2
1.32
V
V
VDD_PMC11_DIG1_CAP14 A7 domain LDO supply
output
—
0.65
—
1.15
Table continues on the next page...
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System specifications
Table 5. Recommended operating conditions (continued)
Symbol
Description
Conditions
Min
Typ
Max Units
PMC1_RUN[LDOVL]
PMC1 RUN mode LDO
configuration requirements
RUN mode; No Bias
—
100011b
(0.95V)
—
V
V
V
PMC1_VLPR[LDOVL]
PMC1_STOP[LDOVL]
PMC1 VLPR mode LDO
configuration requirements
VLPR mode
—
—
011110b
(0.90V)
—
—
PMC1 STOP mode LDO
configuration requirements
STOP mode (CA7
halted and
100011b
(0.95V)
peripherals running
at full rated speed)
PMC1_STOP[LDOVL]
PMC1 STOP mode LDO
configuration requirements
STOP mode (CA7
halted and
—
011110b
(0.90V)
—
V
peripherals running
at VLPR speeds)
PMC1_VLPS[LDOVL]
PMC1_LLS[LDOVL]
RDIG1
PMC1 VLPS mode LDO
configuration requirements
VLPS mode
LLS Mode
—
—
—
—
011110b
(0.90V)
—
—
50
V
PMC1 LLS mode LDO
configuration requirements
001011b
(0.71V)
V
External board routing
impedance from
—
mΩ
VDD_PMC11_DIG1_CAP to
VDD_DIG1
GPIO Supplies15
VDD_PTA16, 17
VDD_PTB1
VDD_PTC
GPIO Port A supply input
GPIO Port B supply input
GPIO Port C supply input
GPIO Port D supply input
GPIO Port E supply input
GPIO Port F supply input
—
—
—
—
—
—
1.71 1.8 or 3.3
1.71 1.8
3.6
1.89
3.6
3.6
3.6
3.6
V
V
V
V
V
V
1.71 1.8 or 3.3
1.71 1.8 or 3.3
1.71 1.8 or 3.3
1.71 1.8 or 3.3
VDD_PTD
VDD_PTE
VDD_PTF18
Peripheral/Interface Supplies
VDD_HSIC
HSIC 1.2V supply input
—
—
1.14 1.2
1.71 1.8
1.32
1.89
V
V
VDD18_HSIC
HSIC 1.8V pre-driver supply
input
VDD_DDR19
VDD18_DDR
DDR I/O supply input
—
—
1.14 1.2
1.71 1.8
1.26
1.89
V
V
DDR 1.8V pre-driver supply
input
VDD_DSI118
VDD_DSI18
VDD_USB33
VDD_USB18
USB0_VBUS
MIPI DSI 1.1V supply input
MIPI DSI 1.8V supply input
USB PHY 3.3V supply input
USB PHY 1.8V supply input
USB0 VBUS detection
—
—
—
—
—
0.8
1.71 1.8
3.0 3.3
1.1
1.155 V
1.89
3.6
V
V
V
V
1.71 1.8
1.89
5.5
4.020 5.0
or
3.0, 21
Analog Supplies
VDD_PLL18
PLL analog supply input
—
1.71 1.8
1.89
V
Table continues on the next page...
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Table 5. Recommended operating conditions (continued)
Symbol
VREFH_ANA18
Description
Conditions
Min
Typ
Max Units
ADC high reference supply
input
—
—
—
—
1.71 1.8
1.89
V
V
V
V
VREFL_ANA
VDD_ANA18
VDD_ANA33
ADC low reference supply
input
0
0
0
ADC analog and IO 1.8V
supply input
1.71 1.8
1.71 1.8 or 3.3
1.89
3.6
ADC analog and IO 3.3V
supply input
1. VDD_PMC18, VDD18_IOREF and VDD_PTB are connected internally and, as such, must be driven from the same
source.
2. If VDD_PMC18_DIG0 is operated at 1.8 V, it should be tied to VDD_PMC18 at the board level.
3. Note that the M4 LDO is always enabled, and the VDD_PMC11_DIG0_CAP is internally regulated. There is no LDO
bypass option. VDD_PMC0_DIG0_CAP is connected to VDD_DIG0 at the board-level. The voltage observed at
VDD_PMC18_DIG0_CAP differs from the from the programmed voltage on the internal LDO because the sense point
for the LDO is on-chip.
4. The table rows under the heading "Real Time Domain (M4 domain) PMC 0 Register Configuration Requirements" define
the required voltage operating points for each operation mode. The register configurations shown must be used.
5. FBB=+/- 0.3 V is the only supported FBB voltage level on the i.MX 7ULP. CM4 FBB voltage levels are configured in the
PMC 0 Biasing Control register (BCTRL) fields FBBPLEVEL and FBBNLEVEL
6. RBB=+/-1.0 V is the only supported RBB voltage level on the i.MX 7ULP. CM4 RBB voltage levels are configured in the
PMC 0 Biasing Control register (BCTRL) fields RBBPLEVEL and RBBNLEVEL.
7. Note that the A7 LDO can be operated in LDO-enabled mode or LDO-bypass mode. In LDO-bypass mode, the internal
LDO is disabled and the voltage supply for the internal logic in the A7 domain is provided externally to
VDD_PMC12_DIG1, VDD_PMC11_DIG1_CAP, and VDD_DIG1.
8. If the MIPI DSI is used, VDD_DSI11 must be connected to VDD_DIG1 at board level. If MIPI DSI is not used,
VDD_DSI11 can be connected to ground through a 10 KΩ resistor.
9. CA7 domain HSRUN is limited to 8760 power-on hours over the lifetime of the product. The total power-on hours
includes all CA7 power modes except VLLS mode and VBAT mode in which the CA7 domain is internally power-gated.
10. FBB=+/- 0.3 V is the only supported FBB voltage level on the i.MX 7ULP. CA7 FBB voltage levels are configured in the
PMC 1 Biasing Control register (BCTRL) fields FBBPLEVEL and FBBNLEVEL.
11. To minimize power consumption in VLPS mode, configure PMC1 register bit SRAMCTRL[SRAM_STDY] to
RETENTION mode.
12. In VLLS mode, VDD_DIG1 is internally power gated to the application domain logic. VDD_DIG1 must remain powered if
the following supplies are powered: VDD_USB18, VDD_USB33, VDD_DSI18 and VDD_DSI11. If the USB and DSI
supplies are not used/powered, VDD_DIG1 can be turned off at the board level.
13. Note that the A7 LDO can be operated in LDO-enabled mode or LDO-bypass mode. In LDO-enabled mode, the voltage
supply to the internal logic in the A7 domain is regulated by the internal LDO.
14. When using LDO-enabled mode, the voltage at the associated *_CAP ball differs from the programmed voltage
because the sense point for the LDO is on-chip.
15. To achieve minimum power consumption, VDD_PTA, VDD_PTB, VDD_PTC, VDD_PTE, and VDD_PTF must remain
powered in all modes except BAT mode.
16. VDD_PTA must be powered during a power-on reset (POR) for the SMC0 Mode register (MR) BOOTCFG field to
properly latch the boot configuration from the PTA signals (GPIO Boot mode).
17. VDD_ANA33 must be shorted to VDD_PTA at the board level.
18. VDD_PTF must be powered during a power-on reset (POR) for the SMC1 Mode register (MR) BOOTCFG field to
properly latch the boot configuration from the PTF signals (GPIO Boot mode). VDD_PTF must also remain powered
during all A7 power modes except for BAT mode.
19. VDD_DDR must remain powered while VDD18_DDR is powered.
20. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:
• A programmable internal VBUS_VALID comparator (the default option), or
• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V
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System specifications
USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID comparator is
used, USBPHY_USB1_VBUS_DETECTn[VBUSVALID_THRESH] determines the threshold voltage for a valid VBUS.
The programmable range is 4.0V to 4.4V (default).
21. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:
• A programmable internal VBUS_VALID comparator (the default option), or
• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V.
USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID_3V detector
is used, the detector voltage is not programmable.
7.1.6 Estimated maximum supply currents
This table represents the estimated maximum current on the power supply rails and
should be used for power supply selection. The data below is based on design
simulation as well as measured data. Note that some of the data in the table is based
on internal companion regulator limits and not actual use cases. Maximum currents
are higher by far than the average power consumption of typical use cases.
Table 6. Estimated maximum supply currents
Power rail
Conditions
Maximum currents
Unit
µA
mA
VDD_VBAT42
VDD_PLL18
4.2 V
1.8 V
1.8 V
23
8
VDD18_IOREF + VDD_PMC18 +
VDD_PTB1
Use Maximum IO equation 2 + 10 mA
VDD18_DDR + VDD18_HSIC
VDD_ANA18 + VREFH_ANA18
VDD_DSI18
1.8 V
1.8 V
1.8 V
1.8 V
15
16
0.6
27
mA
µA
mA
mA
VDD_USB18
High speed mode
1.8 V, CM4 200 MHz
1.15 V
VDD_PMC18_DIG0
60
mA
mA
VDD_PMC12_DIG1 + VDD_DIG1 +
VDD_DSI11
350
CA7 LDO Bypass Mode
CA7 500 MHz
1.15 V
504
350
504
mA
mA
mA
CA7 LDO Bypass Mode
CA7 720 MHz
1.2 V
VDD_PMC12_DIG1
CA7 LDO Enabled Mode
CA7 500 MHz
1.2 V
CA7 LDO Enabled Mode
CA7 720 MHz
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NXP Semiconductors
System specifications
Table 6. Estimated maximum supply currents (continued)
Power rail
Conditions
1.8 V or 3.3 V
Maximum currents
Use Maximum IO equation2
Use Maximum IO equation2
Use Maximum IO equation2
Use Maximum IO equation2
Use Maximum IO equation2
Use Maximum IO equation2
Use Maximum IO equation2
3
Unit
mA
VDD_PTA
VDD_PTC
VDD_PTD
VDD_PTE
VDD_PTF
VDD_DDR
VDD_HSIC
VDD_ANA33
VDD_USB33
1.8 V or 3.3 V
1.8 V or 3.3 V
1.8 V or 3.3 V
1.8 V or 3.3 V
1.2 V
mA
mA
mA
mA
mA
mA
µA
1.2 V
3.3 V
3.3 V
28
mA
Full speed mode
1. VDD_PMC18, VDD18_IOREF and VDD_PTB are connected internally and, as such, must be driven from the same
source.
2. General equation for estimated, maximum power consumption of an I/O power supply: Imax = N × C × V × (0.5 × F)
Where:
N = Number of I/O pins supplied by the power line
C = Equivalent external capacitive load
V = I/O voltage
(0.5 x F) = Data change rate
In this equation, Imax is in amps, C in farads, V in volts, and F in hertz.
NOTE
For additional power information, see the application
note, AN12573: i.MX 7ULP Power Consumption
Measurement.
7.2 System clocks
7.2.1 Clock modules
7.2.1.1 Fast IRC (FIRC) specifications
Table 7. FIRC specifications with 48 MHz internal reference frequency
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
firc48m
Internal reference frequency
—
48
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency
-1.5
—
1.5
%firc48m
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System specifications
Table 7. FIRC specifications with 48 MHz internal reference frequency (continued)
Symbol
Jcyc_irc48m Period Jitter (RMS)
tirc48mst Startup time
Description
Min.
Typ.
Max.
Unit
Notes
—
—
35
2
150
3
ps
μs
1
1. FIRC startup time is defined as the time between clock enablement and clock availability for system use.
Table 8. FIRC specifications with 60 MHz internal reference frequency
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
firc60m
Internal reference frequency
—
60
—
MHz
Δfirc60m_ol_lv Open loop total deviation of IRC60M frequency
-1.5
—
—
35
2
1.5
150
3
%firc60m
ps
Jcyc_irc60m Period Jitter (RMS)
tirc60mst
Startup time
—
μs
1
1. FIRC startup time is defined as the time between clock enablement and clock availability for system use.
7.2.1.2 Slow IRC (SIRC) specifications
Table 9. Slow IRC (SIRC) specifications
Symbol
Description
Min
15.52
-3.8%
Typ
Max
16.48
3.8%
Unit
firc16m
Internal reference frequency
16
MHz
Δfirc16m_ol_lv Open loop total deviation of IRC16M frequency at low
%firc16m_ol_lv
voltage (VDD=1.71V-1.89V) over temperature
7.2.1.3 Oscillator electrical specifications
7.2.1.3.1 Oscillator DC electrical specifications
Table 10. Oscillator DC electrical specifications
Symbol Description
Min.
—
Typ.
—
Max.
—
Unit
Notes
Cx
Cy
RF
EXTAL load capacitance
1
1
XTAL load capacitance
—
—
—
Feedback resistor — low-power mode
(HGO=0)
—
—
—
MΩ
MΩ
Ω
1, 2
Feedback resistor — high-gain mode
(HGO=1)
—
—
1
0
—
—
RS
Series resistor — low-power mode (HGO=0)
Series resistor — high-gain mode (HGO=1)
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System specifications
Table 10. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
3
Vpp
Peak-to-peak amplitude of oscillation
—
0.8
—
V
(oscillator mode) — high-frequency, low-
power mode (HGO=0)
Peak-to-peak amplitude of oscillation
(oscillator mode) — high-frequency, high-
gain mode (HGO=1)
0.75 x
0.8 x
—
V
VDD_PMC18 VDD_PMC18
1. See crystal or resonator manufacturer's recommendation
2. When low power mode is selected, RF is integrated and must not be attached externally.
3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
7.2.1.3.2 System oscillator frequency specifications
Table 11. System oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (SCG_C2[RANGE]=00)
tdc_extal Input clock duty cycle (external clock mode)
Min.
Typ.
Max.
Unit
Notes
4
—
32
MHz
40
50
60
%
7.2.1.4 32 kHz oscillator electrical specifications
7.2.1.4.1 32 kHz oscillator DC electrical specifications
Table 12. 32kHz oscillator DC electrical specifications
Symbol
RF
Description
Min.
—
Typ.
100
1.5
Max.
—
Unit
MΩ
pF
Internal feedback resistor
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
2.0
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
7.2.1.4.2 32 kHz oscillator frequency specifications
Table 13. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
500
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
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System specifications
Table 13. 32 kHz oscillator frequency specifications (continued)
Symbol Description
Externally provided input clock
Min.
Typ.
Max.
Unit
Notes
vec_extal32
700
—
VDD_VBAT18_CAP
mV
2, 3
amplitude
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VDD_VBAT18_CAP.
7.2.2 Core, platform, and system bus clock frequency limitations
The clock ratio restrictions among the core, platform and IP bus clocks are listed as
follows:
• A7 core clock frequency is higher than A7 platform clock frequency.
• Clock ratio must be integers between A7 fast platform (NIC0) and A7 slow
platform (NIC1).
NOTE
Use A7 SPLL for core clock and A7 APLL for
DDR/NIC clocks.
• Clock ratio must be integers between A7 slow platform and A7 system IP bus.
• Clock ratio must be integers between M4 core/platform and M4 system IP bus.
• M4 slow clock must be slower and an integer division of M4 system IP bus.
• A7 Slow platform (NIC1) clock frequency should be higher than A7 System IP
bus clock (NIC1_BUS clock).
The following tables show examples of various allowable clock frequencies for the
cores, platforms, system bus, and DDR in different operating modes.
NOTE
The frequencies stated in these tables are typical
configuration and maximum frequencies in a particular
mode. However, since there are multiple clock dividers,
different clock ratios can be achieved.
Table 14. Maximum A7 system clock frequencies1
Configuration A7 Core
(MHz)
NIC0 (MHz)2
GPU-3D/
GPU-2D (MHz)
DDR (MHz)2 NIC1 (MHz) A7 System IP
Bus (MHz)
eMMC
RUN
500
380.16
400
271.5
190
95
HS200
mode
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System specifications
Table 14. Maximum A7 system clock frequencies1 (continued)
Configuration A7 Core
(MHz)
NIC0 (MHz)2
GPU-3D/
GPU-2D (MHz)
DDR (MHz)2 NIC1 (MHz) A7 System IP
Bus (MHz)
eMMC
HS400
HSRUN
650
400
48
400 (GPU-2D)/ 271.5
650 (GPU-3D)
200
100
mode
VLPR
48
Not operational Not
48
24
Only 24
MHz
operational
(DDR in self-
refresh
compliant
cards
mode)
1. The maximum operating frequency of a given clock must also observe the clock ratio restrictions described in this
section
2. NIC0 and DDR are derived from the same clock.
NOTE
DGO peripherals on the M4 core use the cm4.divslow_clk,
configured by SCG_xCCR[DIVSLOW] in all the modes, with
the maximum frequency of 25 MHz.
.
Table 15. Maximum M4 system clock frequencies1
Configuration
M4 Core/ Platform
(MHz)
Platform (MHz)
M4 System IP Bus
(MHz)
Slow clock (MHz)
RUN
HSRUN
VLPR
120
200
48
120
200
48
60
100
24
20
25
24
1. The maximum operating frequency of a given clock must also observe the clock ratio restrictions described in this
section
7.2.3 Peripheral clock frequencies
The following table lists peripheral clock frequencies and the indication of platform and
IP bus clocks. Some peripherals have a local clock generator that can further divide the
clock, as required, for the desired serial rate.
Table 16. Peripheral clock frequencies
Module
A7 Fast
Platform
Clk
A7 Slow
Platform
Clk
A7 System M4 Platform M4 System
Peripheral
Clock (MHz)
Notes
IP Bus Clk
Clk
IP Bus Clk
AIPS-Lite
--
--
--
Yes
Yes
--
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System specifications
Table 16. Peripheral clock frequencies (continued)
Module
A7 Fast
Platform
Clk
A7 Slow
Platform
Clk
A7 System M4 Platform M4 System
Peripheral
Clock (MHz)
Notes
IP Bus Clk
Clk
IP Bus Clk
AHB-PBridge
AXBS
--
--
Yes
--
Yes
--
--
Yes
--
--
Yes
--
--
--
NIC0
Yes
--
--
--
NIC1
Yes
--
--
--
--
--
AXI RAMC0
AXI RAMC1
AHB RAMC
A7 ROMC
M4 ROMC
MMDC
Yes
--
--
--
--
--
Yes
--
--
--
--
--
--
--
Yes
--
--
--
--
--
Yes
--
Yes
--
--
--
Yes
--
Yes
--
--
Yes
--
Yes
400
200
FlexBus
QSPI
--
--
Yes
--
Yes
--
--
--
66.71
200, 100
320, 160, 80
108
Yes
Yes
DTR w/ DQS
DTR w/o
DQS
STR
DMA1
--
--
Yes
--
Yes
--
--
Yes
--
--
Yes
--
--
--
DMA0
GPU-3D
Yes
Yes
--
800, 400
400, 200
800, 400
GPU-2D
--
Yes
--
--
--
400, 200
LPUART0-3
LPUART4-7
LPSPI0-1
LPSPI2-3
LPI2C0-3
LPI2C4-7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
--
60
60
Yes
--
--
Yes
--
60
--
Yes
--
100
60
--
Yes
--
--
Yes
Yes
60
USB
Yes
--
60
Exact
Controllers
USB PHY
USB HSIC
uSDHC
--
--
--
--
--
Yes
Yes
Yes
--
--
--
--
--
--
480
480
50
Exact
Exact
Yes
Support
internal clock
divider
52
104
200
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System specifications
Table 16. Peripheral clock frequencies (continued)
Module
A7 Fast
Platform
Clk
A7 Slow
Platform
Clk
A7 System M4 Platform M4 System
Peripheral
Clock (MHz)
Notes
IP Bus Clk
Clk
IP Bus Clk
RGPIO2P0
RGPIO2P1
FlexIO0
FlexIO1
LPIT0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
--
--
--
--
Yes
--
80
--
Yes
--
80
--
Yes
--
60
LPIT1
--
Yes
--
60
TPM0-3
TPM4-7
LPTMR
EWM
--
Yes
--
60
--
Yes
--
60
--
Yes
Yes
--
30
--
--
--
DSI
Yes
Yes
Yes
--
Yes
Yes
Yes
--
500
LCDIF
VIU
--
--
66.7 2
--
SAI0-1
CAAM3
SNVS
Yes
--
50
--
Yes
--
Yes
--
Yes
32.678 (kHz)
Exact for
real-time
clock
CRC
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
--
--
--
--
--
--
--
--
--
--
--
TRNG
LTC3
--
JTAG
XRDC
SEM42
MU
--
--
--
Yes
--
WDOG0
WDOG1
Yes
Yes
WDOG2
(Secure
WDOG)
--
ADC0-1
DAC
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
Yes
Yes
--
25
--
CMP0-1
TPIU/SWO
--
100
1. Flexbus clock frequency is generated using SCG1_NICCCR[NIC1_DIVEXT] and SCG1_NICCSR[NIC1_DIVEXT] fields
through the CLKOUT pin
2. This is the value of pix_clk and not the ipg_clk
3. See i.MX 7ULP Security Reference Manual for complete chapter
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System specifications
7.2.4 PLL PFD output
All PLLs on i.MX 7ULP either have VCO base frequency of 480 MHz or 528 MHz.
The following tables show all the possible combination of PFD output supported for
24 MHz input clock.
PFD Output = 18/N x FVCO where N = 12 to 35.
Table 17. PLL PFD output frequencies 1
PLL VCO (MHz)
480
FRAC (N)
12
PFD Output (MHz)
720
480
13
664
480
14
617.142
576
480
15
480
16
540
480
17
508.235
480
480
18
480
19
454.736
432
480
20
480
21
411.428
392.727
375.652
254.117
345.6
480
22
480
23
480
24
480
25
480
26
332.307
320
480
27
480
28
308.571
297.931
288
480
29
480
30
480
31
278.709
270
480
32
480
33
261.818
254.117
246.857
480
34
480
35
1. This table indicates the maximum frequency achievable by different PFD configurations; typical frequencies will limit
the PFD Frac values to be programmed
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
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System specifications
PLL VCO (MHz)
FRAC (N)
PFD Output (MHz)
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
528
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
792
731.07
678.8
633.6
594
559.0588235
528
500.2105263
475.2
452.5714286
432
413.217
396
380.16
365.538
352
339.428
327.724
316.8
306.580
297
288
279.529
271.5
7.2.5 Audio tunable clock
For audio applications where the data stream is coming from a remote source, the
device has to locally tune a clock signal to match the remote system clock. The
Auxiliary PLL, which provides the clock for master audio, has synchronization logic to
support on-the-fly configuration changes. This allows the device to generate a tunable
clock for audio stream. The clock from one of the Auxiliary PLLs (PLL1) can be
divided by the post-dividers in analog and also the dividers in SCG module. The
divided tunable clock generated should meet the following requirement:
• Output center frequency of 12.288 MHz or 11.2896 MHz
• Tunable range of 1000 ppm
• Tunable resolution of 1 ppm
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System specifications
• Settling time of < 100 μsec
• RMS TIE jitter (long-term jitter) < 100 psec
• Frequency update must be smooth with no glitches
7.3 Power sequencing—system
7.3.1 Power-on sequencing
The power-on sequencing requirements for the device are described in this section.
VDD_VBAT42 must be powered and stable before all other supplies begin to ramp
up.
The real-time domain supplies must be powered and stable before RESET0_B is
deasserted. The real-time domain supplies listed below may be powered on in any
order except for those indicating specific sequencing requirements.
• VDD_PMC18_DIG0 and VDD_PMC18 must be powered on together, or
VDD_PMC18 must be powered on first followed by VDD_PMC18_DIG0
• VDD_PLL_18
• VDD_PTA
• VDD_PTB
• VDD18_IOREF
• VREFH_ANA18
• VREFL_ANA
• VDD_ANA18
• VDD_ANA33
The application domain supplies must be powered on and stable before the A7 core
exits reset. The M4 core controls the release of the A7 from reset. The application
domain supplies listed below may be powered on in any order except for those
indicating specific sequencing requirements.
• VDD_PMC12_DIG1
• VDD_PMC11_DIG1_CAP (if using A7 LDO bypass mode)
• VDD_DIG1 (if using A7 LDO bypass mode)
• VDD_PTC
• VDD_PTD and VDD18_IOREF must be powered together, or VDD18_IOREF
powered on first followed by VDD_PTD
• VDD_PTE
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System specifications
• VDD_PTF
• VDD18_DDR
• DDR_VREF0, DDR_VREF1
• VDD_HSIC
• VDD18_HSIC
• VDD_DSI11
• VDD_DSI18
• VDD_USB33
• VDD_USB18
• VDD_DDR must be powered and stable before the A7 core exits reset.
The application domain supplies must not be powered when the real-time supplies are
off.
In A7 LDO bypass mode, VDD_USB18 and VDD_DSI18 should not be powered when
VDD_DIG1 is not powered, or additional leakage current will occur.
See Table 18 for interfaces and power supplies that are not used.
7.3.2 Power-off sequencing
The i.MX 7ULP has no power-off sequencing requirements.
7.4 Requirements for unused interfaces
This table shows the required connections for unused interfaces.
Table 18. Required connections for unused interfaces
Module
Supply Name
VREFH_ANA18
VREFL_ANA
Description
Recommendations if module is unused
10 kΩ resistor to ground
ADC
High Reference supply for ADC
Low Reference supply for ADC
10 kΩ resistor to ground
VDD_ANA18
1.8 V supply for ADC Analog and 10 kΩ resistor to ground
IO segment
VDD_ANA33
3.3 V supply for ADC Analog and 10 kΩ resistor to ground
IO segment
DAC
DAC0_OUT
DAC1_OUT
VDD_DSI11
VDD_DSI18
DAC0 output
Leave unconnected
DAC1 output
Leave unconnected
MIPI DSI
MIPI 1.1 V supply
MIPI 1.8 V supply
10 kΩ resistor to ground
10 kΩ resistor to ground
Table continues on the next page...
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System specifications
Table 18. Required connections for unused interfaces (continued)
Module
Supply Name
DSI_CLK_N
Description
MIPI Negative Clock Signal
MIPI Positive Clock Signal
MIPI Negative Data0 Signal
MIPI Positive Data0 Signal
MIPI Negative Data1 Signal
MIPI Positive Data1 Signal
Port D supply
Recommendations if module is unused
Leave unconnected
DSI_CLK_P
DSI_DATA0_N
DSI_DATA0_P
DSI_DATA1_N
DSI_DATA1_P
VDD_PTD
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Port D Signals
USB0
10 kΩ resistor to ground
10 kΩ resistor to ground
10 kΩ resistor to ground
VDD_USB33
VDD_USB18
USB0_DM
USB0 PHY 3.3 V supply
USB0 PHY 1.8 V supply
USB D- Analog Data Signal on the Leave unconnected
USB Bus
USB0_DP
USB D+ Analog Data Signal on
the USB Bus
Leave unconnected
USB0_VBUS_DETECT USB0 VBUS Detect
10 kΩ resistor to ground
7.5 Electrical Characteristics and Thermal Specifications
7.5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 4. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume all output
signals:
• have CL=30pF loads,
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• are slew rate disabled, and
• are normal drive strength
7.5.2 Nonswitching electrical characteristics
7.5.2.1 GPIO DC Electrical Requirements
Table 19. GPIO DC Electrical Requirements
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vtol
Fail-safe I/O tolerance VDD_PTx=0
when pad supply is off
(PTA, PTB, PTC, PTE
and PTF)
3.6
V
Itol
I/O current when pad VDD_PTx=0 or floating
supply is off
1
µA
Vih
Input High
VDD_PTx= 1.72 - 1.95 V
VDD_PTx = 2.7 - 3.6 V
VDD_PTx = 1.72 - 1.95 V
VDD_PTx = 2.7 - 3.6 V
VDD_PTx = 1.72 - 1.95 V
VDD_PTx = 2.7 - 3.6 V
VDD_PTx = 1.72 - 1.95 V
VDD_PTx = 2.7 - 3.6 V
VDD_PTx = 1.72 - 1.95 V
Vin = VSS
0.7*VDD_PTx
V
V
0.7*VDD_PTx
Vil
Input Low
-0.3
-0.3
0.15
0.15
-1
0.3*VDD_PTx
0.7
V
V
DeltaV
Input Hysterisis
V
V
Iih
High level input
current
0.5
0.5
1
1
1
µA
µA
µA
-1
Iil
Low level input
current
-1
VDD_PTx = 2.7 - 3.6 V
Vin = VSS
-1
1
µA
V
Voh (Low Drive) High Level Output
Voltage
VDD_PTx = 1.72 - 1.95 V
Ioh = -2.9mA
0.8*VDD_PTx
0.8*VDD_PTx
0.8*VDD_PTx
0.8*VDD_PTx
VDD_PTx = 2.7 - 3.6 V
Ioh = -4mA
V
Voh (High Drive) High Level Output
Voltage
VDD_PTx = 1.72 - 1.95 V
Ioh = -5.8mA
V
VDD_PTx = 2.7 - 3.6 V
Ioh = -8mA
V
Vol (Low Drive)
Low Level Output
Voltage
VDD_PTx = 1.72 - 1.95 V
Ioh = 2.9mA
0.2*VDD_PTx
0.2*VDD_PTx
V
VDD_PTx = 2.7 - 3.6 V
Ioh = 4mA
V
Table continues on the next page...
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System specifications
Table 19. GPIO DC Electrical Requirements (continued)
Symbol
Parameter
Condition
VDD_PTx = 1.72 - 1.95 V
Ioh = 5.8mA
Min
Typ
Max
Unit
Vol (High Drive) Low Level Output
Voltage
0.2*VDD_PTx
V
VDD_PTx = 2.7 - 3.6 V
Ioh = 8mA
0.2*VDD_PTx
5
V
Ioz
Output Hi-Z current
-5
µA
7.5.2.1.1 GPIO Pull-up and Pull-Down Resistance
Table 20. Failsafe GPIO (FSGPIO) pull-up and pull-down resistance (PTA, PTB, PTC, PTE
and PTF)
Symbol
R Pull up
R Pull down
Parameter
Pull-up resistance
Pulldown resistance
Min
Max
Unit
25
25
50
50
kΩ
kΩ
Table 21. Standard GPIO (STGPIO) pull-up and pull-down resistance (PTD)
Symbol
R Pull up
Parameter
Min
Max
100
Unit
Pull-up resistance, high voltage range (2.7 V – 3.6 V)
Pull-up resistance, Low voltage range (1.71 V – 1.89 V)
Pull-down resistance, High voltage range (2.7 V – 3.6 V)
Pull-down resistance, Low voltage range (1.71 V – 1.89 V)
10
20
10
20
kΩ
kΩ
kΩ
kΩ
50
R Pull down
100
50
7.5.2.2 Capacitance attributes
See the device IBIS model for pin capacitance values for the package being used.
7.5.3 Switching electrical characteristics
7.5.3.1 General switching timing specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timer functions.
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Table 22. General switching timing specifications
Symbol
Parameter
Min Typ Max
Unit
Notes
tw_GPIO_sync
GPIO pin interrupt pulse width (Digital Filter
disabled) — Synchronous path
1.5
─
─
─
─
─
─
Bus clock
cycles
1
2
2
tw_RESET_async
tw_GPIO_async
External RESET and NMI pin interrupt pulse width 30
— Asynchronous path
ns
GPIO pin interrupt pulse width — Asynchronous
path
30
ns
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
7.5.3.2 GPIO rise and fall times
Table 23. FSGPIO rise and fall time (PTA, PTB, PTC, PTE, and PTF)
Symbol
τrf
Parameter
Condition
Min
Typ Max
8.3
Unit
ns
Notes
transition
time
Continuous Voltage
Range Normal
CL = 25pF Slow Slew
1
Rate
Standard Slew
Rate
3.4
7.3
0.9
5.4
0.8
8.3
3.4
5.5
0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDD_PTx = 2.7–3.6 V
τrf
τrf
τrf
τrf
transition
time
Continuous Voltage
Range Derated
CL = 25pF Slow Slew
Rate
Standard Slew
Rate
VDD_PTx = 1.98–2.7V
transition
time
Continuous Voltage
Range Derated
CL = 25pF Slow Slew
Rate
Standard Slew
Rate
VDD_PTx = 1.71–1.98V
transition
time
High Voltage Range
VDD_PTx = 3–3.6 V
CL = 25pF Slow Slew
Rate
Standard Slew
Rate
transition
time
Low Voltage Range
CL = 25pF Slow Slew
Rate
VDD_PTx = 1.71–1.98 V
Standard Slew
Rate
1. VDD1P8 = 1.8V
Table 24. STGPIO rise and fall time (PTD)
Symbol
Parameter
Condition
CL = 25pF Slow Slew Rate
Min Typ Max Unit Notes
τrf
transition
time
High Voltage Range
12.0
4.1
ns
ns
1
Standard Slew
Rate
VDD_PTx = 3–3.6 Volts
Table continues on the next page...
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Table 24. STGPIO rise and fall time (PTD) (continued)
Symbol
τrf
Parameter
Condition
CL = 25pF Slow Slew Rate
Min Typ Max Unit Notes
transition
time
Low Voltage Range
7.4
0.8
ns
ns
Standard Slew
Rate
VDD_PTx = 1.71–1.98
Volts
1. VDD1P8 = 1.8V
7.5.3.3 GPIO output buffer maximum frequency
Table 25. GPIO output buffer maximum frequency
Symbol
Parameter
Condition
Min Max Unit
Mfreq (low drive low slew)
Maximum
Frequency
VDD_PTx = 1.65 - 1.95 V, CL = 5pf
VDD_PTx = 1.65 - 1.95 V, CL = 10pf
VDD_PTx = 1.65 - 1.95 V, CL = 40pf
VDD_PTx = 2.7 - 3.6 V, CL = 5pf
VDD_PTx = 2.7 - 3.6 V, CL = 10pf
VDD_PTx = 2.7 - 3.6 V, CL = 40pf
VDD_PTx = 1.65 - 1.95 V, CL = 5pf
VDD_PTx = 1.65 - 1.95 V, CL = 10pf
VDD_PTx = 1.65 - 1.95 V, CL = 40pf
VDD_PTx = 2.7 - 3.6 V, CL = 5pf
VDD_PTx = 2.7 - 3.6 V, CL = 10pf
VDD_PTx = 2.7 - 3.6 V, CL = 40pf
VDD_PTx = 1.65 - 1.95 V, CL = 5pf
VDD_PTx = 1.65 - 1.95 V, CL = 10pf
VDD_PTx = 1.65 - 1.95 V, CL = 40pf
VDD_PTx = 2.7 - 3.6 V, CL = 5pf
VDD_PTx = 2.7 - 3.6 V, CL = 10pf
VDD_PTx = 2.7 - 3.6 V, CL = 40pf
VDD_PTx = 1.65 - 1.95 V, CL = 5pf
VDD_PTx = 1.65 - 1.95 V, CL = 10pf
VDD_PTx = 1.65 - 1.95 V, CL = 40pf
VDD_PTx = 2.7 - 3.6 V, CL = 5pf
VDD_PTx = 2.7 - 3.6 V, CL = 10pf
VDD_PTx = 2.7 - 3.6 V, CL = 40pf
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
120 MHz
100 MHz
50
MHz
115 MHz
95
40
MHz
MHz
Mfreq (low drive high slew) Maximum
Frequency
185 MHz
145 MHz
50
MHz
170 MHz
130 MHz
40
MHz
Mfreq (high drive low slew) Maximum
Frequency
140 MHz
125 MHz
85
MHz
130 MHz
115 MHz
70
MHz
Mfreq (high drive high slew) Maximum
Frequency
235 MHz
200 MHz
100 MHz
215 MHz
185 MHz
80
MHz
7.5.4 Debug and trace modules
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7.5.4.1 JTAG timing specifications
Table 26. JTAG timing specifications
Symbol Parameter
Min
Max
Min—
VLPR
mode
Max—
VLPR
mode
Unit
J1
TCLK frequency of operation
• Boundary Scan
• JTAG
0
0
10
25
—
0
0
10
10
—
MHz
MHz
ns
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
• JTAG
1000/J1
1000/J1
50
20
—
20
—
—
3
50
20
—
20
—
—
3
ns
ns
ns
ns
J4
J5
TCLK rise and fall times
Boundary scan input data setup time to TCLK
rise
—
—
J6
Boundary scan input data hold time after TCLK
rise
5
—
5
—
ns
J7
J8
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
28
25
—
—
19
—
—
—
—
—
19
2
28
25
—
—
19
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
J9
10.5
2.5
—
J10
J11
J12
J13
J14
—
2
TCLK low to TDO high-Z
2
TRST assert time
100
8
100
8
TRST setup time (negation) to TCLK high
J2
J4
J3
J3
TCLK (input)
J4
Figure 5. Test clock input timing
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System specifications
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
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TCLK
TRST
J14
J13
Figure 8. TRST timing
7.5.4.2 Serial Wire Debug (SWD) timing specifications
Table 27. SWD timing specificaions
Symbol Description
Min
Max
Min—
VLPR
mode
Max—
VLPR
mode
Unit
J1
SWD_CLK frequency of operation
0
25
—
0
10
—
MHz
ns
J2
J3
SWD_CLK cycle period
1000/J1
1000/J1
SWD_CLK clock pulse width
20
—
10
—
3
20
—
19
—
3
ns
ns
ns
J4
J9
SWD_CLK rise and fall times
SWD_DIO input data setup time to SWD_CLK
rise
—
—
J10
SWD_DIO input data hold time after SWD_CLK
rise
0
—
0
—
ns
J11
J12
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
2
37
—
—
2
37
—
ns
ns
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 9. SWD clock input timing
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SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 10. SWD data timing
7.5.5 Thermal specifications
7.5.5.1 Thermal operating requirements
Table 28. Thermal operating requirements
Symbol
Parameter
Min.
Typ
Max.
Unit
TJ
Die junction temperature—Industrial
-40
–
105
°C
7.5.5.2 Thermal attributes
NOTE
Per JEDEC JESD51-2, the intent of thermal resistance
measurements is solely for a thermal performance
comparison of one package to another in a standardized
environment. This methodology is not meant to and does not
predict the performance of a package in an application-
specific environment.
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Table 29. Thermal resistance data
Rating
Test Conditions
Symbol
14x14 mm (VK)
Package Value
Unit
°C/W
Notes
Junction to Ambient Natural Single-layer board (1S) RθJA
Convection
49.5
1,2
Junction to Ambient Natural Four-layer board (2s2p) RθJA
30.7
38.6
26.0
°C/W
°C/W
°C/W
1,2,3
1,3
Convection
Junction to Ambient (@ 200 Single-layer board (1S) RθJMA
ft/min)
Junction to Ambient (@ 200 Four-layer board (2s2p) RθJMA
ft/min)
1,3
Junction to Board
─
RθJB
RθJC
ΨJT
15.6
11.7
0.4
°C/W
°C/W
°C/W
°C/W
4
5
6
7
Junction to Case
─
Junction to Package Top
Natural Convection
Junction to Package Bottom Natural Convection
ΨJB
10.1
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of the other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as ΨJT.
7. Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
8 Specifications—application domain
8.1 Peripheral operating requirements and behaviors
8.1.1 DDR timing—application domain
See Multi Mode DDR Controller (MMDC).
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8.1.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC
timing—application domain
This section describes the electrical information of the uSDHC, which includes
support for eMMC and SD (Secure Digital) interfaces.
eMMC is designed to be compliant with the eMMC specification 5.0 and supports the
following modes:
• Backward Compatibility mode (MMC)
• High Speed mode
• HS200
• HS400
The SD (Secure Digital) interface is designed to be compliant with the SD 3.0
specification and supports the following operating modes:
• SDR12
• SDR25
• SDR50
• SDR104
• DDR50
8.1.2.1 SD/eMMC4.3 (single data rate) AC timing
The following figure shows the AC timing of SD/eMMC4.3, and the table lists the
SD/eMMC4.3 timing characteristics.
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Figure 11. SD/eMMC4.3 AC timing
Table 30. SD/eMMC4.3 AC parameters
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1
Clock Frequency (Low Speed)
fPP
0
0
400
kHz
2
Clock Frequency (SD/SDIO Full
Speed/High Speed)
fPP
25/50
MHz
3
Clock Frequency (MMC Full
Speed/High Speed)
fPP
0
20/52
400
MHz
kHz
Clock Frequency (Identification
Mode)
fOD
100
SD2
SD3
SD4
SD5
Clock Low Time
Clock High Time
Clock Rise Time
Clock Fall Time
tWL
tWH
tTLH
tTHL
7
7
—
—
3
ns
ns
ns
ns
—
—
3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
uSDHC Output Delay tOD -3.3
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6
3.6
ns
SD7
SD8
uSDHC Input Setup Time
uSDHC Input Hold Time4
tISU
tIH
7.5
1.0
—
—
ns
ns
1. In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2. In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In High-speed
mode, clock frequency can be any value between 0–50 MHz.
3. In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In High-speed
mode, clock frequency can be any value between 0–52 MHz.
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4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
8.1.2.2 eMMC4.4/4.41 (dual data rate) AC timing
The following figure shows the timing of eMMC4.4/4.41, and the table lists the
eMMC4.4/4.41 timing characteristics. Note that only DATA is sampled on both edges
of the clock (not applicable to CMD).
Figure 12. eMMC4.4/4.41 timing
Table 31. eMMC4.4/4.41 interface timing specifications
ID
Parameter
Symbols
Card Input Clock
fPP
Min
Max
Unit
SD1
SD1
Clock Frequency (eMMC4.4/4.41
DDR)
0
0
52
50
MHz
MHz
Clock Frequency (SD3.0 DDR)
fPP
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
uSDHC Output Delay tOD -3.3 3.6
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2
ns
SD3
SD4
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
7.3
1.0
—
—
ns
ns
8.1.2.3 HS200 mode timing
The following figure depicts the timing of HS200 mode, and the subsequent table lists
the HS200 timing characteristics.
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SD1
SD2
SD3
SCLK
'
SD4/SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
Figure 13. HS200 timing
Table 32. HS200 interface timing specifications
ID
Parameter
Symbols
Min.
Max.
Unit
Card Input clock
SD1
SD2
SD3
Clock Frequency Period
Clock Low Time
tCLK
5.0
—
ns
ns
ns
tCL
0.46 × tCLK
0.54 × tCLK
Clock High Time
tCH
0.46 × tCLK
0.54 × tCLK
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
uSDHC Output Delay tOD -1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
Card Output Data Window tODW 0.5 x tCLK
SD5
SD8
ns
ns
—
1. HS200 is for 8 bits while SDR104 is for 4 bits
8.1.2.4 HS400 AC timing—eMMC5.0 only
The following figure depicts the timing of HS400, and the subsequent table lists the
HS400 timing characteristics. Be aware that only data is sampled on both edges of the
clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the
same as CMD input/output timing for SDR104 mode. Check parameters SD5, SD6, and
SD7 in Table 34 for CMD input/output timing for HS400 mode.
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SD1
SD3
SD2
SCK
SD4
SD5
SD5
SD4
DAT0
Output from
DAT1
...
uSDHC to eMMC
DAT7
Strobe
DAT0
SD6
SD7
Input from
eMMC to uSDHC
DAT1
...
DAT7
Figure 14. HS400 timing
Table 33. HS400 timing specifications
ID
Parameter
Symbols
Min
Max
Unit
Card Input clock
SD1
SD2
SD3
Clock Frequency
Clock Low Time
Clock High Time
fPP
tCL
0
192
MHz
0.46 × tCLK
0.46 × tCLK
uSDHC Output/Card inputs DAT (Reference to SCK)
0.54 × tCLK
ns
ns
tCH
0.54 × tCLK
SD4
SD5
Output Skew from Data of Edge of tOSkew1
SCK
0.45
—
ns
ns
Output Skew from Edge of SCK to tOSkew2
Data
0.45
—
uSDHC input/Card Outputs DAT (Reference to Strobe)
SD6
SD7
uSDHC input skew
uSDHC hold skew
tRQ
—
—
0.45
0.45
ns
ns
tRQH
8.1.2.5 SDR50/SDR104 AC timing
The following figure shows the timing of SDR50/SDR104, and the table lists the
SDR50/SDR104 timing characteristics.
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Figure 15. SDR50/SDR104 timing
Table 34. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD2
SD3
Clock Frequency Period
Clock Low Time
tCLK
tCL
4.8
—
ns
ns
ns
0.46*tCLK
0.46*tCLK
0.54*CLK
0.54*tCLK
Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
uSDHC Output Delay tOD -3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay tOD -1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4
SD5
1
ns
ns
SD6
SD7
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.5
1.5
—
—
ns
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
SD8
Card Output Data Window tODW 0.5*tCLK
—
ns
1. Data window in SDR100 mode is variable.
8.1.2.6 Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of
SDR104/SDR50 mode is 1.8 V.
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Specifications—application domain
8.1.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing parameters indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 35. Flexbus switching specifications
Num
Parameter
Min.
Max.
Unit
Notes
Frequency of operation
• HSRUN mode
—
MHz
66
66
—
• Normal RUN mode
FB1
Clock period
ns
15.0
15.0
—
• HSRUN mode
• Normal RUN mode
FB2
FB3
FB4
FB5
Address, data, and control output valid
Address, data, and control output hold
Data input setup
13.0
—
ns
ns
ns
ns
1
1
2
2
1.0
8.5
0.0
—
Data input hold
—
1. Specification is valid for all FB_AD[31:0], FB_BE, FB_CSn_B, FB_OE_B, FB_RW_B, FB_TBST_B, FB_TSIZ[1:0],
FB_ALE, and FB_TS_B.
2. Specification is valid for all FB_AD[31:0].
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Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB5
FB3
Address
FB4
FB2
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
S1
S0
S2
S3
S0
Figure 16. FlexBus read timing diagram
NOTE
The Transfer Acknowledge Signal (FB_TA) is hard-wired in
the design of i.MX 7ULP, so this signal is not available.
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Write Timing Parameters
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB2
FB3
Address
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 17. FlexBus write timing diagram
NOTE
The Transfer Acknowledge Signal (FB_TA) is hard-wired in
the design of i.MX 7ULP, so this signal is not available.
8.1.4 Display, Video, and Audio Interfaces
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Specifications—application domain
8.1.4.1 MIPI DSI timing—application domain
The i.MX 7ULP conforms to the MIPI D-PHY electrical specifications MIPI DSI
Version 1.01 and D-PHY specification Rev. 1.0 (and also DPI version 2.0, DBI version
2.0, DSC version 1.0a at protocol layer) for MIPI display port x2 lanes.
8.1.4.2 Video Input Unit timing
This section provides the timing parameters of the Video Input Unit (VIU) interface.
VIU_PCLK
VIU_D[23:0]
tSU
tHO
Figure 18. VIU Timing Parameters
Table 36. VIU Timing Parameters
Symbol
fPIX_CK
tDSU
tDHD
Characteristic
Min
_
Max
66.7
_
Unit
MHz
ns
VIU pixel clock frequency
VIU data setup time
VIU data hold time
9.0
1
_
ns
8.1.5 Timer specifications—application domain
See General switching timing specifications for EWM, LPTMR, and TPM.
8.1.6 Connectivity and communications specifications—application
domain
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8.1.6.1 LPUART
See General switching timing specifications.
8.1.6.2 Inter-Integrated Circuit Interface (I2C) timing
Table 37. I 2C timing (Standard, Fast, and Fast Plus modes)
Parameter
Symbol
Standard Mode
Fast Mode
Fast-mode Plus
Unit
Min
0
Max
100
—
Min
Max
400
—
Min
0
Max
1000
—
SCL Clock Frequency
fSCL
0
kHz
µs
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
tHD; STA
4
0.6
0.26
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
0.5
—
—
—
µs
µs
µs
0.26
0.26
Set-up time for a repeated
START condition
tSU; STA
4.7
Data hold time for I2C bus
devices
tHD; DAT
01
3.452
03
0.91
0
—
µs
Data set-up time
tSU; DAT
tr
2504
—
—
1002, 5
20
—
50
—
ns
ns
Rise time of SDA and SCL
signals
1000
300
20
+0.1Cb
120
6
7
5
+0.1Cb
Fall time of SDA and SCL
signals
tf
—
300
20
+0.1Cb
300
20
+0.1Cb
120
ns
5
Set-up time for STOP condition tSU; STO
4
—
—
0.6
1.3
—
—
0.26
0.5
—
—
µs
µs
Bus free time between STOP
and START condition
tBUF
4.7
Pulse width of spikes that must
be suppressed by the input filter
tSP
N/A
N/A
0
50
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
6. Cb = total capacitance of the one bus line in pF.
7. Cb = total capacitance of the one bus line in pF.
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Specifications—application domain
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tHD; STA
tSU; STO
S
SR
P
S
tHD; DAT
tHIGH
Figure 19. Timing definition for standard, fast, and fast plus devices on the I2C bus
Table 38. I 2C timing (High speed mode)
Parameter
Symbol
fSCLH
Minimum
Maximum
Unit
MHz
ns
SCLH Clock Frequency
0
3.4
—
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
160
LOW period of the SCLH clock
HIGH period of the SCLH clock
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tLOW
tHIGH
160
60
160
0
—
—
—
70
—
40
80
ns
ns
ns
ns
ns
ns
ns
tSU; STA
tHD; DAT
tSU; DAT
trCL
10
10
10
Rise time of SCLH signal
Rise time of SCLH signal after a repeated START
condition and after an acknowledge bit
trCL1
Fall time of SCLH signal
Rise time of SDAH signal
Fall time of SDAH signal
Set-up time for STOP condition
tfCL
trDA
10
10
10
160
0
40
80
80
—
10
ns
ns
ns
ns
ns
tfDA
tSU; STO
tSP
Pulse width of spikes that must be suppressed by
the input filter
8.1.6.3 Low Power Serial Peripheral Interface (LPSPI) switching
specifications—application domain
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The following tables provide timing characteristics for classic LPSPI timing modes. See
the LPSPI chapter of the chip reference manual for information about the modified
transfer formats used for communicating with slower peripheral devices.
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All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI
pins.
Table 39. LPSPI master mode switching specifications
Num.
Symbol Description
Min
Max
Unit
Note
1
fop
Frequency of operation:
MHz
1
LPSPI0-1
fperiph/2048
fperiph/2048
30
50
LPSPI2-3
2
tSPSCK
SPSCK period:
LPSPI0-1
ns
2
33.33
16.67
1/2
2048 x tperiph
LPSPI2-3
2048 x tperiph
3
4
5
6
tLead
tLag
Enable lead time
Enable lag time
—
—
tSPSCK
tSPSCK
ns
—
—
—
—
1/2
tWSPSCK Clock (SPSCK) high or low time
(tSPSCK/2) - 2 (tSPSCK/2) + 2
tSU
Data setup time (inputs):
LPSPI0-1
—
ns
16.0
11.6
LPSPI2-3
7
8
tHI
tv
Data hold time (inputs)
Data valid (after SPSCK edge):
LPSPI0-1
0
—
ns
ns
—
—
—
17.2
10.0
—
LPSPI2-3
9
tHO
Data hold time (outputs)
-0.7
ns
—
1. Max frequency is also limited to fperiph/2, where fperiph is programmable for each LPSPIn module
2. tperiph = 1/fperiph
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Specifications—application domain
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 20. LPSPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. LPSPI master mode timing (CPHA = 1)
Table 40. LPSPI slave mode switching specifications
Num.
Symbol Description
fop Frequency of operation:
Min
Max
Unit
Note
1
MHz
1
LPSPI0-1
LPSPI2-3
0
0
15
25
Table continues on the next page...
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Specifications—application domain
Table 40. LPSPI slave mode switching specifications
(continued)
Num.
Symbol Description
tSPSCK SPSCK period:
Min
Max
Unit
Note
2
ns
—
LPSPI0-1
LPSPI2-3
66.6
40
1
—
—
—
—
3
4
5
6
tSS2SPSCK SPI_SS valid to SPI_SPSCK delay
tSPSCK2SS SPI_SPSCK to SPI_SS invalid delay
tWSPSCK Clock (SPSCK) high or low time
tperiph
tperiph
ns
2
2
1
(tSPSCK/2) - 2 (tSPSCK/2) + 2
—
—
tSU
Data setup time (inputs):
LPSPI0-1
ns
9
—
—
LPSPI2-3
4.2
7
8
tHI
Data hold time (inputs):
LPSPI0-1
ns
ns
—
—
6
—
—
LPSPI2-3
3.9
tSPSCK2DV SPI_SPSCK to SPI_MISO data valid (output
data valid):
LPSPI0-1
LPSPI2-3
—
—
20.0
15.5
9
tSPSCK2DH SPI_SPSCK to SPI_MISO data invalid (output
data hold):
ns
—
LPSPI0-1
2.0
2.0
18.1
18
—
—
—
—
LPSPI2-3
10
11
tSS2DRV SPI_SS active to SPI_MISO driven
tSS2HIZ SPI_SS inactive to SPI_MISO not driven
ns
ns
—
—
1. Max frequency is also limited to fperiph/4, where fperiph is programmable for each LPSPIn module
2. tperiph = 1/fperiph
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Specifications—application domain
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 22. LPSPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 23. LPSPI slave mode timing (CPHA = 1)
8.1.6.4 USB Full Speed Transceiver and High Speed PHY specifications
This section describes the High Speed USB PHY parameters. The high speed PHY is
capable of full and low speed signaling as well.
The USB PHY meets the electrical compliance requirements defined in the Universal
Serial Bus Revision 2.0 Specification with the amendments below.
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• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0
Specification
• Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specification (available from USB-IF)
• Revision 1.2, December 7, 2010
USB0_VBUS pin is a detector function which is 5v tolerant and complies with the
above specifications without needing any external voltage division components.
8.1.6.5 USB HSIC timings
This section describes the electrical information of the USB HSIC port.
NOTE
HSIC is a DDR signal. The following timing specifications
are for both rising and falling edges.
8.1.6.5.1 USB HSIC transmit timing
Figure 24. USB HSIC transmit waveform
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Specifications—application domain
Table 41. USB HSIC transmit parameters
Name
Parameter
strobe period
Min
4.166
0
Max
4.167
4.1
Unit
ns
Comment
—
Tstrobe
Todelay
Tslew
data output delay time
ns
Measured at 50% point
strobe/data rising/falling time
1.2
—
V/ns
Average of 30% and
70% voltage levels
8.1.6.5.2 USB HSIC receive timing
Figure 25. USB HSIC receive waveform
Table 42. USB HSIC receive parameters
Name
Tstrobe
Parameter
Min
4.166
0.3
Max
4.167
—
Unit
ns
Comment
strobe period
data hold time
—
Thold
Tsetup
Tslew
ns
Measured at 50% point
data setup time
0.367
1.2
—
ns
Measured at 50% point
strobe/data rising/falling time
—
V/ns
Average of 30% and 70%
voltage levels
8.1.6.6 Parallel interface (ULPI interface)
Electrical characteristics and timing parameters for the parallel interface are presented
in the subsequent sections. The following table lists the parallel interface signal
definitions.
Table 43. USB signal definitions—Parallel (ULPI) interface
Name
Direction
Signal description
USB_CLK
In
Interface clock. All interface signals are synchronous to
clock.
USB_DAT[7:0]
I/O
Bidirectional data bus, driven low by the link during Idle. Bus
ownership is determined by Direction.
Table continues on the next page...
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Table 43. USB signal definitions—Parallel (ULPI) interface
(continued)
Name
Direction
Signal description
USB_DIR
USB_STP
In
Direction. Controls the direction of the Data bus.
Out
Stop. The link asserts this signal for 1 clock cycle to stop the
data stream currently on the bus.
USB_NXT
In
Next. The PHY asserts this signal to throttle the data.
The following figure shows the USB transmit/receive timing diagram in parallel
mode.
Figure 26. USB Transmit and Receive timing diagram—Parallel (ULPI) mode
The following table lists the USB Transmit and Receive timing parameters in Parallel
(ULPI) mode.
Table 44. USB Transmit and Receive Timing Parameters—Parallel (ULPI) Mode
ID
Parameter
Min
Max
Unit
Conditions/
reference signal
US15
US16
US17
Setup time (DIR and NXT in, DAT in)
Hold time (DIR and NXT in, DAT in)
Output delay time (STP out, DAT out)
6.0
0
—
—
ns
ns
ns
14 pF
14 pF
14 pF
0
9.0
9 Specifications—real-time domain
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Specifications—real-time domain
9.1 Power sequencing—real-time domain
See Power sequencing—system.
9.2 Peripheral operating requirements and behaviors—real-time
domain
9.2.1 QuadSPI AC specifications
• All data is based on a negative edge data launch from the device and a positive
edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 10 pF on output pins. Input slew: 2 ns
• Timings assume a setting of 0x0004_000x for QuadSPI _SMPR register (see the
reference manual for details).
SDR mode
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tih
Tis
Data in
Figure 27. QuadSPI input timing (SDR mode) diagram
NOTE
• The timing values below are with default settings for
sampling registers like QuadSPI_SMPR.
• A negative time indicates the actual capture edge inside
the device is earlier than clock appearing at pad.
• Frequency calculator guidelines (Max read frequency) for
any frequency: SCR > (Flash access time)max + (Tis)max
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• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 45. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
6
Max
—
Tis
Tih
Setup time for incoming data
ns
ns
Hold time requirement for incoming data
1
—
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Toh
Tov
Data out
Figure 28. QuadSPI output timing (SDR mode) diagram
Table 46. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
—
3
Max
2
Tov
Output Data Valid
Output Data Hold
SCK clock period
ns
ns
Toh
Tck
—
—
5
99
—
MHz
ns
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
5
—
ns
NOTE
For any frequency, setup and hold specifications of the
memory should be met.
DDR Mode
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Specifications—real-time domain
1
2
3
Clock
Tck
SFCK
Tcss
Tcsh
CS
Tih
Tis
Data in
Figure 29. QuadSPI input timing (DDR mode) diagram
NOTE
• Parameters assume a load of 10 pf
• The parameters are for setting of hold condition in
register QuadSPI_SMPR[DDRSMP]
• Read frequency calculations should be: SCK/2 > (flash
access time) + Setup (Tis) - (edge number) x SCK/4
Table 47. QuadSPI input timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
6
Max
—
Tis
Tih
Setup time for incoming data
Hold time requirement for incoming data
ns
ns
1
—
1
2
3
Clock
Tck
SFCK
CS
Tcss
Tcsh
Tov
Toh
Data out
Figure 30. QuadSPI output timing (DDR mode) diagram
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Table 48. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
SCK clock period
-
2
1.75
ns
ns
Toh
Tck
-
60
-
-
MHz
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
2.7
5.62
Clk(sck)
Clk(sck)
-
Hyperflash mode
QSPI_SCLK
TsMIN
ThMIN
DI[7:0]
Figure 31. QuadSPI input timing (Hyperflash mode) diagram
Table 49. QuadSPI input timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Min
6
Max
TsMIN
ThMIN
Setup time for incoming data
-
-
ns
ns
Hold time requirement for incoming data
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QSPI_SCLK
QSPI_SCLK_B
TclkSKMAX
TclkSKMIN
THO
TDVO
Output Invalid Data
Figure 32. QuadSPI output timing (Hyperflash mode) diagram
Table 50. QuadSPI output timing (Hyperflash mode) specifications
Symbol
Characteristic
Output Data Valid
Min
Max
Unit
ns
TdvMAX
Tho
─
4.3
Output Data Hold
Ck to DQS skew max
Ck to DQS skew min
CK clock period
1.3
─
ns
TclkSKMAX
TclkSKMIN
Tck
─
CK/2 + 0.8
ns
-(CK/2 + 1.2)
─
ns
─
70
MHz
NOTE
Maximum QSPI clock frequency = 70 MHz.
9.2.2 Analog modules
9.2.2.1 12-bit ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
Table 51. ADC Electrical Specifications (VREFH=VDD_ANA_18 and VADINmax≤VREFH)
Symbol
VADIN
Description
Min
Typ
Max
Unit
Notes
Input voltage
VREFL
VREFH
V
CADIN
RADIN
Input capacitance
Input resistance
4.5
pF
Ω
500
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Table 51. ADC Electrical Specifications (VREFH=VDD_ANA_18 and VADINmax≤VREFH)
(continued)
Symbol
RAS
Description
Analog source resistance
Min
Typ
Max
Unit
KΩ
Notes
5
1
2
fADCK
ADC Conversion clock frequency
Sample cycles
8
66
MHz
Csample
Ccompare
Cconversion
3.5
131.5
Fixed compare cycles
Conversion cycles
17.5
cycles
cycles
Cconversion= Csample +
Ccompare
TUE
DNL
INL
Total unadjusted Error
Differential nonlinearity
Integral nonlinearity
Effective number of bits
Single-ended mode
Avg = 1
-14 to -2
1.2
LSB
LSB
LSB
3
3,4
3,4
5
1.2
ENOB
10.5
10.8
11.4
Avg = 2
Avg = 16
Differential mode
Avg = 1
11.4
Avg = 2
—
Avg = 16
—
SINAD
EFS
EZS
EIL
Signal to noise plus distortion
Full-scale error
Zero-scale error
Input leakage error
SINAD=6.02 x ENOB + 1.76
dB
-4
0.05
LSB
LSB
mV
3
3
RAS * Iin
1. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low
as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
2. See Sample time vs. RAS.
3. 1 LSB = (VREFH - VREFL)/2N, N=12
4. ADC conversion clock at max frequency and using linear histogram.
5. Input data used for test was 1 kHz sine wave.
Table 52. ADC electrical specifications (VREFH=1.68 V and
VADINmax≤VDD_PTAmax)1
Symbol
VADIN
Description
Min
Typ2
Max
Unit
Notes
Input voltage— VREFL
Port A
VDD_PTAmax
V
Input voltage—
Port B
VDD_PTBmax
CADIN
Input
4.5
pF
capacitance
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Specifications—real-time domain
Table 52. ADC electrical specifications (VREFH=1.68 V and VADINmax≤VDD_PTAmax)1
(continued)
Symbol
RADIN
Description
Min
Typ2
Max
Unit
Notes
Input resistance
1
KΩ
KΩ
RAS
Analog source
resistance
5
3
4
fADCK
ADC
conversion
clock frequency
8
66
MHz
Csample
Sample cycles 3.5
131.5
Ccompare
Fixed compare
cycles
17.5
Cycles
Cycles
LSB
Cconversion
TUE
Conversion
cycles
Cconversion= Csample + Ccompare
-14 to -2
Total
5
unadjusted
error
DNL
INL
Differential
nonlinearity
1.2
1.2
LSB
LSB
5,6
5,6
7
Integral
nonlinearity
ENOB
Effective Number of Bits
Single-ended mode
Avg = 1
10.3
10.6
11.3
Avg = 2
Avg = 16
Differential mode
Avg = 1
11.2
—
Avg = 2
Avg = 16
—
SINAD
Signal to noise SINAD=6.02 x ENOB + 1.76
plus distortion
dB
EFS
EZS
EIL
Full-scale error
Zero-scale error
-4
LSB
LSB
mV
5
5
0.05
Input leakage
error
RAS * Iin
1. Values in this table are based on design simulations.
2. Typical values assume VDD_ANA_18 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are
for reference only, and are not tested in production.
3. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. See Sample time vs. RAS.
5. 1 LSB = (VREFH - VREFL)/2N, N=12
6. ADC conversion clock at max frequency and using linear histogram.
7. Input data used for test was 1 kHz sine wave.
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Specifications—real-time domain
Table 53. ADC electrical specifications (1V≤VREFH<VDD_ANA18MIN and
VADINMAX≤VREFH)1
Symbol
Description
Min
Typ2
Max
VREFH
Unit
Notes
VADIN
CADIN
Input voltage VREFL
V
Input
4.5
pF
capacitance
RADIN
RAS
Input
resistance
500
Ω
Analog
source
resistance
5
KΩ
3
4
fADCK
ADC
conversion
clock
8
44
MHz
frequency
Csample
Sample
cycles
3.5
131.5
Ccompare
Fixed
17.5
Cycles
compare
cycles
Cconversion
TUE
Conversion
cycles
Cconversion= Csample + Ccompare
-14 to -2
Cycles
LSB
Total
5
unadjusted
error
DNL
INL
Differential
nonlinearity
1.2
1.2
LSB
LSB
5,6
5,6
7
Integral
nonlinearity
ENOB
Effective number of bits
Single-ended mode
Avg = 1
9.8
Avg = 2
10.2
11.1
Avg = 16
Differential mode
Avg = 1
10.7
—
Avg = 2
Avg = 16
—
SINAD
Signal to
noise plus
distortion
SINAD=6.02 x ENOB + 1.76
dB
EFS
EZS
EIL
Full-scale
error
-4
LSB
LSB
mV
5
5
Zero-scale
error
0.05
Input leakage RAS * Iin
error
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1. Values in this table are based on design simulations.
2. Typical values assume VDD_ANA_18 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are
for reference only, and are not tested in production.
3. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. See Sample time vs. RAS.
5. 1 LSB = (VREFH - VREFL)/2N, N=12
6. ADC conversion clock at max frequency and using linear histogram.
7. Input data used for test was 1 kHz sine wave.
The following figure shows a plot of the ADC sample time versus RAS.
Figure 33. Sample time vs. RAS
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Specifications—real-time domain
9.2.2.1.1 12-bit ADC operating conditions
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
Pad
leakage
ZAS
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
RADIN
RAS
VADIN
CAS
VAS
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
RADIN
CADIN
Figure 34. ADC input impedance equivalency diagram
9.2.2.2 12-bit DAC electrical characteristics
9.2.2.2.1 12-bit DAC operating requirements
Table 54. 12-bit DAC operating conditions
Symbol
Description
Output load capacitance
Output load current
Min
Typ
Max
Unit
Notes
CL
IL
—
—
50
—
100
1
pF
1
2
mA
1. The DAC output can drive R and C loading. The user should consider both DC and dynamic application requirements.
50pF CL provides the best dynamic performance, while 100pF provides the best DC performance.
2. Sink or source current ability.
Table 55. DAC characteristics
Symbol
Description
Test Conditions
Min
Typ
Max
0.15
Units
Notes
VDACOUTL DAC low level output VREFH_ANA18 selected,
VSS
—
V
1
voltage
Rload=18k, Cload=50pF
VDACOUTH DAC high level output
voltage
VDD_ANA18 —
-0.15
VDD_
ANA18
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Table 55. DAC characteristics (continued)
Symbol
DNL
Description
Test Conditions
Min
Typ
Max
Units
LSB
Notes
Differential non-
linearity error
Code 100h → F00h best fit
—
0.5
1
—
curve
INL
Integral non-linearity
error
Code 100h → F00h best fit
curve
—
—
—
—
1
—
2
2
—
—
—
3
EO
Offset error
Code 100h
Code 100h
0.6
30
%FSR
µV/°C
—
—
TEO
Offset error
temperature coefficient
EG
Gain error
Code F00h
—
—
0.4
—
—
%FSR
—
—
TEG
Gain error temperature Code F00h
coefficient
10
ppm of
FSR/°C
TFS_LS
TFS_MS
TFS_HS
TCC_LS
TCC_MS
TCC_HS
SR_LS
SR_MS
SR_HS
90
Full scale setting time Code → F00h or F00h → 100h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
µs
4
in Low Speed mode
@ ZTC current
Code 100h → F00h or F00h →
100h @ PTAT current
5
Full scale setting time Code 100h → F00h or F00h →
in Middle Speed mode 100h @ ZTC current
1
Code 100h → F00h or F00h →
100h @ PTAT current
1
Full scale setting time Code 100h → F00h or F00h →
0.5
0.5
1
in High Speed mode
100h @ ZTC current
Code 100h → F00h or F00h →
100h @ PTAT current
Code to code setting
time in Low Speed
mode
Code 7F7h → 807h or 807h →
7F7h @ ZTC current
Code 7F7h → 807h or 807h →
1
7F7h @ PTAT current
Code to code setting
Code 7F7h → 807h or 807h →
0.5
0.5
0.3
0.3
0.24
0.24
1.2
1.2
2.4
time in Middle Speed 7F7h @ ZTC current
mode
Code 7F7h → 807h or 807h →
7F7h @ PTAT current
Code to code setting
time in High Speed
mode
Code 7F7h → 807h or 807h →
7F7h @ ZTC current
Code 7F7h → 807h or 807h →
7F7h @ PTAT current
Slew rate in Low
Speed mode
Code 100h → F00h or F00h →
100h @ ZTC current
V/µs
5
Code 100h → F00h or F00h →
100h @ PTAT current
Slew rate in Middle
Speed mode
Code 100h → F00h or F00h →
100h @ ZTC current
Code 100h → F00h or F00h →
100h @ PTAT current
Slew rate in High
Speed mode
Code 100h → F00h or F00h →
100h @ ZTC current
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Specifications—real-time domain
Table 55. DAC characteristics (continued)
Symbol
Description
Test Conditions
Min
Typ
2.4
Max
Units
Notes
Code 100h →F00h or F00h →
100h @ PTAT current
—
—
—
PSRR
Power supply rejection Code 800h,
70
—
dB
6
ratio
ΔVDD_ANA18=100mV,
VREFH_ANA12 selected
Code 100h → F00h → 100h
Code 7FFh → 800h → 7FFh
—
Glitch
Glitch energy
—
—
—
30
30
—
—
nV-s
—
—
CT
Channel to channel
crosstalk
-80
dB
Ω
7
8
ROP
Output resistance
Code 100h → F00h and
—
200
—
Rload=18kΩ
1. It is recommended to operate the DAC in the output voltage range between 0.15 V and (VDD_ANA18 - 0.15 V) for
best accuracy. Linearity of the output voltage outside this range will be affected as current load increases.
2. When VREFH_ANA18 is selected as the reference (DAC_CR[DACRFS]=1b).
3. When the internal 1.2 V source is selected as the reference (DAC_CR[DACRFS]=1b).
4. The DAC output remains within 0.5 LSB of the final measured value for digital input code change. Noise on the
power supply can cause this performance to degrade to 1 LSB. This parameter represents both rising edge and
falling edge settling time.
5. Time for the DAC output to transition from 10% to 90% signal amplitude (rising edge or falling edge).
6. PSRR=20*log{∆VDD_ANA18 /∆VDAC_OUT}
7. If two DACs are used and sharing the same VREFH.
8. Based on design simulation.
9.2.2.3 CMP electrical specifications
Table 56. CMP Operating Conditions
Symbol
VREFH_EXT
VREFH_INT1
Description
External reference voltage
Internal reference voltage
Min
1
Typ
—
Max
1.98
—
Unit
V
—
1.3
V
1. This is an internally generated voltage reference generated by PMC0.
Table 57. CMP Characteristics
Symbol
VAIN
Description
Condition
Min
Typ
Max
VDD_PTx, 1
20
Unit
V
Analog input voltage
0
VAIO
Analog input offset
voltage
mV
VH
Analog comparator
hysteresis
Hysctrl[1:0]=00
Hysctrl[1:0]=01
Hysctrl[1:0]=10
Hysctrl[1:0]=11
5
mV
mV
mV
mV
10
20
30
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Table 57. CMP Characteristics (continued)
Symbol
TDHS
Description
Condition
Min
Typ
Max
Unit
Propagation delay,
high-speed mode
Nominal supply
50
ns
TDHS
Propagation delay,
low-speed mode
5
20
1
µs
µs
Analog comparator
initialization delay
INL
8B DAC integral non-
linearity
-1
-1
LSB
LSB
DNL
8B DAC differential
non-linearity
1
1. The maximum input voltage for CMP analog inputs associated with Port A (PTA) is VDD_PTA. The maximum input
voltage for CMP analog inputs associated with Port B (PTB) is VDD_PTB.
9.2.3 Timer specifications—real-time domain
See General switching timing specifications.
9.2.4 Connectivity and communications specifications—real-time
domain
9.2.4.1 LPUART
See General switching timing specifications.
9.2.4.2 Inter-Integrated Circuit Interface (I2C) timing—real-time domain
See Inter-Integrated Circuit Interface (I2C) timing.
9.2.4.3 LPSPI switching specifications—real-time domain
See Low Power Serial Peripheral Interface (LPSPI) switching specifications—
application domain.
9.2.4.4 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
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(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
Table 58. I2S/SAI master mode timing
Num.
Parameter
Min
20
Max
—
Unit
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
MCLK period
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
40
55%
—
45%
—
55%
7.5
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
1
15.9
—
ns
ns
ns
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
S9
I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
21.3
0
—
S10
—
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 35. I2S/SAI timing — master modes
Table 59. I2S/SAI slave mode timing
Num.
Parameter
Min
40
Max
—
Unit
ns
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input)
45%
55%
MCLK period
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Table 59. I2S/SAI slave mode timing (continued)
Num.
Parameter
Min
Max
Unit
S13
I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/
I2S_RX_BCLK
13
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/
I2S_RX_BCLK
1
—
ns
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
1
22.8
—
ns
ns
ns
ns
ns
12
1
—
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
—
17.0
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 36. I2S/SAI timing — slave modes
9.2.4.5 VLPR, VLPW, and VLPS mode performance
This section provides the operating performance for the device in VLPR, VLPW, and
VLPS modes.
Table 60. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
Num.
Parameter
Min
60
Max
—
Unit
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
MCLK period
ns
I2S_MCLK pulse width high/low
45%
100
45%
—
55%
—
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output valid
Table continues on the next page...
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Table 60. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (continued)
Num.
Parameter
Min
Max
Unit
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
0
25
—
—
—
ns
ns
ns
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
S9
I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
25
0
S10
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 37. I2S/SAI timing — master modes
Table 61. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes
Num.
Parameter
Min
100
45%
30
Max
—
Unit
S11
S12
S13
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input)
ns
MCLK period
ns
55%
—
I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/
I2S_RX_BCLK
S14
I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/
I2S_RX_BCLK
2
—
ns
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
1
40
—
—
—
27
ns
ns
ns
ns
ns
30
5
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 38. I2S/SAI timing — slave modes
9.2.4.6 FlexIO specifications—real-time domain
See General switching timing specifications
10 Package information and contact assignments
This section contains package information and contact assignments for the following
packages:
• BGA 14 x 14 mm, 0.5 mm pitch (VP suffix)
10.1 BGA, 14 x 14 mm, 0.5 mm pitch (VP suffix)
This section includes the following information for the 14 x 14 mm, 0.5 mm pitch
package:
• Case outline
• Ball map
• Contact assignments
10.1.1 14 x 14 mm package case outline
The following figure shows the top, bottom, and side views of the 14 × 14 mm BGA
package.
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Package information and contact assignments
Figure 39. 14 x 14 mm case outline
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Package information and contact assignments
Figure 40. Notes on 14 x 14 mm case outline
10.1.2 14 x 14 mm, 0.5 mm pitch, ball map
The following page shows the 14 × 14 mm, 0.5 mm pitch, ball map.
98
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
NXP Semiconductors
Package information and contact assignments
14 x 14 mm, 0.5 mm pitch, ballmap
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ꢒꢌꢓꢔꢑꢌꢎꢖꢙꢘꢕ
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ꢍꢎꢔꢅ
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ꢋꢐꢐꢑꢍꢎꢐ
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ꢐꢐꢖꢑꢔꢊꢂ
ꢐꢐꢖꢑꢐꢗꢁ
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ꢐꢐꢖꢑꢐꢗꢀꢀ
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ꢡ
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ꢎꢕꢌꢎꢔꢞꢝꢑꢍ
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ꢐꢐꢖꢑꢔꢊꢈ
ꢐꢐꢖꢑꢙꢐꢎ
ꢐꢐꢖꢑꢋꢖꢕꢏꢀ
ꢐꢐꢖꢑꢔꢊꢇ
ꢐꢐꢖꢑꢐꢗꢀꢄ
ꢐꢐꢖꢑꢐꢗꢛꢂ
ꢋꢌꢌ
ꢐꢐꢖꢑꢐꢗꢀꢃ
ꢐꢐꢖꢑꢐꢗꢀꢂ
ꢐꢐꢖꢑꢐꢗꢌꢂꢑꢘ
ꢐꢐꢖꢑꢐꢗꢁꢅ
ꢐꢐꢖꢑꢐꢗꢁꢇ
ꢊꢊ
ꢊꢘ
ꢊꢔ
ꢊꢐ
ꢊꢕ
ꢊꢏ
ꢊꢚ
ꢋꢐꢐꢑꢍꢎꢘ
ꢋꢐꢐꢑꢊꢟꢊꢀꢇ
ꢖꢕꢌꢕꢎꢉꢑꢤ
ꢋꢐꢐꢑꢊꢟꢊꢂꢂ
ꢋꢖꢕꢏꢞꢑꢊꢟꢊ
ꢋꢐꢐꢑꢍꢎꢊ
ꢍꢎꢊꢅ
ꢋꢌꢌ
ꢍꢎꢊꢇ
ꢍꢎꢊꢈ
ꢍꢎꢊꢀꢉ
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ꢍꢎꢊꢀꢈ
ꢊꢊ
ꢊꢘ
ꢊꢔ
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ꢊꢏ
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ꢕꢣꢎꢊꢞꢉ
ꢋꢐꢐꢑꢍꢛꢔꢀꢇ
ꢋꢐꢐꢑꢍꢛꢔꢀꢁꢑꢐꢓꢚꢀ
ꢍꢎꢘꢀꢀ
ꢍꢎꢘꢀꢉ
ꢍꢎꢘꢈ
ꢍꢎꢊꢁꢀ
ꢍꢎꢊꢁꢁ
ꢍꢎꢊꢁꢂ
ꢋꢌꢌ
ꢋꢌꢌ
ꢐꢐꢖꢑꢐꢗꢌꢂ
ꢐꢐꢖꢑꢐꢗꢁꢃ
ꢐꢐꢖꢑꢐꢗꢁꢆ
ꢋꢐꢐꢑꢍꢛꢔꢀꢁꢑꢐꢓꢚꢀ
ꢋꢖꢕꢏꢒꢑꢊꢟꢊꢀꢇ
ꢋꢌꢌꢑꢊꢐꢔꢑꢊꢟꢊ
ꢐꢊꢔꢀꢑꢙꢠꢎ
ꢍꢎꢊꢄ
ꢍꢎꢊꢀꢇ
ꢋꢌꢌ
ꢋꢌꢌ
ꢋꢌꢌ
ꢋꢌꢌ
ꢋꢌꢌ
ꢍꢎꢘꢂ
ꢍꢎꢘꢄ
ꢋꢐꢐꢑꢍꢎꢘ
ꢋꢌꢌ
ꢍꢎꢘꢀꢂ
ꢍꢎꢘꢀꢈ
ꢋꢌꢌ
ꢐꢊꢔꢉꢑꢙꢠꢎ
ꢍꢎꢊꢆ
ꢍꢎꢊꢉ
ꢍꢎꢊꢂ
ꢍꢎꢊꢃ
ꢍꢎꢊꢀꢀ
ꢋꢌꢌ
ꢍꢎꢊꢀꢆ
ꢍꢎꢊꢁꢉ
ꢋꢌꢌ
ꢍꢎꢊꢁꢈ
ꢍꢎꢊꢂꢉ
ꢋꢌꢌ
ꢋꢌꢌ
ꢍꢎꢘꢁ
ꢋꢌꢌ
ꢐꢐꢖꢑꢐꢗꢂꢉ
ꢐꢐꢖꢑꢐꢗꢂꢀ
ꢋꢌꢌ
ꢍꢎꢘꢀ
ꢍꢎꢘꢅ
ꢍꢎꢘꢆ
ꢍꢎꢘꢀꢄ
ꢍꢎꢘꢀꢅ
ꢍꢎꢘꢀꢆ
ꢋꢌꢌꢑꢊꢐꢔꢑꢊꢟꢊ
ꢍꢎꢊꢀ
ꢍꢎꢊꢀꢂ
ꢍꢎꢊꢀꢃ
ꢍꢎꢊꢀꢄ
ꢍꢎꢊꢁꢃ
ꢍꢎꢊꢁꢅ
ꢍꢎꢊꢁꢆ
ꢍꢎꢊꢂꢀ
ꢐꢐꢖꢑꢐꢗꢁꢄ
ꢋꢌꢌ
ꢀ
ꢍꢎꢘꢉ
ꢁ
ꢍꢎꢘꢃ
ꢃ
ꢍꢎꢘꢇ
ꢅ
ꢍꢎꢘꢀꢃ
ꢇ
ꢍꢎꢘꢀꢇ
ꢀꢉ
ꢋꢌꢌꢑꢊꢐꢔꢑꢊꢟꢊ
ꢀꢁ
ꢍꢎꢊꢁ
ꢀꢃ
ꢍꢎꢊꢀꢁ
ꢀꢅ
ꢍꢎꢊꢀꢅ
ꢀꢇ
ꢍꢎꢊꢁꢄ
ꢁꢉ
ꢍꢎꢊꢁꢇ
ꢁꢁ
ꢐꢐꢖꢑꢥꢗꢉ
ꢁꢃ
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99
NXP Semiconductors
i.
MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
Package information and contact assignments
10.1.3 14 x 14 mm power supply and functional contact
assignments
The following table shows the power supply contact assignments for the 14 × 14 mm
package.
Table 62. 14 x 14 mm power supply contact assignments
Supply Name
14x14 mm VP Package Ball
Position
Remarks
DDR_ODT
AA22
DDR on-die termination
DDR_VREF0
DDR_VREF1
DDR_ZQ0
H23
DDR voltage reference input. Connect to a voltage
source that is 50% of VDD_DDR.
Y23
DDR voltage reference input. Connect to a voltage
source that is 50% of VDD_DDR.
AG24
Connect DDR_ZQ0 to an external 240Ω 1% resistor to
Vss. This is a reference used during DDR output
buffer driver calibration.
TESTCLK_N
TESTCLK_P
AA8
AB8
Test function for NXP use only. This output must
remain unconnected.
Test function for NXP use only. This output must
remain unconnected.
USB0_VBUS
VDD_ANA18
VDD_ANA33
VDD_DDR
T4
USB0 VBUS detection
AB11
AA12
ADC analog and IO 1.8V supply input
ADC analog and IO 3.3V supply input
H22, J21, M22, N21, T21, U22, Y21 DDR I/O supply input
VDD_DIG0
VDD_DIG1
V16, V17
M4 domain core and logic supply input
K11, K12, K13, K15, K16, K17, L10, A7 domain core and logic supply input
L14, L18, M10, M18, N10, N18, P11,
P17, R10, R18, T18, U18
VDD_DSI11
L6
MIPI DSI 1.1V supply input
MIPI DSI 1.8V supply input
HSIC 1.2V supply input
VDD_DSI18
M5
VDD_HSIC
D6
VDD_PLL18
W7
PLL analog supply input
VDD_PMC11_DIG0_CAP
VDD_PMC11_DIG1_CAP
VDD_PMC12_DIG1
U14, V15
T10, U10
AB4, AC4
M4 domain LDO supply output
A7 domain LDO supply output
A7 domain LDO and internal memory LDO supply
input
VDD_PMC18
AB3
M4/A7 PMC and PMC IO supply input
VDD_PMC18_DIG0
V11, V12, V13
M4 domain LDO and internal memory LDO supply
input
VDD_PTA
VDD_PTB
AA15, AA19
AA11, AD6
GPIO Port A supply input
GPIO Port B supply input
Table continues on the next page...
100
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
NXP Semiconductors
Package information and contact assignments
Table 62. 14 x 14 mm power supply contact assignments (continued)
Supply Name
14x14 mm VP Package Ball
Position
Remarks
VDD_PTC
D14, E16
GPIO Port C supply input
VDD_PTD
D20, E20
D10, E9
F4, G4
R7
GPIO Port D supply input
GPIO Port E supply input
GPIO Port F supply input
USB PHY 1.8V supply input
USB PHY 3.3V supply input
SNVS domain LDO output
SNVS domain LDO supply input
DDR 1.8V pre-driver supply input
HSIC 1.8V supply input
VDD_PTE
VDD_PTF
VDD_USB18
VDD_USB33
VDD_VBAT18_CAP
VDD_VBAT42
VDD18_DDR
VDD18_HSIC
VDD18_IOREF
R5
T6
T5
F24
A4
L7
1.8V IO supply reference and A7 supply reference
input
VREFH_ANA18
VREFL_ANA
VSS
AC12
AB12
ADC high reference supply input
ADC low reference supply input
A1, A27, B4, C4, C6, C8, C10, C12, Ground
C14, C16, C18, C20, C22, C24, C25,
D3, D25, E21, F3, F8, F20, F21,
F25, G20, H3, H8, H20, H25, K3, K4,
K10, K14, K18, K25L5, L11, L12,
L13, L15, L16, L17, M3, M6, M7,
M11, M14, M17, M21, M25, N2, N11,
N14, N17, P3, P4, P10, P12, P13,
P14, P15, P16, P18, P25, R4, R7,
R11, R14, R17, T3, T7, T11, T4,
T17, T25, U2, U11, U12, U13, U15,
U16, U17, U21, V3, V10, V14, V18,
V25, W5, W6, Y1, Y3, Y5, Y6, Y20,
AA16, AB1, AB24, AB25, AD1, AD2,
AD3, AD4, AD25, AE2, AE6, AE8,
AE10, AE16, AE18, AE20, AE22,
AE24, AF1, AG1, AG27
VSS_ADC_ANA
AD12, AF12, AG12
ADC analog ground
The following table shows functional contact assignments for the 14 x 14 mm
package.
Table 63. 14 x 14 mm functional contact assignments
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
DAC0_OUT
AD11
VDD_ANA18 Analog
-
DAC0_OUT
-
-
Table continues on the next page...
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
101
NXP Semiconductors
Package information and contact assignments
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
DAC1_OUT
AD12
N23
N22
M23
J23
VDD_ANA18 Analog
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DAC1_OUT
DDR_CA0
-
-
DDR_CA0
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output
Output
Output/PD
Output/PD
PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output/PD
Output
Output
Output/PD
Output/PD
PD
DDR_CA1
DDR_CA1
DDR_CA2
DDR_CA2
DDR_CA3
DDR_CA3
DDR_CA4
J22
DDR_CA4
DDR_CA5
T23
T22
U23
AA23
Y22
P26
P24
R26
T26
P27
N24
H26
H27
V26
W26
Y26
Y27
Y25
Y24
A26
B27
B26
C26
H24
D26
D27
D24
E24
AC26
AF26
DDR_CA5
DDR_CA6
DDR_CA6
DDR_CA7
DDR_CA7
DDR_CA8
DDR_CA8
DDR_CA9
DDR_CA9
DDR_CKE0
DDR_CKE1
DDR_CLK0
DDR_CLK0_B
DDR_CS0_B
DDR_CS1_B
DDR_DQ0
DDR_DQ1
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ2
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_CKE0
DDR_CKE1
DDR_CLK0
DDR_CLK0_B
DDR_CS0_B
DDR_CS1_B
DDR_DQ0
DDR_DQ1
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ2
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Table continues on the next page...
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102
NXP Semiconductors
Package information and contact assignments
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
DDR_DQ26
AD27
AD26
AF27
AG26
J24
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ3
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ3
PD
PD
PD
PD
DDR_DQ30
DDR_DQ31
DDR_DQ4
AE25
AF25
K24
DDR_DQ30
DDR_DQ31
DDR_DQ4
PD
PD
PD
DDR_DQ5
K27
DDR_DQ5
PD
DDR_DQ6
K26
DDR_DQ6
PD
DDR_DQ7
L26
DDR_DQ7
PD
DDR_DQ8
V24
DDR_DQ8
PD
DDR_DQ9
V27
DDR_DQ9
PD
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS0_B
DDR_DQS1
DDR_DQS1_B
DDR_DQS2
DDR_DQS2_B
DDR_DQS3
DDR_DQS3_B
DSI_CLK_N
M24
T27
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS0_B
DDR_DQS1
DDR_DQS1_B
DDR_DQS2
DDR_DQS2_B
DDR_DQS3
DDR_DQS3_B
DSI_CLK_N
Output/PD
Output/PD
Output/PD
Output/PD
Hi-Z
Output/PD
Output/PD
Output/PD
Output/PD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
G26
AA24
M26
M27
U24
T24
Hi-Z
Hi-Z
Hi-Z
F27
Hi-Z
F26
Hi-Z
AB26
AB27
M2
Hi-Z
Hi-Z
VDD_DSI18 MIPI DSI
PHY
-
DSI_CLK_P
DSI_DATA0_N
DSI_DATA0_P
DSI_DATA1_N
DSI_DATA1_P
EXTAL
M1
P2
VDD_DSI18 MIPI DSI
PHY
-
-
-
-
-
-
DSI_CLK_P
DSI_DATA0_N
DSI_DATA0_P
DSI_DATA1_N
DSI_DATA1_P
EXTAL
-
-
-
-
-
-
-
-
-
-
-
-
VDD_DSI18 MIPI DSI
PHY
P1
VDD_DSI18 MIPI DSI
PHY
L4
VDD_DSI18 MIPI DSI
PHY
M4
AB2
VDD_DSI18 MIPI DSI
PHY
VDD_PMC18 Analog
Table continues on the next page...
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
103
NXP Semiconductors
Package information and contact assignments
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
EXTAL32
W4
VDD_VBAT1 Analog
8_CAP
-
EXTAL32
-
-
HSIC_DATA
HSIC_STROBE
ONOFF
D4
D5
Y2
VDD_HSIC
VDD_HSIC
DDR
DDR
-
-
-
HSIC_DATA
HSIC_STROBE
ONOFF
Input/PD
Input/PD
Input/PU
Input/PD
Input/PD
Input/PU
VDD_VBAT1 SNVS
8_CAP
PMIC_ON_REQ V1
VDD_VBAT1 SNVS
8_CAP
-
PMIC_ON_REQ Output/High Output/High
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
AE14
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
FSGPIO
0000b
0000b
0000b
0000b
0000b
0000b
0000b
CMP0_IN1_3V
CMP0_IN2_3V
CMP1_IN2_3V
CMP1_IN4_3V
ADC1_CH3A
ADC1_CH3B
Input
Input
Input
Input
Input
Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AF13
AG14
AF14
AD15
AC15
AB15
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
ADC1_CH4A/5A/ Input
6A/7A/8A
PTA7
AD14
AB16
AC16
AD16
AD18
AG16
AF16
AF17
AF18
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
ADC1_CH4B/5B/ Input
6B/7B/8B
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PTA8
ADC1_CH4A/5A/ Input
6A/7A/8A
PTA9
ADC1_CH4B/5B/ Input
6B/7B/8B
PTA10
PTA11
PTA12
PTA13
PTA14
PTA15
ADC1_CH4A/5A/ Input
6A/7A/8A
ADC1_CH4B/5B/ Input
6B/7B/8B
ADC1_CH4A/5A/ Input
6A/7A/8A
ADC1_CH4B/5B/ Input
6B/7B/8B
ADC1_CH4A/5A/ Input
6A/7A/8A
ADC1_CH4B/5B/ Input
6B/7B/8B
PTA16
PTA17
PTA18
PTA19
PTA20
AG18
AD19
AC19
AB19
AD22
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
0000b
0000b
CMP1_IN5_3V
CMP1_IN6_3V
CMP1_IN1_3V
CMP1_IN3_3V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ADC0_CH8A/9A/ Hi-Z
10A
Table continues on the next page...
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
104
NXP Semiconductors
Package information and contact assignments
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
PTA21
AB20
AC20
AD20
AF20
AG20
AF21
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
VDD_PTA
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
0000b
0000b
1010b
ADC0_CH8B/9B/ Hi-Z
10B
Hi-Z
PTA22
PTA23
PTA24
PTA25
PTA26
ADC0_CH8A/9A/ Hi-Z
10A
Hi-Z
ADC0_CH8B/9B/ Hi-Z
10B
Hi-Z
ADC0_CH8A/9A/ Hi-Z
10A
Hi-Z
ADC0_CH8B/9B/ Hi-Z
10B
Hi-Z
JTAG_TMS/
SWD_DIO
Input/PU
Input/PU
PTA27
PTA28
PTA29
AF22
AG22
AD23
VDD_PTA
VDD_PTA
VDD_PTA
FSGPIO
FSGPIO
FSGPIO
1010b
1010b
1010b
JTAG_TDO
JTAG_TDI
Hi-Z
Hi-Z
Input/PU
Input/PD
Input/PU
Input/PD
JTAG_TCLK/
SWD_CLK
PTA30
PTA31
PTB0
PTB1
PTB2
AD24
AF24
AG2
AF2
VDD_PTA
VDD_PTA
VDD_PTB
VDD_PTB
VDD_PTB
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
1010b
0000b
0000b
0000b
0000b
JTAG_TRST_B
ADC0_CH1B
ADC0_CH0A
ADC0_CH0B
Input/PU
Hi-Z
Input/PU
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AE3
ADC0_CH4A/5A/ Hi-Z
6A
Hi-Z
PTB3
AE4
VDD_PTB
FSGPIO
0000b
ADC0_CH4B/5B/ Hi-Z
6B
Hi-Z
PTB4
PTB5
PTB6
PTB7
PTB8
AG4
AF4
AF5
AF6
AG6
VDD_PTB
VDD_PTB
VDD_PTB
VDD_PTB
VDD_PTB
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
0000b
0000b
BT_MODE0
BT_MODE1
ADC1_CH1A
ADC1_CH1B
Input/PD
PD
Input/PD
Hi-Z
PD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ADC0_CH14A/
CMP0_IN0
Hi-Z
PTB9
AD7
VDD_PTB
FSGPIO
0000b
ADC0_CH14B/
CMP0_IN2
Hi-Z
Hi-Z
PTB10
PTB11
PTB12
AC7
AB7
AC8
VDD_PTB
VDD_PTB
VDD_PTB
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
CMP0_IN1
CMP0_IN3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ADC1_CH13A/
CMP1_IN0
PTB13
AD8
VDD_PTB
FSGPIO
0000b
ADC1_CH13B/
CMP1_IN1
Hi-Z
Hi-Z
PTB14
PTB15
AG8
AF8
VDD_PTB
VDD_PTB
FSGPIO
FSGPIO
0000b
0000b
ADC1_CH2A
ADC1_CH2B
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table continues on the next page...
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
105
NXP Semiconductors
Package information and contact assignments
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
PTB16
AF9
VDD_PTB
VDD_PTB
VDD_PTB
VDD_PTB
FSGPIO
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
0000b
ADC0_CH4A/5A/ Hi-Z
6A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PTB17
PTB18
PTB19
AF10
AG10
AD10
ADC0_CH4B/5B/ Hi-Z
6B
ADC0_CH4A/5A/ Hi-Z
6A
ADC0_CH4B/5B/ Hi-Z
6B
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTC8
PTC9
PTC10
PTC11
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
PTC18
PTC19
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTD8
D18
E17
F17
G17
F16
D17
D16
G16
A16
B16
B15
B14
A14
D13
E13
F13
G13
G12
F12
E12
A24
B24
B23
B22
A22
B21
B22
A20
B20
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTC
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTD
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
STGPIO
STGPIO
STGPIO
STGPIO
STGPIO
STGPIO
STGPIO
STGPIO
STGPIO
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table continues on the next page...
106
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
NXP Semiconductors
Package information and contact assignments
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
PTD9
B19
B18
A18
D12
A12
B12
B11
B10
A10
D9
E8
VDD_PTD
VDD_PTD
VDD_PTD
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTE
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTF
STGPIO
STGPIO
STGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
FSGPIO
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
0000b
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PTD10
PTD11
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE7
PTE8
PTE9
PTE10
PTE11
PTE12
PTE13
PTE14
PTE15
PTF0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Hi-Z
F9
G9
D8
A8
B8
B7
B6
A6
D2
B2
PTF1
PTF2
B3
PTF3
C3
E2
PTF4
PTF5
B1
PTF6
A2
PTF7
F2
PTF8
F1
PTF9
D1
G5
G6
H7
H6
H5
H4
H1
PTF10
PTF11
PTF12
PTF13
PTF14
PTF15
PTF16
Table continues on the next page...
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
107
NXP Semiconductors
Revision History
Table 63. 14 x 14 mm functional contact assignments (continued)
Ball Name
14 x 14 mm
VP Package
Ball
Power
Group
Signal Type Default
Default
State
During
Reset3
State After
Reset1, 3
1, 2
MUX_
Function1
MODE1
Position
PTF17
H2
VDD_PTF
VDD_PTF
VDD_PTF
VDD_PTB
VDD_PTF
FSGPIO
FSGPIO
FSGPIO
RESET
RESET
0000b
-
-
-
Hi-Z
Hi-Z
PTF18
J2
0000b
Hi-Z
Hi-Z
PTF19
K2
0000b
Hi-Z
Hi-Z
RESET0_B
RESET1_B
AC11
K1
-
-
-
RESET0_B
RESET1_B
Output/OD
Output/OD
Input/PU
Input/PU
STANDBY_REQ V2
VDD_VBAT1 SNVS
8_CAP
STANDBY_REQ Output/Low Output/Low
TAMPER
V4
VDD_VBAT1 SNVS
8_CAP
-
TAMPER
Hi-Z4
Input
TESTCLK_N
TESTCLK_P
USB0_DM
AA8
AB8
T2
VDD_PTB
VDD_PTB
-
-
-
-
-
-
-
TESTCLK_N
TESTCLK_P
USB0_DM
-
-
-
-
-
-
-
-
-
VDD_USB33 USB PHY
VDD_USB33 USB PHY
VDD_USB33 USB PHY
USB0_DP
T1
USB0_DP
USB0_VBUS_DE T4
TECT
USB0_VBUS_DE -
TECT
XTAL
AA2
Y4
VDD_PMC18 Analog
-
-
XTAL
-
-
-
-
XTAL32
VDD_VBAT1 Analog
8_CAP
XTAL32
1. The state immediately after RESET and before ROM firmware or software has executed.
2. FSGPIO = Failsafe GPIOs; STGPIO - Standard GPIOs
3. PD = internal pull-down enabled; PU = internal pull-up enabled; OD = open-drain
4. TAMPER is Hi-Z during VBAT domain POR and an input otherwise.
11 Revision History
The following table provides a revision history for this document.
The changes shown below represent the changes between the i.MX 7ULP datasheet for
silicon revision B1 (IMX7ULPIEC) and silicon revision B2 (IMX7ULPB2IEC).
Table 64. Revision History
Rev. No.
Date
Substantial Changes
0
04/2021
• Updated orderable part number for B2 silicon on the front page and this table
• Updated Figure 2.
• In this table, updated Nominal and Overdrive frequency for CM4.
• Added this table
• Added a row for B2 silicon revision in Table 3.
• Added i.MX 7ULP LDO Bypass versus LDO-enabled modes
Table continues on the next page...
108
NXP Semiconductors
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
Revision History
Table 64. Revision History (continued)
Rev. No.
Date
Substantial Changes
• In Table 5, updated parameters for real Time Domain (M4 domain) PMC 0 Register
Configuration Requirements and Application Domain (A7 domain) supply voltage
requirements for LDO Bypass modes .
• Updated value for open loop total deviation of IRC16M frequency at low voltage in
Table 9
• Added the section HS200 mode timing.
• Removed external channel leakage current spec from the section 12-bit ADC
electrical specifications
• Removed the section "Fuse definition of Speed Grading"
• Minor editorial changes
• Updated DDR frequency from 380.16 to 271.5 MHz throughout.
1
07/2021
• Updated the power-on hours from 2190 to 8760 in the footnote 9 of Table 5.
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
109
NXP Semiconductors
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Date of release: 07/2021 Document
identifier: IMX7ULPIECB2
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