MCM6343TS11R [NXP]
256KX16 STANDARD SRAM, 11ns, PDSO44, TSOP2-44;
| 型号： | MCM6343TS11R |
| 厂家： | 
NXP |
| 描述： | 256KX16 STANDARD SRAM, 11ns, PDSO44, TSOP2-44 输入元件 静态存储器 光电二极管 输出元件 内存集成电路 |
| 文件： | 总10页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6343/D
MCM6343
256K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6343 is a 4,194,304–bit static random access memory organized as
262,144 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes.
YJ PACKAGE
400 MIL SOJ
CASE 919–01
The MCM6343 is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB and UB) allow individual
bytes to be written and read. LB controls the lower bits DQL [7:0], while UB con-
trols the upper bits DQU [7:0].
TS PACKAGE
TSOP TYPE II
CASE 924A–02
The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package
and a 44–lead TSOP Type II package.
•
•
•
•
•
•
•
•
Single 3.3 V Power Supply
Fast Access Time: 10/11/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 200/195/190/180 mA Maximum, Active AC
Commercial (0°C to 70°C) and
PIN ASSIGNMENT
A
A
A
A
A
1
2
3
4
5
44
43
42
41
40
A
A
A
G
UB
Industrial Temperature (– 40 to 85°C) Options
E
DQL
DQL
DQL
DQL
6
39
38
37
36
35
LB
7
DQU
DQU
DQU
DQU
8
9
BLOCK DIAGRAM
10
OUTPUT
ENABLE
BUFFER
G
HIGH BYTE OUTPUT ENABLE
V
V
11
12
13
14
15
34
33
32
31
30
V
V
DD
SS
SS
DD
LOW BYTE OUTPUT ENABLE
DQL
DQL
DQL
DQU
DQU
DQU
HIGH
BYTE
OUTPUT
BUFFER
9
8
8
ADDRESS
BUFFERS
A*
9
ROW
COLUMN
DECODER DECODER
18
DQL
W
16
17
29
28
DQU
NC
HIGH
BYTE
WRITE
DRIVER
8
A
A
A
A
A
18
19
20
21
22
27
26
25
24
23
A
A
A
A
A
CHIP
ENABLE
BUFFER
E
8
SENSE
AMPS
256K x 16
16
BIT
WRITE
ENABLE
BUFFER
LOW
BYTE
OUTPUT
BUFFER
MEMORY
ARRAY
W
8
8
PIN NAMES
A [17:0] . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . Upper Byte Select
LB . . . . . . . . . . . . . . . . . . . Lower Byte Select
DQL [7:0] . . . . . . . . . . . . Data I/O, Low Byte
DQU [7:0] . . . . . . . . . . . Data I/O, High Byte
LOW
BYTE
WRITE
DRIVER
8
LB
UB
8
BYTE
ENABLE
BUFFER
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
* Address (A) and Data (DQU, DQL) signals are assigned by customer, such that
PCB layout is optimized for a given design.
V
DD
V
SS
. . . . . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
REV 8
2/2/99
Motorola, Inc. 1999
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TRUTH TABLE (X = Don’t Care)
E
H
L
L
L
L
L
L
L
L
G
X
H
X
L
W
X
H
X
H
H
H
L
LB
X
X
H
L
UB
X
X
H
H
L
Mode
V
Current
DQL [7:0]
High–Z
High–Z
High–Z
DQU [7:0]
High–Z
High–Z
High–Z
High–Z
DD
Not Selected
Output Disabled
Output Disabled
Low Byte Read
High Byte Read
Word Read
I
, I
SB1 SB2
I
I
I
I
I
I
I
I
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
D
out
L
H
L
High–Z
D
D
out
out
L
L
D
out
X
X
X
L
H
L
Low Byte Write
High Byte Write
Word Write
D
High–Z
in
L
H
L
High–Z
D
D
in
in
L
L
D
in
ABSOLUTE MAXIMUM RATINGS (See Notes)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.
Rating
Symbol
Value
Unit
Supply Voltage
V
DD
– 0.5 to 4.6
V
V
Voltage on Any Pin
V
in
– 0.5 to V + 0.5
DD
Output Current per Pin
Package Power Dissipation
Temperature Under Bias
I
± 20
TBD
mA
W
out
P
D
Commercial
Industrial
T
bias
– 10 to 85
– 45 to 90
°C
Operating Temperature
Commercial
Industrial
T
A
0 to 70
– 45 to 85
°C
°C
Storage Temperature
NOTES:
T
stg
– 55 to 150
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended
periods of time could affect device reliability.
2. All voltages are referenced to V
.
SS
3. Power dissipation capability will be dependent upon package characteristics and
use environment.
PRODUCT CONFIGURATIONS
Power Supply
Part Number
Commercial
Industrial
+ 10%, – 5%
± 10%
MCM6343YJ10B & MCM6343YJ10BR
MCM6343YJ11 & MCM6343YJ11R
MCM6343YJ12 & MCM6343YJ12R
MCM6343YJ15 & MCM6343YJ15R
MCM6343TS10B & MCM6343TS10BR
MCM6343TS11 & MCM6343TS11R
MCM6343TS12 & MCM6343TS12R
MCM6343TS15 & MCM6343TS15R
SCM6343YJ11A & SCM6343YJ11AR
SCM6343YJ12A & SCM6343YJ12AR
SCM6343YJ15A & SCM6343YJ15AR
SCM6343TS11A & SCM6343TS11AR
SCM6343TS12A & SCM6343TS12AR
SCM6343TS15A & SCM6343TS15AR
MCM6343
2
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DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to 70°C, V
= 3.3 V + 0.3 V, – 0.15 V for 10 ns Device)
DD
A
DD
(T = – 40 to 85°C for Industrial Temperature Option)
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3
Typ
3.3
—
Max
Unit
V
Power Supply Voltage
V
DD
3.6
Input High Voltage
V
IH
2.2
V
V
+ 0.3**
DD
Input Low Voltage
V
IL
—
0.8
V
– 0.5*
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IL
**V (max) = V
IL
+ 0.3 V dc; V (max) = V + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DD
IH
DD
IH
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1
Unit
µA
µA
V
Input Leakage Current (All Inputs, V = 0 to V
)
I
lkg(I)
in
DD
Output Leakage Current (E = V , V
= 0 to V
)
I
lkg(O)
—
± 1
IH out
DD
Output Low Voltage
Output High Voltage
(I
= + 4 mA)
= + 100 µA)
V
OL
—
0.4
OL
(I
V
+ 0.2
OL
SS
(I
= – 4 mA)
= – 100 µA)
V
OH
2.4
—
V
OH
(I
V
– 0.2
OH
DD
POWER SUPPLY CURRENTS
– 40 to
85°C
Parameter
Symbol
0 to 70°C
Unit
AC Active Supply Current
MCM6343–10: t
MCM6343–11: t
MCM6343–12: t
MCM6343–15: t
= 10 ns
= 11 ns
= 12 ns
= 15 ns
I
200
195
190
180
260
255
250
240
mA
AVAV
AVAV
AVAV
AVAV
CC
(I
out
= 0 mA, V
= Max)
CC
AC Standby Current (V
CC
= Max, E = V
,
MCM6343–10: t
MCM6343–11: t
MCM6343–12: t
MCM6343–15: t
= 10 ns
= 11 ns
= 12 ns
= 15 ns
I
45
40
35
30
55
55
55
50
mA
mA
IH
No Other Restrictions on Other Inputs)
AVAV
AVAV
AVAV
AVAV
SB1
CMOS Standby Current (E ≥ V
– 0.2 V, V ≤ V
in
+ 0.2 V or ≥ V – 0.2 V)
CC
I
8
10
CC
SS
SB2
(V
CC
= Max, f = 0 MHz)
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
—
Max
Unit
pF
Address Input Capacitance
Control Input Capacitance
Input/Output Capacitance
C
C
6
6
8
in
in
—
pF
C
—
pF
I/O
MCM6343
3
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to 70°C, V
= 3.3 V + 0.3 V, – 0.15 V for 10 ns Device)
CC
A
DD
(T = – 40 to 85°C for Industrial Temperature Option)
A
Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V
Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM6343–10
MCM6343–11
MCM6343–12
MCM6343–15
Parameter
Read Cycle Time
Symbol
Unit
ns
Notes
Min
10
—
—
—
3
Max
—
Min
11
—
—
—
3
Max
—
11
11
4
Min
12
—
—
—
3
Max
—
Min
15
—
—
—
3
Max
—
t
4
AVAV
Address Access Time
Enable Access Time
t
10
10
4
12
12
4
15
15
5
ns
AVQV
t
ns
5
ELQV
GLQV
AXQX
Output Enable Access Time
t
t
ns
Output Hold from Address
Change
—
—
—
—
ns
Enable Low to Output Active
t
3
0
—
—
3
0
—
—
3
0
—
—
3
0
—
—
ns
ns
6, 7, 8
6, 7, 8
ELQX
Output Enable Low to Output
Active
t
GLQX
Enable High to Output High–Z
t
0
0
5
4
0
0
6
4
0
0
6
4
0
0
7
5
ns
ns
6, 7, 8
6, 7, 8
EHQZ
GHQZ
Output Enable High to Output
High–Z
t
Byte Enable Access Time
t
—
0
5
—
0
6
—
0
6
—
0
7
ns
ns
BLQV
Byte Enable Low to Output
Active
t
—
—
—
—
6, 7, 8
6, 7, 8
BLQX
Byte High to Output High–Z
t
0
5
0
6
0
6
0
7
ns
BHQZ
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. Device is continuously selected (E ≤ V , G ≤ V ).
IL IL
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, t
to device.
max
t
min, and t
max
t min, both for a given device and from device
GLQX
EHQZ
ELQX
GHQZ
7. This parameter is sampled and not 100% tested.
8. Transition is measured ± 200 mV from steady–state voltage.
TIMING LIMITS
+3.3 V
317
Thetable of timing values shows either a minimum
or amaximumlimitforeachparameter. Inputrequire-
mentsare specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that
much time. On the other hand, responses from the
memory are specified from the device point of view.
Thus, the access time is shown as a maximum since
the device never provides data later than that time.
Ω
R
= 50 Ω
L
OUTPUT
351
OUTPUT
Ω
5 pF
Z
= 50 Ω
0
V
= 1.5 V
L
(a)
(b)
Figure 1. AC Test Loads
MCM6343
4
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2000
1600
1200
800
400
0
20
40
60
80
100
C
(pF)
load
Figure 2. Typical I/O Derating Curve
READ CYCLE 1 (See Note 8)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Note 4)
t
AVAV
A (ADDRESS)
t
AVQV
t
ELQV
E (CHIP ENABLE)
t
EHQZ
t
ELQX
G (OUTPUT ENABLE)
t
t
GHQZ
GLQV
t
GLQX
LB, UB (BYTE ENABLE)
Q (DATA OUT)
t
t
BHQZ
BLQV
t
BLQX
DATA VALID
MCM6343
5
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WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
MCM6343–10
MCM6343–11
MCM6343–12
MCM6343–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
11
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
4
AVAV
Address Setup Time
t
—
—
—
—
ns
AVWL
Address Valid to End of Write
t
7
—
8
—
8
—
10
10
—
ns
AVWH
AVWH
Address Valid to End of Write
(G High)
t
8
—
9
—
9
—
—
ns
Write Pulse Width
t
t
9
8
—
—
10
9
—
—
10
9
—
—
12
10
—
—
ns
ns
WLWH
WLEH
t
Write Pulse Width (G High)
WLWH
t
WLEH
DVWH
WHDX
Data Valid to End of Write
Data Hold Time
t
t
5
0
0
3
0
—
—
5
6
0
0
3
0
—
—
6
6
0
0
3
0
—
—
6
7
0
0
3
0
—
—
7
ns
ns
ns
ns
ns
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
5, 6, 7
5, 6, 7
WLQZ
t
—
—
—
—
—
—
—
—
WHQX
t
WHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
5. This parameter is sampled and not 100% tested.
6. Transition is measured ± 200 mV from steady–state voltage.
7. At any given voltage and temperature, t
max < t
min both for a given device and from device to device.
WLQZ
WHQX
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLEH
WLWH
t
W (WRITE ENABLE)
t
t
WHDX
AVWL
LB, UB (BYTE ENABLE)
t
DVWH
D (DATA IN)
DATA VALID
HIGH–Z
t
WLQZ
HIGH–Z
Q (DATA OUT)
t
WHQX
MCM6343
6
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WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
MCM6343–10
MCM6343–11
MCM6343–12
MCM6343–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
11
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
4
AVAV
Address Setup Time
t
—
—
—
—
ns
AVEL
Address Valid to End of Write
t
9
—
10
9
—
10
9
—
12
10
—
ns
AVEH
AVEH
Address Valid to End of Write
(G High)
t
8
—
—
—
—
ns
Enable to End of Write
t
t
9
8
—
—
10
9
—
—
10
9
—
—
12
10
—
—
ns
ns
5, 6
5, 6
ELEH,
ELWH
Enable to End of Write (G High)
t
t
ELEH,
ELWH
Data Valid to End of Write
Data Hold Time
t
5
0
0
—
—
—
6
0
0
—
—
—
6
0
0
—
—
—
7
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
t
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
6. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
t
t
AVEH
EHAX
t
ELEH
E (CHIP ENABLE)
t
t
AVEL
ELWH
W (WRITE ENABLE)
LB, UB (BYTE ENABLE)
t
t
EHDX
DVEH
D (DATA IN)
DATA VALID
HIGH–Z
Q (DATA OUT)
MCM6343
7
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WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3)
MCM6343–10
MCM6343–11
MCM6343–12
MCM6343–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
11
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
4
AVAV
Address Setup Time
t
—
—
—
—
ns
AVBL
Address Valid to End of Write
t
9
—
10
9
—
10
9
—
12
10
—
ns
AVBH
AVBH
Address Valid to End of Write (G
High)
t
8
—
—
—
—
ns
Byte Pulse Width
t
t
9
8
—
—
10
9
—
—
10
9
—
—
12
10
—
—
ns
ns
BLWH
BLEH
t
Byte Pulse Width (G High)
BLWH
t
BLEH
DVBH
BHDX
Data Valid to End of Write
Data Hold Time
NOTES:
t
t
5
0
—
—
6
0
—
—
6
0
—
—
7
0
—
—
ns
ns
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
t
AVAV
A (ADDRESS)
t
AVBH
E (CHIP ENABLE)
t
t
AVBL
BLEH
BLWH
t
LB, UB (BYTE ENABLE)
t
BHDX
W (WRITE ENABLE)
D (DATA IN)
t
DVBH
DATA VALID
HIGH–Z
HIGH–Z
Q (DATA OUT)
MCM6343
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ORDERING INFORMATION
(Order by Full Part Number)
MCM 6343 XX XX
X X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel, Blank = Rails)
Supply Tolerance (A = + 10%, – 10% Industrial,
B = + 10%, – 5% Commercial
C = + 10%, – 5% Industrial
Blank = + 10%, – 10% Commercial)
Speed (10 = 10 ns, 11 = 11 ns, 12 = 12 ns,
15 = 15 ns)
Package (YJ = 400 mil SOJ, TS = TSOP Type II)
Full Commercial Part Numbers — MCM6343YJ10B MCM6343YJ10BR
MCM6343TS10B MCM6343TS10BR
MCM6343YJ11
MCM6343YJ12
MCM6343YJ15
MCM6343YJ11R
MCM6343YJ12R
MCM6343YJ15R
MCM6343TS11
MCM6343TS12
MCM6343TS15
MCM6343TS11R
MCM6343TS12R
MCM6343TS15R
Full Industrial Part Numbers — SCM6343YJ11A
SCM6343YJ12A
SCM6343YJ11AR
SCM6343YJ12AR
SCM6343YJ15AR
SCM6343TS11A
SCM6343TS12A SCM6343TS12AR
SCM6343TS15A SCM6343TS15AR
SCM6343TS11AR
SCM6343YJ15A
PACKAGE DIMENSIONS
YJ PACKAGE
44–LEAD
400 MIL SOJ
CASE 919–01
44
23
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
E1
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 PER END. DIMENSION
E1 DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010
PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005. THE DAMBAR INTRUSION(S)
SHALL NOT REDUCE THE SHOULDER WIDTH TO
LESS THAN 0.001 BELOW b1 MIN.
1
22
B
A
D
44X b1
L
0.007
C A B
42X
e
A
A3
SEATING
PLANE
A
e /2
0.004
C
C
44X b
0.007
M
C
A
B
C
INCHES
DIM
A
A1
A2
A3
b
b1
D
E
MIN
MAX
0.148
–––
0.128
0.025
0.082
0.035
0.015
0.026
1.120
0.435
0.395
E
–––
0.045
0.020
0.032
1.130
0.445
0.405
M
0.007
A B
A
A2
E1
E2
e
0.370 BSC
0.050 BSC
0.030 0.040
44X R R1
R1
E2 /2
A1
E2
VIEW A–A
0.015
B
22 ZONES 2X
MCM6343
9
MOTOROLA FAST SRAM
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Freescale Semiconductor, Inc.
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
VIEW A
B
44
23
E1
A
A
1
22
A2
A
A
D
22X E
M
0.2
C B
NOTES:
44X
1. DIMENSIONINS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETER.
0.004 (0.1)
C
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.15 PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58.
SEATING
PLANE
4X e /2
C
42X
e
MILLIMETERS
DIM
A
A1
A2
b
MIN
–––
MAX
1.20
0.15
1.05
0.45
0.21
18.54
0.05
0.95
0.30
0.12
18.28
c
c
D
e
E
E1
L
0.80 BSC
A1
b
11.56
10.03
0.40
0
11.96
10.29
0.60
5
M
0.2
C B
L
SECTION A–A
VIEW A
40 PLACES
ROTATED 90 CLOCKWISE
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datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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