MCM69C233TQ15 [NXP]
IC,CAM,4KX64,CMOS,QFP,100PIN,PLASTIC;
| 型号： | MCM69C233TQ15 |
| 厂家： | 
NXP |
| 描述： | IC,CAM,4KX64,CMOS,QFP,100PIN,PLASTIC 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69C233/D
MCM69C233
SCM69C233
4K x 64 CAM
The MCM69C233 is a flexible content–addressable memory (CAM) that can
contain 4096 entries of 64 bits each. The widths of the match field and the output
field are programmable, and the match time is designed to be 210 ns. As a result,
the MCM69C233 is well suited for datacom applications such as Virtual Path
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C233 is
user defined, with a trade–off between the time between the match request rate
and the rate of new entries added to the CAM.
TQ PACKAGE
TQFP
CASE 983A–01
•
•
•
•
•
•
•
4096 Entries
210 ns Match Time
Mask Register to “Don’t Care” Selected Bits
Depth Expansion by Cascading Multiple Devices
66 MHz Maximum Clock Rate
Programmable Match and Output Field Widths
Concurrent Matching of Virtual Path Circuits and Virtual Connection
Circuits in ATM Mode
•
•
•
•
•
•
Separate Ports for Control and Match Operations
300 ns Insertion Time if 1 of 12 Entry Queue Locations is Empty
18 ms Initialization Time After Fast Insertion (at Power–Up Only)
Single 3.3 V ±5% Supply
IEEE Standard 1149.1 Test Por(JTAG)
100–Pin TQFP Package
Related Products
— MCM69C432, MCM69C232, MCM69C433 (CAMs)
CONTROL PORT
MATCH PORT
12 x 64
ENTRY QUEUE
MQ31 – MQ0
A2 – A0
DQ15 – DQ0
STATUS/
4K x 64
CAM
TABLE
K
G
SEL
CONTROL
LOGIC
LH/SM
LL
WE
IRQ
DTACK
MC
MS
VPC
INPUT REG
RESET
KMODE
REV 3
6/11/01
Motorola, Inc. 2001
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PIN ASSIGNMENT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
MQ9
MQ8
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MQ22
MQ23
2
3
4
5
6
7
8
9
V
V
SS
SS
V
V
DD
DD
MQ7
MQ6
MQ5
MQ4
MQ24
MQ25
MQ26
MQ27
V
SS
V
SS
V
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DD
MQ3
MQ2
MQ1
MQ0
MQ28
MQ29
MQ30
MQ31
V
SS
V
SS
V
DD
V
DD
DQ15
DQ14
DQ13
DQ12
MC
VPC
MS
G
V
SS
V
SS
V
V
DD
DD
DQ11
DQ10
DQ9
DTACK
IRQ
RESET
TDO
DQ8
V
V
DD
DD
V
V
SS
SS
DQ7
DQ6
TCK
TMS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MCM69C233•SCM69C233
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PIN DESCRIPTIONS
Pin Locations
42 – 44
Symbol
A2 – A0
Type
Input
Output
I/O
Description
3–bit control port address bus.
58
DTACK
Control port data transfer acknowledge (Open Drain).
16–bit bidirectional control port data bus.
17 – 20, 23 – 26,
29 – 32, 35 – 38
DQ15 – DQ0
61
57
39
47
89
G
IRQ
Input
Output
Input
Asynchronous Output Enable control of MQ31 – MQ0.
Control Port Interrupt (Open Drain).
Interface Clock, max frequency of 66 MHz.
See Note.
K
KMODE
LH/SM
Input
Input
Latch High/Start Match. Initiates match sequence on match data present on
MQ31 – MQ0.
92
64
62
LL
MC
Input
Output
Output
I/O
Latch Low. Latches low order bits if match width is > 32 bits.
Match Complete (Open Drain).
MS
Match Successful (Open Drain).
67 – 70, 73 – 76,
79 – 82, 85 – 88,
93 – 96, 99, 100,
1, 2, 5 – 8, 11 – 14
MQ31 – MQ0
32–bit common I/O CAM data. Used for input of match RAM and data RAM
values.
56
46
52
50
55
51
49
63
RESET
SEL
Input
Input
Resets chip to a known state.
Control Port Chip Select, active low.
Test Clock, part of JTAG interface.
Test Data In, part of JTAG interface.
Test Data Out, part of JTAG interface.
Test Mode Select, part of JTAG interface.
TAP Reset part of JTAG interface.
TCK
Input
TDI
Input
TDO
TMS
TRST
VPC
Output
Input
Input
Output
Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has
occurred (Open Drain).
45
WE
Input
Control Port Write Enable.
4, 10, 16, 22, 27, 33,
41, 48, 54, 59, 65, 71,
77, 84, 91, 97
V
DD
Supply
Power Supply: 3.3 V ±5%.
3, 9, 15, 21, 28, 34,
40, 53, 60, 66, 72,
78, 83, 90, 98
V
SS
Supply
Ground.
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
K
RESET
KMODE
MCM69C233•SCM69C233
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ABSOLUTE MAXIMUM RATINGS (See Note 1)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
thatnormalprecautionsbetakentoavoidappli-
cation of any voltage higher than maximum
rated voltages to this high–impedance circuit.
Rating
Symbol
Value
Unit
V
Supply Voltage (see Note 2)
V
DD
4.6
Voltage Relative to V
SS
(see Note 2)
V
in
–0.5 to V
DD
+ 3 V
V
Output Current per Pin
I
±20
mA
W
out
Package Power Dissipation (see Note 3)
P
D
—
Temperature Under Bias (see Note 3)
Commercial
T
bias
°C
–10 to 85
–40 to 85
Industrial
Operating Temperature (see Note 4)
Commercial
T
°C
°C
A
0 to 70
–40 to 85
Industrial
Storage Temperature
NOTES:
T
stg
–55 to 125
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextende
periods of time could affect device reliability.
2. All voltages are referenced to V
.
SS
3. Powerdissipationcapabilitywillbedependentuponpackagecharacteristicsanduse
environment. See Package Thermal Characteristics.
4. ConsultJunctiontoAmbientThermalCharacteristicstablefordetailsandconditions.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ±5%, T < 120°C, Unless Otherwise Noted)
DD
J
RECOMMENDED OPERATING CONITIONS (Voltages Referenced to V
= 0 V)
SS
Parameter
Power Supply Voltage
Symbol
Min
3.1
Typ
3.3
—
0
Max
3.5
Unit
V
V
DD
Operating Temperature (Junction)
Input Low Voltage
T
J
—
120
0.8
°C
V
V
–0.5*
2.0
IL
IH
Input High Voltage
V
3
5.5
V
* V (min) = –3.0 V ac (pulse width
IL
20 ns).
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
—
Max
200
±1
Unit
mA
µA
µA
V
Active Power Supply Current
I
DDA
Input Leakage Current (0 V
Output Leakage Current (0 V
V
V
)
I (I)
lkg
—
in
DD
V
V
)
I (O)
lkg
—
±1
in
DD
Output Low Voltage (I
= 8 mA)
V
OL
—
0.4
—
OL
Output High Voltage (I
= –4 mA)
V
OH
2.4
V
OH
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
27.1
17
Unit
°C/W
°C/W
°C/W
Thermal Resistance Junction to Ambient (200 lfpm, 4 Layer Board) (Note 2)
Thermal Resistance Junction to Board (Bottom) (Note 3)
Thermal Resistance Junction to Case (Top) (Note 4)
NOTES:
R
θJA
R
θJB
R
θJC
9
1. RAM junction temperature is a function of on–chip power dissipation, package thermal impedance, mounting site temperature, and
mounting site thermal impedance.
2. Per SEMI G38–87.
3. Indicates the average thermal impedance between the die and the mounting surface.
4. Indicates the average thermal impedance between the die and the case top surface. Measured via the cold plate method (MIL SPEC–883
Method 1012.1).
MCM69C233•SCM69C233
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CAPACITANCE (Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
—
Max
5
Unit
pF
Input Capacitance
I/O Capacitance
C
in
C
—
8
pF
I/O
JUNCTION TO AMBIENT THERMAL CHARACTERISTICS
Board
1 Layer
1 Layer
1 Layer
4 Layer
4 Layer
4 Layer
Air (LFPM)
θ
(°C/W)
Maximum Ambient Temperature (°C)
JA
0
40.1
55.8
64.4
68.7
71.1
76.6
79.0
200
400
0
34.7
32.1
30.5
27.1
25.6
200
400
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ±5%, T < 120°C, Unless Otherwise Noted)
DD
J
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
CONTROL PORT TIMINGS
(Voltages Referenced to V
= 0 V, Max’s are t
Dependent and Listed Values are for t
= 15 ns)
SS
KHKH
KHKH
Parameter
Symbol
Min
0
Max
—
—
—
—
—
—
—
—
—
20
—
—
—
—
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Address Valid to SEL Low
t
AVSL
DTACK Low to Address Invalid
Data Valid to Select Low
t
0
DTLAX
t
0
DVSL
DTACK Low to Data Invalid
Output Valid to DTACK Low
WE Valid to Select Low
t
0
DTLDX
t
2
QVDTL
t
0
WVSL
DTACK Low to WE High
t
0
DTLWH
WE High to Output Active
Select Low to DTACK Low
Select High to DTACK High
DTACK Low to IRQ Low
t
2
WHQX
SLDTL
SHDTH
t
10
10
10
20
0
1
t
t
DTLIL
IRQ Low to IRQ High
t
ILIH
DTACK Low to Select High
DTACK High to Select Low
Address Valid to Output Valid
Select High to Output High Impedance
t
DTLSH
t
0
DTHSL
t
—
—
AVQV
t
8
SHQZ
RESET Low to RESET High
NOTE:
t
2 x t
KHKH
—
RLRH
1. DTACK is delayed when a write is attempted during certain operations. See Functional Description.
MCM69C233•SCM69C233
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MATCH PORT TIMINGS
(Voltages Referenced to V
= 0 V, Max’s are t
KHKH
Dependent and Listed Values are for t
= 15 ns)
Symbol
SS
KHKH
Parameter
Min
15
6
Max
250
244
244
—
Unit
ns
Clock Cycle Time
Clock High Time
Clock Low Time
t
KHKH
t
ns
KHKL
KLKH
t
6
ns
Clock High to LHSM or LL Low
Clock High to LHSM or LL High
t
3
ns
LLKH
t
1
—
ns
KHLH
MQ Input Data Setup Time to Clock High
Clock High to Match Data Hold Time
Clock High to MQ Valid
Clock High to MC High
t
t
t
t
8
—
ns
MQVKH
KHMQX
KHMQV
KHMCH
2
—
ns
—
—
—
—
—
—
—
3.8
—
18
15
10
7
ns
ns
Clock High to MC Low
t
ns
KHMCL
Clock High to MS Low
t
12
12
15
12
—
ns
KHMSL
KHMSH
Clock High to MS High
t
ns
Clock High to VPC Low
Clock High to VPC High
G Low to MQ Active
t
ns
KHVPL
KHVPH
GLMQX
GHMQZ
t
ns
t
ns
G High to MQ High–Z
t
7
ns
LH/SM Low to LH/SM Low
t
—
cycles
SMSM
R = 50 Ω
L
OUTPUT
Z = 50 Ω
0
V = 1.5 V
L
Figure 1. AC Test Loads
3.3 V
R
H
MCM69C233 OUTPUT PIN
FANOUT TO LOAD DEVICES
NOTES:
1. For IRQ, DTACK, MS, MC, and VPC; R = 200 Ω.
H
2. If multiple MCM69C233s are used, R should be placed as
H
close to the load devices as possible.
Figure 2. Pullup for Open Drain Outputs
MCM69C233•SCM69C233
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operations can then begin. A delete operation is provided to
remove stale data from the CAM table.
FUNCTIONAL DESCRIPTION
The MCM69C233 is a flexible CAM that can contain 4096
entries of 64 bits each. The widths of the match field and the
output field are programmable, and the match time is
designed to be 210 ns. As a result, the MCM69C233 is well
suited for datacom applications such as VPI/VCI translation
in ATM switches up to OC12 (622 Mbps) data rates and MAC
address lookup in Ethernet/Fast Ethernet bridges. The
match duty cycle of the MCM69C233 is determined by the
user, with a trade–off between the match request rate and
the rate of entries added to/deleted from the CAM. With the
minimum required 60 ns of idle time between matches, a typ-
ical value of 1627 insertions or deletions per second can be
made. See Figure 3 for a graph of the relationship between
insertion/deletion pairs and match duty cycle.
Several error codes are defined in the details of the
instruction set. When an error occurs, its corresponding code
is written into the error register and the error bit in the flag
register is set. The error bit is cleared and the error register is
set to FFFF by the next write to the operation register.
16
PROGRAMMING MODEL
Three types of registers are accessible through the
MCM69C233 control port: I/O registers, an operation reg-
ister, and result/condition code registers. Each register is
16 bits in length.
ADDRESS
In its basic operating mode, the MCM69C233 reads a data
input word through the MQ bus and compares it to all the
entries in its CAM table. The MC pin is always asserted after
the comparisons have been made. If a match is found, the
MS pin is asserted, and the data associated with the match-
ing entry is output on the MQ bus. If no match is found, the
MQ bus remains in a high–impedance state to facilitate
depth expansion via the cascading of multiple CAMs.
Before the basic operating mode can be entered, severa
start–up functions must be performed. First, the output width
and match width must be designated by setting the global–
mask register. Second, a choice must be made between
buffered–entry mode and fast–entry mode. Next, the 64–bit
match/output data pairs must be loaded into the table. De-
pending on the entry mode of choice, the table may have to
be initialized. Optionally, the “almost–full” point may be set to
provide warning of impending table overflow.
REGISTER NAME
BIT NUMBER
OFFSET
15
0
I/O REGISTER 0
0
I/O REGISTER 1
1
2
3
4
5
6
7
I/O REGISTER 2
I/O REGISTER 3
OPERATION REGISTER
FLAG REGISTER
ERROR CODE REGISTER
INTERRUPT REGISTER
The input bits to be compared are defined by the global–
mask register. The mask bits that are 0 correspond to the bits
that are used in the match operation.Typically, the bits that
are used in matching are the high order bits in the 64–bit
CAM table entries, and the bits that are used as outputs are
the low order bits. While any of the bits can be defined as
match bits, the low order 32 bits of an entry are always driven
on the MQ bus as output data.
The choice of entry mode is a trade–off between speed of
entry and latency before matching operations can begin. In a
typical application, the fast–entry mode will be used to load
the initial values into the CAM table. Subsequently, the
initialize–table operation, which takes 18 ms, must be
executed to establish the required linkages and relationships
among the entries. After match operations have begun, the
buffered–entry mode should be used to enter new values
dynamically; even one addition in fast–entry mode will dis-
able matching until the table is reinitialized. Table insertions
using the buffered–entry mode and the fast–entry mode
actually take the same amount of time unless the entry
queue is full. The capacity of the queue is 12 entries.
FLAG BIT DEFINITIONS
Bit 0: 1 = At least one interrupt enabled,
0 = No interrupts enabled
Bit 1: 1 = Last control port match successful,
0 = Last match unsuccessful
Bit 2: 1 = Table initialized, 0 = Table not initialized
Bit 3: 1 = Buffered–entry mode, 0 = Fast–entry mode
Bit 4: 1 = Entry queue empty,
0 = Entry queue not empty
Bit 5: 1 = Entry queue full, 0 = Entry queue not full
Bit 6: 1 = CAM table full, 0 = CAM table not full
Bit 7: 1 = Error condition set, 0 = No error
Bit 8: 1 = Table almost full, 0 = Table not almost full
Bit 9: 1 = ATM mode, 0 = Standard mode
Bit 10: 1 = Last operation complete, 0 = Not yet complete
ERROR CODES
FFFF
FFFD
FFFC
FFFB
FFFA
FFF9
FFF8
No error
After the entry mode choice is made, the table can be
loaded. Each 64–bit entry is constructed by writing a 16–bit
value to each of the 4 I/O registers in the control port of the
MCM69C233. The insertion can then be processed. After all
the start–up entries have been loaded into the CAM table,
the initialization operation is run if required. Normal matching
Invalid instruction
Queue not empty for read
Table not initialized
Queue not empty for write
CAM table full
Entry queue full
MCM69C233•SCM69C233
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INTERRUPT BIT DEFINITIONS
INSTRUCTION SET DETAILS
Bit 0: 1 = Enable interrupt on insert with full entry
queue
The MCM69C233 is prepared for match operations by
writing data and instructions via the control port. In the gen-
eral case, required data is loaded into I/O registers 0 – 3,
then an instruction is issued by writing an operation code to
the operation register. As a result of running an instruction,
the CAM table can be modified, bit(s) can be set in the flag
register, error codes can be returned in the error code regis-
ter, and an interrupt can be generated if enabled. For a par-
ticular condition to generate an interrupt, the interrupt
register bit specific to that condition must be set. The user
should verify that the last operation complete bit (bit 10) of
the flag register is set before executing the next instruction, if
the instruction just executed modifies I/O registers. See the
Simultaneous Port Operations section for any exceptions.
Bit 1: 1 = Enable interrupt on insert with full table
Bit 2: 1 = Enable interrupt on completion of
CHECK–FOR–VALUE instruction
Bit 3: 1 = Enable interrupt on completion of
INITIALIZE–TABLE instruction
Bit 4: 1 = Enable interrupt on failed attempt to enter
fast–entry mode
Bit 5: 1 = Enable interrupt on CAM table reaching
almost–full point
Bit 6: 1 = Enable interrupt on fast read with non–empty
queue
Bit 7: 1 = Enable interrupt on illegal instruction
Table 1. MCM69C233 Operation Summary
Operation
INSERT VALUE
Description
OP Code (Base 16)
Loads a new entry into the CAM table
Removes an entry from the CAM table
Runs a match cycle via the control port
Prepares CAM table for matching
0000 or 000F
0001 or 000E
0006
DELETE VALUE
CHECK FOR VALUE
INITIALIZE TABLE
000B
FAST–ENTRY MODE
BUFFERED–ENTRY MODE
Seects entry mode suited for initial CAM table load
0004
Selects entry mode suited for simultaneous loading
and matching
0005
SET ATM MODE
Enter mode that provides concurrent VPC/VCC
search
0008
RETURN ENTRY COUNT
Determines number of entries in CAM
0003
SET GLOBAL–MASK REGISTER
Determines match bits to be checked in a match
operation
0002 or 000D
SET ALMOST–FULL POINT
SET FAST–READ REGISTER
Defines CAM almost–full condition
0007
0009
Defines table entry that is output by the fast–read
operation
FAST READ
Outputs one CAM table entry
000A
INSERT VALUE
and the error–condition flag (bit 7) is set in the flag register.
(The table–full condition is indicated by bit 6 of the flag reg-
ister being set.) An interrupt is generated, if enabled by bit 1
of the interrupt register being set.
Only one entry is allowed for a given match pattern. If an
entry is made in the table that duplicates an existing match
pattern, it will overwrite the entry already in the CAM table, if
the CAM is in buffered–entry mode. The user must ensure
that no entries with the same match pattern are inserted in
fast–entry mode.
This instruction is used to load a new match/output value
into the CAM. The contents of I/O registers 0 – 3 are con-
catenated to create the 64–bit value. Bit 15 of register 3 is the
most significant bit, and bit 0 of register 0 is the least signifi-
cant bit.
If the MCM69C233 is in the buffered–entry mode, the
resulting 64–bit value is written to the first available location
in the entry queue, and is immediately available for match-
ing. If a buffered insert–value instruction is attempted when
the entry queue is full (indicated by bit 5 of the flag register =
DELETE VALUE
1), no value is written, an error code of FFF8 is returned in
16
the error code register, and the error–condition flag (bit 7) is
set in the flag register. An interrupt is generated, if enabled
by bit 0 of the interrupt register being set.
If the MCM69C233 is running in the fast–entry mode, the
concatenated 64–bit value is written directly to the CAM
array. If an insert–value instruction is attempted when in
fast–entry mode and the table is full, no value is written, an
This instruction is used to remove a match/output value
from the CAM. The contents of I/O registers 0 – 3 are con-
catenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit. The bits that
have a 0 in the corresponding bit of the global–mask register
are used to find a matching entry in the CAM table. If such an
entry is found, it is invalidated. Note that any bit that is not a
match bit as defined by the mask register is ignored for this
error code of FFF9 is returned in the error code register,
16
MCM69C233•SCM69C233
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operation. The operation of the MCM69C233 guarantees
interrupt is generated if enabled by bit 4 of the interrupt
register.
If this mode is used to enter data, the initialize–table opera-
tion must be executed before matching operations can be-
gin. The entry–mode bit and the table–initialized bit of the
flag register (bit 3) are cleared by this operation.
that no more than one matching entry can exist in the table,
unless they were accidently loaded using fast–entry mode.
This must be avoided by the user, as the results of subse-
quent matches and deletes will be undefined.
Example: I/O Register 0 =
I/O Register 1 =
3020
0000
543A
16
16
16
BUFFERED–ENTRY MODE
I/O Register 2 =
I/O Register 3 =
Concatenated value = FE55543A00003020
FE55
16
This instruction is used to enter the buffered–entry mode.
When the MCM69C233 is in this mode, insert–value and
delete–value operations utilize the entry queue. This mode
can be entered at any time. Table entries are available for
match operations immediately, without running the initialize–
table operation, if all entries are made in this mode. Note that
if both the buffered–entry and fast–entry modes have been
used to input data, none of the entries are available for
matching until the initialize–table operation is executed. Con-
flicting table and queue values are resolved in favor of the
latest entry in the queue. For example, if there is an entry in
the CAM, a corresponding delete–entry in the queue, and a
later insert–entry in the queue (all with the same match data),
the queued insert–entry will return a match value.
16
Global–Mask Register = C0000000FFFFFFFF
Of the high–order 32 bits, the rightmost 30 bits
16
are cared by the global–mask register. Therefore,
the MCM69C233 will delete an entry, if it exists,
which has a value of 3E55543A in bits 61 – 32.
16
CHECK FOR VALUE
This instruction checks for a matching value in the CAM
table via the control port. The contents of I/O registers 0 – 3
are concatenated, with bit 15 of register 3 as the most signifi-
cant bit, and bit 0 of register 0 as the least significant bit. The
bits that have a 0 in the corresponding bit of the global–mask
register are used to find a matching entry in the CAM table. I
such an entry is found, the last–match–successful bit of the
flag register is set. In addition, the matching entry is written to
I/O registers 0 – 3, with bit 15 of register 3 as the most signifi-
cant bit, and bit 0 of register 0 as the least significant bit
If no match is found, the last–match–successful bit is
cleared. An interrupt is generated regardless of the result, if
enabled by bit 2 of the interrupt register, when the operation
has been completed. The operation of the MCM69C233
guarantees that no more than one matching entry can exist
in the table. If uninterrupted by match port activity, the check
for value instruction will finish in 16 clock cycles. NOTE: If
both the control port and matching port are utilized simulta-
neously, see the Simultaneous Port Operations section.
RETURN ENTRY COUNT
This operation is used to determine the number of valid
entries in the MCM69C233. The value is returned in I/O reg-
ister 0, and reflects the sum of the number of valid entries in
the CAM table and the inserts in the entry queue.
SET GLOBAL–MASK REGISTER
This operation is used to indicate the bits to be used in per-
forming matches. A 1 indicates that a bit should be ignored in
the match operation, while a 0 indicates that a bit should be
used in the match operation.
When this operation is executed, the contents of I/O regis-
ters 0 – 3 are concatenated, with bit 15 of register 3 as the
most significant bit, and bit 0 of register 0 as the least signifi-
cant bit. The resulting 64–bit value is written to the global–
mask register.
INITIALIZE TABLE
If fast–entry mode has been used to load the CAM table,
the initialize–table operation must be used to establish the
needed relationships and linkages between the entries in the
table before matching can proceed. Upon completion, this
operation sets the table–initialized bit in the flag register, and
generates an interrupt if enabled by bit 3 of the interrupt reg-
ister. It also sets the buffered–entry mode bit in the flag regis-
ter. This operation makes the programming model’s registers
read–only for up to 18 ms after the acknowledgment of the
op code write cycle.
This operation should be executed before entering
required values into the CAM table. Otherwise, the initialize–
table instruction must be executed if the global–mask regis-
ter is changed after data is loaded into the CAM.
SET ALMOST–FULL POINT
This operation is used to define the “almost–full” condition
in the CAM table. The 12 low–order bits of I/O register 0 are
copied to the almost–full–point register. If an entry is added
to the MCM69C233 (via the insert–value operation) that
causes the valid–entry count to equal the almost–full point,
then bit 8 of the flag register is set, and an interrupt is gener-
ated if enabled by bit 5 of the interrupt register. The value of
the almost–full register can be changed dynamically during
match operations. For example, it could first be set to 2048 to
generate an interrupt when the table is half full. When that
point is reached, the register could be reprogrammed to
3072 to provide warning that the table has become three–
quarters full. The almost–full interrupt is generated, if
enabled, based on the number of entries in the CAM table.
Entries in the queue are not included in the count.
FAST–ENTRY MODE
This instruction is used to enter the fast–entry mode.
When the MCM69C233 is in this mode, insert–value opera-
tions bypass the entry queue and write new table entries
directly to the CAM table. The fast–entry mode can only be
entered while the entry queue is empty, as reflected by the
queue–empty flag being set (bit 4 of the flag register). If this
operation is attempted while the entry queue is not empty,
the value FFFA
is written to the error code register, the
error–condition flag (bit 7) is set in the flag register, and an
16
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SET FAST–READ REGISTER VALUE
the VCC is not in the table, but a VPC with that VPI is in the
table, the VPC will be deleted.
This operation defines the table address that is output by
the fast–read operation. The least significant 12 bits of I/O
register 0 are copied to the fast–read register. The queue
must be empty when this instruction is executed.
The fast–read instruction can only be executed while the
entry queue is empty, as reflected by the queue–empty flag
being set (bit 4 of the flag register). If this operation is at-
tempted while the entry queue is not empty, the value
The CAM table should never contain, simultaneously, a
VCC entry and VPC entry with matching VPIs. Violation of
this requirement may lead to unpredictable behavior.
Bits 60 – 63 may be used for matching in ATM mode if the
application requires extra bits. The use of bits 0 – 31 for
matching is not supported in ATM mode.
MATCH DUTY CYCLE
FFFC is written to the error code register, the error–condi-
16
At 66 MHz, the MCM69C233 completes a match 210 ns,
or 14 clock cycles, after assertion of the SM signal.
However, if entries need to be added to or deleted from the
CAM, idle time is needed between match output and match
requests for control port insertions and deletions. At 66 MHz,
the match duty cycle should be defined at least at 18 clock
cycles (270 ns), leaving 2 clock cycles for insertions/
deletions. The additional clock cycles are used for holding
the match data on the MQ bus. Therefore, every 18 clock
cycles, when a match operation and data output are
competed, SM can be asserted.
Entries are stored from least value at the top of the table to
the highest value at the bottom. If an entry with a match data
value smaller than any other entry is continually added or
dropped from the table, worst–case scenario occurs causing
shifting of all other entries. The idle time, in terms of the
number cycles, needed to perform a worst–case insertion
and/or deletion is given by the formula 8192 x MDC / (MDC –
16) cycles, where MDC is the match duty cycles. For
example, if match requests are occurring every 18 clock
cycles:
tion flag (bit 7) is set in the flag register, and an interrupt is
generated if enabled by bit 7 of the interrupt register.
FAST READ
This operation is used to output the contents of one entry
in the CAM table. The fast–read register is used to specify
the appropriate entry, and is then auto–incremented. As a re-
sult, successive execution of multiple fast–read operations
will provide access to contiguous entries in the CAM table.
The CAM entry is copied to I/O registers 0 – 3, with bit 15
of register 3 as the most significant bit, and bit 0 of register 0
as the least significant bit.
The fast–read instruction can only be executed while the
entry queue is empty, as reflected by the queue–empty flag
being set (bit 4 of the flag register.) If this operation is at-
tempted while the entry queue is not empty, the value
FFFC is written to the error code register, the error–condi-
16
tion flag (bit 7) is set in the flag register, nd an interrupt is
generated if enabled by bit 7 of the intrrupt register.
SET ATM MODE
8192 x 18 clock cycles
= 73,728 clock cycles
18 clock cycles – 16
When the MCM69C233 is placed in ATM mode, it provides
simultaneous searching for virtual path circuits (VPCs) and
virtual connection circuits (VCCs). A VCC is detected when
both the VPI and the VCI of an incoming cell match an entry
in the CAM. A VPC match occurs when the VPI of an incom-
ing cell matches the VPI field of a CAM entry that has all 1s
as its VCI. A VPC match is signaled by the assertion of the
VPC pin along with the MS pin. At 66 MHz, a match is com-
pleted in 210 ns, whether the applied VPI/VCI belongs to a
VCC or a VPC.
The VCI match field must be defined as bits 32 – 47 of
each entry, and the VPI match data must occupy bits 48 – 59.
The VPI can be limited to bits 48 – 55, if the switch handles
only User–Network Interface (UNI) protocols. The mask reg-
ister should be used to “don’t care” any unused bits beyond
the VPI field. Entering ATM mode will set bit 9 of the flag reg-
ister.
At 66 MHz (15 ns per cycle)
= 0.00110592 sec per insert or deletion.
If both insertions and deletions are occurring
= 452 insertion/deletion pairs per sec (worst–case).
More typical cases consist of insertions occurring at one
end of the table and deletions occurring at the other end, or
when insertions and/or deletions take place toward the
middle of the table. The latter scenario would consist of
approximately half the total entries being shifted. The idle
time, in terms of the number of cycles, needed to perform a
typical insertion and/or deletion is given by the formula 2048
x MDC / (MDC – 9) cycles, where MDC is the match duty
cycles. For example, if match requests are occurring every
18 clock cycles:
To load a VPC into the CAM table, the desired VPI value is
written (right justified) to I/O register 3, FFFF is written to
16
4096 x 18 clock cycles
= 36,864 clock cycles
18 clock cycles – 16
I/O register 2 as the VCI field, the upper half of the desired
output word is written to I/O register 1, and the lower half of
the desired output word is written to I/O register 0. Then, the
“INSERT VALUE” instruction is written to the operation regis-
ter.
When performing a match operation, the VCI must be
placed in bits 0 – 15 of the MQ port. The VPI is expected on
bits 16 – 27, or bits 16 – 23 in the UNI case.
At 66 MHz (15 ns per cycle)
= 0.00055296 sec per insert or deletion.
If both insertions and deletions are occurring
= 904 insertion/deletion pairs per sec (worst–case).
buffered–entry mode insertions and deletions are modified
in the following way when the MCM69C233 is in ATM mode.
If you try to add a VCC with the same VPI as an existing
VPC, you overwrite the VPC. If you try to delete a VCC when
The number of insertion/deletion pairs for both cases are
depicted in Figure 3. In general, the time for an insertion or
deletion is proportional to its distance from the end of the
CAM table. That is, entries with the largest match value take
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12,000
10,000
8,000
6,000
4,000
2,000
0
TYPICAL
WORST CASE
16
26
36
46
56
66
76
86
96
MATCH DUTY CYCLE AT 66 MHz INPUT CLOCK
Figure 3. Connections per Second vs Match Cycle Time
the least time to insert or delete, while entries with the small-
est values take the most time.
serting the LH/SM signal with the appropriate setup time
relative to the rising edge of the clock. The assertion of the
MC output signifies the completion of the match cycle. If a
match has been found, the MS output is also asserted. If the
match is a virtual path circuit match in ATM mode, the VPC
output will be asserted with the MS output. Output data, if
any, is enabled by the assertion of the G input.
If the match width is greater than 32 bits, the lower bits are
first latched into the MCM69C233 by the LL input. The match
cycle is then initiated as specified in the previous paragraph.
Two alternative timing diagrams are presented to describe
the Match Port timing. In the first, LH/SM must meet setup
and hold specs across two consecutive clock cycles, while
the MQ bus need only be valid for a single cycle. In the
second diagram, LH/SM need only be asserted for a single
clock cycle, while the MQ bus must be held valid with
constant data across two clock cycles.
Therefore, the effective rate of insertion and deletion is
maximized if the longest–lived entries are placed near the
beginning of the table and the shortest–lived entries are
placed near the end of the table. For an ATM application, this
would correspond to the assignment of small VPI values to
permanent virtual circuits and large VPI values to switched
virtual circuits.
Note that at start–up, when entries are loaded into the
CAM via the fast–entry mode, the process is dominated by
the time it takes to execute the initialization instruction that
follows. The resulting effective rate of loading the CAM at
start–up is approximately 227,500 entries per second.
RESET
RESET is synchronous to the rising edge of the clock with
0 ns setup and hold. Asserting RESET for two clock cycles
removes all entries from the CAM table and entry queue. The
SIMULTANEOUS PORT OPERATIONS
When the control and match ports are utilized simulta-
neously, certain procedures must be followed. If a CHECK
FOR VALUE command is issued, both the last operation
complete bit (bit 10) and the entry queue empty bit (bit 4) in
the flag register should be set prior to executing the CHECK
FOR VALUE command in order to receive valid results. How-
ever, matching on the match port can be done directly after
the last operation complete flag is set.
flag register is set to 1C
(setting the queue empty,
16
buffered–entry mode, and table initialized bits). The error
register is set to FFFF , indicating no errors. The interrupt
16
mask is cleared, and the almost–full register is set to FFF
.
16
TIMING OVERVIEW
CONTROL PORT
The match port has priority over the control port during
simultaneous operations.
The control port of the MCM69C233 is asynchronous.
Data transfers, both read and write, are initiated by the
assertion of the SEL signal. Address values should be valid
and WE should be high, when SEL is asserted to begin
a read cycle. All values (address, WE, and SEL) should be
held until the MCM69C233 asserts DTACK to signal the end
of the read cycle.
Address and data values should be valid and WE should
be low, when SEL is asserted to begin a write cycle. Address,
data, WE, and SEL values should be held until the
MCM69C233 asserts DTACK to signal the end of the write
cycle.
DEPTH EXPANSION
Multiple CAMs can be cascaded to increase the depth of
the match table. The hardware requirements are very
straightforward, as the following pins on each device are sim-
ply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ,
DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC.
Four CAMs can be easily cascaded. Simulations show that
eight devices can be cascaded if care is taken to minimize
the length of the PC board traces connecting the CAMs.
The buffered–entry mode prevents multiple matching en-
tries in a single CAM. The check for value instruction should
be used to verify that multiple matching entries will not result
from a potential new entry. If a match is found in CAM 1, for
example, the new value should be placed in CAM 1, where it
will replace the existing entry.
MATCH PORT
The MCM69C233 match port is synchronous in operation.
When the match width is ≤32 bits, a match cycle can be initi-
ated by presenting the match data on MQ31 – MQ0 and as-
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DEPTH EXPANSION EXAMPLE
CASCADING FOUR MCM69C233s FOR A 16K WORD TABLE
CONTROL PORT
MATCH PORT
CAM 0
A2 – A0
DQ31 – DQ0
SEL0
MQ31 – MQ0
K
A0 – A2
MQ0 – MQ31
K
DQ0 – DQ31
G
G
LM/SM
LH/SM
WE
WE
MC
MS
MC
IRQ
IRQ
MS
DTACK
DTACK
VPC
VPC
CAM 1
CAM 2
CAM 3
A0 – A2
MQ0 – MQ31
K
DQ0 – DQ31
SEL1
G
LM/SM
WE
MC
MS
IRQ
DTACK
VPC
A0 – A2
MQ0 – MQ31
K
DQ0 – DQ31
SEL2
G
LM/SM
WE
MC
MS
IRQ
DTACK
VPC
A0 – A2
MQ0 – MQ31
K
DQ0 – DQ31
G
SEL3
LM/SM
WE
MC
MS
IRQ
DTACK
VPC
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JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS
FOR THE TEST ACCESS PORT (IEEE 1149.1)
(T < 120°C, Unless Otherwise Noted)
J
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Ω Termination to 1.5 V
TAP CONTROLLER TIMING
Parameter
Symbol
Min
30
12
12
5
Max
—
—
—
9
Unit
ns
Notes
Cycle Time
t
CK
Clock High Time
t
ns
CKH
Clock Low Time
t
ns
CKL
Clock Low to Output Valid
Clock Low to Output High–Z
Clock Low to Output Active
Setup Times:
t
A
ns
t
0
9
ns
1
CKZ
CKX
t
0
9
ns
2, 3
TMS
TDI
TRST
t
S
2
2
2
—
ns
t
t
SD
SR
Hold Times:
NOTES:
TMS
TDI
TRST
t
2
2
10
—
ns
H
t
t
HD
HR
1. TDO will High–Z from a clock low edge depending on the current state of the TAP state machine.
2. TDO is active only in the SHIFT–IR and SHIFT–DR state of the TAP state machine.
3. Transition is measured ±500 mV from steady–state voltage. This parameter is sampled and not 100% tested.
t
CKH
t
t
CK
CKL
TEST CLOCK
(TCK)
t
H
t
S
TEST MODE SELECT
(TMS)
t
HD
t
SD
TEST DATA IN
(TDI)
t
A
t
t
CKX
CKZ
TEST DATA OUT
(TDO)
t
SR
t
HR
TRST
Figure 4. TAP Controller Timing
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TEST ACCESS PORT DESCRIPTION
INSTRUCTION SET
After one clock cycle of TCK, the TAP controller would then
be moved to the SHIFT–DR state where the sampled values
would be shifted out of TDO (and new values would be
shifted in TDI). These values would normally be compared to
expected values to test for board connectivity.
A 5–pin IEEE Standard 1149.1 Test Port (JTAG) is in-
cluded on this device. When the TAP (Test Access Port) con-
troller is in the SHIFT–IR state, the instruction register is
placed between TDI and TDO. In this state, the desired
instruction would be serially loaded through the TDI input.
TRST resets the TAP controller to the test–logic reset state.
The TAP instruction set for this device are as follows.
CLAMP TAP INSTRUCTION
The CLAMP instruction is provided to allow the state of the
signals driven from the output pins to be determined from the
boundary scan register while the bypass register is selected
as the serial path between TDI and TDO. The signals driven
from the output pins will not change while the CLAMP
instruction is selected. EXTEST could also be used for this
purpose, but CLAMP shortens the board scan path by insert-
ing only the bypass register between TDI and TDO. To use
CLAMP, the SAMPLE/PRELOAD instruction would be used
first to scan in the values that will be driven on the output pins
when the CAMP instruction is active.
STANDARD INSTRUCTIONS
Code
(Binary)
Instruction
Description
BYPASS
1111*
Bypass instruction
SAMPLE/PRELOAD
0010
Sample and/or preload
instruction
EXTEST
HIGH–Z
0000
1001
Extest instruction
High–Z all output pins while
the bypass register is
HIGH–Z TAP INSTRUCTION
The HIGH–Z instruction is provided to allow all the outputs
to be placed in an inactive drive state (high–Z). During the
HIGH–Z instruction the bypass register is connected be-
tween TDI and TDO.
between TDI and TDO
CLAMP
1100
Clamp output pins while the
bypass register is between
TDI and TDO
BYPASS TAP INSTRUCTION
* Default state at power–up.
The BYPASS instruction is the default instruction loaded at
power–up. This instruction will place a single shift register
between TDI and TDO during the SHIFT–DR state of the
TAP controller. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE/PRELOAD TAP INSTRUCTION
The SAMPLE/PRELOAD TAP instruction is used to allow
scanning of the boundary scan register without causing inter-
ference to the normal operation of the chip logic. The 62–bit
boundary scan register contains bits for all device signal and
clock pins and associated control signals. This register is ac-
cessible when the SAMPLE/PRELOAD TAP instruction is
loaded into the TAP instruction register in the SHIFT–IR
state. When the TAP controller is then moved to the SHIFT–
DR state, the boundary scan register is placed between TDI
and TDO. This scan register can then be used prior to the
EXTEST instruction to preload the output pins with desired
values so that these pins will drive the desired state when the
EXTEST instruction is loaded. As data is written into TDI,
data also streams out of TDO, which can be used to pre–
sample the inputs and outputs.
BOUNDARY SCAN REGISTER
The boundary scan register is identical in length to the
number of active input, output, and I/O connections on the
device (not counting the TAP pins). The boundary scan reg-
ister, under the control of the TAP controller, is loaded with
the contents of the RAM I/O ring when the controller is in
capture–DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift–DR state.
Several TAP instructions can be used to activate the bound-
ary scan register.
The Bit Scan Order table (Table 2) describes which device
pin connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit at G (i.e., first to be shifted out)
is defined as bit 1. The second column is the name of the pin,
the third column is the pin number, and the fourth column is
the pin type (input, output, or I/O).
SAMPLE/PRELOAD would also be used prior to the
CLAMP instruction to preload the values on the output pins
that will be driven out when the CLAMP instruction is loaded.
EXTEST TAP INSTRUCTION
The EXTEST instruction is intended to be used in con-
junction with the SAMPLE/PRELOAD instruction to assist in
testing board level connectivity. Normally, the SAMPLE/
PRELOAD instruction would be used to preload all output
pins. The EXTEST instruction would then be loaded. During
EXTEST, the boundary scan register is placed between TDI
and TDO in the SHIFT–DR state of the TAP controller. Once
the EXTEST instruction is loaded, the TAP controller would
then be moved to the run–test/idle state. In this state, one
cycle of TCK would cause the preloaded data on the output
pins to be driven while the values on the input pins would be
sampled. Note the TCK, not the clock pin (CLK), is used as
the clock input while CLK is only sampled during EXTEST.
DISABLING THE TEST ACCESS PORT AND
BOUNDARY SCAN
It is possible to use this device without utilizing the four
pins used for the test access port. To circuit disable the
device, TCK must be tied to V
to preclude mid–level
SS
inputs. Although TDI and TMS are designed in such a way
that an undriven input will produce a response equivalent to
the application of a logic 1, it is still advisable to tie these
inputs to V
DD
unconnected.
through a 1K resistor. TDO should remain
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Table 2. Sample/Preload Boundary Scan Register Bit Definitions
Bit No.
1
Bit Pin Name
G
Bit Pin No.
61
62
63
64
67
68
69
70
73
74
75
76
79
80
81
82
85
86
87
88
89
92
93
94
95
96
99
100
1
Bit No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Bit Pin Name
MQ6
MQ5
MQ4
MQ3
MQ2
MQ1
MQ0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
K
Bit Pin No.
6
7
2
MS
8
3
VPC
11
4
MC
12
13
14
17
18
19
20
23
24
25
26
29
30
31
32
35
36
37
38
39
42
43
44
45
46
56
57
58
5
MQ31
MQ30
MQ29
MQ28
MQ27
MQ26
MQ25
MQ24
MQ23
MQ22
MQ21
MQ20
MQ19
MQ18
MQ17
MQ16
LH/SM
LL
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MQ15
MQ14
MQ13
MQ12
MQ11
MQ10
MQ9
A2
A1
A0
WE
SEL
RESET
IRQ
MQ8
2
MQ7
5
DTACK
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the instruction that is currently loaded in the TAP instruction
TEST ACCESS PORT PINS
register (see Figure 5). An undriven TDI pin will produce the
same result as a logic 1 input level.
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (see Figure 5). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a
logic 1 input level.
TRST — TAP RESET
This device has a TRST pin. TRST is optional in IEEE
1149.1. Asserting the asynchronous TRST places the TAP
controller in test–logic reset state. Test–logic reset state can
also be entered by holding TMS high for five rising edges of
TCK. This type of reset does not affect the operation of the
system logic.
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
TEST–LOGIC
RESET
1
0
1
RUN–TEST/
IDLE
0
SELECT DR–SCAN
0
SELECT IR–SCAN
1
1
0
1
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–IR
SHIFT–DR
0
0
1
1
1
1
EXIT1–DR
EXIT1–IR
0
0
PAUSE–IR
PAUSE 1–DR
0
0
1
1
0
0
EXIT2–DR
EXIT2–IR
1
1
PAUSE 2–DR
UPDATE–IR
1
1
0
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MCM69C233•SCM69C233
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ORDERING INFORMATION
(Order by Full Part Number)
MCM
SCM
69C233
XX XX X
Blank = Trays, R = Tape and Reel
Speed (15 = 15 ns)
Motorola Memory Prefix
MCM = Commercial Temp.
SCM = Industrial Temp.
Part Number
Package (TQ = TQFP)
Full Commercial Part Numbers — MCM69C233TQ15
Full Industrial Part Numbers — SCM69C233TQ15
MCM69C233TQ15R
SCM69C233TQ15R
MCM69C233•SCM69C233
20
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PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
4X
e
0.20 (0.008) H A–B
D
2X 30 TIPS
e/2
0.20 (0.008) C A–B
D
–D–
80
51
B
B
50
81
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
METAL
PLATING
E1/2
b1
31
100
c1
c
1
30
b
D1/2
D/2
D1
D
M
S
S
0.13 (0.005)
C A–B
D
SECTION B–B
2X 20 TIPS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
0.20 (0.008) C A–B
D
2. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
3. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
A
2
3
0.10 (0.004) C
–H–
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
–C–
SEATING
PLANE
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
VIEW AB
6. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018).
S
0.05 (0.002)
S
MILLIMETERS
1
DIM MIN
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
A
A1
A2
b
b1
c
c1
D
D1
E
–––
0.05
1.35
0.22
0.22
0.09
0.09
0.25 (0.010)
GAGE PLANE
R2
A2
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
L2
L
R1
A1
E1
e
L1
L
0.45
1.00 REF
0.50 REF
0.75
VIEW AB
L1
L2
S
R1
R2
0.20
–––
–––
0.20
7
0.08
0.08
0
1
2
3
0
11
11
–––
13
13
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NOTES
MCM69C233•SCM69C233
22
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NOTES
MCM69C233•SCM69C233
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