MCM69F819TQ11R [NXP]
256KX18 CACHE SRAM, 11ns, PQFP100, TQFP-100;
| 型号： | MCM69F819TQ11R |
| 厂家： | 
NXP |
| 描述： | 256KX18 CACHE SRAM, 11ns, PQFP100, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69F819/D
MCM69F819
256K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
dataRAMapplications. Synchronousdesignallowsprecisecyclecontrolwiththe
use of an external clock (K).
ZP PACKAGE
PBGA
CASE 999–02
Addresses (SA), data inputs (DQx), and all control signals except output
enable(G) and linear burst order (LBO) are clock (K) controlled through positive
edge–triggered noninverting registers.
TQ PACKAGE
TQFP
CASE 983A–01
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69F819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex of–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
The MCM69F819 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
•
MCM69F819–7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz)
MCM69F819–8: 8 ns Access/10 ns Cycle (100 MHz)
MCM69F819–8.5: 8.5 ns Access/11 ns Cycle 90 MHz)
MCM69F819–11: 11 ns Access/20 ns Cycle (50 MHz)
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Single–Cycle Deselect Timing
Internally Self–Timed Write Cycle
•
•
•
•
•
•
•
•
Byte Write and Global Write Control
PB1 Version 2.0 Compatible
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 7
1/22/98
Motorola, Inc. 1998
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
BURST
2
18
COUNTER
ADSC
ADSP
256K x 18
ARRAY
K2
CLR
2
SA
SA1
SA0
18
16
ADDRESS
REGISTER
SGW
SW
18
18
WRITE
REGISTER
a
SBa
2
DATA–IN
REGISTER
WRITE
REGISTER
b
K
SBb
K2
SE1
SE2
SE3
ENABLE
REGISTER
G
DQa – DQb
MCM69F819
2
MOTOROLA FAST SRAM
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Freescale Semiconductor, Inc.
PIN ASSIGNMENTS
1
2
3
4
5
6
7
10099 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
A
B
C
D
E
NC
NC
NC
1
2
3
4
5
6
7
SA
NC
NC
V
V
SA
SA ADSP
SA ADSC
SA
SA
V
DDQ
DDQ
79
78
77
76
75
74
73
72
NC
SE2
SA
SA
SA
SE3
SA
NC
V
DDQ
DDQ
V
NC
SA
V
NC
SS
DD
V
NC
SS
NC
NC
DQb
DQb
NC
NC
V
NC
SE1
G
V
DQa
NC
SS
SS
SS
SS
SS
SS
SS
SS
DQa
DQa
DQa
8
9
DQb
NC
V
V
V
V
V
V
NC
DQa
NC
DQa
DQb
V
F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
DDQ
DQb
DQb
NC
DD
NC
SS
DQb
DQb
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DQa
DQa
SS
DDQ
V
V
DDQ
DDQ
V
G
NC
DQb SBb
NC
ADV
SGW
DQa
H
V
DQb
V
DQa
NC
SS
SS
NC
V
NC
J
K
L
V
V
V
V
NC
V
V
DD
DDQ
DD
DD
DD
DDQ
V
NC
DQa
DQa
V
NC
DQb
V
K
V
NC
DQa
SS
SS
V
DQb
NC
DQb
NC
V
V
V
V
NC
SW
SA1
SA0
SBa
DQa
NC
NC
DDQ
SS
SS
SS
SS
DDQ
SS
V
M
N
P
SS
V
V
V
V
DQb
DQb
DQb
NC
DDQ
SS
DDQ
DQa
DQa
NC
DQb
V
DQa
NC
NC
SS
SS
NC
NC
DQb
V
DQa
V
V
SS
DDQ
NC
NC
NC
SS
R
T
V
V
DDQ
NC
NC
SA
LBO
V
NC
SA
NC
NC
DD
NC
NC
NC
SA
NC
SA
NC
NC
NC
SA
NC
SA
NC
U
31 3233 343536 3738 3940 414243 444546 4748 49 50
V
V
DDQ
DDQ
TOP VIEW 119 BUMP PBGA
TOP VIEW 100 PIN TQFP
Not to Scale
MCM69F819
3
MOTOROLA FAST SRAM
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PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
4B
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
4A
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
4G
ADV
DQx
G
Input
I/O
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
4F
Input
Asynchronous Output Enable Input:
Low — enables output buffers (Dx pins).
High — DQx pins are high impedance.
4K
3R
K
Input
Input
Clock: This signal registrs the address, data in, and all control signals
except G and LBO
LBO
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 3G
(a) (b)
SBx
SE1
Input
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
4E
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
2B
6B
4H
SE2
SE3
Input
Input
Input
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
SGW
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
4M
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
4C, 2J, 4J, 6J, 4R
V
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
DD
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
DDQ
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
V
SS
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,
5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69F819
4
MOTOROLA FAST SRAM
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TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
84
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
83
ADV
DQx
G
Input
I/O
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86
Input
Asynchronous Output Enable Input:
Low — enables output buffers (Dx pins).
High — DQx pins are high impedance.
89
31
K
Input
Input
Clock: This signal registrs the address, data in, and all control signals
except G and LBO
LBO
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,
80, 81, 82, 99, 100
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
88
SGW
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
92
87
SE2
SE3
SW
Input
Input
Input
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
15, 41, 65, 91
V
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
DD
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
V
SS
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,
39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,
78, 79, 95, 96
NC
—
No Connection: There is no connection to the chip.
MCM69F819
5
MOTOROLA FAST SRAM
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TRUTH TABLE (See Notes 1 Through 5)
Address
Used
3
2, 4
Next Cycle
Deselect
SE1
1
SE2
X
X
0
SE3
X
1
ADSP
ADSC
ADV
X
X
X
X
X
X
X
0
G
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
Write
None
None
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
Deselect
0
X
X
X
X
0
0
1
0
1
0
1
0
1
0
X
X
X
X
X
Deselect
None
0
X
1
Deselect
None
X
X
0
X
0
Deselect
None
X
0
5
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
External
External
Next
1
X
5
0
1
0
READ
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
Next
0
Next
0
High–Z
DQ
Next
1
0
Current
Current
Current
Current
External
Next
X
X
1
1
High–Z
DQ
1
1
High–Z
DQ
1
1
0
X
0
High–Z
High–Z
High–Z
High–Z
High–Z
Continue Write
Continue Write
Suspend Write
Suspend Write
NOTES:
X
1
X
X
X
X
X
X
X
X
Next
0
Current
Current
X
1
1
1
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signaand is not sampled by the clock K. G drives the bus immediately (t
) following G going low.
GLQX
4. On write cycles that follw read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = V
)
SS
1st Address (External)
X . . . X00
2nd Address (Internal)
X . . . X01
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = V
)
DD
2nd Address (Internal)
1st Address (External)
X . . . X00
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X01
X . . . X11
X . . . X10
X . . . X10
X . . . X00
X . . . X01
X . . . X11
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
H
SW
SBa
X
SBb
X
Read
H
L
L
L
L
X
Read
H
H
H
Write Byte a
Write Byte b
Write All Bytes
Write All Bytes
H
L
H
H
H
L
H
L
L
L
X
X
MCM69F819
6
MOTOROLA FAST SRAM
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ABSOLUTE MAXIMUM RATINGS (See Note 1)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Power Supply Voltage
I/O Supply Voltage
Symbol
Value
Unit Notes
V
DD
V
– 0.5 to + 4.6
V
SS
V
DDQ
V
– 0.5 to V
V
V
2
2
SS
DD
Input Voltage Relative to V
Any Pin Except V
DD
for
V , V
in out
V
V
– 0.5 to
SS
SS
+ 0.5
DD
Input Voltage (Three–State I/O)
V
IT
V
V
– 0.5 to
+ 0.5
V
2
SS
DDQ
Output Current (per I/O)
Package Power Dissipation
Ambient Temperature
Die Temperature
I
± 20
mA
W
out
P
1.6
0 to 70
110
3
3
D
T
°C
°C
°C
°C
A
T
J
Temperature Under Bias
Storage Temperature
NOTES:
T
bias
– 10 to 85
T
– 55 to 125
stg
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTCS — PBGA
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
38
22
°C/W
1, 2
θJA
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
R
R
14
5
°C/W
°C/W
3
4
θJB
θJC
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
PACKAGE THERMAL CHARACTERISTICS — TQFP
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
40
25
°C/W
1, 2
θJA
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
R
R
17
9
°C/W
°C/W
3
4
θJB
θJC
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
MCM69F819
7
MOTOROLA FAST SRAM
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DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply (Voltages Referenced to V
SS
= 0 V)
Typ
Parameter
Symbol
Min
3.135
2.375
– 0.3
1.7
Max
3.6
2.9
0.7
Unit
V
Supply Voltage
V
DD
3.3
2.5
—
I/O Supply Voltage
Input Low Voltage
V
DDQ
V
V
IL
V
Input High Voltage
Input High Voltage (I/O Pins)
V
IH
—
V
DD
+ 0.3
V
V
IH2
1.7
—
V
DDQ
+ 0.3
V
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to V
SS
= 0 V)
Parameter
Symbol
Min
3.135
3.135
– 0.5
2
Typ
3.3
3.3
—
Max
3.6
Unit
V
Supply Voltage
V
DD
I/O Supply Voltage
Input Low Voltage
V
DDQ
V
DD
V
V
IL
0.8
V
Input High Voltage
Input High Voltage (I/O Pins)
V
IH
—
V
+ 0.5
V
DD
V
IH2
2
—
V
DDQ
+ 0.5
V
V
IH
V
SS
V
– 1.0 V
SS
20% t
(MIN)
KHKH
Figure 1. Undershoot Voltage
MCM69F819
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DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Input Leakage Current (0 V ≤ V ≤ V
Symbol
Min
—
Typ
—
Max
± 1
Unit
µA
Notes
)
I
lkg(I)
in
DD
Output Leakage Current (0 V ≤ V ≤ V
)
I
lkg(O)
—
—
± 1
µA
in
DDQ
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max)
MCM69F819–7.5
MCM69F819–8
MCM69F819–8.5
MCM69F819–11
I
—
—
350
325
300
250
mA
1, 2, 3
DDA
Includes V
Only
DD
CMOS Standby Supply Current (Device Deselected, Freq = 0,
= Max, All Inputs Static at CMOS Levels)
I
—
—
—
—
—
—
45
mA
mA
mA
4, 5
4, 6
4, 5
SB2
SB3
SB4
V
DD
TTL Standby Supply Current (Device Deselected, Freq = 0,
= Max, All Inputs Static at TTL Levels)
I
50
V
DD
Clock Running (Device Deselected,
Freq = Max, V = Max,
MCM69F819–7.5
MCM69F819–8
MCM69F819–8.5
MCM69F819–11
I
190
175
165
145
DD
All Inputs Toggling at CMOS Levels)
Static Clock Running (Device Deselected, Freq = Max,
= Max, All Inputs Static at TTL Levels)
I
—
—
95
mA
4, 6
SB5
V
DD
Output Low Voltage (I
= 2 mA) V
= 2.5 V
V
—
1.7
—
—
—
—
—
0.7
—
V
V
V
V
OL
DDQ
OL
Output High Voltage (I
= – 2 mA) V
= 2.5 V
V
OH
OL
DDQ
Output Low Voltage (I
= 8 mA) V
= 3.3 V
V
OL2
0.4
—
OL
DDQ
Output High Voltage (I
NOTES:
= – 4 mA) V
= 3.3 V
DDQ
V
OH2
2.4
OL
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. All addresses transition simultaneously low (LSB) then high (MSB).
3. Data states are all zero.
4. Device is deselected as defined by the Truth Table.
5. CMOS levels for I/O’s are V ≤ V
6. TTL levels for I/O’s are V ≤ V or ≥ V
IT IL
+ 0.2 V or ≥ V
. TTL levels for other inputs are V ≤ V or ≥ V .
IH2 in IL IH
– 0.2 V. CMOS levels for other inputs are V ≤ V
in
+ 0.2 V or ≥ V – 0.2 V.
DD
IT
SS
DDQ
SS
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Min
—
Typ
4
Max
5
Unit
pF
Input Capacitance
C
in
Input/Output Capacitance
C
—
7
8
pF
I/O
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM69F819–7.5
117 MHz
MCM69F819–8
100 MHz
MCM69F819–8.5 MCM69F819–11
90 MHz
50 MHz
Parameter
Cycle Time
Symbol
Min
8.5
3
Max
—
Min
Max
—
Min
Max
—
Min
Max
—
Unit
ns
Notes
t
10
4
11
4.5
4.5
—
20
4.5
4.5
—
KHKH
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
t
—
—
—
—
ns
KHKL
KLKH
KHQV
t
3
—
4
—
—
—
ns
t
—
—
7.5
3.5
—
—
8
8.5
3.5
11
ns
Output Enable to Output
Valid
t
3.5
—
—
3.5
ns
GLQV
Clock High to Output Active
t
t
0
2
—
—
0
2
—
—
0
2
—
—
0
2
—
—
ns
ns
3, 4, 5
3, 4
KHQX1
Clock High to Output
Change
KHQX2
Output Enable to Output
Active
t
0
—
0
—
0
—
0
—
ns
3, 4
GLQX
Output Disable to Q High–Z
Clock High to Q High–Z
t
—
2
3.5
3.5
—
—
2
3.5
3.5
—
—
2
3.5
3.5
—
—
2
3.5
3.5
—
ns
ns
ns
3, 4
GHQZ
t
3, 4, 5
KHQZ
ADKH
Setup Times:
Address
t
1.5
2
2
2
ADSP, ADSC, ADV
Data In
t
ADSKH
t
DVKH
Writ
Chip Enable
t
WVKH
t
EVKH
Hold Times:
Address
ADSP, ADSC, ADV
Data In
t
0.5
—
0.5
—
0.5
—
0.5
—
ns
KHAX
t
KHADSX
t
KHDX
Write
Chip Enable
t
KHWX
t
KHEX
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. Measured at ± 200 mV from steady state.
4. This parameter is sampled and not 100% tested.
5. At any given voltage and temperature, t
max is less than t
min for a given device and from device to device.
KHQX1
KHQZ
OUTPUT
Z
= 50 Ω
R
= 50 Ω
0
L
1.25 V
Figure 2. AC Test Load
MCM69F819
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5
4
3
OUTPUT
C
L
2
1
0
0
20
40
60
80
100
LUMPED CAPACITANCE, C (pF)
L
Figure 3. Lumped Capacitive Load and Typical Derating Curve
OUTPUT LOAD
OUTPUT
TEST POINT
BUFFER
UNLOADED RISE AND FALL TIME MEASUREMENT
2.0
2.0
INPUT
0.5
0.5
WAVEFORM
2.0
2.0
OUTPUT
0.5
0.5
WAVEFORM
t
t
f
r
NOTES:
1. Input waveform has a slew rate of 1 V/ns.
2. Rise time is measured from 0.5 to 2.0 V unloaded.
3. Fall time is measured from 2.0 to 0.5 V unloaded.
Figure 4. Unloaded Rise and Fall Time Characterization
MCM69F819
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2.9
2.5
PULL–UP
I (mA) MIN
2.3
2.1
VOLTAGE (V)
I (mA) MAX
– 0.5
0
– 38
– 38
– 38
– 26
– 105
– 105
– 105
– 83
0.8
1.25
1.25
0.8
1.5
2.3
2.7
2.9
– 20
– 70
– 30
– 10
0
0
0
0
0
0
– 38
CURRENT (mA)
– 105
(a) Pull–Up for 2.5 V I/O Supply
3.6
3.135
2.8
PULL–UP
I (mA) MIN
VOLTAGE (V)
I (mA) MAX
– 0.5
0
– 50
– 50
– 50
– 46
– 10
– 150
– 150
– 130
1.65
1.4
1.4
1.65
2.0
3.135
3.6
– 35
0
– 101
– 25
0
0
0
0
– 40
– 80
– 120
CURRENT (mA)
(b) Pull–Up for 3.3 V I/O Supply
V
DD
PULL–DOWN
VOLTAGE (V)
I (mA) MIN
I (mA) MAX
– 0.5
0
0
0
0
0
1.6
0.4
0.8
10
20
20
40
1.25
1.25
1.6
31
40
40
63
80
80
2.8
0.3
0
3.2
3.4
40
40
80
80
0
40
80
CURRENT (mA)
(c) Pull–Down
Figure 5. Typical Output Buffer Characteristics
MCM69F819
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APPLICATION INFORMATION
STOP CLOCK OPERATION
operation for all three stop clock modes, stop read, stop
write, and stop deselect:
To achieve the lowest power operation for all three stop
clock modes, stop read, stop write, and stop deselect:
In the stop clock mode of operation, the SRAM will hold all
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP and ADSC, and stops the clock after the last
write data is latched, or the last read data is driven out.
When starting and stopping the clock, the AC clock timing
and parametrics must be strictly maintained. For example,
clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.To achieve the lowest power
•
•
Force the clock to a low state.
Force the control signals to an inactive state (this
guarantees any potential source of noise on the clock
input will not start an unplanned on activity).
•
Force the address inputs to a low state (V ), preferably
IL
< 0.2 V.
STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
DQx
Q(A1)
Q(A1 + 1)
Q(A2)
ADSP
(INITIATES
BURST READ)
CLOCK STOP
(CONTINUE
BURST READ)
WAKE UP ADSP
(INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (V ).
IL
Best results are obtained if V < 0.2 V.
IL
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STOP CLOCK WITH WRITE TIMING
K
ADSC
ADDRESS
WRITE
ADV
A1
A2
DATA IN
DQx
D(A1)
D(A1 + 1)
V
OR V FIXED (SEE NOTE)
IL
D(A2)
IH
HIGH–Z
ADSC
(INITIATES
CLOCK STOP
(CONTINUE
WAKE UP ADSC
(INITIATES BURST WRITE)
BURST WRITE)
BURST WRITE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (V ) or low (V ) state to reduce the DC current of the
IH
IL
input buffers. For lowest power operation, all data and address lines should be held in a low (V ) state and control
IL
lines held in an inactive state.
MCM69F819
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STOP CLOCK WITH DESELECT OPERATION TIMING
K
ADSC
SE1
DATA IN
V
OR V FIXED (EE NOTE)
IL
IH
HIGH–Z
DQx
DATA
DATA
CONTINUE
BURST READ
CLOCK STOP
(DSELECTED)
WAKE UP
(DESELECTED)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (V ) or low (V ) state to reduce the DC current of the
IH
IL
input buffers. For lowest power operation, all data and address lines should be held in a low (V ) state and control
IL
lines held in an inactive state.
MCM69F819
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NON–BURST SYNCHRONOUS OPERATION
CONTROL PIN TIE VALUES EXAMPLE (H ≥ V , L ≤ V
IH
)
IL
ADSP ADSC ADV SE1 SE2 LBO
Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter-
face can make use of the MCM69F819. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can
be configured to act upon a continuous stream of addresses.
See Figure 6.
Non–Burst
Sync Non–Burst,
Flow–Through
SRAM
H
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
SE3
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(H)
D(G)
READS
WRITES
Figure 6. Example Configuration as Non–Burst Synchronous SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
69F819
XX
X
X
Motorola Memory Prefix
Part Number
Blank = Trays, R = Tape and Reel
Speed (7.5 = 7.5 ns, 8 = 8 ns,
8.5 = 8.5 ns, 11 = 11 ns)
Package (ZP = PBGA, TQ = TQFP)
Full Part Numbers — MCM69F819ZP7.5
MCM69F819ZP7.5R MCM69F819ZP8R MCM69F819ZP8.5R
MCM69F819TQ7.5 MCM69F819TQ8 MCM69F819TQ8.5
MCM69F819ZP8
MCM69F819ZP8.5
MCM69F819ZP11
MCM69F819ZP11R
MCM69F819TQ11
MCM69F819TQ7.5R MCM69F819TQ8R MCM69F819TQ8.5R
MCM69F819TQ11R
MCM69F819
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PACKAGE DIMENSIONS
ZP PACKAGE
7 x 17 BUMP PBGA
CASE 999–02
0.20
4X
119X
b
B
D
M
0.3
A
A
B C
E
C
NOTES:
M
0.15
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
7
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
D1
D2
MILLIMETRS
K
L
DIM
A
A
A2
A3
D
D1
D2
E
E1
E2
b
MIN
–––
0.50
1.30
0.80
MAX
2.40
0.70
1.70
1.00
M
N
P
R
T
16X e
U
22.00 BSC
20.32 BSC
19.40 19.60
14.00 BSC
7.62 BSC
6X
e
E2
E1
BOTTOM VIEW
TOP VIEW
11.90
0.60
1.27 BSC
12.10
0.90
e
0.25
A
A3
A2
0.35
0.20
A
A
SEATING
PLANE
SIDE VIEW
A1
A
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TQ PACKAGE
TQFP
CASE 983A–01
4X
80
e
0.20 (0.008)
H
A–B
D
2X 30 TIPS
0.20 (0.008)
e/2
C
A–B
D
–D–
51
50
81
B
B
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
METAL
PLATING
E1/2
b1
31
100
c1
c
1
30
D1/2
D/2
b
D1
D
M
S
S
0.13 (0.005)
C
A–B
D
SECTION B–B
2X 20 TIPS
0.20 (0.008)
NOTES:
C
A–B
D
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
A
2
3
0.10 (0.004)
C
–H–
–C–
SEATING
PLANE
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
VIEW AB
S
0.05 (0.002)
S
1
0.25 (0.010)
MILLIMETERS
INCHES
MIN
GAGE PLANE
R2
DIM
A
A1
A2
b
b1
c
c1
D
MIN
–––
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
MAX
0.063
0.006
0.057
0.015
0.013
0.008
0.006
A2
–––
0.002
0.053
0.009
0.009
0.004
0.004
0.05
1.35
0.22
0.22
0.09
0.09
L2
L
R1
A1
22.00 BSC
0.866 BSC
L1
D1
E
E1
e
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
VIEW AB
L
0.45
1.00 REF
0.50 REF
0.75
0.018
0.039 REF
0.020 REF
0.030
L1
L2
S
R1
R2
0.20
–––
–––
0.20
7
0.008
–––
–––
0.008
7
0.08
0.08
0
0.003
0.003
0
1
2
3
0
11
11
–––
13
13
0
11
11
–––
13
13
MCM69F819
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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