MCM69R536ZP5_技术文档

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

MOTOROLA

Order this document

by MCM69R536/D

MCM69R536

MCM69R618

Advance Information

1M Late Write HSTL

The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM

designed to provide high performance in secondary cache, ATM switch,

Telecom, and other high speed memory applications. The MCM69R618

organized as 64K words by 18 bits, and the MCM69R536 organized as 32K

words by 36 bits wide are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of

the RAM. At the rising edge of the CK clock all addresses, write enables, and

synchronous selects are registered. An internal buffer and special logic enable

the memory to accept write data on the rising edge of the CK clock a cycle after

address and control signals. Read data is driven on the rising edge of the CK

clock also.

ZP PACKAGE

PBGA

CASE 999–01

TheRAMusesHSTLinputsandoutputs. Theadjustableinputtrip–point(V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

Single 3.3 V + 10%, – 5% Operation

HSTL – I/O (JEDEC Standard JESD8–6 Class 1 Compatible)

HSTL – User Selectable Input Trip–Point

HSTL – Compatible Programmable Impedance Output Drivers

Register to Register Synchronous Operation

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 organization

MCM69R536/618–5 = 5 ns

MCM69R536/618–6 = 6 ns

MCM69R536/618–7 = 7 ns

MCM69R536/618–8 = 8 ns

•

119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

8/15/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69R536•MCM69R618

For More Information On This Product,

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1

Freescale Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

DATA IN

REGISTER

ADDRESS

REGISTERS

MEMORY

ARRAY

SA

DQ

DATA OUT

REGISTER

SW

REGISTERS

CONTROL

LOGIC

SBx

CK

G

SS

REGISTERS

PIN ASSIGNMENTS

TOP VIEW

MCM69R536

MCM69R618

1

2

3

4

5

6

7

1

2

3

4

5

6

7

A

B

C

D

E

A

V

SA

NC

SA

NC

SA

NC

SA

NC

SA

NC

SA

V

SA

NC

SA

NC

SA

NC

SA

NC

SA

NC

V

DDQ

B

C

D

E

NC

SA

V

NC

V

SA

NC

DD

DQc

V

ZQ

V

DQb DQb

DQb

NC

DQb

NC

V

ZQ

SS

G

V

DQa

NC

SS

V

SS

G

V

DQa

F

V

DQb

V

DQa

NC

V

DDQ

G

DQc

DQc SBc

NF

SBb

DQb DQb

NC

DQb SBb

NF

DQa

H

DQc

V

DQb

NC

V

DQa

NC

SS

J

K

L

J

K

L

V

DDQ

DD

ref

DD

ref

DD DDQ

V

V V

DD DDQ

DDQ

DD

ref

DD

ref

DQd

V

CK

V

DQa DQa

NC

DQb

V

CK

V

NC

DQa

NC

SS

DQb

NC

SBa

DQa

DQd

DQd SBd

CK

SW

SA

SBa

M

N

P

M

N

P

V

DQd

V

DQa

V

DQb

NC

V

SW

SA

V

NC

DQa

NC

V

DDQ

SS

DDQ

SS

DDQ

DQd

DQa DQa

DQb

NC

DQd

NC

DQb

DQa

NC

ZZ

R

T

R

T

NC

SA

NC

V

SA

NC

ZZ

SA

V

SA

NC

SS

DD

SS

DD

NC

TCK

DD

SA

TDO

SA

U

V

TMS

TDI

TCK

TDO

V

TMS

TDI

V

DDQ

MCM69R536•MCM69R618

2

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MCM69R536 PIN DESCRIPTIONS

PBGA Pin Locations

Symbol

CK

Type

Input

I/O

Description

4K

4L

Address, data in and control input register clock. Active high.

Address, data in and control input register clock. Active low.

Synchronous Data I/O.

CK

(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P

(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H

(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H

(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P

DQx

4F

G

Input

Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 2C, 3C,

SA

Synchronous Address Inputs: Registered on the rising clock edge.

5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T

5L, 5G, 3G, 3L

(a), (b), (c), (d)

SBx

Input

Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW input. Has no effect on read cycles, active

low.

4E

SS

Input

Synchronous Chip Enable: Registered on the rising clock edge, active

low.

4M

SW

Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.

4U

TCK

TDI

Input

Test Clock (JTAG).

Test Data In (JTAG).

3U

5U

TDO

TMS

Output Test Data Out (JTAG).

Input Test Mode Select (JTAG).

Supply Input Reference: provides reference voltage for input buffers.

2U

3J, 5J

V

ref

4D

7T

ZQ

ZZ

Input

Programmable Output Impedance: Programming pin.

Reserved for future use. Must be grounded.

4C, 2J, 4J, 6J, 4R, 5R

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U

V

Supply Core Power Supply.

DD

V

DDQ

Supply Output Power Supply: Provides operating power for output buffers.

Supply Ground.

3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,

3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R

V

SS

4A, 1B, 2B, 3B, 4B, 5B, 6B, 7B,

1C, 7C, 1R, 7R, 1T, 2T, 6T, 6U

NC

—

No Connection: There is no connection to the chip.

4G, 4H

NF

No Function: There is an internal connection to the chip, but the pin

has no function on this device.

MCM69R536•MCM69R618

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MCM69R618 PIN DESCRIPTIONS

PBGA Pin Locations

Symbol

CK

Type

Input

I/O

Description

4K

4L

Address, data in and control input register clock. Active high.

Address, data in and control input register clock. Active low.

Synchronous Data I/O.

CK

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

DQx

4F

G

Input

Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 2C, 3C, 5C,

SA

Synchronous Address Inputs: Registered on the rising clock edge.

6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T

5L, 3G

(a), (b)

SBx

Input

Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW input. Has no effect on read cycles, active

low.

4E

SS

Input

Synchronous Chip Enable: Registered on the rising clock edge, active

low.

4M

SW

Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.

4U

TCK

TDI

Input

Test Clock (JTAG).

Test Data In (JTAG).

3U

5U

TDO

TMS

Output Test Data Out (JTAG).

Input Test Mode Select (JTAG).

Supply Input Reference: provides reference voltage for input buffers.

2U

3J, 5J

V

ref

4D

7T

ZQ

ZZ

Input

Programmable Output Impedance: Programming pin.

Reserved for future use. Must be grounded.

4C, 2J, 4J, 6J, 4R, 5R

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U

V

Supply Core Power Supply.

DD

V

DDQ

Supply Output Power Supply: Provides operating power for output buffers.

Supply Ground.

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,

3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R

V

SS

4A, 1B, 2B, 3B, 4B, 5B, 6B, 7B, 1C, 7C,

2D, 7D, 1E, 6E, 2F, 1G, 6G,

NC

—

No Connection: There is no connection to the chip.

2H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,

7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U

4G, 4H

NF

—

No Function: There is an internal connection to the chip, but the pin

has no function on this device.

MCM69R536•MCM69R618

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ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V , See Note 1)

SS

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.

This BiCMOS memory circuit has been

designed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established.

Rating

Core Supply Voltage

Symbol

Value

Unit

V

DD

– 0.5 to + 4.6

V

Output Supply Voltage

Voltage On Any Pin

V

DDQ

– 0.5 to V

+ 0.5

V

DD

V

in

– 0.5 to V

+ 0.5

DD

Input Current (per I/O)

Output Current (per I/O)

Power Dissipation (See Note 2)

Operating Temperature

Temperature Under Bias

I

in

± 50

mA

W

I

± 70

—

out

P

D

This device contains circuitry that will ensure

the output devices are in High–Z at power up.

T

A

0 to + 70

°C

T

bias

–10 to + 85

Storage Temperature

NOTES:

T

stg

– 55 to + 125

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended

periods of time could affect device reliability.

2. Powerdissipationcapabilitywillbedependentuponpackagecharacteristicsanduse

environment. See enclosed thermal impedance data.

PBGA PACKAGE THERMAL CHARACTERISTICS

Rating

Symbol

Max

59

44

28

18

9

Unit

°C/W

Notes

1, 2

Junction to Ambient (Still Air)

Junction to Ambient (@200 ft/min)

Junction to Board (Bottom)

Junction to Case (Top)

R

θJA

R

θJA

R

θJA

R

θJB

R

θJC

Single Layer Board

Four Layer Board

1, 2

3

4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883

Method 1012.1).

CLOCK TRUTH TABLE

K

ZZ

L

SS

L

SW

H

L

SBa

X

SBb

X

SBc

X

SBd

X

DQ (n)

High–Z

DQ (n+1)

Mode

L – H

X

D

0–35

0–8

Read Cycle All Bytes

Write Cycle 1st Byte

Write Cycle 2nd Byte

Write Cycle 3rd Byte

Write Cycle 4th Byte

Write Cycle All Bytes

Abort Write Cycle

Deselect Cycle

out

L

H

L

H

L

H

L

D

in

L

H

L

D

9–17

in

L

H

L

D

18–26

27–35

0–35

in

L

H

L

D

L

D

in

L

H

X

H

X

H

X

H

X

High–Z

L

H

X

H

L

X

Deselect Cycle

H

X

Sleep Mode

MCM69R536•MCM69R618

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DC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)

A

RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)

Typical Typical Typical Typical

–5

—

–6

—

–7

—

–8

—

Parameter

Core Power Supply Voltage

Output Driver Supply Voltage

Active Power Supply Current

Symbol

Min

3.15

1.4

Max

3.6

Unit

V

Notes

V

DD

V

1.6

V

DDQ

DD1

(x18)

(x36)

I

—

TBD

mA

5

Quiescent Active Power Supply Current (x18)

(x36)

I

—

TBD

mA

6, 10

7

DD2

Active Standby Power Supply Current

(x18)

(x36)

I

—

TBD

SB1

SB2

SB3

Quiescent Standby Power Supply Current (x18)

(x36)

—

TBD

8, 10

Sleep Mode Power Supply Current

Input Reference DC Voltage

NOTES:

—

TBD

—

TBD

—

TBD

—

TBD

—

TBD

1.1

mA

V

9, 10

11

V

(dc)

0.6

ref

1. AlldatasheetparametersspecifiedtofullrangeofV

unlessotherwisenoted. AllvoltagesarereferencedtovoltageappliedtoV bumps.

SS

DD

2. Supply voltage applied to V

3. Supply voltage applied to V

connections.

DD

connections.

DDQ

4. All power supply currents measured with outputs open or deselected.

5. V

6. V

7. V

8. V

9. V

= V

(max), t

(Max), t

= t

KHKH KHKH

(min), SS registered active, 50% read cycles.

= dc, SS registered active.

DD

KHKH

KHKH KHKH

= t

(min), SS registered inactive.

= dc, SS registered inactive, ZZ low.

= dc, registered inactive, ZZ high.

KHKH

10. 200 mV ≥ V ≥ V

– 200 mV.

11. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of V is supported, the peak to peak ac component

in DDQ

ref

superimposed on V may not exceed 5% of the dc component of V

ref

.

ref

DC INPUT CHARACTERISTICS

Parameter

Symbol

Min

+ 0.1

Max

+ 0.3

DD

Unit

V

Notes

DC Input Logic High

V

(dc)

V

ref

V

IH

DC Input Logic Low (See Figure 2)

Input Leakage Current

V

– 0.3

—

V

ref

– 0.1

V

1

2

IL

I

± 5

µA

V

lkg

Clock Input Signal Voltage

V

in

– 0.3

0.2

V

+ 0.3

+ 0.6

DD

Clock Input Differential Voltage

Clock Input Common Mode Voltage Range (See Figure 3)

Clock Input Crossing Point Voltage Range (See Figure 3)

NOTES:

V

DIF

V

CM

(dc)

V

3

4

DD

0.68

1.1

V

X

V

1. Inputs may undershoot to –0.5 V (peak) for up to 20% t

(e.g., 2 ns at a clock cycle time of 10 ns).

KHKH

2. 0 V ≤ V for all pins.

V

in ≤ DDQ

3. Minimum differential input voltage required for differential input clock operation.

4. Maximum rejectable common mode input voltage variation.

MCM69R536•MCM69R618

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DC OUTPUT BUFFER CHARACTERISTICS – PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE

(0_C ≤ T ≤ 70_C, Unless Otherwise Noted, See Notes 1 and 2)

A

Parameter

Symbol

Min

Max

V /2 +0.025

DDQ

Unit

V

Notes

Output Logic Low

Output Logic High

V

OL

V

/2 – 0.025

3

4

5

6

DDQ

V

OH

V

DDQ

/2 + 0.025

V

DDQ

Light Load Output Logic Low

Light Load Output Logic High

V 1

OL

V

SS

0.2

V

OH

1

V

– 0.2

V

DDQ

V

DDQ

NOTES:

1. The impedance controlled mode is expected to be used in point–to–point applications, driving high impedance inputs.

2. The ZQ pin is connected through RQ to V for the controlled impedance mode.

SS

/2)/(RQ/5) for values of RQ = 175 Ω ≤ RQ ≤ 350 Ω.

3. I

OL

= (V

DDQ

4. | I

| = (V

/2)/(RQ/5) for values of RQ = 175 Ω ≤ RQ ≤ 350 Ω.

OH

DDQ

5. I

OL

≤ 100 µA.

| ≤ 100 µA.

6. | I

OH

DC OUTPUT BUFFER CHARACTERISTICS – MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE

(0_C ≤ T ≤ 70_C, ZQ = V , See Notes 1 and 2)

A

DD

Parameter

Symbol

Min.

Max.

Unit

V

Notes

Output Logic Low

Output Logic High

V 2

OL

V

SS

0.4

3

4

5

6

V

2

3

V

– 0.4

V

DDQ

V

OH

DDQ

Light Load Output Logic Low

Light Load Output Logic High

V

SS

0.2

V

OL

V

OH

3

– 0.2

V

DDQ

V

DDQ

NOTES:

1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC

Standard JESD8–6 Class 1.

2. The ZQ pin is connected to V

to enable the minimum impedance mode.

DD

3. I

OL

≤ 8 mA.

| ≤ 8 mA.

4. | I

OH

≤ 100 µA.

5. I

OL

6. | I

|≤ 100 µA.

OH

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0_C ≤ T ≤ 70_C, Periodically Sampled Rather Than 100% Tested)

A

Characteristic

Symbol

Typ

Max

Unit

pF

Input Capacitance

C

4

5

8

5

in

Input/Output Capacitance

CK, CK Capacitance

C

7

pF

I/O

CK

C

4

pF

MCM69R536•MCM69R618

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AC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)

A

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)

Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V

Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V

Clock Input Timing Reference Level . . . . . . Differential Cross–Point

ZQ for 50 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ω

READ/WRITE CYCLE TIMING (See Note 1)

MCM69R536–5

MCM69R618–5

MCM69R536–6

MCM69R618–6

MCM69R536–7

MCM69R618–7

MCM69R536–8

MCM69R618–8

Parameter

Cycle Time

Symbol

Min

5

Max

—

Min

6

Max

—

3

Min

7

Max

—

Min

8

Max

—

4

Unit Notes

t

ns

KHKH

Clock High Pulse Width

t

2

—

2.4

1

2.8

1

—

3.2

1

KHKL

KLKH

Clock Low Pulse Width

t

2

—

Clock High to Output Low–Z

Clock High to Output Valid

Clock High to Output Hold

Clock High to Output High–Z

t

1

—

ns

2, 3

KHQX1

t

—

0.5

—

0.5

2.5

—

3.5

—

KHQV

KHQX

t

0.5

—

3

0.5

—

0.5

—

4

2

t

2.5

—

3.5

—

2, 3

KHQZ

GLQX

Output Enable Low to Output

Low–Z

t

0.5

—

0.5

—

Output Enable Low to Output

Valid

t

—

2.5

—

3

—

3.5

—

4

ns

GLQV

Output Enable to Output Hold

t

0.5

—

0.5

—

3

0.5

—

0.5

—

4

ns

GHQX

Output Enable High to Output

High–Z

t

2.5

3.5

2, 3

GHQZ

Setup Times:

Hold Times:

NOTES:

Address

Data In

Chip Select

Write Enable

t

0.5

—

0.5

—

0.5

—

0.5

—

ns

AVKH

DVKH

t

SVKH

t

WVKH

Address

Data In

Chip Select

Write Enable

t

1

—

1

—

ns

KHAX

KHDX

t

KHSX

t

KHWX

1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications

(e.g., t ) or at frequencies that exceed the applied K clock frequency.

KHKL

2. This parameter is sampled and not 100% tested.

3. Measured at ± 200 mV from steady state.

AC INPUT CHARACTERISTICS

Parameter

Symbol

Min

Max

Note

AC Input Logic High (See Figure 4)

AC Input Logic Low (See Figure 2 and 4)

Input Reference Peak to Peak ac Voltage

Clock Input Differential Voltage

V

(ac)

V

ref

+ 200 mV

—

IH

V

—

V

– 200 mV

1

2

3

IL

ref

V

ref

5% V (dc)

ref

V

dif

400 mV

V

DDQ

+ 600 mV

NOTES:

1. Inputs may undershoot to – 0.5 V (peak) for up to 20% t

2. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of V is supported, the peak to peak ac component

(e.g., 2 ns at a clock cycle time of 10 ns).

KHKH

ref

superimposed on V may not exceed 5% of the dc component of V

.

ref

3. Minimum differential input voltage required for differential input clock operation.

MCM69R536•MCM69R618

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TIMING LIMITS

The table of timing values shows either a minimum

or a maximum limit for each parameter. Input require-

ments are specified from the external system point of

view. Thus, address setup time is shown as a mini-

mum since the system must supply at least that much

time. On the other hand, responses from the memory

are specified from the device point of view. Thus, the

access time is shown as a maximum since the device

never provides data later than that time.

0.75 V

V

/2

DDQ

V

ref

50

Ω

DEVICE

UNDER

TEST

50

Ω

250

ZQ

Figure 1. AC Test Load

V

OH

V

SS

50%

100%

20% t

KHKH

Figure 2. Undershoot Voltage

V

DDQ

V

TR

CROSSING POINT

V

DIF

V

*

CM

V

CP

V

SS

*V , the Common Mode Input Voltage, equals V

CM TR

– ((V

– V )/2).

TR CP

Figure 3. Differential Inputs/Common Mode Input Voltage

V

DDQ

(ac)

V

IH

V

ref

V

(ac)

IL

V

SS

Figure 4. AC Input Conditions

MCM69R536•MCM69R618

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REGISTER/REGISTER READ–WRITE–READ CYCLES

t

KHKL

KHKH

CK

SA

SS

SW

t

AVKH

KLKH

t

KHAX

A0

A1

A2

A3

A4

t

SVKH

t

KHSX

t

WVKH

t

KHWX

SBx

G

V

IL

t

KHQX1

t

KHQZ

KHQV

t

KHDX

KHQX

t

KHQX

Q1

DVKH

DQx

Q–1

Q0

D2

Q3

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REGISTER/REGISTER READ–WRITE–READ

(G Controlled)

t

KHKL

KHKH

CK

SA

t

AVKH

KLKH

t

KHAX

A0

A1

A2

A3

A4

SS

V

IL

SW

SBx

G

t

GLQV

GLQX

t

GHQZ

t

GHQX

DQx

Q–1

Q0

Q1

D2

Q3

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occur, but the outputs will be deselected as in a normal write

cycle.

FUNCTIONAL OPERATION

READ AND WRITE OPERATIONS

LATE WRITE

All control signals except G are registered on the rising

edge of the CK clock. These signals must meet the setup

and hold times shown in the AC Characteristics table. On the

rising edge of the following clock, read data is clocked into

The write address is sampled on the first rising edge of

clock and write data is sampled on the following rising edge.

The late write feature is implemented with single stage

write buffering. Write buffering is transparent to the user. A

comparator monitors the address bus and, when necessary,

routes buffer contents to the outputs to assure coherent op-

eration. This occurs in all cases whether there is a byte write

or a full word is written.

the output register and available at the outputs at t

. Dur-

KHQV

ing this same cycle a new read address can be applied to the

address pins.

A deselect cycle (dead cycle) must occur prior to a write

cycle. Read cycles may follow write cycles immediately.

G, SS, and SW control output drive. Chip deselect via a

high on SS at the rising edge of the CK clock has its effect on

the output drivers after the next rising edge of the CK clock.

SW low deselects the output drivers immediately (as regis-

tered by CK). Output drive is also controlled directly by out-

put enable, G. No clock edges are required to generate

output disable with G. G asynchronously enables the output

drivers.

PROGRAMMABLE IMPEDANCE OPERATION

The designer can program the RAMs output buffer imped-

ance by terminating the ZQ pin to V

through a precision

SS

resistor (RQ). The value of RQ is five times the output imped-

ance desired. For example, 250 Ω resistor will give an output

impedance of 50 Ω.

Impedance updates occur continuously and the frequency

of the update is based on the subdivided K clock. Note that if

the K clock stops so does the impedance update.

The actual change in the impedance occurs in small incre-

ments and is monotonic. There are no significant distur-

bances that occur on the output because of this smooth

update method.

Output data will be valid the latter of t

and t

.

GLQV

KHQV

Outputs will begin driving at t

vious data until t or t

. Outputs will hold pre-

KHQX1

.

GHQX

KHQX

WRITE AND BYTE WRITE FUNCTIONS

The impedance update is not related to any particular type

of cycle because the impedance is updated continuously and

is based on the K clock. Updates occur regardless of wheth-

er the the device is performing a read, write or a deselect

cycle and does not depend on the state of G.

At power up, the output impedance defaults to approxi-

mately 50 Ω. It will take 4,000 to 16,000 cycles for the imped-

ance to be completely updated if the programmed

impedance is much higher or lower than 50 Ω.

Note that in the following discussion the term “byte” refers

to nine bits of the RAM I/O bus. In all cases, the timing pa-

rameters described for synchronous write input (SW) apply

to each of the byte write enable inputs (SBa, SBb, etc.).

Byte write enable inputs have no effect on read cycles.

This allows the system designer not interested in performing

byte writes to connect the byte enable inputs to active low

(V ). Reads of all bytes proceed normally and write cycles,

SS

activated via a low on SW, and the rising edge of the CK

clock, write the entire RAM I/O width. This way the designer

is spared having to drive multiple write input buffer loads.

Byte writes are performed using the byte write enable in-

puts in conjunction with the synchronous write input (SW). It

is important to note that writing any one byte will inhibit a read

of all bytes at the current address. The RAM cannot simulta-

neously read one byte and write another at the same ad-

dress. A write cycle initiated with none of the byte write

enable inputs active is neither a read or a write. No write will

The output buffers can also be programmed in a minimum

impedance configuration by connecting ZQ to V

.

DD

POWER UP AND INITIALIZATION

Once supplies have reached specification levels, a mini-

mum dwell of 1.0 ms with CK clock inputs cycling is required

before beginning normal operations. At power up the output

impedance will be set at approximately 50 Ω as stated

above.

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SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION

OVERVIEW

1149.1 compliant TAPs. The TAP operates using convention-

al JEDEC Standard 8–1B Low Voltage (3.3 V) TTL/CMOS

logic level signaling.

The serial boundary scan test access port (TAP) on this

RAM is designed to operate in a manner consistent with

IEEE Standard 1149.1–1990 (commonly referred to as

JTAG), but does not implement all of the functions required

for 1149.1 compliance. Certain functions have been modified

or eliminated because their implementation places extra de-

lays in the RAMs critical speed path. Nevertheless, the RAM

supports the standard TAP controller architecture. (The TAP

controller is the state machine that controls the TAPs opera-

tion) and can be expected to function in a manner that does

not conflict with the operation of devices with Standard

DISABLING THE TEST ACCESS PORT

It is possible to use this device without utilizing the TAP. To

disable the TAP Controller without interfering with normal op-

eration of the device, TCK must be tied to V

to preclude

SS

mid level inputs. TDI and TMS are designed so an undriven

input will produce a response identical to the application of a

logic 1, and may be left unconnected. But they may also be

tied to V

nected.

through a 1 k resistor. TDO should be left uncon-

DD

TAP DC OPERATING CHARACTERISTICS

(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)

A

Parameter

Symbol

Min

Max

V + 0.3

DD

Unit

V

Note

Logic Input Logic High

Logic Input Logic Low

Logic Input Leakage Current

Output Logic Low

V

IH

1

2.0

– 0.3

—

V 1

IL

0.8

± 5

0.2

—

V

I

µA

V

1

2

3

4

5

lkg

V 1

OL

—

Output Logic High

V

OH

1

V

– 0.2

V

DD

Output Logic Low

V 2

OL

—

0.4

—

V

Output Logic High

V

OH

2

2.4

V

NOTES:

1. 0 V ≤ V ≤ V

for all logic input pins.

= 0.2 V. Sampled, not 100% tested.

1| ≤ 100 µA @ V – 0.2 V. Sampled, not 100% tested.

in

DD

2. I 1 ≤ 100 µA @ V

OL OL

3. |I

OH

DDQ

= 0.4 V.

4. I 2 ≤ 8 mA @ V

OL

5. |I

OL

2| ≤ 8 mA @ V

= 2.4 V.

OH

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TAP AC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)

A

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)

Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V

Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V

Output Test Load . . . . . . 50 Ω Parallel Terminated T–line with 20 pF

Receiver Input Capacitance

Test Load Termination Supply Voltage (V ) . . . . . . . . . . . . . . . 1.5 V

T

TAP CONTROLLER TIMING

Parameter

Cycle Time

Symbol

Min

100

40

10

0

Max

—

20

Unit

ns

Notes

t

THTH

Clock High Time

t

THTL

Clock Low Time

t

TLTH

TMS Setup

t

MVTH

THMX

TMS Hold

TDI Valid to TCK High

TCK High to TDI Don’t Care

Capture Setup

t

DVTH

THDX

t

1

CS

Capture Hold

t

CH

TCK Low to TDO Unknown

TCK Low to TDO Valid

NOTES:

t

TLQX

—

TLOV

1. t + t

CS CH

defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.

AC TEST LOAD

1.5 V

50

Ω

DEVICE

UNDER

TEST

50

Ω

20 pF

TAP CONTROLLER TIMING DIAGRAM

t

THTH

t

TLTH

TEST CLOCK

(TCK)

t

THTL

t

THMX

t

MVTH

TEST MODE SELECT

(TMS)

t

THDX

t

DVTH

TEST DATA IN

(TDI)

t

TLQV

TLQX

TEST DATA OUT

(TDO)

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BOUNDARY SCAN REGISTER

TEST ACCESS PORT PINS

The boundary scan register is identical in length to the

number of active input and I/O connections on the RAM (not

counting the TAP pins). This also includes a number of place

holder locations (always set to a logic 1) reserved for density

upgrade address pins. There are a total of 70 bits in the case

of the x36 device and 51 bits in the case of the x18 device.

The boundary scan register, under the control of the TAP

controller, is loaded with the contents of the RAMs I/O ring

when the controller is in capture–DR state and then is placed

between the TDI and TDO pins when the controller is moved

to shift–DR state. Several TAP instructions can be used to

activate the boundary scan register.

TCK — TEST CLOCK (INPUT)

Clocks all TAP events. All inputs are captured on the rising

edge of TCK and all outputs propagate from the falling edge

of TCK.

TMS — TEST MODE SELECT (INPUT)

The TMS input is sampled on the rising edge of TCK. This

is the command input for the TAP controller state machine.

An undriven TMS input will produce the same result as a

logic one input level.

TDI — TEST DATA IN (INPUT)

The Bump/Bit Scan Order tables describe which device

bump connects to each boundary scan register location. The

first column defines the bit’s position in the boundary scan

register. The shift register bit nearest TDO (i.e., first to be

shifted out) is defined as bit 1. The second column is the

name of the input or I/O at the bump and the third column is

the bump number.

The TDI input is sampled on the rising edge of TCK. This is

the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is deter-

mined by the state of the TAP controller state machine and

the instruction that is currently loaded in the TAP instruction

register (refer to Figure 6, TAP Controller State Diagram). An

undriven TDI pin will produce the same result as a logic one

input level.

IDENTIFICATION (ID) REGISTER

The ID Register is a 32–bit register that is loaded with a

device and vendor specific 32–bit code when the controller is

put in capture–DR state with the IDCODE command loaded

in the instruction register. The code is loaded from a 32 bit

on–chip ROM. It describes various attributes of the RAM as

indicated below. The register is then placed between the TDI

and TDO pins when the controller is moved into shift–DR

state. Bit 0 in the register is the LSB and the first to reach

TDO when shifting begins.

TDO — TEST DATA OUT (OUTPUT)

Output that is active depending on the state of the TAP

state machine (refer to Figure 6, TAP Controller State Dia-

gram). Output changes in response to the falling edge of

TCK. This is the output side of the serial registers placed be-

tween TDI and TDO.

TRST — TAP RESET

This device does not have a TRST pin. TRST is optional in

IEEE 1149.1. The test–logic reset state is entered while TMS

is held high for five rising edges of TCK. Power on reset cir-

cuitry is included internally. This type of reset does not affect

the operation of the system logic. The reset affects test logic

only.

ID Register Presence Indicator

Bit #

0

1

Value

Motorola JEDEC ID Code (Compressed Format, per

IEEE Standard 1149.1 – 1990

TEST ACCESS PORT REGISTERS

OVERVIEW

Bit #

11

10

9

8

7

6

5

4

3

2

1

Value

0

1

0

The various TAP registers are selected (one at a time) via

the sequences of ones and zeros input to the TMS pin as the

TCK is strobed. Each of the TAPs registers are serial shift

registers that capture serial input data on the rising edge of

TCK and push serial data out on subsequent falling edge of

TCK. When a register is selected it is “placed” between the

TDI and TDO pins.

Reserved For Future Use

Bit #

17

16

15

14

13

12

Value

x

Device Width

Configuration

32K x 36

Bit #

Value

22

0

21

20

1

19

0

18

0

INSTRUCTION REGISTER

0

The instruction register holds the instructions that are

executed by the TAP controller when it is moved into the run

test/idle or the various data register states. The instructions

are three bits long. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction regis-

ter is automatically preloaded with the IDCODE instruction at

power–up or whenever the controller is placed in test–logic–

reset state.

64K x 18

0

1

Device Depth

Configuration

32K x 36

Bit #

Value

27

0

26

0

25

0

24

1

23

1

64K x 18

0

1

0

Revision Number

BYPASS REGISTER

Bit #

31

30

29

28

The bypass register is a single bit register that can be

placed between TDI and TDO. It allows serial test data to be

passed through the RAMs TAP to another device in the scan

chain with as little delay as possible.

Value

x

Figure 5. ID Register Bit Meanings

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MCM69R536 Bump/Bit Scan Order

MCM69R618 Bump/Bit Scan Order

BIT

No.

Signal

Name

Bump

ID

Bit

No.

Signal

Name

Bump

ID

Bit

No.

Signal

Name

Bump

ID

Bit

No.

Signal

Name

Bump

ID

1

M2

SA

5R

4P

4T

6R

5T

7T

6P

7P

6N

7N

6M

6L

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

NC

3B

2B

3A

3C

2C

2A

2D

1D

2E

1E

2F

2G

1G

2H

1H

3G

4D

4E

4G

4H

4M

3L

1

M2

SA

5R

6T

4P

6R

5T

7T

7P

6N

6L

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

SBb

ZQ

3G

4D

4E

4G

4H

4M

2K

1L

2

3

SA

3

SA

SS

4

SA

4

SA

NF

5

SA

5

SA

NF

6

ZZ

SA

6

ZZ

SW

DQb

SA

7

DQa

SBa

CK

DQc

SBc

ZQ

7

DQa

SBa

CK

8

9

2M

1N

2P

3T

2R

4N

2T

3R

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

7K

5L

4L

7L

CK

4K

4F

6H

7G

6F

7E

6D

6A

6C

5C

5A

6B

5B

3B

2B

3A

3C

2C

2A

1D

2E

2G

1H

SA

6K

7K

5L

G

SA

DQa

SA

M1

4L

CK

4K

4F

5G

7H

6H

7G

6G

6F

7E

6E

7D

6D

6A

6C

5C

5A

6B

5B

SS

G

NF

SBb

DQb

SA

NF

SW

SBd

DQd

SA

1K

2K

1L

SA

NC

2L

NC

2M

1N

2N

1P

2P

3T

2R

4N

3R

NC

SA

DQb

SA

NC

SA

35

NC

M1

NOTES:

1. TheNC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced

to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.

2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation.

3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV

of a V

or V

supply rail to ensure consistent results.

SS

DD

4. ZZ must remain at V during boundary scan to ensure consistent results.

IL

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expected. RAM input signals must be stabilized for long

enough to meet the TAPs input data capture set–up plus hold

time (t plus t ). The RAMs clock inputs need not be

TAP CONTROLLER INSTRUCTION SET

OVERVIEW

CS CH

paused for any other TAP operation except capturing the I/O

ring contents into the boundary scan register.

There are two classes of instructions defined in the Stan-

dard 1149.1–1990; the standard (public) instructions, and de-

vice specific (private) instructions. Some public instructions,

are mandatory for 1149.1 compliance. Optional public

instructions must be implemented in prescribed ways.

Although the TAP controller in this device follows the

1149.1 conventions, it is not 1194.1 compliant because some

of the mandatory instructions are not fully implemented. The

TAP on this device may be used to monitor all input and I/O

pads, but can not be used to load address, data or control

signals into the RAM or to preload the I/O buffers. In other

words, the device will not perform Standard 1149.1 EXTEST,

INTEST or the preload portion of the SAMPLE/PRELOAD

command.

When the TAP controller is placed in capture–IR state the

two least significant bits of the instruction register are loaded

with 01. When the controller is moved to the shift–IR state

the instruction register is placed between TDI and TDO. In

this state the desired instruction is serially loaded through the

TDI input (while the previous contents are shifted out at

TDO). For all instructions, the TAP executes newly loaded

instructions only when the controller is moved to update–IR

state. The TAP instruction sets for this device are listed in the

following tables.

Moving the controller to shift–DR state then places the

boundary scan register between the TDI and TDO pins. Be-

cause the PRELOAD portion of the command is not imple-

mented in this device, moving the controller to the

update–DR state with the SAMPLE/PRELOAD instruction

loaded in the instruction register has the same effect as the

pause–DR command. This functionality is not Standard

1149.1 compliant.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It

is to be executed whenever the instruction register, whatever

length it may be in the device, is loaded with all logic 0s. EX-

TEST is not implemented in this device. Therefore this de-

vice is not 1149.1 compliant. Nevertheless, this RAMs TAP

does respond to an all zeros instruction, as follows. With the

EXTEST (000) instruction loaded in the instruction register

the RAM responds just as it does in response to the SAM-

PLE / PRELOAD instruction described above, except the

RAM outputs are forced to high–Z any time the instruction is

loaded.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded

into the ID register when the controller is in capture–DR

mode and places the ID register between the TDI and TDO

pins in shift–DR mode. The IDCODE instruction is the default

instruction loaded in at power up and any time the controller

is placed in the test–logic–reset state.

STANDARD (PUBLIC) INSTRUCTIONS

BYPASS

The BYPASS instruction is loaded in the instruction regis-

ter when the bypass register is placed between TDI and

TDO. This occurs when the TAP controller is moved to the

shift–DR state. This allows the board level scan path to be

shortened to facilitate testing of other devices in the scan

path.

THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION

SAMPLE–Z

SAMPLE/PRELOAD

If the SAMPLE–Z instruction is loaded in the instruction

register, all RAM outputs are forced to an inactive drive state

(high–Z) and the boundary scan register is connected be-

tween TDI and TDO when the TAP controller is moved to the

shift–DR state.

Sample/preload is a Standard 1149.1 mandatory public

instruction. When the sample/preload instruction is loaded in

the Instruction register, moving the TAP controller into the

capture–DR state loads the data in the RAMs input and I/O

buffers into the boundary scan register. Because the RAM

clock(s) are independent from the TAP clock (TCK) it is pos-

sible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e., in a metastable

state). Although allowing the TAP to sample metastable in-

puts will not harm the device, repeatable results can not be

THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION

NOOP

Do not use these instructions; they are reserved for future

use.

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STANDARD (PUBLIC) INSTRUCTION CODES

Instruction

EXTEST

Code*

Description

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all

RAM outputs to High–Z state. *NOT 1149.1 COMPLIANT*

IDCODE

001**

100

Preloads ID register and places it between TDI and TDO.

Does not affect RAM operation.

SAMPLE / PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not

affect RAM operation.

Does not implement 1149.1 Preload function. * NOT 1149.1 COMPLIANT *

BYPASS

111

010

Places bypass register between TDI and TDO.

Does not affect RAM operation.

SAMPLE–Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all

RAM output drivers to High–Z.

*Instruction codes expressed in binary, MSB on left, LSB on right.

**Default instruction automatically loaded at power–up and in test–logic–reset state.

STANDARD (PRIVATE) INSTRUCTION CODES

Instruction

NO OP

Code*

011

Description

Do not use these instructions; they are reserved for future use.

NO OP

101

110

*Instruction codes expressed in binary, MSB on left, LSB on right.

TEST–LOGIC

RESET

1

0

1

RUN–TEST/

IDLE

SELECT

DR–SCAN

SELECT

IR–SCAN

1

0

1

CAPTURE–DR

CAPTURE–IR

0

SHIFT–DR

1

SHIFT–IR

1

0

1

EXIT1–DR

0

EXIT1–IR

0

PAUSE–DR

1

PAUSE–IR

1

0

EXIT2–DR

1

EXIT2–IR

1

UPDATE–DR

UPDATE–IR

1

0

1

0

NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.

Figure 6. TAP Controller State Diagram

MCM69R536•MCM69R618

18

MOTOROLA FAST SRAM

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ORDERING INFORMATION

(Order by Full Part Number)

69R536

MCM

69R618

XX

X

Motorola Memory Prefix

Part Number

R = Tape and Reel, Blank = Tray

Speed (5 = 5 ns, 6 = 6 ns, 7 = 7 ns, 8 = 8 ns)

Package (ZP = PBGA)

Full Part Numbers — MCM69R536ZP5

MCM69R618ZP5

MCM69R536ZP6

MCM69R618ZP6

MCM69R536ZP7

MCM69R618ZP7

MCM69R536ZP8

MCM69R618ZP8

MCM69R536ZP5R

MCM69R618ZP5R

MCM69R536ZP6R MCM69R536ZP7R MCM69R536ZP8R

MCM69R618ZP6R MCM69R618ZP7R MCM69R618ZP8R

MCM69R536•MCM69R618

19

MOTOROLA FAST SRAM

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Freescale Semiconductor, Inc.

PACKAGE DIMENSIONS

ZP PACKAGE

7 X 17 BUMP PBGA

CASE 999–01

NOTES:

0.20 (0.008)

4X

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

A

–W–

2. CONTROLLING DIMENSION: MILLIMETER.

PIN 1A

IDENTIFIER

7

6

5

4

3 2 1

MILLIMETERS

MIN MAX

14.00 BSC

22.00 BSC

INCHES

MIN MAX

0.551 BSC

0.866 BSC

A

B

C

D

E

F

G

H

J

DIM

A

B

C

D

E

–––

0.60

0.50

1.30

2.40

–––

0.024

0.020

0.051

0.094

0.90

0.70

1.70

0.035

0.028

0.067

B

–L–

S

P

F

K

L

G

K

N

P

1.27 BSC

0.050 BSC

M

N

P

R

T

0.80

11.90

19.40

1.00

12.10

19.60

0.031

0.469

0.764

0.039

0.476

0.772

16X G

R

S

7.62 BSC

20.32 BSC

0.300 BSC

0.800 BSC

U

119X

D

N

6X

G

S

0.30 (0.012)

0.10 (0.004)

T

W

L

R

TOP VIEW

BOTTOM VIEW

0.25 (0.010)

T

F

0.35 (0.014)

T

0.15 (0.006)

T

C

–T–

K

SIDE VIEW

E

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and

Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Mfax is a trademark of Motorola, Inc.

How to reach us:

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CUSTOMER FOCUS CENTER: 1-800-521-6274

MCM69R536/D

◊

MCM69R536•MCM69R618

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型号：	MCM69R536ZP5
厂家：	NXP
描述：	32KX36 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 静态存储器
文件：	总20页 (文件大小：378K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCM69R536ZP5 [NXP]

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