MCZ234653EF [NXP]
1.0 A Negative Voltage Hot Swap Controller;
| 型号： | MCZ234653EF |
| 厂家： | 
NXP |
| 描述： | 1.0 A Negative Voltage Hot Swap Controller |
| 文件： | 总24页 (文件大小：1805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Archived by Freescale Semiconductor, Inc., 2008
Document Number: MC34653
Rev. 8.0, 2/2007
escale Semiconductor
Advance Information
1.0 A Negative Voltage Hot
Swap Controller
34653
The 34653 is a highly integrated -48 V hot swap controller with an
internal Power MOSFET. It provides the means to safely install and
remove boards from live -48 V backplanes without having to power
down the entire system. It regulates the inrush current, from the
supply to the load’s filter capacitor, to a user-programmable limit,
allowing the system to safely stabilize. A disable function allows the
user to disable the 34653 manually or through a microprocessor and
safely disconnect the load from the main power line.
HOT SWAP
The 34653 has active high and active low power good output
signals that can be used to directly enable a power module load.
Undervoltage and overvoltage detection circuitry monitors the input
voltage to check that it is within its operating range. A start-up delay
timer ensures that it is safe to turn on the Power MOSFET and charge
the load capacitor.
EF SUFFIX (Pb-Free)
98ASB42564B
A two-level current limit approach to controlling the inrush current
and switching on the load limits the peak power dissipation in the
Power MOSFET. Both current limits are user programmable.
8-PIN SOICN
Features
• Integrated Power MOSFET and Control IC in a Small Outline
Package
• Input Voltage Operation Range from -39 V to -74 V
• Programmable Overcurrent Limit with Auto Retry
• Programmable Charging Current Limit Independent of Load
Capacitor
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
MCZ34653EF/R2
MC34653EF/R2
-40°C to 85°C
8 SOICN
• Start-Up and Retry Delay Timer
• Overvoltage and Undervoltage Detection
• Active High and Low Power Good Output Signals
• Thermal Shutdown
• Pb-Free Packaging Designated by Suffix Code EF
34653
DISABLE
Application
Dependent
PG
GND
System
VPWR
PG
VOUT
Load
Power
Supply
(Backplane)
-48 V
VIN
Optional
External
Components
ICHG
Optional
External
Components
ILIM
Figure 1. 34653 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Archived by Freescale Semiconductor, Inc., 2008
RNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Referenced VPWR
Logic
DISABLE
VPWR
Fixed
Oscillator
PG
-
UVLO
UV
1.3 V
1.3 V
1.3 V
+
Logic
-
PG
+
+
-
OV
VIN
Thermal
Shutdown
3.1 V
ILIM
External
Resistors
Detection
Programmable
Current Limit
8.0 µA
Gate Control
Driver
ICHG
Sensor MOSFET
Power MOSFET
VOUT
VIN
Figure 2. 34653 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
1
2
8
7
PG
PG
ICHG
ILIM
3
4
VOUT
VIN
6
5
DISABLE
VPWR
Figure 3. 8-SOICN Pin Connections
Table 1. 8-SOICN Pin Definitions
A functional description of each pin can be found in the FUNCTIONAL PIN DESCRIPTION section beginning on page 8.
Pin
Pin Name
Formal Name
Definition
1
Power Good Output
(Active High)
This is an active high power good output signal. This pin is referenced to VIN.
PG
2
3
4
5
6
Power Good Output
(Active Low)
This is an active low power good output signal. This pin is referenced to VIN.
PG
VOUT
VIN
Voltage Output
This pin is the drain of the internal Power MOSFET and supplies a current limited voltage
to the load.
Negative Supply
Voltage Input
This is the most negative power supply input. All pins except DISABLE are referenced
to this input.
VPWR
DISABLE
Positive Supply
Voltage Input
This is the most-positive power supply input. The load connects between this pin and the
VOUT pin.
Disable Input Control This pin is used to easily disconnect or connect the load from the main power line by
disabling or enabling the 34653. It can also be used to reset the fault conditions that
cause a “Power No Good” signal. This pin is referenced to VPWR.
7
8
ILIM
Current Limit Control This pin is used to set the overcurrent limit during normal operation.
ICHG
Charging Current
Limit Control
This pin is used to set the load’s input capacitor charging current limit, hence limiting the
inrush current to a known constant value.
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CTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
V
85
V
mJ
A
PWR
Varies (1)
1.0
Power MOSFET Energy Capability
EMOSFET
Continuous Output Current (2)
O(CONT)
I
Maximum Voltage
DISABLE Pin
V
—
—
—
—
V
- 0.3 to V
+ 5.5
PWR
IN
ILIM and ICHG Pins
5.0
85
85
PG Pin (V
- V )
IN
PG
PG Pin (VPG - V
)
IN
—
—
All Pins Minimum Voltage
PG, PG Maximum Current
ESD Voltage, All Pins (3)
Human Body Model
Machine Model
-0.3
V
A
V
Internally Limited
V
±2000
±200
ESD3
V
ESD4
THERMAL RATINGS
Storage Temperature
Operating Temperature
T
-65 to 150
°C
°C
STG
T
Ambient (4)
Junction
A
-40 to 85
T
-40 to 160
J
(6)
Peak Package Reflow Temperature During Reflow (5)
,
TPPRT
Note 6
°C
,
°C/W
(8)
Thermal Resistance (7)
R
167
115
θJA
Junction-to-Ambient, Single-Layer Board (9)
Junction-to-Ambient, Four-Layer Board (10)
Notes
R
θJMA
1. Refer to the section titled Power MOSFET Energy Capability on page 21 for a detailed explanation on this parameter.
2. Continuous output current capability so long as T is ≤ 160°C.
J
3. ESD1 testing is performed in accordance with the Human Body Model (C
=100 pF, R
=1500 Ω), ESD2 testing is performed in
ZAP
ZAP
accordance with the Machine Model (C
=200 pF, R
=0 Ω).
ZAP
ZAP
4. The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
7. Refer to the section titled Thermal Shutdown on page 15 for more thermal resistance values under various conditions.
8. The VOUT and VIN pins comprise the main heat conduction paths.
9. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the
board.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 36 V ≤ VPWR ≤ 80 V and -40°C ≤ TA ≤ 85°C. All voltages are referenced to VIN unless
otherwise noted.
Characteristic
POWER SUPPLY PIN (VPWR)
Symbol
Min
Typ
—
Max
Unit
Supply Voltage
V
V
36
80
V
V
PWR
PWR
Operating Voltage Range
V
V
UV(ON)
—
OV(ON)
1400
Supply Current, Device Enabled, Default Mode, Normal Operation (11)
IN
I
900
μA
V
Undervoltage Lockout Threshold (UVLO)
V
7.0
6.0
—
8.0
7.0
1.0
9.0
8.0
—
Rising
UVLOR
V
Falling
UVLOF
Hysteresis
V
UVLOHY
UNDERVOLTAGE CONTROL
UV Threshold (Default)
Rising
V
V
V
—
—
—
38
37
—
—
—
UV(ON)
Falling
V
UV(OFF)
Hysteresis
1.0
V
UVHY
OVERVOLTAGE CONTROL
OV Threshold (Default)
Rising
V
—
—
—
78
76
—
—
—
OV(OFF)
Falling
V
OV(ON)
Hysteresis
2.0
V
OVHY
DISABLE INPUT CONTROL PIN (DISABLE) (12)
DISABLE Input Voltage
Inactive State
V
V
V
V
-1.2
—
—
—
V
+ 1.2
DISL
PWR
PWR
Active State, Positive Signal
Active State, Negative Signal
V
V
+2.0
—
DISHP
DISHN
PWR
—
V
-2.0
PWR
DISABLE Input Current
I
μA
DIS
V
V
V
= V
= V
= V
+ 3.3 V
- 3.3 V
20
-20
-50
60
-60
140
DIS
DIS
DIS
PWR
PWR
IN
-140
-250
-150
Notes
11. The supply current depends on operation mode and can be calculated as follows:
•Start-Up Mode: IIN = 539 μA + 548 μ * I (A) + 216 μ * I (A) + VPWR(V) / 460(kΩ)
CHG
LIM
•Normal Mode: IIN = 539 μA + 240 μ * I (A) + 288 μ * I
(A) + VPWR(V) / 460(kΩ)
LOAD
LIM
•Overcurrent Mode: IIN = 539 μA + 612 μ * I (A) + VPWR(V) / 460(kΩ)
LIM
•Disable Mode: IIN = 539 μA + 240 μ * I (A) + I (μA) + VPWR(V) / 460(kΩ)
LIM
DIS
12. Referenced to VPWR.
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CTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 36 V ≤ VPWR ≤ 80 V and -40°C ≤ TA ≤ 85°C. All voltages are referenced to VIN unless
otherwise noted.
Characteristic
CURRENT LIMIT PINS (ILIM, ICHG)
Symbol
Min
Typ
Max
Unit
Overcurrent Limit Steady State
Default
I
A
LIM
—
—
—
1.0
—
—
—
Maximum with External Resistor
Minimum with External Resistor
1.25
0.15
Current Limit During Start-Up
Default
I
A
CHG
—
—
—
—
0.1
0.5
—
—
—
—
Maximum with External Resistor
Minimum with External Resistor
0.05
5.0
Short Circuit Current Limit
I
A
%
%
%
V
SHORT
I
I
I
Current Limit Hysteresis
Current Limit Accuracy
I
—
-20
-35
—
12
—
—
20
35
—
—
LIM
LIMHY
I
LIM
LIMCLA
Current Limit Accuracy
I
—
CHG
CHGCLA
ILIM Pin Voltage
V
3.1
129
ILIM
I
to R
Setting Constant
ILIM
—
A
kΩ
ILIMCNS
LIM
*
I
I
Reference Current
I
—
—
-8.0
335
—
—
μA
CHG
CHG
CHGOUT
CHGCNS
to R
Setting Constant
I
kΩ/A
ICHG
POWER GOOD PINS (PG, PG) (13)
Power Good Output Low Voltage
V
V
PGL
I
= 1.6 mA
—
—
—
—
0.5
10
PG
Power Good Leakage Current
Power Good Current Limit
I
μA
PGLG
I
mA
PGCL
V
or VPG = 3.0 V
—
—
—
—
—
7.0
50
—
PG
OUTPUT VOLTAGE PIN (VOUT)
VOUT Leakage Current
I
μA
OUTLG
POWER MOSFET
R
144
mΩ
ON Resistance @ 25°C
DS(ON)
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Temperature Hysteresis
T
—
—
160
25
—
—
°C
°C
SD
T
SDHY
Notes
13. Referenced to VIN.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 36 V ≤ VPWR ≤ 80 V and -40°C ≤ TA ≤ 85°C. All voltages are referenced to VIN unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
UNDERVOLTAGE CONTROL
Undervoltage Active to Gate Low Filter Time
OVERVOLTAGE CONTROL
t
t
—
1.0
—
ms
UVAL
OVAL
Overvoltage Active to Gate Low Filter Time
DISABLE INPUT CONTROL PIN (DISABLE) (14)
DISABLE Active to Gate Low Filter Time
CURRENT LIMIT CONTROL PINS (ILIM, ICHG)
Short Circuit Protection Delay
—
—
1.0
1.0
—
—
ms
ms
t
DISAL
t
t
—
—
—
—
10
—
—
μs
μs
SCPD
OCFT
Overcurrent Limit Filter Time
100
3.0
Overcurrent Limit Regulation Time
t
ms
ms
OC
I
Rise Time
t
ICHGR
CHG
—
1.0
—
—
—
Default
Adjustable with an External Capacitor
1.0
POWER GOOD OUTPUT PINS (PG, PG) (15)
Power Good Output Delay Time, from Power MOSFET Enhancement to PG
and PG Asserted
t
ms
ms
PG
10
28
46
FAULT TIMER
Start-Up and Retry Delay Timer
Default
t
TIMER
130
200
270
Notes
14. Referenced to VPWR.
15. Referenced to VIN.
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CTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Most telecom and data transfer networks require that
circuit boards be inserted and removed from the system
without powering down the entire system. When a circuit
board is inserted into or removed from a live backplane, the
filter or bypass capacitors at the input of the board’s power
module or switching power supply can cause large transient
currents when being charged or discharged. These currents
can cause severe and permanent damage to the boards, thus
making the system unstable. Figure 4 displays the inrush
current to the filter capacitor if a hot swap device is absent.
The inrush current reached an unsafe value of more than
55 A.
voltages in a controlled manner and regulating the inrush
current to a user-programmable limit, thus allowing the
system to safely stabilize (see Figure 5). The 34653 provides
protection against overcurrent, undervoltage, overvoltage,
and overtemperature. Furthermore, it protects the system
from short circuits.
Figure 5. Circuit Board Insertion With the Hot Swap
Device, Inrush Current Limited
By integrating the control circuitry and the Power MOSFET
switch into a space-efficient package, the 34653 offers a
complete, cost-effective, and simple solution that takes much
less board space than a similar part with an external Power
MOSFET requires.
Figure 4. Circuit Board Insertion Without a
Hot Swap Device, Inrush Current Not Limited
The 34653 can be used in -48 V telecom and networking
systems, servers, electronic circuit breakers, -48 V
distributed power systems, negative power supply control,
and central office switching.
The 34653 is an integrated negative voltage hot swap
controller with an internal Power MOSFET. The 34653
resides on the plug-in boards and allows the boards to be
safely inserted or removed by powering up the supply
FUNCTIONAL PIN DESCRIPTION
The signal is deactivated under the following conditions:
NEGATIVE SUPPLY INPUT VOLTAGE (VIN)
• Power is turned off.
This is the most negative power supply input. All pins
except DISABLE, PG, and PG are referenced to this input.
• The device is disabled for more than 1.0 ms.
• The device exceeded its thermal shutdown threshold for
more than 12 μs.
POWER GOOD OUTPUT (ACTIVE HIGH) (PG)
• The device is in overvoltage or undervoltage mode for
The PG pin is the active high power good output signal that
is used to enable or disable a load. This signal goes active
after a successful power-up sequence and stays active as
long as the device is in normal operation and is not
experiencing any faults.
more than 1.0 ms.
• Load current exceeded the overcurrent limit for more than
3.0 ms.
This pin is referenced to VIN.
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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
POWER GOOD OUTPUT (ACTIVE LOW) PG
DISABLE INPUT CONTROL (DISABLE)
The PG pin is the active low power good output signal that
is used to enable or disable a load. This signal goes active
after a successful power-up sequence and stays active as
long as the device is in normal operation and is not
experiencing any faults.
The DISABLE pin is used to easily disconnect or connect
the load from the main power line by disabling or enabling the
34653. It can also be used to reset the fault conditions that
cause a “Power No Good” signal.
If left open or connected to VPWR, the DISABLE pin is
inactive and the device is enabled. If a positive voltage
(above VPWR) or a negative voltage (below VPWR) is applied
to DISABLE, it is active and the device is disabled. The
disable function has a 1.0 ms filter timer.
The signal is deactivated under the following conditions:
• Power is turned off.
• The device is disabled for more than 1.0 ms.
• The device exceeded its thermal shutdown threshold for
more than 12 μs.
This pin is referenced to VPWR.
• The device is in overvoltage or undervoltage mode for
CURRENT LIMIT CONTROL (ILIM)
more than 1.0 ms.
The ILIM pin is used to set the overcurrent limit during
normal operation. This pin can be left unconnected for a
default overcurrent limit value of 1.0 A or the user can
connect an external resistor between the ILIM and VIN pins
to set the overcurrent limit value. This value can vary
between 0.15 A and 1.25 A. The overcurrent detection circuit
has a 100 μs filter timer.
• Load current exceeded the overcurrent limit for more than
3.0 ms.
This pin is referenced to VIN.
OUTPUT VOLTAGE (VOUT)
The VOUT pin is the drain of the internal Power MOSFET
and supplies a current-limited voltage to the load. The load
connects between the VOUT and VPWR pins.
CHARGING CURRENT LIMIT CONTROL (ICHG)
The ICHG pin is used to set the current limit that is used to
charge the load’s input capacitor, hence limiting the inrush
current to a known constant value. This pin can be left
unconnected for a default charging current limit value of 0.1 A
and a default ICHG rise time of 1.0 ms. Or the user can
connect an external resistor between the ICHG and VIN pins
to set the current limit value between 0.05 A and 0.5 A and an
external capacitor to increase the ICHG rise time. The
recommended maximum rise time is 10 ms.
POSITIVE SUPPLY VOLTAGE INPUT (VPWR)
The VPWR pin is the most-positive power supply input.
The load connects between the VPWR and VOUT pins.
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CTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Start-Up Conditions
START-UP SEQUENCE
When power is first applied to the 34653 by connecting the
VIN pin to the negative voltage rail and the VPWR pin to the
positive voltage rail, the 34653 keeps the Power MOSFET
turned off, deactivates the power good output signals, and
resets the retry counter. If the device is disabled, no further
activities will occur and power-up would not start. If the device
is enabled, it starts to establish an internally regulated supply
voltage required for the internal circuitry. The Power
The start-up conditions are as follows:
• Input voltage is below the overvoltage turn-off threshold.
This threshold is a default.
• Input voltage is above the undervoltage turn-off threshold.
This threshold is a default.
• Die temperature is less than the thermal shutdown
temperature.
• Device is enabled.
MOSFET will stay off until the start of the charging process.
If the start-up conditions are satisfied for a time equal to
the length of the start-up timer and the retry counter is less
than or equal to 10, the device starts to turn on the Power
MOSFET gradually to control the inrush current that charges
up the load capacitor to eventually switch on the load (Point B
in Figure 6).
After the Power-ON Reset (POR) and once the
Undervoltage Lockout (UVLO) threshold is cleared, the
34653 checks for external components on two pins—ILIM
and ICHG—to set the levels of the Overcurrent Limit and the
Charging Current Limit, respectively. The device then
initiates the start-up timer (Point A in Figure 6) and checks for
the start-up conditions (see next paragraph). The duration of
the timer is a default value. For undervoltage and overvoltage
faults during power up the 34652 retries infinitely until normal
input voltage is attained. If the die temperature ever
increased beyond the thermal shutdown threshold or the
device is disabled, then the start-up timer resets and the retry
counter increments. If after 10 retries the die temperature is
still high and the device is still disabled, the 34652 will not
retry again and the power in the device must be recycled or
the device must be disabled to reset the retry counter.
Charging Process
When charging a capacitor from a fixed voltage source, a
definite amount of energy will be dissipated in the control
circuit, no matter what the control algorithm is. This energy is
equal to the energy transferred to the capacitor—½CV2.
With this in mind, the Power MOSFET in the 34653 cannot
absorb this pulse of energy instantaneously, so the pulse
must be dissipated over time. To limit the peak power
dissipation in the Power MOSFET and to spread out the
duration of the energy dissipation in the Power MOSFET, the
circuit uses a two-level current approach to controlling the
inrush current and switching on the load as explained in the
following paragraphs.
When the Power MOSFET is turned on, the current limit is
set gradually from 0 A to ICHG (between Points A and B in
Figure 7). The low charging current value and the gradual
rise time of ICHG are either defaults or they can be user
programmable (2.0 ms rise time in the example in Figure 7).
The low charging current value of ICHG is intended to limit the
temperature increase during the load capacitor charging
process, and the gradual rise to ICHG is to prevent transient
dips in the input voltage due to sharp increases in the current.
This prevents the input voltage from drooping due to current
steps acting on the input line inductance, and that in turn
prevents a premature activation of the UV detection circuit.
Figure 6. Start-Up Sequence
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL MODE
If one of the start-up conditions (list on page 10) is violated
any time from the start of the Power MOSFET enhancement
process and thereafter during normal operation, the Power
MOSFET turns off and the power good output signals
deactivate, disabling the load, and a new timer cycle starts as
explained previously. The 34653 also monitors the load
current to prevent any overload or short circuit conditions
from happening to protect the load from damage.
LOAD CURRENT CONTROL
When in normal operation mode, the 34653 monitors the
load and provides two modes of current control as explained
in the paragraphs below.
Overcurrent Mode
The 34653 monitors the load for overcurrent conditions. If
the current going through the load becomes larger than the
overcurrent limit for longer than the overcurrent limit filter
timer of 100 μs, the overcurrent signal is asserted and the
gate of the Power MOSFET is discharged to try to regulate
the current at the ILIM value (Point A in Figure 9). The 34653
is in overcurrent mode for 3.0 ms. If after a 3.0 ms filter timer
the device is still in overcurrent mode, the device turns off the
Power MOSFET and deactivates the power good output
signals (Point B in Figure 9). The 34653 then initiates another
start-up timer and goes back through the enhancement
process. If during the 3.0 ms timer the fault was cleared, then
the 34653 goes back to the normal operation mode and the
power good output signals stay activated as shown in
Figure 10. This way the device overcomes temporary
overcurrent situations and at the same time protects the load
from a more severe overcurrent situation.
Figure 7. Power MOSFET Turn-On and the Gradual
Increase in the Charging Current from 0 A to ICHG
(2.0 ms in Example)
The ICHG current charges up the load capacitor relatively
slowly. When the load capacitor is fully charged, the Power
MOSFET reaches its full enhancement, which triggers the
current limit detection to change from ICHG to ILIM and the load
current to decrease (Point C in Figure 6, page 10). The
current spike at Point C in Figure 6 is better displayed in
Figure 8. We can see that when the ⎜VOUT - VIN ⎜< 0.5 V, the
Power MOSFET fully turns on to reach its full enhancement,
charging the capacitor an additional 0.5 V with a higher
current value that quickly ramps down. This eliminates the
need for a current slew rate control because the hazard for a
voltage change is less than 0.5 V. The power good output
signals activate after a 20 ms delay (Point D in Figure 6),
which in turn enables the load. The 34653 is now in normal
operation mode and the retry counter resets.
Short Circuit Mode
If the current going through the load becomes >5.0 A, the
Power MOSFET is discharged very fast (in less than 10 μs)
to try to regulate the current at the ILIM value, and the 34653
is in the overcurrent mode for 3.0 ms. Then it follows the
pattern outlined in the Overcurrent Mode paragraph above.
Figure 8. Full Power MOSFET Turn-On and Current
Spike Associated with It. End of Charging Process
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
CTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11. Disabling and Enabling the 34653
Figure 9. Overcurrent Mode for More Than 3.0 ms
Figure 12 demonstrates that the 34653 must be enabled
for the length of the start-up timer to start turning on the
Power MOSFET. After the fourth disable signal, the 34653
was enabled for the length of the start-up timer. And because
the retry counter is less than 10, the 34653 turns on the
Power MOSFET and starts the charging process (refer to
Charging Process, pages 10–11).
Figure 10. Overcurrent Mode for Less Than 3.0 ms
DISABLING AND ENABLING THE 34653
Figure 12. Start-Up Timer Versus Disable
BOARD REMOVAL
When a negative voltage (< 1.8 V below VPWR) is applied
to the DISABLE pin for more than 1.0 ms (Point A in
Figure 11), the 34653 is disabled, the Power MOSFET turns
off, and the power good output signals deactivate. The 34653
stays in this state until the voltage on the DISABLE pin is
brought to within ±1.2 V of VPWR for more than 1.0 ms to
enable the device (Point B in Figure 11). Then a new start-up
sequence initiates as described on page 10. Applying a
positive voltage (>1.8 V above VPWR) would also disable the
34653 in the same manner.
When the board is removed, its power ramps down. As
soon as the 34653’s input voltage reaches the undervoltage
turn-off threshold, the undervoltage detection circuit activates
and the Power MOSFET turns off for having violated one of
the start-up conditions (list on page 10).
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
STATE MACHINE
Figure 13 is a representation of the 34653 behavior in
different modes of operation.
Temp
> 160°C
Temp < 135°C
Filter = 12
Filter = 12
μ
s
Turn Off
μs
MOSFET
→ OFF
Thermal
Shutdown
Start-Up Conditions
• Thermal Shutdown < 160°C
• DISABLE = 0
PG = 0
V
< 500 mV
N
≤ 10
DS
Charging Mode
MOSFET
→
OFF
PG = 0
N = N + 1
Power
Good Check
If I < I
Fail PG
Check
• V
• V
Filter = t
< V
> V
PWR
OV(OFF)
UV(OFF)
TIMER
VPWR
> VOV(OFF)
LOAD
LIM
PWR
V
< V
OV(ON)
Filter = 1.0 ms
PWR
and V < 500 mV
DS
Filter = 1.0 ms
for 20 ms
Retry Fault
STOP
Pass PG
Check
Overvoltage
N
> 10
Overcurrent
for > 3.0 ms
MOSFET
→ OFF
Toggle DISABLE
or cycle Power Off
then On to clear fault
PG = 0
I
> I
LIM
LOAD
for 100 μs
VPWR
< VUV(OFF)
V
> V
UV(ON)
PWR
Normal Operation
PG = 1
Filter = 1.0 ms
Ext. Resistor Check
Overcurrent Mode
Filter = 3.0 ms
Filter = 1.0 ms
Undervoltage
MOSFET OFF
PG = 0
A signal “set” is generated to check
resistors on UV, ILIM, ICHG, and
N = 0
I
< I
- I
LOAD
LIM LIMHY
→
TIMER pins and 128
the OV pin
μs later
I
> I
SHORT
LOAD
V
> V
UVLOR
PWR
DISABLE = 0
Filter = 1.0 ms
Filter = 1.0 ms
Short Circuit
Detection
Fast Gate Discharge
< 10
DISABLE
Power Off
MOSFET
→ OFF
MOSFET
→ OFF
PG = 0
N = 0
μs
PG = 0
N = 0
POR is generated
POR is generated
VPWR < V
Filter = 1.0 ms
DISABLE = 1
Filter = 1.0 ms
UVLOF
Figure 13. State Diagram
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
Archived by Freescale Semiconductor, Inc., 2008
CTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
PROTECTION AND DIAGNOSIS FEATURES
UNDERVOLTAGE
When the input voltage drops below the undervoltage
falling threshold for more than 1.0 ms, an undervoltage fault
is detected and one of the start-up conditions (list on
page 10) is violated. The 34653 turns off the Power MOSFET
and deactivates the power good output signals, disabling the
load (Point A in Figure 14). The 34653 stays in this state until
the input voltage rises above the undervoltage rising
threshold for more than 1.0 ms, signaling that the supply
voltage is in the normal operation range (Point B in
Figure 14). Then a new start-up sequence initiates as
described on page 10. The undervoltage detection circuit is
also equipped with a 1.0 V hysteresis.
Figure 15. Start-Up Timer Protection Against
Undervoltage Faults
OVERVOLTAGE
When the input voltage exceeds the overvoltage rising
threshold for more than 1.0 ms, an overvoltage fault is
detected and one of the start-up conditions (list on page 10)
is violated. The 34653 turns off the Power MOSFET and
deactivates the power good output signals, disabling the
load. The 34653 stays in this state until the input voltage falls
below the overvoltage falling threshold for more than 1.0 ms,
signaling that the supply voltage is in the normal operation
range. Then a new start-up sequence initiates as described
on page 10. The overvoltage detection circuit is also
equipped with a 2.0 V hysteresis.
Figure 14. Undervoltage Fault Followed by a
New Start-Up Sequence
shows how the 34653 uses the start-up timer to
Figure 15
The waveforms for an overvoltage fault are shown in
Figure 16.
make sure that the input voltage is above the undervoltage
falling threshold. The 34653 was in normal operation before
Point A. At Point A an undervoltage fault occurs. Then the
fault is cleared at Point B, and the 34653 initiates a start-up
sequence. Before the end of the start-up timer another
undervoltage fault occurs at Point C, so the 34653 does not
turn on the Power MOSFET. At Point D the fault is cleared
again for the length of the start-up timer and the 34653 turns
on the Power MOSFET and starts the charging process (refer
to Charging Process, pages 10–11).
Figure 16. Overvoltage Fault
34653
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Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
THERMAL SHUTDOWN
Then:
I2(LOAD) = [TJ(max) - 55 °C] / [111 °C/W 0.251 Ω]
The thermal shutdown feature helps protect the internal
Power MOSFET and circuitry from excessive temperatures.
During start-up and thereafter during normal operation, the
34653 monitors the temperature of the internal circuitry for
excessive heat. If the temperature of the device exceeds the
thermal shutdown temperature of 160°C, one of the start-up
conditions (list on page 10) is violated, and the device turns
off the Power MOSFET and deactivates the power good
output signals. Until the temperature of the device goes
below 135°C, a new start-up sequence will not be initiated.
This feature is an advantage over solutions with an external
Power MOSFET, because it is not easy for a device with an
external MOSFET to sense the temperature quickly and
accurately. The thermal shutdown circuit is equipped with a
12 μs filter.
*
I2(LOAD) = [TJ(max) - 55 °C] / 27.86 °C/A2
So if the overcurrent limit is 1.0 A, then the maximum
junction temperature is 82.86 °C, which is well below the
thermal shutdown temperature that is allowed.
The previous explanation applies to steady state power
when the device is in normal operation. During the charging
process, the power is dominated by the I *V across the Power
MOSFET. When charging starts, the power in the Power
MOSFET rises up and reaches a maximum value of I*V, then
quickly ramps back down to the steady state level in a period
governed by the size of the load’s input capacitor that is being
charged and by the value of the charging current limit ICHG
In this case the instantaneous power dissipation is much
higher than the steady state case, but it is on for a very short
time.
.
Thermal design is critical to proper operation of the 34653.
The typical RDS(ON) of the internal Power MOSFET is
0.144 Ω at room ambient temperature and can reach up to
0.251 Ω at high temperatures. The thermal performance of
the 34653 can vary depending on many factors, among them:
For example:
ICHG = 100 mA, the default value
CLOAD = 400 μF, a very large capacitor
VPWR = 80 V, worst case
• The ambient operating temperature (TA).
• The type of PC board—whether it is single layer or multi-
layer, has heat sinks or not, etc.—all of which affects the
value of the junction-to-ambient thermal resistance (RθJA).
• The value of the desired load current (ILOAD).
Then:
The power pulse magnitude = ICHG VPWR = 8.0 W
*
The power pulse duration = CLOAD VPWR/ICHG = 320 ms
*
When choosing an overcurrent limit, certain guidelines
need to be followed to make sure that if the load current is
running close to the overcurrent limit the 34653 does not go
into thermal shutdown. It is good practice to set the
parameters so that the resulting maximum junction
temperature is below the thermal shutdown temperature by a
safe margin.
Figure 17 displays the temperature profile of the device
under the instantaneous power pulse during the charging
process. Table 5 depicts thermal resistance values for
different board configurations.
70.0
60.0
50.0
40.0
30.0
20.0
10.0
Equation 1 can be used to calculate the maximum
allowable overcurrent limit based on the maximum desired
junction temperature or vice versa.
The power dissipation in the device can be calculated as
follows:
P = I2
RDS(ON)
(LOAD)
*
OR
P = [TJ(max) - TA(max)] / RθJA
Combining the two equations:
0.0
0.000 0.050 0.100 0.150 0.200 0.250 0.300 0.350
I2(LOAD) = [TJ(max) - TA(max)] / [RθJA RDS(ON)] Eq 1
Time (sec)
*
For example:
Figure 17. Instantaneous Temperature Rise of an 8.0 W
Power Pulse that Decreases Linearly at End of a
320 ms Period
TA(max) = 55°C
RθJA = 111 °C/W for a four-layer board
RDS(ON) = 0.251 Ω at high temperatures
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
Archived by Freescale Semiconductor, Inc., 2008
CTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
Table 5. Thermal Resistance Data
Type
Condition
Symbol Value
Unit
Single-layer board (1s), per JEDEC jesd51-2 with board (JESD51-3) horizontal
Four-layer board (2s2p), per JEDEC JESD51-2 with board (JESD51-3) horizontal
Junction to Ambient
Junction to Ambient
Junction to Ambient
Junction to Ambient
Junction to Ambient
Junction to Ambient
R
167
115
145
143
111
107
°C/W
JA
θ
R
°C/W
°C/W
°C/W
°C/W
°C/W
θJMA
Single-layer board with a 300 mm2 radiator pad on its top surface, not standard JEDEC
–
Single-layer board with a 600 mm2 radiator pad on its top surface, not standard JEDEC
Four-layer board with a via for each thermal lead, not standard JEDEC
–
–
–
Four-layer board with a 300 mm2 radiator pad on its top surface and a full array of vias
between radiator pad and top surface, not standard JEDEC
Four-layer board with a 600 mm2 radiator pad on its top surface and a full array of vias
between radiator pad and top surface, not standard JEDEC
Junction to Ambient
–
107
°C/W
Thermal resistance between die and board per JEDEC JESD51-8
Thermal resistance between die and case top
Junction to Board
Junction to Case
R
62
57
18
°C/W
°C/W
°C/W
θJB
R
θJC
Temperature difference between package top and junction per JEDEC JESD51-2
Junction to Package
Top
Ψ
JT
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 34653 resides on the plug-in board (see Figures 18
PLUG-IN CARD
and 19), allowing the board to be safely inserted or removed
without damaging electrical equipment. The 34653 can be
operated with no external components other than the power
good output signal pull-up resistor if the default mode was
selected for all the programmable features. This is one of the
great advantages of the 34653: it operates with minimal user
interface and minimal external component count and still
offers complete hot swapping functionality with all the
necessary protection features, from undervoltage/
overvoltage detection, to current limiting, to short circuit
protection and power good output signaling. The default
values were chosen to be sufficient for many standard
applications.
GND
44 kΩ
33653
Application
Dependent
VPWR
PG
PG
DISABLE
Enable/Enable
C
LOAD
VOUT
VIN
DC/DC
Converter
ICHG
ILIM
-48 V
Figure 18 is a typical application diagram depicting the
default mode and using the power good output signal pullup
resistor. Refer to the static and dynamic electrical
characteristics tables on pages 5 through 7 for the various
default values.
Figure 19. Typical Application Diagram with External
Components Necessary to Program the Device
UNDERVOLTAGE AND OVERVOLTAGE
DETECTION
PLUG-IN CARD
GND
The 34653 monitors the input voltage to ensure that it is
within the operating range and that there are no overvoltage
or undervoltage conditions, and to quickly turn off the Power
MOSFET if there are. Internal comparators connected to an
internal resistor divider between the VPWR and VIN input
pins compare the supply voltages with a reference voltage.
The typical default values of 37 V for the UV turn-off threshold
(falling threshold) and 78 V for the OV turn-off threshold
(rising threshold) will give a typical operating range of 38 V to
76 V. This range is suitable for telecom industry standards.
44 k
Ω
33653
Application
Dependent
VPWR
PG
PG
Enable/Enable
C
LOAD
VOUT
VIN
DC/DC
Converter
ICHG
ILIM
When the device passes the UVLO threshold, it uses the
UV/OV detection circuits to check the input supply levels
before turning on the Power MOSFET during the start-up
Timer delay and thereafter. As long as the voltage is above
the undervoltage falling threshold and below the overvoltage
rising threshold, the supply is within operating range and the
Power MOSFET is allowed to turn on and stay on. If the input
voltage falls below its undervoltage falling threshold or rises
above its overvoltage rising threshold, then one of the start-
up conditions (list on page 10) is violated and the Power
MOSFET turns off, the power good signal deactivates, and a
new start-up timer initiates. The undervoltage and
-48 V
Figure 18. Typical Application Diagram with Default
Settings and Minimal External Components
The 34653 can be also programmed for different values of
the Overcurrent Limit and the Charging Current Limit using
external components connected to the device. Figure 19
shows the 34653 with the required external components that
allow access to all programmable features in the device.
overvoltage detection circuits are equipped with a 1.0 ms
filter to filter out momentary input supply dips.
TIMER
The Timer function on the 34653 provides the time base
used to generate the timing sequences at start-up. The same
timer controls the retry delay when the device experiences
any fault. The Timer function has a default timer value of
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
Archived by Freescale Semiconductor, Inc., 2008
CAL APPLICATIONS
200 ms. During start-up and if any fault occurred, this timer
value is used when initiating a start-up sequence.
The DISABLE pin is referenced to VPWR. If left open or
connected to VPWR, meaning the voltage at the DISABLE
pin is between VPWR + 1.2 V and VPWR - 1.2 V, it is inactive
and the device is enabled. If a positive voltage (1.8 V above
VPWR) or a negative voltage (1.8 V below VPWR) is applied to
DISABLE, it is active and the device is disabled.
POWER GOOD OUTPUT SIGNALS
The power good pins PG and PG are output pins that are
used to directly enable a power module load. The device has
active high and active low power good output signals.
Choosing which power good active signal depends on the
Enable signal requirement of the load. This feature allows the
34653 to adapt to different applications and a wide variety of
loads.
CHARGING CURRENT LIMIT
When the device passes the UVLO threshold, it checks if
there is any external resistor or external capacitor connected
to the ICHG pin. If there is, then it determines the value of the
charging current limit value and the charging current limit rise
time accordingly. If there is not, it uses the default charging
current limit value of 100 mA and rise time of 1.0 ms.
The power good output signal is active if the Power
MOSFET is fully enhanced and the device is in normal
operation. The signal goes active after a typical 20 ms delay.
The signal deactivates if one of the following occurs:
Note Users are allowed to connect an external capacitor
to ICHG pin only if an external resistor is also connected.
During the external components’ check, a capacitor produces
an impulse of current and an external resistor will be
detected, even it the external resistor is absent.
• Power is turned off.
• The device is disabled for more than 1.0 ms.
• The device exceeded its thermal shutdown threshold for
more than 12 μs.
When the Power MOSFET is turned on, the current limit is
set gradually from 0 A to ICHG. This current charges up the
load capacitor relatively slowly. When the load capacitor is
fully charged, the Power MOSFET reaches its full
enhancement, which triggers the current limit to change from
ICHG to ILIM and the load current to decrease. The power good
output signals activate after a 20 ms delay, which in turn
enables the load. The 34653 is now in normal operation
mode and the retry counter resets.
• The device is in overvoltage or undervoltage mode for
more than 1.0 ms.
• Load current exceeded the overcurrent limit for more than
3.0 ms.
When the power good output signal becomes inactive, it
disables the load, protecting it from any faults or damage.
These loads are usually DC/DC converters, depicted in
Figure 19, page 17. An LED can also be connected to PG to
indicate that the power is good.
The low charging current value of ICHG is intended to limit
the temperature increase during the load capacitor charging
process, and the gradual rise to ICHG is to prevent transient
dips in the input voltage due to sharp increases in the limit
current. This prevents the input voltage from drooping due to
current steps acting on the input line inductance, and that in
turn prevents a premature activation of the UV detection
circuit.
The PG and PG pins are referenced to VIN and require a
pullup resistor connected to VPWR (Figures 18 and 19,
page 17).
DISABLING AND ENABLING THE 34653
The Disable control input (DISABLE) provides two
functions:
• External enable/disable control.
• Manual resetting of the device and the retry counter after
a fault has occurred.
Choosing the External Resistor RICHG Value
The user can change the value of the charging current limit
by adding a resistor (RICHG) between the ICHG and VIN pins,
as shown in Figure 19, page 17. The charging current value
ranges between 50 mA and 500 mA, with a default value of
100 mA. Table 6 lists examples of RICHG for different values
of ICHG and Figure 20 shows a plot of RICHG versus ICHG. It is
recommended that the closest 1% standard resistor value to
the actual value be chosen.
Using the DISABLE pin, a user can enable/disable the
34653 device, which facilitates easy access to connect the
load to or disconnect it from the main power rail.
When power is first applied, the DISABLE pin must be
inactive in order for the 34653 to initiate a start-up sequence.
If the DISABLE pin is active, the device makes no further
steps until the pin is inactive. At any point during the start-up
and thereafter during normal operation, if the DISABLE pin is
activated, then the retry counter resets, the Power MOSFET
turns off and the power good output signals deactivate. The
DISABLE circuit is equipped with a 1.0 ms filter to filter out
any glitches or transients on the DISABLE input and prevent
the Power MOSFET from turning off prematurely.
Note Accuracy requirements are application dependent.
To calculate the value of the RICHG resistor we use the
following equations:
ICHG(A) = [RICHG(kΩ) + 1.4 kΩ] / 335
RICHG(kΩ) = 335 ICHG(A) - 1.4 kΩ
*
34653
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Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
TYPICAL APPLICATIONS
Table 6. RICHG Values for Some Desired ICHG Values
Choosing the External Capacitor CICHG Value
The user can also change the charging current rise time by
adding a capacitor (CICHG) between the ICHG and VIN pins,
as shown in Figure 19, page 17. The charging current rise
time ranges between 1.0 ms (default value) and a
recommended maximum of 10 ms. Table 7 lists examples of
CICHG for different values of tICHGR and Figure 21 shows a
I
(A)
R
(kΩ)
CHG
ICHG
0.05
15.35
32.10
48.85
65.60
82.35
99.10
115.85
135.60
149.35
166.10
0.1
0.15
0.2
plot of CICHG versus tICHGR
.
To calculate the value of the CICHG capacitor we use the
following equation:
0.25
0.3
CICHG(nF) = 1000 tICHGR(ms) / [3 RICHG(kΩ)]
*
*
0.35
0.4
Table 7. CICHG Values for Some Desired tICHGR Values
at a Specific ICHG Value
0.45
0.5
C
(nF)
C
(nF)
C
(nF)
ICHG
ICHG
ICHG
t
(ms)
ICHGR
I
= 0.05 A
I
= 0.1 A
I
= 0.5 A
CHG
CHG
CHG
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
21.72
43.43
10.38
2.01
180
160
140
120
100
80
20.77
31.15
41.54
51.92
62.31
72.69
83.07
93.46
103.84
4.01
6.02
65.15
86.86
8.03
108.58
130.29
152.01
173.72
195.44
217.16
10.03
12.04
14.05
16.05
18.06
20.07
60
40
20
0
0
0.1
0.2
0.3
(A)
0.4
0.5
0.6
220
200
180
160
140
120
100
80
I
CHG
= 0.05 A
I
CHG
Figure 20. External Resistor (RICHG) Value Versus
Charging Current Limit Value (ICHG
)
ICHG = 0.1 A
I
CHG
60
40
= 0.5 A
I
CHG
20
0
0
1
2
3
4
5
6
7
8
9
10 11
t
(ms)
ICHGR
Figure 21. Charging Current External Capacitor (CICHG
)
Versus Charging Current Rise Time tICHGR
34653
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Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
CAL APPLICATIONS
Table 8. RILIM Values for Some Desired ILIM Values
OVERCURRENT LIMIT
When in normal operation mode, the 34653 monitors the
load and compares (with a hysteresis) the current going
through a Sensor MOSFET with a reference current value
generated in reference to the current limit value ILIM. If the
current going through the Sensor MOSFET becomes larger
than the reference current for more than 100 μs, the
overcurrent signal is asserted, the gate of the Power
MOSFET is discharged fast (in less than 10 μs) to try to
regulate the current, and the 34653 is in overcurrent mode for
3.0 ms. If after a 3.0 ms filter time the device is still in
overcurrent mode, the device turns off the Power MOSFET
and deactivates the power good output signals. The 34653
then initiates another start-up timer and goes back through
the enhancement process. If during the 3.0 ms timer the fault
was cleared where the load current was less than ILIM minus
the hysteresis value, which is 12% of ILIM value, then the
34653 goes back to the normal operation mode and the
power good output signals stay activated. This way the
device overcomes temporary overcurrent situations and at
the same time protects the load from more severe
I
(A)
R
(kΩ)
LIM
ILIM
0.15
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.25
859.71
644.43
429.15
321.52
256.93
213.88
183.12
160.06
142.12
127.77
116.02
106.24
101.93
overcurrent situations.
When the device passes the UVLO threshold, it checks if
there is any external resistor connected to the ILIM pin. If
there is, it determines the value of the overcurrent limit. If
there is not, it uses the default overcurrent limit value of 1.0 A.
It then uses the Sensor MOSFET to monitor the load for any
overcurrent conditions during operation as explained in the
previous paragraph.
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
Choosing the External Resistor RILIM Value
The user can change the current limit by adding a resistor
(RILIM) between the ILIM and VIN pins, as shown in
Figure 19, page 17. This way the 34653 device is adaptable
to different requirements and operating environments. The
overcurrent value ranges between 0.15 A and 1.25 A, with a
default value of 1.0 A. Table 8 lists examples of RILIM for
different values of ILIM and Figure 22 shows a plot of RILIM
versus ILIM. It is recommended that the closest 1% standard
resistor value to the actual value be chosen.
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
I
(A)
LIM
Note Accuracy requirements are application dependent.
Figure 22. External Resistor (RILIM) Value Versus
Current Limit Value (ILIM
To calculate the value of the RILIM resistor we use the
following equations:
)
ILIM(A) = 129 / [RILIM(kΩ) + 1.4 kΩ]
RILIM(kΩ) = [129 / ILIM(A)] - 1.4 kΩ
SHORT CIRCUIT DETECTION
If the current going through the load becomes >5.0 A, the
Power MOSFET is discharged very fast (in less than 10 μs)
to try to regulate the current, and the 34653 is in the
overcurrent mode for 3.0 ms. Then it follows the pattern
outlined in the Overcurrent Limit paragraph above.
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
TYPICAL APPLICATIONS
POWER MOSFET ENERGY CAPABILITY
3500
3000
2500
Figure 23 shows a projected energy capability of the
device’s internal Power MOSFET under a drain-to-source
voltage of 82 V and an ambient temperature of 90°C. It is
compared to the energy levels required for the capacitive
loads of 100 μF, 200 μF, and 400 μF at 80 V for the
discharge periods of 16 ms, 32 ms, and 64 ms, respectively.
It is clear that the Power MOSFET well exceeds the required
energy capability for all three cases with a sufficient margin.
For example, the 400 μF capacitor load with a 64 ms
discharge time requires an energy capability of about
1540 mJ, which is well below the Power MOSFET capability
of about 3500 mJ. As a result to this analysis the 33652 is
expected to exceedingly meet all the energy capability
requirements for the possible capacitive loads.
Estimated for Area=1.7mm2
400 μF
200 μF
100 μF
2000
1500
1000
500
0
0
20
40
60
Time (ms)
Figure 23. Projected Energy Capability of the Power
MOSFET Compared to the Required Energy Levels of
Some Capacitive Loads
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
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Archived by Freescale Semiconductor, Inc., 2008
KAGING
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the “98A”
drawing number below.
EF SUFFIX (Pb-Free)
8-PIN SOIC NARROW BODY
PLASTIC PACKAGE
98ASB42564B
ISSUE U
34653
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
Archived by Freescale Semiconductor, Inc., 2008
REVISION HISTORY
REVISION HISTORY
REVISION
6.0
DATE
2/2006
8/2006
DESCRIPTION OF CHANGES
•
Changed Document Order No.
•
•
•
Corrected PIN CONNECTIONS on page 3
Updated document to the prevailing Freescale form and style
Updated PACKAGE DIMENSIONS on page 22
7.0
•
•
•
Added Part Number MCZ34653EF/R2 to Ordering Information
Added RoHS logo
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
MAXIMUM RATINGS on page 4.
2/2007
8.0
•
Added note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC
standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels
(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter
the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on
page 4.
34653
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
Archived by Freescale Semiconductor, Inc., 2008
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MC34653
Rev. 8.0
2/2007
相关型号：
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MCZ33094EGR2
SPECIALTY CONSUMER CIRCUIT, PDSO16, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16
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