MFRC50001T/0FE,112 [NXP]
MFRC50001T - The “Original” MIFARE reader solution SOP 32-Pin;型号: | MFRC50001T/0FE,112 |
厂家: | NXP |
描述: | MFRC50001T - The “Original” MIFARE reader solution SOP 32-Pin |
文件: | 总110页 (文件大小:783K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
Rev. 3.3 — 15 March 2010
048033
Product data sheet
PUBLIC
1. Introduction
This data sheet describes the functionality of the MFRC500 Integrated Circuit (IC). It
includes the functional and electrical specifications and from a system and hardware
viewpoint gives detailed information on how to design-in the device.
Remark: The MFRC500 supports all variants of the MIFARE Classic, MIFARE 1K and
MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the
MIFARE Classic, MIFARE 1K and MIFARE 4K products and protocols have the generic
name MIFARE.
2. General description
The MFRC500 is a member of a new family of highly integrated reader ICs for contactless
communication at 13.56 MHz. This family of reader ICs provide:
• outstanding modulation and demodulation for passive contactless communication
• a wide range of methods and protocols
• pin compatibility with the CLRC632, MFRC530, MFRC531 and SLRC400
All protocol layers of the ISO/IEC 14443 A are supported
The receiver module provides a robust and efficient demodulation/decoding circuitry
implementation for compatible transponder signals (see Section 9.10 on page 30). The
digital module, manages the complete ISO/IEC 14443 A standard framing and error
detection (parity and CRC). In addition, it supports the fast Crypto1 security algorithm for
authenticating the MIFARE products (see Section 9.12 on page 35).
The internal transmitter module (Section 9.9 on page 27) can directly drive an antenna
designed for a proximity operating distance up to 100 mm without any additional active
circuitry.
A parallel interface can be directly connected to any 8-bit microprocessor to ensure
reader/terminal design flexibility.
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
3. Features and benefits
3.1 General
Highly integrated analog circuitry for demodulating and decoding card response
Buffered output drivers enable antenna connection using the minimum of external
components
Proximity operating distance up to 100 mm
Supports the ISO/IEC 14443 A standard, parts 1 to 4
Supports MIFARE Classic protocol
Crypto1 and secure non-volatile internal key memory
Pin-compatible with the CLRC632, MFRC530, MFRC531 and the SLRC400
Parallel microprocessor interface with internal address latch and IRQ line
Flexible interrupt handling
Automatic detection of parallel microprocessor interface type
64-byte send and receive FIFO buffer
Hard reset with low power function
Software triggered Power-down mode
Programmable timer
Unique serial number
User programmable start-up configuration
Bit-oriented and byte oriented framing
Independent power supply pins for analog, digital and transmitter modules
Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz
connection
Clock frequency filtering
3.3 V operation for transmitter in short range and proximity applications
4. Applications
Electronic payment systems
Identification systems
Access control systems
Subscriber services
Banking systems
Digital content systems
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
2 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
5. Quick reference data
Table 1.
Symbol
Tamb
Quick reference data
Parameter
Conditions
Min
−40
−40
−0.5
−0.5
−0.5
−0.5
−0.5
−1.0
-
Typ
Max
Unit
°C
°C
V
ambient temperature
storage temperature
digital supply voltage
analog supply voltage
TVDD supply voltage
-
+150
+150
+6
Tstg
-
VDDD
+5
+5
+5
-
VDDA
+6
V
VDD(TVDD)
|Vi|
+6
V
input voltage (absolute
value)
on any digital pin to DVSS
on pin RX to AVSS
VDDD + 0.5
VDDA + 0.5
+1.0
V
-
V
ILI
input leakage current
TVDD supply current
-
mA
mA
IDD(TVDD)
continuous wave
-
150
6. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
MFRC50001T/0FE SO32
plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
3 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
7. Block diagram
NWR NRD NCS
ALE
21
A0 A1 A2
22 23 24
AD0 to AD7/D0 to D7
13 14 15 16 17 18 19 20
10
11
9
VOLTAGE
MONITOR
AND
POWER ON
DETECT
25
12
PARALLEL INTERFACE CONTROL
(INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION)
DVDD
DVSS
STATE MACHINE
FIFO CONTROL
64-BYTE FIFO
COMMAND REGISTER
RESET
CONTROL
PROGRAMMABLE TIMER
INTERRUPT CONTROL
POWER DOWN 31
CONTROL
CONTROL REGISTER
BANK
RSTPD
IRQ
2
CRC16/CRC8
GENERATION AND CHECK
EEPROM
ACCESS
32 × 16-BYTE
EEPROM
CONTROL
PARALLEL/SERIAL CONVERTER
BIT COUNTER
MASTER KEY BUFFER
CRYPTO1 UNIT
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING
BIT ENCODING
32-BIT PSEUDO
RANDOM GENERATOR
3
4
MFIN
SERIAL DATA SWITCH
MFOUT
LEVEL SHIFTERS
1
CLOCK
AMPLITUDE
RATING
OSCIN
CORRELATION
AND
BIT DECODING
GENERATION,
FILTERING AND
DISTRIBUTION
OSCILLATOR
32
REFERENCE
VOLTAGE
OSCOUT
26
AVDD
AVSS
Q-CLOCK
GENERATION
POWER ON
DETECT
28
I-CHANNEL
AMPLIFIER
Q-CHANNEL
AMPLIFIER
ANALOG
TEST
MULTIPLEXER
I-CHANNEL
DEMODULATOR
Q-CHANNEL
DEMODULATOR
TRANSMITTER CONTROL
GND
V
GND
8
V
30
27
29
RX
5
7
6
VMID
AUX
TVSS
TX1
TX2
TVDD
001aaj629
Fig 1. MFRC500 block diagram
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
4 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
8. Pinning information
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OSCIN
IRQ
OSCOUT
RSTPD
VMID
3
MFIN
4
MFOUT
TX1
RX
5
AVSS
6
TVDD
AUX
7
TX2
AVDD
8
TVSS
DVDD
A2
MFRC500
9
NCS
10
11
12
13
14
15
16
NWR/R/NW/nWrite
NRD/NDS/nDStrb
DVSS
A1
A0/nWait
ALE/AS/nAStrb
D7/AD7
D6/AD6
D5/AD5
D4/AD4
AD0/D0
AD1/D1
AD2/D2
AD3/D3
001aal483
Fig 2. MFRC500 pin configuration
8.1 Pin description
Table 3.
Pin description
Pin
Symbol
Type[1]
Description
1
OSCIN
I
oscillator/clock inputs:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; fclk(ext) = 13.56 MHz
interrupt request: generates an output signaling an interrupt event
ISO/IEC 14443 A MIFARE serial data interface input
serial data ISO/IEC 14443 A output
2
IRQ
O
I
3
4[2]
MFIN
MFOUT
TX1
O
O
P
O
G
I
5
transmitter 1 modulated carrier output; 13.56 MHz
transmitter power supply for the TX1 and TX2 output stages
transmitter 2 modulated carrier output; 13.56 MHz
transmitter ground for the TX1 and TX2 output stages
6
TVDD
TX2
7
8
TVSS
NCS
9
not chip select input is used to select and activate the MFRC500’s microprocessor
interface
10[3]
NWR
I
not write input generates the strobe signal for writing data to the MFRC500
registers when applied to pins D0 to D7
R/NW
nWrite
NRD
I
I
I
read not write input is used to switch between read or write cycles
not write input selects the read or write cycle to be performed
11[3]
not read input generates the strobe signal for reading data from the MFRC500
registers when applied to pins D0 to D7
NDS
I
I
not data strobe input generates the strobe signal for the read and write cycles
not data strobe input generates the strobe signal for the read and write cycles
nDStrb
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
5 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
Table 3.
Pin
Pin description …continued
Symbol
Type[1]
Description
12
DVSS
G
digital ground
13 to 20[3] D0 to D7
AD0 to AD7
ALE
I/O
8-bit bidirectional data bus input/output on pins D0 to D7
8-bit bidirectional address and data bus input/output on pins AD0 to AD7
address latch enable input for pins AD0 to AD5; HIGH latches the internal address
address strobe input for pins AD0 to AD5; HIGH latches the internal address
not address strobe input for pins AD0 to AD5; LOW latches the internal address
address line 0 is the address register bit 0 input
not wait output:
I/O
21[3]
I
AS
I
nAStrb
A0
I
22[3]
I
nWait
O
LOW starts an access cycle
HIGH ends an access cycle
23
24[3]
A1
I
address line 1 is the address register bit 1 input
address line 2 is the address register bit 2 input
digital power supply
A2
I
25
DVDD
AVDD
AUX
P
P
O
26
analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX
27
auxiliary output is used to generate analog test signals. The output signal is
selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits
28
29
AVSS
RX
G
I
analog ground
receiver input is used as the card response input. The carrier is load modulated at
13.56 MHz, drawn from the antenna circuit
30
31
VMID
P
I
internal reference voltage pin provides the internal reference voltage as a supply
Remark: It must be connected to a 100 nF block capacitor connected between pin
VMID and ground
RSTPD
reset and power-down input:
HIGH: the internal current sinks are switched off, the oscillator is inhibited and
the input pads are disconnected
LOW (negative edge): start internal reset phase
32
OSCOUT
O
crystal oscillator output for the oscillator’s inverting amplifier
[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
[2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The MFRC500 functionality includes test functions for the SLRC400 using pin
MFOUT.
[3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for
detailed information).
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
6 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
9. Functional description
9.1 Digital interface
9.1.1 Overview of supported microprocessor interfaces
The MFRC500 supports direct interfacing to various 8-bit microprocessors. Alternatively,
the MFRC500 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows
the parallel interface signals supported by the MFRC500.
Table 4.
Supported microprocessor and EPP interface signals
Bus control signals
Bus
Separated address
and data bus
Multiplexed address and data bus
Separated read and
write strobes
control
NRD, NWR, NCS
NRD, NWR, NCS, ALE
AD0, AD1, AD2, AD3, AD4, AD5
AD0 to AD7
address A0, A1, A2
data
D0 to D7
Common read and write control
strobe
R/NW, NDS, NCS
R/NW, NDS, NCS, AS
AD0, AD1, AD2, AD3, AD4, AD5
AD0 to AD7
address A0, A1, A2
data
D0 to D7
Common read and write control
strobe with handshake
-
-
-
nWrite, nDStrb, nAStrb, nWait
AD0, AD1, AD2, AD3, AD4, AD5
AD0 to AD7
(EPP)
address
data
9.1.2 Automatic microprocessor interface detection
After a Power-On or Hard reset, the MFRC500 resets the parallel microprocessor
interface mode and detects the microprocessor interface type.
The MFRC500 identifies the microprocessor interface using the logic levels on the control
pins. This is performed using a combination of fixed pin connections and the dedicated
Initialization routine (see Section 9.7.4 on page 25).
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
7 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
9.1.3 Connection to different microprocessor types
The connection to various microprocessor types is shown in Table 5.
Table 5.
Connection scheme for detecting the parallel interface type
Parallel interface type and signals
MFRC500
pins
Separated read/write strobe Common read/write strobe
Dedicated
Multiplexed Dedicated
Multiplexed Multiplexed
address bus
address
bus
address bus address bus address bus with
handshake
ALE
A2
HIGH
A2
ALE
HIGH
A2
AS
nAStrb
HIGH
LOW
HIGH
HIGH
NRD
NWR
NCS
LOW
A1
A1
A1
HIGH
LOW
HIGH
A0
A0
A0
nWait
NRD
NWR
NCS
D7 to D0
NRD
NWR
NCS
D7 to D0
NDS
R/NW
NCS
NDS
nDStrb
nWrite
LOW
R/NW
NCS
AD7 to AD0 D7 to D0
AD7 to AD0
AD7 to AD0
9.1.3.1 Separate read and write strobe
DEVICE
NCS
DEVICE
NCS
address bus (A3 to An)
non-multiplexed address
ADDRESS
DECODER
ADDRESS
DECODER
LOW
HIGH
HIGH
A2
A1
A0
address bus (A0 to A2)
data bus (D0 to D7)
A0 to A2
D0 to D7
multiplexed address/data (AD0 to AD7)
AD0 to AD7
HIGH
address latch enable (ALE)
Read strobe (NRD)
ALE
ALE
Read strobe (NRD)
Write strobe (NWR)
NRD
NWR
NRD
NWR
Write strobe (NWR)
001aak607
Fig 3. Connection to microprocessor: separate read and write strobes
Refer to Section 13.4.1 on page 86 for timing specification.
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
8 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
9.1.3.2 Common read and write strobe
DEVICE
NCS
DEVICE
NCS
address bus (A3 to An)
non-multiplexed address
ADDRESS
DECODER
ADDRESS
DECODER
LOW
HIGH
LOW
A2
A1
A0
address bus (A0 to A2)
data bus (D0 to D7)
A0 to A2
D0 to D7
multiplexed address/data (AD0 to AD7)
AD0 to AD7
HIGH
Address strobe (AS)
Data strobe (NDS)
Read/Write (R/NW)
ALE
ALE
Data strobe (NDS)
Read/Write (R/NW)
NRD
NWR
NRD
NWR
001aak608
Fig 4. Connection to microprocessor: common read and write strobes
Refer to Section 13.4.2 on page 87 for timing specification.
9.1.3.3 Common read and write strobe: EPP with handshake
DEVICE
NCS
LOW
HIGH
A2
A1
A0
HIGH
nWait
multiplexed address/data (AD1 to AD8)
AD0 to AD7
Address strobe (nAStrb)
Data strobe (nDStrb)
Read/Write (nWrite)
ALE
NRD
NWR
001aak609
Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake
Refer to Section 13.4.3 on page 88 for timing specification.
Remark: In the EPP standard a chip select signal is not defined. To cover this situation,
the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is
high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The MFRC500 does not support Read Address Cycle.
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
9 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
9.2 Memory organization of the EEPROM
Table 6.
Block
Position Address
EEPROM memory organization diagram
Byte address Access Memory content Refer to
0
0
00h to 0Fh
R
product
information field
Section 9.2.1 on page 11
Section 9.2.2.1 on page 11
1
1
10h to 1Fh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
StartUp register
initialization file
2
2
20h to 2Fh
3
3
30h to 3Fh
register
initialization file
Section 9.2.2.3 “Register
initialization file (read/write)”
on page 13
4
4
40h to 4Fh
5
5
50h to 5Fh
6
6
60h to 6Fh
7
7
70h to 7Fh
8
8
80h to 8Fh
keys for Crypto1
Section 9.2.3 on page 13
9
9
90h to 9Fh
W
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
A0h to AFh
B0h to BFh
C0h to CFh
D0h to DFh
E0h to EFh
F0h to FFh
W
B
W
C
W
D
W
E
W
F
W
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
100h to 10Fh
110h to 11Fh
120h to 12Fh
130h to 13Fh
140h to 14Fh
150h to 15Fh
160h to 16Fh
170h to 17Fh
180h to 18Fh
190h to 19Fh
1A0h to 1AFh
1B0h to 1BFh
1C0h to 1CFh
1D0h to 1DFh
1E0h to 1EFh
1F0h to 1FFh
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
10 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
9.2.1 Product information field (read only)
Table 7.
Byte
Symbol CRC
Product information field byte allocation
15 14 13 12 11 10
9
8
7
6
-
5
4
3
2
1
0
Internal
R
Product Serial Number
R
Product Type Identification
R
Access
R
R
Table 8.
Byte
15
Product information field byte description
Symbol
Access Value Description
CRC
R
-
the content of the product information field
is secured using a CRC byte which is
checked during start-up
14 to 12 Internal
R
R
-
-
three bytes for internal trimming parameters
11 to 8 Product Serial Number
a unique four byte serial number for the
device
7 to 5
4 to 0
reserved
R
R
-
-
Product Type
Identification
the MFRC500 is a member of a new family
of highly integrated reader ICs. Each
member of the product family has a unique
product type identification. The value of the
product type identification is shown in
Table 9.
Table 9.
Definition
Byte
Product type identification definition
Product type identification bytes
0
1
2
3
4[1]
Value
30h
88h
F8h
00h
XXh
[1] Byte 4 contains the current version number.
9.2.2 Register initialization files (read/write)
Register initialization from address 10h to address 2Fh is performed automatically during
the initializing phase (see Section 9.7.3 on page 25) using the StartUp register
initialization file.
In addition, the MFRC500 registers can be initialized using values from the register
initialization file when the LoadConfig command is executed (see Section 11.4.1 on
page 79).
Remark: The following points apply to initialization:
• the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized.
• PreSetxx registers: do not change.
• all reserved register bits set to logic 0: do not change.
9.2.2.1 StartUp register initialization file (read/write)
The EEPROM memory block address 1 and 2 contents are used to automatically set the
register subaddresses 10h to 2Fh during the initialization phase. The default values stored
in the EEPROM during production are shown in Section 9.2.2.2 “Factory default StartUp
register initialization file”.
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
11 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
The byte assignment is shown in Table 10.
Table 10. Byte assignment for register initialization at start-up
EEPROM byte address
Register address
Remark
skipped
copied
…
10h (block 1, byte 0)
10h
11h
…
11h
…
2Fh (block 2, byte 15)
2Fh
copied
9.2.2.2 Factory default StartUp register initialization file
During the production tests, the StartUp register initialization file is initialized using the
default values shown in Table 11. During each power-up and initialization phase, these
values are written to the MFRC500’s registers.
Table 11. Shipment content of StartUp configuration file
EEPROM Register Value Symbol
Description
byte
address
address
10h
11h
10h
11h
00h
58h
Page
free for user
TxControl
transmitter pins TX1 and TX2 are switched off, bridge driver
configuration, modulator driven from internal digital circuitry
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
3Fh
3Fh
19h
13h
00h
00h
00h
73h
08h
ADh
FFh
00h
41h
CwConductance
PreSet13
source resistance of TX1 and TX2 is set to minimum
-
PreSet14
-
ModWidth
PreSet16
pulse width for Miller pulse encoding is set to standard configuration
-
PreSet17
-
Page
free for user
RxControl1
DecoderControl
BitPhase
ISO/IEC 14443 A is set and internal amplifier gain is maximum
bit-collisions always evaluate to HIGH in the data bit stream
BitPhase[7:0] is set to standard configuration
MinLevel[3:0] and CollLevel[3:0] are set to maximum
-
RxThreshold
PreSet1D
RxControl2
use Q-clock for the receiver, automatic receiver off is switched on,
decoder is driven from internal analog circuitry
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
00h
00h
06h
03h
63h
63h
00h
00h
00h
00h
ClockQControl
Page
automatic Q-clock calibration is switched on
free for user
RxWait
frame guard time is set to six bit-clocks
ChannelRedundancy channel redundancy is set using ISO/IEC 14443 A
CRCPresetLSB
CRCPresetMSB
PreSet25
CRC preset value is set using ISO/IEC 14443 A
CRC preset value is set using ISO/IEC 14443 A
-
MFOUTSelect
PreSet27
pin MFOUT is set LOW
-
Page
free for user
MFRC500_33
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Table 11. Shipment content of StartUp configuration file …continued
EEPROM Register Value Symbol
Description
byte
address
address
29h
2Ah
2Bh
2Ch
29h
08h
07h
06h
0Ah
FIFOLevel
WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
2Ah
TimerClock
TimerControl
TimerReload
TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
2Bh
Timer is started at the end of transmission, stopped at the beginning
of reception
2Ch
TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
2Dh
2Eh
2Fh
2Dh
2Eh
2Fh
02h
00h
00h
IRQPinConfig
PreSet2E
pin IRQ is set to high-impedance
-
-
PreSet2F
9.2.2.3 Register initialization file (read/write)
The EEPROM memory content from block address 3 to 7 can initialize register
subaddresses 10h to 2Fh when the LoadConfig command is executed (see
Section 11.4.1 on page 79). This command requires the EEPROM starting byte address
as a two byte argument for the initialization procedure.
The byte assignment is shown in Table 12.
Table 12. Byte assignment for register initialization at startup
EEPROM byte address
Register address
Remark
skipped
copied
…
EEPROM starting byte address
EEPROM + 1 starting byte address
10h
11h
…
EEPROM + 31 starting byte address
2Fh
copied
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data.
Remark: The register initialization file can be read/written by users and these bytes can
be used to store other user data.
After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A
protocol.
9.2.3 Crypto1 keys (write only)
MIFARE security requires specific cryptographic keys to encrypt data stream
communication on the contactless interface. These keys are called Crypto1 keys.
9.2.3.1 Key format
Keys stored in the EEPROM are written in a specific format. Each key byte must be split
into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This
format is a precondition for successful execution of the LoadKeyE2 (see Section 11.6.1 on
page 81) and LoadKey commands (see Section 11.6.2 on page 81).
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Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is
shown in Figure 6.
Master key byte
0 (LSB)
1
5 (MSB)
Master key bits k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0 k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0
EEPROM byte
k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0
n
n + 1
n + 2
n + 3
n + 10
5Ah
n + 11
A5h
address
5Ah
F0h
5Ah
E1h
Example
001aak640
Fig 6. Key storage format
Example: The value for the key must be written to the EEPROM.
• If the key was: A0h A1h A2h A3h A4h A5h then
• 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.
Remark: It is possible to load data for other key formats into the EEPROM key storage
location. However, it is not possible to validate card authentication with data which will
cause the LoadKeyE2 command (see Section 11.6.1 on page 81) to fail.
9.2.3.2 Storage of keys in the EEPROM
The MFRC500 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No
memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every
byte of the dedicated memory area can be the start of a key.
Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for
example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM
block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.
Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32
different keys can be stored in the EEPROM.
Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.
9.3 FIFO buffer
An 8 × 64 bit FIFO buffer is used in the MFRC500 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the MFRC500. This makes it possible to manage data streams up to
64 bytes long without needing to take timing constraints into account.
9.3.1 Accessing the FIFO buffer
9.3.1.1 Access rules
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
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When the microprocessor starts a command, the MFRC500 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses. Table 13 gives an overview of FIFO buffer access
during command processing.
Table 13. FIFO buffer access
Active
FIFO buffer
Remark
command
μp Write
μp Read
StartUp
Idle
-
-
-
-
Transmit
Receive
Transceive
yes
-
-
yes
yes
yes
the microprocessor has to know the state of the
command (transmitting or receiving)
WriteE2
ReadE2
yes
yes
-
yes
the microprocessor has to prepare the arguments,
afterwards only reading is allowed
LoadKeyE2
LoadKey
yes
yes
yes
-
-
-
-
-
-
-
Authent1
Authent2
LoadConfig
CalcCRC
yes
yes
9.3.2 Controlling the FIFO buffer
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
9.3.3 FIFO buffer status information
The microprocessor can get the following FIFO buffer status data:
• the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
• the FIFO buffer full warning: bit HiAlert
• the FIFO buffer empty warning: bit LoAlert
• the FIFO buffer overflow warning: bit FIFOOvfl.
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The MFRC500 can generate an interrupt signal when:
• bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
• bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by Equation 1:
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HiAlert = (64 – FIFOLength) ≤ WaterLevel
(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by Equation 2:
LoAlert = FIFOLength ≤ WaterLevel
(2)
9.3.4 FIFO buffer registers and flags
Table 14 shows the related FIFO buffer flags in alphabetic order.
Table 14. Associated FIFO buffer registers and flags
Flags
Register name
FIFOLength
ErrorFlag
Bit
Register address
FIFOLength[6:0]
FIFOOvfl
6 to 0
04h
0Ah
09h
03h
06h
07h
03h
06h
07h
29h
4
FlushFIFO
HiAlert
Control
0
PrimaryStatus
InterruptEn
InterruptRq
PrimaryStatus
InterruptEn
InterruptRq
FIFOLevel
1
HiAlertIEn
HiAlertIRq
LoAlert
1
1
0
LoAlertIEn
LoAlertIRq
WaterLevel[5:0]
0
0
5 to 0
9.4 Interrupt request system
The MFRC500 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page 45) and activating pin IRQ. The signal
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
9.4.1 Interrupt sources overview
Table 15 shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
• the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
• the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
• when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
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When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 15) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to logic 1.
Table 15. Interrupt sources
Interrupt flag
TimerIRq
TxIRq
Interrupt source
timer unit
Trigger action
timer counts from 1 to 0
transmitter
a data stream, transmitted to the card, ends
all data from the FIFO buffer has been processed
CRC coprocessor
EEPROM
all data from the FIFO buffer has been
programmed
RxIRq
receiver
a data stream, received from the card, ends
command execution finishes
FIFO buffer is full
IdleIRq
Command register
FIFO buffer
FIFO buffer
HiAlertIRq
LoAlertIRq
FIFO buffer is empty
9.4.2 Interrupt request handling
9.4.2.1 Controlling interrupts and getting their status
The MFRC500 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
Table 16. Interrupt control registers
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
InterruptEn
InterruptRq
SetIEn
SetIRq
reserved
reserved
TimerIEn
TimerIRq
TxIEn
TxIRq
RxIEn
RxIRq
IdleIEn
IdleIRq
HiAlertIEn LoAlertIEn
HiAlertIRq LoAlertIRq
If an interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously and because of this,
all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
9.4.2.2 Accessing the interrupt registers
The interrupt request bits are automatically set by the MFRC500’s internal state
machines. In addition, the microprocessor can also set or clear the interrupt request bits
as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice
versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the
interrupt register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
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Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0
while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq
to logic 1 and leaves all other bits unchanged.
9.4.3 Configuration of pin IRQ
The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be
controlled using the following IRQPinConfig register bits.
• bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set
to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq.
• bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When
it is set to logic 0, it is an open-drain output which requires an external resistor to
achieve a HIGH-level at pin IRQ.
Remark: During the reset phase (see Section 9.7.2 on page 25) bit IRQInv is set to
logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.
9.4.4 Register overview interrupt request system
Table 17 shows the related interrupt request system flags in alphabetically.
Table 17. Associated Interrupt request system registers and flags
Flags
Register name
InterruptEn
InterruptRq
InterruptEn
InterruptRq
PrimaryStatus
IRQPinConfig
IRQPinConfig
InterruptEn
InterruptRq
InterruptEn
InterruptRq
InterruptEn
InterruptRq
InterruptEn
InterruptRq
InterruptEn
InterruptRq
Bit
1
1
2
2
3
1
0
0
0
3
3
7
7
5
5
4
4
Register address
HiAlertIEn
HiAlertIRq
IdleIEn
06h
07h
06h
07h
03h
07h
07h
06h
07h
06h
07h
06h
07h
06h
07h
06h
07h
IdleIRq
IRq
IRQInv
IRQPushPull
LoAlertIEn
LoAlertIRq
RxIEn
RxIRq
SetIEn
SetIRq
TimerIEn
TimerIRq
TxIEn
TxIRq
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9.5 Timer unit
The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor
can use this timer to manage timing-relevant tasks.
The timer unit may be used in one of the following configurations:
• Timeout counter
• WatchDog counter
• Stopwatch
• Programmable one shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific timed event occurred. The timer is triggered by events but does not
influence any event (e.g. a time-out during data receiving does not automatically influence
the reception process). Several timer related flags can be set and these flags can be used
to generate an interrupt.
9.5.1 Timer unit implementation
9.5.1.1 Timer unit block diagram
Figure 7 shows the block diagram of the timer module.
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TStartTxBegin
TxBegin Event
TStartTxEnd
TxEnd Event
TReloadValue[7:0]
PARALLEL IN
START COUNTER/
PARALLEL LOAD
TAutoRestart
TStartNow
TStopNow
Q
Q
S
R
COUNTER MODULE
(x ≤ x − 1)
TRunning
STOP COUNTER
RxEnd Event
TStopRxEnd
RxBegin Event
TStopRxBegin
TPreScaler[4:0]
TimerValue[7:0]
CLOCK
DIVIDER
13.56 MHz
PARALLEL OUT
Counter = 0 ?
to parallel interface
to interrupt logic: TimerIRq
001aak611
Fig 7. Timer module block diagram
The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens.
9.5.1.2 Controlling the timer unit
The main part of the timer unit is a down counter. As long as the down counter value is not
zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
The timer is started immediately by loading a value from the TimerReload register into the
counter module.
This is activated by one of the following events:
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• transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1
• transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1
• bit TStartNow is set to logic 1 by the microprocessor
Remark: Every start event reloads the timer from the TimerReload register which
re-triggers the timer unit.
The timer can be configured to stop on one of the following events:
• receipt of the first valid bit from the card (RxBegin event) with bit
TStopRxBegin = logic 1
• receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd = logic 1
• the counter module has decremented down to zero and bit TAutoRestart = logic 0
• bit TStopNow is set to logic 1 by the microprocessor.
Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit
while it is counting will not immediately influence the counter. In both cases, this is
because this register only affects the counter content after a start event.
If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged.
9.5.1.3 Timer unit clock and period
The timer unit clock is derived from the 13.56 MHz on-board chip clock using the
programmable divider. Clock selection is made using the TimerClock register
TPreScaler[4:0] bits based on Equation 3:
2TPreScaler
--------------------------
1
---------------------------
fTimerClock
=
=
[MHz]
(3)
13.56
TTimerClock
The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum
periodic time (TTimerClock) of between 74 ns and 150 ms.
The time period elapsed since the last start event is calculated using Equation 4:
TReLoadValue – TimerValue
----------------------------------------------------------------------------
tTimer
=
[s]
(4)
fTimerClock
This results in a minimum time period (tTimer) of between 74 ns and 40 s.
9.5.1.4 Timer unit status
The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start
events start the timer at the TReloadValue[7:0] and change the status flag TRunning to
logic 1. Conversely, configured stop events stop the timer and set the TRunning status
flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register
changes on the next timer unit clock cycle.
The TimerValue[7:0] bits can be read directly from the TimerValue register.
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9.5.2 Using the timer unit functions
9.5.2.1 Time-out and WatchDog counters
After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue
register beginning with a given start event. If a given stop event occurs, such as a bit
being received from the card, the timer unit stops without generating an interrupt.
If a stop event does not occur, such as the card not answering within the expected time,
the timer unit decrements down to zero and generates a timer interrupt request. This
signals to the microprocessor the expected event has not occurred within the given time
(tTimer).
9.5.2.2 Stopwatch
The time (tTimer) between a start and stop event is measured by the microprocessor using
the timer unit. Setting the TReloadValue register triggers the timer which in turn, starts to
decrement. If the defined stop event occurs, the timer stops. The time between start and
stop is calculated by the microprocessor using Equation 5 when the time does not
decrement down to zero.
Δt = (TReLoadvalue – TimerValue) × tTimer
(5)
9.5.2.3 Programmable one shot timer and periodic trigger
Programmable one shot timer: The microprocessor starts the timer unit and waits for
the timer interrupt. The interrupt occurs after the time specified by tTimer
.
Periodic trigger: If the microprocessor sets the TAutoRestart bit, it generates an interrupt
request after every tTimer cycle.
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9.5.3 Timer unit registers
Table 18 shows the related flags of the timer unit in alphabetical order.
Table 18. Associated timer unit registers and flags
Flags
Register name
TimerClock
TimerValue
TimerReload
TimerClock
SecondaryStatus
Control
Bit
Register address
TAutoRestart
TimerValue[7:0]
TReloadValue[7:0]
TPreScaler[4:0]
TRunning
5
2Ah
0Ch
2Ch
2Ah
05h
09h
2Bh
2Bh
09h
2Bh
2Bh
7 to 0
7 to 0
4 to 0
7
1
0
1
2
2
3
TStartNow
TStartTxBegin
TStartTxEnd
TStopNow
TimerControl
TimerControl
Control
TStopRxBegin
TStopRxEnd
TimerControl
TimerControl
9.6 Power reduction modes
9.6.1 Hard power-down
Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in Table 19.
Table 19. Signal on pins during Hard power-down
Symbol
OSCIN
IRQ
Pin
1
Type
Description
I
not separated from input, pulled to AVSS
high-impedance
2
O
I
MFIN
3
separated from input
LOW
MFOUT
TX1
4
O
O
5
HIGH, if bit TX1RFEn = logic 1
LOW, if bit TX1RFEn = logic 0
TX2
7
O
HIGH, only if bit TX2RFEn = logic 1 and bit
TX2Inv = logic 0
otherwise LOW
NCS
NWR
NRD
D0 to D7
ALE
A0
9
I
separated from input
separated from input
separated from input
separated from input
separated from input
separated from input
separated from input
separated from input
high-impedance
10
I
11
I
13 to 20
21
I/O
I
22
I/O
A1
23
I
A2
24
I
AUX
27
O
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Table 19. Signal on pins during Hard power-down …continued
Symbol
Pin
29
30
31
32
Type
Description
not changed
pulled to VDDA
not changed
HIGH
RX
I
VMID
A
I
RSTPD
OSCOUT
O
9.6.2 Soft power-down mode
Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
9.6.3 Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4 Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up.
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9.7 StartUp phase
The events executed during the StartUp phase are shown in Figure 8.
StartUp phase
t
t
t
init
RSTPD
reset
Hard power-
down phase
Initialising
phase
states
Reset phase
ready
001aak613
Fig 8. The StartUp procedure
9.7.1 Hard power-down phase
The hard power-down phase is active during the following cases:
• a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when VDDD or VDDA is below the relevant analog/digital reset threshold.
• a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 μs (tPD ≥ 100 μs). Shorter phases will not
necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
9.7.2 Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 10.5 on page 43).
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
9.7.3 Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see Section 9.2.2 on page 11).
Remark: During the production test, the MFRC500 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4 Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC500’s start-up. See Section 9.1.3 on page 8 for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC500 automatically switches to idle and the
command value changes to 00h.
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To ensure correct detection of the microprocessor interface, the following sequence is
executed:
• the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the MFRC500 is ready to be
controlled
• write 80h to the Page register to initialize the microprocessor interface
• read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized
• write 00h to the Page registers to activate linear addressing mode.
9.8 Oscillator circuit
DEVICE
OSCOUT
OSCIN
13.56 MHz
15 pF
15 pF
001aak614
Fig 9. Quartz clock connection
The clock applied to the MFRC500 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified. It must meet the specifications described in Section 13.4.4 on
page 90.
Remark: We do not recommend using an external clock source.
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9.9 Transmitter pins TX1 and TX2
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly, using minimal passive
components for matching and filtering (see Section 15.1 on page 91). To enable this, the
output circuitry is designed with a very low-impedance source resistance. The TxControl
register is used to control the TX1 and TX2 signals.
9.9.1 Configuring pins TX1 and TX2
TX1 pin configurations are described in Table 20.
Table 20. Pin TX1 configurations
TxControl register configuration
Envelope TX1 signal
TX1RFEn
FORCE100ASK
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
LOW (GND)
13.56 MHz carrier frequency modulated
13.56 MHz carrier frequency
LOW
13.56 MHz energy carrier
TX2 pin configurations are described in Table 21.
Table 21. Pin TX2 configurations
TxControl register configuration
Envelope TX2 signal
TX2RFEn FORCE100ASK TX2CW TX2Inv
0
1
X
0
X
0
X
0
X
0
LOW
13.56 MHz carrier frequency
modulated
1
1
0
0
0
0
0
1
1
0
13.56 MHz carrier frequency
13.56 MHz carrier frequency
modulated, 180° phase-shift
relative to TX1
1
0
0
1
1
13.56 MHz carrier frequency,
180° phase-shift relative to TX1
1
1
0
0
1
1
0
1
X
X
13.56 MHz carrier frequency
13.56 MHz carrier frequency,
180° phase-shift relative to TX1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
LOW
13.56 MHz carrier frequency
HIGH
13.56 MHz carrier frequency,
180° phase-shift relative to TX1
1
1
1
1
1
1
0
1
X
X
13.56 MHz carrier frequency
13.56 MHz carrier frequency,
180° phase-shift relative to TX1
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9.9.2 Antenna operating distance versus power consumption
Using different antenna matching circuits (by varying the supply voltage on the antenna
driver supply pin TVDD), it is possible to find the trade-off between maximum effective
operating distance and power consumption. Different antenna matching circuits are
described in the Application note “MIFARE Design of MFRC500 Matching Circuit and
Antennas”.
9.9.3 Antenna driver output source resistance
The output source conductance of pins TX1 and TX2 can be adjusted between 1 Ω and
100 Ω using the CwConductance register GsCfgCW[5:0] bits.
The output source conductance of pins TX1 and TX2 during the modulation phase can be
adjusted between 1 Ω and 100 Ω using the ModConductance register GsCfgMod[5:0] bits.
The values are relative to the reference resistance (RS(ref)) which is measured during the
production test and stored in the MFRC500 EEPROM. It can be read from the product
information field (see Section 9.2.1 on page 11). The electrical specification can be found
in Section 13.3.3 on page 86.
9.9.3.1 Source resistance table
Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod
MANT = Mantissa; EXP= Exponent.
GsCfgCW, EXPGsCfgCW
GsCfgMod EXPGsCfgMod MANTGsCfgMod (Ω)
,
MANTGsCfgCW, RS(ref)
GsCfgCW,
GsCfgMod
(decimal)
EXPGsCfgCW
EXPGsCfgMod
(decimal)
,
MANTGsCfgCW
MANTGsCfgMod (Ω)
(decimal)
,
RS(ref)
(decimal)
(decimal)
(decimal)
0
16
32
48
1
0
1
2
3
0
1
0
0
2
1
0
0
1
0
0
3
2
1
0
0
1
0
0
0
0
1
1
2
3
1
2
4
5
3
6
7
1
2
4
8
9
5
-
24
25
37
26
27
51
38
28
29
39
30
52
31
40
41
53
42
43
54
44
45
1
1
2
1
1
3
2
1
1
2
1
3
1
2
2
3
2
2
3
2
2
8
9
0.0652
-
0.0580
0.0541
0.0522
0.0474
0.0467
0.0450
0.0435
0.0401
0.0386
0.0373
0.0350
0.0348
0.0338
0.0300
0.0280
0.0270
0.0246
0.0234
0.0225
0.0208
-
5
-
10
11
3
1.0000
0.5217
0.5000
0.3333
0.2703
0.2609
0.2500
0.2000
0.1739
0.1667
0.1429
0.1402
0.1351
0.1304
0.1250
0.1111
0.1043
17
2
6
3
12
13
7
33
18
4
14
4
5
19
6
15
8
7
9
49
34
20
8
5
10
11
6
9
12
13
21
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Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod …continued
MANT = Mantissa; EXP= Exponent.
GsCfgCW, EXPGsCfgCW
GsCfgMod EXPGsCfgMod MANTGsCfgMod (Ω)
,
MANTGsCfgCW, RS(ref)
GsCfgCW,
GsCfgMod
(decimal)
EXPGsCfgCW
EXPGsCfgMod
(decimal)
,
MANTGsCfgCW
MANTGsCfgMod (Ω)
(decimal)
,
RS(ref)
(decimal)
(decimal)
(decimal)
10
11
35
22
12
13
23
14
50
36
15
0
0
2
1
0
0
1
0
3
2
0
10
11
3
0.1000
0.0909
0.0901
0.0870
0.0833
0.0769
0.0745
0.0714
0.0701
0.0676
0.0667
55
46
47
56
57
58
59
60
61
62
63
3
2
2
3
3
3
3
3
3
3
3
7
0.0200
14
15
8
0.0193
0.0180
0.0175
0.0156
0.0140
0.0127
0.0117
0.0108
0.0100
0.0093
6
12
13
7
9
10
11
12
13
14
15
14
2
4
15
9.9.3.2 Calculating the relative source resistance
The reference source resistance RS(ref) can be calculated using Equation 6.
1
RS(ref)
=
(6)
--------------------------------------------------------------------------------
EXP
GsCfgCW
77
⎛
⎞
-----
MANTGsCfgCW
•
⎝
⎠
40
The reference source resistance (RS(ref)) during the modulation phase can be calculated
using ModConductance register’s GsCfgMod[5:0].
9.9.3.3 Calculating the effective source resistance
Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver
resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The
additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in
Equation 7.
RS(wire)TX1 ≈ 500 mΩ
(7)
Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP
byte) read from the Product Information Field (see Section 9.2.1 on page 11) are
measured during the production test with CwConductance register’s
GsCfgCW[5:0] = 01h.
To calculate the driver resistance for a specific value set in GsCfgMod[5:0], use
Equation 8.
RSx = (RS(ref)maxP – RS(wire)TX1) • RS(rel) + RS(wire)TX1
(8)
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9.9.4 Pulse width
The envelope carries the data signal information that is transmitted to the card. It is an
encoded data signal based on the Miller code. In addition, each pause of the Miller
encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is
adjusted using the ModWidth register. The pulse width (tw) is calculated using Equation 9
where the frequency constant (fclk) = 13.56 MHz.
ModWidth + 1
------------------------------------
tw = 2
(9)
fclk
9.10 Receiver circuit
The MFRC500 uses an integrated quadrature demodulation circuit enabling it to extract
the ISO/IEC 14443 A compliant subcarrier from the 13.56 MHz ASK modulated signal
applied to pin RX.
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90° between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1 Receiver circuit block diagram
Figure 10 shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see Section 9.10.2.1 on page 31).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
ClkQ180Deg
ClkQDelay[4:0]
ClkQCalib
I TO Q
CONVERSION
Gain[1:0]
CollLevel[3:0] RcvClkSell
MinLevel[3:0] RxWait[7:0]
BitPhase[7:0]
clock
I-clock
Q-clock
s_valid
EVALUATION
AND
DIGITIZER
CIRCUITRY
s_data
s_coll
CORRELATION
CIRCUITRY
13.56 MHz
DEMODULATOR
RX
s_clock
VRxFollQ
VRxAmpQ
VRxAmpI
VCorrDI
VCorrDQ
VCorrNQ
VEvalR
VRxFollI
VCorrNI
VEvalL
to
TestAnaOutSel
001aak615
Fig 10. Receiver circuit block diagram
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The signal can be observed on its way through the receiver as shown in Figure 10. One
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
Section 15.2.2 on page 96.
9.10.2 Receiver operation
In general, the default settings programmed in the StartUp initialization file are suitable for
use with the MFRC500 to MIFARE card data communication. However, in some
environments specific user settings will achieve better performance.
9.10.2.1 Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90° phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90°. After
the reset phase, a calibration procedure is automatically performed.
Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
calibration impulse
a rising edge initiates
from reset sequence
Q-clock calibration
calibration impulse
from end of
Transceive command
ClkQCalib bit
001aak616
Fig 11. Automatic Q-clock calibration
Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8 μs.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180°.
Remark:
• The StartUp configuration file enables automatic Q-clock calibration after a reset
• If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration.
• It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8 μs has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
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9.10.2.2 Amplifier
The demodulated signal must be amplified by the variable amplifier to achieve the best
performance. The gain of the amplifiers can be adjusted using the RxControl1 register
Gain[1:0] bits; see Table 23.
Table 23. Gain factors for the internal amplifier
See Table 78 “RxControl1 register bit descriptions” on page 55 for additional information.
Register setting
Gain factor (dB)
(simulation results)
00
01
10
11
20
24
31
35
9.10.2.3 Correlation circuitry
The correlation circuitry calculates the degree of matching between the received and an
expected signal. The output is a measure of the amplitude of the expected signal in the
received signal. This is done for both, the Q and I-channels. The correlator provides two
outputs for each of the two input channels, resulting in a total of four output signals.
The correlation circuitry needs the phase information for the incoming card signal for
optimum performance. This information is defined for the microprocessor using the
BitPhase register. This value defines the phase relationship between the transmitter and
receiver clock in multiples of the BitPhase time (tBitPhase) = 1 / 13.56 MHz.
9.10.2.4 Evaluation and digitizer circuitry
The correlation results are evaluated for each bit-half of the Manchester encoded signal.
The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if
the current bit is valid
• If the bit is valid, its value is identified
• If the bit is not valid, it is checked to identify if it contains a bit-collision
Select the following levels for optimal using RxThreshold register bits:
• MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal
which is considered valid.
• CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the
stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester
encoded signal to generate a bit-collision. If the signal’s strength is below this value,
logic 1 and logic 0 can be determined unequivocally.
After data transmission, the card is not allowed to send its response before a preset time
period which is called the frame guard time in the ISO/IEC 14443 standard. The length of
this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register
defines when the receiver is switched on after data transmission to the card in multiples of
one bit duration.
If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation
circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used.
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Remark: It is recommended to use the Q-clock.
9.11 Serial signal switch
The MFRC500 comprises two main blocks:
• digital circuitry: comprising the state machines, encoder and decoder logic etc.
• analog circuitry: comprising the modulator, antenna drivers, receiver and
amplification circuitry
The interface between these two blocks can be configured so that the interface signals
are routed to pins MFIN and MFOUT. This makes it possible to connect the analog part of
one MFRC500 to the digital part of another device.
9.11.1 Serial signal switch block diagram
Figure 12 shows the serial signal switches. Three different switches are implemented in
the serial signal switch enabling the MFRC500 to be used in different configurations.
The serial signal switch can also be used to check the transmitted and received data
during the design-in phase or for test purposes. Section 15.2.1 on page 94 describes the
analog test signals and measurements at the serial signal switch.
Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The MFRC500
functionality includes the test modes for the SLRC400 using pin MFOUT.
0
1
0
1
2
3
MILLER CODER
1 OUT OF 256
NRZ OR
TX1
TX2
envelope
MFIN
MODULATOR
DRIVER
serial data out
1 OUT OF 4
2
(part of)
analog circuitry
(part of)
serial data processing
Modulator
Source[1:0]
0
1
2
3
0
internal
Manchester out
SUBCARRIER
DEMODULATOR
CARRIER
DEMODULATOR
RX
MANCHESTER
DECODER
Manchester with subcarrier
Manchester
serial data in
2
SUBCARRIER
DEMODULATOR
Decoder
Source[1:0]
3
SERIAL SIGNAL SWITCH
MFOUTSelect[2:0]
digital test signal
signal to MFOUT
0
1
MFIN
MFOUT
001aak617
Fig 12. Serial signal switch block diagram
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Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and
settings used to configure and control the serial signal switch.
9.11.2 Serial signal switch registers
The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal
Manchester decoder and are described in Table 24.
Table 24. DecoderSource[1:0] values
See Table 88 on page 57 for additional information.
Number DecoderSource Input signal to decoder
[1:0]
0
1
2
00
01
10
constant 0
output of the analog part. This is the default configuration
direct connection to pin MFIN; expects an 847.5 kHz subcarrier
signal modulated by a Manchester encoded signal
3
11
direct connection to pin MFIN; expects a Manchester encoded
signal
The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the
transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2.
Table 25. ModulatorSource[1:0] values
See Table 88 on page 57 for additional information.
Number ModulatorSource Input signal to modulator
[1:0]
0
1
2
00
01
10
constant 0 (energy carrier off on pins TX1 and TX2)
constant 1 (continuous energy carrier on pins TX1 and TX2)
modulation signal (envelope) from the internal encoder. This is the
default configuration.
3
11
direct connection to MFIN; expects a Miller pulse coded signal
The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be
routed to pin MFOUT.
Table 26. MFOUTSelect[2:0] values
See Table 102 on page 60 for additional information.
Number MFOUTSelect Signal routed to pin MFOUT
[2:0]
0
1
2
3
000
001
010
011
constant LOW
constant HIGH
modulation signal (envelope) from the internal encoder
serial data stream to be transmitted; the same as for
MFOUTSelect[2:0] = 010 but not encoded by the selected pulse
encoder
4
5
100
101
output signal of the receiver circuit; card modulation signal
regenerated and delayed
output signal of the subcarrier demodulator; Manchester coded card
signal
6
7
110
111
reserved
reserved
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Remark: To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT
bit must be logic 0.
9.11.2.1 Active antenna concept
The MFRC500 analog and digital circuitry is accessed using pins MFIN and MFOUT.
Table 27 lists the required settings.
Table 27. Register settings to enable use of the analog circuitry
Register
Analog circuitry settings
Number[1] Signal
MFRC500 pin
ModulatorSource
MFOUTSelect
3
4
X
Miller pulse encoded
MFIN
MFOUT
-
Manchester encoded with subcarrier
-
DecoderSource
Digital circuitry settings
ModulatorSource
MFOUTSelect
X
2
2
-
-
Miller pulse encoded
MFOUT
MFIN
DecoderSource
Manchester encoded with subcarrier
[1] The number column refers to the value in the number column of Table 24, Table 25 and Table 26.
Two MFRC500 devices configured as described in Table 27 can be connected to each
other using pins MFOUT and MFIN.
9.11.2.2 Driving both RF parts
It is possible to connect both passive and active antennas to a single IC. The passive
antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching
circuit. At the same time an active antenna is connected to pins MFOUT and MFIN. In this
configuration, two RF parts can be driven, one after another, by one microprocessor.
9.12 MIFARE authentication and Crypto1
The security algorithm used in the MIFARE products is called Crypto1. It is based on a
proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards,
knowledge of the key format is needed. The correct key must be available in the
MFRC500 to enable successful card authentication and access to the card’s data stored
in the EEPROM.
After a card is selected as defined in ISO/IEC 14443 A standard, the user can continue
with the MIFARE protocol. It is mandatory that the card authentication is performed.
Crypto1 authentication is a 3-pass authentication which is automatically performed when
the Authent1 and Authent2 commands are executed (see Section 11.6.3 on page 82 and
Section 11.6.4 on page 82).
During the card authentication procedure, the security algorithm is initialized. After a
successful authentication, communication with the MIFARE card is encrypted.
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9.12.1 Crypto1 key handling
On execution of the authentication command, the MFRC500 reads the key from the key
buffer. The key is always read from the key buffer and ensures Crypto1 authentication
commands do not require addressing of a key. The user must ensure the correct key is
prepared in the key buffer before triggering card authentication.
The key buffer can be loaded from:
• the EEPROM using the LoadKeyE2 command (see Section 11.6.1 on page 81)
• the microprocessor’s FIFO buffer using the LoadKey command (see Section 11.6.2
on page 81). This is shown in Figure 13.
WriteE2
EEPROM
KEYS
from the microcontroller
FIFO BUFFER
LoadKey
LoadKeyE2
KEY BUFFER
during
Authent1
serial data stream in
(plain)
serial data stream out
CRYPTO1
MODULE
(encrypted)
001aak624
Fig 13. Crypto1 key handling block diagram
9.12.2 Authentication procedure
The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid
authentication, the correct key has to be available in the key buffer of the MFRC500. This
can be ensured as follows:
1. Load the internal key buffer by using the LoadKeyE2 (see Section 11.6.1 on page 81)
or the LoadKey (see Section 11.6.2 on page 81) commands.
2. Start the Authent1 command (see Section 11.6.3 on page 82). When finished, check
the error flags to obtain the command execution status.
3. Start the Authent2 command (see Section 11.6.4 on page 82). When finished, check
the error flags and bit Crypto1On to obtain the command execution status.
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10. MFRC500 registers
10.1 Register addressing modes
Three methods can be used to operate the MFRC500:
• initiating functions and controlling data by executing commands
• configuring the functional operation using a set of configuration bits
• monitoring the state of the MFRC500 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The MFRC500 can internally address 64 registers using six address lines.
10.1.1 Page registers
The MFRC500 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.
10.1.2 Dedicated address bus
When using the MFRC500 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 28 shows how the register address is assembled.
Table 28. Dedicated address bus: assembling the register address
Register bit: UsePageSelect
Register address
PageSelect2 PageSelect1
1
PageSelect0
A2 A1 A0
10.1.3 Multiplexed address bus
The microprocessor may define all six address lines at once using the MFRC500 with a
multiplexed address bus. In this case either the paging mechanism or linear addressing
can be used.
Table 29 shows how the register address is assembled.
Table 29. Multiplexed address bus: assembling the register address
Multiplexed
address bus
type
UsePage
Select
Register address
Paging mode
1
0
PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0
Linear
AD5
AD4
AD3
AD2 AD1 AD0
addressing
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10.2 Register bit behavior
Bits and flags for different registers behave differently, depending on their functions. In
principle, bits with same behavior are grouped in common registers. Table 30 describes
the function of the Access column in the register tables.
Table 30. Behavior and designation of register bits
Abbreviation Behavior
R/W read and write
Description
These bits can be read and written by the microprocessor.
Since they are only used for control, their content is not
influenced by internal state machines.
Example: TimerReload register may be read and written by
the microprocessor. It will also be read by internal state
machines but never changed by them.
D
dynamic
These bits can be read and written by the microprocessor.
Nevertheless, they may also be written automatically by
internal state machines.
Example: the Command register changes its value
automatically after the execution of the command.
R
read only
write only
These registers hold flags which have a value determined by
internal states only.
Example: the ErrorFlag register cannot be written externally
but shows internal states.
W
These registers are used for control only. They may be written
by the microprocessor but cannot be read. Reading these
registers returns an undefined value.
Example: The TestAnaSelect register is used to determine the
signal on pin AUX however, it is not possible to read its
content.
0, 1 or x
generic value
Where applicable, the values 0 and 1 indicate the expected
logic value for a given bit. Where X is used, any logic value can
be entered
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10.3 Register overview
Table 31. MFRC500 register overview
Sub
Register name
Function
Refer to
address
(Hex)
Page 0: Command and status
00h
01h
02h
03h
04h
05h
06h
07h
Page
selects the page register
Table 33 on page 43
Table 35 on page 44
Command
FIFOData
starts and stops command execution
input and output of 64-byte FIFO buffer
receiver and transmitter and FIFO buffer status flags
number of bytes buffered in the FIFO buffer
secondary status flags
Table 37 on page 44
Table 39 on page 45
Table 41 on page 46
Table 43 on page 46
Table 45 on page 47
Table 47 on page 47
PrimaryStatus
FIFOLength
SecondaryStatus
InterruptEn
InterruptRq
enable and disable interrupt request control bits
interrupt request flags
Page 1: Control and status
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Page
selects the page register
Table 33 on page 43
Table 49 on page 48
Table 51 on page 49
Control
control flags for timer unit, power saving etc
show the error status of the last command executed
ErrorFlag
CollPos
bit position of the first bit-collision detected on the RF interface Table 53 on page 50
TimerValue
CRCResultLSB
CRCResultMSB
BitFraming
value of the timer
Table 55 on page 50
Table 57 on page 50
Table 59 on page 51
Table 61 on page 51
LSB of the CRC coprocessor register
MSB of the CRC coprocessor register
adjustments for bit oriented frames
Page 2: Transmitter and coder control
10h
11h
12h
13h
14h
15h
16h
17h
Page
selects the page register
Table 33 on page 43
Table 63 on page 52
TxControl
CwConductance
PreSet13
PreSet14
ModWidth
PreSet16
PreSet17
controls the operation of the antenna driver pins TX1 and TX2
selects the conductance of the antenna driver pins TX1 and TX2 Table 65 on page 53
do not change these values
do not change these values
selects the modulation pulse width
do not change these values
do not change these values
Table 67 on page 53
Table 69 on page 53
Table 71 on page 54
Table 73 on page 54
Table 75 on page 54
Page 3: Receiver and decoder control
18
Page
selects the page register
Table 33 on page 43
Table 77 on page 55
Table 79 on page 55
Table 81 on page 56
Table 83 on page 56
Table 85 on page 56
Table 87 on page 57
Table 89 on page 57
19
RxControl1
DecoderControl
BitPhase
controls receiver behavior
1A
1B
1C
1D
1Eh
1Fh
controls decoder behavior
selects the bit-phase between transmitter and receiver clock
selects thresholds for the bit decoder
do not change these values
RxThreshold
PreSet1D
RxControl2
ClockQControl
controls decoder and defines the receiver input source
clock control for the 90° phase-shifted Q-channel clock
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Table 31. MFRC500 register overview …continued
Sub
Register name
Function
Refer to
address
(Hex)
Page 4: RF Timing and channel redundancy
20h
21h
22h
Page
selects the page register
Table 33 on page 43
RxWait
selects the interval after transmission before the receiver starts Table 91 on page 58
ChannelRedundancy selects the method and mode used to check data integrity on
the RF channel
Table 93 on page 58
23h
24h
25h
26h
CRCPresetLSB
CRCPresetMSB
PreSet25
preset LSB value for the CRC register
preset MSB value for the CRC register
do not change these values
Table 95 on page 59
Table 97 on page 59
Table 99 on page 59
MFOUTSelect
selects internal signal applied to pin MFOUT, includes the MSB Table 101 on page 60
of value TimeSlotPeriod; see Table 101 on page 60
27h
PreSet27
do not change these values
Table 103 on page 60
Page 5: FIFO, timer and IRQ pin configuration
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Page
selects the page register
Table 33 on page 43
Table 41 on page 46
Table 107 on page 61
Table 109 on page 62
Table 111 on page 62
Table 113 on page 63
Table 115 on page 63
Table 116 on page 63
FIFOLevel
TimerClock
TimerControl
TimerReload
IRQPinConfig
PreSet2E
defines the FIFO buffer overflow and underflow warning levels
selects the timer clock divider
selects the timer start and stop conditions
defines the timer preset value
configures pin IRQ output stage
do not change these values
PreSet2F
do not change these values
Page 6: reserved registers
30h
31h
32h
33h
34h
35h
36h
37h
Page
selects the page register
reserved
Table 33 on page 43
Table 117 on page 63
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Page 7: Test control
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
Page
selects the page register
reserved
Table 33 on page 43
Table 118 on page 64
Table 119 on page 64
Table 121 on page 65
Table 122 on page 65
Table 123 on page 65
Table 125 on page 66
reserved
TestAnaSelect
reserved
selects analog test mode
reserved
reserved
reserved
TestDigiSelect
reserved
selects digital test mode
reserved
reserved
reserved
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10.4 MFRC500 register flags overview
Table 32. MFRC500 register flags overview
Flag(s)
Register
Bit
Address
AccessErr
ErrorFlag
5
0Ah
BitPhase[7:0]
ClkQ180Deg
ClkQCalib
BitPhase
7 to 0 1Bh
ClockQControl
ClockQControl
ClockQControl
ErrorFlag
7
6
1Fh
1Fh
ClkQDelay[4:0]
CollErr
4 to 0 1Fh
0Ah
0
CollLevel[3:0]
CollPos[7:0]
Command[5:0]
CRC3309
RxThreshold
CollPos
3 to 0 1Ch
7 to 0 0Bh
5 to 0 01h
Command
ChannelRedundancy
ChannelRedundancy
ErrorFlag
5
4
3
22h
22h
0Ah
CRC8
CRCErr
CRCPresetLSB[7:0]
CRCPresetMSB[7:0]
CRCReady
CRCResultMSB[7:0]
CRCResultLSB[7:0]
Crypto1On
DecoderSource[1:0]
E2Ready
CRCPresetLSB
CRCPresetMSB
SecondaryStatus
CRCResultMSB
CRCResultLSB
Control
7 to 0 23h
7 to 0 24h
5
05h
7 to 0 0Eh
7 to 0 0Dh
3
09h
RxControl2
1 to 0 1Eh
SecondaryStatus
PrimaryStatus
FIFOData
6
2
05h
03h
Err
FIFOData[7:0]
FIFOLength[6:0]
FIFOOvfl
7 to 0 02h
6 to 0 04h
FIFOLength
ErrorFlag
4
0
2
0Ah
09h
0Ah
FlushFIFO
FramingErr
Gain[1:0]
Control
ErrorFlag
RxControl1
1 to 0 19h
5 to 0 12h
GsCfgCW[5:0]
HiAlert
CwConductance
PrimaryStatus
InterruptEn
1
1
1
2
2
7
3
1
0
6
0
03h
06h
07h
06h
07h
01h
03h
2Dh
2Dh
0Ah
03h
HiAlertIEn
HiAlertIRq
InterruptRq
IdleIEn
InterruptEn
IdleIRq
InterruptRq
IFDetectBusy
IRq
Command
PrimaryStatus
IRQPinConfig
IRQPinConfig
ErrorFlag
IRQInv
IRQPushPull
KeyErr
LoAlert
PrimaryStatus
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Table 32. MFRC500 register flags overview …continued
Flag(s)
Register
Bit
0
Address
06h
LoAlertIEn
InterruptEn
InterruptRq
MFOUTSelect
RxThreshold
PrimaryStatus
TxControl
LoAlertIRq
0
07h
MFOUTSelect[2:0]
MinLevel[3:0]
2 to 0 26h
7 to 4 1Ch
6 to 4 03h
6 to 5 11h
7 to 0 15h
ModemState[2:0]
ModulatorSource[1:0]
ModWidth[7:0]
PageSelect[2:0]
ModWidth
Page
2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
ParityEn
ChannelRedundancy
ErrorFlag
0
1
1
4
7
22h
0Ah
22h
09h
1Eh
ParityErr
ParityOdd
ChannelRedundancy
Control
PowerDown
RcvClkSelI
RxAlign[2:0]
RxAutoPD
RxControl2
BitFraming
6 to 4 0Fh
RxControl2
6
3
3
3
1Eh
22h
06h
07h
RxCRCEn
ChannelRedundancy
InterruptEn
RxIEn
RxIRq
InterruptRq
RxLastBits[2:0]
RxMultiple
SecondaryStatus
DecoderControl
RxWait
2 to 0 05h
1Ah
7 to 0 21h
6
RxWait[7:0]
SetIEn
InterruptEn
7
7
7
5
5
06h
07h
3Dh
09h
2Ah
SetIRq
InterruptRq
SignalToMFOUT
StandBy
TestDigiSelect
Control
TAutoRestart
TestAnaOutSel[4:0]
TestDigiSignalSel[6:0]
TimerIEn
TimerClock
TestAnaSelect
TestDigiSelect
InterruptEn
3 to 0 3Ah
6 to 0 3Dh
5
5
06h
07h
TimerIRq
InterruptRq
TimerValue[7:0]
TPreScaler[4:0]
TReloadValue[7:0]
TRunning
TimerValue
7 to 0 0Ch
4 to 0 2Ah
7 to 0 2Ch
TimerClock
TimerReload
SecondaryStatus
TimerControl
TimerControl
Control
7
0
1
1
2
3
2
05h
2Bh
2Bh
09h
2Bh
2Bh
09h
TStartTxBegin
TStartTxEnd
TStartNow
TStopRxBegin
TStopRxEnd
TStopNow
TimerControl
TimerControl
Control
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Table 32. MFRC500 register flags overview …continued
Flag(s)
Register
Bit
0
Address
11h
TX1RFEn
TX2Cw
TxControl
TxControl
3
11h
TX2Inv
TxControl
3
11h
TX2RFEn
TxCRCEn
TxIEn
TxControl
1
11h
ChannelRedundancy
InterruptEn
InterruptRq
BitFraming
Page
2
22h
4
06h
TxIRq
4
07h
TxLastBits[2:0]
UsePageSelect
2 to 0 0Fh
00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
5 to 0 29h
1Ah
7
WaterLevel[5:0]
ZeroAfterColl
FIFOLevel
DecoderControl
5
10.5 Register descriptions
10.5.1 Page 0: Command and status
10.5.1.1 Page register
Selects the page register.
Table 33. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
reset value: 1000 0000b, 80h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
UsePageSelect
R/W
0000
R/W
PageSelect[2:0]
R/W
R/W
R/W
Table 34. Page register bit descriptions
Bit
Symbol
Value Description
7
UsePageSelect 1
the value of PageSelect[2:0] is used as the register address
A5, A4, and A3. The LSBs of the register address are
defined using the address pins or the internal address latch,
respectively.
0
the complete content of the internal address latch defines
the register address. The address pins are used as
described in Table 5 on page 8.
6 to 3
2 to 0
0000
-
reserved
PageSelect[2:0] -
when UsePageSelect = logic 1, the value of PageSelect is
used to specify the register page (A5, A4 and A3 of the
register address)
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10.5.1.2 Command register
Starts and stops the command execution.
Table 35. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation
Bit
7
IFDetectBusy
R
6
0
5
4
3
2
1
0
Symbol
Access
Command[5:0]
D
R
Table 36. Command register bit descriptions
Bit
Symbol
Value Description
7
IFDetectBusy
shows the status of interface detection logic
interface detection finished successfully
interface detection ongoing
reserved
0
1
-
6
0
5 to 0
Command[5:0]
-
activates a command based on the Command code.
Reading this register shows which command is being
executed.
10.5.1.3 FIFOData register
Input and output of the 64 byte FIFO buffer.
Table 37. FIFOData register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
FIFOData[7:0]
D
Table 38. FIFOData register bit descriptions
Bit
Symbol
Description
7 to 0
FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO
buffer acts as a parallel in to parallel out converter for all data streams.
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10.5.1.4 PrimaryStatus register
Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 39. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation
Bit
7
0
6
5
4
3
IRq
R
2
Err
R
1
HiAlert
R
0
LoAlert
R
Symbol
Access
ModemState[2:0]
R
R
Table 40. PrimaryStatus register bit descriptions
Bit
Symbol
Value Status
Description
7
0
-
reserved
6 to 4 ModemState[2:0]
shows the state of the transmitter and receiver
state machines:
000
Idle
neither the transmitter or receiver are operating;
neither of them are started or have input data
001
010
TxSOF
TxData
transmit start of frame pattern
transmit data from the FIFO buffer (or
redundancy CRC check bits)
011
100
TxEOF
transmit End Of Frame (EOF) pattern
GoToRx1
GoToRx2
PrepareRx
intermediate state 1; receiver starts
intermediate state 2; receiver finishes
101
110
waiting until the RxWait register time period
expires
AwaitingRx
Receiving
receiver activated; waiting for an input signal on
pin RX
111
-
receiving data
3
IRq
shows any interrupt source requesting attention
based on the InterruptEn register flag settings
2
1
Err
1
1
any error flag in the ErrorFlag register is set
HiAlert
the alert level for the number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
HiAlert = (64 – FIFOLength) ≤ WaterLevel
otherwise value = logic 0
Example:
FIFOLength = 60, WaterLevel = 4 then
HiAlert = logic 1
FIFOLength = 59, WaterLevel = 4 then
HiAlert = logic 0
0
LoAlert
1
the alert level for number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
LoAlert = FIFOLength ≤ WaterLevel otherwise
value = logic 0
Example:
FIFOLength = 4, WaterLevel = 4 then
LoAlert = logic 1
FIFOLength = 5, WaterLevel = 4 then
LoAlert = logic 0
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10.5.1.5 FIFOLength register
Number of bytes in the FIFO buffer.
Table 41. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation
Bit
7
0
6
5
4
3
2
1
0
Symbol
Access
FIFOLength[6:0]
R
R
Table 42. FIFOLength bit descriptions
Bit
Symbol
Description
7
0
reserved
6 to 0 FIFOLength[6:0]
gives the number of bytes stored in the FIFO buffer. Writing
increments the FIFOLength register value while reading decrements
the FIFOLength register value
10.5.1.6 SecondaryStatus register
Various secondary status flags.
Table 43. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TRunning E2Ready CRCReady
00
R
RxLastBits[2:0]
R
R
R
R
Table 44. SecondaryStatus register bit descriptions
Bit
Symbol
Value Description
7
TRunning
1
the timer unit is running and the counter decrements the
TimerValue register on the next timer clock cycle
0
1
0
1
0
-
the timer unit is not running
EEPROM programming is finished
EEPROM programming is ongoing
CRC calculation is finished
CRC calculation is ongoing
reserved
6
5
E2Ready
CRCReady
4 to 3 00
2 to 0 RxLastBits[2:0]
-
shows the number of valid bits in the last received byte. If zero,
the whole byte is valid
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10.5.1.7 InterruptEn register
Control bits to enable and disable passing of interrupt requests.
Table 45. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
Bit
7
SetIEn
W
6
0
5
4
3
2
1
0
Symbol
Access
TimerIEn
R/W
TxIEn
R/W
RxIEn IdleIEn HiAlertIEn LoAlertIEn
R/W R/W R/W R/W
R/W
Table 46. InterruptEn register bit descriptions
Bit Symbol Value Description
7
SetIEn
1
0
-
indicates that the marked bits in the InterruptEn register are set
clears the marked bits
6
5
4
3
2
1
0
0
reserved
TimerIEn
TxIEn
-
sends the TimerIRq timer interrupt request to pin IRQ[1]
sends the TxIRq transmitter interrupt request to pin IRQ[1]
sends the RxIRq receiver interrupt request to pin IRQ[1]
sends the IdleIRq idle interrupt request to pin IRQ[1]
sends the HiAlertIRq high alert interrupt request to pin IRQ[1]
sends the LoAlertIRq low alert interrupt request to pin IRQ[1]
-
RxIEn
IdleIEn
HiAlertIEn
-
-
-
LoAlertIEn -
[1] This bit can only be set or cleared using bit SetIEn.
10.5.1.8 InterruptRq register
Interrupt request flags.
Table 47. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
Bit
7
SetIRq
W
6
0
5
TimerIRq
D
4
TxIRq
D
3
2
1
0
Symbol
Access
RxIRq IdleIRq HiAlertIRq LoAlertIRq
R/W
D
D
D
D
Table 48. InterruptRq register bit descriptions
Bit Symbol Value Description
7
SetIRq
1
0
-
sets the marked bits in the InterruptRq register
clears the marked bits in the InterruptRq register
reserved
6
5
0
TimerIRq
1
0
1
timer decrements the TimerValue register to zero
timer decrements are still greater than zero
4
TxIRq
TxIRq is set to logic 1 if one of the following events occurs:
Transceive command; all data transmitted
Authent1 and Authent2 commands; all data transmitted
WriteE2 command; all data is programmed
CalcCRC command; all data is processed
0
when not acted on by Transceive, Authent1, Authent2, WriteE2 or
CalcCRC commands
3
RxIRq
1
0
the receiver terminates
reception still ongoing
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Table 48. InterruptRq register bit descriptions …continued
Bit Symbol Value Description
2
IdleIRq
1
command terminates correctly. For example; when the Command
register changes its value from any command to the Idle command.
If an unknown command is started the IdleIRq bit is set.
Microprocessor start-up of the Idle command does not set the
IdleIRq bit.
0
1
0
1
0
IdleIRq = logic 0 in all other instances
PrimaryStatus register HiAlert bit is set[1]
PrimaryStatus register HiAlert bit is not set
PrimaryStatus register LoAlert bit is set[1]
PrimaryStatus register LoAlert bit is not set
1
0
HiAlertIRq
LoAlertIRq
[1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq.
10.5.2 Page 1: Control and status
10.5.2.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.2.2 Control register
Various control flags, for timer, power saving, etc.
Table 49. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00
StandBy PowerDown Crypto1On TStopNow TStartNow FlushFIFO
R/W
D
D
D
W
W
W
Table 50. Control register bit descriptions
Bit Symbol Value Description
7 to 6 00
-
reserved
5
4
3
StandBy
1
activates Standby mode. The current consuming blocks are
switched off but the clock keeps running
PowerDown
Crypto1On
1
1
0
activates Power-down mode. The current consuming blocks
are switched off including the clock
Crypto1 unit is switched on and all data communication with
the card is encrypted[1]
Crypto1 unit is switched off. All data communication with the
card is unencrypted (plain)
2
1
0
TStopNow
TStartNow
FlushFIFO
1
1
1
immediately stops the timer[2]
immediately starts the timer[2]
immediately clears the internal FIFO buffer’s read and write
pointer, the FIFOLength[6:0] bits are set to logic 0 and the
FIFOOvfl flag[2]
[1] This bit can only be set to logic 1 by successful execution of the Authent2 command
[2] Reading this bit always returns logic 0
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10.5.2.3 ErrorFlag register
Error flags show the error status of the last executed command.
Table 51. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation
Bit
7
0
6
5
4
3
2
1
0
Symbol
Access
KeyErr AccessErr FIFOOvfl CRCErr FramingErr ParityErr CollErr
R
R
R
R
R
R
R
R
Table 52. ErrorFlag register bit descriptions
Bit Symbol Value Description
7
6
0
-
reserved
KeyErr
1
set when the LoadKeyE2 or LoadKey command recognize that the
input data is not encoded based on the key format definition
0
1
0
1
set when the LoadKeyE2 or the LoadKey command starts
set when the access rights to the EEPROM are violated
set when an EEPROM related command starts
5
AccessErr
4
3
FIFOOvfl
CRCErr
set when the microprocessor or MFRC500 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full
1
0
set when RxCRCEn is set and the CRC fails
automatically set during the PrepareRx state in the receiver start
phase
2
1
0
FramingErr
ParityErr
CollErr
1
0
set when the SOF is incorrect
automatically set during the PrepareRx state in the receiver start
phase
1
0
set when the parity check fails
automatically set during the PrepareRx state in the receiver start
phase
1
0
set when a bit-collision is detected
automatically set during the PrepareRx state in the receiver start
phase
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10.5.2.4 CollPos register
Bit position of the first bit-collision detected on the RF interface.
Table 53. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CollPos[7:0]
R
Table 54. CollPos register bit descriptions
Bit Symbol Description
7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a
received frame.
Example:
00h indicates a bit collision in the start bit
01h indicates a bit collision in the 1st bit
...
08h indicates a bit collision in the 8th bit
10.5.2.5 TimerValue register
Value of the timer.
Table 55. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TimerValue[7:0]
R
Table 56. TimerValue register bit descriptions
Bit
Symbol
Description
7 to 0
TimerValue[7:0] this register shows the timer counter value
10.5.2.6 CRCResultLSB register
LSB of the CRC coprocessor register.
Table 57. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CRCResultLSB[7:0]
R
Table 58. CRCResultLSB register bit descriptions
Bit Symbol Description
7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if
CRCReady = logic 1
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10.5.2.7 CRCResultMSB register
MSB of the CRC coprocessor register.
Table 59. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CRCResultMSB[7:0]
R
Table 60. CRCResultMSB register bit descriptions
Bit
Symbol
Description
7 to 0
CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if
CRCReady = logic 1.
The register’s value is undefined for 8-bit CRC calculation.
10.5.2.8 BitFraming register
Adjustments for bit oriented frames.
Table 61. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
Bit
7
0
6
5
RxAlign[2:0]
D
4
3
0
2
1
0
Symbol
Access
TxLastBits[2:0]
D
R/W
R/W
Table 62. BitFraming register bit descriptions
Bit
Symbol
Value Description
7
0
-
reserved
6 to 4 RxAlign[2:0]
defines the bit position in the FIFO buffer for the first bit received
and stored. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
000
001
the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
...
111
the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0
3
0
-
-
reserved
2 to 0 TxLastBits[2:0]
defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.
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10.5.3 Page 2: Transmitter and control
10.5.3.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.3.2 TxControl register
Controls the logical behavior of the antenna pins TX1 and TX2.
Table 63. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation
Bit
7
0
6
5
4
1
3
2
1
0
Symbol
Access
ModulatorSource[1:0]
R/W
TX2Inv TX2Cw TX2RFEn TX1RFEn
R/W R/W R/W R/W
R/W
R/W
Table 64. TxControl register bit descriptions
Bit
7
Symbol
Value Description
0
-
this value must not be changed
6 to 5
ModulatorSource[1:0]
selects the source for the modulator input:
modulator input is LOW
00
01
10
11
-
modulator input is HIGH
modulator input is the internal encoder
modulator input is pin MFIN
4
3
1
this value must not be changed
TX2Inv
1
delivers an inverted 13.56 MHz energy carrier output
signal on pin TX2
2
1
0
TX2Cw
1
delivers a continuously unmodulated 13.56 MHz
energy carrier output signal on pin TX2
0
1
enables modulation of the 13.56 MHz energy carrier
TX2RFEn
TX1RFEn
the output signal on pin TX2 is the 13.56 MHz energy
carrier modulated by the transmission data
0
1
TX2 is driven at a constant output level
the output signal on pin TX1 is the 13.56 MHz energy
carrier modulated by the transmission data
0
TX1 is driven at a constant output level
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10.5.3.3 CwConductance register
Selects the conductance of the antenna driver pins TX1 and TX2.
Table 65. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00
GsCfgCW[5:0]
R/W
R/W
Table 66. CwConductance register bit descriptions
Bit
Symbol
00
Value Description
7 to 6
5 to 0
0
-
these values must not be changed
GsCfgCW[5:0]
defines the conductance register value for the output driver.
This can be used to regulate the output power/current
consumption and operating distance.
See Section 9.9.3.1 for detailed information about GsCfgCW[5:0].
10.5.3.4 PreSet13 register
These bit settings must not be changed.
Table 67. PreSet13 register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00
11111
R/W
R/W
Table 68. PreSet13 register bit descriptions
Bit
Symbol
00
Value Description
7 to 6
5 to 0
0
-
these values must not be changed
these values must not be changed
11111
10.5.3.5 PreSet14 register
These bit settings must not be changed.
Table 69. PreSet14 register (address: 14h) reset value: 0001 1001b, 19h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
000
11
00
1
R/W
R/W
R/W
R/W
Table 70. PreSet14 register bit descriptions
Bit
Symbol
Value
Description
7 to 5 000
4 to 3 11
2 to 1 00
0
1
0
1
these values must not be changed
these values must not be changed
these values must not be changed
these values must not be changed
0
1
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10.5.3.6 ModWidth register
Selects the pulse-modulation width.
Table 71. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
ModWidth[7:0]
R/W
Table 72. ModWidth register bit descriptions
Bit
Symbol
Description
7 to 0
ModWidth[7:0]
defines the width of the modulation pulse based on
tmod = 2⋅(ModWidth + 1) / fclk
10.5.3.7 PreSet16 register
These bit settings must not be changed.
Table 73. PreSet16 register (address: 16h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00000000
R/W
Table 74. PreSet16 register bit descriptions
Bit Symbol Value Description
these values must not be changed
7 to 0 00000000
0
10.5.3.8 PreSet17 register
These bit settings must not be changed.
Table 75. PreSet17 register (address: 17h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00000000
R/W
Table 76. PreSet17 register bit descriptions
Bit Symbol Value Description
7 to 0 00000000 these values must not be changed
0
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10.5.4 Page 3: Receiver and decoder control
10.5.4.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.4.2 RxControl1 register
Controls receiver operation.
Table 77. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation
Bit
7
0
6
5
4
3
2
1
0
Symbol
Access
111
R/W
00
Gain[1:0]
R/W
R/W
R/W
Table 78. RxControl1 register bit descriptions
Bit
Symbol
Value Description
7
0
0
1
0
these values must not be changed
these values must not be changed
these values must not be changed
6 to 4 111
3 to 2 00
1 to 0 Gain[1:0]
defines the receiver’s signal voltage gain factor
20 dB gain factor
00
01
10
11
24 dB gain factor
31 dB gain factor
35 dB gain factor
10.5.4.3 DecoderControl register
Controls decoder operation.
Table 79. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit
allocation
Bit
7
0
6
5
4
0
3
1
2
1
0
Symbol
Access
RxMultiple ZeroAfterColl
R/W R/W
000
R/W
R/W
R/W
R/W
Table 80. DecoderControl register bit descriptions
Bit
7
Symbol
0
Value Description
-
this value must not be changed
6
RxMultiple
0
1
1
after receiving one frame, the receiver is deactivated
enables reception of more than one frame
5
ZeroAfterColl
any bits received after a bit-collision are masked to zero. This
helps to resolve the anti-collision procedure as defined in
ISO/IEC 14443 A
4
3
0
1
0
1
0
this value must not be changed
this value must not be changed
these values must not be changed
2 to 0 000
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10.5.4.4 BitPhase register
Selects the bit-phase between transmitter and receiver clock.
Table 81. BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
BitPhase[7:0]
R/W
Table 82. BitPhase register bit descriptions
Bit
Symbol
Description
7 to 0
BitPhase[7:0]
defines the phase relationship between transmitter and receiver clock
Remark: The correct value of this register is essential for proper
operation.
10.5.4.5 RxThreshold register
Selects thresholds for the bit decoder.
Table 83. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
MinLevel[3:0]
R/W
CollLevel[3:0]
R/W
Table 84. RxThreshold register bit descriptions
Bit
Symbol
Description
7 to 4
MinLevel[3:0]
the minimum signal strength the decoder will accept. If the signal
strength is below this level, it is not evaluated.
3 to 0
CollLevel[3:0]
the minimum signal strength the decoder input that must be reached
by the weaker half-bit of the Manchester encoded signal to generate
a bit-collision (relative to the amplitude of the stronger half-bit)
10.5.4.6 PreSet1D Register
These bit settings must not be changed.
Table 85. PreSet1D register (address: 1Dh) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
00000000
R/W
3
2
1
0
Symbol
Access
Table 86. PreSet1D register bit descriptions
Bit Symbol Value Description
7 to 0 00000000 these values must not be changed
0
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10.5.4.7 RxControl2 register
Controls decoder behavior and defines the input source for the receiver.
Table 87. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
RcvClkSelI RxAutoPD
R/W R/W
0000
R/W
DecoderSource[1:0]
R/W
Table 88. RxControl2 register bit descriptions
Bit
Symbol
Value Description
7
RcvClkSelI
1
0
1
I-clock is used as the receiver clock[1]
Q-clock is used as the receiver clock[1]
6
RxAutoPD
receiver circuit is automatically switched on before
receiving and switched off afterwards. This can be used to
reduce current consumption.
0
-
receiver is always activated
these values must not be changed
selects the source for the decoder input
LOW
5 to 2 0000
1 to 0 DecoderSource[1:0]
00
01
10
internal demodulator
a subcarrier modulated Manchester encoded signal on
pin MFIN
11
a baseband Manchester encoded signal on pin MFIN
[1] I-clock and Q-clock are 90° phase-shifted from each other.
10.5.4.8 ClockQControl register
Controls clock generation for the 90° phase-shifted Q-clock.
Table 89. ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation
Bit
7
6
5
0
4
3
2
1
0
Symbol
Access
ClkQ180Deg ClkQCalib
R/W
ClkQDelay[4:0]
D
R
R/W
Table 90. ClockQControl register bit descriptions
Bit
Symbol
Value Description
7
ClkQ180Deg
1
0
0
Q-clock is phase-shifted more than 180° compared to the
I-clock
Q-clock is phase-shifted less than 180° compared to the
I-clock
6
ClkQCalib
Q-clock is automatically calibrated after the reset phase and
after data reception from the card
1
-
no calibration is performed automatically
this value must not be changed
5
0
4 to 0
ClkQDelay[4:0]
-
this register shows the number of delay elements used to
generate a 90° phase-shift of the I-clock to obtain the
Q-clock. It can be written directly by the microprocessor or
by the automatic calibration cycle.
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10.5.5 Page 4: RF Timing and channel redundancy
10.5.5.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.5.2 RxWait register
Selects the time interval after transmission, before the receiver starts.
Table 91. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation
Bit
7
6
5
4
3
RxWait[7:0]
R/W
2
1
0
Symbol
Access
Table 92. RxWait register bit descriptions
Bit
Symbol
Function
7 to 0
RxWait[7:0]
after data transmission, the activation of the receiver is delayed
for RxWait bit-clock cycles. During this frame guard time any
signal on pin RX is ignored.
10.5.5.3 ChannelRedundancy register
Selects kind and mode of checking the data integrity on the RF channel.
Table 93. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00
R/W R/W
CRC3309
R/W
CRC8 RxCRCEn TxCRCEn ParityOdd ParityEn
R/W R/W R/W R/W R/W
Table 94. ChannelRedundancy bit descriptions
Bit Symbol Value Function
7 to 6 00
-
this value must not be changed
5
CRC3309
1
CRC calculation is performed using ISO/IEC 3309 and
ISO/IEC 15693
0
1
0
1
CRC calculation is performed using ISO/IEC 14443 A
an 8-bit CRC is calculated
4
3
CRC8
a 16-bit CRC is calculated
RxCRCEn
the last byte(s) of a received frame are interpreted as CRC bytes. If
the CRC is correct, the CRC bytes are not passed to the FIFO. If
the CRC bytes are incorrect, the CRCErr flag is set.
0
1
no CRC is expected
2
TxCRCEn
a CRC is calculated over the transmitted data and the CRC bytes
are appended to the data stream
0
no CRC is transmitted
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Table 94. ChannelRedundancy bit descriptions …continued
Bit
Symbol
Value Function
1
ParityOdd
1
0
1
odd parity is generated or expected[1]
even parity is generated or expected
0
ParityEn
a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte (MIFARE,
ISO/IEC 14443 A)
0
no parity bit is inserted or expected
[1] With ISO/IEC 14443 A, this bit must be set to logic 1.
10.5.5.4 CRCPresetLSB register
LSB of the preset value for the CRC register.
Table 95. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CRCPresetLSB[7:0]
R/W
Table 96. CRCPresetLSB register bit descriptions
Bit
Symbol
Description
7 to 0
CRCPresetLSB[7:0] defines the start value for CRC calculation. This value is loaded
into the CRC at the beginning of transmission, reception and
the CalcCRC command (if CRC calculation is enabled).
10.5.5.5 CRCPresetMSB register
MSB of the preset value for the CRC register.
Table 97. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CRCPresetMSB[7:0]
R/W
Table 98. CRCPresetMSB bit descriptions
Bit Symbol Description
7 to 0 CRCPresetMSB[7:0]
defines the starting value for CRC calculation. This value is
loaded into the CRC at the beginning of transmission, reception
and the CalcCRC command (if the CRC calculation is enabled)
Remark: This register is not relevant if CRC8 is set to logic 1.
10.5.5.6 PreSet25 register
These values must not be changed.
Table 99. PreSet25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00000000
R/W
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Table 100. PreSet25 register bit descriptions
Bit
Symbol
Value Description
0 these values must not be changed
7 to 0
00000000
10.5.5.7 MFOUTSelect register
Selects the internal signal applied to pin MFOUT.
Table 101. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00000
R/W
MFOUTSelect[2:0]
R/W
Table 102. MFOUTSelect register bit descriptions
Bit
Symbol
Value
Description
7 to 3 00000
0
these values must not be changed
defines which signal is routed to pin MFOUT:
constant LOW
2 to 0 MFOUTSelect[2:0]
000
001
010
constant HIGH
modulation signal (envelope) from the internal
encoder, (Miller coded)
011
100
serial data stream, not Miller encoded
output signal of the energy carrier demodulator (card
modulation signal)[1]
101
output signal of the subcarrier demodulator
(Manchester encoded card signal)[1]
110
111
reserved
reserved
[1] Only valid for MIFARE and ISO/IEC 14443 A communication at 106 kBd.
10.5.5.8 PreSet27 register
Table 103. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
xxxxxxxx
W
Table 104. PreSet27 register bit descriptions
Bit
Symbol
Value Description
these values can be logic 1 or logic 0
7 to 0
xxxxxxxx
0
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10.5.6 Page 5: FIFO, timer and IRQ pin configuration
10.5.6.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.6.2 FIFOLevel register
Defines the levels for FIFO underflow and overflow warning.
Table 105. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00
WaterLevel[5:0]
R/W
R/W
Table 106. FIFOLevel register bit descriptions
Bit Symbol Description
7 to 6 00 these values must not be changed
5 to 0 WaterLevel[5:0] defines, the warning level of a FIFO buffer overflow or underflow:
HiAlert is set to logic 1 if the remaining FIFO buffer space is equal to,
or less than, WaterLevel[5:0] bits in the FIFO buffer.
LoAlert is set to logic 1 if equal to, or less than, WaterLevel[5:0] bits in
the FIFO buffer.
10.5.6.3 TimerClock register
Selects the divider for the timer clock.
Table 107. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
00
TAutoRestart
RW
TPreScaler[4:0]
RW
RW
Table 108. TimerClock register bit descriptions
Bit Symbol Value Function
7 to 6 00
0
1
these values must not be changed
5
TAutoRestart
the timer automatically restarts its countdown from the
TReloadValue[7:0] instead of counting down to zero
0
-
the timer decrements to zero and register InterruptIRq
TimerIRq bit is set to logic 1
4 to 0 TPreScaler[4:0]
defines the timer clock frequency (fTimerClock). The
TPreScaler[4:0] can be adjusted from 0 to 21. The following
formula is used to calculate the TimerClock frequency
(fTimerClock):
f
TimerClock = 13.56 MHz / 2TPreScaler [MHz]
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10.5.6.4 TimerControl register
Selects start and stop conditions for the timer.
Table 109. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
0000
R/W
TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin
R/W R/W R/W R/W
Table 110. TimerControl register bit descriptions
Bit Symbol Value Description
7 to 4 0000
0
1
0
1
0
1
these values must not be changed
3
2
1
TStopRxEnd
the timer automatically stops when data reception ends
the timer is not influenced by this condition
TStopRxBegin
TStartTxEnd
the timer automatically stops when the first valid bit is received
the timer is not influenced by this condition
the timer automatically starts when data transmission ends. If
the timer is already running, the timer restarts by loading
TReloadValue[7:0] into the timer.
0
1
the timer is not influenced by this condition
0
TStartTxBegin
the timer automatically starts when the first bit is transmitted. If
the timer is already running, the timer restarts by loading
TReloadValue[7:0] into the timer.
0
the timer is not influenced by this condition
10.5.6.5 TimerReload register
Defines the preset value for the timer.
Table 111. TimerReload register (address: 2Ch) reset value: 0000 1010b, 0Ah bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TReloadValue[7:0]
R/W
Table 112. TimerReload register bit descriptions
Bit Symbol Description
7 to 0 TReloadValue[7:0] on a start event, the timer loads the TReloadValue[7:0] value.
Changing this register only affects the timer on the next start event. If
TReloadValue[7:0] is set to logic 0 the timer cannot start.
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10.5.6.6 IRQPinConfig register
Configures the output stage for pin IRQ.
Table 113. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
000000
R/W
IRQInv IRQPushPull
R/W R/W
Table 114. IRQPinConfig register bit descriptions
Bit
7 to 2
1
Symbol
000000
IRQInv
Value Description
0
1
0
1
0
these values must not be changed
inverts the signal on pin IRQ with respect to bit IRq
the signal on pin IRQ is not inverted and is the same as bit IRq
pin IRQ functions as a standard CMOS output pad
pin IRQ functions as an open-drain output pad
0
IRQPushPull
10.5.6.7 PreSet2E register
Table 115. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
0
Symbol
Access
xxxxxxxx
W
10.5.6.8 PreSet2F register
Table 116. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
Symbol
Access
xxxxxxxx
W
10.5.7 Page 6: reserved
10.5.7.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h
Table 117. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h)
reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
xxxxxxxx
W
Remark: These registers are reserved for future use.
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10.5.8 Page 7: Test control
10.5.8.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.8.2 Reserved register 39h
Table 118. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
xxxxxxxx
W
Remark: This register is reserved for future use.
10.5.8.3 TestAnaSelect register
Selects analog test signals.
Table 119. TestAnaSelect register (address: 3Ah) reset value: 0000 0000b, 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
0000
W
TestAnaOutSel[4:0]
W
Table 120. TestAnaSelect bit descriptions
Bit
Symbol
Value Description
7 to 4
3 to 0
0000
0
these values must not be changed
TestAnaOutSel[4:0]
selects the internal analog signal to be routed to the AUX
pin. See Section 15.2.2 on page 96 for detailed
information. The settings are as follows:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VMID
Vbandgap
VRxFollI
VRxFollQ
VRxAmpI
VRxAmpQ
VCorrNI
VCorrNQ
VCorrDI
VCorrDQ
VEvalL
VEvalR
VTemp
reserved
reserved
reserved
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10.5.8.4 Reserved register 3Bh
Table 121. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
xxxxxxxx
W
Remark: This register is reserved for future use.
10.5.8.5 Reserved register 3Ch
Table 122. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
xxxxxxxx
W
Remark: This register is reserved for future use.
10.5.8.6 TestDigiSelect register
Selects digital test mode.
Table 123. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
SignalToMFOUT
W
6
5
4
3
2
1
0
Symbol
Access
TestDigiSignalSel[6:0]
W
Table 124. TestDigiSelect register bit descriptions
Bit
Symbol
Value Description
7
SignalToMFOUT
1
overrules the MFOUTSelect[2:0] setting and routes the
digital test signal defined with the TestDigiSignalSel[6:0]
bits to pin MFOUT
0
-
MFOUTSelect[2:0] defines the signal on pin MFOUT
6 to 0 TestDigiSignalSel[6:0]
selects the digital test signal to be routed to pin MFOUT.
Refer to Section 15.2.3 on page 97 for detailed
information. The following lists the signal names for the
TestDigiSignalSel[6:0] addresses:
F4h
E4h
D4h
C4h
B5h
A5h
96h
s_data
s_valid
s_coll
s_clock
rd_sync
wr_sync
int_clock
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10.5.8.7 Reserved registers 3Eh, 3Fh
Table 125. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
xxxxxxxx
W
Remark: This register is reserved for future use.
11. MFRC500 command set
MFRC500 operation is determined by an internal state machine capable of performing a
command set. The commands can be started by writing the command code to the
Command register. Arguments and/or data necessary to process a command are mainly
exchanged using the FIFO buffer.
• Each command needing a data stream (or data byte stream) as an input immediately
processes the data in the FIFO buffer
• Each command that requires arguments only starts processing when it has received
the correct number of arguments from the FIFO buffer
• The FIFO buffer is not automatically cleared at the start of a command. It is, therefore,
possible to write command arguments and/or the data bytes into the FIFO buffer
before starting a command.
• Each command (except the StartUp command) can be interrupted by the
microprocessor writing a new command code to the Command register e.g. the Idle
command.
11.1 MFRC500 command overview
Table 126. MFRC500 commands overview
Command
Value Action
FIFO communication
Arguments and data
sent
Data received
StartUp
3Fh
runs the reset and initialization phase. See
-
-
Section 11.1.2 on page 68.
Remark: This command can only be activated by
Power-On or Hard resets.
Idle
00h
1Ah
16h
no action; cancels execution of the current command.
See Section 11.1.3 on page 68
-
-
Transmit
Receive
transmits data from the FIFO buffer to the card. See
Section 11.2.1 on page 69
data stream
-
-
activates receiver circuitry. Before the receiver starts,
the state machine waits until the time defined in the
RxWait register has elapsed. See Section 11.2.2 on
page 72.
data stream
Remark: This command may be used for test
purposes only, since there is no timing relationship to
the Transmit command.
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Table 126. MFRC500 commands overview …continued
Command
Value Action
FIFO communication
Arguments and data
sent
Data received
Transceive[1] 1Eh
transmits data from FIFO buffer to the card and
automatically activates the receiver after
data stream
data stream
transmission. The receiver waits until the time defined
in the RxWait register has elapsed before starting.
See Section 11.2.3 on page 75.
WriteE2
ReadE2
01h
03h
reads data from the FIFO buffer and writes it to the
EEPROM. See Section 11.3.1 on page 77.
start address LSB
start address MSB
data byte stream
start address LSB
start address MSB
number of data bytes
start address LSB
start address MSB
-
reads data from the EEPROM and sends it to the
FIFO buffer. See Section 11.3.2 on page 79.
data bytes
Remark: Keys cannot be read back
LoadKeyE2 0Bh
copies a key from the EEPROM into the key buffer
See Section 11.6.1 on page 81.
-
-
LoadKey
Authent1
19h
reads a key from the FIFO buffer and loads it into the byte 0 LSB
key buffer. See Section 11.6.2 on page 81.
byte 1
Remark: The key has to be prepared in a specific
format (refer to Section 9.2.3.1 “Key format” on page
13)
…
byte 10
byte 11 MSB
0Ch
performs the first part of card authentication using the card Authent1 command
-
Crypto1 algorithm. See Section 11.6.3 on page 82.
card block address
card serial number LSB
card serial number byte 1
card serial number byte 2
card serial number MSB
Authent2
14h
performs the second part of card authentication using
the Crypto1 algorithm. See Section 11.6.4 on
page 82.
-
-
LoadConfig
CalcCRC
07h
12h
reads data from EEPROM and initializes the
MFRC500 registers. See Section 11.4.1 on page 79.
start address LSB
start address MSB
data byte stream
-
-
activates the CRC coprocessor
Remark: The result of the CRC calculation is read
from the CRCResultLSB and CRCResultMSB
registers. See Section 11.4.2 on page 80.
[1] This command is the combination of the Transmit and Receive commands.
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11.1.1 Basic states
11.1.2 StartUp command 3Fh
Table 127. StartUp command 3Fh
Command
Value Action
Arguments
and data
Returned
data
StartUp
3Fh runs the reset and initialization phase
-
-
Remark: This command can only be activated by a Power-On or Hard reset.
The StartUp command runs the reset and initialization phases. It does not need or return,
any data. It cannot be activated by the microprocessor but is automatically started after
one of the following events:
• Power-On Reset (POR) caused by power-up on pin DVDD or on pin AVDD
• Negative edge on pin RSTPD
The reset phase comprises an asynchronous reset and configuration of certain register
bits. The initialization phase configures several registers with values stored in the
EEPROM.
When the StartUp command finishes, the Idle command is automatically executed.
Remark:
• The microprocessor must not write to the MFRC500 while it is still executing the
StartUp command. To avoid this, the microprocessor polls for the Idle command to
determine when the initialization phase has finished; see Section 9.7.4 on page 25.
• When the StartUp command is active, it is only possible to read from the Page 0
register.
• The StartUp command cannot be interrupted by the microprocessor.
11.1.3 Idle command 00h
Table 128. Idle command 00h
Command
Value
Action
Arguments Returned
and data
data
Idle
00h
no action; cancels current command
execution
-
-
The Idle command switches the MFRC500 to its inactive state where it waits for the next
command. It does not need or return, any data.
The device automatically enters the idle state when a command finishes. When this
happens, the MFRC500 sends an interrupt request by setting bit IdleIRq. When triggered
by the microprocessor, the Idle command can be used to stop execution of all other
commands (except the StartUp command) but this does not generate an interrupt request
(IdleIRq).
Remark: Stopping command execution with the Idle command does not clear the FIFO
buffer.
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11.2 Commands for card communication
The MFRC500 is a fully ISO/IEC 14443 A compliant reader IC. This enables the
command set to be more flexible and generalized when compared to dedicated MIFARE
reader ICs. Section 11.2.1 to Section 11.2.5 describe the command set for ISO/IEC 14443
A card communication and related communication protocols.
11.2.1 Transmit command 1Ah
Table 129. Transmit command 1Ah
Command Value
Action
Arguments Returned
and data
data
Transmit 1Ah
transmits data from FIFO buffer to card
data stream
-
The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It
does not return any data. The Transmit command can only be started by the
microprocessor.
11.2.1.1 Using the Transmit command
To transmit data, one of the following sequences can be used:
1. All data to be transmitted to the card is written to the FIFO buffer while the Idle
command is active. Then the command code for the Transmit command is written to
the Command register.
Remark: This is possible for transmission of a data stream up to 64 bytes.
2. The command code for the Transmit command is stored in the Command register.
Since there is not any data available in the FIFO buffer, the command is only enabled
but transmission is not activated. Data transmission starts when the first data byte is
written to the FIFO buffer. To generate a continuous data stream on the RF interface,
the microprocessor must write the subsequent data bytes into the FIFO buffer in time.
Remark: This allows transmission of any data stream length but it requires data to be
written to the FIFO buffer in time.
3. Part of the data transmitted to the card is written to the FIFO buffer while the Idle
command is active. Then the command code for the Transmit command is written to
the Command register. While the Transmit command is active, the microprocessor
can send further data to the FIFO buffer. This is then appended by the transmitter to
the transmitted data stream.
Remark: This allows transmission of any data stream length but it requires data to be
written to the FIFO buffer in time.
When the transmitter requests the next data byte to ensure the data stream on the RF
interface is continuous and the FIFO buffer is empty, the Transmit command automatically
exits. This causes the internal state machine to change its state from transmit to idle.
When the data transmission to the card is finished, the TxIRq flag is set by the MFRC500
to indicate to the microprocessor transmission is complete.
Remark: If the microprocessor overwrites the transmit code in the Command register
with another command, transmission stops immediately on the next clock cycle. This can
produce output signals that are not in accordance with ISO/IEC 14443 A.
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11.2.1.2 RF channel redundancy and framing
Each ISO/IEC 14443 A frame transmitted consists of a Start Of Frame (SOF) pattern,
followed by the data stream and is closed by an End Of Frame (EOF) pattern. These
different phases of the transmission sequence can be monitored using the PrimaryStatus
register ModemState[2:0] bits; see Section 11.2.4 on page 75.
Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is
calculated and appended to the data stream. The CRC is calculated according to the
settings in the ChannelRedundancy register. Parity generation is handled according to the
ChannelRedundancy register ParityEn and ParityOdd bits settings.
11.2.1.3 Transmission of bit oriented frames
The transmitter can be configured to send an incomplete last byte. To achieve this the
BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This
is shown in Figure 14.
TxLastBits = 0
TxLastBits = 7
TxLastBits = 1
SOF
SOF
SOF
0
0
0
7
7
7
P
P
P
0
0
0
7
P
EOF
6
EOF
EOF
001aak618
Fig 14. Transmitting bit oriented frames
Figure 14 shows the data stream when bit ParityEn is set in the ChannelRedundancy
register. All fully transmitted bytes are followed by a parity check bit but the incomplete
byte is not followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are
automatically cleared.
Remark: If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be
disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit.
11.2.1.4 Transmission of frames with more than 64 bytes
To generate frames of more than 64 bytes, the microprocessor must write data to the
FIFO buffer while the Transmit command is active. The state machine checks the FIFO
buffer status when it starts transmitting the last bit of the data stream; the check time is
shown in Figure 15 with arrows.
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TxLastBits[2:0]
FIFOLength[6:0]
FIFO empty
TxLastBits = 0
0x01
0x00
TxData
check FIFO empty
accept further data
7
0
7
0
7
001aak619
Fig 15. Timing for transmitting byte oriented frames
As long as the internal signal accept further data is logic 1, data can be written to the FIFO
buffer. The MFRC500 appends this data to the data stream transmitted using the RF
interface.
If the internal accept further data signal is logic 0, the transmission terminates. All data
written to the FIFO buffer after the accept further data signal was set to logic 0 is not
transmitted, however, it remains in the FIFO buffer.
Remark: If parity generation is enabled (ParityEn = logic 1), the parity bit is the last bit
transmitted. This delays the accept further data signal by a duration of one bit.
If the TxLastBits[2:0] bits are not zero, the last byte is not transmitted completely. Only the
number of bits set by TxLastBits[2:0], starting with the least significant bit are transmitted.
This means that the internal state machine has to check the FIFO buffer status at an
earlier point in time; see Figure 16.
NWR (FIFO data)
TxLastBits[2:0]
FIFOLength[6:0]
FIFO empty
TxLastBits = 4
01h
01h
00h
00h
TxData
check FIFO empty
accept further data
4
7
0
3
4
7
0
3
001aak620
Fig 16. Timing for transmitting bit oriented frames
Since in this example TxLastBits[2:0] = 4, transmission stops after bit 3 is transmitted and
the frame is completed with an EOF, if configured.
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Figure 16 also shows write access to the FIFOData register just before the FIFO buffer’s
status is checked. This leads to FIFO empty state being held LOW which keeps the
accept further data active. The new byte written to the FIFO buffer is transmitted using the
RF interface.
Accept further data is only changed by the check FIFO empty function. This function
verifies FIFO empty for one bit duration before the last expected bit transmission.
Table 130. Transmission of frames of more than 64 bytes
Frame definition
8-bit with parity
Verification at:
8
7
th bit
th bit
8-bit without parity
x-bit without parity
(x − 1)th bit
11.2.2 Receive command 16h
Table 131. Receive command 16h
Command
Value
Action
Arguments Returned
and data
data
Receive
16h
activates receiver circuitry
-
data stream
The Receive command activates the receiver circuitry. All data received from the RF
interface is written to the FIFO buffer. The Receive command can be started either using
the microprocessor or automatically during execution of the Transceive command.
Remark: This command can only be used for test purposes since there is no timing
relationship to the Transmit command.
11.2.2.1 Using the Receive command
After starting the Receive command, the internal state machine decrements to the RxWait
register value on every bit-clock. The analog receiver circuitry is prepared and activated
from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming
signal at the RF interface.
When the signal strength reaches a level higher than the RxThreshold register
MinLevel[3:0] bits value, it starts decoding. The decoder stops when the signal can longer
be detected on the receiver input pin RX. The decoder sets bit RxIRq indicating receive
termination.
The different phases of the receive sequence are monitored using the PrimaryStatus
register ModemState[2:0] bits; see Section 11.2.4 on page 75.
Remark: Since the counter values from 3 to 0 are needed to initialize the analog receiver
circuitry, the minimum value for RxWait[7:0] is 3.
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11.2.2.2 RF channel redundancy and framing
The decoder expects the SOF pattern at the beginning of each data stream. When the
SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data
bits. Every completed byte is forwarded to the FIFO buffer.
If an EOF pattern is detected or the signal strength falls below the RxThreshold register
MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command
is entered and an appropriate response for the microprocessor is generated (interrupt
request activated, status flags set).
When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected.
The CRC block can be one byte or two bytes depending on the ChannelRedundancy
register CRC8 bit setting.
Remark: If the CRC block received is correct, it is not sent to the FIFO buffer. This is
realized by shifting the incoming data bytes through an internal buffer of either one or two
bytes (depending on the defined CRC). The CRC block remains in this internal buffer.
Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the
CRC fails, all received bytes are sent to the FIFO buffer including the faulty CRC.
If ParityEn is set in the ChannelRedundancy register, a parity bit is expected after each
byte. If ParityOdd = logic 1, the expected parity is odd, otherwise even parity is expected.
11.2.2.3 Collision detection
If more than one card is within the RF field during the card selection phase, they both
respond simultaneously. The MFRC500 supports the algorithm defined in
ISO/IEC 14443 A to resolve card serial number data collisions by performing the
anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions.
Bit-collision detection is supported by the Manchester coding bit encoding scheme used in
the MFRC500. If in the first and second half-bit of a subcarrier, modulation is detected,
instead of forwarding a 1-bit or 0-bit, a bit-collision is indicated. The MFRC500 uses the
RxThreshold register CollLevel[3:0] bits setting to distinguish between a 1-bit or 0-bit and
a bit-collision. If the amplitude of the half-bit with smaller amplitude is larger than that
defined by the CollLevel[3:0] bits, the MFRC500 flags a bit-collision using the error flag
CollErr. If a bit-collision is detected in a parity bit, the ParityErr flag is set.
On a detected collision, the receiver continues receiving the incoming data stream. In the
case of a bit-collision, the decoder sends logic 1 at the collision position.
Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first
bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state
has been detected. This feature makes it easier for the control software to perform the
anti-collision procedure as defined in ISO/IEC 14443 A.
When the first bit collision in a frame is detected, the bit-collision position is stored in the
CollPos register.
Table 132 shows the collision positions.
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Table 132. Return values for bit-collision positions
Collision in bit
CollPos register value
(Decimal)
SOF
0
Least Significant Bit (LSB) of the Least Significant Byte (LSByte)
1
…
…
8
Most Significant Bit (MSB) of the LSByte
LSB of second byte
9
…
…
16
17
…
MSB of second byte
LSB of third byte
…
Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur
after bit-collisions in the data bits. If a collision is detected in the SOF, a frame error is
flagged and no data is sent to the FIFO buffer. In this case, the receiver continues to
monitor the incoming signal. It generates the correct notifications to the microprocessor
when the end of the faulty input stream is detected. This helps the microprocessor to
determine when it is next allowed to send data to the card.
11.2.2.4 Receiving bit oriented frames
The receiver can manage byte streams with incomplete bytes which result in bit-oriented
frames. To support this, the following values may be used:
• BitFraming register’s RxAlign[2:0] bits select a bit offset for the first incoming byte. For
example, if RxAlign[2:0] = 3, the first 5 bits received are forwarded to the FIFO buffer.
Further bits are packed into bytes and forwarded. After reception, RxAlign[2:0] is
automatically cleared. If RxAlign[2:0] = logic 0, all incoming bits are packed into one
byte.
• RxLastBits[2:0] returns the number of bits valid in the last received byte. For example,
if RxLastBits[2:0] evaluates to 5 bits at the end of the received command, the 5 least
significant bits are valid. If the last byte is complete, RxLastBits[2:0] evaluates to zero.
RxLastBits[2:0] is only valid if a frame error is not indicated by the FramingErr flag. If
RxAlign[2:0] is not zero and ParityEn is active, the first parity bit is ignored and not
checked.
The first byte containing a single bit from the card is not sent to the microprocessor but
suppressed when If RxAlign[2:0] is set to 7 (see Section 10.5.2.4 on page 50).
Remark: Collisions detected at CollPos register bit positions 6, 14, 22, 30 and 38 cannot
be resolved using RxAlign[2:0]. They must be resolved using the control software.
11.2.2.5 Communication errors
The events which can set error flags are shown in Table 133.
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Table 133. Communication error table
Cause
Flag bit
FramingErr
CRCErr
Received data did not start with the SOF pattern
CRC block is not equal to the expected value
Received data is shorter than the CRC block
CRCErr
The parity bit is not equal to the expected value (i.e. a bit-collision, not parity)
A bit-collision is detected
ParityErr
CollErr
11.2.3 Transceive command 1Eh
Table 134. Transceive command 1Eh
Command Value
Action
Arguments Returned
and data data
Transceive 1Eh
transmits data from FIFO buffer to the card data stream data stream
and then automatically activates the
receiver
The Transceive command first executes the Transmit command (see Section 11.2.1 on
page 69) and then starts the Receive command (see Section 11.2.2 on page 72). All data
transmitted is sent using the FIFO buffer and all data received is written to the FIFO buffer.
The Transceive command can only be started by the microprocessor.
Remark: To adjust the timing relationship between transmitting and receiving, use the
RxWait register. This register is used to define the time delay between the last bit
transmitted and activation of the receiver. In addition, the BitPhase register determines the
phase-shift between the transmitter and receiver clock.
11.2.4 Card communication states
The status of the transmitter and receiver state machine can be read from bits
ModemState[2:0] in the PrimaryStatus register.
The assignment of ModemState[2:0] to the internal action is shown in Table 135.
Table 135. Meaning of ModemState
ModemState State
[2:0]
Description
000
001
010
Idle
transmitter and/or receiver are not operating
transmitting the SOF pattern
TxSOF
TxData
transmitting data or redundancy check (CRC) bits from the FIFO
buffer
011
100
TxEOF
transmitting the EOF pattern
GoToRx1
GoToRx2
PrepareRx
AwaitingRx
Receiving
intermediate state passed, when receiver starts
intermediate state passed, when receiver finishes
waiting until the RxWait register time period expires
receiver activated; waiting for an input signal on pin RX
receiving data
101
110
111
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11.2.5 Card communication state diagram
COMMAND =
TRANSMIT,
RECEIVE OR
TRANSCEIVE
IDLE
(000)
FIFO not empty
and command =
command = Receive
Transmit or Transceive
TxSOF
GoToRx1
(001)
(100)
SOF transmitted
next bit clock
TxData
(010)
Prepare Rx
(101)
EOF transmitted and
command = Transceive
data transmitted
RxWaitC[7:0] = 0
TxEOF
(011)
Awaiting Rx
(110)
RxMultiple = 1
signal strength > MinLevel[3:0]
EOF transmitted and
command = Transmit
RECEIVING
(111)
frame received
end of receive frame
and
RxMultiple = 0
GoToRx2
(100)
SET
COMMAND REGISTER = IDLE
(000)
001aak621
Fig 17. Card communication state diagram
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11.3 EEPROM commands
11.3.1 WriteE2 command 01h
Table 136. WriteE2 command 01h
Command Value Action
FIFO
Arguments and
data
Returned
data
WriteE2
01h
get data from FIFO buffer and write it start address LSB
-
-
-
to the EEPROM
start address MSB
data byte stream
The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM
start byte address. Any further bytes are interpreted as data bytes and are programmed
into the EEPROM, starting from the given EEPROM start byte address. This command
does not return any data.
The WriteE2 command can only be started by the microprocessor. It will not stop
automatically but has to be stopped explicitly by the microprocessor by issuing the Idle
command.
11.3.1.1 Programming process
One byte up to 16 bytes can be programmed into the EEPROM during a single
programming cycle. The time needed is approximately 5.8 ms.
The state machine copies all the prepared data bytes to the FIFO buffer and then to the
EEPROM input buffer. The internal EEPROM input buffer is 16 bytes long which is equal
to the block size of the EEPROM. A programming cycle is started if the last position of the
EEPROM input buffer is written or if the last byte of the FIFO buffer has been read.
The E2Ready flag remains logic 0 when there are unprocessed bytes in the FIFO buffer or
the EEPROM programming cycle is still in progress. When all the data from the FIFO
buffer are programmed into the EEPROM, the E2Ready flag is set to logic 1. Together
with the rising edge of E2Ready the TxIRq interrupt request flag shows logic 1. This can
be used to generate an interrupt when programming of all data is finished.
Once E2Ready = logic 1, the WriteE2 command can be stopped by the microprocessor by
sending the Idle command.
Remark: During the EEPROM programming indicated by E2Ready = logic 0, the WriteE2
command cannot be stopped using any other command.
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11.3.1.2 Timing diagram
Figure 18 shows programming five bytes into the EEPROM.
t
prog,del
NWR
data
write addr addr
E2 LSB MSB
Idle
command
byte 0 byte 1
byte 2
byte 3
byte 4
WriteE2
command active
t
t
t
prog
prog
prog
EEPROM
programming
programming
byte 1, byte 2 and byte 3
programming byte 0
programming byte 4
E2Ready
TxIRq
001aak623
Fig 18. EEPROM programming timing diagram
Assuming that the MFRC500 finds and reads byte 0 before the microprocessor is able to
write byte 1 (tprog,del = 300 ns). This causes the MFRC500 to start the programming cycle
(tprog), which takes approximately 5.8 ms to complete. In the meantime, the
microprocessor stores byte 1 to byte 4 in the FIFO buffer.
If the EEPROM start byte address is 16Ch then byte 0 is stored at that address. The
MFRC500 copies the subsequent data bytes into the EEPROM input buffer. Whilst
copying byte 3, it detects that this data byte has to be programmed at the EEPROM byte
address 16Fh. As this is the end of the memory block, the MFRC500 automatically starts
a programming cycle.
Next, byte 4 is programmed at the EEPROM byte address 170h. As this is the last data
byte, the E2Ready and TxIRq flags are set indicating the end of the EEPROM
programming activity.
Although all data has been programmed into the EEPROM, the MFRC500 stays in the
WriteE2 command. Writing more data to the FIFO buffer would lead to another EEPROM
programming cycle continuing from EEPROM byte address 171h. The command is
stopped using the Idle command.
11.3.1.3 WriteE2 command error flags
Programming is restricted for EEPROM block 0 (EEPROM byte address 00h to 0Fh). If
you program these addresses, the AccessErr flag is set and a programming cycle is not
started.
Addresses above 1FFh are taken modulo 200h; see Section 9.2 on page 10 for the
EEPROM memory organization.
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11.3.2 ReadE2 command 03h
Table 137. ReadE2 command 03h
Command Value Action
Arguments
Returned data
ReadE2
03h
reads EEPROM data and
stores it in the FIFO buffer
start address LSB
start address MSB
number of data bytes
data bytes
The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the
EEPROM starting byte address. The next byte specifies the number of data bytes
returned.
When all three argument bytes are available in the FIFO buffer, the specified number of
data bytes is copied from the EEPROM into the FIFO buffer, starting from the given
EEPROM starting byte address.
The ReadE2 command can only be triggered by the microprocessor and it automatically
stops when all data has been copied.
11.3.2.1 ReadE2 command error flags
Reading is restricted to EEPROM blocks 8h to 1Fh (key memory area). Reading from
these addresses sets the flag AccessErr = logic 1.
Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 10 for the
EEPROM memory organization.
11.4 Diverse commands
11.4.1 LoadConfig command 07h
Table 138. LoadConfig command 07h
Command
Value Action
Arguments and
data
Returned data
LoadConfig
07h
reads data from EEPROM and start address LSB
-
-
initializes the registers
start address MSB
The LoadConfig command interprets the first two bytes found in the FIFO buffer as the
EEPROM starting byte address. When the two argument bytes are available in the FIFO
buffer, 32 bytes from the EEPROM are copied into the Control and other relevant
registers, starting at the EEPROM starting byte address. The LoadConfig command can
only be started by the microprocessor and it automatically stops when all relevant
registers have been copied.
11.4.1.1 Register assignment
The 32 bytes of EEPROM content are written to the MFRC500 registers 10h to register
2Fh; see Section 9.2 on page 10 for the EEPROM memory organization.
Remark: The procedure for the register assignment is the same as it is for the StartUp
initialization (see Section 9.7.3 on page 25). The difference is, the EEPROM starting byte
address for the startup initialization is fixed to 10h (block 1, byte 0). However, it can be
chosen with the LoadConfig command.
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11.4.1.2 Relevant LoadConfig command error flags
Valid EEPROM starting byte addresses are between 10h and 60h.
Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the
flag AccessErr = logic 1.
Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 10 for the
EEPROM memory organization.
11.4.2 CalcCRC command 12h
Table 139. CalcCRC command 12h
Command Value Action
Arguments and
data
Returned data
CalcCRC 12h activates the CRC coprocessor
data byte stream
-
The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the
CRC coprocessor. All data stored in the FIFO buffer before the command is started is
processed.
This command does not return any data to the FIFO buffer but the content of the CRC can
be read using the CRCResultLSB and CRCResultMSB registers.
The CalcCRC command can only be started by the microprocessor and it does not
automatically stop. It must be stopped by the microprocessor sending the Idle command.
If the FIFO buffer is empty, the CalcCRC command waits for further input before
proceeding.
11.4.2.1 CRC coprocessor settings
Table 140 shows the parameters that can be configured for the CRC coprocessor.
Table 140. CRC coprocessor parameters
Parameter
Value
Bit
Register
CRC register
length
8-bit or 16-bit CRC
CRC8
ChannelRedundancy
CRC algorithm
ISO/IEC 14443 A or ISO/IEC 3309 CRC3309
ChannelRedundancy
CRC preset value any
CRCPresetLSB CRCPresetLSB
CRCPresetMSB CRCPresetMSB
The CRC polynomial for the 8-bit CRC is fixed to x8 + x4 + x3 + x2 + 1.
The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1.
11.4.2.2 CRC coprocessor status flags
The CRCReady status flag indicates that the CRC coprocessor has finished processing
all the data bytes in the FIFO buffer. When the CRCReady flag is set to logic 1, an
interrupt is requested which sets the TxIRq flag. This supports interrupt driven use of the
CRC coprocessor.
When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB
and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and
CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC
validity for the processed data.
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11.5 Error handling during command execution
If an error is detected during command execution, the PrimaryStatus register Err flag is
set. The microprocessor can evaluate the status flags in the ErrorFlag register to get
information about the cause of the error.
Table 141. ErrorFlag register error flags overview
Error flag
KeyErr
Related commands
LoadKeyE2, LoadKey
WriteE2, ReadE2, LoadConfig
no specific commands
Receive, Transceive, CalcCRC
Receive, Transceive
AccessErr
FIFOOvlf
CRCErr
FramingErr
ParityErr
CollErr
Receive, Transceive
Receive, Transceive
11.6 MIFARE security commands
11.6.1 LoadKeyE2 command 0Bh
Table 142. LoadKeyE2 command 0Bh
Command
Value Action
Arguments and
data
Returned
data
LoadKeyE2
0Bh
reads a key from the EEPROM and start address LSB
-
-
puts it into the internal key buffer
start address MSB
The LoadKeyE2 command interprets the first two bytes found in the FIFO buffer as the
EEPROM starting byte address. The EEPROM bytes starting from the given starting byte
address are interpreted as the key when stored in the correct key format as described in
Section 9.2.3.1 “Key format” on page 13. When both argument bytes are available in the
FIFO buffer, the command executes.
The LoadKeyE2 command can only be started by the microprocessor and it automatically
stops after copying the key from the EEPROM to the key buffer.
11.6.1.1 Relevant LoadKeyE2 command error flags
If the key format is incorrect (see Section 9.2.3.1 “Key format” on page 13) an undefined
value is copied into the key buffer and the KeyErr flag is set.
11.6.2 LoadKey command 19h
Table 143. LoadKey command 19h
Command Value Action
Arguments and Returned
data
data
LoadKey
19h
reads a key from the FIFO buffer and puts it byte 0 (LSB)
-
-
-
-
-
into the key buffer
byte 1
…
byte 10
byte 11 (MSB)
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The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the
key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on
page 13. When the twelve argument bytes are available in the FIFO buffer they are
checked and, if valid, are copied into the key buffer.
The LoadKey command can only be started by the microprocessor and it automatically
stops after copying the key from the FIFO buffer to the key buffer.
11.6.2.1 Relevant LoadKey command error flags
All bytes requested are copied from the FIFO buffer to the key buffer. If the key format is
not correct (see Section 9.2.3.1 “Key format” on page 13) an undefined value is copied
into the key buffer and the KeyErr flag is set.
11.6.3 Authent1 command 0Ch
Table 144. Authent1 command 0Ch
Command Value Action
Arguments and data
Returned
data
Authent1
0Ch
performs the first part of the Crypto1 card Authent1 command
-
-
-
-
-
-
card authentication
card block address
card serial number LSB
card serial number byte1
card serial number byte2
card serial number MSB
The Authent1 command is a special Transceive command; it sends six argument bytes to
the card. The card’s response is not sent to the microprocessor, it is used instead to
authenticate the card to the MFRC500 and vice versa.
The Authent1 command can be triggered only by the microprocessor. The sequence of
states for this command are the same as those for the Transceive command; see
Section 11.2.3 on page 75.
11.6.4 Authent2 command 14h
Table 145. Authent2 command 14h
Command Value Action
Arguments
and data
Returned
data
Authent2
14h
performs the second part of the card
-
-
authentication using the Crypto1 algorithm
The Authent2 command is a special Transceive command. It does not need an argument
byte, however all the data needed to be sent to the card is assembled by the MFRC500.
The card response is not sent to the microprocessor but is used to authenticate the card
to the MFRC500 and vice versa.
The Authent2 command can only be started by the microprocessor. The sequence of
states for this command are the same as those for the Transceive command; see
Section 11.2.3 on page 75.
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11.6.4.1 Authent2 command effects
If the Authent2 command is successful, the authenticity of card and the MFRC500 are
proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1,
all further card communication is encrypted using the Crypto1 security algorithm. If the
Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0).
Remark: The Crypto1On flag can only be set by a successfully executed Authent2
command and not by the microprocessor. The microprocessor can clear bit Crypto1On to
continue with unencrypted (plain) card communication.
Remark: The Authent2 command must be executed immediately after a successful
Authent1 command; see Section 11.6.3 “Authent1 command 0Ch”. In addition, the keys
stored in the key buffer and those on the card must match.
12. Limiting values
Table 146. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Tamb
Parameter
Conditions
Min
−40
Max
Unit
°C
°C
V
ambient temperature
storage temperature
digital supply voltage
analog supply voltage
TVDD supply voltage
input voltage (absolute value)
+150
+150
+6
Tstg
−40
VDDD
VDDA
−0.5
−0.5
−0.5
−0.5
−0.5
+6
V
VDD(TVDD)
|Vi|
+6
V
on any digital pin to DVSS
on pin RX to AVSS
VDDD + 0.5
VDDA + 0.5
V
V
13. Characteristics
13.1 Operating condition range
Table 147. Operating condition range
Symbol
Tamb
Parameter
Conditions
Min
−25
4.5
4.5
3.0
-
Typ
+25
5.0
5.0
5.0
-
Max
+85
5.5
Unit
ambient temperature
digital supply voltage
analog supply voltage
TVDD supply voltage
-
°C
V
VDDD
DVSS = AVSS = TVSS = 0 V
DVSS = AVSS = TVSS = 0 V
DVSS = AVSS = TVSS = 0 V
VDDA
5.5
V
VDD(TVDD)
VESD
5.5
V
electrostatic discharge voltage Human Body Model (HBM); 1.5 kΩ,
1000
V
100 pF
Machine Model (MM); 0.75 μH,
-
-
100
V
200 pF
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13.2 Current consumption
Table 148. Current consumption
Symbol
Parameter
Conditions
Min Typ
Max
11
Unit
mA
mA
μA
IDDD
digital supply current
Idle command
-
-
-
-
-
-
-
-
-
-
-
8
Standby mode
3
5
Soft power-down mode
Hard power-down mode
Idle command; receiver on
Idle command; receiver off
Standby mode
800
1
1000
10
40
15
13
10
10
150
7
μA
IDDA
analog supply current
TVDD supply current
25
12
10
1
mA
mA
mA
μA
Soft power-down mode
Hard power-down mode
continuous wave
1
μA
IDD(TVDD)
-
mA
mA
pins TX1 and TX2 unconnected;
TX1RFEn and TX2RFEn = logic 1
5.5
pins TX1 and TX2 unconnected;
TX1RFEn and TX2RFEn = logic 0
-
65
130
μA
13.3 Pin characteristics
13.3.1 Input pin characteristics
Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in
Table 149.
Table 149. Standard input pin characteristics
Symbol
ILI
Parameter
Conditions
Min
Typ
Max
Unit
input leakage current
threshold voltage
−1.0
-
-
-
+1.0
μA
V
Vth
CMOS: VDDD < 3.6 V
TTL: 4.5 < VDDD
0.35VDDD
0.8
0.65VDDD
2.0
V
The digital input pins NCS, NWR, NRD, ALE, A2, and MFIN have Schmitt trigger
characteristics, and behave as defined in Table 150.
Table 150. Schmitt trigger input pin characteristics
Symbol
ILI
Parameter
Conditions
Min
−1.0
1.4
Typ
Max
+1.0
2.0
Unit
μA
V
input leakage current
threshold voltage
-
-
Vth
positive-going threshold;
TTL = 4.5 < VDDD
CMOS = VDDD < 3.6 V
negative-going threshold;
TTL = 4.5 < VDDD
0.65VDDD
0.8
-
-
0.75VDDD
1.3
V
V
CMOS = VDDD < 3.6 V
0.25VDDD
-
0.4VDDD
V
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Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by
a RC low-pass filter which causes a propagation delay on the reset signal.
Table 151. RSTPD input pin characteristics
Symbol Parameter
Conditions
Min
Typ Max
Unit
μA
V
ILI
input leakage current
−1.0
-
-
+1.0
Vth
threshold voltage
positive-going threshold;
CMOS = VDDD < 3.6 V
0.65VDDD
0.75VDDD
negative-going threshold;
CMOS = VDDD < 3.6 V
0.25VDDD
-
-
-
0.4VDDD
20
V
tPD
propagation delay
μs
The analog input pin RX has the input capacitance and input voltage range shown in
Table 152.
Table 152. RX input capacitance and input voltage range
Symbol
Ci
Parameter
Conditions
Min Typ Max Unit
input capacitance
-
-
-
15
pF
Vi(dyn)
dynamic input voltage VDDA = 5 V; Tamb = 25 °C
1.1
4.4
V
13.3.2 Digital output pin characteristics
Pins D0 to D7, MFOUT and IRQ have CMOS output characteristics and behave as
defined in Table 153.
Table 153. Digital output pin characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
VOH
VOL
IO
HIGH-level output
voltage
VDDD = 5 V; IOH = −1 mA
VDDD = 5 V; IOH = −10 mA
VDDD = 5 V; IOL = 1 mA
VDDD = 5 V; IOL = 10 mA
source or sink; VDDD = 5 V
2.4
4.9
4.2
25
-
-
V
V
2.4
LOW-level output
voltage
-
-
-
400 mV
250 400 mV
- 10 mA
output current
Remark: Pin IRQ can be configured as open collector which causes the VOH values to be
no longer applicable.
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13.3.3 Antenna driver output pin characteristics
The source conductance of the antenna driver pins TX1 and TX2 for driving the
HIGH-level can be configured using the CwConductance register’s GsCfgCW[5:0] bits,
while their source conductance for driving the LOW-level is constant.
The antenna driver default configuration output characteristics are specified in Table 154.
Table 154. Antenna driver output pin characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
VOH
VOL
IO
HIGH-level output
voltage
VDD(TVDD) = 5.0 V; IOL = 20 mA
VDD(TVDD) = 5.0 V; IOL = 100 mA
VDD(TVDD) = 5.0 V; IOL = 20 mA
VDD(TVDD) = 5.0 V; IOL = 100 mA
-
-
-
-
-
4.97
4.85
30
-
-
-
-
V
V
LOW-level output
voltage
mV
mV
150
-
output current
transmitter; continuous wave;
peak-to-peak
200 mA
13.4 AC electrical characteristics
13.4.1 Separate read/write strobe bus timing
Table 155. Timing specification for separate read/write strobe
Symbol
tLHLL
Parameter
Conditions
Min Typ Max Unit
ALE HIGH time
20
15
8
-
-
-
-
-
-
ns
ns
ns
tAVLL
address valid to ALE LOW time
tLLAX
address hold after ALE LOW
time
tLLRWL
tSLRWL
tRWHSH
tRLDV
ALE LOW to read/write LOW
time
ALE LOW to NRD or
NWR LOW
15
0
0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
chip select LOW to read/write NCS LOW to NRD or
LOW time NWR LOW
-
read/write HIGH to chip select NRD or NWR HIGH to
HIGH time
-
NCS HIGH
read LOW to data input valid
time
NRD LOW to data valid
65
20
35
-
tRHDZ
read HIGH to data input high
impedance time
NRD HIGH to data
high-impedance
-
tWLQV
tWHDX
write LOW to data output valid NWR LOW to data valid
time
-
data output hold after write
HIGH time
data hold time after
NWR HIGH
8
tRWLRWH
tAVRWL
read/write LOW time
NRD or NWR
65
30
-
-
-
-
ns
ns
address valid to read/write
LOW time
NRD or NWR LOW
(set-up time)
tWHAX
address hold after write HIGH NWR HIGH (hold time)
time
8
-
-
-
-
ns
ns
tRWHRWL
read/write HIGH time
150
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t
LHLL
ALE
t
t
RWHSH
SLRWL
NCS
t
LLRWL
t
t
t
RWHRWL
RWHRWL
RWLRWH
NWR
NRD
t
t
t
WHDX
WLQV
t
t
LLAX
AVLL
t
RLDV
RHDZ
D0 to D7
A0 to A2
A0 to A2
D0 to D7
Multiplexed address bus
t
t
WHAX
AVRWL
A0 to A2
Separated address bus
001aaj638
Fig 19. Separate read/write strobe timing diagram
Remark: The signal ALE is not relevant for separate address/data bus and the
multiplexed addresses on the data bus do not care. The multiplexed address and data bus
address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8.
13.4.2 Common read/write strobe bus timing
Table 156. Common read/write strobe timing specification
Symbol
tLHLL
Parameter
Conditions
Min Typ Max Unit
ALE HIGH time
20
15
8
-
-
-
-
-
-
-
-
ns
ns
ns
ns
tAVLL
address valid to ALE LOW time
address hold after ALE LOW time
tLLAX
tLLDSL
ALE LOW to data strobe LOW time NWR or NRD
LOW
15
tSLDSL
chip select LOW to data strobe
LOW time
NCS LOW to
NDS LOW
0
0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tDSHSH
tDSLDV
tDSHDZ
tDSLQV
tDSHQX
tDSHRWX
tDSLDSH
data strobe HIGH to chip select
HIGH time
-
data strobe LOW to data input valid
time
65
20
35
-
data strobe HIGH to data input high
impedance time
-
data strobe LOW to data output
valid time
NDS/NCS LOW
-
data output hold after data strobe
HIGH time
NDS HIGH (write
cycle hold time)
8
8
65
RW hold after data strobe HIGH
time
after NDS HIGH
-
data strobe LOW time
NDS/NCS
-
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Table 156. Common read/write strobe timing specification …continued
Symbol
Parameter
Conditions
Min Typ Max Unit
tAVDSL
address valid to data strobe LOW
time
30
-
-
ns
tRHAX
address hold after read HIGH time
data strobe HIGH time
8
-
-
-
-
ns
ns
tDSHDSL
period between
write sequences
150
tWLDSL
write LOW to data strobe LOW time R/NW valid to
NDS LOW
8
-
-
ns
t
LHLL
ALE
t
t
DSHSH
SLDSL
NCS/NDS
R/NW
t
t
DSHRWX
WLDSL
t
LLDSL
t
t
t
DSHDSL
DSHDSL
DSLDSH
NRD
D0 to D7
A0 to A2
t
t
DSHQX
DSLDV
t
t
LLAX
AVLL
t
t
DSLQV
DSHDZ
A0 to A2
D0 to D7
Multiplexed address bus
t
t
RHAX
AVDSL
A0 to A2
Separated address bus
001aaj639
Fig 20. Common read/write strobe timing diagram
13.4.3 EPP bus timing
Table 157. Common read/write strobe timing specification for EPP
Symbol
tASLASH
tAVASH
Parameter
Conditions
Min Typ Max Unit
address strobe LOW time
nAStrb
20
15
-
-
-
-
ns
ns
address valid to address strobe
HIGH time
multiplexed address
bus set-up time
tASHAV
tSLDSL
tDSHSH
tDSLDV
address valid after address strobe
HIGH time
multiplexed address
bus hold time
8
0
0
-
-
-
-
-
-
ns
ns
ns
ns
chip select LOW to data strobe
LOW time
NCS LOW to nDStrb
LOW
-
data strobe HIGH to chip select
HIGH time
nDStrb HIGH to
NCS HIGH
-
data strobe LOW to data input valid read cycle
time
65
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Table 157. Common read/write strobe timing specification for EPP …continued
Symbol Parameter Conditions Min Typ Max Unit
tDSHDZ
tDSLQV
tDSHQX
tDSHWX
data strobe HIGH to data input high read cycle
impedance time
-
-
-
-
-
20
35
-
ns
ns
ns
ns
data strobe LOW to data output
valid time
nDStrb LOW
NCS HIGH
nWrite
-
data output hold after data strobe
HIGH time
8
8
write hold after data strobe HIGH
time
-
tDSLDSH
tWLDSL
data strobe LOW time
nDStrb
65
8
-
-
-
-
ns
ns
write LOW to data strobe LOW time nWrite valid to
nDStrb LOW
tDSL-WAITH data strobe LOW to WAIT HIGH
time
nDStrb LOW to
nWrite HIGH
-
-
-
-
75
75
ns
ns
tDSH-WAITL data strobe HIGH to WAIT LOW
time
nDStrb HIGH to
nWrite LOW
t
DSHSH
t
SLDSL
NCS
t
t
DSHWX
WLDSL
nWrite
t
DSLDSH
nDStrb
nAStrb
t
t
t
DSLDV
DSHQX
DSHDZ
t
DSLQV
D0 to D7
A0 toA7
D0 to D7
nWait
t
t
DSH-WAITL
DSL-WAITH
001aaj640
Fig 21. Timing diagram for common read/write strobe; EPP
Remark: Figure 21 does not distinguish between the address write cycle and a data write
cycle. The timings for the address write and data write cycle are different. In EPP mode,
the address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8.
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13.4.4 Clock frequency
The clock input is pin OSCIN.
Table 158. Clock frequency
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
checked by the clock
filter
-
13.56
-
MHz
δclk
clock duty cycle
jitter time
40
-
50
-
60
10
%
tjit
of clock edges
ps
The clock applied to the MFRC500 acts as a time constant for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for
ensuring proper performance. To obtain highest performance, clock jitter must be as small
as possible. This is best achieved using the internal oscillator buffer and the
recommended circuitry; see Section 9.8 on page 26.
14. EEPROM characteristics
The EEPROM size is 32 × 16 × 8 = 4096 bit.
Table 159. EEPROM characteristics
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Hz
Nendu(W_ER) write or erase endurance erase/write cycles
100.000
-
-
-
-
-
tret
retention time
erase time
Tamb ≤ 55 °C
10
-
-
year
ms
ter
2.9
2.9
ta(W)
write access time
-
ms
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15. Application information
15.1 Typical application
15.1.1 Circuit diagram
Figure 22 shows a typical application where the antenna is directly matched to the
MFRC500:
DVDD
DVDD
Reset
AVDD
AVDD
TVDD
TVDD
RSTPD
control lines
data bus
C1
L0
L0
TX1
MICROPROCESSOR
BUS
C0
C0
C2a
C2b
C3
MICROPROCESSOR
TVSS
TX2
C1
R1
DEVICE
IRQ
IRQ
RX
R2
VMID
DVSS
OSCIN
OSCOUT AVSS
13.56 MHz
C4
100 nF
15 pF
15 pF
001aak625
Fig 22. Application example circuit diagram: directly matched antenna
15.1.2 Circuit description
The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry
(C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself.
Refer to the following application notes for more detailed information about designing and
tuning an antenna.
• MICORE reader IC family; Directly Matched Antenna Design Ref. 1
• MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2.
15.1.2.1 EMC low-pass filter
The MIFARE system operates at a frequency of 13.56 MHz. This frequency is generated
by a quartz oscillator to clock the MFRC500. It is also the basis for driving the antenna
using the 13.56 MHz energy carrier. This not only causes power emissions at 13.56 MHz,
it also emits power at higher harmonics. International EMC regulations define the
amplitude of the emitted power over a broad frequency range. To meet these regulations,
appropriate filtering of the output signal is required.
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A multilayer board is recommended to implement a low-pass filter as shown in Figure 22.
The low-pass filter consists of the components L0 and C0. The recommended values are
given in Application notes MICORE reader IC family; Directly Matched Antenna Design
Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2.
Remark: To achieve best performance, all components must be at least equal in quality to
those recommended.
Remark: The layout has a major influence on the overall performance of the filter.
15.1.2.2 Antenna matching
Due to the impedance transformation of the low-pass filter, the antenna coil has to be
matched to a given impedance. The matching elements C1 and C2 can be estimated and
have to be fine tuned depending on the design of the antenna coil.
The correct impedance matching is important to ensure optimum performance. The
overall quality factor has to be considered to guarantee a proper ISO/IEC 14443 A
communication scheme. Environmental influences have to considered and common EMC
design rules.
Refer to Application notes MICORE reader IC family; Directly Matched Antenna Design
Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2 for details.
Remark: Do not exceed the current limits (IDD(TVDD)), otherwise the chip might be
destroyed.
Remark: The overall 13.56 MHz RFID proximity antenna design in combination with the
MFRC500 IC does not require any specialist RF knowledge. However, all relevant
parameters have to be considered to guarantee optimum performance and international
EMC compliance.
15.1.2.3 Receiver circuit
The internal receiver of the MFRC500 makes use of both subcarrier load modulation
side-bands. No external filtering is required.
It is recommended to use the internally generated VMID potential as the input potential for
pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To
provide a stable DC reference voltage, a capacitor (C4) must be connected between
VMID and ground.
The AC voltage divider of R1 + C3 and R2 has to be designed taking in to account the AC
voltage limits on pin RX. Depending on the antenna coil design and the impedance,
matching the voltage at the antenna coil will differ. Therefore the recommended way to
design the receiver circuit is to use the given values for R1, R2, and C3; refer to
Application note; MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. The
voltage on pin RX can be altered by varying R1 within the given limits.
Remark: R2 is AC connected to ground using C4.
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15.1.2.4 Antenna coil
The precise calculation of the antenna coil’s inductance is not practicable but the
inductance can be estimated using Equation 10. We recommend designing an antenna
that is either circular or rectangular.
I1
1.8
⎛
⎞
------
L1[nH] = 2 ⋅ I1[cm] ⋅ ln 〈 〉 – K N1
(10)
⎝
⎠
D1
• l1 = length of one turn of the conductor loop
• D1 = diameter of the wire or width of the PCB conductor, respectively
• K = antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for square
antennas)
• N1 = number of turns
• ln = natural logarithm function
The values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend
on various parameters such as:
• antenna construction (type of PCB)
• thickness of conductor
• distance between the windings
• shielding layer
• metal or ferrite in the near environment
Therefore a measurement of these parameters under real life conditions or at least a
rough measurement and a tuning procedure is highly recommended to guarantee
adequate performance. Refer to Application notes MICORE reader IC family; Directly
Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity
Antennas Ref. 2 for details.
15.2 Test signals
The MFRC500 allows different kinds of signal measurements. These measurements can
be used to check the internally generated and received signals using the serial signal
switch as described in Section 9.11 on page 33.
In addition, the MFRC500 enables users to select between:
• internal analog signals for measurement on pin AUX
• internal digital signals for observation on pin MFOUT (based on register selections)
These measurements can be helpful during the design-in phase to optimize the receiver’s
behavior, or for test purposes.
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15.2.1 Measurements using the serial signal switch
Using the serial signal switch on pin MFOUT, data is observed that is sent to the card or
received from the card. Table 160 gives an overview of the different signals available.
Table 160. Signal routed to pin MFOUT
SignalToMFOUT
MFOUTSelect
Signal routed to pin MFOUT
LOW
0
0
0
0
0
0
0
0
1
0
1
2
3
4
5
6
7
X
HIGH
envelope
transmit NRZ
Manchester with subcarrier
Manchester
reserved
reserved
digital test signal
15.2.1.1 TX control
Figure 23 shows as an example of an ISO/IEC 14443 A communication.
The signal is measured on pin MFOUT using the serial signal switch to control the data
sent to the card. Setting the flag MFOUTSelect[2:0] = 3 sends the data to the card coded
as NRZ. Setting MFOUTSelect[2:0] = 2 shows the data as a Miller coded signal.
The RFOut signal is measured directly on the antenna and gives the RF signal pulse
shape. Refer to Application note Directly matched Antenna - Excel calculation (Ref. 3) for
detail information on the RF signal pulse.
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(1)
(2)
(3)
10 μs per division
001aak626
(1) MFOUTSelect[2:0] = 3; serial data stream; 2 V per division.
(2) MFOUTSelect[2:0] = 2; serial data stream; 2 V per division.
(3) RFOut; 1 V per division.
Fig 23. TX control signals
15.2.1.2 RX control
Figure 24 shows an example of ISO/IEC 14443 A communication which represents the
beginning of a card’s answer to a request signal.
The RF signal shows the RF voltage measured directly on the antenna so that the card’s
load modulation is visible. Setting MFOUTSelect[2:0] = 4 shows the Manchester decoded
signal with subcarrier. Setting MFOUTSelect[2:0] = 5 shows the Manchester decoded
signal.
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(1)
(2)
(3)
10 μs per division
001aak627
(1) RFOut; 1 V per division.
(2) MFOUTSelect[2:0] = 4; Manchester with subcarrier; 2 V per division.
(3) MFOUTSelect[2:0] = 5; Manchester; 2 V per division.
Fig 24. RX control signals
15.2.2 Analog test signals
The analog test signals can be routed to pin AUX by selecting them using the
TestAnaSelect register TestAnaOutSel[4:0] bits.
Table 161. Analog test signal selection
Value Signal Name Description
0
1
2
3
4
5
6
VMID
voltage at internal node VMID
Vbandgap
VRxFollI
VRxFollQ
VRxAmpI
VRxAmpQ
VCorrNI
internal reference voltage generated by the bandgap
output signal from the demodulator using the I-clock
output signal from the demodulator using the Q-clock
I-channel subcarrier signal amplified and filtered
Q-channel subcarrier signal amplified and filtered
output signal of N-channel correlator fed by the I-channel subcarrier
signal
7
8
9
A
VCorrNQ
VCorrDI
VCorrDQ
VEvalL
output signal of N-channel correlator fed by the Q-channel subcarrier
signal
output signal of D-channel correlator fed by the I-channel subcarrier
signal
output signal of D-channel correlator fed by the Q-channel subcarrier
signal
evaluation signal from the left half-bit
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Table 161. Analog test signal selection …continued
Value Signal Name Description
B
C
D
E
F
VEvalR
VTemp
evaluation signal from the right half-bit
temperature voltage derived from band gap
reserved for future use
reserved
reserved
reserved
reserved for future use
reserved for future use
15.2.3 Digital test signals
Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A
digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits.
The signals selected by the TestDigiSignalSel[6:0] bits are shown in Table 162.
Table 162. Digital test signal selection
TestDigiSignalSel Signal name Description
[6:0]
F4h
E4h
s_data
s_valid
data received from the card
when logic 1 is returned the s_data and s_coll signals are
valid
D4h
C4h
s_coll
when logic 1 is returned a collision has been detected in the
current bit
s_clock
internal serial clock:
during transmission, this is the encoder clock
during reception this is the receiver clock
B5h
A5h
rd_sync
wr_sync
int_clock
internal synchronized read signal which is derived from the
parallel microprocessor interface
internal synchronized write signal which is derived from the
parallel microprocessor interface
96h
00h
internal 13.56 MHz clock
no test signal output as defined by the MFOUTSelect register
MFOUTSelect[2:0] bits routed to pin MFOUT
If test signals are not used, the TestDigiSelect register address value must be 00h.
Remark: All other values for TestDigiSignalSel[6:0] are for production test purposes only.
15.2.4 Analog and digital test signal Examples
Figure 25 shows a MIFARE card’s answer to a request command using the Q-clock
receiving path. RX reference is given to show the Manchester modulated signal on pin
RX.
The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the
amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and
VCorrNQ were generated in the correlation circuitry. They are processed further in the
evaluation and digitizer circuitry.
Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit.
Finally, the digital test signal s_data shows the received data. This is then sent to the
internal digital circuit and s_valid which indicates the received data stream is valid.
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RX reference
VRxAmpQ
VCorrDQ
VCorrNQ
VEvalR
VEvalL
s_data
s_valid
50 μs per division
001aak628
Fig 25. ISO/IEC 14443 A receiving path Q-clock
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16. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w
M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.419
0.394
0.043 0.047
0.016 0.039
0.037
0.022
inches
0.1
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-08-17
03-02-19
SOT287-1
MO-119
Fig 26. Package outline SOT287-1
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17. Abbreviations
Table 163. Abbreviations and acronyms
Acronym
Description
ASK
CMOS
CRC
EOF
EPP
ETU
FIFO
HBM
LSB
Amplitude-Shift Keying
Complementary Metal-Oxide Semiconductor
Cyclic Redundancy Check
End Of Frame
Enhanced Parallel Port
Elementary Time Unit
First In, First Out
Human Body Model
Least Significant Bit
MM
Machine Model
MSB
NRZ
POR
PCD
PICC
SOF
SPI
Most Significant Bit
None Return to Zero
Power-On Reset
Proximity Coupling Device
Proximity Integrated Circuit Card
Start Of Frame
Serial Peripheral Interface
18. References
[1] Application note — MICORE reader IC family; Directly Matched Antenna Design.
[2] Application note — MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas.
[3] Application note — Directly matched Antenna - Excel calculation.
[4] ISO standard — ISO/IEC 14443 Identification cards - Contactless integrated
circuit(s) cards - Proximity cards, part 1-4.
[5] Application note — MIFARE Implementation of Higher Baud rates.
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19. Revision history
Table 164. Revision history
Document ID
MFRC500_33
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20100315
Product data sheet
-
048032
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors
• Legal texts have been adapted to the new company name where appropriate
• This version supersedes all previous revisions.
• The symbols for electrical characteristics and their parameters have been updated to meet the
NXP Semiconductors’ guidelines
• A number of inconsistencies in pin, register and bit names have been eliminated from the data sheet
• All drawings have been updated
• Section 5 “Quick reference data” on page 3: section added
• Section 15.1.2.4 “Antenna coil” on page 93: added missing formula and updated the last clause
• Section 16 “Package outline” on page 99: updated
• Section 18 “References” on page 100: added section and updated the references in the document
048032
048031
048030
048020
048010
20051201
20040501
20030301
20010131
20040430
Product data sheet
Product data sheet
Preliminary data sheet
Objective data sheet
Objective data sheet
-
-
-
-
-
048031
048030
048020
048010
-
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20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
20.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
20.3 Disclaimers
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
non-automotive qualified products in automotive equipment or applications.
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In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
MIFARE — is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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22. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Supported microprocessor and EPP interface
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
reset value: x000 0000b, x0h bit allocation . . . 44
Table 36. Command register bit descriptions . . . . . . . . . 44
Table 37. FIFOData register (address: 02h)
reset value: xxxx xxxxb, xxh bit allocation . . . 44
Table 38. FIFOData register bit descriptions . . . . . . . . . 44
Table 39. PrimaryStatus register (address: 03h)
reset value: 0000 0101b, 05h bit allocation . . 45
Table 40. PrimaryStatus register bit descriptions . . . . . . 45
Table 41. FIFOLength register (address: 04h)
reset value: 0000 0000b, 00h bit allocation . . 46
Table 42. FIFOLength bit descriptions . . . . . . . . . . . . . . 46
Table 43. SecondaryStatus register (address: 05h)
reset value: 01100 000b, 60h bit allocation . . . 46
Table 44. SecondaryStatus register bit descriptions . . . . 46
Table 45. InterruptEn register (address: 06h)
Table 5. Connection scheme for detecting the parallel
interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. EEPROM memory organization diagram . . . . .10
Table 7. Product information field byte allocation . . . . .11
Table 8. Product information field byte description . . . .11
Table 9. Product type identification definition . . . . . . . .11
Table 10. Byte assignment for register initialization at
start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 11. Shipment content of StartUp
configuration file . . . . . . . . . . . . . . . . . . . . . . .12
Table 12. Byte assignment for register initialization at
startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
reset value: 0000 0000b, 00h bit allocation . . 47
Table 46. InterruptEn register bit descriptions . . . . . . . . 47
Table 47. InterruptRq register (address: 07h)
reset value: 0000 0000b, 00h bit allocation . . 47
Table 48. InterruptRq register bit descriptions . . . . . . . . 47
Table 49. Control register (address: 09h)
reset value: 0000 0000b, 00h bit allocation . . 48
Table 50. Control register bit descriptions . . . . . . . . . . . 48
Table 51. ErrorFlag register (address: 0Ah)
reset value: 0100 0000b, 40h bit allocation . . 49
Table 52. ErrorFlag register bit descriptions . . . . . . . . . . 49
Table 53. CollPos register (address: 0Bh)
Table 13. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .15
Table 14. Associated FIFO buffer registers and flags . . .16
Table 15. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .17
Table 16. Interrupt control registers . . . . . . . . . . . . . . . .17
Table 17. Associated Interrupt request system registers
and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 18. Associated timer unit registers and flags . . . . .23
Table 19. Signal on pins during Hard power-down . . . . .23
Table 20. Pin TX1 configurations . . . . . . . . . . . . . . . . . .27
Table 21. Pin TX2 configurations . . . . . . . . . . . . . . . . . .27
Table 22. TX1 and TX2 source resistance of n-channel
driver transistor against
reset value: 0000 0000b, 00h bit allocation . . 50
Table 54. CollPos register bit descriptions . . . . . . . . . . . 50
Table 55. TimerValue register (address: 0Ch)
GsCfgCW or GsCfgMod . . . . . . . . . . . . . . . . .28
Table 23. Gain factors for the internal amplifier . . . . . . . .32
Table 24. DecoderSource[1:0] values . . . . . . . . . . . . . . .34
Table 25. ModulatorSource[1:0] values . . . . . . . . . . . . . .34
Table 26. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .34
Table 27. Register settings to enable use of the analog
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 28. Dedicated address bus: assembling the
register address . . . . . . . . . . . . . . . . . . . . . . . .37
Table 29. Multiplexed address bus: assembling the
register address . . . . . . . . . . . . . . . . . . . . . . . .37
Table 30. Behavior and designation of register bits . . . . .38
Table 31. MFRC500 register overview . . . . . . . . . . . . . .39
Table 32. MFRC500 register flags overview . . . . . . . . . .41
Table 33. Page register (address: 00h, 08h, 10h, 18h,
20h, 28h, 30h, 38h) reset value: 1000 0000b,
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .43
Table 34. Page register bit descriptions . . . . . . . . . . . . .43
Table 35. Command register (address: 01h)
reset value: xxxx xxxxb, xxh bit allocation . . . 50
Table 56. TimerValue register bit descriptions . . . . . . . . 50
Table 57. CRCResultLSB register (address: 0Dh)
reset value: xxxx xxxxb, xxh bit allocation . . . 50
Table 58. CRCResultLSB register bit descriptions . . . . . 50
Table 59. CRCResultMSB register (address: 0Eh)
reset value: xxxx xxxxb, xxh bit allocation . . . 51
Table 60. CRCResultMSB register bit descriptions . . . . 51
Table 61. BitFraming register (address: 0Fh)
reset value: 0000 0000b, 00h bit allocation . . 51
Table 62. BitFraming register bit descriptions . . . . . . . . . 51
Table 63. TxControl register (address: 11h)
reset value: 0101 1000b, 58h bit allocation . . 52
Table 64. TxControl register bit descriptions . . . . . . . . . 52
Table 65. CwConductance register (address: 12h)
reset value: 0011 1111b, 3Fh bit allocation . . . 53
Table 66. CwConductance register bit descriptions . . . . 53
Table 67. PreSet13 register (address: 13h)
continued >>
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reset value: 0011 1111b, 3Fh bit allocation . . .53
Table 68. PreSet13 register bit descriptions . . . . . . . . . .53
Table 69. PreSet14 register (address: 14h)
reset value: 0001 1001b, 19h bit allocation . . .53
Table 70. PreSet14 register bit descriptions . . . . . . . . . .53
Table 71. ModWidth register (address: 15h)
reset value: 0000 0000b, 00h bit allocation . . 60
Table 102. MFOUTSelect register bit descriptions . . . . . 60
Table 103. PreSet27 (address: 27h) reset value:
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 60
Table 104. PreSet27 register bit descriptions . . . . . . . . . 60
Table 105. FIFOLevel register (address: 29h)
reset value: 0001 0011b, 13h bit allocation . . .54
Table 72. ModWidth register bit descriptions . . . . . . . . . .54
Table 73. PreSet16 register (address: 16h)
reset value: 0000 1000b, 08h bit allocation . . 61
Table 106. FIFOLevel register bit descriptions . . . . . . . . 61
Table 107. TimerClock register (address: 2Ah)
reset value: 0000 0000b, 00h bit allocation . . .54
Table 74. PreSet16 register bit descriptions . . . . . . . . . .54
Table 75. PreSet17 register (address: 17h)
reset value: 0000 0000b, 00h bit allocation . . .54
Table 76. PreSet17 register bit descriptions . . . . . . . . . .54
Table 77. RxControl1 register (address: 19h)
reset value: 0000 0111b, 07h bit allocation . . . 61
Table 108. TimerClock register bit descriptions . . . . . . . . 61
Table 109. TimerControl register (address: 2Bh)
reset value: 0000 0110b, 06h bit allocation . . . 62
Table 110. TimerControl register bit descriptions . . . . . . . 62
Table 111. TimerReload register (address: 2Ch)
reset value: 0111 0011b, 73h bit allocation . . .55
Table 78. RxControl1 register bit descriptions . . . . . . . . .55
Table 79. DecoderControl register (address: 1Ah)
reset value: 0000 1000b, 08h bit allocation . . .55
Table 80. DecoderControl register bit descriptions . . . . .55
Table 81. BitPhase register (address: 1Bh) reset value:
1010 1101b, ADh bit allocation . . . . . . . . . . . .56
Table 82. BitPhase register bit descriptions . . . . . . . . . .56
Table 83. RxThreshold register (address: 1Ch)
reset value: 1111 1111b, FFh bit allocation . . .56
Table 84. RxThreshold register bit descriptions . . . . . . .56
Table 85. PreSet1D register (address: 1Dh)
reset value: 0000 0000b, 00h bit allocation . . .56
Table 86. PreSet1D register bit descriptions . . . . . . . . . .56
Table 87. RxControl2 register (address: 1Eh)
reset value: 0100 0001b, 41h bit allocation . . .57
Table 88. RxControl2 register bit descriptions . . . . . . . . .57
Table 89. ClockQControl register (address: 1Fh)
reset value: 000x xxxxb, xxh bit allocation . . . .57
Table 90. ClockQControl register bit descriptions . . . . . .57
Table 91. RxWait register (address: 21h) reset value:
0000 0101b, 06h bit allocation . . . . . . . . . . . . .58
Table 92. RxWait register bit descriptions . . . . . . . . . . . .58
Table 93. ChannelRedundancy register (address: 22h)
reset value: 0000 0011b, 03h bit allocation . . .58
Table 94. ChannelRedundancy bit descriptions . . . . . . .58
Table 95. CRCPresetLSB register (address: 23h)
reset value: 0101 0011b, 63h bit allocation . . .59
Table 96. CRCPresetLSB register bit descriptions . . . . .59
Table 97. CRCPresetMSB register (address: 24h)
reset value: 0101 0011b, 63h bit allocation . . .59
Table 98. CRCPresetMSB bit descriptions . . . . . . . . . . .59
Table 99. PreSet25 register (address: 25h)
reset value: 0000 1010b, 0Ah bit allocation . . 62
Table 112. TimerReload register bit descriptions . . . . . . . 62
Table 113. IRQPinConfig register (address: 2Dh)
reset value: 0000 0010b, 02h bit allocation . . 63
Table 114. IRQPinConfig register bit descriptions . . . . . . 63
Table 115. PreSet2E register (address: 2Eh)
reset value: xxxx xxxxb, xxh bit allocation . . . 63
Table 116. PreSet2F register (address: 2Fh)
reset value: xxxx xxxxb, xxh bit allocation . . . 63
Table 117. Reserved registers (address: 31h, 32h, 33h,
34h, 35h, 36h, 37h) reset value: xxxx xxxxb,
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
Table 118. Reserved register (address: 39h)
reset value: xxxx xxxxb, xxh bit allocation . . . 64
Table 119. TestAnaSelect register (address: 3Ah)
reset value: 0000 0000b, 00h bit allocation . . 64
Table 120. TestAnaSelect bit descriptions . . . . . . . . . . . . 64
Table 121. Reserved register (address: 3Bh)
reset value: xxxx xxxxb, xxh bit allocation . . . 65
Table 122. Reserved register (address: 3Ch)
reset value: xxxx xxxxb, xxh bit allocation . . . 65
Table 123. TestDigiSelect register (address: 3Dh)
reset value: xxxx xxxxb, xxh bit allocation . . . 65
Table 124. TestDigiSelect register bit descriptions . . . . . 65
Table 125. Reserved register (address: 3Eh, 3Fh)
reset value: xxxx xxxxb, xxh bit allocation . . . 66
Table 126. MFRC500 commands overview . . . . . . . . . . . 66
Table 127. StartUp command 3Fh . . . . . . . . . . . . . . . . . . 68
Table 128. Idle command 00h . . . . . . . . . . . . . . . . . . . . . 68
Table 129. Transmit command 1Ah . . . . . . . . . . . . . . . . . 69
Table 130. Transmission of frames of more than
64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 131. Receive command 16h . . . . . . . . . . . . . . . . . 72
Table 132. Return values for bit-collision positions . . . . . 74
Table 133. Communication error table . . . . . . . . . . . . . . . 75
Table 134. Transceive command 1Eh . . . . . . . . . . . . . . . 75
reset value: 0000 0000b, 00h bit allocation . . .59
Table 100. PreSet25 register bit descriptions . . . . . . . . . .60
Table 101. MFOUTSelect register (address: 26h)
continued >>
MFRC500_33
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Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
105 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
Table 135. Meaning of ModemState . . . . . . . . . . . . . . . . .75
Table 136. WriteE2 command 01h . . . . . . . . . . . . . . . . . .77
Table 137. ReadE2 command 03h . . . . . . . . . . . . . . . . . .79
Table 138. LoadConfig command 07h . . . . . . . . . . . . . . .79
Table 139. CalcCRC command 12h . . . . . . . . . . . . . . . . .80
Table 140. CRC coprocessor parameters . . . . . . . . . . . .80
Table 141. ErrorFlag register error flags overview . . . . . .81
Table 142. LoadKeyE2 command 0Bh . . . . . . . . . . . . . . .81
Table 143. LoadKey command 19h . . . . . . . . . . . . . . . . .81
Table 144. Authent1 command 0Ch . . . . . . . . . . . . . . . . .82
Table 145. Authent2 command 14h . . . . . . . . . . . . . . . . .82
Table 146. Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .83
Table 147. Operating condition range . . . . . . . . . . . . . . . .83
Table 148. Current consumption . . . . . . . . . . . . . . . . . . . .84
Table 149. Standard input pin characteristics . . . . . . . . . .84
Table 150. Schmitt trigger input pin characteristics . . . . .84
Table 151. RSTPD input pin characteristics . . . . . . . . . . .85
Table 152. RX input capacitance and input voltage
range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 153. Digital output pin characteristics . . . . . . . . . . .85
Table 154. Antenna driver output pin characteristics . . . .86
Table 155. Timing specification for separate read/write
strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 156. Common read/write strobe timing
specification . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 157. Common read/write strobe timing
specification for EPP . . . . . . . . . . . . . . . . . . . .88
Table 158. Clock frequency . . . . . . . . . . . . . . . . . . . . . . .90
Table 159. EEPROM characteristics . . . . . . . . . . . . . . . .90
Table 160. Signal routed to pin MFOUT . . . . . . . . . . . . . .94
Table 161. Analog test signal selection . . . . . . . . . . . . . .96
Table 162. Digital test signal selection . . . . . . . . . . . . . . .97
Table 163. Abbreviations and acronyms . . . . . . . . . . . . .100
Table 164. Revision history . . . . . . . . . . . . . . . . . . . . . . .101
MFRC500_33
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
106 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
23. Figures
Fig 1. MFRC500 block diagram. . . . . . . . . . . . . . . . . . . .4
Fig 2. MFRC500 pin configuration. . . . . . . . . . . . . . . . . .5
Fig 3. Connection to microprocessor: separate
read and write strobes . . . . . . . . . . . . . . . . . . . . . .8
Fig 4. Connection to microprocessor: common
read and write strobes . . . . . . . . . . . . . . . . . . . . . .9
Fig 5. Connection to microprocessor: EPP common
read/write strobes and handshake. . . . . . . . . . . . .9
Fig 6. Key storage format . . . . . . . . . . . . . . . . . . . . . . .14
Fig 7. Timer module block diagram . . . . . . . . . . . . . . . .20
Fig 8. The StartUp procedure. . . . . . . . . . . . . . . . . . . . .25
Fig 9. Quartz clock connection . . . . . . . . . . . . . . . . . . .26
Fig 10. Receiver circuit block diagram. . . . . . . . . . . . . . .30
Fig 11. Automatic Q-clock calibration . . . . . . . . . . . . . . .31
Fig 12. Serial signal switch block diagram. . . . . . . . . . . .33
Fig 13. Crypto1 key handling block diagram . . . . . . . . . .36
Fig 14. Transmitting bit oriented frames . . . . . . . . . . . . .70
Fig 15. Timing for transmitting byte oriented frames . . . .71
Fig 16. Timing for transmitting bit oriented frames. . . . . .71
Fig 17. Card communication state diagram . . . . . . . . . . .76
Fig 18. EEPROM programming timing diagram. . . . . . . .78
Fig 19. Separate read/write strobe timing diagram . . . . .87
Fig 20. Common read/write strobe timing diagram . . . . .88
Fig 21. Timing diagram for common read/write strobe;
EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Fig 22. Application example circuit diagram: directly
matched antenna. . . . . . . . . . . . . . . . . . . . . . . . .91
Fig 23. TX control signals . . . . . . . . . . . . . . . . . . . . . . . .95
Fig 24. RX control signals . . . . . . . . . . . . . . . . . . . . . . . .96
Fig 25. ISO/IEC 14443 A receiving path Q-clock. . . . . . .98
Fig 26. Package outline SOT287-1 . . . . . . . . . . . . . . . . .99
MFRC500_33
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
107 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
24. Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
9.4.4
9.5
9.5.1
Register overview interrupt request system. . 18
Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timer unit implementation . . . . . . . . . . . . . . . 19
Timer unit block diagram . . . . . . . . . . . . . . . . 19
Controlling the timer unit . . . . . . . . . . . . . . . . 20
Timer unit clock and period . . . . . . . . . . . . . . 21
Timer unit status. . . . . . . . . . . . . . . . . . . . . . . 21
Using the timer unit functions. . . . . . . . . . . . . 22
Time-out and WatchDog counters . . . . . . . . . 22
Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Programmable one shot timer and
2
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
4
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
5
6
7
8
8.1
periodic trigger . . . . . . . . . . . . . . . . . . . . . . . . 22
Timer unit registers . . . . . . . . . . . . . . . . . . . . 23
Power reduction modes . . . . . . . . . . . . . . . . . 23
Hard power-down. . . . . . . . . . . . . . . . . . . . . . 23
Soft power-down mode . . . . . . . . . . . . . . . . . 24
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 24
Automatic receiver power-down. . . . . . . . . . . 24
StartUp phase . . . . . . . . . . . . . . . . . . . . . . . . 25
Hard power-down phase . . . . . . . . . . . . . . . . 25
Reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Initialization phase . . . . . . . . . . . . . . . . . . . . . 25
Initializing the parallel interface type . . . . . . . 25
Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 26
Transmitter pins TX1 and TX2 . . . . . . . . . . . . 27
Configuring pins TX1 and TX2. . . . . . . . . . . . 27
Antenna operating distance versus power
consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Antenna driver output source resistance . . . . 28
Source resistance table . . . . . . . . . . . . . . . . . 28
Calculating the relative source resistance . . . 29
Calculating the effective source resistance . . 29
Pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Receiver circuit . . . . . . . . . . . . . . . . . . . . . . . 30
Receiver circuit block diagram. . . . . . . . . . . . 30
Receiver operation. . . . . . . . . . . . . . . . . . . . . 31
9
9.1
9.1.1
Functional description . . . . . . . . . . . . . . . . . . . 7
Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview of supported microprocessor
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic microprocessor interface
detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection to different microprocessor
types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Separate read and write strobe . . . . . . . . . . . . 8
Common read and write strobe . . . . . . . . . . . . 9
Common read and write strobe: EPP with
handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory organization of the EEPROM . . . . . . 10
Product information field (read only). . . . . . . . 11
Register initialization files (read/write) . . . . . . 11
StartUp register initialization file
9.5.3
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.8
9.1.2
9.1.3
9.1.3.1
9.1.3.2
9.1.3.3
9.2
9.9
9.9.1
9.9.2
9.2.1
9.2.2
9.2.2.1
(read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Factory default StartUp register
9.9.3
9.2.2.2
9.9.3.1
9.9.3.2
9.9.3.3
9.9.4
9.10
9.10.1
9.10.2
initialization file . . . . . . . . . . . . . . . . . . . . . . . . 12
Register initialization file (read/write) . . . . . . . 13
Crypto1 keys (write only) . . . . . . . . . . . . . . . . 13
Key format . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Storage of keys in the EEPROM . . . . . . . . . . 14
FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Accessing the FIFO buffer . . . . . . . . . . . . . . . 14
Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Controlling the FIFO buffer . . . . . . . . . . . . . . . 15
FIFO buffer status information . . . . . . . . . . . . 15
FIFO buffer registers and flags. . . . . . . . . . . . 16
Interrupt request system. . . . . . . . . . . . . . . . . 16
Interrupt sources overview . . . . . . . . . . . . . . . 16
Interrupt request handling. . . . . . . . . . . . . . . . 17
Controlling interrupts and getting their
9.2.2.3
9.2.3
9.2.3.1
9.2.3.2
9.3
9.3.1
9.3.1.1
9.3.2
9.3.3
9.3.4
9.4
9.10.2.1 Automatic Q-clock calibration . . . . . . . . . . . . 31
9.10.2.2 Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.10.2.3 Correlation circuitry . . . . . . . . . . . . . . . . . . . . 32
9.10.2.4 Evaluation and digitizer circuitry . . . . . . . . . . 32
9.11
9.11.1
9.11.2
Serial signal switch . . . . . . . . . . . . . . . . . . . . 33
Serial signal switch block diagram. . . . . . . . . 33
Serial signal switch registers . . . . . . . . . . . . . 34
9.4.1
9.4.2
9.4.2.1
9.11.2.1 Active antenna concept . . . . . . . . . . . . . . . . . 35
9.11.2.2 Driving both RF parts . . . . . . . . . . . . . . . . . . . 35
status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Accessing the interrupt registers . . . . . . . . . . 17
Configuration of pin IRQ. . . . . . . . . . . . . . . . . 18
9.12
9.12.1
9.12.2
MIFARE authentication and Crypto1 . . . . . . . 35
Crypto1 key handling . . . . . . . . . . . . . . . . . . . 36
Authentication procedure. . . . . . . . . . . . . . . . 36
9.4.2.2
9.4.3
continued >>
MFRC500_33
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© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
108 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
10
10.1
10.1.1
10.1.2
10.1.3
10.2
10.3
10.4
10.5
10.5.1
MFRC500 registers . . . . . . . . . . . . . . . . . . . . . 37
10.5.5.5 CRCPresetMSB register . . . . . . . . . . . . . . . . 59
10.5.5.6 PreSet25 register. . . . . . . . . . . . . . . . . . . . . . 59
10.5.5.7 MFOUTSelect register . . . . . . . . . . . . . . . . . . 60
10.5.5.8 PreSet27 register. . . . . . . . . . . . . . . . . . . . . . 60
Register addressing modes . . . . . . . . . . . . . . 37
Page registers . . . . . . . . . . . . . . . . . . . . . . . . 37
Dedicated address bus. . . . . . . . . . . . . . . . . . 37
Multiplexed address bus. . . . . . . . . . . . . . . . . 37
Register bit behavior. . . . . . . . . . . . . . . . . . . . 38
Register overview. . . . . . . . . . . . . . . . . . . . . . 39
MFRC500 register flags overview. . . . . . . . . . 41
Register descriptions . . . . . . . . . . . . . . . . . . . 43
Page 0: Command and status . . . . . . . . . . . . 43
10.5.6
Page 5: FIFO, timer and IRQ pin
configuration . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.5.6.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.5.6.2 FIFOLevel register . . . . . . . . . . . . . . . . . . . . . 61
10.5.6.3 TimerClock register . . . . . . . . . . . . . . . . . . . . 61
10.5.6.4 TimerControl register . . . . . . . . . . . . . . . . . . . 62
10.5.6.5 TimerReload register . . . . . . . . . . . . . . . . . . . 62
10.5.6.6 IRQPinConfig register . . . . . . . . . . . . . . . . . . 63
10.5.6.7 PreSet2E register. . . . . . . . . . . . . . . . . . . . . . 63
10.5.6.8 PreSet2F register. . . . . . . . . . . . . . . . . . . . . . 63
10.5.1.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.5.1.2 Command register . . . . . . . . . . . . . . . . . . . . . 44
10.5.1.3 FIFOData register. . . . . . . . . . . . . . . . . . . . . . 44
10.5.1.4 PrimaryStatus register . . . . . . . . . . . . . . . . . . 45
10.5.1.5 FIFOLength register . . . . . . . . . . . . . . . . . . . . 46
10.5.1.6 SecondaryStatus register . . . . . . . . . . . . . . . . 46
10.5.1.7 InterruptEn register. . . . . . . . . . . . . . . . . . . . . 47
10.5.1.8 InterruptRq register. . . . . . . . . . . . . . . . . . . . . 47
10.5.7
Page 6: reserved . . . . . . . . . . . . . . . . . . . . . . 63
10.5.7.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.5.7.2 Reserved registers 31h, 32h, 33h, 34h,
35h, 36h and 37h. . . . . . . . . . . . . . . . . . . . . . 63
10.5.8
Page 7: Test control . . . . . . . . . . . . . . . . . . . . 64
10.5.2
Page 1: Control and status . . . . . . . . . . . . . . . 48
10.5.8.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.5.8.2 Reserved register 39h . . . . . . . . . . . . . . . . . . 64
10.5.8.3 TestAnaSelect register. . . . . . . . . . . . . . . . . . 64
10.5.8.4 Reserved register 3Bh . . . . . . . . . . . . . . . . . . 65
10.5.8.5 Reserved register 3Ch. . . . . . . . . . . . . . . . . . 65
10.5.8.6 TestDigiSelect register . . . . . . . . . . . . . . . . . . 65
10.5.8.7 Reserved registers 3Eh, 3Fh . . . . . . . . . . . . . 66
10.5.2.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.5.2.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . 48
10.5.2.3 ErrorFlag register . . . . . . . . . . . . . . . . . . . . . . 49
10.5.2.4 CollPos register . . . . . . . . . . . . . . . . . . . . . . . 50
10.5.2.5 TimerValue register. . . . . . . . . . . . . . . . . . . . . 50
10.5.2.6 CRCResultLSB register . . . . . . . . . . . . . . . . . 50
10.5.2.7 CRCResultMSB register. . . . . . . . . . . . . . . . . 51
10.5.2.8 BitFraming register . . . . . . . . . . . . . . . . . . . . . 51
11
11.1
11.1.1
11.1.2
11.1.3
11.2
MFRC500 command set . . . . . . . . . . . . . . . . . 66
MFRC500 command overview. . . . . . . . . . . . 66
Basic states . . . . . . . . . . . . . . . . . . . . . . . . . . 68
StartUp command 3Fh. . . . . . . . . . . . . . . . . . 68
Idle command 00h . . . . . . . . . . . . . . . . . . . . . 68
Commands for card communication . . . . . . . 69
Transmit command 1Ah. . . . . . . . . . . . . . . . . 69
10.5.3
Page 2: Transmitter and control . . . . . . . . . . . 52
10.5.3.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.5.3.2 TxControl register. . . . . . . . . . . . . . . . . . . . . . 52
10.5.3.3 CwConductance register . . . . . . . . . . . . . . . . 53
10.5.3.4 PreSet13 register . . . . . . . . . . . . . . . . . . . . . . 53
10.5.3.5 PreSet14 register . . . . . . . . . . . . . . . . . . . . . . 53
10.5.3.6 ModWidth register. . . . . . . . . . . . . . . . . . . . . . 54
10.5.3.7 PreSet16 register . . . . . . . . . . . . . . . . . . . . . . 54
10.5.3.8 PreSet17 register . . . . . . . . . . . . . . . . . . . . . . 54
11.2.1
11.2.1.1 Using the Transmit command . . . . . . . . . . . . 69
11.2.1.2 RF channel redundancy and framing. . . . . . . 70
11.2.1.3 Transmission of bit oriented frames. . . . . . . . 70
11.2.1.4 Transmission of frames with more than
10.5.4
Page 3: Receiver and decoder control . . . . . . 55
10.5.4.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.5.4.2 RxControl1 register. . . . . . . . . . . . . . . . . . . . . 55
10.5.4.3 DecoderControl register . . . . . . . . . . . . . . . . . 55
10.5.4.4 BitPhase register . . . . . . . . . . . . . . . . . . . . . . 56
10.5.4.5 RxThreshold register . . . . . . . . . . . . . . . . . . . 56
10.5.4.6 PreSet1D Register . . . . . . . . . . . . . . . . . . . . . 56
10.5.4.7 RxControl2 register. . . . . . . . . . . . . . . . . . . . . 57
10.5.4.8 ClockQControl register . . . . . . . . . . . . . . . . . . 57
64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Receive command 16h . . . . . . . . . . . . . . . . . 72
11.2.2
11.2.2.1 Using the Receive command. . . . . . . . . . . . . 72
11.2.2.2 RF channel redundancy and framing. . . . . . . 73
11.2.2.3 Collision detection . . . . . . . . . . . . . . . . . . . . . 73
11.2.2.4 Receiving bit oriented frames . . . . . . . . . . . . 74
11.2.2.5 Communication errors . . . . . . . . . . . . . . . . . . 74
11.2.3
11.2.4
11.2.5
11.3
Transceive command 1Eh . . . . . . . . . . . . . . . 75
Card communication states . . . . . . . . . . . . . . 75
Card communication state diagram . . . . . . . . 76
EEPROM commands. . . . . . . . . . . . . . . . . . . 77
WriteE2 command 01h . . . . . . . . . . . . . . . . . 77
10.5.5
Page 4: RF Timing and channel
redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.5.5.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.5.5.2 RxWait register . . . . . . . . . . . . . . . . . . . . . . . . 58
10.5.5.3 ChannelRedundancy register . . . . . . . . . . . . . 58
10.5.5.4 CRCPresetLSB register . . . . . . . . . . . . . . . . . 59
11.3.1
11.3.1.1 Programming process . . . . . . . . . . . . . . . . . . 77
continued >>
MFRC500_33
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
109 of 110
MFRC500
NXP Semiconductors
Highly Integrated ISO/IEC 14443 A Reader IC
11.3.1.2 Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . 78
11.3.1.3 WriteE2 command error flags. . . . . . . . . . . . . 78
16
17
18
19
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 99
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100
References. . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . 101
11.3.2
ReadE2 command 03h. . . . . . . . . . . . . . . . . . 79
11.3.2.1 ReadE2 command error flags. . . . . . . . . . . . . 79
11.4
11.4.1
Diverse commands. . . . . . . . . . . . . . . . . . . . . 79
LoadConfig command 07h . . . . . . . . . . . . . . . 79
20
Legal information . . . . . . . . . . . . . . . . . . . . . 102
Data sheet status . . . . . . . . . . . . . . . . . . . . . 102
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 102
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 103
20.1
20.2
20.3
20.4
11.4.1.1 Register assignment. . . . . . . . . . . . . . . . . . . . 79
11.4.1.2 Relevant LoadConfig command error flags . . 80
11.4.2
CalcCRC command 12h. . . . . . . . . . . . . . . . . 80
11.4.2.1 CRC coprocessor settings . . . . . . . . . . . . . . . 80
11.4.2.2 CRC coprocessor status flags . . . . . . . . . . . . 80
21
22
23
24
Contact information . . . . . . . . . . . . . . . . . . . 103
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.5
11.6
11.6.1
Error handling during command execution. . . 81
MIFARE security commands . . . . . . . . . . . . . 81
LoadKeyE2 command 0Bh. . . . . . . . . . . . . . . 81
11.6.1.1 Relevant LoadKeyE2 command error flags . . 81
11.6.2 LoadKey command 19h . . . . . . . . . . . . . . . . . 81
11.6.2.1 Relevant LoadKey command error flags . . . . 82
11.6.3
11.6.4
Authent1 command 0Ch. . . . . . . . . . . . . . . . . 82
Authent2 command 14h . . . . . . . . . . . . . . . . . 82
11.6.4.1 Authent2 command effects. . . . . . . . . . . . . . . 83
12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 83
13
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.4
13.4.1
13.4.2
13.4.3
13.4.4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 83
Operating condition range . . . . . . . . . . . . . . . 83
Current consumption . . . . . . . . . . . . . . . . . . . 84
Pin characteristics . . . . . . . . . . . . . . . . . . . . . 84
Input pin characteristics . . . . . . . . . . . . . . . . . 84
Digital output pin characteristics. . . . . . . . . . . 85
Antenna driver output pin characteristics . . . . 86
AC electrical characteristics . . . . . . . . . . . . . . 86
Separate read/write strobe bus timing . . . . . . 86
Common read/write strobe bus timing . . . . . . 87
EPP bus timing. . . . . . . . . . . . . . . . . . . . . . . . 88
Clock frequency . . . . . . . . . . . . . . . . . . . . . . . 90
14
EEPROM characteristics. . . . . . . . . . . . . . . . . 90
15
15.1
15.1.1
15.1.2
Application information. . . . . . . . . . . . . . . . . . 91
Typical application . . . . . . . . . . . . . . . . . . . . . 91
Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . 91
Circuit description. . . . . . . . . . . . . . . . . . . . . . 91
15.1.2.1 EMC low-pass filter. . . . . . . . . . . . . . . . . . . . . 91
15.1.2.2 Antenna matching. . . . . . . . . . . . . . . . . . . . . . 92
15.1.2.3 Receiver circuit. . . . . . . . . . . . . . . . . . . . . . . . 92
15.1.2.4 Antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15.2
15.2.1
Test signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Measurements using the serial signal
switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
15.2.1.1 TX control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
15.2.1.2 RX control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
15.2.2
15.2.3
15.2.4
Analog test signals . . . . . . . . . . . . . . . . . . . . . 96
Digital test signals. . . . . . . . . . . . . . . . . . . . . . 97
Analog and digital test signal Examples . . . . . 97
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 March 2010
048033
相关型号:
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