MIMX8DX5CVLFZAC_技术文档

Document Number: IMX8QXPIEC

Rev. 0, 05/2020

NXP Semiconductors

Data Sheet: Technical Data

MIMX8QXnAVLFZAC

MIMX8DXnAVLFZAC

i.MX 8QuadXPlus and

8DualXPlus Industrial

Applications Processors

Package Information

21 x 21 mm package case outline

Ordering Information

See Section 1.1Table 2 on page 5

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 System Controller Firmware (SCFW) Requirements5

1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 14

3.2 Recommended Connections for Unused Interfaces14

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Power supplies requirements and restrictions. . . . 25

4.3 PLL electrical characteristics. . . . . . . . . . . . . . . . . 28

4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 31

4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 34

4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41

4.7 Output Buffer Impedance Parameters. . . . . . . . . . 43

4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48

4.9 General-Purpose Media Interface (GPMI) Timing. 52

4.10 External Peripheral Interface Parameters . . . . . . . 61

4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 109

Boot mode configuration. . . . . . . . . . . . . . . . . . . . . . . . 112

5.1 Boot mode configuration pins . . . . . . . . . . . . . . . 112

5.2 Boot devices interfaces allocation. . . . . . . . . . . . 112

Package information and contact assignments . . . . . . 114

6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch . . . . . . . . . 114

Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

1 Introduction

This data sheet contains specifications for the

i.MX 8QuadXPlus and 8DualXPlus processors, which,

along with the i.MX 8DualX processor , comprise the

i.MX 8X Family (for i.MX 8DualX specifications, see

i.MX 8DualX Industrial Processors [IMX8DXIEC]).

The i.MX 8X processors consist of three to five Arm

2

3

4

®

cores (two to four Arm Cortex -A35 and one

®

Cortex -M4F). All devices include separate GPU and

VPU subsystems as well as a failover-ready display

controller. Advanced multicore audio processing is

supported by the Arm cores and a high performance

®

Tensilica HiFi 4 DSP for pre- and post-audio

processing as well as voice recognition. The i.MX 8X

Family supports up to three displays with multiple

display output options, including parallel, MIPI-DSI,

and LVDS. Memory interfaces for this device include:

5

6

7

•

LPDDR4 (no error correcting code [ECC])

DDR3L (optional ECC)

2× Quad SPI or 1× Octal SPI (FlexSPI)

eMMC 5.1, RAW NAND, and SD 3.0

NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of

its products.

Introduction

A wide range of peripheral I/Os such as CAN, parallel or MIPI CSI camera input, Gigabit Ethernet,

USB 2.0 OTG, USB 3.0 (8QuadXPlus/8DualXPlus only), ADC, and PCIe 3.0 provide impressive

flexibility.

The i.MX 8QuadXPlus/8DualXPlus processors offer numerous advanced features as shown in this table.

Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features

Function

Feature

Multicore architecture provides 2×–

4× Cortex-A35 and 1× Cortex-M4F

cores

AArch64 for 64-bit support and new architectural features

AArch32 for full backward compatibility with ARMv7

Cortex-A35 cores support ARM virtualization extensions.

Cortex-M4F cores for real-time applications

Graphics Processing Unit (GPU)

4× Vec4 shaders with 16 execution units optimized for higher performance

Supports OpenGL 3.0, 2.1,; OpenGL ES 3.1, 3.0, 2.0, and 1.1; OpenCL 1.2 Full Profile

and 1.1; OpenVG 1.1; and Vulkan

High-performance 2D Blit Engine

H.265 decode (4Kp30)

Video Processing Unit (VPU)

H.264 decode (4Kp30)

WMV9/VC-1 imple decode

MPEG 1 and 2 decode

AVS decode

MPEG4.2 ASP, H.263, Sorenson Spark decode

Divx 3.11 including GMC decode

ON2/Google VP6/VP8 decode

RealVideo 8/9/10 decode

JPEG and MJPEG decode

H.264 encode (1080p30)

Tensilica HiFi 4 DSP for pre- and

post-processing

640 MHz

Fixed-point and vector-floating-point support

32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and

64 KB of TCM)

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Introduction

Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued)

Function Feature

Memory

32-bit LPDDR4 @1200 MHz

40-bit DDR3L @933 MHz (ECC option)

1× Quad SPI which can be used to connect to an FPGA

2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash

2× SD 3.0 card interfaces (note: if eMMC is used, then 1× SD 3.0 available in IOMUX)

1× eMMC5.1/SD3.0 (note: use of eMMC will restrict SD card availability to 1× SD 3.0

due to IOMUX restrictions)

RAW NAND (62-bit ECC support via BCH-62 module)

Supports up to 3 independent displays (2× MIPI or LVDS + 1× Parallel)

Up to 18-layer composition

Display Controller

Complementary 2D blitting engines and online warping functionality

Integrated Failover Path (SafeAssure) to ensure display content stays valid even in

event of a software failure

Display I/O

Two MIPI-DSI/LVDS Combo PHYs (each up to 1080p60):

Each single PHY can either be a 4-lane MIPI-DSI or a 4-lane channel LVDS interface

for a total of 2 display interfaces. In combination, the two PHYs can be configured to

be a single dual-channel LVDS interface.

1× 24-bit parallel LCD up to 720p60 (DDR bandwidth might limit the available

resolution).

Camera I/O and video

Security

1× MIPI-CSI with 4-lanes

1× 8-bit/10-bit parallel CSI

Advanced High Assurance Boot (AHAB) secure & encrypted boot

Random Number Generator with a high-quality entropy source generator and

Hash_DRBG (based on hash functions)

RSA up to 4096, Elliptic Curve up to 1023

AES-128/192/256, DES, 3DES, MD5, SHA-1, SHA-224/256/384/512

Dedicated Security Controller for Flashless SHE and HSM support, Trustzone, RTIC

Built-in ECDSA/DSA protocol support

See the security reference manual for this chip for a full list of security features.

10× tamper pins (up to 5 active or 10 passive)

Voltage and Temperature tamper detection

64 kB Secure RAM (can be erased via tamper detection)

• 2× I²C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core)

System Control

•

The tightly coupled M4 I²C ports cannot be used for general-purpose use

• System Control Unit (SCU):

•

Power control, clocks, reset

Boot ROMs

PMIC interface

Resource Domain Controller

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Introduction

Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued)

Function

Feature

I/O

1× PCIe 3.0 (1-lane) with L1 substate support

1× USBOTG 3.0 with PHY—USB 3.0 can be used as USB 2.0

1× USBOTG 2.0 (with PHY)

2× 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB)

3× CAN/CAN-FD

Note: Legacy CAN mode supports both Mailbox (MB) and RX FIFO (with DMA

support) operation. Flexible Data (FD) mode supports MB operation only. There is no

enhanced RX FIFO or DMA support in FD mode.

6× UARTs:

• 4× UARTs (3× with hardware flow control)

• 1× UART tightly coupled with Cortex-M4F cores

• 1× SCU UART (Note: SCU UART is dedicated to the SCU and not available for

general use)

10× I²C (note that there are two types of I²C: High-speed I²C ports with DMA support,

and low-speed I²C ports with no DMA support, which are used in conjunction with a

specific PHY interface—for example, for touchscreen):

• 4× I2C: High Speed, DMA support

• 4× I2C: Low Speed, no DMA support

• 1× I2C: PMIC control (dedicated)

• 1× I2C: Cortex M4F (dedicated)

Note: I2C ports associated with a PHY (e.g. MIPI DSI) can be used generally but

require the PHY to be powered on even if the PHY interface itself is not used.

4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only)

1× Enhanced Serial Audio Interface (ESAI)

2× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly

connected to this module)

1× SPDIF (Tx and Rx)

1× 6-channel ADC converter

3.3 V/1.8 V GPIO

4× PWM channels

1× 6×8 KPP (Key Pad Port)

1× MQS (Medium Quality Sound)

4× SPI

Packaging

Case FCPBGA 21 x 21 mm, 0.8 mm pitch

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NXP Semiconductors

Introduction

1.1

Ordering Information

For ordering information, contact an NXP representative at nxp.com.

Table 2. i.MX 8QuadXPlus Orderable part numbers

Cortex-A35

Cortex-M4F

Speed

Part Number

Options

Speed

Grade

Package

Grade

MIMX8QX6CVLFZAC With GPU, VPU, 24-bit Parallel

LCD, DSP

1.2 GHz

264 MHz

21 mm X 21 mm, 0.8

mm pitch, FCPBGA

(lidded)

MIMX8QX5CVLFZAC With GPU, VPU, 24-bit Parallel

LCD

1.2 GHz

21 mm X 21 mm, 0.8

mm pitch, FCPBGA

(lidded)

Table 3. i.MX 8DualXPlus Orderable part numbers

Cortex-A35 Cortex-M4F

Part Number

Options

Speed

Grade

Speed

Grade

Package

MIMX8DX6CVLFZAC

With GPU, VPU, 24-bit

Parallel LCD, DSP

1.2 GHz

264 MHz

21 mm X 21 mm, 0.8 mm

pitch, FCPBGA (lidded)

MIMX8DX5CVLFZAC

With GPU, VPU, 24-bit

Parallel LCD

21 mm X 21 mm, 0.8 mm

pitch, FCPBGA (lidded)

1.2

System Controller Firmware (SCFW) Requirements

The i.MX 8 and 8X families require a minimum SCFW release version for correct operation and to prevent

potential reliability issues.

The SCFW is released as part of a Board Support Package (e.g. Linux, Android) which may vary in version

number for a specific BSP.

For example, NXP Yocto Linux release 4.14.98_2.3.0 contains SCFW version 1.3.0, NXP Yocto Linux

release 4.14.98_2.0.0 GA contains SCFW version 1.2.10, whereas NXP Yocto Linux release

4.14.78_1.0.0GA contains SCFW version 1.1.10.

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Architectural Overview

The released SCFW version associated within each BSP is the minimum version required to correctly

support the wider BSP functionality.

Customers should always check that they are using the specific SCFW binary delivered within their chosen

BSP release. Customers should not mix newer BSP versions with older revisions of the SCFW.

1.3

Related resources

Table 4. Related resources

Description

Type

Reference manual

The i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual

(IMX8DQXPRM) contains a comprehensive description of the structure and function

(operation) of the SoC.

Data sheet

Chip Errata

This data sheet includes electrical characteristics and signal connections.

The chip mask set errata provides additional and/or corrective information for a particular

device mask set.

Package drawing

Hardware guide

Package dimensions are provided in Section 6, “Package information and contact

assignments".”

Contact an NXP representative for access.

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 8QuadXPlus/8DualXPlus

processor system.

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Architectural Overview

2.1

Block Diagram

The following figure shows the functional modules in the processor system.

1x GPIO

1x I2C

1x UART

Memories

CPU Platform

User CM4 Complex

M4 Platform

M4 CPU

10/100/1000M

Ethernet + AVB

2x FlexSPI

4x ARM Cortex-A35

1x USB 3.0

PHY

NAND CTRL (BCH62)

NEON

32KB I$

VFP

32KB D$

nvic

fpu

mpu

MCM

16KB system$

1x USBOTG 2.0

OTG & PHY

External Memory Interface

MMCAU

32-bit LPDDR4

(no ECC)

@1200 MHz

512KB L2 w/ ECC

16KB code$

PG

DDR

Controller

256KB TCM w/ ECC

BN

TrustZone

40-bit DDR3L

(w/ ECC)

@933 MHz

1x eMMC

5.1 / SD 3.0

WDOG

RGPIO

LPIT

INTs

PWM

2x SD 3.0

(UHS-I)

High Speed I/O

Subsystem

LPUART

LPI2C

2x MU

SSI Bus

Internal Memory

OCRAM (256KB)

x1 PCIe 3.0

(1 lane)

PCIe

RAW /

ONFI 3.2

NAND Flash

Connectivity Subsystem

USB3

2x uSDHC

2x ENET

NAND

Imaging

24-bit LCD

Parallel

Display

Parallel

2x Quad SPI /

1x Octal SPI

NOR Flash

2x USB2

I/F

MJPEG MJPEG

DEC

ENC

ISI

(in ADMA SS)

Low Speed I/O (LSIO) Subsystem

LPI2C

1x I2C

4x4 Keypad

32-bit GPIO

I2C w/ DMA

IEE

4x PWM

5x GPT

KPP

2x FlexSPI

14x MU

8x GPIO

2x LVDS /

MIPI-DSI

MIPI / LVDS

Combo

Display Controller

DPU

Audio DMA

(ADMA)

Subsystem

ASRC

ACM

MQS

AUDMIX

4x SAI

PWM

ESAI

ASRC

SPDIF

SAI

3x FlexCAN

4x LPI2C

1x ADC (4ch)

LPI2C

1x I2C

UART (5 Mb/s)

CAN / CAN-FD

ADC (6 channels)

4x LPSPI

4x LPUART

2x FTM

MIPI-CSI2

(4-lanes)

1x MIPI

CSI2

GPT

4x eDMA

IRQs

LCDIF

Graphics Processing Unit

GPU

LPI2C

SPDIF TX / RX

ESAI TX / RX

MQS L/R

1x I2C

System Control Unit

8/10-bit

Parallel Camera

Parallel

I/F

JTAGC

IOMUX

SCU CM4 Complex

Debug

Clock, Reset

Power Mgmt

DAP, CTI, etc

M4 Platform

M4 CPU

Video Processing Unit

VPU

LPI2C

1x I2C

2x SAI TX / RX

2x SAI RX

Boot ROM

HAB

RDC

nvic

MMCAU

16KB code$

fpu

mpu

Tempmon

PMIC I/F

MCM

DSP Core

(part of ADMA SS)

Security

16KB system$

SECO

SNVS

256KB TCM w/ ECC

24M and 32k

XTALOSC

Sources

HIFI4 DSP

OTP

ADM

Security

Controller

(M0+)

32KB I$

48KB D$

WDOG

RGPIO

LPIT

INTs

PWM

512KB SRAM

64KB TCM

LPUART

LPI2C

2x MU

CAAM

Secure

JTAG

4 shaders

Mult-format Decode

H.265 Dec (4k30)

H.264 Dec (1080p60)

H.264 Enc (1080p30)

RNG

Vulkan, OGLES 3.1,

OCL 1.2, VG 1.1

2D Blit Engine

1x GPIO

1x I2C

1x UART

Ciphers

(ECC, RSA)

Tamper

Detection

Dedicated

64k Secure

RAM

Secure RTC

Figure 1. i.MX 8QuadXPlus/8DualXPlus System Block Diagram

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Modules List

3 Modules List

The i.MX 8QuadXPlus/8DualXPlus processors contain a variety of digital and analog modules. This table

describes the processor modules in alphabetical order.

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list

Block

Mnemonic

Block Name

Brief Description

ADC

Analog-to-Digital

Converter

The analog-to-digital converter (ADC) is a successive approximation ADC

designed for operation within a SoC.

APBH-DMA

NAND Flash and BCH The AHB-to-APBH bridge provides the chip with a peripheral attachment bus

ECC DMA Controller

running on the AHB's HCLK, which includes the AHB-to-APB PIO bridge for a

memory-mapped I/O to the APB devices, as well as a central DMA facility for

devices on this bus and a vectored interrupt controller for the Arm core.

A35

Arm (CPU1)

2–4x Cortex-A35 CPUs with a 32KB L1 instruction cache and a 32 KB data cache.

The CPUs share a 512 KB L2 cache.

ASRC

Asynchronous Sample The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of

Rate Converter

a signal associated to an input clock into a signal associated to a different output

clock. The ASRC supports concurrent sample rate conversion of up to 10 channels

of about -120dB THD+N. The sample rate conversion of each channel is

associated to a pair of incoming and outgoing sampling rates. The ASRC supports

up to three sampling rate pairs.

BCH-62

CAAM

Binary-BCH ECC

Processor

The BCH62 module provides up to 62-bit ECC for NAND Flash controller (GPMI2)

Cryptographic

Accelerator and

Assurance Module

CAAM is a cryptographic accelerator and assurance module. CAAM implements

several encryption and hashing functions, a run-time integrity checker, and a

Pseudo Random Number Generator (PRNG).

CAAM also implements a Secure Memory mechanism. In this device the security

memory provided is 64 KB.

CTI

Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is

used by features of the Coresight infrastructure.

CTM

DAP

Cross Trigger Matrix

Debug Access Port

Cross Trigger Matrix IP is used to route triggering events between CTIs.

The DAP provides real-time access for the debugger without halting the core to:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan chains.

DC

Display Controller

DRAM Controller

Dual display controller

DDR Controller

• Memory types: LPDDR4 (no ECC) and DDR3L (ECC option)

• One channel of 32-bit memory:

• LPDDR4 up to 1.2 GHz

• DDR3L up to 933MHz

DPR

Display/Prefetch/

Resolve

The DPR prefetches data from memory and converts the data to raster format for

display output. Raster source buffers can also be prefetched unconverted. The

resolve process supports graphics and video formatted tile frame buffers and

converts them to raster format. Embedded display memory is used as temporary

storage for data which is sourced by the display controller to drive the display.

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Modules List

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued)

Block

Mnemonic

Block Name

Brief Description

eDMA

Enhanced Direct

Memory Access

• 4× eDMA with a total of 96 channels (note: all channels are not assigned; see

the product reference manual for more information):

• 2× instances with 32 channels each

• 2× instances with 16 channels each

• Programmable source, destination addresses, transfer size, plus support for

enhanced addressing modes

• Internal data buffer, used as temporary storage to support 64-byte burst

transfers, one outstanding transaction per DMA controller.

• Transfer control descriptor organized to support two-deep, nested transfer

operations

• Channel service request via one of three methods:

• Explicit software initiation

• Initiation via a channel-to-channel linking mechanism for continuous

transfers

• Peripheral-paced hardware requests (one per channel)

• Support for fixed-priority and round-robin channel arbitration

• Channel completion reported via interrupt requests

• Support for scatter/gather DMA processing

• Support for complex data structures via transfer descriptors

• Support to cancel transfers via software or hardware

• Each eDMA instance can be uniquely assigned to a different resource domain,

security (TZ) state, and virtual machine

• In scatter-gather mode, each transfer descriptor’s buffers can be assigned to

different SMMU translation

ENET

ESAI

Ethernet Controller

2× 1 Gbps Ethernet + AVB (Audio Video Bridging, IEEE 802.1Qav)

Enhanced Serial Audio The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for

Interface

serial communication with a variety of serial devices, including industry-standard

codecs, SPDIF transceivers, and other processors. The ESAI consists of

independent transmitter and receiver sections, each section with its own clock

generator. All serial transfers are synchronized to a clock. Additional

synchronization signals are used to delineate the word frames. The normal mode

of operation is used to transfer data at a periodic rate, one word per period. The

network mode is also intended for periodic transfers; however, it supports up to 32

words (time slots) per period. This mode can be used to build time division

multiplexed (TDM) networks. In contrast, the on-demand mode is intended for

non-periodic transfers of data and to transfer data serially at high speed when the

data becomes available.

The ESAI has 12 pins for data and clocking connection to external devices.

FTM

FlexTimer

Provides input signal capture and PWM support

FlexCAN

Flexible Controller Area Communication controller implementing the CAN with Flexible Data rate (CAN FD)

Network protocol and the CAN protocol according to the CAN 2.0B protocol specification.

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Modules List

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued)

Block

Mnemonic

Block Name

Flexible Serial

Brief Description

FlexSpi (Quad

SPI/Octal SPI)

• Flexible sequence engine to support various flash vendor devices, including

HyperBus™ devices:

Peripheral Interface

• Support for FPGA interface

• Single, dual, quad, and octal mode of operation.

• DDR/DTR mode wherein the data is generated on every edge of the serial flash

clock.

• Support for flash data strobe signal for data sampling in DDR and SDR mode.

• Two identical serial flash devices can be connected and accessed in parallel for

data read operations, forming one (virtual) flash memory with doubled readout

bandwidth.

GIC

Generic Interrupt

Controller

The GIC-500 handles all interrupts from the various subsystems and is ready for

virtualization.

GPIO

GPMI

General Purpose I/O

Modules

Used for general purpose input/output to external devices. Each GPIO module

supports 32 bits of I/O.

^{General Purpose Media The GPMI module supports up to 8}× NAND devices. 62-bit ECC (BCH) for NAND

Interface

Flash controller (GPMI). The GPMI supports separate DMA channels per NAND

device.

GPT

General Purpose Timer Each GPT is a 32-bit “free-running” or “set and forget” mode timer with

programmable prescaler and compare and capture register. A timer counter value

can be captured using an external event and can be configured to trigger a capture

event on either the leading or trailing edges of an input pulse. When the timer is

configured to operate in “set and forget” mode, it is capable of providing precise

interrupts at regular intervals with minimal processor intervention. The counter has

output compare logic to provide the status and interrupt at comparison. This timer

can be configured to run either on an external clock or on an internal clock.

GPU

Graphics Processing

Audio Processor

1× GC7000Lite with 4x Vec4 shader cores (16 execution units)

HiFi 4 DSP

A highly optimized audio processor geared for efficient execution of audio and

voice codecs and pre- and post-processing modules to offload the Arm core.

I²C

I²C Interface

I²C provides serial interface for external devices.

IEE

• Supports direct encryption and decryption of FlexSPI memory type

• Provides decryption services (lower performance) for DRAM traffic

• Supports I/O direct encrypted storage and retrieval

• Support for a number of cryptographic standards:

• 128/256-bit AES Encryption (AES-CTR, AES-XTS mode options)

• Multiple keys supported:

• Loaded via secure key channel from security block

• Key selection is per access and based on source of transaction

IOMUXC

JPEG/dec

JPEG/enc

IOMUX Control

This module enables flexible I/O multiplexing. Each I/O pad has default and several

alternate functions. The alternate functions are software configurable.

MJPEG engine for

decode

Provides up to 4-stream decoding in parallel.

MJPEG engine for

encode

Provides up to 4-stream encoding in parallel.

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Modules List

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued)

Block Name Brief Description

Key Pad Port

Block

Mnemonic

KPP

The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 4 x 4 keypad

matrix interface or as general purpose input/output (I/O).

LPIT-1

LPIT-2

Low-Power Periodic

Interrupt Timer

Each LPIT is a 32-bit “set and forget” timer that starts counting after the LPIT is

enabled by software. It is capable of providing precise interrupts at regular intervals

with minimal processor intervention. It has a 12-bit prescaler for division of input

clock frequency to get the required time setting for the interrupts to occur, and

counter value can be programmed on the fly.

LPSPI 0–3

M4F

Configurable SPI

Arm (CPU3)

Full-duplex enhanced Synchronous Serial Interface. It is configurable to support

Master/Slave modes, four chip selects to support multiple peripherals.

• Cortex-M4F core

• AHB LMEM (Local Memory Controller) including controllers for TCM and cache

memories

• 256 KB tightly coupled memory(TCM) (128 KB TCMU, 128 KB TCML)

• 16 KB Code Bus Cache

• 16 KB System Bus Cache

• ECC for TCM memories and parity for code and system caches

• Integrated Nested Vector Interrupt Controller (NVIC)

• Wakeup Interrupt Controller (WIC)

• FPU (Floating Point Unit)

• Core MPU (Memory Protection Unit)

• Support for exclusive access on the system bus

• MMCAU (Crypto Acceleration Unit)

• MCM (Miscellaneous Control Module)

MIPI CSI-2

MIPI CSI-2 Interface

The MIPI CSI-2 IP provides MIPI CSI-2 standard camera interface ports. The MIPI

CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes

MIPI-DSI/LVDS MIPI DSI/LVDS Combo The MIPI DSI IP provides DSI standard display serial interface with 4 data lines.

interface

The DSI interface supports 80 Mbps to 1.05 Gbps speed per data lane.

The LVDS is a high-performance 2-channel serializer that interfaces with LVDS

displays.

Note: This is a combination PHY interface. It includes the digital logic and physical

interface pins for both MIPI DSI (4 data lanes) and LVDS (4 differential pairs plus

one for clock). The interface can be pinned out either as MIPI DSI or as LVDS.

However, it does not allow for simultaneous use on one interface

MQS

Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality

PWM-like audio via two standard digital GPIO pins.

OCOTP_CTRL

OTP Controller

The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading,

programming, and/or overriding identification and control information stored in

on-chip fuse elements. The module supports electrically-programmable poly fuses

(eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible

signals that can be used for software control of hardware elements, not requiring

non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for

interfacing with on-chip fuse elements. Among the uses for the fuses are unique

chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,

boot characteristics, and various control signals requiring permanent nonvolatility.

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Modules List

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued)

Block

Mnemonic

Block Name

Brief Description

OCRAM

On-Chip Memory

Controller

The On-Chip Memory controller (OCRAM) module is designed as an interface

between the system’s AXI bus and the internal (on-chip) SRAM memory module.

The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit

AXI bus.

Parallel CSI

Parallel CSI interface

The Parallel Port Capture Subsystem interfaces to Parallel CSI sensors and

includes the following features:

• Configurable interface logic to support the most commonly used parallel CMOS

sensors

• Configurable master clock output to drive external sensor (24 MHz nominal)

• Up to 150 MHz input clock from sensor

• Input data formats supported:

• 8-bit/10-bit BT.656

• 8-bit/24-bit data port for RGB, YCbCr, and YUV data input

• 8-bit/12-bit/10-bit/16-bit data port for Bayer data input

Note: For some formats a single pixel is sent per clock, for others two or three are

sent per clock.

PCIe

PRG

PCI Express 3.0

The PCIe IP provides PCI Express Gen 3.0 functionality .

Prefetch/Resolve

Gasket

The PRG is a gasket which translates system memory accesses to local display

RTRAM accesses for display refresh. It works with the DPR to complete the

prefetch and resolving operations needed to drive the display.

PWM

Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images and it can also generate tones.

It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms.

RAM

64 KB Secure

RAM

Secure/non-secure

RAM

Secure/non-secure Internal RAM, interfaced through the CAAM.

RAM

Internal RAM

Internal RAM, which is accessed through OCRAM memory controllers.

256 KB

RNG

Random Number

Generator

The purpose of the RNG is to generate cryptographically strong random data. It

uses a true random number generator (TRNG) and a pseudo-random number

generator (PRNG) to achieve true randomness and cryptographic strength. The

RNG generates random numbers for secret keys, per message secrets, random

challenges, and other similar quantities used in cryptographic algorithms.

SAI

I2S/SSI/AC97 Interface The SAI module provides a synchronous audio interface that supports full duplex

serial interfaces with frame synchronization, such as I2S, AC97, TDM, and

codec/DSP interfaces.

SECO

SJC

Security Controller

Core and associated memory and hardware responsible for key management.

Secure JTAG Controller The SJC provides the JTAG interface, which is compatible with JTAG TAP

standards, to internal logic. This device uses JTAG port for production, testing, and

system debugging. Additionally, the SJC provides BSR (Boundary Scan Register)

standard support, which is compatible with IEEE1149.1 and IEEE1149.6 standards.

The JTAG port must be accessible during platform initial laboratory bring-up, for

manufacturing tests and troubleshooting, as well as for software debugging by

authorized entities. The SJC incorporates three security modes for protecting

against unauthorized accesses. Modes are selected through eFUSE configuration.

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Modules List

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued)

Block

Mnemonic

Block Name

Brief Description

SNVS

SPDIF

Secure Non-Volatile

Storage

Secure Non-Volatile Storage, including Secure Real Time Clock, Security State

Machine, Master Key Control, and Violation/Tamper Detection and reporting.

Sony Philips Digital

Interconnect Format

The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that

allows the processor to receive and transmit digital audio. The SPDIF transceiver

allows the handling of both SPDIF channel status (CS) and User (U) data and

includes a frequency measurement block that allows the precise measurement of

an incoming sampling frequency.

TEMPMON

UART

Temperature Monitor

UART Interface

The temperature monitor/sensor IP module for detecting high temperature

conditions. The temperature read out does not reflect case or ambient temperature.

It reflects the temperature in proximity of the sensor location on the die.

Temperature distribution may not be uniformly distributed; therefore, the read-out

value may not be the reflection of the temperature value for the entire die.

• High-speed TIA/EIA-232-F compatible, up to 5.0 Mbps

• Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)

• 9-bit or Multidrop mode (RS-485) support (automatic slave address detection)

• 7, 8, 9, or 10-bit data characters (7-bits only with parity)

• 1 or 2 stop bits

• Programmable parity (even, odd, and no parity)

• Hardware flow control support for request to send (RTS_B) and clear to send

(CTS_B) signals

USB3/USB2

The USB3/USB2 OTG module has been specified to perform USB 3.0 dual role and

USB 2.0 On-The-Go (OTG) compatible with the USB 3.0, and USB 2.0

specification with OTG supplementary specifications. This controller supports

^{twoindependent USB cores (1}× USB3.0 dual-role, 1× USB2.0 OTG) and includes

the PHY and I/O interfaces to support this operation. The full pinout of the USB 3.0

controller includes the signaling for both USB 3.0 and USB 2.0. This does not

mean there is a separate USB 2.0 controller that can be used independently and

simultaneously with USB 3.0. This device has an additional separate,

independent USB 2.0 OTG controller which can be used simultaneously with this

USB 3.0. Specific features requested for this updated module:

• Super Speed (5 Gbps), High Speed (480 Mbps), full speed (12 Mbps) and low

speed (1.5 Mbps)

• Fully compatible with the USB 3.0 specification (backward compatible with USB

2.0)

• Fully compatible with the USB On-The-Go supplement to the USB 2.0

specification

• Hardware support for OTG signaling

• Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

implemented in hardware, which can also be controlled by software

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Modules List

Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued)

Block

Mnemonic

Block Name

Brief Description

USBOH

The USBOH module has been specified which performs USB 2.0 On-The-Go

(OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG

^{supplement specification. This controller supports one independent USB core (1}×

USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation.

Key features:

• One USB2.0 OTG controller

• High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps)

• Fully compatible with the USB 2.0 specification

• Fully compatible with the USB On-The-Go supplement to the USB 2.0

specification

• Hardware support for OTG signaling

Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

implemented in hardware, which can also be controlled by software

uSDHC

SD/eMMC and SDXC

The uSDHC is a host controller used to communicate with external low cost data

Enhanced Multi-Media storage and communication media. It supports the previous versions of the

Card / Secure Digital

Host Controller

MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the

uSDHC supports:

• SD Host Controller Standard Specification v3.0 with the exception that all the

registers do not match the standards address mapping.

• SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50)

• SDIO specification v3.0

• eMMC System Specification v5.1

VPU

Video Processing Unit See the device reference manual for the complete list of the VPU’s

decoding/encoding capabilities.

WDOG

Watchdog

The Watchdog Timer supports two comparison points during each counting period.

Each of the comparison points is configurable to evoke an interrupt to theArm core,

and a second point evokes an external event on the WDOG line.

XTAL OSC24M

XTAL OSC32K

The 24 MHz clock source is an external crystal that acts as one of two main clock

sources to the chip. The OSC24M is used as the source clock for subsystem PLLs.

OSC24M can be turned off by the System Control Unit (SCU) during sleep mode.

The 32 KHz clock source is an external crystal that is one of two main clock sources

to the chip. The OSC32K is intended to be always on and is distributed by the SCU

to modules in the chip.

3.1

Special Signal Considerations

The package contact assignments can be found in Section 6, “Package information and contact

assignments".” Signal descriptions are defined in the device reference manual.

3.2

Recommended Connections for Unused Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused

Input/Output Terminations,” in the hardware development guide for this device.

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Electrical characteristics

4 Electrical characteristics

This section provides the device and module-level electrical characteristics for these processors.

4.1

Chip-level conditions

This section provides the device-level electrical characteristics for the SoC. See the following table for a

quick reference to the individual tables and sections.

Table 6. Chip-level conditions

For these characteristics, …

Absolute maximum ratings

Topic appears …

on page 15

on page 17

on page 18

on page 20

on page 21

on page 24

FCPBGA package thermal resistance data

Operating ranges

External Input Clock Frequency

Maximum supply currents

USB 2.0 PHY typical current consumption in Power-Down

Mode

USB 3.0 PHY typical current consumption in Power-Down

Mode

on page 24

Typical current consumption in Power-Down mode for USB

2.0 PHY embedded in USB 3.0 PHY

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 7 may affect reliability or cause

permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions beyond those

indicated in the “Operating ranges” or other parameter tables is not implied.

Exposure to absolute-maximum-rated conditions for extended periods will

affect device reliability.

Table 7. Absolute maximum ratings

Parameter Description

Symbol

Min

Max

Units

Core Supplies Input Voltage

VDD_A35

VDD_GPU

VDD_MAIN

-0.3

1.2

V

DDR PHY supplies

VDD_DDR_VDDQ

-0.3

1.75

V

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Electrical characteristics

Table 7. Absolute maximum ratings (continued)

Parameter Description

Symbol

Min

Max

Units

1.0V IO supplies

VDD_MIPI_1P0

-0.3

1.2

V

VDD_USB_OTG_1P0

IO Supply for GPIO Type

1.8V IO Single supply

VDD_ADC_1P8

-0.5

2.1

V

VDD_ADC_DIG_1P8

VDD_ANA0_1P8 (IO, analog,OSC SCU)

VDD_ANA1_1P8 (IO, analog,OSC SCU)

VDD_DDR_PLL_1P8 (memory PLLs)

VDD_MIPI_1P8 (PHY, GPIO)

VDD_MIPI_CSI_DIG_1P8 (PHY, GPIO)

VDD_PCIE_1P8 (PHY)

VDD_USB_1P8 (PHY, GPIO)

IO Supply for GPIO Type

1.8 / 2.5 / 3.3V IO Tri-voltage Supply

VDD_ENET0_VSELECT_1P8_2P5_3P3 -0.3

VDD_ENET0_1P8_2P5_3P3

3.8

V

VDD_ESAI_SPDIF_1P8_2P5_3P3

IO Supply for GPIO Type

1.8 / 3.3V IO Dual Voltage Supply

VDD_CAN_UART_1P8_3P3

VDD_CSI_1P8_3P3

-0.3

VDD_EMMC0_1P8_3P3

VDD_EMMC0_VSELECT_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_PCIE_DIG_1P8_3P3

VDD_QSPI0A_1P8_3P3

VDD_QSPI0B_1P8_3P3

VDD_SPI_MCLK_UART_1P8_3P3

VDD_SPI_SAI_1P8_3P3

VDD_TMPR_CSI_1P8_3P3

VDD_USB_3P3 (PHY & GPIO)

VDD_USDHC1_1P8_3P3

VDD_USDHC1_VSELECT_1P8_3P3

VDD_SNVS_4P2

SNVS Coin Cell

-0.3

4.3

3.63

5.5

V

USB VBUS (OTG2)

USB VBUS (OTG1)

USB_OTG2_VBUS

USB_OTG1_VBUS

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Electrical characteristics

Table 7. Absolute maximum ratings (continued)

Parameter Description

Symbol

Min

Max

Units

I/O Voltage for USB Drivers

USB_OTG1_DP/USB_OTG1_DN

USB_OTG2_DP/USB_OTG2_DN

ADC_INx

-0.3

3.63

V

I/O Voltage for ADC

-0.1

-0.3

2.1

V

Vin/Vout input/output voltage range (GPIO Vin/Vout

Type Pins)

OVDD+0.3¹

Vin/Vout input/output voltage range (DDR Vin/Vout

pins)

-0.3

OVDD+0.4^1,2

V

ESD immunity (HBM).

ESD immunity (CDM).

Storage temperature range

Vesd_HBMX

—

1000

250

V

Vesd_CDM

Tstorage

V

-55

150

°C

1

OVDD is the I/O supply voltage.

2

The absolute maximum voltage includes an allowance for 400 mV of overshoot on the I/O pins. Per JEDEC standard the allowed

signal overshoot must be derated if NVCC_DRAM exceeds 1.575 V.

4.1.2

Thermal resistance

4.1.2.1

FCPBGA package thermal resistance

This table provides the FCPBGA package thermal resistance data.

Table 8. FCPBGA package thermal resistance data

Value,

21x21 mm

package

Rating

Board Type¹

Symbol

Unit

Junction to Ambient Thermal

Resistance²

JESD51-9, 2s2p

JESD51-9, 1s

R_θJA

Ψ_JT

15.2

0.1

°C/W

Junction to Package Top Thermal

Resistance²

Junction to Case Thermal Resistance³

R_θJC

0.7

1

Thermal test board meets JEDEC specification for this package (JESD51-9).

2

Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this

report is solely for a thermal performance comparison of one package to another in a standardized specified

environment. It is not meant to predict the performance of a package in an application-specific environment.

3

Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the

mold surface temperature at the package top side dead center.

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Electrical characteristics

4.1.3

Operating Ranges

The following table provides the operating ranges of these processors.

1

Table 9. Operating ranges

Symbol

Description

Mode

Min Typ Max Unit

Comments

VDD_A35

VDD_GPU

Power supply of

Cortex-A35 cluster

Overdrive 1.05 1.10 1.15

Nominal 0.95 1.00 1.10

V

Max frequency: 1.2 GHz

Max frequency: 900 MHz

Power supply of

GPU instance

Overdrive 1.05 1.10 1.15

V

Max frequencies:

• Shaders: 850MHz

• Core: 700 MHz

Nominal

N/A

0.95 1.00 1.10

Max frequencies:

shaders: 372 MHz;

core: 372 MHz

VDD_MAIN²

Power supply of

remaining core

logic

Max freq.: HiFi4 DSP

640 MHz

Max freq.: M4 264 MHz

Max freq.: VPU 600 MHz

VDD_DDR_VDDQ

Power supplies of

memory IOs

DDR3L

1.30 1.35 1.45

V

Max frequency: 933 MHz

to support DDR3L-1866

LPDDR4 1.06 1.10 1.17

Max frequency: 1.2GHz

to support

LPDDR4-2400

VDD_DDR_PLL_1P8

VDD_MIPI_1P0

Power supplies of

memory PLLs

N/A

1.65 1.80 1.95

V

PLL supply can be

merged with other 1.8V

supplies with proper on

board decoupling.

Power supplies of

PHYs (1.0V part)

N/A

0.95 1.00 1.10

1.65 1.80 1.95

V

—

VDD_ANA0_1P8

VDD_ANA1_1P8

Power supplies of

IOs, analog and

oscillator of the

SCU

These balls shall be

powered by a dedicated

supply

VDD_ADC_1P8

VDD_ADC_DIG_1P8

VDD_MIPI_1P8

VDD_MIPI_CSI_DIG_1P8

VDD_USB_1P8

Power supplies of

PHYs (1.8V part)

and GPIO

operating at 1.8V

only.

N/A

1.65 1.80 1.95

1.71 1.80 1.89

V

—

VDD_PCIE_1P8

Power supplies of

PCIE PHY (1.8 V

part)

—

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Electrical characteristics

1

Table 9. Operating ranges (continued)

Symbol

Description

Mode

Min Typ Max Unit

Comments

VDD_USB_3P3

Power supplies of

PHYs (3.3V part)

and GPIO

N/A

3.00 3.30 3.60

V

—

operating at 3.3V

only

VDD_CAN_UART_1P8_3P3

VDD_CSI_1P8_3P3

VDD_EMMC0_1P8_3P3

VDD_EMMC0_VSELECT_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_PCIE_DIG_1P8_3P3

VDD_QSPI0A_1P8_3P3

Power supplies of

GPIO supporting

both 1.8V or 3.3V

1.8V

1.65 1.80 1.95

V

When

VDD_USDHC1_1P8_3P

3 is used to support an

SD card, then it shall be

on a dedicated

1.8V/3.3V regulator.

When

VDD_QSPI0B_1P8_3P3

VDD_SPI_MCLK_UART_1P8_3P3

VDD_SPI_SAI_1P8_3P3

VDD_TMPR_CSI_1P8_3P3

VDD_USDHC1_1P8_3P3

VDD_SIM0_1P8_3P3 is

used to support a SIM

card, it shall be on a

dedicated 1.8V/3.3V

regulator.

VDD_USDHC1_VSELECT_1P8_3P3

When

VDD_TMPR_CSI_1P8_

3P3 is used as a GPIO it

can be connected to the

1.8/3.3V supply.

VDDs of this list targeting

1.8V can share 1.8V

regulator of 1.8V only

VDDs

VDDs of this list targeting

3.3V can share 3.3V

regulator of 3.3V only

VDDs

3.3V

1.8V

2.5V

3.3V

N/A

3.00 3.30 3.60

1.65 1.80 1.95

2.40 2.50 2.60

3.00 3.30 3.60

2.80 3.30 4.20

V

—

VDD_ENET0_1P8_2P5_3P3

VDD_ENET0_VSELECT_1P8_2P5_3P3 ethernet IOs

VDD_ESAI_SPDIF_1P8_2P5_3P3

Power supplies of

VDD_SNVS_4P2

Power supply of

SNVS

It can be supplied by a

backup battery: a coin

cell or a super cap.

Output of embedded LDOs

VDD_PCIE_LDO_1P0_CAP

VDD_USB_SS3_LDO_1P0_CAP

1.0V output of

embedded LDOs

N/A

—

1.00

1.80

—

V

—

VDD_SNVS_LDO_1P8_CAP

1.8V output of

SNVS embedded

LDO

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Electrical characteristics

Symbol

1

Table 9. Operating ranges (continued)

Description Mode Min Typ Max Unit

Power supplies that shall be connected to output of an embedded LDO

Comments

VDD_TMPR_CSI_1P8_3P3

—

N/A

—

1.80

—

V

Shall be connected to

VDD_SNVS_LDO_1P8_

CAP when used as a

tamper pin. In CSI mode

use an external 1.8 V

supply. In this case,

follow the 1.8 V I/O

specification above.

VDD_USB_OTG_1P0

Junction temperature

—

N/A

—

1.00

—

V

Shall be externally

connected to

VDD_USB_SS3_LDO_1

P0_CAP

Junction temperature

—

-40

—

105 °C

—

1

2

Voltage ranges are defined to group as many supplies as possible. Some supplies may have a wider range than listed here.

During low power state (see Section 4.1.6, “Low power mode supply currents"), this voltage can be dropped to 0.8 V +/- 3%

for retention.

4.1.4

External clock sources

Each processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency

(XTALI).

The RTC_XTALI is used for real time functions. It supplies the clock for real time clock operation and for

slow-system and watchdog counters. The clock input can be connected to either an external oscillator or a

crystal using the internal oscillator amplifier.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input requires a crystal using the internal oscillator amplifier.

The PCIe oscillator can be sourced internally or input to the chip. In both cases, it is a 100 MHz nominal

clock using HCSL signaling to provide the PCIe reference clock.

The following table shows the interface frequency requirements.

Table 10. External Input Clock Frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator^1,2

XTALI Oscillator^4,2

PCIe oscillator⁵

f_ckil

f_xtal

f_100M

—

32.768³/32.0

—

kHz

MHz

ppm

24

100

—

Frequency accuracy

±300

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Electrical characteristics

1

2

External oscillator or a crystal with internal oscillator amplifier.

The required frequency stability of this clock source is application dependent. For recommendations, see the hardware

development guide for this device.

3

4

5

Recommended nominal frequency 32.768 kHz.

Fundamental frequency crystal with internal oscillator amplifier.

If using an external clock instead of the internal clock source, an HCSL-compatible clock is required.

The typical values shown in Table 10 are required for use with NXP board support packages (BSPs) to

ensure precise time keeping and USB operations.

4.1.5

Maximum Supply Currents

NOTE

Some of the numbers shown in this table are based on the companion

regulator limits and not actual use cases. Work is in progress to provide use

case–based numbers in future data sheet releases.

Table 11. Maximum supply currents

Symbol

Value Unit

Comments

VDD_A35¹

VDD_GPU¹

VDD_MAIN

2500 mA

5000 mA

VDD_DDR_VDDQ

1200 mA Does not comprehend IO of memory

VDD_DDR_PLL_1P8

VDD_ANA0_1P8

20

200

100

115

18

mA

VDD_ANA1_1P8

VDD_MIPI_1P0

VDD_MIPI_1P8

VDD_ADC_DIG_1P8

VDD_CAN_UART_1P8_3P3

VDD_CSI_1P8_3P3

30

12

VDD_EMMC0_1P8_3P3

VDD_EMMC0_VSELECT_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_2P5_3P3

30

15

30

VDD_ENET0_VSELECT_1P8_2P5_3

P3

30

VDD_ESAI_SPDIF_1P8_2P5_3P3

VDD_MIPI_CSI_DIG_1P8

39

15

mA

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Electrical characteristics

Symbol

Table 11. Maximum supply currents (continued)

Value Unit Comments

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_PCIE_DIG_1P8_3P3

VDD_QSPI0A_1P8_3P3

VDD_QSPI0B_1P8_3P3

VDD_SPI_MCLK_UART_1P8_3P3

VDD_SPI_SAI_1P8_3P3

VDD_TMPR_CSI_1P8_3P3

VDD_USDHC1_1P8_3P3

VDD_USDHC1_VSELECT_1P8_3P3

VDD_ADC_1P8

24

9

mA

40

36

48

30

20

5

mA

VDD_USB_OTG_1P0

36

175

40

255

5

mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP

VDD_USB_1P8

mA

VDD_USB_3P3

mA

VDD_PCIE_1P8

mA

VDD_SNVS_4P2²

mA Start-up current

1

VDD_A35 and VDD_GPU can be combined with one power supply.

2

Under normal operating conditions, the maximum current on VDD_SNVS_4P2 is shown Table 11. During initial power on,

VDD_SNVS_4P2 can draw up to 5 mA if the supply is capable of sourcing that current. If less than 5 mA is available, the

VDD_SNVS_LDO_1P8_CAP charge time will increase.

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4.1.6

Low power mode supply currents

The following table shows the current core consumption (not including I/O) in selected low power modes.

Table 12. i.MX 8QuadXPlus/8DualXPlus Key State (KSx) power consumption

Mode

Test conditions

Supply

Max

Unit

KS0 SNVS only, all other supplies OFF. RTC running, tamper not active,

external 32K crystal.

VDD_SNVS_4P2 (4.2 V)

50

μA

KS1¹RAM and IO state retained.

DRAM in self-refresh, associated I/O’s OFF.

32K running, 24M, PLLs and ring oscillators OFF.

PHYs are in idle state.

VDD_ANAx_1P8 (1.8 V)

VDD_A35 (OFF)

VDD_GPU (OFF)

VDD_MAIN (0.8 V)

VDD_DDR_VDDQ (1.1 V)

Total

0.9

—

33

0.5

28.6

mA

mW

A35 and GPU supplies OFF.

MAIN²dropped to 0.8 V.

KS4³Leakage test, not intended as a customer use case.

VDD_ANAx_1P8 (1.8 V)

3.5

600

250

1100

2541

mA

mW

Overdrive conditions set, memories active, all sub-systems powered ON. VDD_A35 (1.1 V)

Active power minimized.

VDD_GPU (1.1 V)

VDD_MAIN (1.0 V)

Total

1

2

3

Maximum values are for 25 °C T_ambient

0.8 V nominal—voltage specification under this case is ± 3%.

.

Maximum values are for 105 °C T_junction

.

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4.1.7

USB 2.0 PHY typical current consumption in Power-Down mode

In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.

The following table shows the USB interface typical current consumption in Power-Down mode.

Table 13. USB 2.0 PHY typical current consumption in Power-Down Mode

VDD_USB_3P3 (3.3 V)

VDD_USB_1P8 (1.8 V)

VDD_USB_OTG_1P0 (1.0 V)

Current

1 μA

0.06 μA

0.5 μA

4.1.8

USB 3.0 PHY typical current consumption in Power-Down mode

In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.

The following table shows the USB interface typical current consumption in Power-Down mode.

Table 14. USB 3.0 PHY typical current consumption in Power-Down Mode

—

VDD_USB_1P8 (1.8 V)

VDD_USB_OTG_1P0 (1.0 V)

Current

—

10 μA

70 μA

The following table shows the current consumption for the USB 2.0 PHY embedded in the USB 3.0

PHY.

Table 15. Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY

VDD_USB_OTG2_1P0VDD_U

VDD_USB_3P3 (3.3 V)

VDD_USB_1P8 (1.8 V)

SB_OTG_1P0 (1.0 V)

Current—Host mode

22.6 μA

12.6 μΑ

12.7 μΑ

85.7 μΑ

81.5 μΑ

78.5 μΑ

Current—Device mode

4.1.8.1

USB 3.0 Type-C connector considerations

The device supports USB 3.0 Type-C connection when used in conjunction with the following devices:

•

PTN36043

PTN5150A

NX5P3090UK

NXP supports many other configurations and implementations for USB 3.0 Type-C connections. See NXP

USB Type-C: True Plug’n Play .

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4.2

Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to ensure the reliable operation of the device. Any deviation from

these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor

4.2.1

Power-up sequence

The device has the following power-up sequence requirements:

•

Supply group 0 (SNVS) must be powered first. It is expected that group 0 will typically remain

always on after the first power-on.

Supply group 1 (MAIN and SCU) and group 0 must both be powered to their nominal values prior

to boot. They must power up after or simultaneously with group 0.

Supply group 2 (I/O’s and DDR interface) consists of those modules required to start the boot

process by accessing external storage devices. These must be fully powered prior to POR release

if booting from one of these supplies interfaces. They must power up after or simultaneously with

group 1.

•

Supply group 3 consists of the remaining portions of the SoC. This includes nonboot I/O voltages

and supplies for the major computational units. These can be sequenced in any order and as

required to perform the desired functions for the intended application. They must power up after

or simultaneously with group 2.

NOTE

The definition of “power-up” refers to a stable voltage operating within the

range defined in Table 9. This should be taken into consideration, along

with the different capacitive loading on each rail, if considering

simultaneous switch-on of the different supply groups.

4.2.2

Power-down sequence

The device processor has the following power-down sequence requirements:

•

Supply group 0 must be turned off last, after all other supplies.

Supply group 1 can be turned off just prior to group 0.

All remaining supplies can be turned off prior to group 1.

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NOTE

When switching off supply group 0 (SNVS), VDD_SNVS_4P2 must be

discharged below 2.4 V before starting the next power-up sequence to

ensure correct operation. This will generate a full SNVS reset, allowing

correct operation on the next power-up sequence. This would also be a

requirement to clear any security related flag as a result of an SNVS voltage

drop, when tamper features are enabled.

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4.3

PLL electrical characteristics

4.3.1

PLLs of subsystems

i.MX 8QuadXPlus/8DualXPlus embeds a large number of PLLs to address clocking requirements of the

various subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or

Cortex-M4F processors. A software API shall be used by those processors to access the PLL settings.

Additional PLLs are specific to high-performance interfaces. These are described in the following

sections.

This table summarizes the PLLs controlled by the SCU.

Table 17. PLLs controlled by SCU

Locking range¹

Subsystem

PLL usage

Source clock

Lock freq.

Unit

Min freq. Max freq.

Cortex-A35

Subsystem

24

650

1300

• Overdrive: 1200

• Nominal: 900²

GPU

PLL #0: subsystem

PLL #1: shaders

Subsystem

24

648

1344

2500

• Overdrive: 700

• Nominal: 744³

MHz

• Overdrive: : 850

• Nominal: 744⁴

DRC (DRAM

Controller)

1250

• LPDDR4: 2400

• DDR3L: 1866⁵

DB (DRAM Block)

Subsystem

24

650

1300

1200

800

MHz

Display Controller 0 PLL #0: subsystem

PLL #1: display clock #0

User-configurable

1200

PLL #2: display clock #1

Imaging

ADMA⁶

Subsystem

PLL #0: subsystem

PLL #1: audio PLL #0

PLL #2: audio PLL #1

PLL #3: Parallel LCD display

PLL #0: Subsystem

PLL #1: PHY

1280

User-configurable

Pixel freq. ×N

792

Connectivity

1000

HSIO (High-speed

I/O)

Subsystem

800

LSIO (Low-speed

I/O)

Subsystem

24

650

1300

800

MHz

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Table 17. PLLs controlled by SCU (continued)

Locking range¹

Subsystem

PLL usage

Source clock

Lock freq.

Unit

Min freq. Max freq.

Cortex-M4

Subsystem

24

650

1300

792

1200

864

MHz

VPU

PLL #0: subsystem

Subsystem

MIPI-DSI

MIPI-CSI

Subsystem

720

SCU (System

Subsystem

1056

Controller Unit)

1

2

Operating frequencies are limited to only those supported by the SCFW.

1200 MHz is used to generate the overdrive frequency point, and 900 MHz for the nominal frequency point. See Table 9 to get

associated voltages.

3

4

5

700 MHz is used to generate the overdrive frequency point, and 744 is used to generate the nominal point (372 MHz).

850 MHz is used to generate the overdrive frequency point, and 744 is used to generate the nominal point (372 MHz)

2400 MHz is used to generate 1200 MHz when in LPDDR4 mode. 1866 MHz is used to generate 933 MHz when in DDR3L

mode. See Table 9 to get associated voltages.

6

The audio PLLs support on-the-fly frequency changes for clock synchronization applications, 25 Hz steps, up to a maximum

change of +/- 250 KHz is supported.

4.3.2

PLLs dedicated to specific interfaces

The following sections cover PLLs used for specific interfaces. Clock output frequency and clock output

range refer to the output of the PLL. Additional clock dividers may be on the output path to divide the

output frequency down to the targeted frequency. See the related sections in the reference manual for

settings of these clock dividers.

4.3.2.1

Ethernet PLL

This PLL is controlled by the SCU.

Table 18. Ethernet PLL

Parameter

Value

Unit

Reference clock

24

1

MHz

GHz

Clock output frequency

4.3.2.2

USB 3.0 PLLs

USB 3.0 has two PLLs. One is embedded in Super-Speed PHY. The other one is embedded in the USB 2.0

OTG PHY that is part of the USB 3.0 interface.

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The table below describes the PLL embedded in the Super-Speed PHY.

Table 19. USB 2.0 PLL embedded in Super Speed PHY

Parameter

Value

Unit

Reference clock

24

5

MHz

GHz

Clock output frequency

The table below describes the PLL embedded in the USBOTG PHY.

Table 20. USB 2.0 PLL embedded in USBOTG PHY

Parameter

Value

Unit

Reference clock

24

MHz

Clock output frequency

480

4.3.2.3

USB 2.0 OTG PLLs

This PLL is embedded in the USB 2.0 OTG PHY (the one which is not part of the USB 3.0 feature).

Table 21. USB 2.0 OTG PLLs

Parameter

Value

Unit

Reference clock

24

MHz

Clock output frequency

480

4.3.2.4

PCIe PLLs

The PCIe interface has three PLLs:

•

One is used to generate the single, common 100 MHz reference clock to each lane

One Transmit and one Receive PLL in one lane

The table below shows the characteristics for the reference clock PLL.

Table 22. PCIe reference clock PLLs

Parameter

Value

Unit

Comments

Reference clock

Clock output frequency

24

MHz

—

100

MHz Used to generate internal 100 MHz reference clock to PCIe lanes

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The table below shows characteristics of the TX and RX PLLs used in each lane.

Table 23. PCIe Transmit and Receive PLLs

Parameter

Value

Unit

Comments

Reference clock

100

MHz From differential input clock pads or from internal PLL

Clock output range

6 ~ 10

GHz PCIe gen3: 8GHz to get 8GHz baud clock

PCIe gen2: 10GHz to get 5GHz baud clock

PCIe gen3: 10GHz to get 2.5GHz baud clock

4.3.2.5

MIPI-DSI/LVDS combo PLL

The table below shows characteristics of the PLL embedded in the MIPI-DSI/LVDS combo PHY.

Table 24. MIPI-DSI/LVDS combo PHY PLL

Parameter

Value

Unit

Comments

Reference clock

Clock output range

24

MHz

—

0.75 ~ 1.05

GHz Dependent on targeted display configuration

4.4

On-chip oscillators

OSC24M

4.4.1

This block integrates trimmable internal loading capacitors and driving circuitry. When combined with a

suitable 24 MHz external quartz element, it can generate a low-jitter clock. The oscillator is powered from

VDD_ANA1_1P8. The internal loading capacitors are trimmable to provide fine adjustment of the

24 MHz oscillation frequency. It is expected that customers burn appropriate trim values for the selected

crystal and board parasitics.

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Figure 2. Normal Crystal Oscillation mode

Table 25. Crystal specifications

Parameter description

Min

Typ

Max

Unit

Frequency¹

—

24

18

—

60

MHz

pF

Cload²

Maximum drive level

200

—

μW

Ω

ESR

1

The required frequency accuracy is set by the serial interfaces utilized for a specific application and is detailed in the

respective standard documents.

2

Cload is the specification of the quartz element, not for the capacitors coupled to the quartz element.

4.4.2

OSC32K

This block implements an internal amplifier, trimmable load capacitors and a bias network that when

combined with a suitable quartz crystal implements a low power oscillator.

Additionally, if the clock monitor determines that the 32KHz oscillation is not present, then the source of

the 32 KHz clock will automatically switch to the internal relaxation oscillator of lesser frequency

accuracy.

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CAUTION

The internal ring oscillator is not meant to be used in customer applications,

due to gross frequency variation over wafer processing, temperature, and

supply voltage. These variations will cause timing issues to many different

circuits that use the internal ring oscillator for reference; and, if this timing

is critical, application issues will occur. To prevent application issues, it is

recommended to only use an external crystal or an accurate external clock.

If this recommendation is not followed, NXP cannot guarantee full

compliance of any circuit using this clock. The OSC32K runs from

VDD_SNVS_LDO_1P8_CAP, which is regulated from VDD_SNVS. The

target battery/voltage range is 2.8 to 4.2 V for VDD_SNVS, with a regulated

output of approximately 1.75 V.

Table 26. OSC32K main characteristics

Parameter

Min

Typ

Max

Comments

Fosc

—

32.768 kHz

—

This frequency is nominal and determined mainly by

the crystal selected. 32.0 KHz is also supported.

Current

consumption

—

• xtal oscillator mode: 5 μA

—

These values are for typical process and room

temperature. Values will be updated after silicon

characterization.

• 32K internal oscillator mode: 10 μA

Bias resistor

200 MΩ

This the integrated bias resistor that sets the amplifier

into a high gain state. Any leakage through the ESD

network, external board leakage, or even a scope

probe that is significant relative to this value will

debias the amplifier. The debiasing will result in low

gain, and will impact the circuit's ability to start up and

maintain oscillations.

Target Crystal Properties

Cload

ESR

—

10 pF

—

Usually crystals can be purchased tuned for different

Cloads. This Cload value is typically 1/2 of the

capacitances realized on the PCB on either side of

the quartz. A higher Cload will decrease oscillation

margin, but increases current oscillating through the

crystal.

50 kΩ

100 kΩ Equivalent series resistance of the crystal. Choosing

a crystal with a higher value will decrease the

oscillating margin.

Table 27. External input clock for OSC32K

Min

Typ

Max

Unit

Notes

Frequency

—

700

—

32.768 or 32

—

kHz

mV

ns

—

1,2,3

V_PPRTC_XTALI

Rise/fall time

—

VDD_SNVS_LDO_1P8_CAP

—

4

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1

The external clock is fed into the chip from the RTC_XTALI pin; the RTC_XTALO pin should be left floating.

2

The parameter specified here is a peak-to-peak value and VI_H/V_ILspecifications do not apply.

3

The voltage applied on RTC_XTALI must be within the range of VSS to VDD_SNVS_LDO_1P8_CAP.

4

The rise/fall time of the applied clock are not strictly confined.

4.5

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

XTALI and RTC_XTALI (clock inputs) DC parameters

General Purpose I/O (GPIO) DC parameters

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output.

ovdd

pmos (Rpu)

Voh min

1

Vol max

or

0

pdat

pad

Predriver

nmos (Rpd)

ovss

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.5.1

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

For RTC_XTALI, V /V specifications do not apply. The high and low levels of the applied clock on

IH IL

this pin are not strictly defined, as long as the input’s peak-to-peak amplitude meet the requirements and

the input’s voltage value does not exceed the limits.

4.5.2

General-purpose I/O (GPIO) DC parameters

Tri-voltage GPIO DC parameters

4.5.2.1

The following tables show tri-voltage 1.8V, 2.5 V, and 3.3 V DC parameters, respectively, for GPIO pads.

These parameters are guaranteed per the operating ranges in Table 9, unless otherwise noted.

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1

Table 28. Tri-voltage 1.8 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^2,3

V_OH

I_OH= -0.1mA

DSE=1

0.8 × OVDD

—

V

I_OH= -2mA

DSE=0

Low-level output voltage^2,3

V_OL

I_OL= -0.1mA

DSE=1

—

0.125 × OVDD

V

I

_OL= -2mA

DSE=0

High-Level input voltage^2,4

Low-Level input voltage

Pull-up resistance

V_IH

V_IL

—

0.625 × OVDD

OVDD

0.25 × OVDD

50

V

0

R_PU

V_IN=0V (Pullup Resistor)

PUN = "L", PDN = "H"

15

kΩ

Pull-down resistance

R_DOWN

V_IN=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

15

-1

50

1

kΩ

μA

Input current (no PU/PD)

I_IN

VI = 0, VI = OVDD

PUN = "H", PDN = "H"

1

For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly.

For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation,

PSW_OVR = 0b1 and COMP = 0b010.

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD

is the I/O Supply)

3

4

DSE is the setting of the PDRV register. High Drive mode is recommended for 3v3 and 2v5 modes. Low Drive mode is

recommended for 1v8 mode.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 ns.

1

Table 29. Tri-voltage 2.5 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

V

High-level output voltage^2,3

I_OH= -2mA

DSE=0

0.8 × OVDD

—

V

OH

V

Low-level output voltage^2,3

I_OL= -2mA

DSE=0

—

0.125 × OVDD

V

OL

V

High-Level input voltage^2,4

Low-Level input voltage

Pull-up resistance

—

0.625 × OVDD

OVDD

0.25 × OVDD

100

V

IH

V_IL

0

RPU

V_IN=0V (Pullup Resistor)

PUN = "L", PDN = "H"

10

kΩ

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1

Table 29. Tri-voltage 2.5 V GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Pull-down resistance

R_DOWN

V_IN=OVDD( Pulldown

Resistor)

10

100

kΩ

PUN = "H", PDN = "L"

Input current (no PU/PD)

I_IN

VI = 0, VI = OVDD

PUN = "H", PDN = "H"

-1

1

μA

1

For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly.

For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation,

PSW_OVR = 0b1 and COMP = 0b010.

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD

is the I/O supply.)

3

4

DSE is the setting of the PDRV register. High Drive mode is recommended for 3v3 and 2v5 modes. Low Drive mode is

recommended for 1v8 mode.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 ns.

1

Table 30. Tri-voltage 3.3 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

V

High-level output voltage^2,3

I_OH= -0.1mA

4DSE=1

0.8 × OVDD

V

OH

I_OH= -2mA

4DSE=0

V

Low-level output voltage^2,3

I_OL= -0.1mA

4DSE³=1

—

0.125 × OVDD

V

OL

I_OL= -2mA

4DSE=0

V

High-Level input voltage^2,4,3

Low-Level input voltage

Pull-up resistance

—

0.725 × OVDD

OVDD

0.25 × OVDD

100

V

IH

V_IL

0

RPU

V_IN=0V (Pullup Resistor)

PUN = "L", PDN = "H"

10

kΩ

Pull-down resistance

R_DOWN

V_IN=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

10

-2

100

2

kΩ

μA

Input current (no PU/PD)

IIN

VI = 0, VI = OVDD

PUN = "H", PDN = "H"

1

For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly.

For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation,

PSW_OVR = 0b1 and COMP = 0b010.

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2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD

is the I/O Supply.)

3

4

DSE is the setting of the PDRV register. High Drive mode recommended for 3v3 and 2v5 modes. Low Drive mode is

recommended for 1v8 mode.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 ns.

4.5.2.2

Dual-voltage GPIO DC parameters

The following two tables show dual-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO

pads. These parameters are guaranteed per the operating ranges in Table 9, unless otherwise noted.

Table 31. Dual-voltage 1.8 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Ioh= -0.1mA

Min

Max

Units

High-level output voltage^1,2

V_OH

0.8 × OVDD

—

V

DSE=1

Ioh= -2mA

DSE=0

Low-level output voltage^1,2

High-Level input voltage^1,3

V_OL

Iol= -0.1mA

DSE=1

—

0.125 × OVD

V

D

Iol= -2mA

DSE=0

V_IH

—

0.625 × OVD

OVDD

D

Low-Level input voltage

Pull-up resistance

V_IL

0

0.25 × OVDD

V

R_PU

Vin=0 V (Pullup Resistor)

PUN = "L", PDN = "H"

15

50

kΩ

Pull-down resistance

R_downVin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

15

-1

50

1

kΩ

μA

Input current (no PU/PD)

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

1

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD

is the IO Supply.)

2

3

DSE is the setting of the PDRV register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard

(1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode).

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 ns.

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Table 32. Dual-voltage 3.3 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^1,2

V_OH

Ioh= -0.1mA

DSE=1

0.8 × OVDD

—

V

Ioh= -2mA

DSE=0

Low-level output voltage^1,2

V_OL

Iol= -0.1mA

DSE=1

—

0.125 × OVDD

V

Iol= -2mA

DSE=0

High-Level input voltage^1,3

Low-Level input voltage

Pull-upresistance

V_IH

V_IL

—

0.725 × OVDD

OVDD

0.25 × OVDD

100

V

0

R_PU

Vin=0V (Pullup Resistor)

PUN = "L", PDN = "H"

10

kΩ

Pull-down resistance

R_down

Vin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

10

-2

100

2

kΩ

μA

Input current (no PU/PD)

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

1

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the I/O

Supply.)

2

3

DSE is the setting of the PDRV register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard

(1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode).

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 ns.

4.5.2.3

Single-voltage GPIO DC parameters

Table 33 and Table 34 show single-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads.

These parameters are guaranteed per the operating ranges in Table 9 unless otherwise noted.

Table 33. Single-voltage 1.8 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^1,2

V_OH

I_OH= -0.1mA

DSE = 000 or 001

OVDD × 0.8

—

V

I_OH= -2mA

DSE = 010 or 011

I_OH= -4mA

DSE = 100 to 110

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Table 33. Single-voltage 1.8 V GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Low-level output voltage^1,2

V_OL

I_OL= 0.1mA

DSE = 000 or 001

—

OVDD × 0.2

V

I_OL= 2mA

DSE = 010 or 011

I

_OL= 4mA

DSE = 100 to 110

High-Level input voltage^2,3

Low-Level input voltage^2,3

Pull-up resistance

V_IH

V_IL

—

0.65 × OVDD

OVDD

0.35 × OVDD

90

V

0

R_PU

Vin=0V (Pullup Resistor)

PUN = "L", PDN = "H"

20

kΩ

Pull-down resistance

R_down

Vin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

20

-5

90

5

kΩ

μA

kΩ

Input current (no PU/PD)

Keeper Circuit Resistance

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

R_Keeper

V_I=.3xOVDD, VI = .7x OVDD

PUN = "L", PDN = "L"

20

90

1

As programmed in the associated IOMUX (DSE field) register.

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3

V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD

is the IO supply.)

3

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 ns.

Table 34. Single-voltage 3.3 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^1,2

V_OH

I_OH= -0.1mA

DSE = 00 or 01

0.8 × OVDD

—

V

I_OH= -2mA

DSE = 10 or 11

Low-level output voltage^1,2

V_OL

I_OL=0.1mA

DSE = 00 or 01

—

0.2 × OVDD

V

I_OL= 2mA

DSE = 10 or 11

High-Level input voltage^2,3

Low-Level input voltage^2,3

Pull-upresistance

V_IH

V_IL

—

0.75 × OVDD

OVDD

0.25 × OVDD

90

V

0

R_PU

Vin=0 V (Pullup Resistor)

PUN = "L", PDN = "H"

20

kΩ

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Table 34. Single-voltage 3.3 V GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Pull-down resistance

R_down

Vin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

20

90

kΩ

Input current (no PU/PD)

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

-5

5

μA

kΩ

Keeper Circuit Resistance

R_Keeper

V_I=.3xOVDD, VI = .7x OVDD

PUN = "L", PDN = "L"

20

90

1

As programmed in the associated IOMUX (DSE field) register.

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD

is the IO supply.)

3

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, V_ILor V_IH. Monotonic input transition time is from 0.1 ns to 1 ns.

4.5.3

DDR I/O DC parameters

4.5.3.1

LPDDR4 mode I/O DC parameters

These parameters are guaranteed per the operating ranges in Table 9 unless otherwise noted.

Table 35. LPDDR4 DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage¹

V_OH

Out Drive = All setting

(40,48,60,80,120,240)

unterminated outputs loaded

with 1pF capacitor load

0.9 × V_DDQ

—

V

Low-level output voltage¹

V_OL

Out Drive = All setting

(40,48,60,80,120,240)

unterminated outputs loaded

with 1pF capacitor load

—

0.1 × V_DDQ

V

Input current (no ODT)

I_IN

V_I= VSSQ, V_I= VDDQ

-2

2

μA

V

DC High-Level input voltage

DC Low-Level input voltage

V_{IH_DC}

V_{IL_DC}

—

VREF + 0.1

VSSQ

VDDQ

VREF – 0.1

V

1

Maximum peak amplitude allowed for overshoot and undershoot area = 0.35 V. Maximum overshoot area above VDD/VDDQ

0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns.

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4.5.3.2

DDR3L mode I/O DC parameters

Table 36. SSTL DDR3L DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

DC High-level output voltage ¹

V_OH

Out Drive = All setting

(40,60,120) unterminated

outputs loaded with 1pF

capacitor load

0.8 × V_DDQ

—

V

DC Low-level output voltage¹

V_OL

Out Drive = All setting

(40,60,120) unterminated

outputs loaded with 1pF

capacitor load

—

0.2 × V_DDQ

V

Input termination resistance (ODT) to VDDQ/2

RTT

40 Ω setting

36

54

44

Ω

60 Ω setting

66

140

120 Ω setting

100

Input current (no ODT)

I_IN

V_I= VSSQ, V_I= VDDQ

-2

2

μA

V

DC High-Level input voltage

DC Low-Level input voltage

V_{IH_DC}

V_{IL_DC}

VREF + 0.09

VSSQ

VDDQ

VREF – 0.09

V

1

Maximum peak amplitude allowed for overshoot and undershoot area = 0.35 V. Maximum overshoot area above VDD/VDDQ

0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns.

4.6

I/O AC Parameters

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and

Figure 5.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

OVDD

0 V

80%

20%

80%

20%

tr

Output (at pad)

tf

Figure 5. Output Transition Time Waveform

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4.6.1

General Purpose I/O (GPIO) AC Parameters

1

Table 37. General Purpose I/O AC Parameters

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

1.8 V application²

f_max

Maximum frequency

Load = 21 pF (PDRV = H, high

—

208

MHz

drive, Type A, 33 Ω

Load = 15 pF (PDRV = L, low

drive, Type B, 50 Ω

tr

tf

Rise time

Fall time

Measured between V_OLand

V_OH

0.4

—

1.32

ns

Measured between V_OHand

V_OL

Driver 3.3 V application³

f_max

tr

Maximum frequency

Rise time

Load = 30 pF

—

52

3

MHz

ns

Measured between

V_OLand V_OH

tf

Fall time

Measured between

V_OHand V_OL

—

3

ns

1

All output I/O specifications are guaranteed for Accurate mode of the compensation cell operation. This is applicable for both

DC and AC specifications.

2

3

All timing specifications in 1.8 V application are valid for High Drive mode (PDRV = H). In Low Drive mode (PDRV = L), the

driver is functional.

All timing specifications in 3.3 V application are valid for Type B driver only. In Type A, the driver is functional.

Table 38. Dynamic input characteristics

Symbol

Parameter

Condition^1,2

Min

Max

Unit

Dynamic Input Characteristics for 3.3 V Application

f_op

Input frequency of operation

—

52

3.5

MHz

ns

INPSL Slope of input signal at I/O

IOMAX High level input voltage

IOMIN Low level input voltage

Measured between 10% to 90% of the I/O swing

—

3.3 V + 0.3 V

—

V

-0.3 V

Dynamic Input Characteristics for 1.8 V Application

f_op

Input frequency of operation

—

208

1.5

MHz

ns

INPSL Slope of input signal at I/O

IOMAX High level input voltage

IOMIN Low level input voltage

Measured between 10% to 90% of the I/O swing

—

1.8 V + 0.3 V

—

V

-0.3 V

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1

2

For all supply ranges of operation.

The dynamic input characteristic specifications are applicable for the digital bidirectional cells.

4.7

Output Buffer Impedance Parameters

This section defines the I/O impedance parameters for the following I/O types:

•

General Purpose I/O (GPIO) output buffer impedance

Double Data Rate I/O (DDR) output buffer impedance for LPDDR4 and DDR3L modes

NOTE

GPIO and DDR I/O output driver impedance is measured with “long”

transmission line of impedance Ztl attached to I/O pad and incident wave

launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that

defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 6).

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OVDD

PMOS (Rpu)

Ztl Ω, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

Vin (do)

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd – Vref1

Vref1

Rpu =

Rpd =

× Ztl

Vref2

Vovdd – Vref2

Figure 6. Impedance Matching Load for Measurement

4.7.1

GPIO output buffer impedance

4.7.1.1

Tri-voltage GPIO output buffer impedance

Table 39. Tri-voltage 1.8 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

33

50

Ω

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1

As programmed in the associated IOMUX (PDRV field) register.

Table 40. Tri-voltage 2.5 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

25

33

Ω

1

As programmed in the associated IOMUX (PDRV field) register.

Table 41. Tri-voltage 3.3 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

25

37

Ω

1

As programmed in the associated IOMUX (PDRV field) register.

4.7.1.2

Dual-voltage GPIO output buffer impedance

Table 42. Dual-voltage 1.8 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

33

50

Ω

1

‘As programmed in the associated IOMUX (PDRV field) register.

Table 43. Dual-voltage 3.3 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

25

37

Ω

1

As programmed in the associated IOMUX (PDRV field) register.

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4.7.1.3

Single-voltage 1.8 V GPIO output buffer drive strength

The following table shows the GPIO output buffer drive strength (OVDD 1.8 V).

Table 44. Single-voltage GPIO 1.8 V output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

¹DSE=000

¹DSE=001

¹DSE=010

¹DSE=011

¹DSE=100

¹DSE=101

¹DSE=110

¹DSE=111

200

100

55

Ω

40

Output impedance

Z_O

30

24

20

18

1

As programmed in the associated IOMUX (DSE field) register.

4.7.1.4

Single-voltage 3.3 V GPIO output buffer drive strength

The following table shows the GPIO output buffer drive strength (OVDD 3.3 V).

Table 45. Single-voltage GPIO 3.3 V output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=00

¹DSE=01

¹DSE=10

¹DSE=11

400

200

100

50

Ω

1

As programmed in the associated IOMUX (DSE field) register.

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4.7.2

DDR I/O output buffer impedance

The following tables show DDR3L and LPDDR4 I/O output buffer impedance of the device.

The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances

of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The

resulting calibration setting is then applied to all DDR pads within the PHY complex.

Table 46 and Table 48 show, respectively, the recommended ZQnPR0 field settings for the DDR3L and

LPDDR4 I/Os to achieve the desired output buffer impedances. Table 47 and Table 49 show,

respectively, the recommended ZQnPR0 field settings for the DDR3L and LPDDR4 I/Os to achieve the

desired ODT settings.

Table 46. LPDDR4 I/O output buffer impedance

Typical

Parameter

ZQnPR0

ZPROG_ASYM_PU_DRV

ZQnPR0

ZPROG_ASYM_PD_DRV

Impedance

Recommended combinations

for DQ /CA pins

5

7

80 Ω

60 Ω

48 Ω

40 Ω

3

5

7

9

120 Ω

80 Ω

60 Ω

48 Ω

9

11

Table 47. LPDDR4 I/O on-die termination impedance

Typical

Parameter

ZQnPR0. ZPROG_HOST_ODT

Impedance

Recommended combinations

for DQ/CA pins

120.0 Ω

80.0 Ω

60.0 Ω

48.0 Ω

40.0 Ω

3

5

7

9

11

Table 48. DDR3L I/O output buffer impedance

Typical

Parameter

ZQnPR0. ZPROG_ASYM_PU_DRV

Impedance

ZQnPR0. ZPROG_ASYM_PD_DRV

Recommended combinations

for DQ/CA pins

48.0 Ω

40.0 Ω

34.3 Ω

9

11

13

11

13

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Table 49. DDR3L I/O on-die termination impedance

Typical

Parameter

ZQnPR0. ZPROG_HOST_ODT

Impedance

Recommended combinations

for DQ/CA pins

120.0 Ω

60.0 Ω

40.0 Ω

1

3

5

NOTE

•

Output driver impedance is controlled across PVTs using ZQ calibration

procedure.

•

Calibration is done against 240 Ω external reference resistor.

Output driver impedance deviation (calibration accuracy) is ±5%

(max/min impedance) across PVTs.

4.8

System Modules Timing

This section contains the timing and electrical parameters for the modules in each processor.

4.8.1

Reset Timing Parameters

The following figure shows the reset timing and Table 50 lists the timing parameters.

POR_B

(Input)

CC1

Figure 7. Reset timing diagram

Table 50. Reset timing parameters

ID

Parameter

Min

Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid

1

—

XTALOSC_RTC_ XTALI cycle

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4.8.2

WDOG reset timing parameters

The following figure shows the WDOG reset timing and Table 51 lists the timing parameters.

Figure 8. SCU_WDOG_OUT timing diagram

Table 51. WDOG1_B timing parameters

ID

Parameter

Min

Max

Unit

CC3 Duration of SCU_WDOG_OUT assertion

1

—

XTALOSC_RTC_ XTALI cycle

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.

4.8.3

DDR SDRAM–specific parameters (LPDDR4 and DDR3L)

The i.MX 8x Family of processors have been designed and tested to work with JEDEC JESD209-4A–

compliant LPDDR4 memory and with JEDEC JESD79-3-1 DDR3L compliant with DDR3L memory.

Timing diagrams and tolerances required to work with these memories are specified in the respective

documents and are not reprinted here.

Meeting the necessary timing requirements for a DDR memory system is highly dependent on the

components chosen and the design layout of the system as a whole. NXP cannot cover in this document

all the requirements needed to achieve a design that meets full system performance over temperature,

voltage, and part variation; PCB trace routing, PCB dielectric material, number of routing layers used,

placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND and Supply planes

layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory

system. Consult the hardware user guide for this device and NXP validated design layouts for information

on how to properly design a PCB for best DDR performance. NXP strongly recommends duplicating an

NXP validated design as much as possible in the design of critical power rails, placement of

bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory.

All supporting material is readily available on the device web page on

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https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applicatio

ns-processors/i.mx-8-processors:IMX8-SERIES .

Processors that demonstrate full DDR performance on NXP validated designs, but do not function on

customer designs, are not considered marginal parts. A report detailing how the returned part behaved on

an NXP validated system will be provided to the customer as closure to a customer’s reported DDR issue.

Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and

modeling the designed DDR system, and validating the system under all expected operating conditions

(temperatures, voltages) prior to releasing their product to market.

Table 52. i.MX 8 Family DRAM controller supported SDRAM configurations

Parameter

LPDDR4

Number of Controllers

Number of Channels

Number of Chip Selects

Bus Width

2

2 per controller

2 per channel

16 bit per channel¹

1600 MHz

Maximum Clock Frequency

1

Only 16-bit external memory configurations are supported.

Table 53. i.MX 8QuadXPlus/8DualXPlus DRAM controller supported SDRAM configurations

Parameter

Number of Controllers

LPDDR4

DDR3L

1

Number of Channels

Number of Chip Selects

Bus Width

2 per controller

2 per channel

16-bit per channel

1200 MHz

N/A

2 per controller

32-bit (optional 40-bit with ECC)

933 MHz

Maximum Clock Frequency

4.8.3.1

Clock/data/command/address pin allocations

These processors uses generic names for clock, data and command address bus (DCF—DRAM controller

functions); the following table provides mapping of clock, data and command address signals for LPDDR4

and DDR3L modes.

Table 54. Clock, data, and command address signals for LPDDR4 and DDR3L modes

Signal name

LPDDR4

DDR_CK0_P

DDR_CK0_N

CK_t_A

CK_c_A

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Table 54. Clock, data, and command address signals for LPDDR4 and DDR3L modes (continued)

Signal name

LPDDR4

DDR_CK1_P

DDR_CK1_N

DDR_DQ_[15:0]

DDR_DQ_[31:16]

DDR_DQ_[39:32]

DDR_DQS_N_[3:0]

DDR_DQS_P_[3:0]

DDR_DQS_N_4

DDR_DQS_P_4

DDR_DM_[3:0]

DDR_DM_4

CK_t_B

CK_c_B

DQ[15:0]_A

DQ[15:0]_B

DQS_N_[3:0]

DQS_P_[3:0]

DM_[3:0]

DDR_DCF00

DDR_DCF01

DDR_DCF03

DDR_DCF04

DDR_DCF05

DDR_DCF07

DDR_DCF08

DDR_DCF09

DDR_DCF10

DDR_DCF11

DDR_DCF12

DDR_DCF14

DDR_DCF15

DDR_DCF16

DDR_DCF17

DDR_DCF18

DDR_DCF19

DDR_DCF20

DDR_DCF21

DDR_DCF22

DDR_DCF23

DDR_DCF24

CA2_A

CA4_A

CA5_A

CA3_A

ODT_CA_A

CS0_A

CA0_A

CS1_A

CKE0_A

CKE1_A

CA1_A

CA4_B

RESET_N

CA5_B

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Table 54. Clock, data, and command address signals for LPDDR4 and DDR3L modes (continued)

Signal name

LPDDR4

DDR_DCF25

DDR_DCF26

DDR_DCF27

DDR_DCF28

DDR_DCF29

DDR_DCF30

DDR_DCF31

DDR_DCF32

DDR_DCF33

ODT_CA_B

CA3_B

CA0_B

CS0_B

CS1_B

CKE0_B

CKE1_B

CA1_B

CA2_B

4.8.3.2

ECC for DDR3L

i.MX 8QuadXPlus/8DualXPlus supports up to 8-bit ECC when using DDR3L only. This is accomplished

through the use of a fifth byte lane (DQS4[P:N],DM4, DQ[32:39]). When using the fifth byte lane, it is

not a requirement that all DDR3L devices be identical, but it is required that all devices be able to operate

with the same timing parameters. This can be easily accomplished by using memory containing the same

die(s), but contained in different packages. Consult the DDR3L device datasheets for timing requirements.

The fifth byte lane is for the exclusive use of ECC. If not using ECC, leave the pins as not connected. For

LPDDR4 mode, pins DQS4[P:N],DM4, DQ[32:39] are not used and cannot be substituted for one of the

other byte lanes. If using LPDDR4 mode, leave these pins as not connected.

4.9

General-Purpose Media Interface (GPMI) Timing

The GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 400 MB/s

I/O speed, and individual chip select. It supports Asynchronous Timing mode, Source Synchronous

Timing mode, and Toggle Timing mode, as described in the following subsections.

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4.9.1

GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 9 through Figure 12 depict

the relative timing between GPMI signals at the module level for different operations underAsynchronous

mode. Table 55 describes the timing parameters (NF1–NF17) that are shown in the figures.

NF2

NF1

.!.$?#,%

NF3

NF4

.!.$?#%ꢀ?"

.!.$?7%?"

NF5

.!.$?!,%

NF6

NF8

Command

NF7

NF9

.!.$?$!4!XX

Figure 9. Command Latch Cycle Timing Diagram

NF1

.!.$?#,%

NF3

.!.$?#%ꢀ?"

.!.$?7%?"

NF10

NF5

NF11

NF7

.!.$?!,%

NF6

NF8

Address

NF9

NAND_DATAxx

Figure 10. Address Latch Cycle Timing Diagram

NF1

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

NF6

.!.$?!,%

NF8

Data to NF

NF9

.!.$?$!4!XX

Figure 11. Write Data Latch Cycle Timing Diagram

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Electrical characteristics

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?2%?"

NF14

NF13

NF15

.!.$?2%!$9?"

NF12

NF16

NF17

Data from NF

.!.$?$!4!XX

Figure 12. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF13

NF15

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF17

NF16

NAND_DATAxx

Data from NF

Figure 13. Read Data Latch Cycle Timing Diagram (EDO Mode)

1

Table 55. Asynchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

(AS + DS) × T - 0.12 [see ^2,3

Max

NF1

NF2

NF3

NF4

NF5

NF6

NF7

NF8

NF9

NAND_CLE setup time

NAND_CLE hold time

NAND_CEx_B setup time

NAND_CEx_B hold time

NAND_WE_B pulse width

NAND_ALE setup time

NAND_ALE hold time

Data setup time

tCLS

tCLH

tCS

]

ns

DH × T - 0.72 [see ²]

(AS + DS + 1) × T [see ^3,2

(DH+1) × T - 1 [see ²]

DS × T [see ²]

]

tCH

tWP

tALS

tALH

tDS

(AS + DS) × T - 0.49 [see ^3,2

(DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

]

Data hold time

tDH

NF10 Write cycle time

tWC

tWH

tRR⁴

tRP

NF11 NAND_WE_B hold time

NF12 Ready to NAND_RE_B low

NF13 NAND_RE_B pulse width

NF14 READ cycle time

(AS + 2) × T [see ^3,2

]

—

DS × T [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

tRC

NF15 NAND_RE_B high hold time

tREH

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1

Table 55. Asynchronous Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF16 Data setup on read

NF17 Data hold on read

tDSR

tDHR

—

(DS × T -0.67)/18.38 [see ^5,6

]

ns

0.82/11.83 [see ^5,6

]

—

1

The GPMI asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

5

6

AS minimum value can be 0, while DS/DH minimum value is 1.

T = GPMI clock period -0.075ns (half of maximum p-p jitter).

NF12 is met automatically by the design.

Non-EDO mode.

EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 13), NF16/NF17 are different from the definition in non-EDO mode (Figure 12).

They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The

typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO

mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an

internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY(see the GPMI chapter

of the device reference manual. The typical value of this control register is 0x8 at 50 MT/s EDO mode.

However, if the board delay is large enough and cannot be ignored, the delay value should be made larger

to compensate the board delay.

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Electrical characteristics

4.9.2

GPMI Source Synchronous mode AC timing (ONFI 2.x compatible)

The following figure shows the write and read timing of Source Synchronous mode.

NF19

NF18

.!.$?#%?"

NF23

NAND_CLE

NF26

NF25

NF24

NAND_ALE

NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

Output enable

NF20

NF21

CMD

ADD

NAND_DATA[7:0]

Output enable

Figure 14. Source Synchronous Mode Command and Address Timing Diagram

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NF19

NF18

.!.$?#%ꢀ?"

.!.$?#,%

NF23

NF24

NF25

NF26

.!.$?!,%

NAND_WE/RE_B

NF22

.!.$?#,+

.!.$?$13

NF27

.!.$?$13

Output enable

NF29

.!.$?$1;ꢁꢂꢀ=

NF28

.!.$?$1;ꢁꢂꢀ=

Output enable

Figure 15. Source Synchronous Mode Data Write Timing Diagram

NF18

NF19

.!.$?#%?"

.!.$?#,%

NF24

NF23

NF26

NF25

NAND_ALE

NF25

.!.$?7%ꢃ2%

NF25

NF22

NF26

.!.$?#,+

.!.$?$13

/UTPUT ENABLE

.!.$?$!4!;ꢁꢂꢀ=

/UTPUT ENABLE

Figure 16. Source Synchronous Mode Data Read Timing Diagram

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.!.$?$13

NF30

.!.$?$!4!;ꢁꢂꢀ=

D0

D1

D2

D3

NF30

NF31

Figure 17. NAND_DQS/NAND_DQ Read Valid Window

1

Table 56. Source Synchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

2

NF18 NAND_CEx_B access time

NF19 NAND_CEx_B hold time

tCE

tCH

CE_DELAY × T - 0.79 [see ]

0.5 × tCK - 0.63 [see ²]

0.5 × tCK - 0.05

ns

—

NF20 Command/address NAND_DATAxx setup time

NF21 Command/address NAND_DATAxx hold time

NF22 clock period

tCAS

tCAH

tCK

0.5 × tCK - 1.23

—

NF23 preamble delay

tPRE

tPOST

tCALS

tCALH

tDQSS

tDS

PRE_DELAY × T - 0.29 [see ²]

POST_DELAY × T - 0.78 [see ²]

0.5 × tCK - 0.86

NF24 postamble delay

NF25 NAND_CLE and NAND_ALE setup time

NF26 NAND_CLE and NAND_ALE hold time

NF27 NAND_CLK to first NAND_DQS latching transition

NF28 Data write setup

0.5 × tCK - 0.37

T - 0.41 [see ²]

0.25 × tCK - 0.35

NF29 Data write hold

tDH

0.25 × tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

tDQSQ

tQHS

—

2.06

1.95

1

The GPMI source synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing

depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

2

T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

Figure 17 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source

Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s.

GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal,

which can be provided by an internal DPLL. The delay value can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference

manual. Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle

delay expected. However, if the board delay is large enough and cannot be ignored, the delay value should

be made larger to compensate the board delay.

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4.9.3

ONFI NV-DDR2 mode (ONFI 3.2 compatible)

Command and address timing

4.9.3.1

ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.

See Section 4.9.1, “GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)",” for details.

4.9.3.2

Read and write timing

ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, “Toggle

mode AC Timing",” for details.

4.9.4

Toggle mode AC Timing

4.9.4.1

Command and address timing

NOTE

Toggle mode command and address timing is the same as ONFI 1.0

compatible Asynchronous mode AC timing. See Section 4.9.1, “GPMI

Asynchronous mode AC timing (ONFI 1.0 compatible)",” for details.

4.9.4.2

Read and write timing

Figure 18. Toggle mode data write timing

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DEV?CLK

.!.$?#%X?"

.& ꢄꢅ

.!.$?#,%

.!.$?!,%

ꢄ T #+

ꢄ

.&ꢆꢈ

.!.$?7%?"

.!.$?2%?"

ꢄ T #+

.& ꢆꢇ

ꢄ T #+

.!.$?$13

.!.$?$!4!;ꢁꢂꢀ=

Figure 19. Toggle mode data read timing

1

Table 57. Toggle mode timing parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF1 NAND_CLE setup time

NF2 NAND_CLE hold time

tCLS

tCLH

tCS

(AS + DS) × T - 0.12 [see note²s^,3]

DH × T - 0.72 [see note²]

(AS + DS) × T - 0.58 [see notes^,2]

DH × T - 1 [see note²]

NF3 NAND_CE0_B setup time

NF4 NAND_CE0_B hold time

NF5 NAND_WE_B pulse width

NF6 NAND_ALE setup time

NF7 NAND_ALE hold time

tCH

tWP

tALS

tALH

tCAS

tCAH

tCE

DS × T [see note²]

(AS + DS) × T - 0.49 [see notes^,2]

DH × T - 0.42 [see note²]

DS × T - 0.26 [see note²]

DH × T - 1.37 [see note²]

NF8 Command/address NAND_DATAxx setup time

NF9 Command/address NAND_DATAxx hold time

NF18 NAND_CEx_B access time

NF22 clock period

CE_DELAY × T [see notes^4,2

]

—

ns

tCK

—

NF23 preamble delay

tPRE PRE_DELAY × T [see notes^5,2

]

NF24 postamble delay

tPOST

POST_DELAY × T +0.43 [see

note²]

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1

Table 57. Toggle mode timing parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF28 Data write setup

tDS⁶

tDH⁶

0.25 × tCK - 0.32

—

ns

NF29 Data write hold

0.25 × tCK - 0.79

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

tDQSQ⁷

tQHS⁷

—

3.18

3.27

1

The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

AS minimum value can be 0, while DS/DH minimum value is 1.

T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).

CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

5

6

7

PRE_DELAY+1) ≥ (AS+DS)

Shown in Figure 18.

Shown in Figure 19.

For DDR Toggle mode, Figure 19 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will

sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference

manual. Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected.

But if the board delay is big enough and cannot be ignored, the delay value should be made larger to

compensate the board delay.

4.10 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.10.1 LPSPI timing parameters

All LPSPI interfaces do not have the same maximum serial clock frequency. There are two groups. LPSPI

interfaces which can operate at 60 MHz in Master mode and 40 MHz in Slave mode and the other group

where interfaces operate at 40 MHz in Master mode and 20 MHz in Slave mode. The same performance

is achieved at 1.8 V and 3.3 V unless otherwise stated.

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Below are the LPSPI interfaces and their respective chip selects:

Table 58. LPSPI interfaces and chip selects

LPSPI interface

Chip select

Comment

60 MHz in Master mode and 40 MHz in SPI0, SPI2, SPI2b, SPI3

Slave mode

SPI2 - default SPI2 balls

SPI2b - muxed behind audio balls

40 MHz in Master mode and 20 MHz in SPI1, SPI1b, SPI2c

Slave mode

SPI1 - muxed behind SAI balls

SPI1b - muxed behind CSI balls

SP2c - muxed behind uSDHC1 balls

4.10.1.1 LPSPI Master mode

Waveform is assuming LPSPI is configured in mode 0, i.e. TCR.CPOL=0b0 and TCR.CPHA=0b0. Timing

parameters are valid for all modes using appropriate edge of the clock.

Figure 20. LPSPI Master mode

Table 59. LPSPI timings—Master mode at 60 MHz

ID

Parameter

SPIx_SCLK Cycle frequency

Min

Max

Unit

—

60

—

MHz

ns

t1 SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

7.5

t2 SPIx_CSy pulse width

t3 SPIx_CSy Lead Time⁽¹⁾

7.5

—

ns

FCLK_PERIOD⁽²⁾x (PCSSCK

+ 1) / 2^PRESCALE- 3

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Table 59. LPSPI timings—Master mode at 60 MHz (continued)

ID

Parameter

Min

Max

Unit

t4 SPIx_CSy Lag Time⁽³⁾

FCLK_PERIOD⁽²⁾x (SCKPCS

+ 1) / 2^PRESCALE+ 3

—

ns

t5 SPIx_SDO output Delay (CLOAD = 20 pF)

t6 SPIx_SDI Setup Time

—

2

3

ns

—

t7 SPIx_SDI Hold Time

2

1

2

3

This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers.

FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz.

This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.

Table 60. LPSPI timings—Master mode at 40 MHz

ID

Parameter

SPIx_SCLK Cycle frequency

Min

Max

Unit

—

11

40

—

MHz

ns

t1 SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

t2 SPIx_CSy pulse width

t3 SPIx_CSy Lead Time⁽¹⁾

11

—

ns

FCLK_PERIOD⁽²⁾x (PCSSCK

+ 1) / 2^PRESCALE+ 3

t4 SPIx_CSy Lag Time⁽³⁾

FCLK_PERIOD⁽²⁾x (SCKPCS

+ 1) / 2^PRESCALE+ 3

—

ns

t5 SPIx_SDO output Delay (CLOAD = 20 pF)

t6 SPIx_SDI Setup Time

—

5

ns

—

t7 SPIx_SDI Hold Time

4

1

2

3

This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers.

FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz.

This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.

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Figure 21. LPSPI Slave mode

Table 61. LPSPI timings—Slave mode at 40 MHz

Parameter

ID

Min

Max

Unit

—

t1

SPIx_SCLK Cycle frequency

SPIx_SCLK High or Low Time–Read

—

11

40

—

MHz

ns

SPIx_SCLK High or Low Time–Write

t2

t3

t4

t5

t6

t7

SPIx_CSy pulse width

11

4

—

5

ns

SPIx_CSy Lead Time (CS setup time)

SPIx_CSy Lag Time (CS hold time)

SPIx_SDO output Delay (CLOAD = 20 pF)

SPIx_SDI Setup Time

2

—

2

—

SPIx_SDI Hold Time

2

Table 62. LPSPI timings—Slave mode at 20 MHz

Parameter

ID

Min

Max

Unit

—

t1

SPIx_SCLK Cycle frequency

—

20

—

MHz

ns

SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

22

t2

t3

SPIx_CSy pulse width

22

4

—

ns

SPIx_CSy Lead Time (CS setup time)

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Table 62. LPSPI timings—Slave mode at 20 MHz (continued)

ID

Parameter

Min

Max

Unit

t4

t5

t6

t7

SPIx_CSy Lag Time (CS hold time)

2

—

2

—

18

—

ns

SPIx_SDO output Delay (CLOAD = 20 pF)

SPIx_SDI Setup Time

SPIx_SDI Hold Time

2

4.10.2 Serial audio interface (SAI) timing parameters

The timings and figures in this section are valid for noninverted clock polarity (I2S_TCR2.BCP = 0b0,

I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity (I2S_TCR4.FSP = 0b0, I2S_RCR4.FSP =

0b0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by

inverting the clock signal (SAI_TXC / SAI_RXC) and/or the frame sync (SAI_TXFS / SAI_RXFS) shown

in the figures below.

The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated.

NOTE

SAI0 and SAI1 are transmit/receive capable. SAI2 and SAI3 are receive

only.

4.10.2.1 SAI Master Synchronous mode

In this mode, transmitter clock and frame sync are used by both transmitter and receiver

(I2S_TCR2.SYNC=0b00, I2S_RCR2.SYNC=0b01). In that case, SAI interface requires only 4 signals to

be routed: SAI_TXC, SAI_TXFS, SAI_TXD and SAI_RXD. SAI_RXC and SAI_RXFS can be left

unconnected. I2S_RCR2.BCI shall be set to 0b1 to get setup and hold times provided in Table 63.

Figure 22. SAI Master Synchronous mode

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Electrical characteristics

Table 63. SAI timings—Master Synchronous mode

ID

Parameters

Min

Max

Unit

—

SAI TXC clock frequency

—

45%

—

49.152

MHz

t1 SAI TXC pulse width low / high

t2 SAI TXFS output valid

t3 SAI TXD output valid

t4 SAI RXD input setup

t5 SAI RXD input hold

55%

2

SAI_TXC period

ns

—

2

1

—

4

4.10.2.2 SAI Master mode

In this mode, transmitter and/or receiver part are set to bring out transmit and/or receive clock. Frame sync

can be either input or output.

Figure 23. SAI Master mode

Table 64. SAI timings—Master mode

ID

Parameters

SAI TXC / RXC clock frequency¹

Min

Max

Unit

—

45%

—

49.152

55%

2

MHz

TXC/RXC period

ns

t1 SAI TXC / RXC pulse width low / high

t2 SAI TXFS / RXFS output valid

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Unit

Table 64. SAI timings—Master mode (continued)

ID

Parameters

Min

Max

t3 SAI TXD output valid

—

6

2

ns

t4 SAI RXD/RXFS/TXFS input setup

t5 SAI RXD/RXFS/TXFS input hold

—

0

1

Given the high setup time requirement on inputs, receiver and transmitter, when using frame sync in input, are likely to run at

a lower frequency. This frequency will be driven by characteristics of the external component connected to the interface.

4.10.2.3 SAI Slave mode

In this mode, transmitter and/or receiver parts are set to receive transmit and/or receive clock from external

world. Frame sync can be either input or output.

Figure 24. SAI Slave mode

Table 65. SAI timings—Slave mode

ID

Parameters

SAI TXC/RXC clock frequency

Min

Max

Unit

—

45%

—

24.576

55%

13

MHz

t11 SAI TXC/RXC pulse width low/high

t12 SAI TXFS/RXFS output valid

t13 SAI TXD output valid

TXC/RXC period

ns

—

13

t14 SAI RXD/RXFS/TXFS input setup

t15 SAI RXD/RXFS/TXFS input hold

1

—

4

—

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4.10.3 Enhanced serial audio interface (ESAI)

The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated.

SCKT

t1

(Input / Output)

FST (bit) out

2t

FST (word) out

Data Out

2t

Last bit

First bit

t3

4t

t4

FST (bit) in

FST (word) in

Flags Out

t5

t6

t5

t6

t7

Figure 25. ESAI Transmit timing

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Figure 26. ESAI Receive timing

The following table shows the interface timing values. The ID field in the table refers to timing signals

found in Figure 25 and Figure 26.

Table 66. Enhanced Serial Audio Interface (ESAI) Timing

ID

Parameters

Min

Max

Condition¹

Unit

—

t1

t2

Clock frequency

SCKT / SCKT pulse width high / low

FST output delay

—

45%

—

24.576

55%

—

MHz

SCKT / SCKR period

ns

10

2

x ck

i ck

t3

t4

t5

t6

t7

TX data - high impedance / valid data

TX data output delay

—

9

1

x ck

i ck

ns

10

2

x ck

i ck

FST - setup requirement

FST - hold requirement

Flag output delay

2

10

x ck

i ck

2

0

x ck

i ck

10

2

x ck

i ck

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Table 66. Enhanced Serial Audio Interface (ESAI) Timing (continued)

ID

Parameters

Min

Max

Condition¹

Unit

t8

FSR output delay

7

4

x ck

i ck a

ns

t9

RX data pins - setup requirement

RX data pins - hold requirement

FSR - setup requirement

2

10

—

x ck

i ck

ns

t10

t11

t12

t13

t14

2

0

x ck

i ck

2

10

x ck

i ck a

FSR - hold requirement

2

0

x ck

i ck a

Flags - setup requirement

Flags - hold requirement

2

10

x ck

i ck s

2

0

x ck

i ck s

—

RX_HF_CLK / TX_HX_CLK clock cycle

TX_HF_CLK input to SCKT

20

—

10

—

ns

RX_HF_CLK input to SCKR

1

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock)

4.10.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

Timing

This section describes the electrical information of the uSDHC, including:

•

SD3.1/eMMC5.1 High-Speed mode AC Timing

eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing

HS400 AC timing—eMMC 5.1 only

HS200 Mode Timing

SDR50/SDR104 AC Timing

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4.10.4.1 SD3.1/eMMC5.1 High-Speed mode AC Timing

The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 67 lists the

timing characteristics.

SD4

SD2

SD1

SD5

SDx_CLK

SD3

SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7

SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 27. SD3.1/eMMC5.1 High-Speed mode Timing

Table 67. SD3.1/eMMC5.1 High-Speed mode interface timing specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1

Clock Frequency (Low Speed)

f_PP

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

2

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

Clock Low Time

f_PP

3

f_PP

0

f_OD

t_WL

100

7

SD2

SD3

SD4

SD5

Clock High Time

t_WH

t_TLH

t_THL

7

—

ns

Clock Rise Time

—

3

ns

Clock Fall Time

3

ns

eSDHC Output/Card Inputs SD_CMD, SD_DATA (Reference to SD_CLK)

eSDHC Output Delay t_OD–6.6

eSDHC Input/Card Outputs SD_CMD, SD_DATA (Reference to SD_CLK)

SD6

3.6

ns

SD7

SD8

eSDHC Input Setup Time

eSDHC Input Hold Time⁴

t_ISU

t_IH

2.5

1.5

—

ns

1

2

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

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3

In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

4

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.10.4.2 eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing

The following figure depicts the timing of eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode, and Table 68

lists the timing characteristics. Be aware that only SDx_DATA is sampled on both edges of the clock (not

applicable to SD_CMD).

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card

SDx_DATA[7:0]

......

SD3

SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

Figure 28. eMMC 5.1 timing

Figure 29. eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode interface timing

Table 68. eMMC5.1 DDR 52 mode/SD3.150 mode interface timing specification

ID

Parameter

Symbols

Card Input Clock¹

Min

Max

Unit

SD1

Clock Frequency (eMMC5.1 DDR)

Clock Frequency (SD3.1 DDR)

f_PP

0

52

50

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

uSDHC Output Delay t_OD2.8

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

6.8

ns

SD3

SD4

uSDHC Input Setup Time

uSDHC Input Hold Time

t_ISU

t_IH

1.7

1.5

—

ns

1

Clock duty cycle will be in the range of 47% to 53%.

4.10.4.3 HS400 AC timing—eMMC 5.1 only

Figure 30 depicts the timing of HS400. Table 69 lists the HS400 timing characteristics. Be aware that only

data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for

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HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7

parameters in Table 71 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for

HS400 mode.

Figure 30. HS400 timing

Table 69. HS400 interface timing specifications

ID

Parameter

Symbols

Min

Max

Unit

Card Input clock

SD1

Clock Frequency

fPP

t_CL

0

200

Mhz

ns

SD2

SD3

Clock Low Time

Clock High Time

0.46 × t_CLK

0.54 × t_CLK

t_CH

ns

uSDHC Output/Card inputs DAT (Reference to SCK)

SD4

SD5

Output Skew from Data of

Edge of SCK

t_OSkew1

0.45

—

ns

Output Skew from Edge of

SCK to Data

t_OSkew2

uSDHC input/Card Outputs DAT (Reference to Strobe)

SD6

SD7

uSDHC input skew

uSDHC hold skew

t_RQ

—

0.45

ns

t_RQH

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4.10.4.4 HS200 Mode Timing

The following figure depicts the timing of HS200 mode, and Table 70 lists the HS200 timing

characteristics.

SD1

SD2

SD3

SD7

SCK

SD4/SD5

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD6

SD8

Figure 31. HS200 Mode Timing

Table 70. HS200 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

SD2

Clock Frequency Period

Clock Low Time

t_CLK

t_CL

5.0

—

ns

0.46 × t_CLK

0.54 × t_CLK

Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

uSDHC Output Delay t_OD–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)¹

Card Output Data Window t_ODW0.5*t_CLK

1

ns

SD5

—

SD8

¹HS200 is for 8 bits while SDR104 is for 4 bits.

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4.10.4.5 SDR50/SDR104 AC Timing

The following figure depicts the timing of SDR50/SDR104, and Table 71 lists the SDR50/SDR104 timing

characteristics.

SD1

SD2

SD3

SCK

SD5

SD4

Output from uSDHC to card

SD7

SD6

Input from card to uSDHC

SD8

Figure 32. SDR50/SDR104 timing

Table 71. SDR50/SDR104 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

4.8

—

ns

0.46 × t_CLK

0.54 × t_CLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

SD4 uSDHC Output Delay t_OD–3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)

uSDHC Output Delay t_OD–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

1

ns

1

SD5

uSDHC Input Setup Time

uSDHC Input Hold Time

t_ISU

t_IH

2.5

1.5

—

ns

SD6

SD7

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)¹

Card Output Data Window t_ODW0.5 × t_CLK

—

ns

SD8

1

Data window in SDR100 mode is variable.

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4.10.4.6 Bus Operation Condition for 3.3 V and 1.8 V Signaling

The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those

shown in “,” and Table 31, "Dual-voltage 1.8 V GPIO DC parameters," on page 37Table 32,

"Dual-voltage 3.3 V GPIO DC parameters," on page 38.

4.10.5 Ethernet Controller (ENET) AC Electrical Specifications

ENET interface supporting RGMII protocol in delay and non-delay mode. RGMII is used to support up to

1000 Mbps Ethernet as well as RMII protocol. RMII is used to support up to 100 Mbps Ethernet.

NOTE

Both ENET0 and ENET1 support RGMII at 1.8 V and 2.5 V, and RMII at

3.3 V.

Table 72. RGMII/RMII pin mapping

Pin name¹

RGMII

RGMII_TXC

RMII

Comment²

ENETx_RGMII_TXC

RCLK50M

RCLK50M can be an input or

an output. It's using different

Alternate pin muxing modes.

Refer to pin muxing for details.

ENETx_RGMII_TX_CTL

ENETx_RGMII_TXD0

ENETx_RGMII_TXD1

ENETx_RGMII_TXD2

ENETx_RGMII_TXD3

ENETx_RGMII_RXC

ENETx_RGMII_RX_CTL

ENETx_RGMII_RXD0

ENETx_RGMII_RXD1

ENETx_RGMII_RXD2

RGMII_TX_CTL

RGMII_TXD0

RGMII_TXD1

RGMII_TXD2

RGMII_TXD3

RGMII_RXC

RMII_TXEN

RMII_TXD0

RMII_TXD1

N/A

—

N/A

RGMII_RX_CTL

RGMII_RXD0

RGMII_RXD1

RGMII_RXD2

RMII_CRS_DV

RMII_RXD0

RMII_RXD1

RMII_RXER

RMII_RXER is mapped on

ALT1 mode of pin muxing.

ENETx_RGMII_RXD3

RGMII_RXD3

N/A

—

ENETx_REFCLK_125M_25M RGMII_REF_CLK

RGMII_REF_CLK is optional

for RGMII operation and

dependent on the intended

clock configuration.

ENETx_MDIO

ENETx_MDC

RGMII_MDIO

RGMII_MDC

RMII_MDIO

RMII_MDC

—

1

x can be 0 or 1.

2

Except for RCLK50M and RMII_RXER, all other RMII functions are using the same pin muxing mode as RGMII.

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4.10.5.1 RGMII

4.10.5.1.1 No-Internal-Delay mode

This mode corresponds to the RGMIIv1.3 specification.

Figure 33. RGMII timing diagram—No-Internal-Delay mode

Table 73. RGMII timings—No-Internal-Delay mode

ID

Parameter

Min

Typ

Max

Unit

TXC / RXC frequency

Clock cycle

—

7.2

-500

1

125

8

—

8.8

500

2.6

MHz

ns

t1

t2

t3

Data to clock output skew

—

ps

Data to clock input skew¹⁽¹⁾

ns

1

This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and

less than 2.0 ns is added to the associated clock signal.

4.10.5.1.2 Internal-delay mode

This mode corresponds to RGMIIv2.0 specification.

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Figure 34. RGMII timing diagram—Internal-Delay mode

Table 74. RGMII timing—Internal-Delay mode

ID

Parameter

Min

Typ

Max

Unit

TXC / RXC frequency

—

7.2

1.2

0

125

8

—

8.8

—

MHz

ns

t1

t2

t3

t4

t5

Clock cycle

TXD setup time

TXD hold time

RXD setup time

RXD hold time

—

ns

2.5

ns

4.10.5.2 RMII

RMII interface is matching RMII v1.2 specification. In RMII mode, the reference clock can be generated

internally and provided to the PHYthrough RCLK50M_OUT. Or, it come from and external 50MHz clock

generator which is connected to the PHY and to i.MX8 through RCLK50M_IN pin.

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Figure 35. RMII timing diagram

Timings in table below are covering both cases: reference clock generated internally or externally.

Table 75. RMII timing

ID

Parameter

Min

Typ

Max

Unit

t1

Reference clock

—

35

2

50

—

50

65

12

—

MHz

ppm

%

Reference clock accuracy

Reference clock duty-cycle

t2

t3

t4

RMII_TXEN, RMII_TXD output delay

RMII_CRS_DV, RMII_RXD setup time

RMII_CRS_DV, RMII_RXD hold time

ns

4

ns

2

ns

4.10.5.3 MDIO

MDIO is the control link used to configure Ethernet PHY connected to i.MX8 device.

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Figure 36. MDIO timing diagram

Table 76. MDIO timing

ID

Parameter

Min

Typ

Max

Unit

MDC frequency

—

180

0

2.5

—

20

—

MHz

%

t1

t2

t3

t4

MDC high / low pulse width

MDIO output delay

MDIO setup time

MDIO hold time

ns

10

ns

4.10.6 CAN network AC Electrical Specifications

The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing

the CAN protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B

protocol specification. The processor has three CAN modules available for systems design. Tx and Rx

ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the device

reference manual to see which pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and

FLEXCAN_RX, respectively.

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4.10.7 I²C Module Timing Parameters

2

This section describes the timing parameters of the I C module. The following figure depicts the timing

2

of the I C module, and Table 77 lists the I C module timing characteristics.

I2Cx_SDA

I2Cx_SCL

IC11

IC9

IC10

IC7

IC4

IC2

IC3

IC8

IC10b

IC6

IC11b

STOP

START

IC5

IC1

2

Figure 37. I C bus timing

2

Table 77. I C Module Timing Parameters

Standard Mode

Fast Mode

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

I2Cx_SCL cycle time

10

4.0

0¹

—

2.5

0.6

0¹

—

µs

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

—

3.45²

—

0.9²µs

HIGH Period of I2Cx_SCL Clock

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

4.0

4.7

250

4.7

—

0.6

1.3

0.6

—

µs

ns

µs

—

100³

1.3

Bus free time between a STOP and START condition

—

4

IC10/IC10b Rise time of both I2Cx_SDA and I2Cx_SCL signals

IC11/IC11b Fall time of both I2Cx_SDA and I2Cx_SCL signals

1000

300

400

20 + 0.1C_b300 ns

4

—

20 + 0.1C_b300 ns

IC12

Capacitive load for each bus line (C_b)

—

400 pF

1

A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal in order to bridge the undefined region of

the falling edge of I2Cx_SCL.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.

If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the I2Cx_SCL line is released.

4

C_b= total capacitance of one bus line in pF.

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Table 78. I2C timing

Fast Mode Plus

Min

High Speed¹

Min Max

Unit

ID

Parameter

SCL clock frequency

Max

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

—

1

—

160

0

3.4

—

70

—

MHz

ns

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

260

0

—

ns

HIGH Period of I2Cx_SCL Clock

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

260

500

260

50

60

ns

160

10

ns

Bus free time between a STOP and START

condition

500

150

ns

IC10 Rise time of I2Cx_SDA signals

IC11 Fall time of I2Cx_SDA signals

—

120

10

80

ns

12 (@3.3 V)

6.5 (@1.8 V)

IC10b Rise time of I2Cx_SCL signals

IC11b Fall time of I2Cx_SCL signals

—

120

10

40

ns

12 (@3.3 V)

6.5 (@1.8 V)

IC12 Capacitive load for each bus line (Cb)

—

550

—

100

pF

1

High-speed mode is only available for I2C modules in DMA, SCU and Cortex-M4 subsystems.

4.10.8 MIPI-DSI/LVDS combo display output specifications

The physical pins of the combo display output controller can be used in LVDS mode or in DSI display

mode.

4.10.8.1 MIPI-DSI/LVDS display bridge module parameters

Maximum frequency support for combination MIPI-DSI/LVDS modules:

Table 79. MIPI-DSI/LVDS combo pins

Function^1,2

DSI

Channel A

DSI up to 1.05 Gb/per lane

Channel B

DSI up to 1.05 Gb/per lane

Mix

4 pairs LVDS up to 1.05 Gb per pair

DSI up to 1.05 Gb/per lane

4 pairs LVDS up to 1.05 Gb per pair

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Table 79. MIPI-DSI/LVDS combo pins (continued)

Channel A

Function^1,2

Channel B

LVDS (single

channel)

4 pairs LVDS up to 1.05 Gb per pair

LVDS (dual

channel)

8 pairs LVDS up to 595 Mb per pair

1

For DSI the maximum clock speed is 1.05 GHz.

2

For LVDS in single-channel operation the maximum clock speed is 150 MHz; in dual-channel operation with a single

synchronized clock the maximum clock speed is 85 MHz.

4.10.8.2 LVDS display bridge (LDB) module electrical specifications

The MIPI DSI/LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see

TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS)

Interface Circuits.”

Table 80. LVDS Display Bridge (LDB) Electrical Specifications

Parameter

Symbol

Test Condition

100 Ω Differential load

Min

Max

Units

Differential Voltage Output Voltage

Output Voltage High

V_OD

Voh

0.25

—

0.4

V

100 Ω differential load

(0 V Diff—Output High Voltage static)

1.475

Output Voltage Low

Offset Static Voltage

Vol

100 Ω differential load

0.925

1.125

—

V

(0 V Diff—Output Low Voltage static)

V_OS

Two 49.9 Ω resistors in series between

N-P terminal, with output in either Zero or

One state, the voltage measured between

the 2 resistors.

1.275

VOS Differential

V_OSDIFF

Difference in V_OSbetween a One and a

Zero state

—

mV

Output short-circuited to GND

Output short current

ISA ISB

ISAB

With the output common shorted to GND

—

40

12

mA

4.10.8.3 MIPI-DSI HS-TX specifications

Table 81. MIPI high-speed transmitter DC specifications

Parameter

Symbol

Min Typ Max

Unit

1

V_CMTX

High Speed Transmit Static Common Mode Voltage

V_CMTXmismatch when Output is Differential-1 or Differential-0

High Speed Transmit Differential Voltage

150 200

250

5

mV

|ΔV_{CMTX (1,0)}

|

—

1

|V_OD

|

140 200

270

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Table 81. MIPI high-speed transmitter DC specifications (continued)

Symbol

|ΔV_OD

Parameter

Min Typ Max

Unit

|

V_ODmismatch when Output is Differential-1 or Differential-0

High Speed Output High Voltage

—

40

—

50

—

10

360

62.5

10

mV

Ω

1

V_OHHS

Z_OS

Single Ended Output Impedance

ΔZ_OS

Single Ended Output Impedance Mismatch

%

1

Value when driving into load impedance anywhere in the Z_IDrange.

Table 82. MIPI high-speed transmitter AC specifications

Symbol

Parameter

Min

Typ

Max

Unit

ΔV_CMTX(HF)

ΔV_CMTX(LF)

Common-level variations above 450 MHz

Common-level variation between 50-450 MHz

Rise Time and Fall Time (20% to 80%)

—

15

25

mVRMS

mVPEAK

ps

1

t_Rand t_F

100

0.35 UI

1

UI is the long-term average unit interval.

4.10.8.4 MIPI-DSI LP-TX specifications

Table 83. MIPI low-power transmitter DC specifications

Symbol

Parameter

Min

Typ

Max

Unit

1

V_OH

Thevenin Output High Level

Thevenin Output Low Level

1.1

–50

110

1.2

—

1.3

50

—

V

mV

Ω

V_OL

2

Z_OLP

Output Impedance of Low Power Transmitter

—

1

2

This specification can only be met when limiting the core supply variation from 1.1 V till 1.3 V.

Although there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification

is met.

Table 84. MIPI low-power transmitter AC specifications

Symbol

Parameter

Min Typ Max Unit

1

T_RLP/T_FLP

15% to 85% Rise Time and Fall Time

30% to 85% Rise Time and Fall Time

—

25

35

—

ns

1,2,3

T_REOT

4

T_LP-PULSE-TXPulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop 40

state or last pulse before Stop state

Pulse width of the LP exclusive-OR clock: All other pulses

Period of the LP exclusive-OR clock

20

90

—

ns

T_LP-PER-TX

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Table 84. MIPI low-power transmitter AC specifications (continued)

Parameter Min Typ Max Unit

Symbol

1,5,6,7

δV/δt_SR

Slew Rate @ CLOAD= 0 pF

Slew Rate @ CLOAD= 5 pF

Slew Rate @ C^LOAD= 20 pF

Slew Rate @ CLOAD= 70 pF

Load Capacitance

30

0

—

500 mV/ns

200 mV/ns

150 mV/ns

100 mV/ns

C_LOAD

70

pF

1

C_LOADincludes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <

10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay.

2

The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due

to stopping the differential drive.

3

4

With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane.

This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches

between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11)

is glitch behavior as described in Low-Power Receiver section.

5

6

7

When the output voltage is between 15% and below 85% of the fully settled LP signal levels.

Measured as average across any 50 mV segment of the output signal transition.

This value represents a corner point in a piecewise linear curve.

4.10.8.5 MIPI-DSI LP-RX specifications

Table 85. MIPI low power receiver DC specifications

Parameter Min

Symbol

V_IH

Typ

Max

Unit

Logic 1 input voltage

880

—

1.3

550

300

—

mV

V_IL

Logic 0 input voltage, not in ULP state

Logic 0 input voltage, ULP state

Input hysteresis

V_IL-ULPS

V_HYST

—

25

Table 86. MIPI low power receiver AC specifications

Symbol

Parameter

Min

Typ

Max

Unit

1,2

e_SPIKE

Input pulse rejection

—

20

—

300

—

V.ps

ns

3

T_MIN-RX

Minimum pulse width response

Peak Interference amplitude

Interference frequency

V_INT

—

200

—

mV

MHz

f_INT

450

1

2

3

Time-voltage integration of a spike above V_ILwhen in LP-0 state or below VIH when in LP-1 state.

An impulse below this value will not change the receiver state.

An input pulse greater than this value shall toggle the output.

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4.10.8.6 MIPI-DSI LP-CD specifications

Table 87. MIPI contention detector DC specifications

Parameter Min

Symbol

Typ

Max

Unit

V_IHCD

V_ILCD

Logic 1 contention threshold

Logic 0 contention threshold

450

—

mV

200

4.10.8.7 MIPI-DSI DC specifications

Table 88. MIPI input characteristics DC specifications

Symbol

V_PIN

Parameter

Min

Typ

Max

Unit

Pad signal voltage range

Pin leakage current

Ground shift

–50

–10

–50

–0.15

—

1350

10

mV

μA

mV

V

1

I_LEAK

V_GNDSH

50

2

V_PIN(absmax)

Maximum pin voltage level

1.45

20

3

T_VPIN(absmax)Maximum transient time above V_PIN(max)or below V_PIN(min)

ns

1

When the pad voltage is within the signal voltage range between V_GNDSH(min)to VOH + V_GNDSH(max)and the Lane Module is

in LP receive mode.

2

3

This value includes ground shift.

The voltage overshoot and undershoot beyond the V_PINis only allowed during a single 20 ns window after any LP-0 to LP-1

transition or vice versa. For all other situations it must stay within the V_PINrange.

4.10.9 PCIe 3.0 PHY Parameters

The TX and RX eye diagrams specifications are per the template shown in the following figure. The

summary of specifications is shown in Table 89 and Table 90. Note that the time closure (1–AOPENING)

in the eye templates needs not match jitter specifications in the Standards Specifications, as there are such

discrepancies in some Standards Specifications. The design meets the tightest of specifications in case of

discrepancy.

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Figure 38. TX and RX eye diagram template

Table 89. PCIe transmitter eye specifications for example standards

UI A_OPENINGB_OPENINGA_OPENINGB_OPENINGV_DIFFp-pmin V_DIFFp-pmax

ps

UI

ps

mV

PCI Express Gen 1 Transition Bit

PCI ExpressGen 1 De-emphasized Bit

PCI Express Gen 2 Transition Bit

PCI Express Gen 2 De-emphasized Bit

400

200

0.75

0

300

150

0

800

505

800

379

1200¹

757

1200¹

850

1

V_DIFFp-peye opening is limited to VDDIO under matched termination conditions.

Table 90. PCIe receiver eye specifications for example standards

UI A_OPENINGB_OPENINGA_OPENINGB_OPENINGV_DIFFp-pmin V_DIFFp-pmax

ps

UI

ps

mV

PCI Express Gen 1 Transition Bit

400

200

125

0.4

0

160

0

175

100

25

1200

1300

PCI Express Gen 2 Transition Bit

PCI Express Gen 3 Virtual EYE¹

0.3

38

1

PCIE 3.0 8 GT/s measured using PCIE reference equalizer + CDR per PCIE specification.

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Table 91. PCIe differential output driver characteristics (including board and load)

Parameter

Min

Typ

Max

Units

Notes

1

Output Rise and fall time T_R, T_F

175

—

350

20

50

—

ps

%

ps

ns

μs

Ω

1, 2

Output Rise/Fall matching

Output skewT_OSKEW

—

Initialization time from assertion of TXOE

Initialization time from assertion of TXENA

Transmission line characteristic impedance (Z_O)

100

—

10

—

50

—

Driver output impedance, single ended (small signal @

Vout=Vcm)

—

1000

—

Ω

Output single ended voltage (RS= 33, RT= 50 Ω)

3, 4

3

V_OH

0.65

-13

-0.20

0.71

-14.2

0.00

0.85

-17

0.05

V

mA

V

I_OH@ 6 * I_R

V_OL

Output common mode voltage (RS = 33, RT= 50 Ω)

|V_OCM

|

0.25

-0.015

-0.050

0.375

0.55

0.015

0.050

5

6

ΔV_{OCM (DC)}

ΔV_{OCM (AC)}

V

7,8

9

Buffer induced deterministic jitter (absolute, pk-pk)

Reference Buffer Dynamic Power (Digital)

Reference Buffer Dynamic Power (Analog)

Output Buffer Dynamic Power (Digital)

—

4

ps

μA

mA

μA

mA

0.015

2.8

0.66

3.14

1.8

9

0.035

18.9

9

Output Buffer Dynamic Power (Analog)

22.11

1

When the output is transitioning between logic 0 and logic 1, or logic 1 and logic 0, and driving a terminated

transmission line, the outputs monotonically transition between VOL and VOH, VOH, and VOL respectively. Target rise and

fall times observed at the receiver and are primarily set by board trace impedance and Load capacitance. Rise and fall

times are defined by 25% and 75% crossing points.

2

3

Calculated as: 2 × (TR–TF) / (TR+ TF)

I_Ris proportional to the reference current. Measured across RT. The primary contributor to output voltage spread is

VDD spread, and so a VDD tighter than ±10% may be required to achieve this spread.

4

Higher output voltages may occur depending on load, power supply, and selected output drive. Higher output voltages may

transiently occur during initialization period following TXENA assertion.

5

6

7

Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under DC conditions.

Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under AC conditions.

Measured under “clean power supply and ground” conditions, and after de-embedding the jitter of the input, measured over a

time span of 1000 cycles

8

9

Power supply induced jitter is included under this category, and the power supply variation is to be less than 8mVpp.

Note that customer has to be uncommonly careful with power supply fidelity due to the small jitter numbers.

Power consumption is simulated under the following conditions:

Typ: TT, VDD=1.0 V, VD18=1.8 V, 25 °C

Max: FF, VDD=1.1 V, VD18=1.98 V, 125 °C

Dynamic: TXENA=1, TXOE=1

Static: TXENA=0, TXOE=1

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4.10.9.1 PCIE_REXT reference resistor connection

The following figure shows the PCIE_REXT reference resistor connection.

Figure 39. PCIE_REXT reference resistor connection

4.10.9.2 PCIE_REF_CLK

Contact an NXP representative to obtain the hardware development guide for this device, which contains

details on the PCIe reference clock requirements.

4.10.10 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

The following figure depicts the timing of the PWM, and Table 92 lists the PWM timing parameters.

PWMn_OUT

Figure 40. PWM Timing

Table 92. PWM Output Timing Parameters

ID

Parameter

Min

Max

Unit

—

P1

P2

PWM Module Clock Frequency

PWM output pulse width high

PWM output pulse width low

0

ipg_clk

—

MHz

ns

15

—

ns

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4.10.11 LCD controller (LCDIF) parameters

Figure 41 shows the LCDIF timing, and the table below lists the timing parameters.

L1

L2

L3

LCDn_CLK

(falling edge capture)

LCDn_CLK

(rising edge capture)

LCDn_DATA[23:00]

LCDn Control Signals

L4

L5

L6

L7

Figure 41. LCD Timing

Table 93. LCD Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

L1

L2

L3

L4

L5

L6

L7

LCD pixel clock frequency

tCLK(LCD)

tCLKH(LCD)

tCLKL(LCD)

td(CLKH-DV)

td(CLKL-DV)

—

6

80

—

1

MHz

ns

LCD pixel clock high (falling edge capture)

LCD pixel clock low (rising edge capture)

6

ns

LCD pixel clock high to data valid (falling edge capture)

LCD pixel clock low to data valid (rising edge capture)

-1

ns

1

ns

LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV)

LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV)

1

ns

1

ns

4.10.11.1 LCDIF signal mapping

The table below lists the details about the mapping signals.

Table 94. LCD Signal Parameters

8-bit DOTCLK LCD 16-bit DOTCLK LCD 18-bit DOTCLK LCD 24-bit DOTCLK LCD 8-bit DVI LCD

Pin name

IF

LCD_RS

—

CCIR_CLK

—

LCD_VSYNC*

(Two options)

LCD_VSYNC

LCD_HSYNC

—

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Table 94. LCD Signal Parameters (continued)

LCD_DOTCLK

LCD_ENABLE

LCD_D23

LCD_D22

LCD_D21

LCD_D20

LCD_D19

LCD_D18

LCD_D17

LCD_D16

LCD_DOTCLK

—

LCD_ENABLE

R[7]

—

R[6]

—

R[5]

—

R[4]

—

R[3]

—

R[2]

—

R[5]

R[4]

R[3]

R[1]

—

R[0]

LCD_D15 /

VSYNC*

R[4]

G[7]

LCD_D14 /

HSYNC**

—

R[3]

R[2]

R[1]

G[6]

G[5]

—

LCD_D13 /

LCD_DOTCLK

**

R21]

LCD_D12 /

ENABLE**

—

R[1]

R[0]

G[4]

—

LCD_D11

LCD_D10

LCD_D9

LCD_D8

LCD_D7

LCD_D6

LCD_D5

LCD_D4

LCD_D3

LCD_D2

LCD_D1

LCD_D0

LCD_RESET

—

R[0]

G[5]

G[4]

G[3]

G[2]

—

G[4]

G[3]

G[1]

—

G[3]

G[2]

G[0]

—

G[3]

G[2]

G[0]

—

R[2]

R[1]

R[0]

G[2]

G[1]

G[0]

B[1]

G[2]

G[1]

B[7]

Y/C[7]

Y/C[6]

Y/C[5]

Y/C[4]

Y/C[3]

Y/C[2]

Y/C[1]

Y/C[0]

—

G[1]

G[0]

B[6]

G[0]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

LCD_RESET

LCD_BUSY /

LCD_VSYNC

LCD_BUSY (or

optional

LCD_BUSY (or

optional LCD_VSYNC)

LCD_BUSY (or

optional

LCD_BUSY (or

optional

—

LCD_VSYNC)

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4.10.12 FlexSPI (Quad SPI/Octal SPI) timing parameters

The FlexSPI interface can work in SDR or DDR modes. It can operate up to 60 MHz at 3.3 V, 166 MHz

at 1.8 V SDR mode or 200 MHz at 1.8 V DDR mode. It supports single-ended and differential DQS

signaling.

FlexSPI supports the following clocking scheme for a read data path:

•

Dummy read strobe generated by FlexSPI controller and looped back internally

(FlexSPIn_MCR0[RXCLKSRC] = 0x0)

Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x1). It means the I/O cannot be used for another feature.

Read strobe provided by memory device and input from DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x3)

4.10.12.1 SDR mode

4.10.12.1.1 SDR mode timing diagrams

The following write timing diagram is valid for any FlexSPIn_MCR0[RXCLKSRC] value.

Figure 42. FlexSPI write timing diagram (SDR mode)

The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1.

Figure 43. FlexSPI read timing diagram (SDR mode)

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The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x3.

Figure 44. FlexSPI read with DQS timing diagram (SDR mode)

4.10.12.1.2 SDR mode timing parameter tables

Table 95. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (SDR mode)

ID

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

60

—

1

MHz

ns

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

7.5

1

SCLK

ns

t3 QSPIx[A/B]_SSy_B Lead Time¹

TCSS+0.5

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH

t5 QSPIx[A/B]_DATAy output Delay

t6 QSPIx[A/B]_DATAy Setup Time

—

6

—

ns

t7 QSPIx[A/B]_DATAy Hold Time

0

ns

1

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 96. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (SDR mode)

ID

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

166

—

1

MHz

ns

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

t3 QSPIx[A/B]_SSy_B Lead Time¹

t4 QSPIx[A/B]_SSy_B Lag Time¹

t5 QSPIx[A/B]_DATAy output Delay

t6 QSPIx[A/B]_DATAy Setup Time

t7 QSPIx[A/B]_DATAy Hold Time

2.7

1

SCLK

ns

TCSS+0.5

TCSH

—

1

—

ns

2

ns

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1

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 97. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (SDR mode)

ID

Parameter

QSPIx[A/B]_DQS Cycle frequency

Min

Max

Unit

—

2.25

200

—

MHz

ns

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width¹

t3 QSPIx[A/B]_SSy_B Lead Time²

t4 QSPIx[A/B]_SSy_B Lag Time²

CSINTERVAL

TCSS+0.5

TCSH

—

SCLK

ns

—

t5 QSPIx[A/B]_DATAy output Delay

t8 QSPIx[A/B]_DQS / QSPIx[A/B]_DATAy delta

—

1

-0.65

0.65

ns

1

2

Minimum is 2 SCLK cycles even if CSINTERVAL value is less than 2.

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

4.10.12.2 DDR mode

4.10.12.2.1 DDR mode timing diagrams

Figure 45. FlexSPI write timing diagram (DDR mode)

Figure 46. FlexSPI read timing diagram (DDR mode)

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QSPIx[A/B]_DQS

QSPIx[A/B]_DATAy

t9

t10

Figure 47. FlexSPI read with DQS timing diagram (DDR mode)

Table 98. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode)

ID

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

30

—

MHz

ns

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

15

1

SCLK

ns

t3 QSPIx[A/B]_SSy_B Lead Time¹

(TCSS+0.5)/2

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH/2

t5 QSPIx[A/B]_DATAy output valid time

t6 QSPIx[A/B]_DATAy output hold time

t7 QSPIx[A/B]_DATAy Setup Time

6.5

6

ns

t8 QSPIx[A/B]_DATAy Hold Time

0

ns

1

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 99. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (DDR mode)

ID

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

83

—

MHz

ns

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

5.4

1

SCLK

ns

t3 QSPIx[A/B]_SSy_B Lead Time¹

(TCSS+0.5)/2

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH/2

t5 QSPIx[A/B]_DATAy output valid time

t6 QSPIx[A/B]_DATAy output hold time

t7 QSPIx[A/B]_DATAy Setup Time

2

1

ns

t8 QSPIx[A/B]_DATAy Hold Time

ns

1

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

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Table 100. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode)

ID

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

200

—

MHz

ns

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

2.25

1

(TCSS+0.5)/2

TCSH/2

0.65

—

SCLK

ns

t3 QSPIx[A/B]_SSy_B Lead Time¹

—

t4 QSPIx[A/B]_SSy_B Lag Time¹

—

t5 QSPIx[A/B]_DATAy output valid time

t6 QSPIx[A/B]_DATAy output hold time

t9 QSPIx[A/B]_DATAy Setup Skew

—

0.65

—

ns

—

0.65

ns

t10 QSPIx[A/B]_DATAy Hold Skew

—

ns

1

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

4.10.13 Secure JTAG controller (SJC)

4.10.13.1 Internal pull-up/pull-down configuration

The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG

interface. External pull-ups and pull-downs are needed when this interface is routed to a connector.

Table 101. JTAG default configuration for internal pull-up/pull-down

Ball name

Internal pull setting¹

Typical pull value

Unit

JTAG_TMS

JTAG_TCK

JTAG_TDI

PU

PD

PU

PD

50

KΩ

TEST_MODE_SELECT

1

PU = pull-up; PD = pull-down

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4.10.13.2 JTAG timing parameters

Figure 48 depicts the SJC test clock input timing. Figure 49 depicts the SJC boundary scan timing.

Figure 50 depicts the SJC test access port. Signal parameters are listed in Table 102.

SJ1

SJ2

VM

SJ2

VM

JTAG_TCK

(Input)

VIH

VIL

SJ3

Figure 48. Test Clock Input Timing Diagram

JTAG_TCK

(Input)

VIH

SJ5

Input Data Valid

VIL

SJ4

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 49. Boundary system (JTAG) timing diagram

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JTAG_TCK

(Input)

VIH

SJ9

VIL

SJ8

Input Data Valid

JTAG_TDI

JTAG_TMS

(Input)

SJ10

SJ11

SJ10

JTAG_TDO

(Output)

Output Data Valid

JTAG_TDO

(Output)

JTAG_TDO

(Output)

Output Data Valid

Figure 50. Test Access Port Timing Diagram

Table 102. JTAG Timing

All Frequencies

ID

Parameter^1,2

Unit

Min

Max

1

SJ0

SJ1

SJ2

SJ3

SJ4

SJ5

SJ6

SJ7

SJ8

SJ9

SJ10

SJ11

JTAG_TCK frequency of operation 1/(3xT_DC

JTAG_TCK cycle time in crystal mode

)

0.001

45

22.5

—

22

—

3

MHz

ns

2

JTAG_TCK clock pulse width measured at V_M

JTAG_TCK rise and fall times

Boundary scan input data set-up time

Boundary scan input data hold time

JTAG_TCK low to output data valid

JTAG_TCK low to output high impedance

JTAG_TMS, JTAG_TDI data set-up time

JTAG_TMS, JTAG_TDI data hold time

JTAG_TCK low to JTAG_TDO data valid

5

—

40

—

44

24

—

5

25

—

JTAG_TCK low to JTAG_TDO high impedance

= target frequency of SJC

—

1

2

T

DC

V_M= mid-point voltage

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4.10.14 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 103, Figure 51, and Figure 52 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

Table 103. SPDIF Timing Parameters

Timing Parameter Range

Parameter

Symbol

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

ns

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

ns

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

srckp

srckpl

V_M

srckph

V_M

SPDIF_SR_CLK

(Output)

Figure 51. SPDIF_SR_CLK Timing Diagram

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 52. SPDIF_ST_CLK Timing Diagram

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4.10.15 UART I/O configuration and timing parameters

4.10.15.0.1 UART Transmitter

The following figure depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1

stop bit format. Table 104 lists the UART RS-232 serial mode transmit timing characteristics.

POSSIBLE

PARITY

UA1

Bit 3

BIT

Start

Bit

UARTx_TX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 53. UART RS-232 Serial Mode Transmit Timing Diagram

Table 104. UART RS-232 Serial Mode Transmit Timing Parameters

ID

Parameter

Transmit Bit Time

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

2

UA1

t_Tbit

1/F_{baud_rate}¹– T_{ref_clk}

—

1

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0]

× (OSR+1)).

2

T_{ref_clk}: The period of UART reference clock ref_clk (LPUART_clk after SBR divider).

4.10.15.0.2 UART Receiver

The following figure depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format.

Table 105 lists serial mode receive timing characteristics.

POSSIBLE

PARITY

UA2

Bit 3

BIT

Start

Bit

UARTx_RX_DATA

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 54. UART RS-232 Serial Mode Receive Timing Diagram

Table 105. RS-232 Serial Mode Receive Timing Parameters

ID

Parameter

Receive Bit Time¹

Symbol

Min

Max

Unit

2

UA2

t_Rbit

1/F_{baud_rate}

–

1/F_{baud_rate}

+

—

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate})

1

2

The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit, but accumulation tolerance in one frame must

not exceed 3/((OSR+1) × Fbaud_rate).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] ×

(OSR+1)).

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4.10.15.0.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

UART IrDA Mode Transmitter

The following figure depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format.

Table 106 lists the transmit timing characteristics.

UA3

UA4

UA3

UARTx_TX_DATA

(output)

Start

Bit

STOP

BIT

POSSIBLE

PARITY

BIT

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 55. UART IrDA Mode Transmit Timing Diagram

Table 106. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

2

UA3 Transmit Bit Time in IrDA mode

UA4 Transmit IR Pulse Duration

t_TIRbit

1/F_{baud_rate}¹– T_{ref_clk}

—

t_TIRpulse(TNP+1)/(OSR+1) × (1/F_{baud_rat}(TNP+1)/(OSR+1) × (1/F_{baud_rat}

_e) – T_{ref_clk e}) + T_{ref_clk}

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] ×

(OSR+1)).

T_{ref_clk}: The period of UART reference clock ref_clk (LPUART_clk after SBR divider).

UART IrDA Mode Receiver

The following figure depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format.

Table 107 lists the receive timing characteristics.

UA5

UA6

UA5

UARTx_RX_DATA

(input)

STOP

BIT

Start

Bit

POSSIBLE

PARITY

BIT

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 56. UART IrDA Mode Receive Timing Diagram

Table 107. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}

Unit

2

UA5 Receive Bit Time¹in IrDA mode

t_RIRbit

1/F_{baud_rate}

–

+

—

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate}

)

UA6 Receive IR Pulse Duration

t_RIRpulse

1.41 μs

(5/16) × (1/F_{baud_rate}

)

—

1

The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame

must not exceed 3/((OSR+1) × Fbaud_rate).

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2

Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] ×

(OSR+1)).

4.10.16 USB 2.0 PHY Parameters

4.10.16.1 USB 2.0 PHY Transmitter specifications

This section describes the transmitter specifications for USB2.0 PHY.

4.10.16.1.1 USB 2.0 PHY full-speed/low-speed transmitter specifications

The following table lists the full-speed/low-speed (FS/LS) transmitter specifications for USB2.0 PHY.

Table 108. USB 2.0 PHY FS/LS transmitter specifications

Symbol

Description

Min Typ

Max

Units

VOL

VOH

Output Voltage Low

0

2.8

0.8

1.3

4

—

0.3

3.6

—

V

Output Voltage High (Driven)

V

VOSE1 Single Ended One (SE1)

V

VCRS

TFR

TLR

TFF

Output Signal Cross Over Voltage

2.0

20

V

Driver Rise Time - FS

Driver Rise Time - LS

Driver Fall Time - FS

Driver Fall Time - LS

ns

%

Ω

75

300

20

4

TLF

75

300

111.11

125

49.5

3.5

4

TFRFM Differential Rise and Fall Time Matching - FS

TLRFM Differential Rise and Fall Time Matching - LS

ZHSDRV Driver Output Resistance (Also serves as HS Termination)

90

80

40.5

-3.5

-4

TDJ1

TDJ2

Source Jitter (Next Transition) - FS

Source Jitter (Paired Transition) - FS

ns

μs

TFDEOP Source Jitter (Differential to SE0 transition) - FS

TFEOPT Source SE0 interval of EOP - FS

-2

5

160

-25

-14

-95

-150

-40

1.25

175

25

TDDJ1

TDDJ2

TUDJ1

TUDJ2

Source Jitter in downstream direction (Next Transition) - LS

Source Jitter in downstream direction (Paired Transition) - LS

Source Jitter in upstream direction (Next Transition) - LS

Source Jitter in upstream direction (Paired Transition) - LS

14

95

150

100

1.5

TLDEOP Source Jitter in upstream direction (Differential to SE0 transition) - LS

TLEOPT Source SE0 interval of EOP - LS

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4.10.16.2 USB 2.0 PHY high-speed transmitter specifications

The following table lists the high-speed (HS) transmitter specifications for USB 2.0 PHY.

Table 109. USB 2.0 PHY HS transmitter specifications

Symbol/Parameter

Description

Min Typ

Max

Units

HSOI

High Speed Idle Level

-10

—

10

mV

Ω

VHSTERM

VHSOL

Termination Voltage in High Speed

High Speed Data Signaling Low

Chirp J (Differential Voltage)

Chirp K (Differential Voltage)

Driver Output Resistance

-10

10

VCHIRPJ

700

-900

40.5

100

-300

1100

-500

49.5

—

VCHIRPK

ZHSDRV

THSR

Rise Time (10% to 90%)

ps

THSF

Fall Time (10% to 90%)

—

ps

HS Eye Opening: Template 1

Differential eye opening at 37.5% US and 62.5% UI for a

hub measured at TP2 and for a device without a captive

cable measured at TP3.

300

mV

HS Eye Opening: Template 2

HS Jitter: Template 1

Differential eye opening at 37.5% US and 62.5% UI for a

device with a captive cable measured at TP2.

-175

—

175

mV

Peak-Peak Jitter at Zero crossing for a hub measured at

TP2 and for a device without captive cable measured at

TP3.

—

15

%UI

ps

312.5

HS Jitter: Template 2

Peak-Peak Jitter at Zero crossing for a device with captive

cable measured at TP2.

—

25

%UI

ps

520.83

4.10.16.3 USB 2.0 PHY receiver specifications

This section describes the receiver specifications implemented in USB 2.0 PHY.

4.10.16.3.1 USB 2.0 PHY full-speed/low-speed (FS/LS) receiver specifications

Table 110. USB 2.0 PHY FS/LS receiver specifications

Symbol

VIH

Description

Input Voltage Level - High (Driven)

Min

Typ

Max

Units

2

2.7

—

3.6

0.8

2.0

2.5

18.5

V

VIHZ

VIL

Input Voltage Level - High (Floating)

Input Voltage Level - Low

V

VTH

VCM

TJR1

Switching Threshold

0.8

-18.5

V

Common Mode Range

V

Receiver Jitter Budget (Next Transition) - FS

ns

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Table 110. USB 2.0 PHY FS/LS receiver specifications (continued)

Symbol

TJR2

Description

Min

Typ

Max

Units

Receiver Jitter Budget (Paired Transition) - FS

Receiver EOP Interval of EOP - FS

-9

82

—

9

—

ns

TFEOPR

TUJR1

TUJR2

TDJR1

TDJR2

TLEOPR

US Port Differential Receiver Jitter (Next Transition) - LS

US Port Differential Receiver Jitter (Paired Transition) - LS

DS Port Differential Receiver Jitter (Next Transition) - LS

DS Port Differential Receiver Jitter (Paired Transition) - LS

Receiver EOP Interval of EOP - LS

-152

-200

-75

152

200

75

-45

45

670

—

4.10.16.3.2 USB 2.0 PHY high-speed receiver specifications

The following table lists the high-speed (HS) receiver specifications for USB 2.0 PHY.

Table 111. USB 2.0 PHY HS receiver specifications

Symbol/Parameter

VHSCM

Description

Min Typ Max Units

HS RX input common mode voltage range.

-50

40.5

—

500

49.5

20

mV

Ω

ZHSDRV

HS RX input termination (Same as Driver output resistance).

HSRX Jitter: Template 3

HS RX Peak-Peak Jitter specification at differential zero crossing for a

device with captive cable when signal applied at TP2.

%UI

—

416.66 ps

HSRX Jitter: Template 4

HS RX Peak-Peak Jitter specification at differential zero crossing for a

device without captive cable at TP3 and for a hub at TP2.

—

30

%UI

ps

—

625

275

HSRX Input Eye Opening: HS RX differential sensitivity specification at 40% and 60% UI for a

Template 3 device with captive cable when signal is applied at TP2.

-275

mV

HSRX Input Eye Opening: HS RX differential sensitivity specification at 35% and 65% UI for a

-150

—

150

mV

Template 4

device without captive cable when signal is applied at TP3 and for a

hub when a signal is applied at TP2.

4.10.16.3.3 USB 2.0 PHY high-speed envelope detector specifications

The following table lists the high-speed (HS) Envelope Detector Specifications of USB 2.0 PHY.

Table 112. USB 2.0 PHY HS envelope detector specifications

Symbol

Description

Min Typ Max Units

VHSSQ

VHSDSC

HS Squelch Detection threshold (differential signal amplitude)

HS Disconnect Detection threshold (differential signal amplitude)

100

525

—

150

625

mV

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4.10.16.4 USB 2.0 PHY full-speed/high-speed terminations specification

The following table lists the full-speed/low-speed (FS/LS) Terminations Specification of USB 2.0 PHY.

Table 113. USB 2.0 PHY FS/LS terminations specification

Symbol

RPU

Description

Min

Typ

Max

Units

Bus Pull-Up resistor on US Port in IDLE State

Bus Pull-Up resistor on US Port in ACTIVE State

Bus Pull-Down resistor on DS Port

900

1425

14.25

3.0

—

1575

3090

24.8

3.6

Ω

RPD

KΩ

V

VTERM

Termination Voltage for US Port Pull-Up (RPU)

4.10.16.5 Voltage threshold specification

The following table lists the OTG Comparator Specifications of USB2.0 PHY.

Table 114. USB 2.0 PHY OTG comparator specifications

Symbol

Description

Min

Typ

Max

Units

sessvld

vbusvalid

B-Device Session Valid threshold

VBUS Valid threshold

0.8

4.4

—

4.0

V

4.75

4.10.17 USB 3.0 PHY parameters

The following content is from the USB 3.0 PHY specifications.

4.10.17.1 USB 3.0 PHY external component

Table 115. USB 3.0 PHY external component specifications

Name Min Typ Max Units Descriptions

rext 497.5 500 502.5

Ω

There needs to be an external resistor component connected at rext ball while the

internal resistor or current is getting calibrated. Package routing from rext ball to its

respective bump should not contribute more than 0.05 Ω.

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4.10.17.2 USB 3.0 PHY transmitter module

Table 116. USB 3.0 PHY transmitter module electrical specifications

Symbol

Description

Min Typ

Max

Unit

Voltage/current parameters

V_TX-DIFFp

Programmable output voltage

swing (single-ended)

50

—

500

1000

1200

100

mV

V_TX-DIFFp-p

Programmable differential

peak-to-peak output voltage

100

400

1

V_{TX-DIFFp-p-LOW}

Low power differential p-p TX

voltage swing

I_TX-SHORT

RL_TX-DIFF

Transmit lane short-circuit current

Transmitter differential return loss

—

mA

Db

0 < -20dB < 100Mhz

100Mhz < -18dB < 300Mhz

300Mhz < -16dB < 600Mhz

600Mhz < -10dB < 2500Mhz

2500Mhz < -9dB < 4875Mhz

4875Mhz < -8dB < 11200Mhz

11200Mhz < -5dB < 16800Mhz

and -3dB beyond that

Transmitter common mode return

loss

—

50Hz < -8dB < 15000Mhz

dB

RL

TX-CM

DC differential TX impedance

Unit Interval

80

100

120

Ω

Z

TX-DIFF-DC

UI

199.94

—

200.06

0.4

ps

UI

T_{TX-MAX-JITTER}

Transmitter total jitter

(peak-to-peak) (Tj)

T_{TX-RJ-PLL-sigma}

After application of TX jitter transfer

function

—

2.42

210

ps

UI

LTLAT-10

Transmitter data latency

Voltage parameters

V_{TX-CM-DC-ACTIVE-IDLE-DELTA}Absolute Delta of DC Common

Mode Voltage during L0 and

0

—

100

mV

Electrical Idle.

V_{TX-IDLE-DIFF-AC-p}

V_{TX-CM-DC-LINE-DELTA}

V_{TX-RCV-DETECT}

Electrical Idle Differential Peak

Output Voltage

0

—

20

25

600

8

mV

ns

Absolute Delta of DC Common

Mode Voltage between D+ and D-

The amount of voltage change

allowed during Receiver Detection

0

T_{TX-IDLE-SET-TO-IDLE}

Maximum time to transition to a

valid Electrical Idle after sending an

EIOS

—

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Table 116. USB 3.0 PHY transmitter module electrical specifications (continued)

Symbol

Description

Min Typ

Max

Unit

T_{TX-IDLE-TO-DIFF-DATA}

Maximum time to transition to valid

diff signaling after leaving Electrical

Idle

—

8

ns

V_TX-CM-AC-PP

Tx AC peak-peak common mode

voltage (5.0 GT/s)

20

—

150

5

mVpp

T_EIExit

Time to exit Electrical Idle (L0s)

state and to enter L0

Txsysclk

Tx signal characteristics

f_tol

TX Frequency Long Term Accuracy -300

—

300

33

ppm of

Fbaud

f_SSC

Spread-Spectrum Modulation

Frequency

30

kHz

t_20-80TX

t_skewTX

TX Rise/Fall Time

0.2

—

0.41

20

UI

ps

TX Differential Skew

1

For USB 3.0, no EQ is required

4.10.17.3 USB 3.0 PHY receiver module

Table 117. USB 3.0 PHY receiver module electrical specifications

Symbol

Description

Min

Typ Max Unit

Comments

Voltage Parameters

V_RX-DIFF(p-p)

Differential input voltage

(peak-to-peak) (that is, receiver

eye voltage opening)

100

—

1200 mV

—

V_{RX-IDLE-DET-DIFF(p-p}Differential input threshold voltage

300

mV USB3 LFPS

(peak-to-peak) to detect idle

(LFPS)

)

V_{cm, acRX}

RX AC Common Mode Voltage

—

0

100 mVp-p Simulated at 250 MHz

V_RX-CM-AC

Receiver common-mode voltage

for AC coupling

150

mV

—

Z_RX-DIFF-DC

RL_RX-DIFF

Differential input impedance (DC)

Receiver differential return loss

80

100 120

W

100 Ω ± 10%

Same as

TX RL

—

dB

—

Jitter Parameters

T_{RX-MAX-JITTER}

Receiver total jitter tolerance

0

—

0.66

UI

Incoming Jitter:

USB3 = 0.43UI DJ + 0.23UI RJ

USB3 numbers are with REFC-TLE

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Table 118. PLL module electrical specifications

Parameter

Symbol

Description

Min

Typ

Max Units

Input Reference Clock

REF CLK

Frequency

REF CLK

—

19.2 19.2/24/25/26/38.4 38.4 MHz

REF CLK Duty

Cycle

—

47

40

—

53

MHz

ps

REF CLK

Frequency

REF CLK

—

40/48/50/52/100 100

REF CLK RJ

Tolerance

Integrated jitter from 10 kHz to 16 MHz

after applying appropriate PLL ref clock

transfer function and the protocol JTF

—

0.5

63

REF CLK Duty

Cycle

—

37

—

%

Divided Reference

Frequency

—

19.2

38.4 MHz

Dividers

Input division

IPDIV<7:0>

—

1

2

—

255 Counts

1025 Counts

<2 Counts

Feedback division pll_fbdiv_high<9:0>

pll_fbdiv_low<9:0>

2

Feedback fractional

division range

—

>-2

Number of

—

This includes one bit for sign

—

27

—

Bits

fractional bits

VCO

Clock frequency

VCO frequency

—

Output full rate clocks

—

5000

—

MHz

ppm

VCO oscillation frequency

This includes SSC deviation

Output clock

-5300

300

frequency tolerance

SSC modulation

rate

—

As applicable for USB3.0

30

—

33

kHz

ps

Output clock RJ

sigma for TX

After application of TX jitter transfer

function

2.42

1.40

Output clock RJ

sigma for RX

After application of RX jitter transfer

function

ps

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4.11 Analog-to-digital converter (ADC)

The following table shows the ADC electrical specifications for VREFH=VDD_ADC_1P8.

Table 119. ADC electrical specifications (VREFH=VDD_ADC_1P8)

Symbol

V_ADIN

Description

Min

Typ¹

Max

Unit

Notes

Input Voltage

VREFL

—

4.5

500

—

VREFH

—

V

pF

—

C_ADIN

R_ADIN

R_AS

Input capacitance

Input Resistance

—

Ω

—

2

Analog Source Resistance

ADC Conversion Clock Frequency

Sample cycles

—

5

kΩ

f_ADCK

—

24

—

MHz

—

3

C_sample

C_compare

C_conversion

DNL

3.5

—

131.5

—

Fixed compare cycles

Conversion cycles

Differential Non-Linearity

Integral Non-Linearity

Effective Number of Bits

Avg = 1

17.5

cycles

LSB

—

C_{conversion =}C_{sample +}C_compare

—

4

—

± 0.6

± 0.9

—

-0.5 to +1.1

4

INL

±1.1

—

5,6,7

ENOB

—

10.1

10.5

11.1

10.4

10.7

11.3

—

Bits

dB

Avg = 2

—

Avg = 16

—

SINAD

E_G

Signal to Noise plus Distortion

Gain error

SINAD=6.02 x ENOB + 1.76

—

8

—

-0.29

0.01

—

%FSV

μA

9

E_O

Offset error

—

10

I_VDDA18

I_in,ext,leak

E_IL

Supply Current

480

External Channel Leakage Current

Input leakage error

30

500

nA

—

RAS * I_in

mV

1

Typical values assume VDD_ADC_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for

reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production.

2

This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS

(analog source capacitance) time constant should be kept to < 1 ns.

3

4

5

6

7

See Figure 57.

ADC conversion clock at max frequency and using linear histogram.

Input data used for test was 1 kHz sine wave.

Measured at VREFH = 1.8 V and pwrsel = 2.

ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling

may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling

becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content.

8

9

Error measured at fullscale at 1.8 V.

Error measured at zero scale at 0 V.

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Electrical characteristics

¹⁰Power Configuration Select, PWRSEL, is set to 10 binary.

The following table shows the ADC electrical specifications for 1V≤VREFH<VDD_ADC_1P8.

Table 120. ADC electrical specifications (1V≤VREFH<VDD_ADC_1P8)

Symbol

V_ADIN

Description

Min

Typ¹

Max

Unit

Notes

Input Voltage

VREFL

—

4.5

500

—

VREFH

—

V

pF

—

C_ADIN

R_ADIN

R_AS

Input capacitance

Input Resistance

—

Ω

—

2

Analog Source Resistance

ADC Conversion Clock Frequency

Sample cycles

—

5

kΩ

f_ADCK

—

24

—

MHz

—

3

C_sample

C_compare

C_conversion

DNL

3.5

—

131.5

—

Fixed compare cycles

Conversion cycles

Differential Non-Linearity

Integral Non-Linearity

Effective Number of Bits

Avg = 1

17.5

cycles

LSB

—

C_{conversion =}C_{sample +}C_compare

—

4

—

± 0.6

± 0.9

—

-0.5 to +1.1

4

INL

±1.1

—

5,6,7

ENOB

—

9.5

9.9

10.8

9.7

—

Bits

dB

Avg = 2

10.1

11

—

Avg = 16

—

SINAD

E_G

Signal to Noise plus Distortion

Gain error

SINAD=6.02 x ENOB + 1.76

—

8

—

0.29

0.01

—

%FSV

μA

9

E_O

Offset error

—

10

I_VDDA18

I_in,ext,leak

E_IL

Supply Current

480

External Channel Leakage Current

Input leakage error

30

500

nA

—

RAS * I_in

mV

1

Typical values assume VDD_ANA_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for

reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production.

2

This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS

(analog source capacitance) time constant should be kept to < 1 ns.

3

4

5

6

7

See Figure 57.

ADC conversion clock at max frequency and using linear histogram.

Input data used for test was 1 kHz sine wave.

Measured at VREFH = 1 V and pwrsel = 2.

ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling

may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling

becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content.

8

Error measured at fullscale at 1.0 V.

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Electrical characteristics

9

Error measured at zero scale at 0 V.

¹⁰Power Configuration Select, PWRSEL, is set to 10 binary.

The following figure shows a plot of the ADC sample time versus R .

AS

Figure 57. Sample time vs. R

AS

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Boot mode configuration

5 Boot mode configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot mode configuration pins

The following table provides boot options, functionality, fuse values, and associated pins. Several input

pins are also sampled at reset and can be used to override fuse values, depending on the value of

FORCE_BOOT_FROM_FUSE. After it is blown, the Boot mode pin is ignored by ROM; ROM receives

'boot mode' from the BT_MODE_FUSES fuse. The boot option pins are in effect when BT_FUSE_SEL

fuse is ‘0’ (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by

the Boot mode pins, see the “System Boot, Fusemap, and eFuse” chapter of the device reference manual

for more details.

Table 121. Fuse and associated pins used for Boot

Interface

IP Instance

Allocated Pads During Boot

SCU_BOOT_MODE0

Comment

BOOT_MODE[0]

BOOT_MODE[1]

BOOT_MODE[2]

BOOT_MODE[3]

Input

Boot mode selection

SCU_BOOT_MODE1

SCU_BOOT_MODE2

SCU_BOOT_MODE3

5.2

Boot devices interfaces allocation

The following table lists the interfaces that can be used by the boot process in accordance with the

specific Boot mode configuration. The table also describes the interface’s specific modes and IOMUXC

allocation, which are configured during boot when appropriate.

Table 122. Interface allocation during boot

Interface IP Instance

Allocated Pads During Boot

Comment

eMMC

USDHC0 EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0,

EMMC0_DATA1, EMMC0_DATA2,

EMMC0_DATA3, EMMC0_DATA4,

EMMC0_DATA5, EMMC0_DATA6,

EMMC0_DATA7, EMMC0_RESET_B

SD

USDHC1 USDHC1_CD_B, USDHC1_CLK, USDHC1_CMD, USDHC1_CD_B is used by first (A0) silicon only.

USDHC1_DATA0, USDHC1_DATA1,

USDHC1_DATA2, USDHC1_DATA3,

USDHC1_RESET_B, USDHC1_VSELECT

Second (B0) silicon uses USDHC1_DATA3 for

CD (Card Detect).

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Boot mode configuration

Table 122. Interface allocation during boot (continued)

Allocated Pads During Boot

Interface IP Instance

Comment

NAND

GPMI

EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0,

EMMC0_DATA1, EMMC0_DATA2,

EMMC0_DATA3, EMMC0_DATA4,

EMMC0_DATA5, EMMC0_DATA6,

EMMC0_DATA7, EMMC0_STROBE,

EMMC0_RESET_B, USDHC1_CD_B,

USDHC1_CMD, USDHC1_DATA0,

USDHC1_DATA1, USDHC1_DATA2,

USDHC1_DATA3, USDHC1_RESET_B,

USDHC1_VSELECT, USDHC1_WP

8 bit boot from CS0 only, but will drive CS1 to

high when booting if specified in fuse.

Single-ended DQS:

• USDHC1_CD_B

Single-ended RE:

• USDHC1_VSELECT

Differential DQS:

• _N use USDHC1_WP

• _P use USDHC1_CD_B

Differential RE:

• _N use USDHC1_RESET_B

• _P use USDHC1_VSELECT

Quad SPI

QSPI0

QSPI0A_DATA0, QSPI0A_DATA1,

4, dual-4, or 8 bit

QSPI0A_DATA2, QSPI0A_DATA3, QSPI0A_DQS,

QSPI0A_SCLK, QSPI0A_SS0_B,

QSPI0A_SS1_B, QSPI0B_DATA0,

QSPI0B_DATA1, QSPI0B_DATA2,

QSPI0B_DATA3, QSPI0B_DQS, QSPI0B_SCLK,

QSPI0B_SS0_B, QSPI0B_SS1_B

USB

USB-OTG1 USB_OTG1_DN, USB_OTG2_DN,

USB_OTG1_DP, USB_OTG2_DP,

USB_OTG1_ID, USB_OTG2_ID,

USB_OTG1_VBUS, USB_OTG2_VBUS

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Package information and contact assignments

6 Package information and contact assignments

This section contains package information and contact assignments for the following package(s):

•

FCPBGA, 21 x 21 mm, 0.8 mm pitch

6.1

FCPBGA, 21 x 21 mm, 0.8 mm pitch

This section includes the following information for the 21 x 21 mm, 0.8 mm pitch package:

•

Mechanical package drawing

Ball map

Contact assignments

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Package information and contact assignments

6.1.1

21 x 21 mm package case outline

The following figure shows the top, bottom, and side views of the 21 x 21 mm package.

Figure 58. 21 x 21 mm Package Top, Bottom, and Side Views

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Package information and contact assignments

The following notes pertain to the preceding figure, “21 x 21 mm Package Top, Bottom, and Side

Views.”

Figure 59. Notes on 21 x 21 mm Package Top, Bottom, and Side Views

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Package information and contact assignments

6.1.2

21 x 21 mm, 0.8 mm pitch ball map

The following page shows the 21 x 21 mm, 0.8 mm pitch ball map.

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Package information and contact assignments

6.1.3

21 x 21 mm power supplies and functional contact assignments

The following table shows the power supplies contact assignments for the 21 × 21 mm package

Table 123. 21 x 21 mm power supplies contact assignments

Power rail

Ball reference

VDD_A35¹

VDD_ADC_1P8

AA15,AA17,AA19,AB16,AB18,AB20

V28

VDD_ADC_DIG_1P8

W25

VDD_ANA0_1P8

M14

VDD_ANA1_1P8

AB24

VDD_CAN_UART_1P8_3P3

VDD_CSI_1P8_3P3

Y24

AE23

VDD_DDR_PLL_1P8

AC9

VDD_DDR_VDDQ

AA11,AA9,M12,N9,N11,R7,R11,T12,U11,W11,Y12,AC11,AD12,AE11

VDD_EMMC0_1P8_3P3

VDD_EMMC0_VSELECT_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_2P5_3P3

VDD_ENET0_VSELECT_1P8_2P5_3P3

VDD_ESAI_SPDIF_1P8_2P5_3P3

VDD_GPU¹

L19

M20

L25

M24

L23

N25

N23,P20,P22,R21,T22,U23,V20,W21

VDD_MAIN

AA23,AB12,AC13,AC17,AC21,AD14,AD22,N15,N19,P12,P16,P24,R13,R17,T14,T

18,U15,U19,V12,V16,V24,W13,W17,Y14,Y18,Y22

VDD_MIPI_1P0

VDD_MIPI_1P8

AD18,AE19

AD16,AE17

AE21

AA25

G13

VDD_MIPI_CSI_DIG_1P8

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_PCIE_1P8

VDD_PCIE_DIG_1P8_3P3

VDD_PCIE_LDO_1P0_CAP

VDD_QSPI0A_1P8_3P3

VDD_QSPI0B_1P8_3P3

VDD_SNVS_4P2

L11

L13

AE15

AE13

AC25

AE25

R25

VDD_SNVS_LDO_1P8_CAP

VDD_SPI_MCLK_UART_1P8_3P3

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Package information and contact assignments

Table 123. 21 x 21 mm power supplies contact assignments (continued)

Power rail

Ball reference

VDD_SPI_SAI_1P8_3P3

VDD_TMPR_CSI_1P8_3P3

VDD_USB_1P8

U25

AD24

M18

L15

VDD_USB_3P3

VDD_USB_OTG_1P0

L17

VDD_USB_SS3_LDO_1P0_CAP

VDD_USDHC1_1P8_3P3

VDD_USDHC1_VSELECT_1P8_3P3

VSS_MAIN

M16

M22

L21

A17, A3, A33, AA1, AA13, AA21, AA27, AA3,

AA5,AA7,AB10,AB14,AB22,AB26,AB30,AC15,AC19,AC23,AC27,AC33,AD10,AD2,

AD20,AD26,AD4,AD6,AE27,AE9,AF10,AF12,AF14,AF16,AF18,AF20,AF22,AF24,A

F26,AF30,AG1,AG11,AG13,AG15,AG17,AG19,AG21,AG23,

AG25,AG27,AG3,AG33,AG5,AG7,AG9,AH14,AH16,AH18,AH20,AH22,AH24,AH26

,AK2,AK30,AK4,AK6,AK8,AL13,AL15,AL17,AL19,AL21,AL23,AL25,AL33,

AN1,AN11,AN13,AN27,AN3,AN31,AN5,AN7,AN9,AR3,B14,B20,B8,C1,C11,C13,C1

7,C19,C23,C27,C3,C31,C35,C5,C7,C9,E15,E29,E33,

F10,F18,F2,F20,F24,F4,F6,F8,H30,J1,J11,J13,J15,J17,J19,J21,J23,J25,J27,J3,J3

3,J5,J7,J9,K10,K12,K14,K16,K18,K20,K22,K24,K26,L27,L9,M10,M2,M26,

M30,M4,M6,M8,N13,N17,N21,N27,N33,P10,P14,P18,P26,R1,R15,R19,R23,R27,R

3,R5,R9,T10,T16,T20,T24,T26,T28,T30,T32,T34,U13,U17,U21,U27,U9, V10,

V14,V18,V2,V22,V26,V4,V6,V8,W15,W19,W23,W27,W31,W33,W35,W9,Y10,Y16,

Y20,Y26,Y28,Y30

VSS_SCU_XTAL

AN33,AN35,AR33

1

VDD_A35 and VDD_GPU can be combined with one power supply.

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Package information and contact assignments

The following table shows functional contact assignments for the 21 × 21 mm package.

Table 124. 21 x 21 mm functional contact assignments

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

U35

U33

ADC_IN0

ADC_IN1

VDD_ADC_DIG_1P8

GPIO

ANA

ALT0

ADMA.ADC.IN0

ADMA.ADC.IN1

INPUT

PD(50K)

V32

ADC_IN2

VDD_ADC_DIG_1P8

ADMA.ADC.IN2

V30

ADC_IN3

VDD_ADC_DIG_1P8

ADMA.ADC.IN3

W29

V34

ADC_IN4

VDD_ADC_DIG_1P8

ADMA.ADC.IN4

ADC_IN5

VDD_ADC_DIG_1P8

ADMA.ADC.IN5

U29

ADC_VREFH

ADC_VREFL

ANA_TEST_OUT_N

ANA_TEST_OUT_P

CSI_D00

VDD_ADC_1P8

ADC_VREFH

U31

VDD_ADC_1P8

ANA

ADC_VREFL

AK34

AL35

AK28

AL29

AP30

AJ27

AN29

AM30

AJ25

AM28

AR29

AL27

AP28

AM26

AK26

AR27

G19

VDD_SCU_ANA_1P8

VDD_TMPR_CSI_1P8_3P3

VDD_CSI_1P8_3P3

ANA

SCU.DSC.TEST_OUT_N

SCU.DSC.TEST_OUT_P

CI_PI.CSI_D02

ANA

GPIO

ALT0

ALT4

ALT0

INPUT

PD(50K)

CSI_D01

CI_PI.CSI_D03

CSI_D02

CI_PI.CSI_D04

CSI_D03

CI_PI.CSI_D05

CSI_D04

CI_PI.CSI_D06

CSI_D05

CI_PI.CSI_D07

CSI_D06

CI_PI.CSI_D08

CSI_D07

CI_PI.CSI_D09

CSI_HSYNC

CSI_VSYNC

CSI_EN

CI_PI.CSI_HSYNC

CI_PI.CSI_VSYNC

CI_PI.CSI_EN

CSI_MCLK

VDD_CSI_1P8_3P3

LSIO.GPIO3.IO01

CI_PI.CSI_PCLK

CI_PI.CSI_RESET

LSIO.GPIO4.IO07

CONN.EMMC0.CMD

CONN.EMMC0.DATA0

CONN.EMMC0.DATA1

CONN.EMMC0.DATA2

CONN.EMMC0.DATA3

CONN.EMMC0.DATA4

CONN.EMMC0.DATA5

CONN.EMMC0.DATA6

CSI_PCLK

VDD_CSI_1P8_3P3

CSI_RESET

EMMC0_CLK

EMMC0_CMD

EMMC0_DATA0

EMMC0_DATA1

EMMC0_DATA2

EMMC0_DATA3

EMMC0_DATA4

EMMC0_DATA5

EMMC0_DATA6

VDD_CSI_1P8_3P3

VDD_EMMC0_1P8_3P3

FASTD ALT4

FASTD ALT0

D20

C21

A21

E21

H20

B22

VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0

G21

A23

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Package information and contact assignments

Table 124. 21 x 21 mm functional contact assignments (continued)

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

D22

H22

F22

EMMC0_DATA7

EMMC0_RESET_B

EMMC0_STROBE

ENET0_MDC

VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0

VDD_EMMC0_VSELECT_1P8_3P3 GPIO ALT4

VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0

CONN.EMMC0.DATA7

LSIO.GPIO4.IO18

INPUT

PD(50K)

PU(50K)

PD(50K)

PU(50K)

PD(50K)

CONN.EMMC0.STROBE

LSIO.GPIO5.IO11

D30

B32

F28

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_2P5_3P3

GPIO

ALT4

ALT0

ALT4

ENET0_MDIO

CONN.ENET0.MDIO

LSIO.GPIO5.IO09

ENET0_REFCLK_125M_25M

ENET0_RGMII_RX_CTL

ENET0_RGMII_RXC

ENET0_RGMII_RXD0

ENET0_RGMII_RXD1

ENET0_RGMII_RXD2

ENET0_RGMII_RXD3

ENET0_RGMII_TX_CTL

ENET0_RGMII_TXC

ENET0_RGMII_TXD0

ENET0_RGMII_TXD1

ENET0_RGMII_TXD2

ENET0_RGMII_TXD3

ESAI0_FSR

B30

D28

A31

C29

G27

H26

A29

H24

G25

B28

E27

F26

FASTD ALT0

CONN.ENET0.RGMII_RX_CTL

CONN.ENET0.RGMII_RXC

CONN.ENET0.RGMII_RXD0

CONN.ENET0.RGMII_RXD1

CONN.ENET0.RGMII_RXD2

CONN.ENET0.RGMII_RXD3

LSIO.GPIO4.IO30

VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4

LSIO.GPIO4.IO29

LSIO.GPIO4.IO31

LSIO.GPIO5.IO00

LSIO.GPIO5.IO01

LSIO.GPIO5.IO02

F30

VDD_ESAI_SPDIF_1P8_2P5_3P3

VDD_CAN_UART_1P8_3P3

GPIO

TEST

ALT0

ALT4

ALT0

ALT4

ALT0

ALT4

ALT0

ADMA.ESAI0.FSR

G29

H28

E31

D32

B34

K28

C33

F32

ESAI0_FST

ADMA.ESAI0.FST

ESAI0_SCKR

ADMA.ESAI0.SCKR

ADMA.ESAI0.SCKT

ADMA.ESAI0.TX0

ESAI0_SCKT

ESAI0_TX0

ESAI0_TX1

ADMA.ESAI0.TX1

ESAI0_TX2_RX3

ESAI0_TX3_RX2

ESAI0_TX4_RX1

ESAI0_TX5_RX0

FLEXCAN0_RX

ADMA.ESAI0.TX2_RX3

ADMA.ESAI0.TX3_RX2

ADMA.ESAI0.TX4_RX1

ADMA.ESAI0.TX5_RX0

ADMA.FLEXCAN0.RX

LSIO.GPIO1.IO16

J29

Y34

Y32

AA33

AA35

AB34

AA31

AE31

FLEXCAN0_TX

VDD_CAN_UART_1P8_3P3

FLEXCAN1_RX

VDD_CAN_UART_1P8_3P3

ADMA.FLEXCAN1.RX

LSIO.GPIO1.IO18

FLEXCAN1_TX

VDD_CAN_UART_1P8_3P3

FLEXCAN2_RX

VDD_CAN_UART_1P8_3P3

ADMA.FLEXCAN2.RX

LSIO.GPIO1.IO20

FLEXCAN2_TX

VDD_CAN_UART_1P8_3P3

JTAG_TCK

VDD_ANA1_1P8

SCU.JTAG.TCK

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Package information and contact assignments

Table 124. 21 x 21 mm functional contact assignments (continued)

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

AH34

AF32

AG35

G35

JTAG_TDI

VDD_ANA1_1P8

TEST

GPIO

CSI

ALT0

ALT4

SCU.JTAG.TDI

SCU.JTAG.TDO

INPUT

OUTPUT

INPUT

PU(50K)

HiZ

JTAG_TDO

JTAG_TMS

VDD_ANA1_1P8

SCU.JTAG.TMS

PU(50K)

PD(50K)

Hi-Z

MCLK_IN0

VDD_SPI_MCLK_UART_1P8_3P3

VDD_MIPI_1P8

ADMA.ACM.MCLK_IN0

ADMA.ACM.MCLK_IN1

LSIO.GPIO0.IO20

MIPI_CSI0.CKN

M28

MCLK_IN1

L29

MCLK_OUT0

AN21

AR21

AM22

AP22

AM20

AP20

AN23

AR23

AN19

AR19

AR25

AP24

AP26

AM24

AN25

AJ19

AK20

AJ21

AK22

AJ17

AK18

AJ23

AK24

AJ15

AK16

AD32

AE35

AC31

AB28

MIPI_CSI0_CLK_N

MIPI_CSI0_CLK_P

MIPI_CSI0_DATA0_N

MIPI_CSI0_DATA0_P

MIPI_CSI0_DATA1_N

MIPI_CSI0_DATA1_P

MIPI_CSI0_DATA2_N

MIPI_CSI0_DATA2_P

MIPI_CSI0_DATA3_N

MIPI_CSI0_DATA3_P

MIPI_CSI0_GPIO0_00

MIPI_CSI0_GPIO0_01

MIPI_CSI0_I2C0_SCL

MIPI_CSI0_I2C0_SDA

MIPI_CSI0_MCLK_OUT

MIPI_DSI0_CLK_N

MIPI_DSI0_CLK_P

MIPI_DSI0_DATA0_N

MIPI_DSI0_DATA0_P

MIPI_DSI0_DATA1_N

MIPI_DSI0_DATA1_P

MIPI_DSI0_DATA2_N

MIPI_DSI0_DATA2_P

MIPI_DSI0_DATA3_N

MIPI_DSI0_DATA3_P

MIPI_DSI0_GPIO0_00

MIPI_DSI0_GPIO0_01

MIPI_DSI0_I2C0_SCL

MIPI_DSI0_I2C0_SDA

VDD_MIPI_1P8

CSI

MIPI_CSI0.CKP

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DN0

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DP0

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DN1

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DP1

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DN2

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DP2

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DN3

Hi-Z

VDD_MIPI_1P8

CSI

MIPI_CSI0.DP3

Hi-Z

VDD_MIPI_CSI_DIG_1P8

VDD_MIPI_1P8

GPIO

DSI

ALT0

ALT4

MIPI_CSI0.GPIO0.IO00

MIPI_CSI0.GPIO0.IO01

MIPI_CSI0.I2C0.SCL

MIPI_CSI0.I2C0.SDA

LSIO.GPIO3.IO04

MIPI_DSI0.CKN

INPUT

PD(50K)

PU(50K)

PD(50K)

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.CKP

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DN0

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DP0

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DN1

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DP1

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DN2

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DP2

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DN3

Hi-Z

VDD_MIPI_1P8

DSI

MIPI_DSI0.DP3

Hi-Z

VDD_MIPI_DSI_DIG_1P8_3P3

GPIO

ALT0

MIPI_DSI0.GPIO0.IO00

MIPI_DSI0.GPIO0.IO01

MIPI_DSI0.I2C0.SCL

MIPI_DSI0.I2C0.SDA

INPUT

PD(50K)

PU(50K)

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123

Package information and contact assignments

Table 124. 21 x 21 mm functional contact assignments (continued)

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

AM16

AP16

AN15

AR15

AN17

AR17

AM14

AP14

AM18

AP18

AD30

AF34

AE33

AC29

AH28

D10

MIPI_DSI1_CLK_N

MIPI_DSI1_CLK_P

VDD_MIPI_1P8

DSI

MIPI_DSI1.CKN

MIPI_DSI1.CKP

Hi-Z

MIPI_DSI1_DATA0_N

MIPI_DSI1_DATA0_P

MIPI_DSI1_DATA1_N

MIPI_DSI1_DATA1_P

MIPI_DSI1_DATA2_N

MIPI_DSI1_DATA2_P

MIPI_DSI1_DATA3_N

MIPI_DSI1_DATA3_P

MIPI_DSI1_GPIO0_00

MIPI_DSI1_GPIO0_01

MIPI_DSI1_I2C0_SCL

MIPI_DSI1_I2C0_SDA

ON_OFF_BUTTON

VDD_MIPI_1P8

DSI

MIPI_DSI1.DN0

VDD_MIPI_1P8

DSI

MIPI_DSI1.DP0

VDD_MIPI_1P8

DSI

MIPI_DSI1.DN1

VDD_MIPI_1P8

DSI

MIPI_DSI1.DP1

VDD_MIPI_1P8

DSI

MIPI_DSI1.DN2

VDD_MIPI_1P8

DSI

MIPI_DSI1.DP2

VDD_MIPI_1P8

DSI

MIPI_DSI1.DN3

VDD_MIPI_1P8

DSI

MIPI_DSI1.DP3

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_SNVS_LDO_1P8_CAP

VDD_PCIE_DIG_1P8_3P3

VDD_PCIE_1P8

GPIO

ANA

GPIO

PCIE

SCU

ANA

SCU

ALT0

MIPI_DSI1.GPIO0.IO00

MIPI_DSI1.GPIO0.IO01

MIPI_DSI1.I2C0.SCL

MIPI_DSI1.I2C0.SDA

SNVS.ON_OFF_BUTTON

HSIO.PCIE0.CLKREQ_B

HSIO.PCIE0.PERST_B

HSIO.PCIE0.WAKE_B

HSIO.PCIE_IOB.REF_QR

HSIO.PCIE_IOB.EXT_REFCLK100M_N

HSIO.PCIE_IOB.EXT_REFCLK100M_P

HSIO.PCIE.REXT

INPUT

PD(50K)

PU(50K)

PCIE_CTRL0_CLKREQ_B

PCIE_CTRL0_PERST_B

PCIE_CTRL0_WAKE_B

PCIE_REF_QR

ALT0

INPUT

PD(50K)

PU(50K)

H10

A11

F12

D12

PCIE_REFCLK100M_N

PCIE_REFCLK100M_P

PCIE_REXT

VDD_PCIE_1P8

E11

VDD_PCIE_1P8

H12

VDD_PCIE0_1P0

G11 PCIE0_PHY_PLL_REF_RETURN

VDD_PCIE_LDO_1P0_CAP

VDD_ANA1_1P8

HSIO.PCIE0.PLL_REF_RETURN

HSIO.PCIE0.RX0_N

HSIO.PCIE0.RX0_P

HSIO.PCIE0.TX0_N

HSIO.PCIE0.TX0_P

SCU.PMIC_I2C.SCL

SCU.PMIC_I2C.SDA

SCU.DSC.PMIC_INT_B

SNVS.PMIC_ON_REQ

SCU.DSC.POR_B

B12

A13

PCIE0_RX0_N

PCIE0_RX0_P

PCIE0_TX0_N

PCIE0_TX0_P

PMIC_I2C_SCL

PMIC_I2C_SDA

PMIC_INT_B

A9

B10

AJ35

AH32

AJ33

AR31

AG31

AK14

AR13

AJ13

ALT0

INPUT

PU(50K)

VDD_ANA1_1P8

PMIC_ON_REQ

POR_B

VDD_SNVS_LDO_1P8_CAP

VDD_ANA1_1P8

ALT0

INPUT

PU(50K)

PD(50K)

QSPI0A_DATA0

QSPI0A_DATA1

QSPI0A_DATA2

VDD_QSPI0A_1P8_3P3

FASTD ALT0

LSIO.QSPI0A.DATA0

LSIO.QSPI0A.DATA1

LSIO.QSPI0A.DATA2

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NXP Semiconductors

124

Package information and contact assignments

Table 124. 21 x 21 mm functional contact assignments (continued)

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

AH12

AL11

AP12

AM12

AK12

AM10

AL9

QSPI0A_DATA3

QSPI0A_DQS

VDD_QSPI0A_1P8_3P3

VDD_QSPI0B_1P8_3P3

VDD_SNVS_LDO_1P8_CAP

VDD_SPI_SAI_1P8_3P3

VDD_ANA1_1P8

FASTD ALT0

FASTD ALT4

FASTD ALT0

FASTD ALT4

ANA

LSIO.QSPI0A.DATA3

LSIO.QSPI0A.DQS

LSIO.GPIO3.IO16

INPUT

PD(50K)

PU(50K)

PD(50K)

PU(50K)

QSPI0A_SCLK

QSPI0A_SS0_B

QSPI0A_SS1_B

QSPI0B_DATA0

QSPI0B_DATA1

QSPI0B_DATA2

QSPI0B_DATA3

QSPI0B_DQS

LSIO.GPIO3.IO14

LSIO.GPIO3.IO15

LSIO.QSPI0B.DATA0

LSIO.QSPI0B.DATA1

LSIO.QSPI0B.DATA2

LSIO.QSPI0B.DATA3

LSIO.QSPI0B.DQS

LSIO.GPIO3.IO17

AJ11

AM8

AK10

AR11

AH10

AJ9

QSPI0B_SCLK

QSPI0B_SS0_B

QSPI0B_SS1_B

RTC_XTALI

LSIO.GPIO3.IO23

LSIO.GPIO3.IO24

AP32

AM32

M34

SNVS.RTC_XTALI

SNVS.RTC_XTALO

ADMA.SAI0.RXD

RTC_XTALO

ANA

SAI0_RXD

GPIO

SCU

ALT0

ALT1

ALT0

ALT4

ALT0

INPUT

OUTPUT

PD(50K)

PU(50K)

HiZ

J35

SAI0_TXC

ADMA.SAI0.TXC

K34

SAI0_TXD

ADMA.SAI0.TXD

L33

SAI0_TXFS

ADMA.SAI0.TXFS

L35

SAI1_RXC

ADMA.SAI1.RXC

M32

SAI1_RXD

ADMA.SAI1.RXD

N35

SAI1_RXFS

ADMA.SAI1.RXFS

SCU.DSC.BOOT_MODE0

SCU.DSC.BOOT_MODE1

SCU.DSC.BOOT_MODE2

SCU.DSC.BOOT_MODE3

SCU.GPIO0.IO00

AJ31

AK32

AL31

AJ29

AF28

AH30

AG29

AD28

E35

SCU_BOOT_MODE0

SCU_BOOT_MODE1

SCU_BOOT_MODE2

SCU_BOOT_MODE3

SCU_GPIO0_00

SCU_GPIO0_01

SCU_PMIC_STANDBY

VDD_ANA1_1P8

SCU

VDD_ANA1_1P8

SCU

VDD_ANA1_1P8

SCU

VDD_ANA1_1P8

GPIO

SCU

VDD_ANA1_1P8

SCU.GPIO0.IO01

VDD_ANA1_1P8

SCU.DSC.PMIC_STANDBY

SCU.WDOG0.WDOG_OUT

ADMA.SPDIF0.EXT_CLK

ADMA.SPDIF0.RX

LSIO.GPIO0.IO11

3

SCU_WDOG_OUT

VDD_ANA1_1P8

SCU

OUTPUT PD(50K)

SPDIF0_EXT_CLK

SPDIF0_RX

SPDIF0_TX

SPI0_CS0

VDD_ESAI_SPDIF_1P8_2P5_3P3

VDD_SPI_SAI_1P8_3P3

GPIO

INPUT

PD(50K)

G31

D34

R33

ADMA.SPI0.CS0

R35

SPI0_CS1

ADMA.SPI0.CS1

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Package information and contact assignments

Table 124. 21 x 21 mm functional contact assignments (continued)

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

P30

P34

R31

P28

R29

N31

P32

J31

SPI0_SCK

SPI0_SDI

VDD_SPI_SAI_1P8_3P3

GPIO

SCU

ALT0

ALT4

ALT0

ALT4

ALT0

ALT4

ALT0

ALT4

ALT0

ALT4

ALT0

ALT4

ALT0

ALT4

ADMA.SPI0.SCK

ADMA.SPI0.SDI

INPUT

PD(50K)

SPI0_SDO

VDD_SPI_SAI_1P8_3P3

LSIO.GPIO1.IO06

SPI2_CS0

VDD_SPI_SAI_1P8_3P3

ADMA.SPI2.CS0

SPI2_SCK

VDD_SPI_SAI_1P8_3P3

ADMA.SPI2.SCK

SPI2_SDI

VDD_SPI_SAI_1P8_3P3

ADMA.SPI2.SDI

SPI2_SDO

VDD_SPI_SAI_1P8_3P3

LSIO.GPIO1.IO01

SPI3_CS0

VDD_SPI_MCLK_UART_1P8_3P3

VDD_ANA1_1P8

ADMA.SPI3.CS0

K30

H32

G33

F34

SPI3_CS1

ADMA.SPI3.CS1

SPI3_SCK

ADMA.SPI3.SCK

SPI3_SDI

ADMA.SPI3.SDI

SPI3_SDO

LSIO.GPIO0.IO14

AE29

AB32

AA29

K32

N29

L31

TEST_MODE_SELECT

UART0_RX

SCU.TCU.TEST_MODE_SELECT

ADMA.UART0.RX

VDD_CAN_UART_1P8_3P3

VDD_SPI_MCLK_UART_1P8_3P3

VDD_CAN_UART_1P8_3P3

VDD_USB_3P3

GPIO

OTG

UART0_TX

LSIO.GPIO1.IO22

UART1_CTS_B

UART1_RTS_B

UART1_RX

ADMA.UART1.CTS_B

LSIO.GPT0.CLK

ADMA.UART1.RX

H34

AD34

AC35

E19

D18

G17

H18

D16

E17

F16

UART1_TX

LSIO.GPIO0.IO21

UART2_RX

ADMA.UART2.RX

UART2_TX

LSIO.GPIO1.IO23

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_ID

USB_OTG1_VBUS

USB_OTG2_DN

USB_OTG2_DP

USB_OTG2_ID

USB_OTG2_REXT

USB_OTG2_VBUS

USB_SS3_REXT

USB_SS3_RX_N

USB_SS3_RX_P

USB_SS3_TC0

USB_SS3_TC1

CONN.USB_OTG1.DN

CONN.USB_OTG1.DP

CONN.USB_OTG1.ID

CONN.USB_OTG1.VBUS

CONN.USB_OTG2.DM

CONN.USB_OTG2.DP

CONN.USB_OTG2.ID

CONN.USB_OTG2.RTRIM

CONN.USB_OTG2.VBUS

CONN.USB_SS3.REXT

CONN.USB_SS3.RX_M_LN_0

CONN.USB_SS3.RX_P_LN_0

ADMA.I2C1.SCL

VDD_USB_3P3

OTG

VDD_USB_3P3

OTG

VDD_USB_3P3

OTG

D14

H16

E13

B18

A19

F14

OTG

VDD_USB_1P8

VDD_USB_SS3_LDO_1P0_CAP

VDD_USB_3P3

USB3

GPIO

Hi-Z

ALT0

INPUT

PD(50K)

H14

VDD_USB_3P3

ADMA.I2C1.SCL

i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020

NXP Semiconductors

126

Package information and contact assignments

Table 124. 21 x 21 mm functional contact assignments (continued)

Reset Condition²

Ball

Ball Name

Power Domain

Type

Default

Mode

Default Default

Direction Pull

1

Default Function

G15

C15

A15

B16

E23

G23

C25

A27

B26

D26

E25

B24

A25

D24

AP34

AM34

USB_SS3_TC2

USB_SS3_TC3

USB_SS3_TX_N

USB_SS3_TX_P

USDHC1_CD_B

USDHC1_CLK

USDHC1_CMD

USDHC1_DATA0

USDHC1_DATA1

USDHC1_DATA2

USDHC1_DATA3

USDHC1_RESET_B

USDHC1_VSELECT

USDHC1_WP

VDD_USB_3P3

GPIO

USB3

ALT0

ADMA.I2C1.SDA

INPUT

PD(50K)

VDD_USB_SS3_LDO_1P0_CAP

CONN.USB_SS3.TX_M_LN_0

CONN.USB_SS3.TX_P_LN_0

CONN.USDHC1.CD_B

LSIO.GPIO4.IO23

VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT0

INPUT

PU(50K)

PD(50K)

PU(50K)

PD(50K)

VDD_USDHC1_1P8_3P3

FASTD ALT4

FASTD ALT0

CONN.USDHC1.CMD

CONN.USDHC1.DATA0

CONN.USDHC1.DATA1

CONN.USDHC1.DATA2

CONN.USDHC1.DATA3

LSIO.GPIO4.IO19

VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT4

VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT0

LSIO.GPIO4.IO20

CONN.USDHC1.WP

SCU.DSC.XTALI

XTALI

VDD_ANA1_1P8

ANA

XTALO

SCU.DSC.XTALO

1

2

FASTD are GPIO balls configured for high speed operation using the FASTRZ control.

Reset condition shown is before boot code execution. For pad changes after boot code execution, see the System Boot chapter

of the device reference manual.

3

SCU_WDOG_OUT was previously named JTAG_TRST_B; it has been renamed because its functionality has changed.

i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020

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127

Package information and contact assignments

The following table shows DDR pin function.

Table 125. DRAM pin function

Ball Name

Ball

LPDDR4 function

DDR3L function

DDR_ATO

AB8

Y6

W5

N5

P6

W1

U3

U1

U7

U5

T2

—

DDR_CK0_N

DDR_CK0_P

DDR_CK1_N

DDR_CK1_P

CA2_A

CA4_A

CA5_A

—

DDR_CK0_N

DDR_CK0_P

DDR_CK1_N

DDR_CK1_P

DDR_DCF00

DDR_DCF01

DDR_DCF03

DDR_DCF04

DDR_DCF05

DDR_DCF07

DDR_DCF08

DDR_DCF09

DDR_DCF10

DDR_DCF11

DDR_DCF12

DDR_DCF14

DDR_DCF15

DDR_DCF16

DDR_DCF17

DDR_DCF18

DDR_DCF19

DDR_DCF20

DDR_DCF21

DDR_DCF22

DDR_DCF23

DDR_DCF24

DDR_DCF25

DDR_DCF26

DDR_DCF27

DDR_DCF28

DDR_CK0_N

DDR_CK0_P

DDR_CK1_N

DDR_CK1_P

A5

A6

A7

A8

—

A9

—

RAS#

A3

AB4

AB6

AC5

W3

Y8

Y2

Y4

W7

N3

L1

CA3_A

ODT_CA_A

CS0_A

CA0_A

CS1_A

CKE0_A

CKE1_A

CA1_A

CA4_B

RESET_N

CA5_B

—

ODT

A1

A0

A2

—

A4

A12

RESET_N

A14

N1

P4

T8

A15

—

BA0

P2

T4

—

BA1

—

BA2

T6

—

CAS#

ODT1

A13

K8

L7

ODT_CA_B

CA3_B

CA0_B

CS0_B

K4

K6

A10

CS_N[0]

i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020

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128

Package information and contact assignments

Table 125. DRAM pin function (continued)

Ball Name

Ball

LPDDR4 function

DDR3L function

DDR_DCF29

DDR_DCF30

DDR_DCF31

DDR_DCF32

DDR_DCF33

DDR_DM0

K2

N7

CS1_B

CS_N[1]

CKE0

CKE0_B

L5

CKE1_B

CKE1

L3

CA1_B

A11

P8

CA2_B

WE#

AJ7

AF4

D4

DDR_DMI0

DDR_DMI1

DDR_DMI2

DDR_DMI3

—

DDR_DMI0

DDR_DMI1

DDR_DMI2

DDR_DMI3

DDR_DMI4

DDR_DQ00

DDR_DQ01

DDR_DQ02

DDR_DQ03

DDR_DQ04

DDR_DQ05

DDR_DQ06

DDR_DQ07

DDR_DQ08

DDR_DQ09

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DQ16

DDR_DQ17

DDR_DQ18

DDR_DQ19

DDR_DQ20

DDR_DQ21

DDR_DQ22

DDR_DM1

DDR_DM2

DDR_DM3

E1

DDR_DM4

AP6

AF6

AE5

AH8

AF8

AM4

AM6

AL5

AL7

AJ1

AJ3

AH2

AH4

AC3

AE3

AB2

AC1

B6

DDR_DQ00

DDR_DQ01

DDR_DQ02

DDR_DQ03

DDR_DQ04

DDR_DQ05

DDR_DQ06

DDR_DQ07

DDR_DQ08

DDR_DQ09

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DQ16

DDR_DQ17

DDR_DQ18

DDR_DQ19

DDR_DQ20

DDR_DQ21

DDR_DQ22

DDR_DQ00

DDR_DQ01

DDR_DQ02

DDR_DQ03

DDR_DQ04

DDR_DQ05

DDR_DQ06

DDR_DQ07

DDR_DQ08

DDR_DQ09

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DQ16

DDR_DQ17

DDR_DQ18

DDR_DQ19

DDR_DQ20

DDR_DQ21

DDR_DQ22

E9

E7

D8

G7

H8

H6

i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020

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129

Package information and contact assignments

Table 125. DRAM pin function (continued)

Ball Name

Ball

LPDDR4 function

DDR3L function

DDR_DQ23

DDR_DQ24

DDR_DQ25

DDR_DQ26

DDR_DQ27

DDR_DQ28

DDR_DQ29

DDR_DQ30

DDR_DQ31

DDR_DQ32

DDR_DQ33

DDR_DQ34

DDR_DQ35

DDR_DQ36

DDR_DQ37

DDR_DQ38

DDR_DQ39

DDR_DQS0_N

DDR_DQS0_P

DDR_DQS1_N

DDR_DQS1_P

DDR_DQS2_N

DDR_DQS2_P

DDR_DQS3_N

DDR_DQS3_P

DDR_DQS4_N

DDR_DQS4_P

DDR_DTO0

DDR_DTO1

DDR_VREF

DDR_ZQ

G5

H2

DDR_DQ23

DDR_DQ24

DDR_DQ25

DDR_DQ26

DDR_DQ27

DDR_DQ28

DDR_DQ29

DDR_DQ30

DDR_DQ31

DDR_DQ32

DDR_DQ33

DDR_DQ34

DDR_DQ35

DDR_DQ36

DDR_DQ37

DDR_DQ38

DDR_DQ39

DDR_DQS0_N

DDR_DQS0_P

DDR_DQS1_N

DDR_DQS1_P

DDR_DQS2_N

DDR_DQS2_P

DDR_DQS3_N

DDR_DQS3_P

DDR_DQS4_N

DDR_DQS4_P

—

DDR_DQ24

H4

DDR_DQ25

G3

DDR_DQ26

G1

DDR_DQ27

A7

DDR_DQ28

B4

DDR_DQ29

B2

DDR_DQ30

A5

DDR_DQ31

AL1

AM2

AL3

AP2

AP8

AP10

AR9

AR7

AH6

AJ5

AE1

AF2

E5

—

DDR_DQS0_N

DDR_DQS0_P

DDR_DQS1_N

DDR_DQS1_P

DDR_DQS2_N

DDR_DQS2_P

DDR_DQS3_N

DDR_DQS3_P

—

D6

E3

D2

AR5

AP4

AC7

AE7

AD8

G9

—

i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020

NXP Semiconductors

130

Release Notes

7 Release Notes

This table provides release notes for the data sheet.

Table 126. Data sheet release notes

Substantive Change(s)

Rev.

Number

Date

0

05/2020 • Initial draft

i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020

NXP Semiconductors

131

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Document Number: IMX8QXPIEC

Rev. 0

05/2020


型号：	MIMX8DX5CVLFZAC
厂家：	NXP
描述：	i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors
文件：	总132页 (文件大小：2245K)
中文：	中文翻译
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