MIMX8QPNAVUXXAX [NXP]

i.MX 8QuadPlus Automotive and Infotainment Applications Processors;


型号：	MIMX8QPNAVUXXAX
厂家：	NXP
描述：	i.MX 8QuadPlus Automotive and Infotainment Applications Processors
文件：	总147页 (文件大小：2863K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IMX8QPAEC

Rev. 2, 05/2021

NXP Semiconductors

Data Sheet: Technical Data

MIMX8QPnAVUxxAx

i.MX 8QuadPlus

Automotive and

Infotainment

Package Information

29 x 29 mm package case outline

Applications Processors

Ordering Information

See Table 2 on page 5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 System Controller Firmware (SCFW) Requirements5

1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 13

3.2 Recommended Connections for Unused Interfaces13

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Power supplies requirements and restrictions. . . . 26

4.3 PLL electrical characteristics. . . . . . . . . . . . . . . . . 29

4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 33

4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42

4.7 Output Buffer Impedance Parameters. . . . . . . . . . 45

4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 49

4.9 General-Purpose Media Interface (GPMI) Timing. 53

4.10 External Peripheral Interface Parameters . . . . . . . 62

4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 111

Boot mode configuration. . . . . . . . . . . . . . . . . . . . . . . . 115

5.1 Boot mode configuration inputs. . . . . . . . . . . . . . 115

5.2 Boot devices interfaces allocation. . . . . . . . . . . . 115

Package information and contact assignments . . . . . . 117

6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 117

Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

1 Introduction

The i.MX 8 Family consists of two processors:

i.MX 8QuadMax and 8QuadPlus. This data sheet covers

the i.MX 8QuadPlus processor, which is composed of

seven cores (one Arm Cortex -A72, four Arm

Cortex -A53, and two Arm Cortex -M4F), dual 32-bit

GPU subsystems, 4K H.265 capable VPU, and dual

failover-ready display controllers. This processor

supports a single 4K display (with multiple display

output options, including MIPI-DSI, HDMI, eDP/DP,

and LVDS), or multiple smaller displays. Memory

interfaces supporting LPDDR4, Quad SPI/Octal SPI

(FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a wide

range of peripheral I/Os such as PCIe 3.0, provide wide

flexibility. Advanced multicore audio processing is

supported by the Arm cores and a high performance

Tensilica HiFi 4 DSP for pre- and post-audio

processing as well as voice recognition.

NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of

its products.

Introduction

The i.MX 8QuadPlus processor offers numerous advanced features as shown in this table.

Table 1. i.MX 8QuadPlus advanced features

Function

Feature

Multicore architecture provides

4× Cortex-A53, 1× Cortex-A72 cores,

and 2× Cortex-M4F cores

AArch64 for 64-bit support and new architectural features

AArch32 for full backward compatibility with ARMv7

Cortex-A72 and Cortex-A53 cores support ARM virtualization extensions. sMMU

provides address virtualization to all subsystems.

Cortex-M4F cores for real-time applications

Graphics Processing Unit (GPU)

Video Processing Unit (VPU)

16× Vec4 shaders with 64 execution units. Split GPU architecture allows for dual

independent 8-Vec4 shader GPUs or a combined 16-Vec4 shader GPU.

Supports OpenGL 3.0, 2.1,; OpenGL ES 3.2, 3.1 (with AEP), 3.0, 2.0, and 1.1;

OpenCL 1.2 Full Profile and 1.1; OpenVG 1.1; and Vulkan

High-performance 2D Blit Engine

H.265 decode (4Kp60)

H.264 decode (4Kp30)

WMV9/VC-1 imple decode

MPEG 1 and 2 decode

AVS decode

MPEG4.2 ASP, H.263, Sorenson Spark decode

Divx 3.11 including GMC decode

ON2/Google VP6/VP8 decode

RealVideo 8/9/10 decode

JPEG and MJPEG decode

H.264 encode (1080p30)

Tensilica HiFi 4 DSP for pre- and

post-processing

666 MHz

Fixed-point and vector-floating-point support

32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and

64 KB of TCM)

Memory

64-bit LPDDR4 @1600 MHz

1× Quad SPI which can be used to connect to an FPGA

2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash

2× SD 3.0 card interfaces

1× eMMC5.1/SD3.0

RAW NAND (62-bit ECC support via BCH-62 module)

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Introduction

Table 1. i.MX 8QuadPlus advanced features (continued)

Feature

Function

Display Controller

Supports single UltraHD 4Kp60 display or up to 4 independent FullHD 1080p60

displays

Up to 18-layer composition

Complementary 2D blitting engines and online warping functionality

Integrated Failover Path (SafeAssure) to ensure display content stays valid even in

event of a software failure

Display I/O

2× MIPI-DSI with 4 lanes each

1× HDMI-TX/DisplayPort compliant with:

• HDMI

• eDP 1.4

• DP 1.3

This high performance serializer supports a pair of LVDS displays with 8 lanes each.

Each port can be configured for 2x Tx with 4 lanes each.

Camera I/O and video

Security

2× MIPI-CSI with 4-lanes each

Advanced High Assurance Boot (AHAB) secure & encrypted boot

Random Number Generator with a high-quality entropy source generator and

Hash_DRBG (based on hash functions)

RSA up to 4096, Elliptic Curve up to 1023

AES-128/192/256, DES, 3DES, MD5, SHA-1, SHA-224/256/384/512

Dedicated Security Controller for Flashless SHE and HSM support, Trustzone

Built-in ECDSA/DSA protocol support

See the security reference manual for this chip for a full list of security features.

• 2× I²C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core)

System Control

•

The tightly coupled M4 I²C ports cannot be used for general-purpose use

• System Control Unit (SCU):

•

Power control, clocks, reset

Boot ROMs

PMIC interface

Resource Domain Controller

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Introduction

Table 1. i.MX 8QuadPlus advanced features (continued)

Feature

Function

I/O

1× PCIe 3.0 (2-lanes). Can be used as two PCIe 3.0 controllers with one-lane,

independent operation. PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your

NXP representative.

1× USB 3.0 with PHY

2× USB 2.0 (1 with PHY, 1 with HSIC)

1× SATA 3.0 can be used as PCIe one-lane. This is in addition to the standard PCIe

controller. PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP

representative.

2× 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB)

3× CAN/CAN-FD

8× UARTs:

• 5× UARTs (2× with hardware flow control)

• 2× UARTs tightly coupled with Cortex-M4F cores (1× per Cortex-M4F core)

• 1× UART tightly coupled with SCU

18× I²C:

• 5× General-Purpose I²C (full-speed with DMA support)

• Low-speed I²C without DMA support:

•

2× master I²C in MIPI-DSI (1× per instance)

4× master I²C in LVDS (2× per instance)

2× master I²C in HDMI-TX

2× master I²C in MIPI-CSI (1× per instance)

Note: Although low-speed I²Cs can be made available for general purpose use

which requires the associated PHY (for example, MIPI) to be powered on, it is not

recommended.

Note: I/O muxing constraints prevent using all I²Cs simultaneously.

• 2x I2C tightly coupled with Cortex-M4 cores (1x per Cortex M4F core)

Note: The tightly coupled M4 I2C ports cannot be used for general purpose use.

• 1× I²C tightly coupled with SCU for communication with the PMIC. Not general

purpose and not available for non-PMIC uses.

4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only)

2× Enhanced Serial Audio Interface (ESAI)

× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly

connected to this module)

1× SPDIF (Tx and Rx)

2× 4-channel ADC converters

3.3 V/1.8 V GPIO

4× PWM channels

1× 6×8 KPP (Key Pad Port)

1× MQS (Medium Quality Sound)

4× SPI

Packaging

Case FCPBGA 29 x 29 mm, 0.75 mm pitch

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Architectural Overview

1.1

Ordering Information

The following table provides the ordering information.

Table 2. i.MX 8QuadPlus Orderable part numbers

Qualification

Part Number

Options Cortex-A72 Cortex-A53 Cortex-M4F

GPU

Package

Tier

MIMX8QP5AVUFFAB

MIMX8QP6AVUFFAB

1 x VPU

One @

1.6 GHz

Four @

1.2 GHz

Two @

264 MHz

Two @

625 MHz AEC-Q100

Automotive

^{29 mm}× 29 mm

0.75 mm pitch

FCPBGA (lidded)

1 x VPU

1 x DSP

1.2

System Controller Firmware (SCFW) Requirements

The i.MX 8 and 8X families require a minimum SCFW release version for correct operation and to prevent

potential reliability issues.

The SCFW is released as part of a Board Support Package (e.g. Linux, Android) which may vary in version

number for a specific BSP.

For example, 5.4.70_2.3.0 GA contains SCFW version 1.7.1. Whereas 5.10.0_1.0.0 GA contains SCFW

version 1.8.0.

The released SCFW version associated within each BSP is the minimum version required to correctly

support the wider BSP functionality.

Customers should always check that they are using the specific SCFW binary delivered within their chosen

BSP release. Customers should not mix newer BSP versions with older revisions of the SCFW.

1.3

Related resources

Table 3. Related resources

Description

Type

Reference manual

The i.MX 8QuadMax Applications Processor Reference Manual (IMX8QMRM) contains a

comprehensive description of the structure and function (operation) of the QuadPlus SoC.

Data sheet

Chip Errata

This data sheet includes electrical characteristics and signal connections.

The chip mask set errata provides additional and/or corrective information for a particular

device mask set.

Package drawing

Hardware guide

Package dimensions are provided in Section 6, “Package information and contact

assignments".”

The i.MX 8QuadMax/8QuadPlus Hardware Developer’s Guide (IMX8HWDG) provides

system design guidelines.

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 8QuadPlus processor system.

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

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Architectural Overview

2.1

Block Diagram

The following figure shows the functional modules in the processor system.

CPU1 Platform

CPU2 Platform

2x User CM4 Complexes

M4 Platform

4x ARM Cortex-A53

1x ARM Cortex-A72

M4 CPU

nvic

fpu

mpu

MCM

16KB system$

NEON

48KB I$

VFP

NEON

32KB I$

VFP

1x UART

(each)

MMCAU

16KB code$

32KB D$

256KB TCM w/ ECC

1x I2C

(each)

1MB L2 w/ optional ECC

1MB L2 w/ ECC

WDOG

RGPIO

LPIT

INTs

PWM

1x GPIO

(each)

LPUART

LPI2C

2x MU

Cache Coherent Interconnect (CCI-400)

I2C w/ DMA

UART (5 Mb/s)

CAN / CAN-FD

DMA Subsystem

External Memory Interface

2x ADC

2x eDMA

5x LPUART

4x LPSPI

5x LPI2C

2x FTM

DDR

64-bit LPDDR4

@1600 MHz

2x EVM SIM 3x FlexCAN

ADC

(4 channels each)

Controller

Audio Subsystem

x1 PCIe

2 lanes /

SPDIF TX / RX

ESAI TX / RX

2x ASRC

2x ESAI

8x SAI

SPDIF

HDMI TX SAI

ACM

High Speed I/O

2x PCIe

SATA

x2 PCIe

1 lane each

MQS

2x eDMA

2x SAI TX / RX

2x SAI RX

1x SATA 3.0 /

1x PCIe

(1 lane)

6x GPT

Audio Mixer

SSI Bus

RAW /

ONFI 3.2

NAND Flash

Imaging

Connectivity Subsystem

NAND

VPU Subsystem

2x LVDS

1/2 LVDS TX

(4 lanes each)

MJPEG MJPEG

DEC

ENC

Video Processing Unit

ISI

1x eMMC

5.1 / SD 3.0

LPI2C

1x I2C

VPU

3x uSDHC

USB3

2x SD 3.0 (UHS-I)

Display Controllers

2x DPU (4x LCD)

1x USB 3.0 PHY

LPI2C

DSP Core

HIFI4 DSP

1x I2C

1x USB 2.0

Host / HSIC

2x MIPI CSI2

(4-lanes)

2x MIPI

CSI2

32KB I$

448KB OCRAM

64KB TCM

48KB D$

2x USB2

2x ENET

1x USB 2.0

OTG, PHY

LPI2C

1x I2C

Graphics Processing Unit

2x GPU

2x MIPI

DSI

MIPI Display

(4-lanes)

10/100/1000M

Ethernet + AVB

LPI2C

1x I2C

System Control Unit

SJC

IOMUX

SCU CM4 Complex

M4 Platform

M4 CPU

Internal Memory

OCRAM (256KB)

HDMI Tx 2.0a

(eDP 1.4

DisplayPort 1.3)

Debug

Clock, Reset

Power Mgmt

HDMI

DAP, CTI, etc

Boot ROM

HAB

RDC

nvic

fpu

mpu

Tempmon

PMIC I/F

MMCAU

MCM

Security

16KB system$

16KB code$

Low Speed I/O

(LSIO) Subsystem

SECO

SNVS

OTP

256KB TCM w/ ECC

6x8 Keypad

32-bit GPIO

24M and 32k

XTALOSC

Sources

IEE

4x PWM

5x GPT

KPP

Security

Controller

(M0+)

WDOG

RGPIO

LPIT

INTs

PWM

ADM

14x MU

8x GPIO

2x Quad SPI /

1x Octal SPI

NOR Flash

LPUART

LPI2C

2x MU

CAAM

2x FlexSPI

Secure

JTAG

Dual Core, 16 shaders

Vulkan, OGLES 3.2 w/ AEP,

OCL 2.0, VG 1.1

Mult-format Decode

H.265 Dec (4k60)

H.264 Dec (1080p60)

H.264 Enc (1080p30)

RNG

1x GPIO

1x I2C

1x UART

Ciphers

(ECC, RSA)

Tamper

Detection

2D Blit Engine

Dedicated

64k Secure

RAM

Secure RTC

Figure 1. i.MX 8QuadPlus System Block Diagram

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

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Modules List

3 Modules List

The i.MX 8QuadPlus processors contain a variety of digital and analog modules. This table describes the

processor modules in alphabetical order.

Table 4. i.MX 8QuadPlus modules list

Block

Mnemonic

Block Name

Brief Description

ADC

Analog-to-Digital

Converter

The analog-to-digital converter (ADC) is a successive approximation ADC

designed for operation within a SoC.

APBH-DMA

NAND Flash and BCH The AHB-to-APBH bridge provides the chip with a peripheral attachment bus

ECC DMA Controller

running on the AHB's HCLK, which includes the AHB-to-APB PIO bridge for a

memory-mapped I/O to the APB devices, as well as a central DMA facility for

devices on this bus and a vectored interrupt controller for the Arm core.

A53

Arm (CPU1)

Arm (CPU2)

CPU cluster embedding 4x Cortex-A53 CPUs with a 32KB L1 instruction cache and

a 32KB data cache. The CPUs share a 1 MB L2 cache.

A72

CPU cluster embedding 1x Cortex-A72 CPU with a 48 KB L1 instruction cache and

32 KB data cache. The CPU has a 1MB L2 cache.

ASRC

Asynchronous Sample The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of

Rate Converter

a signal associated to an input clock into a signal associated to a different output

clock. The ASRC supports concurrent sample rate conversion of up to 10 channels

of about -120dB THD+N. The sample rate conversion of each channel is

associated to a pair of incoming and outgoing sampling rates. The ASRC supports

up to three sampling rate pairs.

BCH-62

CAAM

Binary-BCH ECC

Processor

The BCH62 module provides up to 62-bit ECC for NAND Flash controller (GPMI2)

Cryptographic

Accelerator and

Assurance Module

CAAM is a cryptographic accelerator and assurance module. CAAM implements

several encryption and hashing functions, a run-time integrity checker, and a

Pseudo Random Number Generator (PRNG).

CAAM also implements a Secure Memory mechanism. In this device the security

memory provided is 64 KB.

CTI

Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is

used by features of the Coresight infrastructure.

CTM

DAP

Cross Trigger Matrix

Debug Access Port

Cross Trigger Matrix IP is used to route triggering events between CTIs.

The DAP provides real-time access for the debugger without halting the core to:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan chains.

Display Controller

DRAM Controller

Dual display controller

DDR Controller

• Memory types: LPDDR4

• Two channels of 32-bit memory:

• LPDDR4 up to 1.6 GHz

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Modules List

Table 4. i.MX 8QuadPlus modules list (continued)

Block

Mnemonic

Block Name

Brief Description

DPR

Display/Prefetch/

Resolve

The DPR prefetches data from memory and converts the data to raster format for

display output. Raster source buffers can also be prefetched unconverted. The

resolve process supports graphics and video formatted tile frame buffers and

converts them to raster format. Embedded display memory is used as temporary

storage for data which is sourced by the display controller to drive the display.

eDMA

Enhanced Direct

Memory Access

• 4× eDMA with a total of 128 channels (note: all channels are not assigned; see

the product reference manual for more information):

• 4× instances with 32 channels each

• Programmable source, destination addresses, transfer size, plus support for

enhanced addressing modes

• Internal data buffer, used as temporary storage to support 64-byte burst

transfers, one outstanding transaction per DMA controller.

• Transfer control descriptor organized to support two-deep, nested transfer

operations

• Channel service request via one of three methods:

• Explicit software initiation

• Initiation via a channel-to-channel linking mechanism for continuous

transfers

• Peripheral-paced hardware requests (one per channel)

• Support for fixed-priority and round-robin channel arbitration

• Channel completion reported via interrupt requests

• Support for scatter/gather DMA processing

• Support for complex data structures via transfer descriptors

• Support to cancel transfers via software or hardware

• Each eDMA instance can be uniquely assigned to a different resource domain,

security (TZ) state, and virtual machine

• In scatter-gather mode, each transfer descriptor’s buffers can be assigned to

different SMMU translation

ENET

ESAI

Ethernet Controller

2× 1 Gbps Ethernet controllers supporting RGMII + AVB (Audio Video Bridging,

IEEE 802.1Qav)

Enhanced Serial Audio The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for

Interface

serial communication with a variety of serial devices, including industry-standard

codecs, SPDIF transceivers, and other processors. The ESAI consists of

independent transmitter and receiver sections, each section with its own clock

generator. All serial transfers are synchronized to a clock. Additional

synchronization signals are used to delineate the word frames. The normal mode

of operation is used to transfer data at a periodic rate, one word per period. The

network mode is also intended for periodic transfers; however, it supports up to 32

words (time slots) per period. This mode can be used to build time division

multiplexed (TDM) networks. In contrast, the on-demand mode is intended for

non-periodic transfers of data and to transfer data serially at high speed when the

data becomes available.

The ESAI has 12 pins for data and clocking connection to external devices.

FTM

FlexTimer

Provides input signal capture and PWM support

FlexCAN

Flexible Controller Area Communication controller implementing the CAN with Flexible Data rate (CAN FD)

Network protocol and the CAN protocol according to the CAN 2.0B protocol specification.

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Modules List

Table 4. i.MX 8QuadPlus modules list (continued)

Block Name Brief Description

Block

Mnemonic

FlexSpi (Quad

SPI/Octal SPI)

Flexible Serial

Peripheral Interface

• Flexible sequence engine to support various flash vendor devices, including

HyperBus™ devices:

• Support for FPGA interface

• Single, dual, quad, and octal mode of operation.

• DDR/DTR mode wherein the data is generated on every edge of the serial flash

clock.

• Support for flash data strobe signal for data sampling in DDR and SDR mode.

• Two identical serial flash devices can be connected and accessed in parallel for

data read operations, forming one (virtual) flash memory with doubled readout

bandwidth.

GIC

Generic Interrupt

Controller

The GIC-500 handles all interrupts from the various subsystems and is ready for

virtualization.

GPIO

GPMI

General Purpose I/O

Modules

Used for general purpose input/output to external devices. Each GPIO module

supports 32 bits of I/O.

^{General Purpose Media The GPMI module supports up to 8}× NAND devices. 62-bit ECC (BCH)

Interface

encryption/decryption for NAND Flash controller (GPMI). The GPMI supports

separate DMA channels per NAND device.

GPT

General Purpose Timer Each GPT is a 32-bit “free-running” or “set and forget” mode timer with

programmable prescaler and compare and capture register. A timer counter value

can be captured using an external event and can be configured to trigger a capture

event on either the leading or trailing edges of an input pulse. When the timer is

configured to operate in “set and forget” mode, it is capable of providing precise

interrupts at regular intervals with minimal processor intervention. The counter has

output compare logic to provide the status and interrupt at comparison. This timer

can be configured to run either on an external clock or on an internal clock.

GPU

Graphics Processing

HDMI Tx interface

Audio Processor

I²C Interface

2× GC7000XSVX GPUs with 8 shaders each that can run either independently or

in “dual-mode” with 16 shaders.

HDMI Tx/

DP/eDP

HDMI transmitter, Display Port 1.3 and embedded Display Port 1.4

HiFi 4 DSP

A highly optimized audio processor geared for efficient execution of audio and

voice codecs and pre- and post-processing modules to offload the Arm core.

I²C

I²C provides serial interface for external devices.

IEE

• Supports direct encryption and decryption of FlexSPI memory type

• Provides decryption services (lower performance) for DRAM traffic

• Supports I/O direct encrypted storage and retrieval

• Support for a number of cryptographic standards:

• 128/256-bit AES Encryption (AES-CTR, AES-XTS mode options)

• Multiple keys supported:

• Loaded via secure key channel from security block

• Key selection is per access and based on source of transaction

IOMUXC

IOMUX Control

This module enables flexible I/O multiplexing. Each I/O pad has default and several

alternate functions. The alternate functions are software configurable.

JPEG/dec

MJPEG engine for

decode

Provides up to 4-stream decoding in parallel.

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Modules List

Table 4. i.MX 8QuadPlus modules list (continued)

Block Name Brief Description

Provides up to 4-stream encoding in parallel.

Block

Mnemonic

JPEG/enc

KPP

MJPEG engine for

encode

Key Pad Port

The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 6 x 8 keypad

matrix interface or as general purpose input/output (I/O).

LPIT-1

LPIT-2

Low-Power Periodic

Interrupt Timer

Each LPIT is a 32-bit “set and forget” timer that starts counting after the LPIT is

enabled by software. It is capable of providing precise interrupts at regular intervals

with minimal processor intervention. It has a 12-bit prescaler for division of input

clock frequency to get the required time setting for the interrupts to occur, and

counter value can be programmed on the fly.

LPSPI 0–3

LVDS

Configurable SPI

LVDS Display Bridge

Arm (CPU3)

Full-duplex enhanced Synchronous Serial Interface. It is configurable to support

Master/Slave modes, four chip selects to support multiple peripherals.

This high performance serializer supports a pair of LVDS displays with 8 lanes

each. Each port can be configured for 2x Tx with 4 lanes each.

M4F

• Cortex-M4F core

• AHB LMEM (Local Memory Controller) including controllers for TCM and cache

memories

• 256 KB embedded tightly coupled memory(TCM) (128 KB TCMU, 128 KB

TCML)

• 16 KB Code Bus Cache

• 16 KB System Bus Cache

• ECC for TCM memories and parity for code and system caches

• Integrated Nested Vector Interrupt Controller (NVIC)

• Wakeup Interrupt Controller (WIC)

• FPU (Floating Point Unit)

• Core MPU (Memory Protection Unit)

• Support for exclusive access on the system bus

• MMCAU (Crypto Acceleration Unit)

• MCM (Miscellaneous Control Module)

MIPI CSI-2

MIPI-DSI

MIPI CSI-2 Interface

MIPI DSI interface

The MIPI CSI-2 IP provides MIPI CSI-2 standard camera interface ports. The MIPI

CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes

The MIPI DSI IP provides DSI standard display serial interface. The DSI interface

supports 80 Mbps to 1.5 Gbps speed per data lane.

MQS

Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality

PWM-like audio via two standard digital GPIO pins.

OCOTP_CTRL

OTP Controller

The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading,

programming, and/or overriding identification and control information stored in

on-chip fuse elements. The module supports electrically-programmable poly fuses

(eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible

signals that can be used for software control of hardware elements, not requiring

non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for

interfacing with on-chip fuse elements. Among the uses for the fuses are unique

chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,

boot characteristics, and various control signals requiring permanent nonvolatility.

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Modules List

Table 4. i.MX 8QuadPlus modules list (continued)

Block Name Brief Description

Block

Mnemonic

OCRAM

On-Chip Memory

Controller

The On-Chip Memory controller (OCRAM) module is designed as an interface

between the system’s AXI bus and the internal (on-chip) SRAM memory module.

The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit

AXI bus.

PCIe

PRG

PCI Express 3.0

PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable; contact your NXP representative.

Prefetch/Resolve

Gasket

The PRG is a gasket which translates system memory accesses to local display

RTRAM accesses for display refresh. It works with the DPR to complete the

prefetch and resolving operations needed to drive the display.

PWM

Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images and it can also generate tones.

It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms.

RAM

64 KB Secure

RAM

Secure/non-secure

RAM

Secure/non-secure Internal RAM, interfaced through the CAAM.

RAM

Internal RAM

Internal RAM, which is accessed through OCRAM memory controllers.

256 KB

RNG

Random Number

Generator

The purpose of the RNG is to generate cryptographically strong random data. It

uses a true random number generator (TRNG) and a pseudo-random number

generator (PRNG) to achieve true randomness and cryptographic strength. The

RNG generates random numbers for secret keys, per message secrets, random

challenges, and other similar quantities used in cryptographic algorithms.

SAI

I2S/SSI/AC97 Interface The SAI module provides a synchronous audio interface that supports full duplex

serial interfaces with frame synchronization, such as I2S, AC97, TDM, and

codec/DSP interfaces.

SECO

SJC

Security Controller

Core and associated memory and hardware responsible for key management.

Secure JTAG Controller The SJC provides the JTAG interface, which is compatible with JTAG TAP

standards, to internal logic. This device uses JTAG port for production, testing, and

system debugging. Additionally, the SJC provides BSR (Boundary Scan Register)

standard support, which is compatible with IEEE1149.1 and IEEE1149.6 standards.

The JTAG port must be accessible during platform initial laboratory bring-up, for

manufacturing tests and troubleshooting, as well as for software debugging by

authorized entities. The SJC incorporates three security modes for protecting

against unauthorized accesses. Modes are selected through eFUSE configuration.

sMMU

SNVS

SPDIF

System MMU

The System MMU is an MMU-500 from Arm. It supports two-stage address

translation and multiple translation contexts.

Secure Non-Volatile

Storage

Secure Non-Volatile Storage, including Secure Real Time Clock, Security State

Machine, Master Key Control.

Sony Philips Digital

Interconnect Format

The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that

allows the processor to receive and transmit digital audio. The SPDIF transceiver

allows the handling of both SPDIF channel status (CS) and User (U) data and

includes a frequency measurement block that allows the precise measurement of

an incoming sampling frequency.

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Modules List

Table 4. i.MX 8QuadPlus modules list (continued)

Block

Mnemonic

Block Name

Brief Description

TEMPMON

Temperature Monitor

The temperature monitor/sensor IP module for detecting high temperature

conditions. The temperature read out does not reflect case or ambient temperature.

It reflects the temperature in proximity of the sensor location on the die.

Temperature distribution may not be uniformly distributed; therefore, the read-out

value may not be the reflection of the temperature value for the entire die.

UART

UART Interface

• High-speed TIA/EIA-232-F compatible, up to 5.0 Mbps

• Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)

• 9-bit or Multidrop mode (RS-485) support (automatic slave address detection)

• 7, 8, 9, or 10-bit data characters (7-bits only with parity)

• 1 or 2 stop bits

• Programmable parity (even, odd, and no parity)

• Hardware flow control support for request to send (RTS_B) and clear to send

(CTS_B) signals

USB3/USB2

The USB3/USB2 OTG module has been specified to perform USB 3.0 dual role and

USB 2.0 On-The-Go (OTG) compatible with the USB 3.0, and USB 2.0

specification with OTG supplementary specifications. This controller supports

^{twoindependent USB cores (1}× USB3.0 dual-role, 1× USB2.0 OTG) and includes

the PHY and I/O interfaces to support this operation. The full pinout of the USB 3.0

controller includes the signaling for both USB 3.0 and USB 2.0. This does not

mean there is a separate USB 2.0 controller that can be used independently and

simultaneously with USB 3.0. This device has an additional separate,

independent USB 2.0 OTG controller which can be used simultaneously with this

USB 3.0. Specific features requested for this updated module:

• Super Speed (5 Gbps), High Speed (480 Mbps), full speed (12 Mbps) and low

speed (1.5 Mbps)

• Fully compatible with the USB 3.0 specification (backward compatible with USB

2.0)

• Fully compatible with the USB On-The-Go supplement to the USB 2.0

specification

• Hardware support for OTG signaling

• Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

implemented in hardware, which can also be controlled by software

USBOH

The USBOH module has been specified which performs USB 2.0 On-The-Go

(OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG

supplement and HS IC-USB specification. This controller supports two

^{independent USB cores (1}× USB2.0 OTG, 1× USB2.0 Host) and includes the PHY

and I/O interfaces to support this operation.

Key features:

• One USB2.0 OTG controller

• High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps)

• Fully compatible with the USB 2.0 specification

• Fully compatible with the USB On-The-Go supplement to the USB 2.0

specification

• Hardware support for OTG signaling

• Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

implemented in hardware, which can also be controlled by software

• USB2.0 Host with HS IC-USB specification

• HS IC-USB transceiver-less downstream support (Host only).

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Modules List

Table 4. i.MX 8QuadPlus modules list (continued)

Block Name Brief Description

Block

Mnemonic

uSDHC

SD/eMMC and SDXC

i.MX 8 Family SoC-specific characteristics:

Enhanced Multi-Media All three MMC/SD/SDIO controller IPs are identical and are based on the uSDHC

Card / Secure Digital

Host Controller

IP.

The uSDHC is a host controller used to communicate with external low cost data

storage and communication media. It supports the previous versions of the

MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the

uSDHC supports:

• SD Host Controller Standard Specification v3.0 with the exception that all the

registers do not match the standards address mapping.

• SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50)

• SDIO specification v3.0

• eMMC System Specification v5.1

VPU

Video Processing Unit See the device reference manual for the complete list of the VPU’s

decoding/encoding capabilities.

WDOG

Watchdog

The Watchdog Timer supports two comparison points during each counting period.

Each of the comparison points is configurable to evoke an interrupt to theArm core,

and a second point evokes an external event on the WDOG line.

XTAL OSC24M

XTAL OSC32K

The 24 MHz clock source is an external crystal that acts as the main system clock.

The OSC24M is used as the source clock for subsystem PLLs. OSC24M can be

turned off by the System Control Unit (SCU) during sleep mode.

The 32.768 kHz clock source is an external crystal. The OSC32K is intended to be

always on and is distributed by the SCU to modules in the chip.

3.1

Special Signal Considerations

Special signal considerations can be found in the Hardware Developer’s Guide for this device in the

Design Checklist section.

3.2

Recommended Connections for Unused Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused

Input/Output Terminations,” in the Hardware Developer’s Guide for this device.

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Electrical characteristics

4 Electrical characteristics

This section provides the device and module-level electrical characteristics for these processors.

4.1

Chip-level conditions

This section provides the device-level electrical characteristics for the SoC. See the following table for a

quick reference to the individual tables and sections.

Table 5. Chip-level conditions

For these characteristics, …

Absolute maximum ratings

Topic appears …

on page 15

on page 17

on page 21

on page 48

on page 25

FCPBGA package thermal resistance data

Operating ranges

External Input Clock Frequency

Maximum supply currents

Standby use cases

USB 2.0 PHY typical current consumption in Power-Down

Mode

USB 3.0 PHY typical current consumption in Power-Down

Mode

on page 25

Typical current consumption in Power-Down mode for USB

2.0 PHY embedded in USB 3.0 PHY

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 6 may affect reliability or cause

permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions beyond those

indicated in the “Operating ranges” or other parameter tables is not implied.

Exposure to absolute-maximum-rated conditions for extended periods will

affect device reliability.

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Electrical characteristics

Table 6. Absolute maximum ratings

Symbol

Parameter Description

Min

Max

Units

Core Supplies Input Voltage

VDD_A72

-0.3

1.2

VDD_A53

VDD_GPU0

VDD_GPU1

VDD_MAIN

VDD_MEMC

DDR PHY supplies

1.0V IO supplies

VDD_DDR_VDDQ

-0.3

1.75

1.2

VDD_MIPI_1P0

VDD_USB_OTG_1P0

VDD_ADC_1P8

IO Supply for GPIO Type

1.8V IO Single supply

-0.5

2.1

VDD_ADC_DIG_1P8

VDD_ANA0_1P8 (IO, analog,OSC SCU)

VDD_ANA1_1P8 (IO, analog,OSC SCU)

VDD_DDR_PLL_1P8 (memory PLLs)

VDD_MIPI_1P8 (PHY, GPIO)

VDD_MIPI_CSI_DIG_1P8 (PHY, GPIO)

VDD_PCIE_1P8 (PHY)

VDD_USB_1P8 (PHY, GPIO)

VDD_ENET1_1P8_2P5_3P3

VDD_ENET0_1P8_3P3

IO Supply for GPIO Type

1.8 / 2.5 / 3.3V IO Tri-voltage Supply

-0.3

3.8

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Electrical characteristics

Table 6. Absolute maximum ratings (continued)

Parameter Description

Symbol

Min

Max

Units

IO Supply for GPIO Type

1.8 / 3.3V IO Dual Voltage Supply

VDD_CAN_UART_1P8_3P3

VDD_CSI_1P8_3P3

-0.3

3.8

VDD_EMMC0_1P8_3P3

VDD_EMMC0_VSELECT_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_PCIE_DIG_1P8_3P3

VDD_QSPI0A_1P8_3P3

VDD_QSPI0B_1P8_3P3

VDD_SPI_MCLK_UART_1P8_3P3

VDD_SPI_SAI_1P8_3P3

VDD_TMPR_CSI_1P8_3P3

VDD_USB_3P3 (PHY & GPIO)

VDD_USDHC1_1P8_3P3

VDD_USDHC1_VSELECT_1P8_3P3

VDD_SNVS_4P2

SNVS Coin Cell

-0.3

4.3

3.63

5.5

USB VBUS (OTG2)

USB VBUS (OTG1)

I/O Voltage for USB Drivers

USB_OTG2_VBUS

USB_OTG1_VBUS

USB_OTG1_DP/USB_OTG1_DN

USB_OTG2_DP/USB_OTG2_DN

ADC_INx

3.63

I/O Voltage for ADC

-0.1

2.1

Vin/Vout input/output voltage range (GPIO Vin/Vout

Type Pins)

See Section 4.6.1

Vin/Vout input/output voltage range (DDR Vin/Vout

pins)

See Section 4.6.1

ESD immunity (HBM).

ESD immunity (CDM).

Storage temperature range

Vesd_HBMX

—

1000

250

Vesd_CDM

Tstorage

-40

150

°C

NOTE

HDMI CEC is 3.3V tolerant. HDMI DDC signals and HPD are 5V tolerant.

Refer to the Hardware Developer’s Guide for proper terminations.

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Electrical characteristics

4.1.2

Thermal resistance

4.1.2.1

FCPBGA package thermal resistance

This table provides the FCPBGA package thermal resistance data.

Table 7. FCPBGA package thermal resistance data

29x29 mm

Unit

Rating

Board Type¹

Symbol

package

Junction to Ambient Thermal Resistance²

Junction to Package Top Thermal Resistance²

Junction to Case Thermal Resistance³

JESD51-9, 2s2p

JESD51-9, 1s

R_θJA

Ψ_JT

12.9

0.1

°C/W

R_θJC

0.3

Thermal test board meets JEDEC specification for this package (JESD51-9).

Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant

to predict the performance of a package in an application-specific environment.

Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold surface

temperature at the package top side dead center.

4.1.3

Operating Ranges

The following table provides the operating ranges of these processors.

Table 8. Operating ranges

Symbol

Description

Mode

Min Typ Max Unit

Comments

VDD_A72²

VDD_A53²

Power supply Overdrive 1.05 1.10 1.15

of Cortex-A72

Min frequency = 208.5 MHz

Max frequency = 1.6 GHz

cluster

Nominal 0.95 1.00 1.10

Max frequency = 1.06 GHz

Power supply Overdrive 1.05 1.10 1.15

of Cortex-A53

Min frequency = 208.5 MHz

Max frequency = 1.2 GHz

cluster

Nominal 0.95 1.00 1.10

Max frequency = 900 MHz

VDD_GPU0

VDD_GPU1

VDD_MEMC

Power supply

of first GPU

instance

Nominal 0.95 1.00 1.10

Max frequencies:

Shaders = 625 MHz;

Core = 625 MHz

Power supply

of second

GPU instance

Max frequencies.:

Shaders = 625 MHz;

Core = 625 MHz

Power supply

of memory

controller

N/A

1.05 1.10 1.15

—

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Electrical characteristics

Table 8. Operating ranges (continued)

Symbol

Description

Mode

Min Typ Max Unit

Comments

Max frequencies:

HiFi4 DSP = 666 MHz

M4 = 264 MHz

VDD_MAIN³

Power supply

of remaining

core logic

N/A

0.95 1.00 1.10

VPU = 600 MHz

VDD_DDR_CH0_VDDQ,

VDD_DDR_CH0_VDDQ_CKE,

VDD_DDR_CH1_VDDQ,

Power

supplies of

memory I/Os

LPDDR4 1.06 1.10 1.17

Max frequency = 1.6 GHz

Supports LPDDR4-3200

VDD_DDR_CH1_VDDQ_CKE,

VDD_DDR_CH0_VDDA_PLL_1P8, Power

N/A

1.65 1.80 1.95

0.95 1.00 1.10

PLL supply can be merged with

other 1.8V supplies with proper

on board decoupling.

VDD_DDR_CH1_VDDA_PLL_1P8

supplies of

memory PLLs

VDD_MIPI_CSI0_1P0,

VDD_MIPI_CSI1_1P0,

VDD_MIPI_DSI0_1P0,

VDD_MIPI_DSI0_PLL_1P0,

VDD_MIPI_DSI1_1P0,

VDD_MIPI_DSI1_PLL_1P0,

VDD_LVDS0_1P0,

Power

These balls shall be connected to

the same power supply as

VDD_MAIN. It shall be a star

connection from the power

supply. Each VDD power supply

ball shall have its own dedicated

decoupling caps.

supplies of

PHYs (1.0 V

part)

VDD_LVDS1_1P0

VDD_ANA1_1P8, VDD_ANA2_1P8, Power

N/A

1.65 1.70 1.75

These balls shall be powered by a

dedicated supply.

VDD_ANA3_1P8, VDD_CP_1P8,

VDD_SCU_1P8,

VDD_SCU_ANA_1P8,

VDD_SCU_XTAL_1P8

supplies of

I/Os, analog

and oscillator

of the SCU

Note: The disconnect between

the ball naming, implying a 1.8 V

supply, and the actual required

operating voltage of 1.7 V is

known and correct as shown.

VDD_PCIE_IOB_1P8,

VDD_ADC_1P8,

VDD_ADC_DIG_1P8,

VDD_HDMI_RX0_1P8⁴,

VDD_HDMI_TX0_1P8,

VDD_LVDS0_1P8,

Power

1.65 1.80 1.95

—

supplies of

PHYs (1.8 V

part) and

GPIO

operating at

1.8 V only.

VDD_LVDS1_1P8,

VDD_MIPI_CSI0_1P8,

VDD_MIPI_CSI1_1P8,

VDD_MIPI_DSI0_1P8,

VDD_MIPI_DSI1_1P8,

VDD_MLB_1P8⁵,

VDD_PCIE_LDO_1P8,

VDD_PCIE_SATA0_PLL_1P8⁴,

VDD_PCIE0_PLL_1P8,

VDD_PCIE1_PLL_1P8,

VDD_USB_HSIC0_1P8,

VDD_ANA0_1P8,

VDD_MIPI_CSI_DIG_1P8

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Electrical characteristics

Table 8. Operating ranges (continued)

Symbol

Description

Mode

Min Typ Max Unit

Comments

VDD_HDMI_RX0_VH_RX_3P3⁴,

VDD_HDMI_TX0_DIG_3P3,

VDD_USB_OTG1_3P3,

VDD_USB_OTG2_3P3,

VDD_USB_SS3_TC_3P3

Power

N/A

3.00 3.30 3.60

—

supplies of

PHYs (3.3 V

part) and

GPIO

operating at

3.3 V only

VDD_PCIE_DIG_1P8_3P3,

VDD_ENET0_1P8_3P3,

VDD_ENET_MDIO_1P8_3P3,

VDD_EMMC0_1P8_3P3,

Power

supplies of

GPIO

supporting

both 1.8 V or

3.3 V

1.8 V

3.3 V

1.65 1.80 1.95

3.00 3.30 3.60

When VDD_USDHC1_1P8_3P3

or VDD_USDHC2_1P8_3P3 is

used to support an SD card then

it shall be on a dedicated

1.8V/3.3V regulator.

When VDD_SIM0_1P8_3P3 is

used to support a SIM card, it

shall be on a dedicated 1.8V/3.3V

regulator.

VDDs of this list targeting 1.8V

can share 1.8V regulator of 1.8V

only VDDs

VDDs of this list targeting 3.3V

can share 3.3V regulator of 3.3V

only VDDs

VDD_USDHC1_1P8_3P3,

VDD_USDHC2_1P8_3P3,

VDD_USDHC_VSELECT_1P8_3P3,

VDD_SIM0_1P8_3P3,

VDD_ESAI0_MCLK_1P8_3P3,

VDD_ESAI1_SPDIF_SPI_1P8_3P3,

VDD_FLEXCAN_1P8_3P3,

VDD_LVDS_DIG_1P8_3P3,

VDD_M4_GPT_UART_1P8_3P3,

VDD_MIPI_DSI_DIG_1P8_3P3,

VDD_MLB_DIG_1P8_3P3⁶,

VDD_QSPI0_1P8_3P3,

VDD_QSPI1A_1P8_3P3,

VDD_SPI_SAI_1P8_3P3

VDD_ENET1_1P8_2P5_3P3

Power

supplies of

ethernet I/Os

1.8 V

2.5 V

3.3 V

N/A

1.65 1.80 1.95

2.38 2.50 2.63

3.00 3.30 3.60

1.1 1.2 1.3

—

VDD_USB_HSIC0_1P2

VDD_SNVS_4P2

Power supply

of USB-HSIC

I/Os

Power supply

of SNVS

N/A

2.80 3.30 4.20

It can be supplied by a backup

battery: a coin cell or a super cap.

Output of embedded LDOs and negative charge pump

VDD_USB_SS3_LDO_1P0_CAP,

1.0 V output of

N/A

—

1.00

—

VDD_HDMI_RX0_LDO0_1P0_CAP⁴embedded

LDOs

VDD_HDMI_RX0_LDO1_1P0_CAP⁴

, VDD_HDMI_TX0_LDO_1P0_CAP,

VDD_PCIE_LDO_1P0_CAP

VDD_SNVS_LDO_1P8_CAP

1.8 V output of

SNVS

N/A

—

1.80

—

embedded

LDO

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Electrical characteristics

Table 8. Operating ranges (continued)

Symbol

Description

Mode

Min Typ Max Unit

-1.80

Comments

VDD_M1P8 _CAP

-1.8 V output

of embedded

charge pump

N/A

—

Power supplies that shall be connected to output of an embedded LDO

VDD_HDMI_TX0_1P0

—

N/A

—

1.00

—

Shall be externally connected to

VDD_HDMI_TX0_LDO_1P0_CA

VDD_PCIE_SATA0_1P0⁴,

VDD_PCIE0_1P0, VDD_PCIE1_1P0

—

N/A

—

1.00

—

Shall be externally connected to

VDD_PCIE_LDO_1P0_CAP

VDD_USB_OTG1_1P0,

VDD_USB_OTG2_1P0

Shall be externally connected to

VDD_USB_SS3_LDO_1P0_CA

Junction temperature

-40

Junction temperature

—

125 °C

—

Voltage ranges are defined to group as many supplies as possible. Individual supplies may have a wider range than listed here.

These are the supported frequencies included in the Linux, Android, and all other operating systems using the SCU defined

DVFS (Dynamic Voltage and Frequency Scaling) set points. An additional Overdrive set point is included to provide a more

balanced power-versus-performance trade-off, where the A72 runs at 1.3 GHz and the A53 runs at 1.1 GHz. Likewise, an

additional Nominal set point is included where both the A72 and A53 run at 600 MHz.

During low power state, this voltage can be dropped to 0.8 V +/- 3% for retention.

HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected

HDMI-RX support will be enabled.

MLB is not supported on this product. This MLB power rail may be tied to the power supply voltage indicated or may be

terminated, per the Hardware Developer’s Guide power supplies of unused functions.

MLB is not supported on this product. The MLB power rail must be tied to the power supply voltage indicated if other I/O

functions are used, as determined by IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer’s

Guide power supplies of unused functions.

4.1.4

External clock sources

Each processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency

(XTALI).

The RTC_XTALI is used for real time functions. It supplies the clock for real time clock operation and for

slow-system and watchdog counters. The clock input can be connected to either an external oscillator or a

crystal using the internal oscillator amplifier.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input requires a crystal using the internal oscillator amplifier.

The PCIe oscillator can be sourced internally or input to the chip. In both cases, it is a 100 MHz nominal

clock using HCSL signaling to provide the PCIe reference clock.

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Electrical characteristics

The following table shows the interface frequency requirements.

Table 9. External Input Clock Frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator^1,2

XTALI Oscillator^4,2

PCIe oscillator⁵

f_ckil

f_xtal

f_100M

—

32.768³/32.0

—

kHz

MHz

ppm

100

—

Frequency accuracy

±300

External oscillator or a crystal with internal oscillator amplifier.

The required frequency stability of this clock source is application dependent. For recommendations, see the hardware

development guide for this device.

Recommended nominal frequency 32.768 kHz.

Fundamental frequency crystal with internal oscillator amplifier.

If using an external clock instead of the internal clock source, an HCSL-compatible clock is required. Concerning EMI/EMC,

note that internal source is not spread-spectrum capable.

The typical values shown in Table 9 are required for use with NXP board support packages (BSPs) to

ensure precise time keeping and USB and HDMI operations.

4.1.5

Maximum Supply Currents

NOTE

Some of the numbers shown in this table are based on the companion

regulator limits and not actual use cases. Current-drain application note

AN13249 is also available for reference. This document contains measured

results for i.MX 8QuadMax and should be used as a guideline for i.MX

8QuadPlus.

Table 10. Maximum supply currents

Symbol

Value Unit

Comments

VDD_A72

3500 mA Value based on max current delivered by PMIC

2500 mA Value based on max current delivered by PMIC

3500 mA Value based on max current delivered by PMIC

5000 mA Value based on max current delivered by PMIC

3200 mA Value based on max current delivered by PMIC

VDD_A53

VDD_GPU0

VDD_GPU1

VDD_MAIN

VDD_MEMC

VDD_DDR_CH0_VDDQ

800

200

mA Does not include current used by external memory.

VDD_DDR_CH0_VDDQ_CKE

VDD_DDR_CH0_VDDA_PLL_1P8

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Electrical characteristics

Symbol

Table 10. Maximum supply currents (continued)

Value Unit Comments

mA Does not include current used by external memory.

VDD_DDR_CH1_VDDQ

VDD_DDR_CH1_VDDQ_CKE

VDD_DDR_CH1_VDDA_PLL_1P8

VDD_SCU_ANA_1P8

800

200

mA Does not include current used by external memory.

VDD_SCU_1P8

175

140

110

mA Digital I/Os of SCU

VDD_CP_1P8

ma There is a peak current of 60mA over 140 μs.

VDD_SCU_XTAL_1P8

VDD_ANA0_1P8

mA Supply of crystal oscillator and integrated 200 MHz oscillator

VDD_ANA1_1P8

VDD_ANA2_1P8

VDD_ANA3_1P8

VDD_SIM0_1P8_3P3

VDD_M4_GPT_UART_1P8_3P3

VDD_ESAI1_SPDIF_SPI_1P8_3P3

VDD_ESAI0_MCLK_1P8_3P3

VDD_SPI_SAI_1P8_3P3

VDD_FLEXCAN_1P8_3P3

VDD_QSPI1A_1P8_3P3

VDD_QSPI0_1P8_3P3

VDD_EMMC0_1P8_3P3

VDD_USDHC_VSELECT_1P8_3P3

VDD_USDHC1_1P8_3P3

VDD_USDHC2_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_3P3

VDD_ENET1_1P8_2P5_3P3

VDD_LVDS_DIG_1P8_3P3

VDD_LVDSx_1P8

100

mA x is 0 or 1

VDD_LVDSx_1P0

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_MIPI_DSIx_1P8

mA x is 0 or 1

VDD_MIPI_DSIx_1P0

VDD_MIPI_DSIx_PLL_1P0

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Electrical characteristics

Table 10. Maximum supply currents (continued)

Value Unit Comments

Symbol

VDD_MIPI_CSI_DIG_1P8

VDD_MIPI_CSIx_1P8

VDD_MIPI_CSIx_1P0

VDD_HDMI_TX0_DIG_3P3

VDD_HDMI_TX0_1P8

VDD_HDMI_TX0_1P0

VDD_ADC_1P8

mA x is 0 or 1

mA Shall be externally connected to VDD_HDMI_TX0_LDO_1P0_CAP

VDD_ADC_DIG_1P8

VDD_MLB_DIG_1P8_3P3¹

VDD_MLB_1P8²

VDD_USB_OTG1_1P0

VDD_USB_OTG1_3P3

VDD_USB_OTG2_1P0

VDD_USB_OTG2_3P3

VDD_USB_SS3_TC_3P3

VDD_USB_HSIC0_1P2

VDD_USB_HSIC0_1P8

VDD_PCIE_DIG_1P8_3P3

VDD_PCIE_IOB_1P8

VDD_PCIE_LDO_1P8

VDD_PCIE_SATA0_PLL_1P8

VDD_PCIE0_PLL_1P8

VDD_PCIE1_PLL_1P8

VDD_PCIE_SATA0_1P0

VDD_PCIE0_1P0

mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP

190

mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP

mA Start-up current

VDD_PCIE1_1P0

VDD_SNVS_4P2³

MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Table 8 if other I/O functions

are used, as determined by IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer’s Guide

power supplies of unused functions.

MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated,

per the Hardware Developer’s Guide power supplies of unused tables.

Under normal operating conditions, the maximum current on VDD_SNVS_4P2 is shown Table 11. During initial power on,

VDD_SNVS_4P2 can draw up to 5 mA if the supply is capable of sourcing that current. If less than 5 mA is available, the

VDD_SNVS_LDO_1P8_CAP charge time will increase.

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Electrical characteristics

4.1.6

Low power mode supply currents

The following table shows the current core consumption (not including I/O) in selected low power modes.

Table 11. i.MX 8QuadPlus Key State (KSx) power consumption

Mode

Test conditions

Supply

Max

Unit

KS0 SNVS only, all other supplies OFF. RTC running,

tamper not active, external 32K crystal.

VDD_SNVS_4P2 (4.2 V)

μA

KS1¹RAM and IO state retained.

DRAM in self-refresh, associated I/O’s OFF.

32K running, 24M, PLLs and ring oscillators OFF

PHYs are in idle state.

VDD_ANAx_1P8, VDD_SCUx_1P8,

VDD_CP_1P8 (1.7V)

VDD_A53 (OFF)

VDD_A72 (OFF)

VDD_GPU0 (OFF)

VDD_GPU1 (OFF)

VDD_MEMC (OFF)

VDD_DDR_CHx_VDDQ (1.1V)

VDD_MAIN (0.8V)

Total

—

MEMC, A53, A72, and GPU supplies OFF.

MAIN²dropped to 0.8 V.

—

1.4

21.94

1066

2000

KS4³Leakage test, not intended as a customer use case. VDD_A53 (1.1V)

Overdrive conditions set, memories active, all

VDD_A72 (1.1V)

sub-systems powered ON.

Active power minimized.

VDD_GPU0 (1.0V)

See

footnote⁴

VDD_GPU1 (1.0V)

See

footnote⁴

VDD_MEMC (1.1V)

VDD_MAIN (1.0V)

Total

1800

1500

Maximum values are for 25 °C T_ambient

0.8 V nominal—voltage specification under this case is ± 3%.

Maximum values are for 125 °C T_junction. Stated supply voltages do not exceed +2% during test.

Unavailable at time of publication.

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4.1.7

USB 2.0 PHY typical current consumption in Power-Down mode

In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.

The following table shows the USB interface typical current consumption in Power-Down mode.

Table 12. USB 2.0 PHY typical current consumption in Power-Down Mode

VDD_USB_OTG1_3P3 (3.3 V)

VDD_ANA0_1P8 (1.8 V)

VDD_USB_OTG1_1P0 (1.0 V)

Current

1 μA

0.06 μA

0.5 μA

4.1.8

USB 3.0 PHY typical current consumption in Power-Down mode

In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.

The following table shows the USB interface typical current consumption in Power-Down mode.

Table 13. USB 3.0 PHY typical current consumption in Power-Down Mode

—

VDD_ANA0_1P8 (1.8 V)

VDD_USB_OTG2_1P0 (1.0 V)

Current

—

10 μA

70 μA

The following table shows the current consumption for the USB 2.0 PHY embedded in the USB 3.0

PHY.

Table 14. Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY

VDD_USB_OTG2_3P3 (3.3 V)

VDD_ANA0_1P8 (1.8 V)

VDD_USB_OTG2_1P0 (1.0 V)

Current—Host mode

22.6 μA

12.6 μΑ

12.7 μΑ

85.7 μΑ

81.5 μΑ

78.5 μΑ

Current—Device mode

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4.2

Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to ensure the reliable operation of the device. Any deviation from

these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor

4.2.1

Power-up sequence

The device has the following power-up sequence requirements:

•

Supply group 0 (SNVS) must be powered first. It is expected that group 0 will typically remain

always on after the first power-on.

Supply group 1 (MAIN and SCU) and group 0 must both be powered to their nominal values prior

to boot. They must power up after or simultaneously with group 0.

Supply group 2 (I/O’s and DDR interface) consists of those modules required to start the boot

process by accessing external storage devices. These must be fully powered prior to POR release

if booting from one of these supplies interfaces. They must power up after or simultaneously with

group 1.

•

Supply group 3 consists of the remaining portions of the SoC. This includes nonboot I/O voltages

and supplies for the major computational units. These can be sequenced in any order and as

required to perform the desired functions for the intended application. They must power up after

or simultaneously with group 2.

NOTE

The definition of “power-up” refers to a stable voltage operating within the

range defined in Table 8. This should be taken into consideration, along

with the different capacitive loading on each rail, if considering

simultaneous switch-on of the different supply groups.

4.2.2

Power-down sequence

The device processor has the following power-down sequence requirements:

•

Supply group 0 must be turned off last, after all other supplies.

Supply group 1 can be turned off just prior to group 0.

All remaining supplies can be turned off prior to group 1.

NOTE

When switching off supply group 0 (SNVS), VDD_SNVS_LDO_1P8_CAP

must be fully discharged to 0 V before starting the next power-up sequence

to ensure correct operation.

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Electrical characteristics

4.2.3

Power Supplies Usage

The following table shows the power supplies usage by group.

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Table 15. Power supplies usage

Supply

Groups

Voltage

Group0

2.4 - 4.2v

VDD_SNVS_4P2

1.0v

Group 1

1.8v

VDD_MAIN

VDD_ANA1_1P8

VDD_ANA2_1P8

VDD_ANA3_1P8

VDD_CP_1P8

VDD_LVDSx_1P0

VDD_MIPI_CSIx_1P0

VDD_MIPI_DSIx_1P0

VDD_MIPI_DSIx_PLL_1P0

VDD_SCU_1P8

VDD_SCU_x_1P8

Group 2

1.1V

1.8v

VDD_ADC_DIG_1P8

VDD_ADC_1P8

1.8v or 3.3v

1.8v or 3.3v switchable

3.3v

VDD_MEMC

VDD_EMMC0_1P8_3P3

VDD_ESAI0_MCLK_1P8_3P3

VDD_ESAI1_SPDIF_SPI_1P8_3P3

VDD_FLEXCAN_1P8_3P3

VDD_USDHCx_1P8_3P3 VDD_HDMI_RX0_VH_RX_3P3

VDD_DDR_CHx_VDDQ

VDD_DDR_CHx_VDDQ_CKE

VDD_SIM0_1P8_3P3

VDD_HDMI_TX0_DIG_3P3

VDD_USB_OTGx_3P3

VDD_USB_SS3_TC_3P3

VDD_ANA0_1P8

VDD_DDR_CHx_VDDA_PLL_1P8

VDD_HDMI_x_1P8

VDD_LVDSx_1P8

VDD_LVDS_DIG_1P8_3P3

VDD_M4_GPT_UART_1P8_3P3

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_MIPI_CSI_DIG_1P8

VDD_MIPI_x_1P8

VDD_MLB_DIG_1P8_3P3

VDD_MLB_1P8

VDD_PCIE_DIG_1P8_3P3

VDD_QSPIx_1P8_3P3

VDD_PCIE_SATA0_PLL_1P8

VDD_PCIE_x_1P8

VDD_PCIEx_PLL_1P8

VDD_USB_HSIC0_1P8

1.2v

VDD_SPI_SAI_1P8_3P3

VDD_USDHC_VSELECT_1P8_3P3

Group 3

1.1 - 1.1v

1.0v internal LDO's

VDD_HDMI_TX0_1P0

VDD_PCIE_SATA0_1P0

1.8v or 2.5v or 3.3v

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_3P3

VDD_A53

VDD_A72

VDD_USB_HSIC0_1P2

VDD_ENET1_1P8_2P5_3P3

VDD_GPUx

VDD_PCIEx_1P0

VDD_USB_OTGx_1P0

MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Table 8 if other I/O functions are used as determined by

IOMUX selection. Alternately, terminate the MLB supply, per the Hardware Developer’s Guide power supplies usage of unused features.

MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated, per the Hardware Developer’s

Guide power supplies of unused functions.

Electrical characteristics

4.3

PLL electrical characteristics

PLLs of subsystems

4.3.1

i.MX 8QuadPlus embeds a large number of PLLs to address clocking requirements of the various

subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F

processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs

are specific to high-performance interfaces. These are described in the following sections.

This table summarizes the PLLs controlled by the SCU.

Table 16. PLLs controlled by SCU

Locking range¹

Subsystem

Cortex-A53²

PLL usage

Source clock

Lock freq.

Unit

Min freq. Max freq.

Subsystem

1250

2500

• Overdrive: 2400

• Nominal: 1800

MHz

Cortex-A72³

Subsystem

• Overdrive: 1600

• Nominal: 2120

CCI

Subsystem

650

1300

2500

1000

MHz

GPU

PLL #0: subsystem

1250

• Nominal: 2500

• Underdrive: 1600⁴

PLL #1: shaders

Subsystem

1250

2500

• Nominal: 2500

MHz

• Underdrive: 1600⁴

DRC (DRAM

Controller)

• LPDDR4: 1600

DB (DRAM Block)

DBLog

Subsystem

650

1300

750

800

MHz

Display Controller 0 PLL #0: subsystem

PLL #1: display clock #0

800

User-configurable

800

PLL #2: display clock #1

Display Controller 1 PLL #0: subsystem

PLL #1: display clock #0

User-configurable

1200

PLL #2: display clock #1

Imaging

Audio

Subsystem

PLL #0: subsystem

PLL #1: audio PLL #0

PLL #2: audio PLL #1

Subsystem

700

User-configurable

792

Connectivity

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Electrical characteristics

Subsystem

Table 16. PLLs controlled by SCU (continued)

Locking range¹

PLL usage

Source clock

Lock freq.

Unit

Min freq. Max freq.

HSIO (High-speed

I/O)

Subsystem

650

1300

800

MHz

LSIO (Low-speed

I/O)

Subsystem

Cortex-M4

VPU

Subsystem

650

1300

792

MHz

PLL #0: subsystem

PLL #1: Audio DSP (HiFi 4)

Subsystem

1200

666

HDMI-TX / eDP

MIPI-DSI

MIPI-CSI

DMA

User-configurable

Subsystem

864

720

Subsystem

960

SCU (System

Subsystem

1056

Controller Unit)

Operating frequencies are limited to only those supported by the SCFW.

2400 MHz is used to generate the 1200 MHz maximum and 600 MHz slow operating points; 1800 MHz is used to generate the

900 MHz typical operating point. See Table 8 to get associated voltages.

1600 MHz is used for max operating point, 2120 MHz is used to generate 1060 MHz for typical operating point, and 2400 MHz

is used to generate the 600 MHz slow operating point. See Table 8 to get associated voltages.

2500 MHz is used to generate 625 MHz for the max operating point, 1600 MHz is used to generate 400 MHz for the slow

operating point. See Table 8 to get associated voltages.

4.3.2

PLLs dedicated to specific interfaces

The following sections cover PLLs used for specific interfaces. Clock output frequency and clock output

range refer to the output of the PLL. Additional clock dividers may be on the output path to divide the

output frequency down to the targeted frequency. See the related sections in the reference manual for

settings of these clock dividers.

4.3.2.1

Ethernet PLL

This PLL is controlled by the SCU.

Table 17. Ethernet PLL

Parameter

Value

Unit

Reference clock

MHz

GHz

Clock output frequency

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Electrical characteristics

4.3.2.2

USB 3.0 PLLs

USB 3.0 has two PLLs. One is embedded in Super-Speed PHY. The other one is embedded in the USB 2.0

OTG PHY that is part of the USB 3.0 interface.

The table below describes the PLL embedded in the Super-Speed PHY.

Table 18. USB 3.0 PLL embedded in Super Speed PHY

Parameter

Value

Unit

Reference clock

MHz

GHz

Clock output frequency

The table below describes the PLL embedded in the USBOTG PHY.

Table 19. USB 3.0 PLL embedded in USBOTG PHY

Parameter

Value

Unit

Reference clock

MHz

Clock output frequency

480

4.3.2.3

USB 2.0 OTG and USB-HSIC PLLs

This PLL is embedded in the USB 2.0 OTG PHY (the one which is not part of the USB 3.0 feature). It is

also used to supply the 480 MHz clock to the HSIC interface.

Table 20. USB 2.0 OTG and USB-HSIC PLLs

Parameter

Value

Unit

Reference clock

MHz

Clock output frequency

480

4.3.2.4

PCIe PLLs

The PCIe interface has seven PLLs:

•

One is used to generate the single, common 100 MHz reference clock to each lane

One Transmit and one Receive PLL per lane (three lanes)

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Electrical characteristics

The table below shows the characteristics for the reference clock PLL.

Table 21. PCIe reference clock PLLs

Parameter

Value

Unit

Comments

Reference clock

Clock output frequency

MHz

—

100

MHz Used to generate internal 100 MHz reference clock to PCIe lanes

The table below shows characteristics of the TX and RX PLLs used in each lane.

Table 22. PCIe Transmit and Receive PLLs

Parameter

Value

Unit

Comments

Reference clock

100

MHz From differential input clock pads or from internal PLL

Clock output range

6 ~ 10

GHz PCIe gen3: 8GHz to get 8GHz baud clock

PCIe gen2: 10GHz to get 5GHz baud clock

PCIe gen1: 10GHz to get 2.5GHz baud clock

PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP representative.

4.3.2.5

HDMI-TX / DP PLLs

The HDMI-TX interface uses two PLLs. One is used to generate the reference clock when using the HDMI

PHY itself in HDMI mode. In DP mode, this PLL is bypassed and only the PLL embedded in the PHY is

used.

The table below shows characteristics of the reference clock PLL for HDMI.

Table 23. HDMI reference clock PLL

Parameter

Value

Unit

Comments

Reference clock

Clock output range

MHz

—

1.25 ~ 2.5

GHz Refer to HDMI / DP section of reference manual

The table below shows characteristics of the PLL embedded in HDMI/DP PHY.

Table 24. PLL embedded in HDMI/DP PHY

Parameter

Value

Unit

Comments

Reference clock

24MHz / derived from

HDMI-TX PLL

MHz 24MHz: when in DP mode

derived from HDMI-TX PLL: when in HDMI mode

Clock output range

≤5.4

GHz Dependent on targeted display configuration

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Electrical characteristics

4.3.2.6

MIPI-DSI PLL

The table below shows characteristics of the PLL embedded in the MIPI-DSI PHY.

Table 25. MIPI-DSIPHY PLL

Parameter

Value

Unit

Comments

Reference clock

Clock output range

MHz

—

0.75 ~ 1.5

GHz Dependent on targeted display configuration

4.3.2.7

LVDS PLL

The table below shows characteristics of the PLL embedded in LVDS PHY.

Table 26. LVDS PHY PLL

Parameter

Value

Unit

Comments

Reference clock

Data rate range

25 ~ 160

MHz

—

175 ~ 1120

Mbps Dependent on targeted display configuration

4.4

On-chip oscillators

OSC24M

4.4.1

This block integrates trimmable internal loading capacitors and driving circuitry. When combined with a

suitable 24 MHz external quartz element, it can generate a low-jitter clock. The oscillator is powered from

VDD_SCU_XTAL_1P8. The internal loading capacitors are trimmable to provide fine adjustment of the

24 MHz oscillation frequency. It is expected that customers burn appropriate trim values for the selected

crystal and board parasitics.

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Electrical characteristics

Figure 2. Normal Crystal Oscillation mode

Table 27. Crystal specifications

Parameter description

Min

Typ

Max

Unit

Frequency¹

—

MHz

Cload²

Maximum drive level

200

—

μW

ESR

The required frequency accuracy is set by the serial interfaces utilized for a specific application and is detailed in the

respective standard documents.

Cload is the specification of the quartz element, not for the capacitors coupled to the quartz element.

4.4.2

OSC32K

This block implements an internal amplifier, trimmable load capacitors and a bias network that when

combined with a suitable quartz crystal implements a low power oscillator.

Additionally, if the clock monitor determines that the 32KHz oscillation is not present, then the source of

the 32 KHz clock will automatically switch to the internal relaxation oscillator of lesser frequency

accuracy.

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Electrical characteristics

CAUTION

The internal ring oscillator is not meant to be used in customer applications,

due to gross frequency variation over wafer processing, temperature, and

supply voltage. These variations will cause timing issues to many different

circuits that use the internal ring oscillator for reference; and, if this timing

is critical, application issues will occur. To prevent application issues, it is

recommended to only use an external crystal or an accurate external clock.

If this recommendation is not followed, NXP cannot guarantee full

compliance of any circuit using this clock. The OSC32K runs from

VDD_SNVS_LDO_1P8_CAP, which is regulated from VDD_SNVS. The

target battery/voltage range is 2.8 to 4.2 V for VDD_SNVS, with a regulated

output of approximately 1.75 V.

Table 28. OSC32K main characteristics

Parameter

Min

Typ

Max

Comments

Fosc

—

32.768 kHz

—

This frequency is nominal and determined mainly by

the crystal selected. 32.0 KHz is also supported.

Current

consumption

—

• xtal oscillator mode: 5 μA

—

These values are for typical process and room

temperature. Values will be updated after silicon

characterization.

• 32K internal oscillator mode: 10 μA

Bias resistor

200 MΩ

This the integrated bias resistor that sets the amplifier

into a high gain state. Any leakage through the ESD

network, external board leakage, or even a scope

probe that is significant relative to this value will

debias the amplifier. The debiasing will result in low

gain, and will impact the circuit's ability to start up and

maintain oscillations.

Target Crystal Properties

Cload

ESR

—

10 pF

—

Usually crystals can be purchased tuned for different

Cloads. This Cload value is typically 1/2 of the

capacitances realized on the PCB on either side of

the quartz. A higher Cload will decrease oscillation

margin, but increases current oscillating through the

crystal.

50 kΩ

100 kΩ Equivalent series resistance of the crystal. Choosing

a crystal with a higher value will decrease the

oscillating margin.

Table 29. External input clock for OSC32K

Min

Typ

Max

Unit

Notes

Frequency

—

700

—

32.768 or 32

—

kHz

—

1,2,3

V_PPRTC_XTALI

Rise/fall time

—

VDD_SNVS_LDO_1P8_CAP

—

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Electrical characteristics

The external clock is fed into the chip from the RTC_XTALI pin; the RTC_XTALO pin should be left floating.

The parameter specified here is a peak-to-peak value and VI_H/V_ILspecifications do not apply.

The voltage applied on RTC_XTALI must be within the range of VSS to VDD_SNVS_LDO_1P8_CAP.

The rise/fall time of the applied clock are not strictly confined.

4.5

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

XTALI and RTC_XTALI (clock inputs) DC parameters

General Purpose I/O (GPIO) DC parameters

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output.

ovdd

pmos (Rpu)

Voh min

Vol max

pdat

pad

Predriver

nmos (Rpd)

ovss

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.5.1

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

For RTC_XTALI, V /V specifications do not apply. The high and low levels of the applied clock on

IH IL

this pin are not strictly defined, as long as the input’s peak-to-peak amplitude meet the requirements and

the input’s voltage value does not exceed the limits.

4.5.2

General-purpose I/O (GPIO) DC parameters

NOTE

The term “OVDD” in this section refers to the associated supply rail of an

input or output. The association is shown in Table 127.

4.5.2.1

Tri-voltage GPIO DC parameters

The following tables show tri-voltage 1.8V, 2.5 V, and 3.3 V DC parameters, respectively, for GPIO pads.

These parameters are guaranteed per the operating ranges in Table 8, unless otherwise noted.

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Table 30. Tri-voltage 1.8 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^2,3

V_OH

I_OH= 0.1mA

PDRV=1

0.8 × OVDD

—

I_OH= 2mA

PDRV=0

Low-level output voltage^2,3

V_OL

I_OL= -0.1mA

PDRV=1

—

0.125 × OVDD

_OL= -2mA

PDRV=0

High-Level input voltage^2,4

Low-Level input voltage

Pull-up resistance

V_IH

V_IL

—

0.625 × OVDD

OVDD

0.25 × OVDD

R_PU

V_IN=0V (Pullup Resistor)

PUN = "L", PDN = "H"

kΩ

Pull-down resistance

R_DOWN

V_IN=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

-1

kΩ

μA

Input current (no PU/PD)

I_IN

VI = 0, VI = OVDD

PUN = "H", PDN = "H"

For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly.

For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation,

PSW_OVR = 0b1 and COMP = 0b010.

Refer to Section 4.6.1 for undershoot and overshoot specifications.

As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for 3v3 and 2v5 modes.

Low Drive mode is recommended for 1v8 mode.

Refer to Section 4.6.2 for monotonic requirements.

Table 31. Tri-voltage 2.5 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^2,3

I_OH= 2mA

PDRV=0

0.8 × OVDD

—

Low-level output voltage^2,3

I_OL= -2mA

PDRV=0

—

0.125 × OVDD

High-Level input voltage^2,4

Low-Level input voltage

Pull-up resistance

—

0.625 × OVDD

OVDD

0.25 × OVDD

100

V_IL

RPU

V_IN=0V (Pullup Resistor)

PUN = "L", PDN = "H"

kΩ

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Table 31. Tri-voltage 2.5 V GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Pull-down resistance

R_DOWN

V_IN=OVDD( Pulldown

Resistor)

100

kΩ

PUN = "H", PDN = "L"

Input current (no PU/PD)

I_IN

VI = 0, VI = OVDD

PUN = "H", PDN = "H"

-1

μA

For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly.

For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation,

PSW_OVR = 0b1 and COMP = 0b010.

Refer to Section 4.6.1 for undershoot and overshoot specifications.

As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for 3v3 and 2v5 modes.

Low Drive mode is recommended for 1v8 mode.

Refer to Section 4.6.2 for monotonic requirements.

Table 32. Tri-voltage 3.3 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^2,3

I_OH= 0.1mA

PDRV=1

0.8 × OVDD

I_OH= 2mA

PDRV=0

Low-level output voltage^2,3

I_OL= -0.1mA

PDRV³=1

—

0.125 × OVDD

I_OL= -2mA

PDRV=0

High-Level input voltage^2,4,3

Low-Level input voltage

Pull-up resistance

—

0.725 × OVDD

OVDD

0.25 × OVDD

100

V_IL

RPU

V_IN=0V (Pullup Resistor)

PUN = "L", PDN = "H"

kΩ

Pull-down resistance

R_DOWN

V_IN=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

-2

100

kΩ

μA

Input current (no PU/PD)

IIN

VI = 0, VI = OVDD

PUN = "H", PDN = "H"

For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly.

For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation,

PSW_OVR = 0b1 and COMP = 0b010.

Refer to Section 4.6.1 for undershoot and overshoot specifications.

As programmed in the associated IOMUX (PDRV field) register. High Drive mode recommended for 3v3 and 2v5 modes. Low

Drive mode is recommended for 1v8 mode.

Refer to Section 4.6.2 for monotonic requirements.

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4.5.2.2

Dual-voltage GPIO DC parameters

The following two tables show dual-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO

pads. These parameters are guaranteed per the operating ranges in Table 8, unless otherwise noted.

Table 33. Dual-voltage 1.8 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Ioh= 0.1mA

Min

Max

Units

High-level output voltage^1,2

V_OH

0.8 × OVDD

—

PDRV=1

Ioh= 2mA

PDRV=0

Low-level output voltage^1,2

High-Level input voltage^1,3

V_OL

Iol= -0.1mA

PDRV=1

—

0.125 × OVD

Iol= -2mA

PDRV=0

V_IH

—

0.625 × OVD

OVDD

Low-Level input voltage

Pull-up resistance

V_IL

0.25 × OVDD

R_PU

Vin=0 V (Pullup Resistor)

PUN = "L", PDN = "H"

kΩ

Pull-down resistance

R_downVin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

-1

kΩ

μA

Input current (no PU/PD)

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

Refer to Section 4.6.1 for undershoot and overshoot specifications.

As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for SD standard (3v3 mode)

and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode).

Refer to Section 4.6.2 for monotonic requirements.

Table 34. Dual-voltage 3.3 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^1,2

V_OH

Ioh= 0.1mA

PDRV=1

0.8 × OVDD

—

Ioh= 2mA

PDRV=0

Low-level output voltage^1,2

V_OL

Iol= -0.1mA

PDRV=1

—

0.125 × OVDD

Iol= -2mA

PDRV=0

High-Level input voltage^1,3

Low-Level input voltage

V_IH

V_IL

—

0.725 × OVDD

OVDD

0.25 × OVDD

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Table 34. Dual-voltage 3.3 V GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Pull-upresistance

R_PU

Vin=0V (Pullup Resistor)

PUN = "L", PDN = "H"

100

kΩ

Pull-down resistance

R_down

Vin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

-2

100

kΩ

μA

Input current (no PU/PD)

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

Refer to Section 4.6.1 for undershoot and overshoot specifications.

As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for SD standard (3v3 mode)

and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode).

Refer to Section 4.6.2 for monotonic requirements.

4.5.2.3

Single-voltage GPIO DC parameters

Table 35 and Table 36 show single-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads.

These parameters are guaranteed per the operating ranges in Table 8 unless otherwise noted.

Table 35. Single-voltage 1.8 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^1,2

V_OH

I_OH= 0.1mA

DSE = 000 or 001

OVDD × 0.8

—

I_OH= 2mA

DSE = 010 or 011

I_OH= 4mA

DSE = 100 to 110

Low-level output voltage^1,2

V_OL

I_OL= -0.1mA

DSE = 000 or 001

—

OVDD × 0.2

I_OL= -2mA

DSE = 010 or 011

I_OL= -4mA

DSE = 100 to 110

High-Level input voltage^2,3

Low-Level input voltage^2,3

Pull-up resistance

V_IH

V_IL

—

0.65 × OVDD

OVDD

0.35 × OVDD

R_PU

Vin=0V (Pullup Resistor)

PUN = "L", PDN = "H"

kΩ

Pull-down resistance

R_down

Vin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

-5

kΩ

μA

kΩ

Input current (no PU/PD)

Keeper Circuit Resistance

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

R_Keeper

V_I=.3xOVDD, VI = .7x OVDD

PUN = "L", PDN = "L"

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As programmed in the associated IOMUX (DSE field) register.

Refer to Section 4.6.1 for undershoot and overshoot specifications.

Refer to Section 4.6.2 for monotonic requirements.

Table 36. Single-voltage 3.3 V GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage^1,2

V_OH

I_OH= 0.1mA

DSE = 00 or 01

0.8 × OVDD

—

I_OH= 2mA

DSE = 10 or 11

Low-level output voltage^1,2

V_OL

I_OL= -0.1mA

DSE = 00 or 01

—

0.2 × OVDD

_OL= -2mA

DSE = 10 or 11

High-Level input voltage^2,3

Low-Level input voltage^2,3

Pull-upresistance

V_IH

V_IL

—

0.75 × OVDD

OVDD

0.25 × OVDD

R_PU

Vin=0 V (Pullup Resistor)

PUN = "L", PDN = "H"

kΩ

Pull-down resistance

R_down

Vin=OVDD( Pulldown Resistor)

PUN = "H", PDN = "L"

-5

kΩ

μA

kΩ

Input current (no PU/PD)

Keeper Circuit Resistance

I_IN

V_I= 0, V_I= OVDD

PUN = "H", PDN = "H"

R_Keeper

V_I=.3xOVDD, VI = .7x OVDD

PUN = "L", PDN = "L"

As programmed in the associated IOMUX (DSE field) register.

Refer to Section 4.6.1 for undershoot and overshoot specifications.

Refer to Section 4.6.2 for monotonic requirements.

4.5.3

HDMI control signals parameters

The following table shows HDMI control signals DC parameters. These parameters are guaranteed per the

operating ranges in Table 8, unless otherwise noted.

Table 37. HDMI DDC and HPD DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level input voltage

Low-level input voltage

V_IH

V_IL

—

5.3

0.8

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4.5.4

DDR I/O DC parameters

4.5.4.1

LPDDR4 mode I/O DC parameters

These parameters are guaranteed per the operating ranges in Table 8 unless otherwise noted.

Table 38. LPDDR4 DC parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage¹

V_OH

Output Drive = All settings

(40,48,60,80,120,240)

unterminated outputs

0.9 × V_DDQ

—

Low-level output voltage¹

V_OL

Output Drive = All settings

(40,48,60,80,120,240)

unterminated outputs

—

0.1 × V_DDQ

Input current (no ODT)

I_IN

V_I= VSSQ, V_I= VDDQ

-2

μA

DC High-Level input voltage

DC Low-Level input voltage

V_{IH_DC}

V_{IL_DC}

—

VREF + 0.1

VSSQ

VDDQ

VREF – 0.1

Refer to Section 4.6.1 for undershoot and overshoot specifications.

4.6

I/O AC Parameters

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and

Figure 5.

From Output

Under Test

Test Point

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

OVDD

0 V

80%

20%

80%

20%

Output (at pad)

Figure 5. Output Transition Time Waveform

4.6.1

I/O Overshoot and Undershoot Parameters

For all inputs/outputs, maximum peak amplitude allowed for overshoot and undershoot is specified in

Table 39. OVDD is the I/O Supply.

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NOTE

If a signal edge produces more than one overshoot/undershoot event, the

sum of all areas following the transition must be less than the area specified.

Table 39. Overshoot and Undershoot Parameters

Parameter

Symbol

Min

Max

Units

Amplitude above OVDD or below GND

Area above OVDD or below GND (A + B)

V_Peak

V_Area

—

0.35

0.8

V-ns

Overshoot/undershoot must be controlled through printed circuit board layout, transmission line

impedance matching, signal line termination, and other methods. Noncompliance to this specification may

affect device reliability or cause permanent damage to the device.

VPeak

Figure 6. Undershoot Waveform Example

4.6.2

Input Signal Monotonic Requirements

Processor input signal monotonic requirements are illustrated in the following figure.

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Figure 7. Input Waveform Monotonic Requirement

VIH_min and VIL_max are the guaranteed minimum logic-high and maximum logic-low voltage

specifications, respectively. NXP devices are typically better than guaranteed specifications; these values

are shown in the diagram as “typ”. Nominally, lower voltages than the guaranteed specification are

accepted by the device as logic high and higher voltages than the guaranteed specification are accepted as

logic low.

4.6.3

General Purpose I/O (GPIO) AC Parameters

Table 40. General Purpose I/O AC Parameters

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

1.8 V application²

f_max

Maximum frequency

Load = 21 pF (PDRV = L, high

—

208

MHz

drive, 33 Ω

Load = 15 pF (PDRV = H, low

drive, 50 Ω

Rise time

Fall time

Measured between V_OLand

V_OH

0.4

—

1.32

Measured between V_OHand

V_OL

Driver 3.3 V application³

f_max

Maximum frequency

Load = 30 pF

—

MHz

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Table 40. General Purpose I/O AC Parameters (continued)

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Rise time

Fall time

Measured between

V_OLand V_OH

—

Measured between

V_OHand V_OL

—

All output I/O specifications are guaranteed for Accurate mode of the compensation cell operation. This is applicable for both

DC and AC specifications.

All timing specifications in 1.8 V application are valid for High Drive mode (PDRV = L). In Low Drive mode (PDRV = H), the

driver is functional.

All timing specifications in 3.3 V application are valid for Low Drive only. For High Drive setting, the driver is functional.

Table 41. Dynamic input characteristics

Symbol

Parameter

Condition^1,2

Min

Max

Unit

Dynamic Input Characteristics for 3.3 V Application

f_op

Input frequency of operation

—

MHz

INPSL Slope of input signal at I/O

Measured between 10% to 90% of the I/O swing

3.5

Dynamic Input Characteristics for 1.8 V Application

f_op

Input frequency of operation

—

208

1.5

MHz

INPSL Slope of input signal at I/O

Measured between 10% to 90% of the I/O swing

For all supply ranges of operation.

The dynamic input characteristic specifications are applicable for the digital bidirectional cells.

4.7

Output Buffer Impedance Parameters

This section defines the I/O impedance parameters for the following I/O types:

•

General Purpose I/O (GPIO) output buffer impedance

Double Data Rate I/O (DDR) output buffer impedance for LPDDR4

NOTE

GPIO and DDR I/O output driver impedance is measured with “long”

transmission line of impedance Ztl attached to I/O pad and incident wave

launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that

defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 8).

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OVDD

PMOS (Rpu)

Ztl Ω, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

Vin (do)

t,(ns)

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

Vovdd – Vref1

Vref1

Rpu =

Rpd =

× Ztl

Vref2

Vovdd – Vref2

Figure 8. Impedance Matching Load for Measurement

4.7.1

GPIO output buffer impedance

4.7.1.1

Tri-voltage GPIO output buffer impedance

Table 42. Tri-voltage 1.8 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

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As programmed in the associated IOMUX (PDRV field) register.

Table 43. Tri-voltage 2.5 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

As programmed in the associated IOMUX (PDRV field) register.

Table 44. Tri-voltage 3.3 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

As programmed in the associated IOMUX (PDRV field) register.

4.7.1.2

Dual-voltage GPIO output buffer impedance

Table 45. Dual-voltage 1.8 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

‘As programmed in the associated IOMUX (PDRV field) register.

Table 46. Dual-voltage 3.3 V GPIO output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=0

¹DSE=1

As programmed in the associated IOMUX (PDRV field) register.

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4.7.1.3

Single-voltage 1.8 V GPIO output buffer drive strength

The following table shows the GPIO output buffer drive strength (OVDD 1.8 V).

Table 47. Single-voltage GPIO 1.8 V output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

¹DSE=000

¹DSE=001

¹DSE=010

¹DSE=011

¹DSE=100

¹DSE=101

¹DSE=110

¹DSE=111

200

100

Output impedance

Z_O

As programmed in the associated IOMUX (DSE field) register.

4.7.1.4

Single-voltage 3.3 V GPIO output buffer drive strength

The following table shows the GPIO output buffer drive strength (OVDD 3.3 V).

Table 48. Single-voltage GPIO 3.3 V output impedance DC parameters

Parameter

Symbol

Test conditions

Typical

Units

Output impedance

Z_O

¹DSE=00

¹DSE=01

¹DSE=10

¹DSE=11

400

200

100

As programmed in the associated IOMUX (DSE field) register.

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4.7.2

DDR I/O output buffer impedance

The following tables show LPDDR4 I/O output buffer impedance of the device.

The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances

of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The

resulting calibration setting is then applied to all DDR pads within the PHY complex.

Table 49 shows the recommended ZQnPR0 field settings for the LPDDR4 I/Os to achieve the desired

output buffer impedances.

Table 49. LPDDR4 I/O output buffer impedance

Typical

Parameter

ZQnPR0

ZPROG_ASYM_PU_DRV

ZQnPR0

ZPROG_ASYM_PD_DRV

Impedance

Recommended combinations

for DQ /CA pins

80 Ω

60 Ω

48 Ω

40 Ω

120 Ω

80 Ω

60 Ω

48 Ω

Table 50. LPDDR4 I/O on-die termination impedance

Typical

Parameter

ZQnPR0. ZPROG_HOST_ODT

Impedance

Recommended combinations

for DQ/CA pins

120.0 Ω

80.0 Ω

60.0 Ω

48.0 Ω

40.0 Ω

4.8

System Modules Timing

This section contains the timing and electrical parameters for the modules in each processor.

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4.8.1

Reset Timing Parameters

The following figure shows the reset timing and Table 51 lists the timing parameters.

POR_B

(Input)

CC1

Figure 9. Reset timing diagram

Table 51. Reset timing parameters

Parameter

Min

Max

Unit

CC1

Duration of SRC_POR_B to be qualified as valid

—

XTALOSC_RTC_ XTALI cycle

4.8.2

WDOG reset timing parameters

The following figure shows the WDOG reset timing and Table 52 lists the timing parameters.

Figure 10. SCU_WDOG_OUT timing diagram

Table 52. WDOG1_B timing parameters

Parameter

Min

Max

Unit

CC3 Duration of SCU_WDOG_OUT assertion

—

XTALOSC_RTC_ XTALI cycle

NOTE

XTALOSC_RTC_XTALI is approximately 32 kHz.

XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.

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4.8.3

DDR SDRAM–specific parameters (LPDDR4)

The i.MX 8 Family of processors have been designed and tested to work with JEDEC JESD209-4A–

compliant LPDDR4 memory . Timing diagrams and tolerances required to work with these memories are

specified in the respective documents and are not reprinted here.

Meeting the necessary timing requirements for a DDR memory system is highly dependent on the

components chosen and the design layout of the system as a whole. NXP cannot cover in this document

all the requirements needed to achieve a design that meets full system performance over temperature,

voltage, and part variation; PCB trace routing, PCB dielectric material, number of routing layers used,

placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND and Supply planes

layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory

system. Consult the hardware user guide for this device and NXP validated design layouts for information

on how to properly design a PCB for best DDR performance. NXP strongly recommends duplicating an

NXP validated design as much as possible in the design of critical power rails, placement of

bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory.

All supporting material is readily available on the device web page on

https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applicatio

ns-processors/i.mx-8-processors:IMX8-SERIES .

Processors that demonstrate full DDR performance on NXP validated designs, but do not function on

customer designs, are not considered marginal parts. A report detailing how the returned part behaved on

an NXP validated system will be provided to the customer as closure to a customer’s reported DDR issue.

Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and

modeling the designed DDR system, and validating the system under all expected operating conditions

(temperatures, voltages) prior to releasing their product to market.

Table 53. i.MX 8 Family DRAM controller supported SDRAM configurations

Parameter

LPDDR4

Number of Controllers

Number of Channels

Number of Chip Selects

Bus Width

2 per controller

2 per channel

16 bit per channel¹

16 (R0-R15)

1600 MHz

Number of Address Rows

Maximum Clock Frequency

Only 16-bit external memory configurations are supported.

4.8.3.1

Clock/data/command/address pin allocations

These processors uses generic names for clock, data and command address bus (DCF—DRAM controller

functions); the following table provides mapping of clock, data and command address signals for LPDDR4

modes.

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Electrical characteristics

Table 54. Clock, data, and command address signals for LPDDR4 modes

Signal name

LPDDR4

DDR_CH[1:0].CK0_P

DDR_CH[1:0].CK0_N

DDR_CH[1:0].CK1_P

DDR_CH[1:0].CK1_N

DDR_CH[1:0].DQ_[15:0]

DDR_CH[1:0].DQ_[31:16]

DDR_CH[1:0].DQS_N_[3:0]

DDR_CH[1:0].DQS_P_[3:0]

DDR_CH[1:0].DM_[3:0]

DDR_CH[1:0].DCF00

DDR_CH[1:0].DCF01

DDR_CH[1:0].DCF02

DDR_CH[1:0].DCF03

DDR_CH[1:0].DCF04

DDR_CH[1:0].DCF05

DDR_CH[1:0].DCF06

DDR_CH[1:0].DCF07

DDR_CH[1:0].DCF08

DDR_CH[1:0].DCF09

DDR_CH[1:0].DCF10

DDR_CH[1:0].DCF11

DDR_CH[1:0].DCF12

DDR_CH[1:0].DCF13

DDR_CH[1:0].DCF14

DDR_CH[1:0].DCF15

DDR_CH[1:0].DCF16

DDR_CH[1:0].DCF17

DDR_CH[1:0].DCF18

DDR_CH[1:0].DCF19

DDR_CH[1:0].DCF20

DDR_CH[1:0].DCF21

DDR_CH[1:0].DCF22

CK_t_A

CK_c_A

CK_t_B

CK_c_B

DQ[15:0]_A

DQ[15:0]_B

DQS_N_[3:0]

DQS_P_[3:0]

DM_[3:0]

CA2_A

CA4_A

CA5_A

CA3_A

ODT_CA_A

CS0_A

CA0_A

CS1_A

CKE0_A

CKE1_A

CA1_A

CA4_B

RESET_N

CA5_B

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Table 54. Clock, data, and command address signals for LPDDR4 modes (continued)

Signal name

LPDDR4

DDR_CH[1:0].DCF23

DDR_CH[1:0].DCF24

DDR_CH[1:0].DCF25

DDR_CH[1:0].DCF26

DDR_CH[1:0].DCF27

DDR_CH[1:0].DCF28

DDR_CH[1:0].DCF29

DDR_CH[1:0].DCF30

DDR_CH[1:0].DCF31

DDR_CH[1:0].DCF32

DDR_CH[1:0].DCF33

ODT_CA_B

CA3_B

CA0_B

CS0_B

CS1_B

CKE0_B

CKE1_B

CA1_B

CA2_B

4.9

General-Purpose Media Interface (GPMI) Timing

The GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 400 MB/s

I/O speed, and individual chip select. It supports Asynchronous Timing mode, Source Synchronous

Timing mode, and Toggle Timing mode, as described in the following subsections.

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Electrical characteristics

4.9.1

GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 11 through Figure 14

depict the relative timing between GPMI signals at the module level for different operations under

Asynchronous mode. Table 55 describes the timing parameters (NF1–NF17) that are shown in the figures.

NF2

NF1

.!.$?#,%

NF3

NF4

.!.$?#%ꢀ?"

.!.$?7%?"

NF5

.!.$?!,%

NF6

NF8

Command

NF7

NF9

.!.$?$!4!XX

Figure 11. Command Latch Cycle Timing Diagram

NF1

.!.$?#,%

NF3

.!.$?#%ꢀ?"

.!.$?7%?"

NF10

NF5

NF11

NF7

.!.$?!,%

NF6

NF8

Address

NF9

NAND_DATAxx

Figure 12. Address Latch Cycle Timing Diagram

NF1

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

NF6

.!.$?!,%

NF8

Data to NF

NF9

.!.$?$!4!XX

Figure 13. Write Data Latch Cycle Timing Diagram

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NXP Semiconductors

Electrical characteristics

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?2%?"

NF14

NF13

NF15

.!.$?2%!$9?"

NF12

NF16

NF17

Data from NF

.!.$?$!4!XX

Figure 14. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF13

NF15

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF17

NF16

NAND_DATAxx

Data from NF

Figure 15. Read Data Latch Cycle Timing Diagram (EDO Mode)

Table 55. Asynchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

Parameter

Symbol

Unit

Min

(AS + DS) × T - 0.12 [see ^2,3

Max

NF1

NF2

NF3

NF4

NF5

NF6

NF7

NF8

NF9

NAND_CLE setup time

NAND_CLE hold time

NAND_CEx_B setup time

NAND_CEx_B hold time

NAND_WE_B pulse width

NAND_ALE setup time

NAND_ALE hold time

Data setup time

tCLS

tCLH

tCS

]

DH × T - 0.72 [see ²]

(AS + DS + 1) × T [see ^3,2

(DH+1) × T - 1 [see ²]

DS × T [see ²]

]

tCH

tWP

tALS

tALH

tDS

(AS + DS) × T - 0.49 [see ^3,2

(DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

]

Data hold time

tDH

NF10 Write cycle time

tWC

tWH

tRR⁴

tRP

NF11 NAND_WE_B hold time

NF12 Ready to NAND_RE_B low

NF13 NAND_RE_B pulse width

NF14 READ cycle time

(AS + 2) × T [see ^3,2

]

—

DS × T [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

tRC

NF15 NAND_RE_B high hold time

tREH

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Electrical characteristics

Table 55. Asynchronous Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

Parameter

Symbol

Unit

Min

Max

NF16 Data setup on read

NF17 Data hold on read

tDSR

tDHR

—

(DS × T -0.67)/18.38 [see ^5,6

]

0.82/11.83 [see ^5,6

]

—

The GPMI asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

AS minimum value can be 0, while DS/DH minimum value is 1.

T = GPMI clock period -0.075ns (half of maximum p-p jitter).

NF12 is met automatically by the design.

Non-EDO mode.

EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 15), NF16/NF17 are different from the definition in non-EDO mode (Figure 14).

They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The

typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO

mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an

internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY(see the GPMI chapter

of the device reference manual. The typical value of this control register is 0x8 at 50 MT/s EDO mode.

However, if the board delay is large enough and cannot be ignored, the delay value should be made larger

to compensate the board delay.

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4.9.2

GPMI Source Synchronous mode AC timing (ONFI 2.x compatible)

The following figure shows the write and read timing of Source Synchronous mode.

NF19

NF18

.!.$?#%?"

NF23

NAND_CLE

NF26

NF25

NF24

NAND_ALE

NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

Output enable

NF20

NF21

CMD

ADD

NAND_DATA[7:0]

Output enable

Figure 16. Source Synchronous Mode Command and Address Timing Diagram

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Electrical characteristics

NF19

NF18

.!.$?#%ꢀ?"

.!.$?#,%

NF23

NF24

NF25

NF26

.!.$?!,%

NAND_WE/RE_B

NF22

.!.$?#,+

.!.$?$13

NF27

.!.$?$13

Output enable

NF29

.!.$?$1;ꢁꢂꢀ=

NF28

.!.$?$1;ꢁꢂꢀ=

Output enable

Figure 17. Source Synchronous Mode Data Write Timing Diagram

NF18

NF19

.!.$?#%?"

.!.$?#,%

NF24

NF23

NF26

NF25

NAND_ALE

NF25

.!.$?7%ꢃ2%

NF25

NF22

NF26

.!.$?#,+

.!.$?$13

/UTPUT ENABLE

.!.$?$!4!;ꢁꢂꢀ=

/UTPUT ENABLE

Figure 18. Source Synchronous Mode Data Read Timing Diagram

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Electrical characteristics

.!.$?$13

NF30

.!.$?$!4!;ꢁꢂꢀ=

NF30

NF31

Figure 19. NAND_DQS/NAND_DQ Read Valid Window

Table 56. Source Synchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

Parameter

Symbol

Unit

Min

Max

NF18 NAND_CEx_B access time

NF19 NAND_CEx_B hold time

tCE

tCH

CE_DELAY × T - 0.79 [see ]

0.5 × tCK - 0.63 [see ²]

0.5 × tCK - 0.05

—

NF20 Command/address NAND_DATAxx setup time

NF21 Command/address NAND_DATAxx hold time

NF22 clock period

tCAS

tCAH

tCK

0.5 × tCK - 1.23

—

NF23 preamble delay

tPRE

tPOST

tCALS

tCALH

tDQSS

tDS

PRE_DELAY × T - 0.29 [see ²]

POST_DELAY × T - 0.78 [see ²]

0.5 × tCK - 0.86

NF24 postamble delay

NF25 NAND_CLE and NAND_ALE setup time

NF26 NAND_CLE and NAND_ALE hold time

NF27 NAND_CLK to first NAND_DQS latching transition

NF28 Data write setup

0.5 × tCK - 0.37

T - 0.41 [see ²]

0.25 × tCK - 0.35

NF29 Data write hold

tDH

0.25 × tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

tDQSQ

tQHS

—

2.06

1.95

The GPMI source synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing

depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

Figure 19 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source

Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s.

GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal,

which can be provided by an internal DPLL. The delay value can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference

manual. Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle

delay expected. However, if the board delay is large enough and cannot be ignored, the delay value should

be made larger to compensate the board delay.

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Electrical characteristics

4.9.3

ONFI NV-DDR2 mode (ONFI 3.2 compatible)

4.9.3.1

Command and address timing

ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.

See Section 4.9.1, “GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)",” for details.

4.9.3.2

Read and write timing

ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, “Toggle

mode AC Timing",” for details.

4.9.4

Toggle mode AC Timing

4.9.4.1

Command and address timing

NOTE

Toggle mode command and address timing is the same as ONFI 1.0

compatible Asynchronous mode AC timing. See Section 4.9.1, “GPMI

Asynchronous mode AC timing (ONFI 1.0 compatible)",” for details.

4.9.4.2

Read and write timing

Figure 20. Toggle mode data write timing

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Electrical characteristics

DEV?CLK

.!.$?#%X?"

.& ꢄꢅ

.!.$?#,%

.!.$?!,%

ꢄ T #+

ꢄ

.&ꢆꢈ

.!.$?7%?"

.!.$?2%?"

ꢄ T #+

.& ꢆꢇ

ꢄ T #+

.!.$?$13

.!.$?$!4!;ꢁꢂꢀ=

Figure 21. Toggle mode data read timing

Table 57. Toggle mode timing parameters

Timing

T = GPMI Clock Cycle

Parameter

Symbol

Unit

Min.

Max.

NF1 NAND_CLE setup time

NF2 NAND_CLE hold time

tCLS

tCLH

tCS

(AS + DS) × T - 0.12 [see note²s^,3]

DH × T - 0.72 [see note²]

(AS + DS) × T - 0.58 [see notes^,2]

DH × T - 1 [see note²]

NF3 NAND_CE0_B setup time

NF4 NAND_CE0_B hold time

NF5 NAND_WE_B pulse width

NF6 NAND_ALE setup time

NF7 NAND_ALE hold time

tCH

tWP

tALS

tALH

tCAS

tCAH

tCE

DS × T [see note²]

(AS + DS) × T - 0.49 [see notes^,2]

DH × T - 0.42 [see note²]

DS × T - 0.26 [see note²]

DH × T - 1.37 [see note²]

NF8 Command/address NAND_DATAxx setup time

NF9 Command/address NAND_DATAxx hold time

NF18 NAND_CEx_B access time

NF22 clock period

CE_DELAY × T [see notes^4,2

]

—

tCK

—

NF23 preamble delay

tPRE PRE_DELAY × T [see notes^5,2

]

NF24 postamble delay

tPOST

POST_DELAY × T +0.43 [see

note²]

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Electrical characteristics

Table 57. Toggle mode timing parameters (continued)

Timing

T = GPMI Clock Cycle

Parameter

Symbol

Unit

Min.

Max.

NF28 Data write setup

NF29 Data write hold

tDS⁶

tDH⁶

0.25 × tCK - 0.32

—

0.25 × tCK - 0.79

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

tDQSQ⁷

tQHS⁷

—

3.18

3.27

The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

AS minimum value can be 0, while DS/DH minimum value is 1.

T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).

CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

PRE_DELAY+1) ≥ (AS+DS)

Shown in Figure 20.

Shown in Figure 21.

For DDR Toggle mode, Figure 21 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will

sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference

manual. Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected.

But if the board delay is big enough and cannot be ignored, the delay value should be made larger to

compensate the board delay.

4.10 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.10.1 LPSPI timing parameters

All LPSPI interfaces do not have the same maximum serial clock frequency. There are two groups. LPSPI

interfaces which can operate at 60 MHz in Master mode and 40 MHz in Slave mode and the other group

where interfaces operate at 40 MHz in Master mode and 20 MHz in Slave mode. The same performance

is achieved at 1.8 V and 3.3 V unless otherwise stated.

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Electrical characteristics

Below are the LPSPI interfaces and their respective chip selects:

Table 58. LPSPI interfaces and chip selects

LPSPI interface

Chip select

Comment

60 MHz in Master mode and 40 MHz in SPI0, SPI1, SPI2, SPI3 (primary mode) SPI1 is muxed behind ADC pins so it

Slave mode

operates at 1.8 V only.

—

40 MHz in Master mode and 20 MHz in SPI3b (behind UART1)

Slave mode

4.10.1.1 LPSPI Master mode

Waveform is assuming LPSPI is configured in mode 0, i.e. TCR.CPOL=0b0 and TCR.CPHA=0b0. Timing

parameters are valid for all modes using appropriate edge of the clock.

Figure 22. LPSPI Master mode

Table 59. LPSPI timings—Master mode at 60 MHz

Parameter

SPIx_SCLK Cycle frequency

Min

Max

Unit

—

MHz

t1 SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

7.5

t2 SPIx_CSy pulse width

t3 SPIx_CSy Lead Time⁽¹⁾

7.5

—

FCLK_PERIOD⁽²⁾x (PCSSCK

+ 1) / 2^PRESCALE- 3

t4 SPIx_CSy Lag Time⁽³⁾

FCLK_PERIOD⁽²⁾x (SCKPCS

+ 1) / 2^PRESCALE+ 3

—

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Electrical characteristics

Table 59. LPSPI timings—Master mode at 60 MHz (continued)

Parameter

Min

Max

Unit

t5 SPIx_SDO output Delay (CLOAD = 20 pF)

t6 SPIx_SDI Setup Time

—

t7 SPIx_SDI Hold Time

This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers.

FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz.

This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.

Table 60. LPSPI timings—Master mode at 40 MHz

Parameter

SPIx_SCLK Cycle frequency

Min

Max

Unit

—

MHz

t1 SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

t2 SPIx_CSy pulse width

t3 SPIx_CSy Lead Time⁽¹⁾

—

FCLK_PERIOD⁽²⁾x (PCSSCK

+ 1) / 2^PRESCALE+ 3

t4 SPIx_CSy Lag Time⁽³⁾

FCLK_PERIOD⁽²⁾x (SCKPCS

+ 1) / 2^PRESCALE+ 3

—

t5 SPIx_SDO output Delay (CLOAD = 20 pF)

t6 SPIx_SDI Setup Time

—

t7 SPIx_SDI Hold Time

This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers.

FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz.

This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers.

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Electrical characteristics

Figure 23. LPSPI Slave mode

Table 61. LPSPI timings—Slave mode at 40 MHz

Parameter

Min

Max

Unit

—

SPIx_SCLK Cycle frequency

—

MHz

SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

SPIx_CSy pulse width

—

SPIx_CSy Lead Time (CS setup time)

SPIx_CSy Lag Time (CS hold time)

SPIx_SDO output Delay (CLOAD = 20 pF)

SPIx_SDI Setup Time

—

SPIx_SDI Hold Time

Table 62. LPSPI timings—Slave mode at 20 MHz

Parameter

Min

Max

Unit

—

SPIx_SCLK Cycle frequency

—

MHz

SPIx_SCLK High or Low Time–Read

SPIx_SCLK High or Low Time–Write

SPIx_CSy pulse width

—

SPIx_CSy Lead Time (CS setup time)

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Electrical characteristics

Table 62. LPSPI timings—Slave mode at 20 MHz (continued)

Parameter

Min

Max

Unit

SPIx_CSy Lag Time (CS hold time)

SPIx_SDO output Delay (CLOAD = 20 pF)

—

SPIx_SDI Setup Time

SPIx_SDI Hold Time

4.10.2 Serial audio interface (SAI) timing parameters

The timings and figures in this section are valid for noninverted clock polarity (I2S_TCR2.BCP = 0b0,

I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity (I2S_TCR4.FSP = 0b0, I2S_RCR4.FSP =

0b0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by

inverting the clock signal (SAI_TXC / SAI_RXC) and/or the frame sync (SAI_TXFS / SAI_RXFS) shown

in the figures below.

The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated.

NOTE

SAI0 and SAI1 are transmit/receive capable. SAI2 and SAI3 are receive

only.

4.10.2.1 SAI Master Synchronous mode

In this mode, transmitter clock and frame sync are used by both transmitter and receiver

(I2S_TCR2.SYNC=0b00, I2S_RCR2.SYNC=0b01). In that case, SAI interface requires only 4 signals to

be routed: SAI_TXC, SAI_TXFS, SAI_TXD and SAI_RXD. SAI_RXC and SAI_RXFS can be left

unconnected. I2S_RCR2.BCI shall be set to 0b1 to get setup and hold times provided in Table 63.

Figure 24. SAI Master Synchronous mode

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Table 63. SAI timings—Master Synchronous mode

Parameters

Min

Max

Unit

—

SAI TXC clock frequency

—

45%

—

49.152

MHz

t1 SAI TXC pulse width low / high

t2 SAI TXFS output valid

t3 SAI TXD output valid

t4 SAI RXD input setup

t5 SAI RXD input hold

55%

SAI_TXC period

—

4.10.2.2 SAI Master mode

In this mode, transmitter and/or receiver part are set to bring out transmit and/or receive clock. Frame sync

can be either input or output.

Figure 25. SAI Master mode

Table 64. SAI timings—Master mode

Parameters

SAI TXC / RXC clock frequency¹

Min

Max

Unit

—

45%

—

49.152

55%

MHz

TXC/RXC period

t1 SAI TXC / RXC pulse width low / high

t2 SAI TXFS / RXFS output valid

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Table 64. SAI timings—Master mode (continued)

Parameters

Min

Max

Unit

t3 SAI TXD output valid

—

t4 SAI RXD/RXFS/TXFS input setup

t5 SAI RXD/RXFS/TXFS input hold

—

Given the high setup time requirement on inputs, receiver and transmitter, when using frame sync in input, are likely to run at

a lower frequency. This frequency will be driven by characteristics of the external component connected to the interface.

4.10.2.3 SAI Slave mode

In this mode, transmitter and/or receiver parts are set to receive transmit and/or receive clock from external

world. Frame sync can be either input or output.

Figure 26. SAI Slave mode

Table 65. SAI timings—Slave mode

Parameters

SAI TXC/RXC clock frequency

Min

Max

Unit

—

45%

—

24.576

55%

MHz

t11 SAI TXC/RXC pulse width low/high

t12 SAI TXFS/RXFS output valid

t13 SAI TXD output valid

TXC/RXC period

—

t14 SAI RXD/RXFS/TXFS input setup

t15 SAI RXD/RXFS/TXFS input hold

—

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4.10.3 Enhanced serial audio interface (ESAI)

The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated.

SCKT

(Input / Output)

FST (bit) out

FST (word) out

Data Out

Last bit

First bit

FST (bit) in

FST (word) in

Flags Out

Figure 27. ESAI Transmit timing

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Figure 28. ESAI Receive timing

The following table shows the interface timing values. The ID field in the table refers to timing signals

found in Figure 27 and Figure 28.

Table 66. Enhanced Serial Audio Interface (ESAI) Timing

Parameters

Min

Max

Condition¹

Unit

—

Clock frequency

SCKT / SCKT pulse width high / low

FST output delay

—

45%

—

24.576

55%

—

MHz

SCKT / SCKR period

x ck

i ck

TX data - high impedance / valid data

TX data output delay

—

x ck

i ck

x ck

i ck

FST - setup requirement

FST - hold requirement

Flag output delay

x ck

i ck

x ck

i ck

x ck

i ck

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Table 66. Enhanced Serial Audio Interface (ESAI) Timing (continued)

Parameters

Min

Max

Condition¹

Unit

FSR output delay

x ck

i ck a

RX data pins - setup requirement

RX data pins - hold requirement

FSR - setup requirement

—

x ck

i ck

t10

t11

t12

t13

t14

x ck

i ck

x ck

i ck a

FSR - hold requirement

x ck

i ck a

Flags - setup requirement

Flags - hold requirement

x ck

i ck s

x ck

i ck s

—

RX_HF_CLK / TX_HX_CLK clock cycle

TX_HF_CLK input to SCKT

—

RX_HF_CLK input to SCKR

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock)

4.10.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

Timing

This section describes the electrical information of the uSDHC, including:

•

SD3.1/eMMC5.1 High-Speed mode AC Timing

eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing

HS400 AC timing—eMMC 5.1 only

HS200 Mode Timing

SDR50/SDR104 AC Timing

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4.10.4.1 SD3.1/eMMC5.1 High-Speed mode AC Timing

The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 67 lists the

timing characteristics.

SD4

SD2

SD1

SD5

SDx_CLK

SD3

SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7

SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 29. SD3.1/eMMC5.1 High-Speed mode Timing

Table 67. SD3.1/eMMC5.1 High-Speed mode interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

f_PP

400

25/50

20/52

400

—

kHz

MHz

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

Clock Low Time

f_PP

f_OD

t_WL

100

SD2

SD3

SD4

SD5

Clock High Time

t_WH

t_TLH

t_THL

—

Clock Rise Time

—

Clock Fall Time

eSDHC Output/Card Inputs SD_CMD, SD_DATA (Reference to SD_CLK)

eSDHC Output Delay t_OD–6.6

eSDHC Input/Card Outputs SD_CMD, SD_DATA (Reference to SD_CLK)

SD6

3.6

SD7

SD8

eSDHC Input Setup Time

eSDHC Input Hold Time⁴

t_ISU

t_IH

2.5

1.5

—

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

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In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.10.4.2 eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing

The following figure depicts the timing of eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode, and Table 68

lists the timing characteristics. Be aware that only SDx_DATA is sampled on both edges of the clock (not

applicable to SD_CMD).

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card

SDx_DATA[7:0]

......

SD3

SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

Figure 30. eMMC 5.1 timing

Figure 31. eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode interface timing

Table 68. eMMC5.1 DDR 52 mode/SD3.150 mode interface timing specification

Parameter

Symbols

Card Input Clock¹

Min

Max

Unit

SD1

Clock Frequency (eMMC5.1 DDR)

Clock Frequency (SD3.1 DDR)

f_PP

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

uSDHC Output Delay t_OD2.8

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

6.8

SD3

SD4

uSDHC Input Setup Time

uSDHC Input Hold Time

t_ISU

t_IH

1.7

1.5

—

Clock duty cycle will be in the range of 47% to 53%.

4.10.4.3 HS400 AC timing—eMMC 5.1 only

Figure 32 depicts the timing of HS400. Table 69 lists the HS400 timing characteristics. Be aware that only

data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for

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HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7

parameters in Table 71 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for

HS400 mode.

Figure 32. HS400 timing

Table 69. HS400 interface timing specifications

Parameter

Symbols

Min

Max

Unit

Card Input clock

SD1

Clock Frequency

fPP

t_CL

200

Mhz

SD2

SD3

Clock Low Time

Clock High Time

0.46 × t_CLK

0.54 × t_CLK

t_CH

uSDHC Output/Card inputs DAT (Reference to SCK)

SD4

SD5

Output Skew from Data of

Edge of SCK

t_OSkew1

0.45

—

Output Skew from Edge of

SCK to Data

t_OSkew2

uSDHC input/Card Outputs DAT (Reference to Strobe)

SD6

SD7

uSDHC input skew

uSDHC hold skew

t_RQ

—

0.45

t_RQH

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4.10.4.4 HS200 Mode Timing

The following figure depicts the timing of HS200 mode, and Table 70 lists the HS200 timing

characteristics.

SD1

SD2

SD3

SD7

SCK

SD4/SD5

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD6

SD8

Figure 33. HS200 Mode Timing

Table 70. HS200 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

SD2

Clock Frequency Period

Clock Low Time

t_CLK

t_CL

5.0

—

0.46 × t_CLK

0.54 × t_CLK

Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

uSDHC Output Delay t_OD–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)¹

Card Output Data Window t_ODW0.5*t_CLK

SD5

—

SD8

¹HS200 is for 8 bits while SDR104 is for 4 bits.

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4.10.4.5 SDR50/SDR104 AC Timing

The following figure depicts the timing of SDR50/SDR104, and Table 71 lists the SDR50/SDR104 timing

characteristics.

SD1

SD2

SD3

SCK

SD5

SD4

Output from uSDHC to card

SD7

SD6

Input from card to uSDHC

SD8

Figure 34. SDR50/SDR104 timing

Table 71. SDR50/SDR104 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

4.8

—

0.46 × t_CLK

0.54 × t_CLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

SD4 uSDHC Output Delay t_OD–3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)

uSDHC Output Delay t_OD–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)

SD5

uSDHC Input Setup Time

uSDHC Input Hold Time

t_ISU

t_IH

2.5

1.5

—

SD6

SD7

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)¹

Card Output Data Window t_ODW0.5 × t_CLK

—

SD8

Data window in SDR100 mode is variable.

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4.10.4.6 Bus Operation Condition for 3.3 V and 1.8 V Signaling

Signaling level of SD/eMMC 5.1 and eMMC 5.1 modes is 3.3 V. Signaling level of SDR104/SDR50 mode

is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to

those shown in “,” and Table 33, "Dual-voltage 1.8 V GPIO DC parameters," on page 39Table 34,

"Dual-voltage 3.3 V GPIO DC parameters," on page 39.

4.10.5 Ethernet Controller (ENET) AC Electrical Specifications

ENET interface supporting RGMII protocol in delay and non-delay mode. RGMII is used to support up to

1000 Mbps Ethernet as well as RMII protocol. RMII is used to support up to 100 Mbps Ethernet.

NOTE

ENET1 supports RGMII at 1.8 V and 2.5 V, and RMII at 3.3 V. ENET0

supports RGMII at 1.8 V only and RMII at 3.3 V.

Table 72. RGMII/RMII pin mapping

Pin name¹

RGMII

RGMII_TXC

RMII

Comment²

ENETx_RGMII_TXC

RCLK50M

RCLK50M can be an input or

an output. It's using different

Alternate pin muxing modes.

Refer to pin muxing for details.

ENETx_RGMII_TX_CTL

ENETx_RGMII_TXD0

ENETx_RGMII_TXD1

ENETx_RGMII_TXD2

ENETx_RGMII_TXD3

ENETx_RGMII_RXC

ENETx_RGMII_RX_CTL

ENETx_RGMII_RXD0

ENETx_RGMII_RXD1

ENETx_RGMII_RXD2

RGMII_TX_CTL

RGMII_TXD0

RGMII_TXD1

RGMII_TXD2

RGMII_TXD3

RGMII_RXC

RMII_TXEN

RMII_TXD0

RMII_TXD1

N/A

—

N/A

RGMII_RX_CTL

RGMII_RXD0

RGMII_RXD1

RGMII_RXD2

RMII_CRS_DV

RMII_RXD0

RMII_RXD1

RMII_RXER

RMII_RXER is mapped on

ALT1 mode of pin muxing.

ENETx_RGMII_RXD3

RGMII_RXD3

N/A

—

ENETx_REFCLK_125M_25M RGMII_REF_CLK

RGMII_REF_CLK is optional

for RGMII operation and

dependent on the intended

clock configuration.

ENETx_MDIO

ENETx_MDC

RGMII_MDIO

RGMII_MDC

RMII_MDIO

RMII_MDC

—

x can be 0 or 1.

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Except for RCLK50M and RMII_RXER, all other RMII functions are using the same pin muxing mode as RGMII.

4.10.5.1 RGMII

4.10.5.1.1 No-Internal-Delay mode

This mode corresponds to the RGMIIv1.3 specification.

Figure 35. RGMII timing diagram—No-Internal-Delay mode

Table 73. RGMII timings—No-Internal-Delay mode

Parameter

Min

Typ

Max

Unit

TXC / RXC frequency

Clock cycle

—

7.2

-500

125

—

8.8

500

2.6

MHz

Data to clock output skew

—

Data to clock input skew¹⁽¹⁾

This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and

less than 2.0 ns is added to the associated clock signal.

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4.10.5.1.2 Internal-delay mode

This mode corresponds to RGMIIv2.0 specification. The interface is still operating at 2.5 V. 1.5 V is not

supported.

Figure 36. RGMII timing diagram—Internal-Delay mode

Table 74. RGMII timing—Internal-Delay mode

Parameter

Min

Typ

Max

Unit

TXC / RXC frequency

Clock cycle

—

7.2

1.2

125

—

8.8

—

MHz

TXD setup time

TXD hold time

RXD setup time

RXD hold time

—

2.5

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4.10.5.2 RMII

RMII interface is matching RMII v1.2 specification. In RMII mode, the reference clock can be generated

internally and provided to the PHYthrough RCLK50M_OUT. Or, it come from and external 50MHz clock

generator which is connected to the PHY and to i.MX8 through RCLK50M_IN pin.

Figure 37. RMII timing diagram

Timings in table below are covering both cases: reference clock generated internally or externally.

Table 75. RMII timing

Parameter

Min

Typ

Max

Unit

Reference clock

—

MHz

ppm

Reference clock accuracy

Reference clock duty-cycle

RMII_TXEN, RMII_TXD output delay

RMII_CRS_DV, RMII_RXD setup time

RMII_CRS_DV, RMII_RXD hold time

4.10.5.3 MDIO

MDIO is the control link used to configure Ethernet PHY connected to i.MX8 device.

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Figure 38. MDIO timing diagram

Table 76. MDIO timing

Parameter

Min

Typ

Max

Unit

MDC frequency

—

180

2.5

—

MHz

MDC high / low pulse width

MDIO output delay

MDIO setup time

MDIO hold time

4.10.6 CAN network AC Electrical Specifications

The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing

the CAN protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B

protocol specification. The processor has three CAN modules available for systems design. Tx and Rx

ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the device

reference manual to see which pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and

FLEXCAN_RX, respectively.

4.10.7 HDMI Tx module timing parameters

See the following specifications:

•

DisplayPort 1.3 standard (VESA.org)

Embedded DisplayPort 1.4 standard (VESA.org)

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The DDC link requires external pull-up resistors to be connected to a 5 V supply. The following table

provides the range for those pull-ups.

Table 77. HDMI—Pull-up resistors for DDC link

Ball name

Min

Typ

Max

Unit

HDMI_TX0_DDC_SCL

HDMI_TX0_DDC_SDA

1.5

—

kΩ

4.10.8 HDMI Tx and Rx REXT reference resistor connection

Table 78. HDMI_REXT reference resistor connection

Name Min Typ Max Unit

REXT 497.50 500 502.50

Descriptions

REXT resistor is 500 Ω ± 0.5%. It shall be connected to ground.

4.10.9 I²C Module Timing Parameters

This section describes the timing parameters of the I C module. The following figure depicts the timing

of the I C module, and Table 79 lists the I C module timing characteristics.

I2Cx_SDA

I2Cx_SCL

IC11

IC9

IC10

IC7

IC4

IC2

IC3

IC8

IC10b

IC6

IC11b

STOP

START

IC5

IC1

Figure 39. I C bus timing

Table 79. I C Module Timing Parameters

Standard Mode

Fast Mode

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

IC3

IC4

I2Cx_SCL cycle time

4.0

0¹

—

2.5

0.6

0¹

—

µs

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

—

3.45²

0.9²µs

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Table 79. I C Module Timing Parameters (continued)

Standard Mode

Parameter

Fast Mode

Unit

Min

Max

Min

Max

IC5

IC6

IC7

IC8

IC9

HIGH Period of I2Cx_SCL Clock

4.0

4.7

250

4.7

—

0.6

1.3

—

µs

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

—

0.6

—

100³

1.3

Bus free time between a STOP and START condition

—

IC10/IC10b Rise time of both I2Cx_SDA and I2Cx_SCL signals

IC11/IC11b Fall time of both I2Cx_SDA and I2Cx_SCL signals

1000

300

400

20 + 0.1C_b300 ns

—

20 + 0.1C_b300 ns

IC12

Capacitive load for each bus line (C_b)

—

400 pF

A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal in order to bridge the undefined region of

the falling edge of I2Cx_SCL.

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.

If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the I2Cx_SCL line is released.

C_b= total capacitance of one bus line in pF.

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Table 80. I2C timing

Fast Mode Plus

Min

High Speed¹

Min Max

Unit

Parameter

SCL clock frequency

Max

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

—

160

3.4

—

MHz

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

260

—

HIGH Period of I2Cx_SCL Clock

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

260

500

260

160

Bus free time between a STOP and START

condition

500

150

IC10 Rise time of I2Cx_SDA signals

IC11 Fall time of I2Cx_SDA signals

—

120

12 (@3.3 V)

6.5 (@1.8 V)

IC10b Rise time of I2Cx_SCL signals

IC11b Fall time of I2Cx_SCL signals

—

120

12 (@3.3 V)

6.5 (@1.8 V)

IC12 Capacitive load for each bus line (Cb)

—

550

—

100

High-speed mode is only available for I2C modules in DMA, SCU and Cortex-M4 subsystems.

4.10.10 LVDS and MIPI-DSI display output specifications

4.10.10.1 LVDS display bridge module parameters

Maximum frequency support for dedicated LVDS channels on this device:

Table 81. LVDS pins

Function¹

Channel A

Channel B

4 pairs LVDS up to 1.12 Gbps per pair

Single channel

Dual channel

4 pairs LVDS up to 1.12 Gbps per pair

8 pairs LVDS up to 595 Mbps per pair

In single channel operation the maximum clock speed is 160 MHz; in dual channel operation with a single synchronized clock

the maximum clock speed is 85 MHz.

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4.10.10.2 MIPI-DSI display bridge module parameters

Maximum frequency support for dedicated MIPI-DSI channels on this device:

Table 82. MIPI-DSI pins

Function¹

Channel A

DSI

DSI up to 1.5 Gb/per lane

Maximum clock speed is 1.5 GHz.

4.10.10.3 LVDS display bridge (LDB) module electrical specifications

The LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see TIA/EIA

STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface

Circuits.”

Table 83. LVDS Display Bridge (LDB) Electrical Specifications

Parameter

Symbol

Test Condition

100 Ω Differential load

Min

Max

Units

Differential Voltage Output Voltage

Output Voltage High

V_OD

Voh

0.25

—

0.4

100 Ω differential load

(0 V Diff—Output High Voltage static)

1.475

Output Voltage Low

Offset Static Voltage

Vol

100 Ω differential load

0.925

1.125

—

(0 V Diff—Output Low Voltage static)

V_OS

Two 49.9 Ω resistors in series between

N-P terminal, with output in either Zero or

One state, the voltage measured between

the 2 resistors.

1.275

VOS Differential

V_OSDIFF

Difference in V_OSbetween a One and a

Zero state

—

Output short-circuited to GND

Output short current

ISA ISB

ISAB

With the output common shorted to GND

—

4.10.10.4 MIPI-DSI HS-TX specifications

Table 84. MIPI high-speed transmitter DC specifications

Parameter

Symbol

Min Typ Max

Unit

V_CMTX

High Speed Transmit Static Common Mode Voltage

V_CMTXmismatch when Output is Differential-1 or Differential-0

High Speed Transmit Differential Voltage

150 200

250

|ΔV_{CMTX (1,0)}

—

|V_OD

140 200

270

|ΔV_OD

V_ODmismatch when Output is Differential-1 or Differential-0

—

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Table 84. MIPI high-speed transmitter DC specifications (continued)

Parameter Min Typ Max

Symbol

Unit

V_OHHS

High Speed Output High Voltage

Single Ended Output Impedance

—

360

62.5

Z_OS

ΔZ_OS

Single Ended Output Impedance Mismatch

Value when driving into load impedance anywhere in the Z_IDrange.

Table 85. MIPI high-speed transmitter AC specifications

Symbol

Parameter

Min

Typ

Max

Unit

ΔV_CMTX(HF)

ΔV_CMTX(LF)

Common-level variations above 450 MHz

Common-level variation between 50-450 MHz

Rise Time and Fall Time (20% to 80%)

—

mVRMS

mVPEAK

t_Rand t_F

100

0.35 UI

UI is the long-term average unit interval.

4.10.10.5 MIPI-DSI LP-TX specifications

Table 86. MIPI low-power transmitter DC specifications

Symbol

Parameter

Min

Typ

Max

Unit

V_OH

Thevenin Output High Level

Thevenin Output Low Level

1.1

–50

110

1.2

—

1.3

—

V_OL

Z_OLP

Output Impedance of Low Power Transmitter

—

This specification can only be met when limiting the core supply variation from 1.1 V till 1.3 V.

Although there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification

is met.

Table 87. MIPI low-power transmitter AC specifications

Symbol

Parameter

Min Typ Max Unit

T_RLP/T_FLP

15% to 85% Rise Time and Fall Time

30% to 85% Rise Time and Fall Time

—

1,2,3

T_REOT

T_LP-PULSE-TXPulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop 40

state or last pulse before Stop state

Pulse width of the LP exclusive-OR clock: All other pulses

Period of the LP exclusive-OR clock

—

T_LP-PER-TX

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Table 87. MIPI low-power transmitter AC specifications (continued)

Parameter Min Typ Max Unit

Symbol

1,5,6,7

δV/δt_SR

Slew Rate @ CLOAD= 0 pF

Slew Rate @ CLOAD= 5 pF

Slew Rate @ C^LOAD= 20 pF

Slew Rate @ CLOAD= 70 pF

Load Capacitance

—

500 mV/ns

200 mV/ns

150 mV/ns

100 mV/ns

C_LOAD

C_LOADincludes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <

10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay.

The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due

to stopping the differential drive.

With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane.

This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches

between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11)

is glitch behavior as described in Low-Power Receiver section.

When the output voltage is between 15% and below 85% of the fully settled LP signal levels.

Measured as average across any 50 mV segment of the output signal transition.

This value represents a corner point in a piecewise linear curve.

4.10.10.6 MIPI-DSI LP-RX specifications

Table 88. MIPI low power receiver DC specifications

Parameter Min

Symbol

V_IH

Typ

Max

Unit

Logic 1 input voltage

880

—

1.3

550

300

—

V_IL

Logic 0 input voltage, not in ULP state

Logic 0 input voltage, ULP state

Input hysteresis

V_IL-ULPS

V_HYST

—

Table 89. MIPI low power receiver AC specifications

Symbol

Parameter

Min

Typ

Max

Unit

1,2

e_SPIKE

Input pulse rejection

—

300

—

V.ps

T_MIN-RX

Minimum pulse width response

Peak Interference amplitude

Interference frequency

V_INT

—

200

—

MHz

f_INT

450

Time-voltage integration of a spike above V_ILwhen in LP-0 state or below VIH when in LP-1 state.

An impulse below this value will not change the receiver state.

An input pulse greater than this value shall toggle the output.

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4.10.10.7 MIPI-DSI LP-CD specifications

Table 90. MIPI contention detector DC specifications

Parameter Min

Symbol

Typ

Max

Unit

V_IHCD

V_ILCD

Logic 1 contention threshold

Logic 0 contention threshold

450

—

200

4.10.10.8 MIPI-DSI DC specifications

Table 91. MIPI input characteristics DC specifications

Symbol

V_PIN

Parameter

Min

Typ

Max

Unit

Pad signal voltage range

Pin leakage current

Ground shift

–50

–10

–50

–0.15

—

1350

μA

I_LEAK

V_GNDSH

V_PIN(absmax)

Maximum pin voltage level

1.45

T_VPIN(absmax)Maximum transient time above V_PIN(max)or below V_PIN(min)

When the pad voltage is within the signal voltage range between V_GNDSH(min)to VOH + V_GNDSH(max)and the Lane Module is

in LP receive mode.

This value includes ground shift.

The voltage overshoot and undershoot beyond the V_PINis only allowed during a single 20 ns window after any LP-0 to LP-1

transition or vice versa. For all other situations it must stay within the V_PINrange.

4.10.11 PCIe PHY Parameters

The TX and RX eye diagrams specifications are per the template shown in the following figure. The

summary of specifications is shown in Table 92 and Table 93. Note that the time closure (1–AOPENING)

in the eye templates needs not match jitter specifications in the Standards Specifications, as there are such

discrepancies in some Standards Specifications. The design meets the tightest of specifications in case of

discrepancy.

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Figure 40. TX and RX eye diagram template

Table 92. PCIe transmitter eye specifications for example standards

UI A_OPENINGB_OPENINGA_OPENINGB_OPENINGV_DIFFp-pmin V_DIFFp-pmax

PCI Express Gen 1 Transition Bit

PCI ExpressGen 1 De-emphasized Bit

PCI Express Gen 2 Transition Bit

PCI Express Gen 2 De-emphasized Bit

400

200

0.75

300

150

800

505

800

379

1200¹

757

1200¹

850

V_DIFFp-peye opening is limited to VDDIO under matched termination conditions.

Table 93. PCIe receiver eye specifications for example standards

UI A_OPENINGB_OPENINGA_OPENINGB_OPENINGV_DIFFp-pmin V_DIFFp-pmax

PCI Express Gen 1 Transition Bit

400

200

125

0.4

0.32

0.3

160

175

100

1200

1300

PCI Express Gen 2 Transition Bit¹

PCI Express Gen 3 Virtual EYE²

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For a lossy channel, the default DFE setting may not work for PCIe Gen1 -3.5dB TX de-emphasis. It is recommended to use

a higher DFE setting (reg241[7]=A1_force=1 and reg241[5:0]=A1_init) in this case.

PCIE 3.0 8 GT/s measured using PCIE reference equalizer + CDR per PCIE specification.PCIe 1.0 and 2.0 compliant. PCIe

3.0 capable, contact your NXP representative.

Table 94. PCIe differential output driver characteristics (including board and load)

Parameter

Min

Typ

Max

Units

Notes

Output Rise and fall time T_R, T_F

175

—

350

—

μs

1, 2

Output Rise/Fall matching

Output skewT_OSKEW

—

Initialization time from assertion of TXOE

Initialization time from assertion of TXENA

Transmission line characteristic impedance (Z_O)

100

—

Driver output impedance, single ended (small signal @

Vout=Vcm)

—

1000

—

Output single ended voltage (RS= 33, RT= 50 Ω)

3, 4

V_OH

0.65

-13

-0.20

0.71

-14.2

0.00

0.85

-17

0.05

I_OH@ 6 * I_R

V_OL

Output common mode voltage (RS = 33, RT= 50 Ω)

|V_OCM

0.25

-0.015

-0.050

0.375

0.55

0.015

0.050

ΔV_{OCM (DC)}

ΔV_{OCM (AC)}

7,8

Buffer induced deterministic jitter (absolute, pk-pk)

Reference Buffer Dynamic Power (Digital)

Reference Buffer Dynamic Power (Analog)

Output Buffer Dynamic Power (Digital)

—

μA

0.015

2.8

0.66

3.14

1.8

0.035

18.9

Output Buffer Dynamic Power (Analog)

22.11

When the output is transitioning between logic 0 and logic 1, or logic 1 and logic 0, and driving a terminated

transmission line, the outputs monotonically transition between VOL and VOH, VOH, and VOL respectively. Target rise and

fall times observed at the receiver and are primarily set by board trace impedance and Load capacitance. Rise and fall

times are defined by 25% and 75% crossing points.

Calculated as: 2 × (TR–TF) / (TR+ TF)

I_Ris proportional to the reference current. Measured across RT. The primary contributor to output voltage spread is

VDD spread, and so a VDD tighter than ±10% may be required to achieve this spread.

Higher output voltages may occur depending on load, power supply, and selected output drive. Higher output voltages may

transiently occur during initialization period following TXENA assertion.

Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under DC conditions.

Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under AC conditions.

Measured under “clean power supply and ground” conditions, and after de-embedding the jitter of the input, measured over a

time span of 1000 cycles

Power supply induced jitter is included under this category, and the power supply variation is to be less than 8mVpp.

Note that customer has to be uncommonly careful with power supply fidelity due to the small jitter numbers.

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Power consumption is simulated under the following conditions:

Typ: TT, VDD=1.0 V, VD18=1.8 V, 25 °C

Max: FF, VDD=1.1 V, VD18=1.98 V, 125 °C

Dynamic: TXENA=1, TXOE=1

Static: TXENA=0, TXOE=1

4.10.11.1 PCIE_REXT reference resistor connection

The following figure shows the PCIE_REXT reference resistor connection.

Figure 41. PCIE_REXT reference resistor connection

4.10.11.2 PCIE_REF_CLK

Contact an NXP representative to obtain the hardware development guide for this device, which contains

details on the PCIe reference clock requirements.

4.10.12 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

The following figure depicts the timing of the PWM, and Table 95 lists the PWM timing parameters.

PWMn_OUT

Figure 42. PWM Timing

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Table 95. PWM Output Timing Parameters

Parameter

PWM Module Clock Frequency

Min

Max

Unit

—

ipg_clk

—

MHz

PWM output pulse width high

PWM output pulse width low

—

4.10.13 FlexSPI (Quad SPI/Octal SPI) timing parameters

The FlexSPI interface can work in SDR or DDR modes. It can operate up to 60 MHz at 3.3 V, 166 MHz

at 1.8 V SDR mode or 200 MHz at 1.8 V DDR mode. It supports single-ended and differential DQS

signaling.

FlexSPI supports the following clocking scheme for a read data path:

•

Dummy read strobe generated by FlexSPI controller and looped back internally

(FlexSPIn_MCR0[RXCLKSRC] = 0x0)

Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x1). It means the I/O cannot be used for another feature.

Read strobe provided by memory device and input from DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x3)

4.10.13.1 SDR mode

4.10.13.1.1 SDR mode timing diagrams

The following write timing diagram is valid for any FlexSPIn_MCR0[RXCLKSRC] value.

Figure 43. FlexSPI write timing diagram (SDR mode)

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The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1.

Figure 44. FlexSPI read timing diagram (SDR mode)

The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x3.

Figure 45. FlexSPI read with DQS timing diagram (SDR mode)

4.10.13.1.2 SDR mode timing parameter tables

Table 96. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (SDR mode)

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

MHz

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

7.5

SCLK

t3 QSPIx[A/B]_SSy_B Lead Time¹

TCSS+0.5

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH

t5 QSPIx[A/B]_DATAy output Delay

t6 QSPIx[A/B]_DATAy Setup Time

—

t7 QSPIx[A/B]_DATAy Hold Time

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

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Table 97. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (SDR mode)

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

166

—

MHz

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

2.7

SCLK

t3 QSPIx[A/B]_SSy_B Lead Time¹

TCSS+0.5

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH

t5 QSPIx[A/B]_DATAy output Delay

t6 QSPIx[A/B]_DATAy Setup Time

—

t7 QSPIx[A/B]_DATAy Hold Time

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 98. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (SDR mode)

Parameter

QSPIx[A/B]_DQS Cycle frequency

Min

Max

Unit

—

2.25

200

—

MHz

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width¹

t3 QSPIx[A/B]_SSy_B Lead Time²

t4 QSPIx[A/B]_SSy_B Lag Time²

CSINTERVAL

TCSS+0.5

TCSH

—

SCLK

—

t5 QSPIx[A/B]_DATAy output Delay

t8 QSPIx[A/B]_DQS / QSPIx[A/B]_DATAy delta

—

-0.65

0.65

Minimum is 2 SCLK cycles even if CSINTERVAL value is less than 2.

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

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4.10.13.2 DDR mode

4.10.13.2.1 DDR mode timing diagrams

Figure 46. FlexSPI write timing diagram (DDR mode)

Figure 47. FlexSPI read timing diagram (DDR mode)

QSPIx[A/B]_DQS

QSPIx[A/B]_DATAy

t10

Figure 48. FlexSPI read with DQS timing diagram (DDR mode)

Table 99. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode)

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

MHz

t1 QSPIx[A/B]_SCLK High or Low Time

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Table 99. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) (continued)

Parameter

Min

Max

Unit

t2 QSPIx[A/B]_SSy_B pulse width

—

SCLK

t3 QSPIx[A/B]_SSy_B Lead Time¹

(TCSS+0.5)/2

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH/2

t5 QSPIx[A/B]_DATAy output valid time

t6 QSPIx[A/B]_DATAy output hold time

t7 QSPIx[A/B]_DATAy Setup Time

6.5

t8 QSPIx[A/B]_DATAy Hold Time

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 100. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (DDR mode)

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

MHz

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

5.4

SCLK

t3 QSPIx[A/B]_SSy_B Lead Time¹

(TCSS+0.5)/2

t4 QSPIx[A/B]_SSy_B Lag Time¹

TCSH/2

t5 QSPIx[A/B]_DATAy output valid time

t6 QSPIx[A/B]_DATAy output hold time

t7 QSPIx[A/B]_DATAy Setup Time

t8 QSPIx[A/B]_DATAy Hold Time

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

Table 101. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode)

Parameter

QSPIx[A/B]_SCLK Cycle frequency

Min

Max

Unit

—

2.25

200

—

MHz

t1 QSPIx[A/B]_SCLK High or Low Time

t2 QSPIx[A/B]_SSy_B pulse width

t3 QSPIx[A/B]_SSy_B Lead Time¹

t4 QSPIx[A/B]_SSy_B Lag Time¹

t5 QSPIx[A/B]_DATAy output valid time

t6 QSPIx[A/B]_DATAy output hold time

SCLK

(TCSS+0.5)/2

TCSH/2

0.65

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Table 101. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode) (continued)

Parameter

Min

Max

Unit

t9 QSPIx[A/B]_DATAy Setup Skew

—

0.65

t10 QSPIx[A/B]_DATAy Hold Skew

Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

4.10.14 Secure JTAG controller (SJC)

4.10.14.1 Internal pull-up/pull-down configuration

The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG

interface. External pull-ups and pull-downs are needed when this interface is routed to a connector.

Table 102. JTAG default configuration for internal pull-up/pull-down

Ball name

Internal pull setting¹

Typical pull value

Unit

JTAG_TMS

JTAG_TCK

JTAG_TDI

KΩ

JTAG_TRST_B

TEST_MODE_SELECT

PU = pull-up; PD = pull-down

4.10.14.2 JTAG timing parameters

Figure 49 depicts the SJC test clock input timing. Figure 50 depicts the SJC boundary scan timing.

Figure 51 depicts the SJC test access port. Figure 52 depicts the JTAG_TRST_B timing. Signal

parameters are listed in Table 103.

SJ1

SJ2

JTAG_TCK

(Input)

VIH

VIL

SJ3

Figure 49. Test Clock Input Timing Diagram

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JTAG_TCK

(Input)

VIH

SJ5

Input Data Valid

VIL

SJ4

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 50. Boundary system (JTAG) timing diagram

JTAG_TCK

(Input)

VIH

VIL

SJ8

Input Data Valid

SJ9

JTAG_TDI

JTAG_TMS

(Input)

SJ10

SJ11

SJ10

JTAG_TDO

(Output)

Output Data Valid

JTAG_TDO

(Output)

JTAG_TDO

(Output)

Output Data Valid

Figure 51. Test Access Port Timing Diagram

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JTAG_TCK

(Input)

SJ13

JTAG_TRST_B

(Input)

SJ12

Figure 52. JTAG_TRST_B Timing Diagram

Table 103. JTAG Timing

All Frequencies

Parameter^1,2

Unit

Min

Max

SJ0

SJ1

SJ2

JTAG_TCK frequency of operation 1/(3xT_DC

JTAG_TCK cycle time in crystal mode

)

0.001

22.5

—

MHz

JTAG_TCK clock pulse width measured at V_M

JTAG_TCK rise and fall times

SJ3

SJ4

Boundary scan input data set-up time

Boundary scan input data hold time

JTAG_TCK low to output data valid

JTAG_TCK low to output high impedance

JTAG_TMS, JTAG_TDI data set-up time

JTAG_TMS, JTAG_TDI data hold time

JTAG_TCK low to JTAG_TDO data valid

—

SJ5

—

SJ6

SJ7

—

SJ8

SJ9

—

SJ10

SJ11

SJ12

SJ13

JTAG_TCK low to JTAG_TDO high impedance

JTAG_TRST_B assert time

—

100

JTAG_TRST_B set-up time to JTAG_TCK low

= target frequency of SJC

V_M= mid-point voltage

4.10.15 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 104, Figure 53, and Figure 54 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

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Table 104. SPDIF Timing Parameters

Timing Parameter Range

Parameter

Symbol

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

srckp

srckpl

V_M

srckph

V_M

SPDIF_SR_CLK

(Output)

Figure 53. SPDIF_SR_CLK Timing Diagram

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 54. SPDIF_ST_CLK Timing Diagram

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4.10.16 UART I/O configuration and timing parameters

4.10.16.0.1 UART Transmitter

The following figure depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1

stop bit format. Table 105 lists the UART RS-232 serial mode transmit timing characteristics.

POSSIBLE

PARITY

UA1

Bit 3

BIT

START

BIT

Start

Bit

UARTx_TX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 55. UART RS-232 Serial Mode Transmit Timing Diagram

Table 105. UART RS-232 Serial Mode Transmit Timing Parameters

Parameter

Transmit Bit Time

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

UA1

t_Tbit

1/F_{baud_rate}¹– T_{ref_clk}

—

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0]

× (OSR+1)).

T_{ref_clk}: The period of UART reference clock ref_clk (LPUART_clk after SBR divider).

4.10.16.0.2 UART Receiver

The following figure depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format.

Table 106 lists serial mode receive timing characteristics.

POSSIBLE

PARITY

UA2

Bit 3

BIT

START

BIT

Start

Bit

UARTx_RX_DATA

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 56. UART RS-232 Serial Mode Receive Timing Diagram

Table 106. RS-232 Serial Mode Receive Timing Parameters

Parameter

Receive Bit Time¹

Symbol

Min

Max

Unit

UA2

t_Rbit

1/F_{baud_rate}

–

1/F_{baud_rate}

—

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate})

The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit, but accumulation tolerance in one frame must

not exceed 3/((OSR+1) × Fbaud_rate).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] ×

(OSR+1)).

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4.10.16.0.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

UART IrDA Mode Transmitter

The following figure depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format.

Table 107 lists the transmit timing characteristics.

UA3

UA4

UA3

UARTx_TX_DATA

(output)

Start

Bit

STOP

BIT

POSSIBLE

PARITY

BIT

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 57. UART IrDA Mode Transmit Timing Diagram

Table 107. IrDA Mode Transmit Timing Parameters

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

UA3 Transmit Bit Time in IrDA mode

UA4 Transmit IR Pulse Duration

t_TIRbit

1/F_{baud_rate}¹– T_{ref_clk}

—

t_TIRpulse(TNP+1)/(OSR+1) × (1/F_{baud_rat}(TNP+1)/(OSR+1) × (1/F_{baud_rat}

_e) – T_{ref_clk e}) + T_{ref_clk}

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] ×

(OSR+1)).

T_{ref_clk}: The period of UART reference clock ref_clk (LPUART_clk after SBR divider).

UART IrDA Mode Receiver

The following figure depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format.

Table 108 lists the receive timing characteristics.

UA5

UA6

UA5

UARTx_RX_DATA

(input)

STOP

BIT

Start

Bit

POSSIBLE

PARITY

BIT

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 58. UART IrDA Mode Receive Timing Diagram

Table 108. IrDA Mode Receive Timing Parameters

Parameter

Symbol

Min

Max

1/F_{baud_rate}

Unit

UA5 Receive Bit Time¹in IrDA mode

t_RIRbit

1/F_{baud_rate}

–

—

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate}

)

UA6 Receive IR Pulse Duration

t_RIRpulse

1.41 μs

(5/16) × (1/F_{baud_rate}

)

—

The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame

must not exceed 3/((OSR+1) × Fbaud_rate).

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Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] ×

(OSR+1)).

4.10.17 USB HSIC Timings

This section describes the electrical information of the USB HSIC port.

NOTE

HSIC is a DDR signal. The following timing specification is for both rising

and falling edges.

4.10.17.1 USB HSIC Transmit Timing

Tstrobe

USB_H_STROBE

Todelay

USB_H_DATA

Figure 59. USB HSIC Transmit Waveform

Table 109. USB HSIC Transmit Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

4.165

550

4.168

1350

—

Todelay data output delay time

Measured at 50% point

Averaged from 30% – 70% points

Tslew

strobe/data rising/falling time

0.7

V/ns

4.10.17.2 USB HSIC Receive Timing

Tstrobe

USB_H_STROBE

USB_H_DATA

Thold

Tsetup

Figure 60. USB HSIC Receive Waveform

Table 110. USB HSIC Receive Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

Thold data hold time

4.165

300

4.168

—

Measured at 50% point

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Table 110. USB HSIC Receive Parameters (continued)

Name

Parameter

Min

Max

Unit

Comment

Tsetup

Tslew

data setup time

300

0.7

—

Measured at 50% point

Averaged from 30% – 70% points

strobe/data rising/falling time

V/ns

The timings in the table are guaranteed when:

^{—AC I/O voltage is between 0.9}× to 1× the I/O supply

—DDR_SEL configuration bits of the I/O are set to (10)b

4.10.18 USB 2.0 PHY Parameters

4.10.18.1 USB 2.0 PHY Transmitter specifications

This section describes the transmitter specifications for USB2.0 PHY.

4.10.18.1.1 USB 2.0 PHY full-speed/low-speed transmitter specifications

The following table lists the full-speed/low-speed (FS/LS) transmitter specifications for USB2.0 PHY.

Table 111. USB 2.0 PHY FS/LS transmitter specifications

Symbol

Description

Min Typ

Max

Units

VOL

VOH

Output Voltage Low

2.8

0.8

1.3

—

0.3

3.6

—

Output Voltage High (Driven)

VOSE1 Single Ended One (SE1)

VCRS

TFR

TLR

TFF

Output Signal Cross Over Voltage

2.0

Driver Rise Time - FS

Driver Rise Time - LS

Driver Fall Time - FS

Driver Fall Time - LS

300

TLF

300

111.11

125

49.5

3.5

TFRFM Differential Rise and Fall Time Matching - FS

TLRFM Differential Rise and Fall Time Matching - LS

ZHSDRV Driver Output Resistance (Also serves as HS Termination)

40.5

-3.5

-4

TDJ1

TDJ2

Source Jitter (Next Transition) - FS

Source Jitter (Paired Transition) - FS

TFDEOP Source Jitter (Differential to SE0 transition) - FS

TFEOPT Source SE0 interval of EOP - FS

-2

160

-25

-14

-95

175

TDDJ1

TDDJ2

TUDJ1

Source Jitter in downstream direction (Next Transition) - LS

Source Jitter in downstream direction (Paired Transition) - LS

Source Jitter in upstream direction (Next Transition) - LS

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Table 111. USB 2.0 PHY FS/LS transmitter specifications (continued)

Symbol

Description

Min Typ

Max

Units

TUDJ2

Source Jitter in upstream direction (Paired Transition) - LS

-150

-40

—

150

100

1.5

μs

TLDEOP Source Jitter in upstream direction (Differential to SE0 transition) - LS

TLEOPT Source SE0 interval of EOP - LS

1.25

4.10.18.2 USB 2.0 PHY high-speed transmitter specifications

The following table lists the high-speed (HS) transmitter specifications for USB 2.0 PHY.

Table 112. USB 2.0 PHY HS transmitter specifications

Symbol/Parameter

Description

Min Typ

Max

Units

HSOI

High Speed Idle Level

-10

—

VHSTERM

VHSOL

Termination Voltage in High Speed

High Speed Data Signaling Low

Chirp J (Differential Voltage)

Chirp K (Differential Voltage)

Driver Output Resistance

-10

VCHIRPJ

700

-900

40.5

100

-300

1100

-500

49.5

—

VCHIRPK

ZHSDRV

THSR

Rise Time (10% to 90%)

THSF

Fall Time (10% to 90%)

—

HS Eye Opening: Template 1

Differential eye opening at 37.5% US and 62.5% UI for a

hub measured at TP2 and for a device without a captive

cable measured at TP3.

300

HS Eye Opening: Template 2

HS Jitter: Template 1

Differential eye opening at 37.5% US and 62.5% UI for a

device with a captive cable measured at TP2.

-175

—

175

Peak-Peak Jitter at Zero crossing for a hub measured at

TP2 and for a device without captive cable measured at

TP3.

—

%UI

312.5

HS Jitter: Template 2

Peak-Peak Jitter at Zero crossing for a device with captive

cable measured at TP2.

—

%UI

520.83

4.10.18.3 USB 2.0 PHY receiver specifications

This section describes the receiver specifications implemented in USB 2.0 PHY.

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4.10.18.3.1 USB 2.0 PHY full-speed/low-speed (FS/LS) receiver specifications

Table 113. USB 2.0 PHY FS/LS receiver specifications

Symbol

VIH

Description

Input Voltage Level - High (Driven)

Min

Typ

Max

Units

2.7

—

3.6

0.8

2.0

2.5

18.5

VIHZ

Input Voltage Level - High (Floating)

VIL

Input Voltage Level - Low

VTH

Switching Threshold

0.8

-18.5

-9

VCM

Common Mode Range

TJR1

Receiver Jitter Budget (Next Transition) - FS

Receiver Jitter Budget (Paired Transition) - FS

Receiver EOP Interval of EOP - FS

TJR2

TFEOPR

TUJR1

TUJR2

TDJR1

TDJR2

TLEOPR

—

US Port Differential Receiver Jitter (Next Transition) - LS

US Port Differential Receiver Jitter (Paired Transition) - LS

DS Port Differential Receiver Jitter (Next Transition) - LS

DS Port Differential Receiver Jitter (Paired Transition) - LS

Receiver EOP Interval of EOP - LS

-152

-200

-75

-45

670

152

200

—

4.10.18.3.2 USB 2.0 PHY high-speed receiver specifications

The following table lists the high-speed (HS) receiver specifications for USB 2.0 PHY.

Table 114. USB 2.0 PHY HS receiver specifications

Symbol/Parameter

VHSCM

Description

Min Typ Max Units

HS RX input common mode voltage range.

-50

40.5

—

500

49.5

ZHSDRV

HS RX input termination (Same as Driver output resistance).

HSRX Jitter: Template 3

HS RX Peak-Peak Jitter specification at differential zero crossing for a

device with captive cable when signal applied at TP2.

%UI

—

416.66 ps

HSRX Jitter: Template 4

HS RX Peak-Peak Jitter specification at differential zero crossing for a

device without captive cable at TP3 and for a hub at TP2.

—

%UI

—

625

275

HSRX Input Eye Opening: HS RX differential sensitivity specification at 40% and 60% UI for a

Template 3 device with captive cable when signal is applied at TP2.

-275

HSRX Input Eye Opening: HS RX differential sensitivity specification at 35% and 65% UI for a

-150

—

150

Template 4

device without captive cable when signal is applied at TP3 and for a

hub when a signal is applied at TP2.

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4.10.18.3.3 USB 2.0 PHY high-speed envelope detector specifications

The following table lists the high-speed (HS) Envelope Detector Specifications of USB 2.0 PHY.

Table 115. USB 2.0 PHY HS envelope detector specifications

Symbol

Description

Min Typ Max Units

VHSSQ

VHSDSC

HS Squelch Detection threshold (differential signal amplitude)

HS Disconnect Detection threshold (differential signal amplitude)

100

525

—

150

625

4.10.18.4 USB 2.0 PHY full-speed/high-speed terminations specification

The following table lists the full-speed/low-speed (FS/LS) Terminations Specification of USB 2.0 PHY.

Table 116. USB 2.0 PHY FS/LS terminations specification

Symbol

RPU

Description

Min

Typ

Max

Units

Bus Pull-Up resistor on US Port in IDLE State

Bus Pull-Up resistor on US Port in ACTIVE State

Bus Pull-Down resistor on DS Port

900

1425

14.25

3.0

—

1575

3090

24.8

3.6

RPD

KΩ

VTERM

Termination Voltage for US Port Pull-Up (RPU)

4.10.18.5 Voltage threshold specification

The following table lists the OTG Comparator Specifications of USB2.0 PHY.

Table 117. USB 2.0 PHY OTG comparator specifications

Symbol

Description

Min

Typ

Max

Units

sessvld

vbusvalid

B-Device Session Valid threshold

VBUS Valid threshold

0.8

4.4

—

4.0

4.75

4.10.19 USB 3.0 PHY parameters

The following content is from the USB 3.0 PHY specifications.

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4.10.19.1 USB 3.0 PHY external component

Table 118. USB 3.0 PHY external component specifications

Name Min Typ Max Units

rext 497.5 500 502.5

Descriptions

There needs to be an external resistor component connected at rext ball while the

internal resistor or current is getting calibrated. Package routing from rext ball to its

respective bump should not contribute more than 0.05 Ω.

4.10.19.2 USB 3.0 PHY transmitter module

Table 119. USB 3.0 PHY transmitter module electrical specifications

Symbol

Description

Min Typ

Max

Unit

Voltage/current parameters

V_TX-DIFFp

Programmable output voltage

swing (single-ended)

—

500

1000

1200

100

V_TX-DIFFp-p

Programmable differential

peak-to-peak output voltage

100

400

V_{TX-DIFFp-p-LOW}

Low power differential p-p TX

voltage swing

I_TX-SHORT

RL_TX-DIFF

Transmit lane short-circuit current

Transmitter differential return loss

—

0 < -20dB < 100Mhz

100Mhz < -18dB < 300Mhz

300Mhz < -16dB < 600Mhz

600Mhz < -10dB < 2500Mhz

2500Mhz < -9dB < 4875Mhz

4875Mhz < -8dB < 11200Mhz

11200Mhz < -5dB < 16800Mhz

and -3dB beyond that

Transmitter common mode return

loss

—

50Hz < -8dB < 15000Mhz

TX-CM

DC differential TX impedance

Unit Interval

100

120

TX-DIFF-DC

199.94

—

200.06

0.4

T_{TX-MAX-JITTER}

Transmitter total jitter

(peak-to-peak) (Tj)

T_{TX-RJ-PLL-sigma}

After application of TX jitter transfer

function

—

2.42

210

LTLAT-10

Transmitter data latency

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Table 119. USB 3.0 PHY transmitter module electrical specifications (continued)

Symbol

Description

Min Typ

Max

Unit

Voltage parameters

V_{TX-CM-DC-ACTIVE-IDLE-DELTA}Absolute Delta of DC Common

Mode Voltage during L0 and

—

100

Electrical Idle.

V_{TX-IDLE-DIFF-AC-p}

V_{TX-CM-DC-LINE-DELTA}

V_{TX-RCV-DETECT}

Electrical Idle Differential Peak

Output Voltage

—

600

Absolute Delta of DC Common

Mode Voltage between D+ and D-

The amount of voltage change

allowed during Receiver Detection

T_{TX-IDLE-SET-TO-IDLE}

Maximum time to transition to a

valid Electrical Idle after sending an

EIOS

—

T_{TX-IDLE-TO-DIFF-DATA}

Maximum time to transition to valid

diff signaling after leaving Electrical

Idle

—

V_TX-CM-AC-PP

Tx AC peak-peak common mode

voltage (5.0 GT/s)

—

150

mVpp

T_EIExit

Time to exit Electrical Idle (L0s)

state and to enter L0

Txsysclk

Tx signal characteristics

f_tol

TX Frequency Long Term Accuracy -300

—

300

ppm of

Fbaud

f_SSC

Spread-Spectrum Modulation

Frequency

kHz

t_20-80TX

t_skewTX

TX Rise/Fall Time

0.2

—

0.41

TX Differential Skew

For USB 3.0, no EQ is required

4.10.19.3 USB 3.0 PHY receiver module

Table 120. USB 3.0 PHY receiver module electrical specifications

Symbol

Description

Min

Voltage Parameters

100

Typ Max Unit

Comments

V_RX-DIFF(p-p)

Differential input voltage

(peak-to-peak) (that is, receiver

eye voltage opening)

—

1200 mV

—

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Table 120. USB 3.0 PHY receiver module electrical specifications (continued)

Symbol

Description

Min

Typ Max Unit

Comments

V_{RX-IDLE-DET-DIFF(p-p}Differential input threshold voltage

100

—

300

mV USB3 LFPS

(peak-to-peak) to detect idle

(LFPS)

)

V_{cm, acRX}

RX AC Common Mode Voltage

—

100 mVp-p Simulated at 250 MHz

V_RX-CM-AC

Receiver common-mode voltage

for AC coupling

150

—

Z_RX-DIFF-DC

RL_RX-DIFF

Differential input impedance (DC)

Receiver differential return loss

100 120

100 Ω ± 10%

Same as

TX RL

—

Jitter Parameters

T_{RX-MAX-JITTER}

Receiver total jitter tolerance

—

0.66

Incoming Jitter:

USB3 = 0.43UI DJ + 0.23UI RJ

USB3 numbers are with REFC-TLE

Table 121. PLL module electrical specifications

Parameter

Symbol

Description

Min

Typ

Max Units

Input Reference Clock

REF CLK

Frequency

REF CLK

—

19.2 19.2/24/25/26/38.4 38.4 MHz

REF CLK Duty

Cycle

—

MHz

REF CLK

Frequency

REF CLK

—

40/48/50/52/100 100

REF CLK RJ

Tolerance

Integrated jitter from 10 kHz to 16 MHz

after applying appropriate PLL ref clock

transfer function and the protocol JTF

—

0.5

REF CLK Duty

Cycle

—

Divided Reference

Frequency

—

19.2

38.4 MHz

Dividers

Input division

IPDIV<7:0>

—

255 Counts

1025 Counts

<2 Counts

Feedback division pll_fbdiv_high<9:0>

pll_fbdiv_low<9:0>

Feedback fractional

division range

—

>-2

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Table 121. PLL module electrical specifications (continued)

Parameter

Number of

Symbol

Description

Min

Typ

Max Units

—

This includes one bit for sign

—

Bits

fractional bits

VCO

Clock frequency

VCO frequency

—

Output full rate clocks

—

5000

—

MHz

ppm

VCO oscillation frequency

This includes SSC deviation

Output clock

-5300

300

frequency tolerance

SSC modulation

rate

—

As applicable for USB3.0

—

kHz

Output clock RJ

sigma for TX

After application of TX jitter transfer

function

2.42

1.40

Output clock RJ

sigma for RX

After application of RX jitter transfer

function

4.11 Analog-to-digital converter (ADC)

The following table shows the ADC electrical specifications for VREFH=VDD_ADC_1P8.

Table 122. ADC electrical specifications (VREFH=VDD_ADC_1P8)

Symbol

V_ADIN

Description

Min

Typ¹

Max

Unit

Notes

Input Voltage

VREFL

—

4.5

500

—

VREFH

—

C_ADIN

R_ADIN

R_AS

Input capacitance

Input Resistance

—

Analog Source Resistance

ADC Conversion Clock Frequency

Sample cycles

—

kΩ

f_ADCK

—

MHz

—

C_sample

C_compare

C_conversion

DNL

3.5

—

131.5

—

Fixed compare cycles

Conversion cycles

Differential Non-Linearity

Integral Non-Linearity

Effective Number of Bits

Avg = 1

17.5

cycles

LSB

—

C_{conversion =}C_{sample +}C_compare

—

± 0.6

± 0.9

—

-0.5 to +1.1

INL

±1.1

—

5,6,7

ENOB

—

10.1

10.5

11.1

10.4

10.7

11.3

—

Bits

Avg = 2

—

Avg = 16

—

SINAD

Signal to Noise plus Distortion

SINAD=6.02 x ENOB + 1.76

—

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Table 122. ADC electrical specifications (VREFH=VDD_ADC_1P8) (continued)

Symbol

Description

Min

Typ¹

Max

Unit

Notes

E_G

E_O

Gain error

—

-0.29

0.01

—

%FSV

μA

Offset error

Supply Current

I_VDDA18

I_in,ext,leak

E_IL

480

—

External Channel Leakage Current

Input leakage error

500

—

RAS * I_in

Typical values assume VDD_ADC_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for

reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production.

This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS

(analog source capacitance) time constant should be kept to < 1 ns.

See Figure 61.

ADC conversion clock at max frequency and using linear histogram.

Input data used for test was 1 kHz sine wave.

Measured at VREFH = 1.8 V and pwrsel = 2.

ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling

may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling

becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content.

Error measured at fullscale at 1.8 V.

Error measured at zero scale at 0 V.

¹⁰Power Configuration Select, PWRSEL, is set to 10 binary.

The following table shows the ADC electrical specifications for 1V≤VREFH<VDD_ADC_1P8.

Table 123. ADC electrical specifications (1V≤VREFH<VDD_ADC_1P8)

Symbol

V_ADIN

Description

Min

Typ¹

Max

Unit

Notes

Input Voltage

VREFL

—

4.5

500

—

VREFH

—

C_ADIN

R_ADIN

R_AS

Input capacitance

Input Resistance

—

Analog Source Resistance

ADC Conversion Clock Frequency

Sample cycles

—

kΩ

f_ADCK

—

MHz

—

C_sample

C_compare

C_conversion

DNL

3.5

—

131.5

—

Fixed compare cycles

Conversion cycles

17.5

cycles

LSB

—

C_{conversion =}C_{sample +}C_compare

—

Differential Non-Linearity

Integral Non-Linearity

—

± 0.6

± 0.9

-0.5 to +1.1

±1.1

INL

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Table 123. ADC electrical specifications (1V≤VREFH<VDD_ADC_1P8) (continued)

Symbol

ENOB

Description

Effective Number of Bits

Min

Typ¹

Max

Unit

Notes

5,6,7

—

9.5

—

9.7

10.1

—

Bits

Avg = 1

Avg = 2

9.9

Avg = 16

10.8

SINAD

E_G

Signal to Noise plus Distortion

Gain error

SINAD=6.02 x ENOB + 1.76

—

0.29

0.01

—

%FSV

μA

E_O

Offset error

—

I_VDDA18

I_in,ext,leak

E_IL

Supply Current

External Channel Leakage Current

Input leakage error

480

500

—

RAS * I_in

Typical values assume VDD_ANA_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for

reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production.

This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS

(analog source capacitance) time constant should be kept to < 1 ns.

See Figure 61.

ADC conversion clock at max frequency and using linear histogram.

Input data used for test was 1 kHz sine wave.

Measured at VREFH = 1 V and pwrsel = 2.

ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling

may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling

becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content.

Error measured at fullscale at 1.0 V.

Error measured at zero scale at 0 V.

¹⁰Power Configuration Select, PWRSEL, is set to 10 binary.

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The following figure shows a plot of the ADC sample time versus R .

Figure 61. Sample time vs. R

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Boot mode configuration

5 Boot mode configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot mode configuration inputs

The following table lists boot option dedicated inputs. These inputs are sampled at reset and can be used

to override fuse values, depending on the value of FORCE_BOOT_FROM_FUSE. After this fuse is

blown, the Boot mode inputs are ignored by ROM; ROM receives 'boot mode' from the

BT_MODE_FUSES fuse. The boot option inputs are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared,

which is the case for an unblown fuse). For detailed boot mode options configured by the Boot mode pins,

see the “System Boot, Fusemap, and eFuse” chapter of the device reference manual.

Table 124. Boot options and associated inputs used for Boot

Interface

IP Instance

Allocated Pads During Boot

SCU_BOOT_MODE0

Comment

BOOT_MODE[0]

BOOT_MODE[1]

BOOT_MODE[2]

BOOT_MODE[3]

BOOT_MODE[4]

BOOT_MODE[5]

Input

Boot mode selection

SCU_BOOT_MODE1

SCU_BOOT_MODE2

SCU_BOOT_MODE3

SCU_BOOT_MODE4

SCU_BOOT_MODE5

5.2

Boot devices interfaces allocation

The following table lists the interfaces that can be used by the boot process in accordance with the

specific Boot mode configuration. The table also describes the interface’s specific modes and IOMUXC

allocation, which are configured during boot when appropriate.

Table 125. Interface allocation during boot

Interface

MMC

IP Instance

Allocated Pads During Boot

Comment

USDHC-0

EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0, 4 or 8 bit

EMMC0_DATA1, EMMC0_DATA2,

EMMC0_DATA3, EMMC0_DATA4,

EMMC0_DATA5, EMMC0_DATA6,

EMMC0_DATA7, EMMC0_RESET_B

SD/MMC

USDHC-1

USDHC1_CLK, USDHC1_CMD,

4 or 8 bit

USDHC1_DATA0, USDHC1_DATA1,

USDHC1_DATA2, USDHC1_DATA3,

USDHC1_DATA4, USDHC1_DATA5,

USDHC1_DATA6, USDHC1_DATA7,

USDHC1_VSELECT, USDHC1_RESET_B

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

115

Boot mode configuration

Table 125. Interface allocation during boot (continued)

Allocated Pads During Boot

Interface

IP Instance

Comment

USDHC-2

USDHC2_CLK, USDHC2_CMD,

USDHC2_DATA0, USDHC2_DATA1,

USDHC2_DATA2, USDHC2_DATA3,

USDHC2_RESET_B, USDHC2_VSELECT,

USDHC2_CD_B

4 bit

QSPI

QSPI0

QSPI0A_DATA0, QSPI0A_DATA1,

QSPI0A_DATA2, QSPI0A_DATA3,

QSPI0A_DQS, QSPI0A_SS0_B,

QSPI0A_SS1_B, QSPI0A_SCLK,

QSPI0B_SCLK, QSPI0B_DATA0,

QSPI0B_DATA1, QSPI0B_DATA2,

QSPI0B_DATA3, QSPI0B_DQS,

QSPI0B_SS0_B, QSPI0B_SS1_B

4, dual-4, or 8 bit

During boot, QSPI0B can only be used in

combination with QSPI0A, i.e. booting with

4-bit QSPI0B is not supported.

NAND

GPMI

EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0, 8 bit

EMMC0_DATA1, EMMC0_DATA2,

EMMC0_DATA3, EMMC0_DATA4,

EMMC0_DATA5, EMMC0_DATA6,

EMMC0_DATA7, EMMC0_STROBE,

EMMC0_RESET_B,, USDHC1_DATA0,

USDHC1_DATA1

Boot from CS0 only, but will drive CS1to high

when booting if specified in fuse, this is for

Multi-CS NAND chip.

• Single-ended DQS—use EMMC0_CMD

• Single-ended RE—use USDHC1_DATA5

• Differential DQS—

USDHC1_DATA2, USDHC1_DATA3,

USDHC1_DATA4, USDHC1_DATA5

USDHC1_DATA6, USDHC1_DATA7

USDHC1_STROBE

• _N use USDHC1_DATA2

• _P use USDHC1_DATA3

• Differential RE—

• _N use USDHC1_DATA0

• _P use USDHC1_DATA1

USB

USB-OTG

PHY

USB_OTG1_VBUS, USB_OTG1_DP,

USB_OTG1_DN, USB_OTG2_VBUS,

USB_OTG2_DP, USB_OTG2_DN

—

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

116

Package information and contact assignments

6 Package information and contact assignments

This section contains package information and contact assignments for the following package(s):

•

FCPBGA, 29 x 29 mm, 0.75 mm pitch

6.1

FCPBGA, 29 x 29 mm, 0.75 mm pitch

This section includes the following information for the 29 x 29 mm, 0.75 mm pitch package:

•

Mechanical package drawing

Ball map

Contact assignments

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

117

Package information and contact assignments

6.1.1

29 x 29 mm package case outline

The following figure shows the top, bottom, and side views of the 29 × 29 mm package.

Figure 62. 29 x 29 mm Package Top, Bottom, and Side Views

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

118

NXP Semiconductors

Package information and contact assignments

The notes in the following figure pertain to the preceding figure., “29 x 29 mm Package Top, Bottom, and

Side Views.”

Figure 63. Notes on 29 x 29 mm Package Top, Bottom, and Side Views

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

119

Package information and contact assignments

6.1.2

29 x 29 mm, 0.75 mm pitch ball map

The following page shows the 29 x 29 mm, 0.75 mm pitch ball map.

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

120

NXP Semiconductors

29 x 29 mm, 0.75 pitch ballmap

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ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢞꢌꢜꢏꢉꢊꢍꢒ

ꢊꢗꢊꢀ

ꢞꢌꢜꢏꢉꢊꢍꢌ

ꢌꢀꢍꢘ

ꢞꢌꢜꢏꢉꢘꢍꢌ

ꢔꢙꢛ

ꢞꢌꢜꢏꢉꢘꢍꢒ

ꢊꢗꢊꢂ

ꢞꢌꢜꢏꢉꢘꢍꢌ

ꢌꢉꢍꢘ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢑꢌꢘꢍꢠꢗꢡ

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ꢐ

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ꢑꢌꢒꢓꢔꢀꢍ

ꢒꢊꢗꢊꢀ

ꢑꢌꢒꢓꢔꢀꢍ

ꢒꢊꢗꢊꢂ

ꢑꢌꢒꢓꢔꢀꢍ

ꢒꢊꢗꢊꢅ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢑꢌꢒꢓꢔꢁꢍ

ꢔꢙꢛ

ꢋꢌꢌꢍꢎꢊꢏ

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ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢚ

ꢜꢔꢏꢖꢍꢔꢗꢕ

ꢙꢀꢍꢜꢖꢕꢌꢗ

ꢍꢘ

ꢒꢒꢕꢍꢔꢓꢀ

ꢍꢒꢞꢉꢄ

ꢒꢒꢕꢍꢔꢓꢀ

ꢍꢒꢞꢉꢅ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢚꢙꢖꢟꢔꢊꢐ

ꢀꢍꢗꢟ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢞꢌꢜꢏꢀꢊꢍꢌ

ꢌꢀꢍꢘ

ꢞꢌꢜꢏꢉꢊꢍꢒ

ꢊꢗꢊꢉ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢞꢌꢜꢏꢉꢊꢍꢒ

ꢞꢌ

ꢞꢌꢜꢏꢉꢘꢍꢒ

ꢊꢗꢊꢁ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

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ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢖꢎꢎꢔꢉꢍꢒ

ꢊꢗꢊꢉ

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ꢊꢗꢊꢁ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢖꢎꢎꢔꢉꢍꢒ

ꢊꢗꢊꢆ

ꢖꢎꢎꢔꢉꢍꢌ

ꢗꢕꢠꢘꢖ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢑꢌꢒꢓꢔꢀꢍ

ꢔꢎꢒ

ꢑꢌꢒꢓꢔꢀꢍ

ꢒꢊꢗꢊꢄ

ꢑꢌꢒꢓꢔꢁꢍ

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ꢖꢐꢖꢗꢀꢍꢕꢡ

ꢎꢏꢏꢍꢗꢟꢒꢁ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢞꢉꢅ

ꢒꢒꢕꢍꢔꢓꢉ

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ꢒꢒꢕꢍꢔꢓꢀ

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ꢞꢌꢜꢏꢉꢊꢍꢒ

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ꢞꢌꢜꢏꢉꢘꢍꢌ

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ꢒꢒꢕꢍꢔꢓꢉ

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ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢞꢉꢇ

ꢒꢒꢕꢍꢔꢓꢉ

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ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢞꢌꢉꢍꢐ

ꢙ

ꢜꢔꢏꢖꢍꢌꢊꢗ

ꢊꢉꢍꢜꢓꢣꢍ

ꢜꢙꢙꢍꢕꢖꢚꢍ

ꢕꢖꢗꢑꢕꢐ

ꢋꢒꢒꢍꢑꢌꢘ

ꢍꢌꢌꢂꢍꢙꢒ

ꢠꢍꢀꢜꢉꢍꢔ

ꢊꢜ

ꢋꢒꢒꢍꢎꢙꢘ

ꢍꢒꢏꢡꢍꢀꢜꢇ

ꢍꢂꢜꢂ

ꢋꢒꢒꢍꢑꢌꢘ

ꢍꢌꢌꢂꢍꢗꢔꢍ

ꢂꢜꢂ

ꢋꢒꢒꢍꢞꢌꢜꢏ

ꢀꢊꢍꢀꢜꢇꢍꢂ

ꢜꢂ

ꢋꢒꢒꢍꢜꢔꢏꢖ

ꢀꢍꢜꢙꢙꢍꢀꢜ

ꢇ

ꢋꢒꢒꢍꢜꢔꢏꢖ

ꢍꢌꢊꢗꢊꢉꢍ

ꢀꢜꢉ

ꢜꢔꢏꢖꢉꢍꢜꢓ

ꢣꢍꢜꢙꢙꢍꢕꢖ

ꢚꢍꢕꢖꢗꢑꢕꢐ

ꢋꢒꢒꢍꢑꢌꢘ

ꢍꢠꢗꢡꢀꢍꢀꢜ

ꢉ

ꢋꢒꢒꢍꢑꢌꢘ

ꢍꢠꢗꢡꢁꢍꢂꢜ

ꢂ

ꢋꢒꢒꢍꢑꢌꢒ

ꢓꢔꢀꢍꢀꢜꢇꢍ

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ꢋꢒꢒꢍꢑꢌꢒ

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ꢜꢂ

ꢋꢌꢌꢍꢎꢊꢏ

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ꢋꢒꢒꢍꢜꢔꢏꢖ

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ꢋꢌꢌꢍꢎꢊꢏ

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ꢎ

ꢋꢒꢒꢍꢖꢐꢖ

ꢗꢍꢎꢒꢏꢠꢍꢀ

ꢜꢇꢍꢁꢜꢄꢍꢂ

ꢜꢂ

ꢋꢒꢒꢍꢚꢙꢖ

ꢟꢔꢊꢐꢍꢀꢜ

ꢇꢍꢂꢜꢂ

ꢋꢒꢒꢍꢞꢌꢜꢏ

ꢉꢍꢀꢜꢇꢍꢂꢜ

ꢂ

ꢋꢒꢒꢍꢜꢔꢏꢖ

ꢍꢌꢊꢗꢊꢉꢍ

ꢜꢙꢙꢍꢀꢜꢇ

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ꢋꢒꢒꢍꢑꢌꢘ

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ꢂ

ꢋꢒꢒꢍꢖꢎꢎ

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ꢒꢒꢕꢍꢔꢓꢀ

ꢍꢒꢔꢚꢉꢈ

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ꢍꢒꢞꢀꢈ

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ꢎꢃꢀꢍꢡꢜꢏꢠ

ꢉꢍꢉꢉ

ꢌꢏꢎꢉꢍꢡꢜꢏ

ꢠꢉꢍꢉꢉ

ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢞꢁꢈ

ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢎꢂ

ꢊꢒꢔꢍꢏꢐꢆ

ꢊꢒꢔꢍꢏꢐꢁ

ꢊꢒꢔꢍꢏꢐꢉ

ꢋꢒꢒꢍꢊꢄꢂ

ꢋꢒꢒꢍꢊꢆꢁ

ꢌꢏꢎꢉꢍꢕꢌꢗ

ꢋꢒꢒꢍꢖꢌꢊꢏ

ꢉꢍꢎꢔꢙꢛꢍꢀ

ꢜꢇꢍꢂꢜꢂ

ꢋꢒꢒꢍꢌꢔꢑ

ꢍꢊꢐꢊꢍꢀꢜ

ꢇ

ꢒꢒꢕꢍꢔꢓꢀ

ꢍꢒꢞꢁꢇ

ꢒꢒꢕꢍꢔꢓꢀ

ꢍꢒꢞꢂꢀ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

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ꢐ

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ꢐ

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ꢐ

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ꢐ

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ꢐ

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ꢐ

ꢑꢊꢕꢗꢀꢍꢕ

ꢗꢌꢍꢘ

ꢎꢃꢀꢍꢏꢁꢔꢉ

ꢍꢌꢔꢙ

ꢎꢃꢉꢍꢡꢜꢏꢠ

ꢉꢍꢉꢉ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢞꢂꢀ

ꢒꢒꢕꢍꢔꢓꢉ

ꢍꢒꢞꢁꢇ

ꢊꢒꢔꢍꢏꢐꢄ

ꢋꢒꢒꢍꢊꢄꢂ

ꢋꢒꢒꢍꢊꢆꢁ

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ꢐ

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ꢖꢌꢊꢏꢀꢍꢗꢟ

ꢄꢍꢕꢟꢉ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

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ꢐ

ꢋꢒꢒꢍꢌꢐꢋ

ꢌꢍꢃꢜꢁ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

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ꢟ

ꢋꢌꢌꢍꢎꢊꢏ

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ꢝꢖꢕꢍꢖꢐ

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ꢐ

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ꢋꢒꢒꢍꢊꢄꢂ

ꢋꢒꢒꢍꢊꢆꢁ

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ꢜꢂ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢕꢟꢉꢍꢙꢒ

ꢠꢉꢍꢀꢜꢉꢍꢔ

ꢊꢜ

ꢋꢒꢒꢍꢓꢒꢎꢏ

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ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

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ꢇ

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ꢌ

ꢖꢌꢊꢏꢉꢍꢗꢟ

ꢄꢍꢕꢟꢉ

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ꢖꢌꢊꢏꢀꢍꢗꢟ

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ꢐ

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ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

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ꢋꢒꢒꢍꢎꢊꢏ

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ꢐ

ꢌꢔꢑꢍꢡꢜꢏꢠ

ꢉꢍꢉꢉ

ꢑꢊꢕꢗꢉꢍꢕ

ꢗꢌꢍꢘ

ꢎꢃꢀꢍꢡꢜꢏꢠ

ꢉꢍꢉꢀ

ꢎꢃꢀꢍꢏꢁꢔꢉ

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ꢎꢃꢉꢍꢏꢁꢔꢉ

ꢍꢌꢒꢊ

ꢎꢃꢉꢍꢡꢜꢏꢠ

ꢉꢍꢉꢀ

ꢌꢊꢏꢀꢍꢗꢟꢒ

ꢌꢜꢏꢁꢍꢔꢌꢉ

ꢌꢜꢏꢁꢍꢌꢒꢠ

ꢌꢜꢏꢉꢍꢔꢌꢉ

ꢌꢊꢏꢀꢍꢗꢟꢔ

ꢌꢜꢏꢁꢍꢌꢔꢛ

ꢌꢜꢏꢉꢍꢌꢒꢏ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢕꢟꢉꢍꢋꢓ

ꢍꢕꢟꢍꢂꢜꢂ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢔꢌꢏꢍꢒꢏꢡꢍꢀ

ꢜꢇ

ꢋꢒꢒꢍꢙꢋꢒ

ꢌꢍꢒꢏꢡꢍꢀꢜ

ꢇꢍꢂꢜꢂ

ꢌꢊꢏꢀꢍꢗꢟꢚ

ꢌ

ꢖꢌꢊꢏꢉꢍꢗꢟ

ꢃꢍꢕꢟꢀ

ꢖꢌꢊꢏꢀꢍꢗꢟ

ꢂꢍꢕꢟꢁ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢗꢟꢉꢍꢀꢜꢉ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢕꢟꢉꢍꢀꢜꢇ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢔꢌꢏꢉꢍꢀꢜꢇ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢔꢌꢏꢉꢍꢀꢜꢉ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢒꢌꢏꢀꢍꢀꢜꢉ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢒꢌꢏꢀꢍꢀꢜꢇ

ꢋꢒꢒꢍꢙꢋꢒ

ꢌꢉꢍꢀꢜꢇ

ꢋꢒꢒꢍꢙꢋꢒ

ꢌꢉꢍꢀꢜꢉ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢌꢔꢑꢍꢡꢜꢏꢠ

ꢉꢍꢉꢀ

ꢑꢊꢕꢗꢀꢍꢔ

ꢗꢌꢍꢘ

ꢑꢊꢕꢗꢉꢍꢗ

ꢟ

ꢑꢊꢕꢗꢉꢍꢕ

ꢟ

ꢡꢜꢗꢉꢍꢔꢊ

ꢜꢗꢑꢕꢖ

ꢌꢊꢏꢀꢍꢕꢟꢒ

ꢌꢜꢏꢁꢍꢌꢒꢏ

ꢌꢜꢏꢉꢍꢌꢔꢛ

ꢌꢊꢏꢀꢍꢕꢟꢔ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢗꢟꢉꢍꢙꢒꢠ

ꢍꢀꢜꢉꢍꢔꢊꢜ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢗꢟꢉꢍꢒꢏꢡ

ꢍꢂꢜꢂ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢒꢌꢏꢀꢍꢜꢙꢙꢍ

ꢀꢜꢉ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢒꢌꢏꢉꢍꢜꢙꢙꢍ

ꢀꢜꢉ

ꢋꢒꢒꢍꢌꢐꢋ

ꢌꢍꢙꢒꢠꢍꢀꢜ

ꢇꢍꢔꢊꢜ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢖꢌꢊꢏꢉꢍꢚꢌ

ꢕ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢒꢒꢍꢓꢒꢎꢏ

ꢍꢗꢟꢉꢍꢀꢜꢇ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢔꢌꢏꢀꢍꢀꢜꢉ

ꢋꢒꢒꢍꢎꢏꢜꢏꢍ

ꢒꢌꢏꢉꢍꢀꢜꢇ

ꢋꢒꢒꢍꢙꢋꢒ

ꢌꢀꢍꢀꢜꢇ

ꢋꢒꢒꢍꢙꢋꢒ

ꢌꢀꢍꢀꢜꢉ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢌꢔꢑꢍꢡꢜꢏꢠ

ꢉꢍꢉꢁ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢑꢊꢕꢗꢉꢍꢔ

ꢗꢌꢍꢘ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢡꢜꢗꢉꢍꢔꢠ

ꢎꢜꢊꢕꢖ

ꢖꢌꢊꢏꢉꢍꢌꢔ

ꢛꢗ

ꢖꢌꢊꢏꢀꢍꢌꢔ

ꢛꢗ

ꢖꢌꢊꢏꢀꢍꢗꢟ

ꢃꢍꢕꢟꢀ

ꢌꢔꢑꢍꢘꢠꢠ

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ꢌꢔꢑꢍꢡꢜꢏꢠ

ꢉꢍꢉꢄ

ꢜꢎꢏꢔꢍꢏꢁꢔꢍ

ꢌꢔꢙ

ꢑꢊꢕꢗꢀꢍꢗ

ꢟ

ꢡꢜꢗꢀꢍꢔꢊ

ꢜꢗꢑꢕꢖ

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ꢌꢜꢏꢉꢍꢌꢒꢠ

ꢡꢜꢗꢉꢍꢔꢙꢛ

ꢌꢔꢑꢍꢜꢎꢏꢔ

ꢍꢌꢗꢊꢐꢒꢘ

ꢣ

ꢖꢌꢊꢏꢉꢍꢗꢟ

ꢀ

ꢖꢌꢊꢏꢉꢍꢗꢟ

ꢉ

ꢖꢌꢊꢏꢀꢍꢗꢟ

ꢀ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

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ꢋꢌꢌꢍꢎꢊꢏ

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ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢢꢗꢊꢡꢍꢗꢎ

ꢌ

ꢡꢜꢗꢀꢍꢔꢠ

ꢎꢜꢊꢕꢖ

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ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

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ꢖꢌꢊꢏꢉꢍꢌꢔ

ꢛꢕ

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ꢐ

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ꢎꢔꢙꢛꢍꢏꢐꢉ

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ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢡꢜꢏꢠꢉꢍꢉꢀ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢡꢜꢏꢠꢉꢍꢉꢉ

ꢙꢋꢒꢌꢀꢍꢏꢁ

ꢔꢀꢍꢌꢔꢙ

ꢙꢋꢒꢌꢀꢍꢡ

ꢜꢏꢠꢉꢉ

ꢙꢋꢒꢌꢉꢍꢏꢁ

ꢔꢉꢍꢌꢒꢊ

ꢙꢋꢒꢌꢉꢍꢏꢁ

ꢔꢉꢍꢌꢔꢙ

ꢙꢋꢒꢌꢉꢍꢡ

ꢜꢏꢠꢉꢀ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢢꢗꢊꢡꢍꢗꢒ

ꢠ

ꢌꢜꢏꢂꢍꢔꢌꢀ

ꢗꢍꢠꢑꢗꢀꢍꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢒꢔꢍꢌꢒ

ꢊ

ꢊꢐꢊꢍꢗꢖꢌ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢖꢌꢊꢏꢀꢍꢚꢌ

ꢕ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢏꢁꢔꢉꢍꢌꢒꢊ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢂꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢀꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢔꢙꢛꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢉꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢁꢍꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢏꢁꢔꢉꢍꢌꢔꢙ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢏꢁꢔꢉꢍꢌꢔꢙ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢏꢁꢔꢉꢍꢌꢒꢊ

ꢙꢋꢒꢌꢀꢍꢏꢁ

ꢔꢉꢍꢌꢒꢊ

ꢙꢋꢒꢌꢉꢍꢏꢁ

ꢔꢀꢍꢌꢒꢊ

ꢙꢋꢒꢌꢉꢍꢏꢁ

ꢔꢀꢍꢌꢔꢙ

ꢙꢋꢒꢌꢉꢍꢡ

ꢜꢏꢠꢉꢉ

ꢌꢐꢋꢌꢍꢗꢊ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢠꢐꢍꢠꢚꢚꢍ

ꢘꢑꢗꢗꢠꢐ

ꢢꢗꢊꢡꢍꢗꢕ

ꢌꢗꢍꢘ

ꢌꢜꢏꢂꢍꢌꢒꢏ

ꢜꢠꢕꢍꢘ

ꢢꢗꢊꢡꢍꢗꢒꢏ

ꢗꢍꢠꢑꢗꢀꢍꢜ

ꢎꢜꢖꢕꢍꢏꢐꢉ

ꢎꢜꢖꢕꢍꢏꢐꢀ

ꢜꢎꢏꢔꢍꢖꢊꢕ

ꢙꢣꢍꢝꢊꢕꢐ

ꢏꢐꢡ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢖꢌꢊꢏꢀꢍꢗꢟ

ꢉ

ꢖꢌꢊꢏꢀꢍꢚꢌ

ꢗ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢓꢜꢒ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢂꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢀꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢔꢙꢛꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢉꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢒꢊꢗꢊꢁꢍꢜ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢌꢔꢑꢍꢡꢜꢏꢠ

ꢉꢍꢉꢆ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢌꢜꢏꢂꢍꢌꢒꢠ

ꢌꢜꢏꢂꢍꢌꢔꢛ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢒꢔꢍꢌꢔ

ꢙ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢊꢑꢟꢍꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢖꢌꢊꢏꢉꢍꢚꢌ

ꢗ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢏꢁꢔꢉꢍꢌꢒꢊ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢂꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢀꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢔꢙꢛꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢉꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢁꢍꢜ

ꢙꢋꢒꢌꢉꢍꢔ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢌꢔꢑꢍꢡꢜꢏꢠ

ꢉꢍꢉꢅ

ꢜꢎꢏꢔꢍꢏꢁꢔꢍ

ꢌꢒꢊ

ꢊꢐꢊꢍꢗꢖꢌ

ꢌꢜꢏꢂꢍꢔꢌꢉ

ꢓꢀꢍꢗꢟꢂꢍꢐ

ꢓꢀꢍꢗꢟꢁꢍꢐ

ꢓꢀꢍꢗꢟꢀꢍꢐ

ꢓꢀꢍꢗꢟꢉꢍꢐ

ꢓꢀꢍꢔꢙꢛꢍꢐ

ꢗꢍꢠꢑꢗꢉꢍꢜ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢒꢔꢍꢌꢔ

ꢙ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢊꢑꢟꢍꢜ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢓꢜꢒ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢂꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢀꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢔꢙꢛꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢉꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢁꢍꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢏꢁꢔꢉꢍꢌꢔꢙ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢂꢍꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢀꢍꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢔꢙꢛꢍꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢉꢍꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢒꢊꢗꢊꢁꢍꢐ

ꢙꢋꢒꢌꢀꢍꢡ

ꢜꢏꢠꢉꢀ

ꢙꢋꢒꢌꢉꢍꢔ

ꢜꢎꢏꢔꢍꢏꢐꢗꢍ

ꢘ

ꢊꢐꢊꢍꢗꢖꢌ

ꢓꢀꢍꢗꢟꢂꢍꢜ

ꢓꢀꢍꢗꢟꢁꢍꢜ

ꢓꢀꢍꢗꢟꢀꢍꢜ

ꢓꢀꢍꢗꢟꢉꢍꢜ

ꢓꢀꢍꢔꢙꢛꢍꢜ

ꢗꢍꢠꢑꢗꢉꢍꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢎꢔꢙꢛꢍꢠꢑ

ꢗ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢔꢖꢔ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢕꢖꢟꢗ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢔꢖꢔ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢕꢖꢟꢗ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢂꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢀꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢔꢙꢛꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢉꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢀꢍ

ꢒꢊꢗꢊꢁꢍꢜ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢌꢔꢑꢍꢘꢠꢠ

ꢗꢍꢎꢠꢒꢖꢁ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢔꢙꢛꢍꢖꢒꢜ

ꢂꢍꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢎꢏꢜꢏꢍꢒꢌꢏꢀꢍ

ꢡꢜꢏꢠꢉꢍꢉꢀ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢒꢊꢗꢊꢀꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢒꢊꢗꢊꢉꢍꢜ

ꢙꢋꢒꢌꢀꢍꢔ

ꢙꢋꢒꢌꢉꢍꢔ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢋꢌꢌꢍꢌꢔꢑ

ꢍꢟꢗꢊꢙ

ꢌꢔꢑꢍꢘꢠꢠ

ꢗꢍꢎꢠꢒꢖꢄ

ꢓꢀꢍꢗꢟꢂꢍꢐ

ꢓꢀꢍꢗꢟꢀꢍꢐ

ꢓꢀꢍꢔꢙꢛꢍꢐ

ꢓꢉꢍꢔꢙꢛꢍꢐ

ꢓꢉꢍꢗꢟꢀꢍꢐ

ꢓꢉꢍꢗꢟꢂꢍꢐ

ꢓꢉꢍꢗꢟꢉꢍꢐ

ꢓꢉꢍꢗꢟꢁꢍꢐ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢔꢙꢛꢍꢖꢒꢜ

ꢂꢍꢜ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢊꢗꢊꢉꢍ

ꢖꢒꢜꢁꢍꢜ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢊꢗꢊꢀꢍ

ꢖꢒꢜꢀꢍꢜ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢊꢗꢊꢁꢍ

ꢖꢒꢜꢉꢍꢜ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢊꢗꢊꢉꢍ

ꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢊꢗꢊꢀꢍ

ꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢊꢗꢊꢁꢍ

ꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢔꢙꢛꢍꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢊꢕꢔꢍꢐ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢡꢜꢏꢠꢉꢍꢉꢉ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢒꢊꢗꢊꢂꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢔꢙꢛꢍꢜ

ꢎꢏꢜꢏꢍꢒꢌꢏꢉꢍ

ꢒꢊꢗꢊꢁꢍꢜ

ꢙꢋꢒꢌꢀꢍꢔ

ꢙꢋꢒꢌꢀꢍꢏꢁ

ꢔꢉꢍꢌꢔꢙ

ꢙꢋꢒꢌꢀꢍꢔ

ꢙꢋꢒꢌꢉꢍꢔ

ꢕꢗꢔꢍꢟꢗꢊ

ꢙꢠ

ꢜꢎꢏꢔꢍꢠꢐꢍ

ꢕꢖꢞ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢟꢗꢊꢙꢠ

ꢓꢀꢍꢗꢟꢁꢍꢐ

ꢓꢀꢍꢗꢟꢉꢍꢐ

ꢓꢉꢍꢗꢟꢉꢍꢐ

ꢓꢉꢍꢗꢟꢁꢍꢐ

ꢓꢉꢍꢔꢙꢛꢍꢐ

ꢓꢉꢍꢗꢟꢀꢍꢐ

ꢓꢉꢍꢗꢟꢂꢍꢐ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢊꢗꢊꢉꢍ

ꢖꢒꢜꢁꢍꢐ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢊꢗꢊꢀꢍ

ꢖꢒꢜꢀꢍꢐ

ꢓꢒꢎꢏꢍꢗꢟꢉ

ꢍꢒꢊꢗꢊꢁꢍ

ꢖꢒꢜꢉꢍꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢊꢗꢊꢉꢍ

ꢜ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢊꢗꢊꢀꢍ

ꢜ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢒꢊꢗꢊꢁꢍ

ꢜ

ꢋꢌꢌꢍꢎꢊꢏ

ꢐ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢔꢙꢛꢍꢜ

ꢓꢒꢎꢏꢍꢕꢟꢉ

ꢍꢊꢕꢔꢍꢜ

ꢎꢏꢜꢏꢍꢔꢌꢏꢉꢍ

ꢡꢜꢏꢠꢉꢍꢉꢀ

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ꢓꢉꢍꢗꢟꢂꢍꢜ

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

ꢀ21

Package information and contact assignments

6.1.3

29 x 29 mm power supplies and functional contact assignments

The following table shows power supplies contact assignments for the 29 × 29 mm package.

Table 126. 29 x 29 mm power supplies contact assignments

Power rail

Ball reference

VDD_A53

VDD_A72

AM22, AM26, AN23, AP24, AR21, AR25, AT22

AL29, AL33, AM30, AM34, AN27, AN31, AN35, AP28, AP32, AR29, AR33, AT34

VDD_ADC_1P8

AL15

VDD_ADC_DIG_1P8

AK16

VDD_ANA0_1P8

U29, U31

VDD_ANA1_1P8

U25

VDD_ANA2_1P8

AJ35

VDD_ANA3_1P8

AK20

VDD_CP_1P8

AN37

VDD_DDR_CH0_VDDA_PLL_1P8

VDD_DDR_CH0_VDDQ

VDD_DDR_CH0_VDDQ_CKE

VDD_DDR_CH1_VDDA_PLL_1P8

VDD_DDR_CH1_VDDQ

VDD_DDR_CH1_VDDQ_CKE

VDD_EMMC0_1P8_3P3

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_3P3

VDD_ENET1_1P8_2P5_3P3

VDD_ESAI0_MCLK_1P8_3P3

VDD_ESAI1_SPDIF_SPI_1P8_3P3

VDD_FLEXCAN_1P8_3P3

VDD_GPU0

AE43

AA39, AE39, AF38, AG39, AH38, AJ39, U39, V38, W39, Y38

AB38, AC39, AD38

AE11

AA15, AE15, AF16, AG15, AH16, AJ15, U15, V16, W15, Y16

AB16, AC15, AD16

N35

N17

M40, N39

T38

AP16, AR15

AU15

N15

AA19, AB20, AC21, AD18, AD22, AE19, V20, W21, Y18, Y22

VDD_GPU1

AA35, AB32, AB36, AC33, AD34, AE35, U35, V36, W33, Y34

VDD_HDMI_RX0_LDO0_1P0_CAP¹

VDD_HDMI_RX0_LDO1_1P0_CAP¹

VDD_HDMI_RX0_VH_RX_3P3¹

VDD_HDMI_TX0_1P0

AU19

AU21

AV20

AV16

AW17

VDD_HDMI_TX0_1P8

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

122

Package information and contact assignments

Table 126. 29 x 29 mm power supplies contact assignments (continued)

Power rail

Ball reference

VDD_HDMI_TX0_DIG_3P3

VDD_HDMI_TX0_LDO_1P0_CAP

VDD_LVDS_DIG_1P8_3P3

VDD_LVDS0_1P0

AW21

AW15

AV32

AV36

VDD_LVDS0_1P8

AV34

VDD_LVDS1_1P0

AW35

VDD_LVDS1_1P8

AW33

VDD_M1P8_CAP

AP42

VDD_M4_GPT_UART_1P8_3P3

VDD_MAIN

AL39, AM38

AA23, AA27, AA31, AB24, AB28, AC25, AC29, AD26, AD30, AE23, AE27, AE31, AF20,

AF24, AF28, AF32, AF36, AG21, AG33, AH18, AH34, AJ19, AJ31, AK32, AK36, AL17,

AL21, AL25, AL37, AM18, AN19, AP20, AP36, AR17, AR37, AT18, AT26, AT30, AU35,

T34, U19, U23, V24, V32, W25, W29, Y26, Y30

VDD_MEMC

AC17, AC37, AG17, AG25, AG29, AG37, AH22, AH26, AH30, AJ23, AJ27, AK24, AK28,

W17, W37

VDD_MIPI_CSI_DIG_1P8

VDD_MIPI_CSI0_1P0

VDD_MIPI_CSI0_1P8

VDD_MIPI_CSI1_1P0

VDD_MIPI_CSI1_1P8

VDD_MIPI_DSI_DIG_1P8_3P3

VDD_MIPI_DSI0_1P0

VDD_MIPI_DSI0_1P8

VDD_MIPI_DSI0_PLL_1P0

VDD_MIPI_DSI1_1P0

VDD_MIPI_DSI1_1P8

VDD_MIPI_DSI1_PLL_1P0

VDD_MLB_1P8²

AV22

AV26

AV24

AW25

AU23

AU27

AU29

AW31

AW29

AV28

AV30

AW27

T30

VDD_MLB_DIG_1P8_3P3³

VDD_PCIE_DIG_1P8_3P3

VDD_PCIE_IOB_1P8

M14

T22

T26

VDD_PCIE_LDO_1P0_CAP

VDD_PCIE_LDO_1P8

VDD_PCIE_SATA0_1P0¹

N29

U27

M24

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

123

Package information and contact assignments

Table 126. 29 x 29 mm power supplies contact assignments (continued)

Power rail

Ball reference

VDD_PCIE_SATA0_PLL_1P8¹

VDD_PCIE0_1P0

N21

M26

VDD_PCIE0_PLL_1P8

VDD_PCIE1_1P0

N27

N25

VDD_PCIE1_PLL_1P8

VDD_QSPI0_1P8_3P3

VDD_QSPI1A_1P8_3P3

VDD_SCU_1P8

M22

N19

M18

AN39, AP38

AR39

AU39

AK42

AT38

AW39

AM16, AN15

V26

VDD_SCU_ANA_1P8

VDD_SCU_XTAL_1P8

VDD_SIM0_1P8_3P3

VDD_SNVS_4P2

VDD_SNVS_LDO_1P8_CAP

VDD_SPI_SAI_1P8_3P3

VDD_USB_HSIC0_1P2

VDD_USB_HSIC0_1P8

VDD_USB_OTG1_1P0

VDD_USB_OTG1_3P3

VDD_USB_OTG2_1P0

VDD_USB_OTG2_3P3

VDD_USB_SS3_LDO_1P0_CAP

VDD_USB_SS3_TC_3P3

VDD_USDHC_VSELECT_1P8_3P3

VDD_USDHC1_1P8_3P3

VDD_USDHC2_1P8_3P3

VREFH_ADC

V28

M32

N33

N31

M34

M30

M16

T18

M36, N37

M38

AL11

AM10

VREFL_ADC

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

124

Package information and contact assignments

Table 126. 29 x 29 mm power supplies contact assignments (continued)

Power rail

Ball reference

VSS_MAIN

A23, A3, A31, A51, AA1, AA11, AA13, AA17, AA21, AA25, AA29, AA3, AA33, AA37,

AA41, AA43, AA45, AA47, AA49, AA5, AA51, AA53, AA7, AA9, AB12, AB18, AB22,

AB26, AB30, AB34, AB42, AC13, AC19, AC23, AC27, AC31, AC35, AC41, AD10, AD12,

AD2, AD20, AD24, AD28, AD32, AD36, AD4, AD42, AD44, AD46, AD48, AD50, AD52,

AD6, AD8, AE13, AE17, AE21, AE25, AE29, AE33, AE37, AE41, AF12, AF18, AF22,

AF26, AF30, AF34, AF42, AG1, AG11, AG13, AG19, AG23, AG27, AG3, AG31, AG35,

AG41, AG43, AG45, AG47, AG49, AG5, AG51, AG53, AG7, AG9, AH12, AH20, AH24,

AH28, AH32, AH36, AH42, AJ13, AJ17, AJ21, AJ25, AJ29, AJ33, AJ37, AJ41, AK10,

AK12, AK18, AK2, AK22, AK26, AK30, AK34, AK38, AK4, AK44, AK46, AK48, AK50,

AK52, AK6, AK8, AL13, AL19, AL23, AL27, AL31, AL35, AL41, AM12, AM20, AM24,

AM28, AM32, AM36, AM42, AM46, AM8, AN1, AN13, AN17, AN21, AN25, AN29, AN3,

AN33, AN41, AN43, AN47, AN49, AN5, AN51, AN53, AN7, AP12, AP18, AP22, AP26,

AP30, AP34, AR11, AR19, AR23, AR27, AR31, AR35, AR49, AR5, AT12, AT16, AT2,

AT20, AT24, AT28, AT32, AT36, AT4, AT42, AT46, AT50, AT52, AT6, AT8, AU17, AU25,

AU31, AU33, AU37, AV12, AV38, AV42, AW11, AW19, AW23, AW3, AW37, AW43,

AW47, AW51, AW7, B12, B14, B18, B28, B36, B46, B6, BA13, BA15, BA17, BA19, BA21,

BA23, BA25, BA27, BA29, BA31, BA33, BA35, BA37, BA39, BA41, BA45, BB10, BB14,

BB16, BB18, BB2, BB20, BB22, BB24, BB26, BB28, BB30, BB32, BB34, BB36, BB38,

BB40, BB48, BB52, BB6, BC11, BC13, BC15, BC17, BC19, BC21, BC23, BC25, BC27,

BC29, BC31, BC33, BC35, BC37, BC39, BC41, BC43, BD14, BD16, BD18, BD20, BD22,

BD24, BD26, BD48, BD50, BE3, BE45, BE7, BE9, BF26, BF28, BF30, BF32, BF34,

BF36, BF38, BF4, BF40, BF42, BF44, BF52, BG11, BG13, BG15, BG17, BG19, BG21,

BG23, BG47, BG7, BH22, BH4, BJ25, BJ27, BJ29, BJ3, BJ31, BJ33, BJ35, BJ37, BJ39,

BJ41, BJ43, BJ45, BJ47, BJ49, BJ5, BJ51, BK10, BK12, BK14, BK16, BK18, BK20,

BK22, BK46, BK6, BK8, BL1, BL21, BL53, BM10, BM46, BN21, BN3, C1, C11, C15, C19,

C21, C23, C29, C31, C33, C41, C43, C49, C53, C9, D16, D18, D24, D26, D28, D34, D36,

D38, D40, D6, E19, E21, E47, E9, F12, F2, F24, F32, F36, F4, F44, F50, F52, G15, G21,

G23, G27, G33, G39, G49, G5, G9, J1, J13, J15, J17, J19, J21, J23, J25, J29, J3, J31,

J35, J37, J41, J47, J49, J5, J51, J53, J7, K12, K14, K16, K18, K20, K22, K24, K26, K28,

K30, K32, K34, K36, K38, K40, K42, K46, K8, L11, L13, L15, L17, L19, L21, L23, L25,

L27, L29, L31, L33, L35, L37, L39, L41, L43, M10, M2, M4, M44, M46, M48, M50, M52,

M6, M8, N13, N41, P12, P42, R1, R11, R15, R17, R19, R21, R23, R25, R27, R29, R3,

R31, R33, R35, R37, R39, R43, R45, R47, R49, R5, R51, R53, R7, R9, T12, T16, T20,

T24, T28, T32, T36, T42, U17, U21, U33, U37, V10, V12, V18, V2, V22, V30, V34, V4,

V42, V44, V46, V48, V50, V52, V6, V8, W19, W23, W27, W31, W35, Y12, Y20, Y24, Y28,

Y32, Y36, Y42

VSS_SCU_XTAL

BK48, BM48, BM50, BN51

HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected

HDMI-RX support will be enabled.

MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated,

per the Hardware Developer’s Guide power supplies of unused functions.

MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Table 8 if other I/O functions

are used, as determined by IOMUX selection. Alternately, terminate the MLB supply, per the Hardware Developer’s Guide power

supplies of unused functions.

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

125

Package information and contact assignments

The following table shows functional contact assignments for the 29 × 29 mm package.

Table 127. 29 × 29 mm functional contact assignments

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

AP10

AN11

AP8

AR9

AN9

AR7

AL9

AP6

BH52

BG53

BD2

BE1

H28

J27

ADC_IN0

ADC_IN1

VDD_ADC_3P3

GPIO

ALT0

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

ADC_IN4

ADC_IN5

ADC_IN6

ADC_IN7

ADC_IN2

ADC_IN3

ADC_IN4

ADC_IN5

ADC_IN6

ADC_IN7

ANA_TEST_OUT0_N

ANA_TEST_OUT0_P

ANA_TEST_OUT1_N

ANA_TEST_OUT1_P

EMMC0_CLK

VDD_SCU_ANA_1P8

VDD_EMMC0_1P8_3P3

ANA

NXP Internal Use Only

(Leave Unconnected)

FASTD ALT1

ALT0

NAND_READY_B

EMMC0_CMD

G29

H30

G31

H32

J33

EMMC0_DATA0

EMMC0_DATA1

EMMC0_DATA2

EMMC0_DATA3

EMMC0_DATA4

EMMC0_DATA5

EMMC0_DATA6

EMMC0_DATA7

EMMC0_RESET_B

EMMC0_STROBE

ENET0_MDC

EMMC0_DATA0

EMMC0_DATA1

EMMC0_DATA2

EMMC0_DATA3

EMMC0_DATA4

EMMC0_DATA5

EMMC0_DATA6

EMMC0_DATA7

LSIO.GPIO5.IO13

EMMC0_STROBE

LSIO.GPIO4.IO14

ENET0_MDIO

H34

H36

G35

H38

G37

GPIO

ALT3

FASTD ALT0

VDD_ENET_MDIO_1P8_3P3

VDD_ENET0_1P8_3P3

GPIO

ALT3

ALT0

ALT3

D10

B10

E43

B44

A47

ENET0_MDIO

ENET0_REFCLK_125M_25M

ENET0_RGMII_RX_CTL

ENET0_RGMII_RXC

ENET0_RGMII_RXD0

LSIO.GPIO4.IO15

ENET0_RGMII_RX_CTL

ENET0_RGMII_RXC

ENET0_RGMII_RXD0

FASTD ALT0

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

126

Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Default function

Ball

Ball Name

Power Domain

Type¹

Default

mode

State²

D44

C45

E45

E41

A41

A43

B42

A45

D42

A13

C13

A11

E49

B50

E51

C51

D52

E53

B48

D46

A49

C47

G47

D48

AW9

BG9

BB8

AY8

BA9

BA7

AU9

BC5

ENET0_RGMII_RXD1

ENET0_RGMII_RXD2

ENET0_RGMII_RXD3

ENET0_RGMII_TX_CTL

ENET0_RGMII_TXC

ENET0_RGMII_TXD0

ENET0_RGMII_TXD1

ENET0_RGMII_TXD2

ENET0_RGMII_TXD3

ENET1_MDC

VDD_ENET0_1P8_3P3

FASTD ALT0

ENET0_RGMII_RXD1

ENET0_RGMII_RXD2

ENET0_RGMII_RXD3

LSIO.GPIO5.IO31

LSIO.GPIO5.IO30

LSIO.GPIO6.IO00

LSIO.GPIO6.IO01

LSIO.GPIO6.IO02

LSIO.GPIO6.IO03

LSIO.GPIO4.IO18

ENET1_MDIO

ALT3

VDD_ENET_MDIO_1P8_3P3

VDD_ENET1_1P8_2P5_3P3

GPIO

ALT3

ALT0

ALT3

ENET1_MDIO

ENET1_REFCLK_125M_25M

ENET1_RGMII_RX_CTL

ENET1_RGMII_RXC

ENET1_RGMII_RXD0

ENET1_RGMII_RXD1

ENET1_RGMII_RXD2

ENET1_RGMII_RXD3

ENET1_RGMII_TX_CTL

ENET1_RGMII_TXC

ENET1_RGMII_TXD0

ENET1_RGMII_TXD1

ENET1_RGMII_TXD2

ENET1_RGMII_TXD3

ESAI0_FSR

LSIO.GPIO4.IO16

ENET1_RGMII_RX_CTL

ENET1_RGMII_RXC

ENET1_RGMII_RXD0

ENET1_RGMII_RXD1

ENET1_RGMII_RXD2

ENET1_RGMII_RXD3

LSIO.GPIO6.IO11

LSIO.GPIO6.IO10

LSIO.GPIO6.IO12

LSIO.GPIO6.IO13

LSIO.GPIO6.IO14

LSIO.GPIO6.IO15

ESAI0_FSR

FASTD ALT0

ALT3

VDD_ESAI0_MCLK_1P8_3P3

GPIO

ALT0

ESAI0_FST

ESAI0_SCKR

ESAI0_SCKT

ESAI0_TX0

ESAI0_TX1

ESAI0_TX2_RX3

ESAI0_TX3_RX2

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

127

Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

AV8

AU7

ESAI0_TX4_RX1

ESAI0_TX5_RX0

ESAI1_FSR

VDD_ESAI0_MCLK_1P8_3P3

GPIO

ALT0

ESAI0_TX4_RX1

ESAI0_TX5_RX0

ESAI1_FSR

BE11

BF12

BD12

AY10

BF10

BA11

AU11

AV10

AY12

AT10

VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO

ALT0

ESAI1_FST

ESAI1_SCKR

ESAI1_SCKT

ESAI1_TX0

ESAI1_TX1

ESAI1_TX2_RX3

ESAI1_TX3_RX2

ESAI1_TX4_RX1

ESAI1_TX5_RX0

FLEXCAN0_RX

FLEXCAN0_TX

FLEXCAN1_RX

FLEXCAN1_TX

FLEXCAN2_RX

FLEXCAN2_TX

GPT0_CAPTURE

GPT0_CLK

ESAI1_TX2_RX3

ESAI1_TX3_RX2

ESAI1_TX4_RX1

ESAI1_TX5_RX0

FLEXCAN0_RX

LSIO.GPIO3.IO30

FLEXCAN1_RX

LSIO.GPIO4.IO00

FLEXCAN2_RX

LSIO.GPIO4.IO02

GPT0_CAPTURE

GPT0_CLK

VDD_FLEXCAN_1P8_3P3

VDD_M4_GPT_UART_1P8_3P3

VDD_HDMI_RX0_1P8

GPIO

HDMI

ALT0

ALT3

ALT0

ALT3

ALT0

ALT3

ALT0

AV52

AY52

AW53

AY50

BA53

BA51

BL13

BM14

BJ9

GPT0_COMPARE

GPT1_CAPTURE

GPT1_CLK

GPT0_COMPARE

GPT1_CAPTURE

GPT1_CLK

GPT1_COMPARE

HDMI_RX0_ARC_N³

HDMI_RX0_ARC_P³

HDMI_RX0_CEC³

HDMI_RX0_CLK_N³

HDMI_RX0_CLK_P³

HDMI_RX0_DATA0_N³

HDMI_RX0_DATA0_P³

HDMI_RX0_DATA1_N³

HDMI_RX0_DATA1_P³

GPT1_COMPARE

Not muxed

BL11

BM12

BL15

BM16

BL17

BM18

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BL19

BM20

BH10

BE13

BF14

BN11

BJ11

BG3

BH2

BJ1

HDMI_RX0_DATA2_N³

HDMI_RX0_DATA2_P³

HDMI_RX0_DDC_SCL³

HDMI_RX0_DDC_SDA³

HDMI_RX0_HPD³

VDD_HDMI_RX0_1P8

HDMI

Not muxed

HDMI_RX0_MON_5V³

HDMI_RX0_REXT³

HDMI_TX0_AUX_N

VDD_HDMI_TX0_1P8

HDMI

Not muxed

HDMI_TX0_AUX_P

HDMI_TX0_CEC

BK2

HDMI_TX0_CLK_EDP3_N

HDMI_TX0_CLK_EDP3_P

HDMI_TX0_DATA0_EDP2_N

HDMI_TX0_DATA0_EDP2_P

HDMI_TX0_DATA1_EDP1_N

HDMI_TX0_DATA1_EDP1_P

HDMI_TX0_DATA2_EDP0_N

HDMI_TX0_DATA2_EDP0_P

HDMI_TX0_DDC_SCL

HDMI_TX0_DDC_SDA

HDMI_TX0_HPD

BL3

BM4

BL5

BM6

BL7

BM8

BL9

BG1

BN5

BH8

BJ7

HDMI_TX0_REXT

BN9

BN7

BC51

BE51

BD52

HDMI_TX0_TS_SCL

HDMI_TX0_TS_SDA

JTAG_TCK

VDD_HDMI_TX0_DIG_3P3

VDD_SCU_1P8

GPIO

TEST

ALT0

HDMI_TX0_TS_SCL

HDMI_TX0_TS_SDA

Not muxed

JTAG_TDI

JTAG_TDO

Drive-

BA49

BE53

JTAG_TMS

JTAG_TRST_B

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BL41

BN41

BK42

BM42

BL43

BN43

BK44

BM44

BL45

BN45

BG45

BH46

BG43

BH44

BG41

BH42

BG39

BH40

BG37

BH38

BE39

BD40

BD38

BD36

BE37

BE35

LVDS0_CH0_CLK_N

LVDS0_CH0_CLK_P

LVDS0_CH0_TX0_N

LVDS0_CH0_TX0_P

LVDS0_CH0_TX1_N

LVDS0_CH0_TX1_P

LVDS0_CH0_TX2_N

LVDS0_CH0_TX2_P

LVDS0_CH0_TX3_N

LVDS0_CH0_TX3_P

LVDS0_CH1_CLK_N

LVDS0_CH1_CLK_P

LVDS0_CH1_TX0_N

LVDS0_CH1_TX0_P

LVDS0_CH1_TX1_N

LVDS0_CH1_TX1_P

LVDS0_CH1_TX2_N

LVDS0_CH1_TX2_P

LVDS0_CH1_TX3_N

LVDS0_CH1_TX3_P

LVDS0_GPIO00

VDD_LVDS0_1P8

LVDS

Not muxed

VDD_LVDS0_1P8

LVDS

Not muxed

VDD_LVDS_DIG_1P8_3P3

GPIO

ALT0

LVDS0_GPIO00

LVDS0_GPIO01

LVDS0_I2C0_SCL

LVDS0_I2C0_SDA

LVDS0_I2C1_SCL

LVDS0_I2C1_SDA

LVDS0_I2C0_SCL

LVDS0_I2C0_SDA

LVDS0_I2C1_SCL

LVDS0_I2C1_SDA

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BK36

BM36

BL37

BN37

BK38

BM38

BL39

BN39

BK40

BM40

BK34

BM34

BL33

BN33

BK32

BM32

BL31

BN31

BK30

BM30

BD34

BH36

BL35

BE33

BD32

BN35

LVDS1_CH0_CLK_N

LVDS1_CH0_CLK_P

LVDS1_CH0_TX0_N

LVDS1_CH0_TX0_P

LVDS1_CH0_TX1_N

LVDS1_CH0_TX1_P

LVDS1_CH0_TX2_N

LVDS1_CH0_TX2_P

LVDS1_CH0_TX3_N

LVDS1_CH0_TX3_P

LVDS1_CH1_CLK_N

LVDS1_CH1_CLK_P

LVDS1_CH1_TX0_N

LVDS1_CH1_TX0_P

LVDS1_CH1_TX1_N

LVDS1_CH1_TX1_P

LVDS1_CH1_TX2_N

LVDS1_CH1_TX2_P

LVDS1_CH1_TX3_N

LVDS1_CH1_TX3_P

LVDS1_GPIO00

VDD_LVDS1_1P8

LVDS

Not muxed

VDD_LVDS1_1P8

LVDS

Not muxed

VDD_LVDS_DIG_1P8_3P3

GPIO

ALT0

LVDS1_GPIO00

LVDS1_GPIO01

LVDS1_I2C0_SCL

LVDS1_I2C0_SDA

LVDS1_I2C1_SCL

LVDS1_I2C1_SDA

LVDS1_I2C0_SCL

LVDS1_I2C0_SDA

LVDS1_I2C1_SCL

LVDS1_I2C1_SDA

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

AR47

AU53

AM44

AU51

AP44

AU47

AR45

AU49

BC3

M40_GPIO0_00

M40_GPIO0_01

VDD_M4_GPT_UART_1P8_3P3

GPIO

ALT0

M40_GPIO0_00

M40_GPIO0_01

M40_I2C0_SCL

M40_I2C0_SDA

M41_GPIO0_00

M41_GPIO0_01

M41_I2C0_SCL

M41_I2C0_SDA

MCLK_IN0

M40_I2C0_SCL

M40_I2C0_SDA

M41_GPIO0_00

M41_GPIO0_01

M41_I2C0_SCL

M41_I2C0_SDA

MCLK_IN0

VDD_ESAI0_MCLK_1P8_3P3

VDD_MIPI_CSI0_1P8

GPIO

CSI

ALT0

ALT3

BD4

MCLK_OUT0

LSIO.GPIO3.IO01

Not muxed

BE21

BF20

BE23

BF22

BE19

BF18

BE25

BF24

BE17

BF16

BL23

BM22

BH24

BN19

BJ23

MIPI_CSI0_CLK_N

MIPI_CSI0_CLK_P

MIPI_CSI0_DATA0_N

MIPI_CSI0_DATA0_P

MIPI_CSI0_DATA1_N

MIPI_CSI0_DATA1_P

MIPI_CSI0_DATA2_N

MIPI_CSI0_DATA2_P

MIPI_CSI0_DATA3_N

MIPI_CSI0_DATA3_P

MIPI_CSI0_GPIO0_00

MIPI_CSI0_GPIO0_01

MIPI_CSI0_I2C0_SCL

MIPI_CSI0_I2C0_SDA

MIPI_CSI0_MCLK_OUT

VDD_MIPI_CSI0_1P8

VDD_MIPI_CSI_DIG

CSI

Not muxed

GPIO

ALT0

ALT3

MIPI_CSI0_GPIO0_00

MIPI_CSI0_GPIO0_01

MIPI_CSI0_I2C0_SCL

MIPI_CSI0_I2C0_SDA

LSIO.GPIO1.IO29

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BH16

BJ17

BH18

BJ19

BH14

BJ15

BH20

BJ21

BH12

BJ13

BN15

BN13

BN17

BE15

BN23

BN27

BL27

BM28

BK28

BM26

BK26

BN29

BL29

BN25

BL25

BD30

BD28

BE29

BE31

MIPI_CSI1_CLK_N

MIPI_CSI1_CLK_P

VDD_MIPI_CSI1_1P8

CSI

Not muxed

MIPI_CSI1_DATA0_N

MIPI_CSI1_DATA0_P

MIPI_CSI1_DATA1_N

MIPI_CSI1_DATA1_P

MIPI_CSI1_DATA2_N

MIPI_CSI1_DATA2_P

MIPI_CSI1_DATA3_N

MIPI_CSI1_DATA3_P

MIPI_CSI1_GPIO0_00

MIPI_CSI1_GPIO0_01

MIPI_CSI1_I2C0_SCL

MIPI_CSI1_I2C0_SDA

MIPI_CSI1_MCLK_OUT

MIPI_DSI0_CLK_N

VDD_MIPI_CSI_DIG

GPIO

ALT0

ALT3

MIPI_CSI1_GPIO0_00

MIPI_CSI1_GPIO0_01

MIPI_CSI1_I2C0_SCL

MIPI_CSI1_I2C0_SDA

LSIO.GPIO1.IO29

VDD_MIPI_DSI0_1P8

DSI

Not muxed

MIPI_DSI0_CLK_P

MIPI_DSI0_DATA0_N

MIPI_DSI0_DATA0_P

MIPI_DSI0_DATA1_N

MIPI_DSI0_DATA1_P

MIPI_DSI0_DATA2_N

MIPI_DSI0_DATA2_P

MIPI_DSI0_DATA3_N

MIPI_DSI0_DATA3_P

MIPI_DSI0_GPIO0_00

MIPI_DSI0_GPIO0_01

MIPI_DSI0_I2C0_SCL

MIPI_DSI0_I2C0_SDA

VDD_MIPI_DSI_DIG_1P8_3P3

GPIO

ALT0

MIPI_DSI0_GPIO0_00

MIPI_DSI0_GPIO0_01

MIPI_DSI0_I2C0_SCL

MIPI_DSI0_I2C0_SDA

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BH30

BG31

BH32

BG33

BH28

BG29

BH34

BG35

BH26

BG27

BM24

BK24

BE27

BG25

MIPI_DSI1_CLK_N

MIPI_DSI1_CLK_P

MIPI_DSI1_DATA0_N

MIPI_DSI1_DATA0_P

MIPI_DSI1_DATA1_N

MIPI_DSI1_DATA1_P

MIPI_DSI1_DATA2_N

MIPI_DSI1_DATA2_P

MIPI_DSI1_DATA3_N

MIPI_DSI1_DATA3_P

MIPI_DSI1_GPIO0_00

MIPI_DSI1_GPIO0_01

MIPI_DSI1_I2C0_SCL

MIPI_DSI1_I2C0_SDA

MLB_CLK⁴

VDD_MIPI_DSI1_1P8

DSI

Not muxed

VDD_MIPI_DSI_DIG_1P8_3P3

GPIO

ALT0

MIPI_DSI1_GPIO0_00

MIPI_DSI1_GPIO0_01

MIPI_DSI1_I2C0_SCL

MIPI_DSI1_I2C0_SDA

MLB_CLK

VDD_MLB_DIG_1P8_3P3

VDD_MLB_1P8

GPIO

MLB

MLB_DATA⁴

MLB_DATA

MLB_SIG⁴

MLB_SIG

E33

MLB_CLK_N⁵

Not muxed

D32

MLB_CLK_P⁵

E35

MLB_DATA_N⁵

F34

MLB_DATA_P⁵

E31

MLB_SIG_N⁵

D30

MLB_SIG_P⁵

BE47

A17

ON_OFF_BUTTON

PCIE_CTRL0_CLKREQ_B

PCIE_CTRL0_PERST_B

PCIE_CTRL0_WAKE_B

PCIE_CTRL1_CLKREQ_B

PCIE_CTRL1_PERST_B

PCIE_CTRL1_WAKE_B

VDD_SNVS_LDO_1P8_CAP

VDD_PCIE_DIG_1P8_3P3

ANA

Not muxed

GPIO

ALT0

PCIE_CTRL0_CLKREQ_B

PCIE_CTRL0_PERST_B

PCIE_CTRL0_WAKE_B

PCIE_CTRL1_CLKREQ_B

PCIE_CTRL1_PERST_B

PCIE_CTRL1_WAKE_B

D20

A15

A25

G25

A27

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

E23

D22

PCIE_REF_QR

PCIE_REXT

VDD_PCIE_LDO_1P8

PCIE

Not muxed

M20 PCIE_SATA0_PHY_PLL_REF_RETURN³

M28

N23

E25

PCIE0_PHY_PLL_REF_RETURN

PCIE1_PHY_PLL_REF_RETURN

PCIE_SATA_REFCLK100M_N³

PCIE_SATA_REFCLK100M_P³

PCIE_SATA0_RX0_N³

PCIE_SATA0_RX0_P³

PCIE_SATA0_TX0_N³

PCIE_SATA0_TX0_P³

PCIE0_RX0_N

VDD_PCIE_LDO_1P0_CAP

PCIE

HCSL compatiable clock

Not muxed

F26

B20

Not muxed

A19

C17

B16

B30

A29

PCIE0_RX0_P

C27

B26

PCIE0_TX0_N

PCIE0_TX0_P

B22

PCIE1_RX0_N

A21

PCIE1_RX0_P

C25

B24

PCIE1_TX0_N

PCIE1_TX0_P

BF50

AY46

BG51

BH50

BL51

PMIC_EARLY_WARNING

PMIC_I2C_SCL

VDD_SCU_1P8

SCU

ALT0

PMIC_EARLY_WARNING

PMIC_I2C_SCL

PMIC_I2C_SDA

PMIC_INT_B

PMIC_I2C_SDA

PMIC_INT_B

PMIC_ON_REQ

VDD_SNVS_LDO_1P8_CAP

VDD_SCU_1P8

ANA

SCU

Not muxed

Drive-

BE49

POR_B

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135

Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

G13

F14

H14

H16

G17

E17

E15

F16

H18

H20

G19

F20

H22

F18

F22

H24

D12

D14

E13

E11

H12

F10

J11

QSPI0A_DATA0

QSPI0A_DATA1

QSPI0A_DATA2

QSPI0A_DATA3

QSPI0A_DQS

QSPI0A_SCLK

QSPI0A_SS0_B

QSPI0A_SS1_B

QSPI0B_DATA0

QSPI0B_DATA1

QSPI0B_DATA2

QSPI0B_DATA3

QSPI0B_DQS

QSPI0B_SCLK

QSPI0B_SS0_B

QSPI0B_SS1_B

QSPI1A_DATA0

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1A_DQS

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

RTC_XTALI

VDD_QSPI0_1P8_3P3

FASTD ALT0

ANA

QSPI0A_DATA0

QSPI0A_DATA1

QSPI0A_DATA2

QSPI0A_DATA3

QSPI0A_DQS

QSPI0A_SCLK

QSPI0A_SS0_B

QSPI0A_SS1_B

QSPI0B_DATA0

QSPI0B_DATA1

QSPI0B_DATA2

QSPI0B_DATA3

QSPI0B_DQS

VDD_QSPI0_1P8_3P3

QSPI0B_SCLK

QSPI0B_SS0_B

QSPI0B_SS1_B

QSPI1A_DATA0

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1A_DQS

VDD_QSPI1A_1P8_3P3

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

Not muxed

G11

BN47

BL47

AV6

AV4

AU3

AU5

AU1

AV2

VDD_SNVS_LDO_1P8_CAP

VDD_SPI_SAI_1P8_3P3

RTC_XTALO

SAI1_RXC

GPIO

ALT0

SAI1_RXC

SAI1_RXD

SAI1_RXFS

SAI1_TXC

SAI1_TXD

SAI1_TXFS

SAI1_RXD

SAI1_RXFS

SAI1_TXC

SAI1_TXD

SAI1_TXFS

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136

Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BB44

BC45

BJ53

BA43

AY42

BK52

AU43

AV44

AW45

BB46

BC47

AY44

BG49

BF48

BC53

BA47

BB50

AL45

AP46

AN45

AL43

AT48

AP48

BE41

BE43

BD46

BD42

BD6

SCU_BOOT_MODE0

SCU_BOOT_MODE1

SCU_BOOT_MODE2

SCU_BOOT_MODE3

SCU_BOOT_MODE4

SCU_BOOT_MODE5

SCU_GPIO0_00

SCU_GPIO0_01

SCU_GPIO0_02

SCU_GPIO0_03

SCU_GPIO0_04

SCU_GPIO0_05

SCU_GPIO0_06

SCU_GPIO0_07

SCU_PMIC_MEMC_ON

SCU_PMIC_STANDBY

SCU_WDOG_OUT

SIM0_CLK

VDD_SCU_1P8

SCU

Not muxed

ALT0

SCU_BOOT_MODE4

SCU_BOOT_MODE5

SCU_GPIO0_00

SCU_GPIO0_01

SCU_GPIO0_02

SCU_GPIO0_03

SCU_GPIO0_04

SCU_GPIO0_05

SCU_GPIO0_06

SCU_GPIO0_07

Not muxed

VDD_SCU_1P8

GPIO

ALT0

VDD_SCU_1P8

SCU

Drive-

VDD_SIM0_1P8_3P3

GPIO

ALT3

LSIO.GPIO0.IO00

LSIO.GPIO0.IO05

LSIO.GPIO0.IO02

SIM0_PD

SIM0_GPIO0_00

SIM0_IO

SIM0_PD

SIM0_POWER_EN

SIM0_RST

LSIO.GPIO0.IO04

SIM0_RST

SNVS_TAMPER_IN0

SNVS_TAMPER_IN1

SNVS_TAMPER_OUT0

SNVS_TAMPER_OUT1

SPDIF0_EXT_CLK

SPDIF0_RX

VDD_SNVS_LDO_1P8_CAP

ANA

Not muxed

Hi-Z

VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO

ALT0

ALT3

SPDIF0_EXT_CLK

SPDIF0_RX

BC7

BC9

SPDIF0_TX

LSIO.GPIO2.IO15

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Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

BC1

BA3

BB4

BA5

AY6

SPI0_CS0

SPI0_CS1

VDD_SPI_SAI_1P8_3P3

GPIO

ALT0

SPI0_CS0

SPI0_CS1

SPI0_SCK

SPI0_SDI

SPI0_SDO

ALT3

ALT0

LSIO.GPIO3.IO03

SPI2_CS0

AW1

AY2

SPI2_CS0

SPI2_CS1

AW5

AY4

SPI2_SCK

SPI2_SDI

BA1

BG5

BD8

BF6

SPI2_SDO

ALT3

ALT0

LSIO.GPIO3.IO08

SPI3_CS0

VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO

SPI3_CS1

SPI3_SCK

ALT0

ALT3

SPI3_SCK

BE5

BF2

SPI3_SDI

SPI3_SDO

LSIO.GPIO2.IO18

Not muxed

Hi-Z

BC49

AW49

AU45

AV50

AV48

AV46

AR43

AT44

AY48

H26

TEST_MODE_SELECT

UART0_CTS_B

UART0_RTS_B

UART0_RX

VDD_SCU_1P8

SCU

VDD_M4_GPT_UART_1P8_3P3

GPIO

ALT0

ALT3

ALT0

ALT3

ALT0

ALT3

ALT0

ALT3

UART0_CTS_B

LSIO.GPIO0.IO22

UART0_RX

UART0_TX

LSIO.GPIO0.IO21

UART1_CTS_B

LSIO.GPIO0.IO26

UART1_RX

UART1_CTS_B

UART1_RTS_B

UART1_RX

UART1_TX

LSIO.GPIO0.IO24

USB_HSIC0_DATA

USB_HSIC0_STROBE

Not muxed

USB_HSIC0_DATA

USB_HSIC0_STROBE

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_ID

USB_OTG1_VBUS

VDD_USB_HSIC0_1P2

VDD_USB_OTG1_3P3

FASTD ALT0

F28

C39

OTG

B40

A37

A39

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138

Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

C37

B38

F30

E29

A35

E27

B34

C35

B32

A33

USB_OTG2_DN

USB_OTG2_DP

USB_OTG2_ID

USB_OTG2_REXT

USB_OTG2_VBUS

USB_SS3_REXT

USB_SS3_RX_N

USB_SS3_RX_P

USB_SS3_TX_N

USB_SS3_TX_P

USB_SS3_TC0

USB_SS3_TC1

USB_SS3_TC2

USB_SS3_TC3

USDHC1_CLK

VDD_USB_OTG2_3P3

OTG

USB3

GPIO

Not muxed

VDD_USB_SS3_LDO_1P0_CAP

Not muxed

VDD_USB_SS3_TC_3P3

ALT0

USB_SS3_TC0

USB_SS3_TC1

USB_SS3_TC2

USB_SS3_TC3

USDHC1_CLK

H10

J39

VDD_USDHC1_1P8_3P3

FASTD ALT0

Drive-

G41

E37

F38

E39

F40

H40

G43

F42

H42

J43

USDHC1_CMD

USDHC1_DATA0

USDHC1_DATA1

USDHC1_DATA2

USDHC1_DATA3

USDHC1_DATA4

USDHC1_DATA5

USDHC1_DATA6

USDHC1_DATA7

USDHC1_STROBE

USDHC1_RESET_B

USDHC1_VSELECT

USDHC2_CD_B

USDHC1_CMD

USDHC1_DATA0

USDHC1_DATA1

USDHC1_DATA2

USDHC1_DATA3

USDHC1_DATA4

USDHC1_DATA5

USDHC1_DATA6

USDHC1_DATA7

USDHC1_STROBE

LSIO.GPIO4.IO07

USDHC2_CD_B

VDD_USDHC_VSELECT_1P8_3P3 GPIO

ALT3

ALT0

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

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139

Package information and contact assignments

Table 127. 29 × 29 mm functional contact assignments (continued)

Reset Condition

Ball

Ball Name

Power Domain

Type¹

Default

mode

Default function

State²

F46

H44

H48

G45

L45

J45

USDHC2_CLK

USDHC2_CMD

USDHC2_DATA0

USDHC2_DATA1

USDHC2_DATA2

USDHC2_DATA3

USDHC2_RESET_B

USDHC2_VSELECT

USDHC2_WP

VDD_USDHC2_1P8_3P3

FASTD ALT3

ALT0

LSIO.GPIO5.IO24

USDHC2_CMD

USDHC2_DATA0

USDHC2_DATA1

USDHC2_DATA2

USDHC2_DATA3

LSIO.GPIO4.IO09

LSIO.GPIO4.IO10

USDHC2_WP

VDD_USDHC_VSELECT_1P8_3P3 GPIO

ALT3

ALT0

BN49

BL49

XTALI

VDD_SCU_XTAL_1P8

ANA

Not muxed

XTALO

FASTD are GPIO balls configured for high speed operation using the FASTFRZ control.

Reset condition shown is before boot code execution. For pad changes after boot code execution, see the “System Boot” chapter of

the device reference manual,

HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected

HDMI-RX support will be enabled.

MLB is not supported on this device. Users may choose alternate functions as determined by the IOMUX.

MLB is not supported on this device. Terminate these outputs per the Hardware Developer’s Guide for unused I/O signals.

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

140

NXP Semiconductors

Package information and contact assignments

The following table shows the DRAM pin function for the 29 x 29 mm package.

Table 128. 29 x 29 mm DRAM pin function

LPDDR4 Function

Ball Name

x = 0 x = 1

Notes

DDR_CHx_ATO

AF46 AF8

—

CK_c_A

CK_t_A

CK_c_B

CK_t_B

CA2_A

CA4_A

—

NXP Internal Use Only (Leave Unconnected)

DDR_CHx_CK0_N

DDR_CHx_CK0_P

DDR_CHx_CK1_N

DDR_CHx_CK1_P

DDR_CHx_DCF00

DDR_CHx_DCF01

DDR_CHx_DCF02

DDR_CHx_DCF03

DDR_CHx_DCF04

DDR_CHx_DCF05

DDR_CHx_DCF06

DDR_CHx_DCF07

DDR_CHx_DCF08

DDR_CHx_DCF09

DDR_CHx_DCF10

DDR_CHx_DCF11

DDR_CHx_DCF12

DDR_CHx_DCF13

DDR_CHx_DCF14

DDR_CHx_DCF15

DDR_CHx_DCF16

DDR_CHx_DCF17

DDR_CHx_DCF18

DDR_CHx_DCF19

DDR_CHx_DCF20

DDR_CHx_DCF21

DDR_CHx_DCF22

DDR_CHx_DCF23

DDR_CHx_DCF24

Y50

The exact clock and control line connections will be

dependent on the memory configuration in use. Refer to

the Hardware Developers Guide (HDG) for further details.

W49

AB50 AB4

AC49 AC5

U47

W47

Y48

Y46

CA5_A

—

W43 W11

Y44

W45

W51

T48

T52

T50

U51

U49

T46

W53

Y52

U53

Y10

—

CA3_A

—

CS0_A

CA0_A

CS1_A

—

CKE0_A

CKE1_A

CA1_A

CA4_B

RESET_N

CA5_B

—

AC47 AC7

AB48 AB6

AB46 AB8

AC43 AC11

AE45 AE9

AC51 AC3

AC45 AC9

AB44 AB10

—

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

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141

Package information and contact assignments

Table 128. 29 x 29 mm DRAM pin function (continued)

Ball Name

x = 0 x = 1

LPDDR4 Function

Notes

DDR_CHx_DCF25

DDR_CHx_DCF26

DDR_CHx_DCF27

DDR_CHx_DCF28

DDR_CHx_DCF29

DDR_CHx_DCF30

DDR_CHx_DCF31

DDR_CHx_DCF32

DDR_CHx_DCF33

DDR_CHx_DM0

DDR_CHx_DM1

DDR_CHx_DM2

DDR_CHx_DM3

DDR_CHx_DQ00

DDR_CHx_DQ01

DDR_CHx_DQ02

DDR_CHx_DQ03

DDR_CHx_DQ04

DDR_CHx_DQ05

DDR_CHx_DQ06

DDR_CHx_DQ07

DDR_CHx_DQ08

DDR_CHx_DQ09

DDR_CHx_DQ10

DDR_CHx_DQ11

DDR_CHx_DQ12

DDR_CHx_DQ13

DDR_CHx_DQ14

DDR_CHx_DQ15

DDR_CHx_DQ16

DDR_CHx_DQ17

DDR_CHx_DQ18

DDR_CHx_DQ19

AF52 AF2

AE47 AE7

AE51 AE3

AF50 AF4

AE49 AE5

AC53 AC1

AB52 AB2

AE53 AE1

AF48 AF6

—

The exact clock and control line connections will be

dependent on the memory configuration in use. Refer to

the Hardware Developers Guide (HDG) for further details.

CA3_B

CA0_B

CS0_B

CS1_B

CKE0_B

CKE1_B

CA1_B

CA2_B

DMI[3..0]

H52

N47

The exact mask, strobe and data connections to memory

are flexible as long as the correct byte mapping is used,

there is no restriction on the bit connections within each

byte.

AJ47 AJ7

AP52 AP2

DM0 -> DQS0(_N/P) -> DQ[7..0]

DM1 -> DQS1(_N/P) -> DQ[15..8]

DM2 -> DQS2(_N/P) -> DQ[23..16]

DM3 -> DQS3(_N/P) -> DQ[31..24]

P44

N45

L47

K48

H50

G53

G51

N43

L49

K50

N51

L51

P46

N49

P50

P48

P10

DQ[31..0]

N11

AM50 AM4

AL49 AL5

AL51 AL3

AJ51 AJ3

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

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142

Package information and contact assignments

Table 128. 29 x 29 mm DRAM pin function (continued)

Ball Name

x = 0 x = 1

LPDDR4 Function

Notes

DDR_CHx_DQ20

DDR_CHx_DQ21

DDR_CHx_DQ22

DDR_CHx_DQ23

DDR_CHx_DQ24

DDR_CHx_DQ25

DDR_CHx_DQ26

DDR_CHx_DQ27

DDR_CHx_DQ28

DDR_CHx_DQ29

DDR_CHx_DQ30

DDR_CHx_DQ31

DDR_CHx_DQS0_N

DDR_CHx_DQS0_P

DDR_CHx_DQS1_N

DDR_CHx_DQS1_P

DDR_CHx_DQS2_N

DDR_CHx_DQS2_P

DDR_CHx_DQS3_N

DDR_CHx_DQS3_P

DDR_CHx_DTO0

DDR_CHx_DTO1

DDR_CHx_VREF

DDR_CHx_ZQ

AJ49 AJ5

AH46 AH8

AH48 AH6

AH50 AH4

AJ45 AJ9

AH44 AH10

AM48 AM6

AL47 AL7

AR53 AR1

AP50 AP4

AJ43 AJ11

AR51 AR3

DQ[31..0]

The exact mask, strobe and data connections to memory

are flexible as long as the correct byte mapping is used,

there is no restriction on the bit connections within each

byte.

DM0 -> DQS0(_N/P) -> DQ[7..0]

DM1 -> DQS1(_N/P) -> DQ[15..8]

DM2 -> DQS2(_N/P) -> DQ[23..16]

DM3 -> DQS3(_N/P) -> DQ[31..24]

L53

K52

P52

N53

DQS[3..0]_c maps to _N

DQS[3..0]_t maps to _P

AH52 AH2

AJ53 AJ1

AL53 AL1

AM52 AM2

U45

T44

U43

T10

U11

—

NXP Internal Use Only (Leave Unconnected)

—

AF44 AF10

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

NXP Semiconductors

143

Release Notes

7 Release Notes

This table provides release notes for the data sheet.

Table 129. Data sheet release notes

Substantive Change(s)

Rev.

Number

Date

05/2021 • Clarified LVDS Tx port information in Table 1, "i.MX 8QuadPlus advanced features" under Display I/O.

• Updated Table 2, "i.MX 8QuadPlus Orderable part numbers" information.

• Updated the example in Section 1.2, “System Controller Firmware (SCFW) Requirements".

• Corrected document IDs in Table 3, "Related resources".

• Updated LVDS information and clarified KHz for XTAL OSC32K in Table 4, "i.MX 8QuadPlus modules

list".

• In Table 8, "Operating ranges", added min frequency for VDD_A72 and VDD_A53.

• Updated note in Section 4.1.5, “Maximum Supply Currents".

• Updated the value ranges in Table 26, "LVDS PHY PLL".

• Updated footnotes pointing to Section 4.6.2, “Input Signal Monotonic Requirements" in Table 30,

Table 31, Table 32, Table 33, Table 34, Table 35, and Table 36.

• Corrected test conditions in Table 38, "LPDDR4 DC parameters".

• Added Section 4.6.2, “Input Signal Monotonic Requirements".

• Corrected maximum frequency test conditions and footnotes 2 and 3 in Table 40, "General Purpose I/O

AC Parameters".

• In Table 81, "LVDS pins", updated single channel values.

• Updated PCI Express Gen 2 values for A_OPENINGand added footnote to Table 93, "PCIe receiver eye

specifications for example standards".

• Rewrote introductory paragraph for Section 5.1, “Boot mode configuration inputs".

• Clarified QSPI information in Table 125, "Interface allocation during boot".

• Corrected default function for Ball AP46 in Table 127, "29 × 29 mm functional contact assignments".

• Corrected x=0 column value for DDR_CHx_DTO1 in Table 128, "29 x 29 mm DRAM pin function".

i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021

144

NXP Semiconductors

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Date of release: 05/2021

Document identifier: IMX8QPAEC

MIMX8QPNAVUXXAX [NXP]

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