MK50X256CMC100R [NXP]
32-BIT, FLASH, 100MHz, RISC MICROCONTROLLER, PBGA121, 8 X 8 MM, MAPBGA-121;
| 型号： | MK50X256CMC100R |
| 厂家： | 
NXP |
| 描述： | 32-BIT, FLASH, 100MHz, RISC MICROCONTROLLER, PBGA121, 8 X 8 MM, MAPBGA-121 时钟 微控制器 外围集成电路 |
| 文件： | 总69页 (文件大小：1770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: K50P121M100SF2
Rev. 4, 3/2011
Freescale Semiconductor
Data Sheet: Product Preview
K50P121M100SF2
K50 Sub-Family Data Sheet
Supports the following:
MK50X256CMC100,
MK50N512CMC100
Features
Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
•
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 85°C
•
•
•
Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (up to x64) integrated
into each ADC
– Two 12-bit DACs
– Two operational amplifiers
– Two transimpedance amplifiers
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
Timers
•
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
Clocks
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
Communication interfaces
– USB full-/low-speed On-the-Go controller with on-
chip transceiver
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– I2S module
•
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
– 128-bit unique identification (ID) number per chip
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2011 Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................4
6.1 Core modules....................................................................21
6.1.1 Debug trace timing specifications.........................21
6.1.2 JTAG electricals....................................................21
6.2 System modules................................................................25
6.3 Clock modules...................................................................25
6.3.1 MCG specifications...............................................25
6.3.2 Oscillator electrical specifications.........................27
6.3.3 32kHz Oscillator Electrical Characteristics............29
6.4 Memories and memory interfaces.....................................30
6.4.1 Flash (FTFL) electrical specifications....................30
6.4.2 EzPort Switching Specifications............................32
6.4.3 Flexbus Switching Specifications..........................33
6.5 Security and integrity modules..........................................35
6.6 Analog...............................................................................35
6.6.1 ADC electrical specifications.................................35
6.6.2 CMP and 6-bit DAC electrical specifications.........43
6.6.3 12-bit DAC electrical characteristics.....................46
6.6.4 Op-amp electrical specifications...........................49
6.6.5 Transimpedance amplifier electrical
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3 Terminology and guidelines......................................................5
3.1 Definition: Operating requirement......................................5
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................6
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................7
3.6 Relationship between ratings and operating
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
3.9 Typical value conditions....................................................9
4 Ratings......................................................................................9
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................10
4.3 ESD handling ratings.........................................................10
4.4 Voltage and current operating ratings...............................10
5 General.....................................................................................11
5.1 Nonswitching electrical specifications...............................11
5.1.1 Voltage and current operating requirements.........11
5.1.2 LVD and POR operating requirements.................12
5.1.3 Voltage and current operating behaviors..............13
5.1.4 Power mode transition operating behaviors..........13
5.1.5 Power consumption operating behaviors..............14
5.1.6 EMC radiated emissions operating behaviors.......17
5.1.7 Designing with radiated emissions in mind...........18
5.1.8 Capacitance attributes..........................................18
5.2 Switching specifications.....................................................18
5.2.1 Device clock specifications...................................18
5.2.2 General switching specifications...........................19
5.3 Thermal specifications.......................................................20
5.3.1 Thermal operating requirements...........................20
5.3.2 Thermal attributes.................................................20
6 Peripheral operating requirements and behaviors....................20
specifications — full range....................................50
6.6.6 Transimpedance amplifier electrical
specifications — limited range..............................51
6.6.7 Voltage reference electrical specifications............52
6.7 Timers................................................................................53
6.8 Communication interfaces.................................................54
6.8.1 USB electrical specifications.................................54
6.8.2 USB DCD electrical specifications........................54
6.8.3 USB VREG electrical specifications......................54
6.8.4 DSPI switching specifications (low-speed mode)..55
6.8.5 DSPI switching specifications (high-speed mode) 56
6.8.6 I2C switching specifications..................................58
6.8.7 UART switching specifications..............................58
6.8.8 SDHC specifications.............................................58
6.8.9 I2S switching specifications..................................59
6.9 Human-machine interfaces (HMI)......................................61
6.9.1 TSI electrical specifications...................................61
7 Dimensions...............................................................................62
7.1 Obtaining package dimensions.........................................62
8 Pinout........................................................................................63
8.1 K50 Signal Multiplexing and Pin Assignments..................63
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
2
Freescale Semiconductor, Inc.
Preliminary
8.2 K50 Pinouts.......................................................................68
9 Revision History........................................................................68
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
3
Preliminary
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK50 and MK50.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
M
Kinetis family
• K50
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
4
Freescale Semiconductor, Inc.
Terminology and guidelines
Values
Field
Description
Program flash memory size
FFF
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• EX = 64 QFN (9 mm x 9 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MF = 196 MAPBGA (15 mm x 15 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CCC
Maximum CPU frequency (MHz)
Packaging type
• 50 = 50 MHz
• 72 = 72 MHz
• 100 = 100 MHz
• 120 = 120 MHz
• 150 = 150 MHz
N
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK50N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
5
Preliminary
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal
range
Normal
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
8
Freescale Semiconductor, Inc.
Preliminary
Ratings
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
V
VDD
3.3 V supply voltage
3.3
4 Ratings
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
9
Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
Solder temperature, leaded
—
—
260
245
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 85°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
5.5
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
10
Freescale Semiconductor, Inc.
General
Unit
Symbol
Description
Min.
Max.
VAIO
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDDA
VUSB_DP
VUSB_DM
VREGIN
VBAT
Analog supply voltage
USB_DP input voltage
USB_DM input voltage
USB regulator input
VDD – 0.3
–0.3
VDD + 0.3
3.63
V
V
V
V
V
–0.3
3.63
–0.3
6.0
RTC battery supply voltage
–0.3
3.8
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
–0.1
–0.1
1.71
3.6
0.1
0.1
3.6
V
V
V
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
VBAT
VIH
RTC battery supply voltage
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
Input hysteresis
0.06 × VDD
—
V
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
11
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIC
DC injection current — single pin
• VIN < VSS
1
0
–0.2
mA
DC injection current — total MCU limit, includes sum
of all stressed pins
1
0
–5
mA
• VIN < VSS
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
TBD
1. All functional non-supply pins are internally clamped to VSS, and induce an injection current when VIN is less than VSS. The
IIC maximum operating requirement should not be exceeded. If this requirement cannot be met, the input must be current
limited to the value specified.
5.1.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
TBD
TBD
TBD
TBD
2.70
2.80
2.90
3.00
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
60
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
TBD
1.60
TBD
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
TBD
TBD
TBD
TBD
1.80
1.90
2.00
2.10
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
40
mV
VBG
tLPO
Bandgap voltage reference
TBD
TBD
1.00
TBD
TBD
V
Internal low power oscillator period
factory trimmed
1000
μs
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
12
Freescale Semiconductor, Inc.
General
Notes
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
VPOR_VBAT Falling VBAT supply POR detect voltage
TBD
1.1
TBD
V
5.1.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) except TRI0_DM,
TRI0_DP, TRI1_DM, TRI1_DP
1
1
IILKG_A
Input leakage current (per pin) for TRI0_DM,
TRI0_DP, TRI1_DM, TRI1_DP
—
1
nA
IOZ
RPU
RPD
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
30
30
1
μA
kΩ
kΩ
50
50
2
3
Internal pulldown resistors
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
13
General
5.1.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus and FlexBus clocks = 50 MHz
• Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
RUN → VLLS1 → RUN
• RUN → VLLS1
—
—
4.1
μs
μs
• VLLS1 → RUN
123.8
RUN → VLLS2 → RUN
• RUN → VLLS2
—
—
4.1
μs
μs
• VLLS2 → RUN
49.3
RUN → VLLS3 → RUN
• RUN → VLLS3
—
—
4.1
μs
μs
• VLLS3 → RUN
49.2
RUN → LLS → RUN
• RUN → LLS
—
—
4.1
5.9
μs
μs
• LLS → RUN
RUN → STOP → RUN
• RUN → STOP
—
—
4.1
4.2
μs
μs
• STOP → RUN
RUN → VLPS → RUN
• RUN → VLPS
—
—
4.1
5.8
μs
μs
• VLPS → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
14
Freescale Semiconductor, Inc.
General
5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
TBD
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
2
3
4
• @ 1.8V
• @ 3.0V
—
—
40
42
TBD
TBD
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
55
56
TBD
TBD
mA
mA
IDD_RUN_M Run mode current — all peripheral clocks
enabled and peripherals active, code executing
AX
from flash
• @ 1.8V
—
—
85
85
TBD
TBD
mA
mA
• @ 3.0V
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
35
15
TBD
TBD
mA
mA
2
5
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
—
—
0.4
TBD
TBD
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.25
6
7
8
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
TBD
TBD
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
1.05
50
TBD
TBD
TBD
mA
μA
μA
IDD_LLS
Low leakage stop mode current at 3.0 V
12
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
4
2
TBD
TBD
TBD
μA
μA
nA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
550
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, but peripherals are not in active operation.
4. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, and peripherals are in active operation.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
15
Preliminary
General
6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled. Code executing from flash.
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled, USB regulator disabled
• No GPIOs toggled
• Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16
Freescale Semiconductor, Inc.
Preliminary
General
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled but peripherals are not in active operation
• LVD disabled, USB regulator disabled
• No GPIOs toggled
• Code execution from flash
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
17
Preliminary
General
5.1.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
VRE3
VRE4
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
0.15–50
50–150
TBD
TBD
TBD
TBD
TBD
dBμV
1, 2
150–500
500–1000
0.15–1000
VRE_IEC_SAE IEC and SAE level
—
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.1.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.2 Switching specifications
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
18
Freescale Semiconductor, Inc.
General
Notes
5.2.1 Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fSYS_USB
fBUS
System and core clock
—
20
—
—
—
100
—
MHz
MHz
MHz
MHz
MHz
System and core clock when USB in operation
Bus clock
50
50
25
FB_CLK
fFLASH
FlexBus clock
Flash clock
VLPR mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
2
2
2
1
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I2C signals.
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
2
2
GPIO pin interrupt pulse width (digital glitch filter
ns
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
TBD
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
3
4
—
—
12
36
ns
ns
• Slew enabled
Port rise and fall time (low drive strength)
• Slew disabled
—
—
32
36
ns
ns
• Slew enabled
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
4. 15pF load
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
85
°C
5.3.2 Thermal attributes
Board
type
Symbol
Description
121
Unit
°C/W
°C/W
°C/W
°C/W
Notes
MAPBGA
Single-layer RθJA
(1s)
Thermal resistance, junction to ambient (natural
convection)
TBD
1
Four-layer
(2s2p)
RθJA
Thermal resistance, junction to ambient (natural
convection)
TBD
TBD
TBD
1
1
1
Single-layer RθJMA
(1s)
Thermal resistance, junction to ambient (200 ft./min.
air speed)
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to ambient (200 ft./min.
air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction to board
Thermal resistance, junction to case
TBD
TBD
TBD
°C/W
°C/W
°C/W
2
3
4
Thermal characterization parameter, junction to
package top outside center (natural convection)
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
20
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Twh
Tr
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
ns
ns
ns
ns
ns
—
—
3
Tf
3
Ts
—
—
Th
Data hold
2
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 4. Trace data specifications
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 11. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
ns
50
20
10
—
—
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 12. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
TCLK cycle period
1/J1
—
ns
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J3
TCLK clock pulse width
• Boundary Scan
ns
50
25
—
—
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
0
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
—
—
8
25
25
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
22.1
22.1
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 5. Test clock input timing
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25°C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
—
—
TBD
TBD
0.1
—
4
µA
µs
tirefsts
Internal reference (slow clock) startup time
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+ 0.5
- 1.0
0.5
3.5
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
TBD
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
3
—
—
4
5
MHz
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Iintf
Internal reference (fast clock) current
—
TBD
—
µA
tirefstf
floc_low
Internal reference startup time (fast clock)
—
TBD
—
TBD
—
µs
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20.97
MHz
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
Jacc_fll
FLL period jitter
—
—
TBD
TBD
TBD
TBD
ps
ps
6
6
FLL accumulated jitter of DCO output over a 1µs
time window
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
8
950
• PLL @ 96 MHz (fosc_hi_1=8MHz,
fpll_ref=2MHz, VDIV multiplier=48)
fpll_ref
Jcyc_pll
Jacc_pll
PLL reference frequency range
PLL period jitter
2.0
—
—
4.0
—
MHz
ps
400
TBD
9, 10
9, 10
PLL accumulated jitter over 1µs window
—
—
ps
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Dlock
Dunl
Lock entry frequency tolerance
1.49
—
2.98
%
Lock exit frequency tolerance
Lock detector detection time
4.47
—
—
—
5.97
%
tpll_lock
0.15 +
ms
11
1075(1/
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification was obtained at internal frequency of TBD.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
700
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1.5
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 14. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
800
1.5
3
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
28
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
32
—
40
kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
—
—
8
MHz
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
TBD
ms
2, 3
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
800
4
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
3
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32kHz oscillator DC electrical specifications
Table 16. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
RF
Internal feedback resistor
—
—
100
2.5
—
—
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 16. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cload
Internal load capacitance (programmable)
—
15
—
pF
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
6.3.3.2 32kHz oscillator frequency specifications
Table 17. 32kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
1000
—
1
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 18. NVM program/erase timing specifications
Symbol Description
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
20
TBD
μs
—
—
20
100
800
ms
ms
1
1
thversblk256k Erase Block high-voltage time for 256 KB
160
1. Maximum time based on expectations at cycling end-of-life.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.2 Flash timing specifications — commands
Table 19. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
• 256 KB data flash
—
—
1.4
ms
trd1sec2k
tpgmchk
trdrsrc
Read 1s Section execution time (flash sector)
Program Check execution time
—
—
—
—
—
—
—
50
40
35
μs
μs
μs
μs
1
1
1
Read Resource execution time
35
tpgm4
Program Longword execution time
TBD
Erase Flash Block execution time
• 256 KB data flash
2
2
tersblk256k
tersscr
—
—
160
20
800
100
ms
ms
Erase Flash Sector execution time
Program Section execution time
• 512 B flash
tpgmsec512
tpgmsec1k
tpgmsec2k
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
ms
ms
ms
• 1 KB flash
• 2 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
2.8
35
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
50
320
—
TBD
1600
35
tersall
Erase All Blocks execution time
2
1
tvfykey
Verify Backdoor Access Key execution time
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
Symbol
Description
Typ.
Unit
mA
IDD_PGM
Worst case programming current in program flash
10
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
5
TBD
TBD
—
—
years
years
2
2
10
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 21. NVM reliability specifications (continued)
Typ.1
Symbol Description
Min.
15
Max.
—
Unit
years
cycles
Notes
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
TBD
2
3
10 K
TBD
—
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
12
—
ns
ns
—
12
ns
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EP7
EZP_CS
EP9
EP8
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 9. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 23. Flexbus switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
50
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
Mhz
ns
FB1
FB2
FB3
FB4
FB5
20
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
TBD
0
11.5
—
ns
1
1
2
2
ns
8.5
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
33
Preliminary
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 10. FlexBus read timing diagram
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 11. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
35
Preliminary
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DP3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are used as the PGA inputs and are not
direct device pins. Accuracy specifications for these pins are defined in Table 26 and
Table 27.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 24. 16-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VSSA
—
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VADIN
CADIN
Input voltage
VREFH
V
Input
capacitance
• 16 bit modes
—
—
8
4
10
5
pF
• 8/10/12 bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13/12 bit modes
fADCK < 4MHz
3
—
fADCK
ADC conversion ≤13 bit modes
clock frequency
4
5
1.0
2.0
—
—
18.0
12.0
MHz
MHz
fADCK
ADC conversion 16 bit modes
clock frequency
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion ≤13
6
rate
bit modes
18.484
—
818.330
Ksps
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock =
50MHz
Crate
ADC conversion 16 bit modes
rate
7
No ADC hardware
37.037
—
361.402
Ksps
averaging
Continuous
conversions enabled
Peripheral clock =
50MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
5. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
6. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
7. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
37
Preliminary
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 12. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA
Supply current
0.215
—
1.7
mA
3
ADC
asynchronous
clock source
• ADLPC=1, ADHSC=0
—
—
—
—
2.4
4.0
5.2
6.2
—
—
—
—
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
fADACK
Sample Time
See Reference Manual chapter for sample times
Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC
configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/
converters/ADC_CALCULATOR_CNV.zip?fpsp=1
LSB4
TUE
Total unadjusted
error
• ≤13 bit modes
• <12 bit modes
0.8
0.5
TBD
1
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
• ≤13 bit modes
Typ.2
0.7
Symbol Description
Min.
Max.
TBD
0.5
Unit
Notes
LSB4
DNL
Differential non-
linearity
ADC
conversion
clock
• <12 bit modes
0.2
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
LSB4
LSB4
INL
EFS
EQ
Integral non-
linearity
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• 16 bit modes
• ≤13 bit modes
—
—
—
—
—
—
1.0
0.5
TBD
TBD
TBD
TBD
—
Max
averaging
Full-scale error
0.4
VADIN
VDDA
=
1.0
Quantization
error
-1 to 0
—
0.5
ENOB
Effective number 16 bit differential mode
5
of bits
• Avg=32
TBD
TBD
13.6
13.2
TBD
TBD
bits
bits
• Avg=1
16 bit single-ended mode
• Avg=32
TBD
TBD
TBD
TBD
TBD
TBD
bits
bits
• Avg=1
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
5
5
—
—
-94
TBD
TBD
dB
dB
16 bit single-ended mode
• Avg=32
TBD
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
TBD
TBD
95
—
—
dB
dB
16 bit single-ended mode
• Avg=32
TBD
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IIn
leakage
current
EIL
Input leakage
error
IIn × RAS
mV
=
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
• –40°C to 25°C
• 25°C to 105°C
—
—
TBD
TBD
—
—
mV/°C
mV/°C
VTEMP25 Temp sensor
voltage
25°C
—
TBD
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
5. Input data is 1 kHz sine wave.
FIGURE TBD
Figure 13. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
FIGURE TBD
Figure 14. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
modes
6.6.1.3 16-bit ADC with PGA operating conditions
Table 26. 16-bit ADC with PGA operating conditions
Typ.1
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREFOUT VREFOUT VREFOUT
V
2, 3
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
Input Common
Mode range
V
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA operating conditions (continued)
Typ.1
128
64
Symbol Description
Conditions
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Min.
—
Max.
—
Unit
Notes
IN+ to IN-4
RPGAD
Differntial input
impedance
kΩ
—
—
—
32
—
RAS
TS
Analog source
resistance
—
100
—
Ω
5
6
ADC sampling
time
1.25
—
—
µs
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4 16-bit ADC with PGA characteristics
Table 27. 16-bit ADC with PGA characteristics
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
μA
A
Notes
IDDA_PGA Supply current
—
590
TBD
IDC_PGA
Input DC current
2
IILKG
Input Leakage
current
PGA disabled
—
TBD
TBD
μA
3
Gain4
G
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.98
1.99
3.97
7.95
15.8
31.4
61.2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
R
AS < 100Ω
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
Power supply
rejection ration
Gain=1
TBD
TBD
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC with PGA characteristics (continued)
Typ.1
TBD
TBD
Symbol
Description
Conditions
• Gain=1
Min.
TBD
TBD
Max.
—
Unit
dB
Notes
VCM
500mVpp,
fVCM= 50Hz,
100Hz
CMRR
Common mode
rejection ratio
=
• Gain=64
—
dB
VOFS
TGSW
dG/dT
Input offset
voltage
—
—
0.2
—
TBD
10
mV
µs
Gain=1, ADC
Averaging=32
Gain switching
settling time
5
Gain drift over
temperature
• Gain=1
• Gain=64
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
ppm/°C
ppm/°C
0 to 50°C
dVOFS/dT Offset drift over
temperature
Gain=1
ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
—
—
TBD
TBD
TBD
TBD
%/V
%/V
mV
VDDA from 1.71
to 3.6V
EIL
Input leakage
error
All modes
IIn × RAS
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
Maximum
V
6
differential input
signal swing
where VX = VREFPGA × 0.583
SNR
Signal-to-noise
ratio
• Gain=1
• Gain=64
TBD
TBD
83.0
57.5
—
—
dB
dB
16-bit
differential
mode,
Average=32
THD
Total harmonic
distortion
• Gain=1
• Gain=64
TBD
TBD
89.4
90.0
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
SFDR
Spurious free
dynamic range
• Gain=1
• Gain=64
TBD
TBD
90.9
77.0
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC with PGA characteristics (continued)
Typ.1
12.3
12.7
8.4
Symbol
Description
Conditions
• Gain=1, Average=4
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max.
—
Unit
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
Notes
ENOB
Effective number
of bits
16-bit
differential
mode,
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
—
—
fin=500Hz
8.7
—
13.3
13.1
12.5
11.8
11.1
10.2
9.3
—
—
—
—
—
—
—
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function if input common mode voltage (VCM) and the PGA gain.
3. This is the input leakage current of the module in addition to the PAD leakage current.
Gain = 2PGAG
4.
5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 28. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
—
—
—
—
—
200
20
μA
μA
V
VSS – 0.3
—
VDD
20
VAIO
Analog input offset voltage
mV
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Table 28. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
120
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
TBD
—
ns
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
44
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
45
Preliminary
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 29. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VDACR
TA
Reference voltage
Temperature
1.13
−40
—
3.6
105
100
1
V
1
°C
pF
mA
CL
Output load capacitance
Output load current
2
IL
—
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
46
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 30. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
700
μA
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
—
—
—
1
100
15
200
30
μs
μs
1
1
1
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
—
5
μs
tCCDACHP Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
TBD
100
—
—
μs
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
TBD
VDACR
mV
mV
Vdacouth DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
−100
INL
DNL
DNL
Integral non-linearity error — high speed mode
Differential non-linearity error — VDACR > 2 V
—
—
—
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR
VREFO (1.15 V)
=
VOFFSET Offset error
0.4
0.1
60
—
—
—
0.8
0.6
90
—
%FSR
%FSR
dB
5
5
EG
PSRR
TCO
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
TBD
TBD
μV/C
TGE
—
—
ppm of
FSR/C
AC
Rop
SR
Offset aging coefficient
—
—
—
—
TBD
250
μV/yr
Ω
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP
)
1.2
1.7
—
—
0.05
0.12
• Low power (SPLP
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
)
550
40
—
—
—
—
• Low power (SPLP
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
5. Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
Figure 17. Typical INL error vs. digital code
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 18. Offset at half scale vs. temperature
6.6.4 Op-amp electrical specifications
Table 31. Op-amp electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Operating voltage
1.71
—
3.6
V
ISUPPLY
ISUPPLY
VOS
Supply current (IOUT=0mA, CL=0), low-power mode
Supply current (IOUT=0mA, CL=0), high-speed mode
Input offset voltage
—
—
—
—
—
—
—
70
500
3
TBD
TBD
TBD
—
μA
μA
mV
μV/C
pA
αVOS
IOS
Input offset voltage temperature coefficient
Input offset current (0~50°C)
10
300
TBD
300
—
IOS
Input offset current (-40~105°C)
—
pA
IBIAS
Input bias current (0~50°C)
—
pA
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
Table 31. Op-amp electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IBIAS
Input bias current (0~105°C)
—
TBD
—
pA
VCML
VCMH
RIN
Input common mode voltage low
Input common mode voltage high
Input resistance
0
—
—
—
—
VDD
—
V
V
500
—
—
MΩ
pF
CIN
Input capacitance
—
TBD
—
|XIN|
AC input impedance (fIN=100kHz)
Input common mode rejection ratio
Power supply rejection ratio
Slew rate (ΔVIN=100mV), low-power mode
Slew rate (ΔVIN=100mV), high-speed mode
Unity gain bandwidth, low-power mode
Unity gain bandwidth, high-speed mode
DC open-loop voltage gain
Load capacitance driving capability
Output resistance
—
50
—
MΩ
dB
CMRR
PSRR
SR
60
60
0.1
1
—
—
—
dB
—
—
V/μs
V/μs
MHz
MHz
dB
SR
—
—
GBW
GBW
AV
0.15
1
—
—
—
—
80
—
90
—
—
CL(max)
ROUT
VOUT
IOUT
TBD
TBD
TBD
—
pF
—
—
Ω
Output voltage range
0.1
—
—
V
Output load current
0.5
20
56
TBD
mA
dB
GM
Gain margin
—
—
PM
Phase margin
45
—
—
deg
μs
Tsettle
Settling time (Buffer mode, low-power mode)
(To<0.1%, Vin=2Vp-p, CL=25pF, RL=100k)
—
Tsettle
Settling time (Buffer mode, high-speed mode)
(To<0.1%, Vin=2Vp-p, CL=25pF, RL=100k)
—
TBD
—
μs
Vn
Vn
Voltage noise density (noise floor) 1kHz
Voltage noise density (noise floor) 10kHz
—
—
350
90
TBD
TBD
nV/√Hz
nV/√Hz
6.6.5 Transimpedance amplifier electrical specifications — full range
Table 32. TRIAMP full range operating requirements
Symbol
VDDA
Description
Min.
Max.
Unit
Notes
Supply voltage
1.71
-0.2
3.6
V
V
pf
Ω
VIN
Input voltage range
Output load capacitance
Output resistance
VDDA-1.4
100
CL
ROUT
1500
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 33. TRIAMP full range operating behaviors
Symbol Description
ISUPPLY Supply current (IOUT=0mA, CL=0) — Low-power
mode
Min.
Typ.
Max.
Unit
Notes
—
60
—
—
μA
μA
mV
ISUPPLY
Supply current (IOUT=0mA, CL=0) — High-speed —
mode
280
VOS
αVOS
IOS
Input offset voltage
—
—
—
—
3
TBD
TBD
TBD
TBD
—
Input offset voltage temperature coefficient
Input offset current
10
μV/C
pA
200
300
IBIAS
RIN
Input bias current
pA
Input resistance
500
—
—
MΩ
pF
CIN
Input capacitance
17
TBD
—
—
|XIN|
CMRR
PSRR
SR
AC input impedance (fIN=100kHz)
Input common mode rejection ratio
Power supply rejection ratio
Slew rate (ΔVIN=100mV) — Low-power mode
Slew rate (ΔVIN=100mV) — High speed mode
—
—
MΩ
dB
60
60
0.1
1
—
—
—
dB
—
—
V/μs
V/μs
MHz
MHz
dB
SR
—
—
GBW
GBW
AV
Unity gain bandwidth — Low-power mode 50pF 0.15
—
—
Unity gain bandwidth — High speed mode 50pF
DC open-loop voltage gain
Output voltage range
1
—
—
80
0.15
—
—
50
—
—
—
—
VOUT
IOUT
GM
—
VDD-0.15
—
V
Output load current
0.5
20
60
280
100
mA
Gain margin
—
dB
PM
Phase margin
—
deg
nV/√Hz
nV/√Hz
Vn
Voltage noise density (noise floor) 1kHz
Voltage noise density (noise floor) 10kHz
—
Vn
—
Figure 19. Typical Open Loop Gain vs. Frequency [TBD]
Figure 20. Typical Phase vs. Frequency [TBD]
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
51
Preliminary
Peripheral operating requirements and behaviors
6.6.6 Transimpedance amplifier electrical specifications — limited
range
Table 34. TRIAMP limited range operating requirements
Symbol
VDDA
Description
Min.
Max.
Unit
Notes
Supply voltage
2.4
0.1
0
3.3
V
V
C
pf
Ω
VIN
TA
Input voltage range
Temperature
VDDA-1.4
50
CL
Output load capacitance
Output resistance
100
ROUT
1500
Table 35. TRIAMP limited range operating behaviors
Symbol Description
Min.
Typ.
Max.
TBD
Unit
Notes
VOS
αVOS
IOS
Input offset voltage
—
—
—
—
3
mV
Input offset voltage temperature coefficient
Input offset current
4
TBD
TBD
TBD
—
μV/C
pA
300
300
IBIAS
|XIN|
CMRR
PSRR
SR
Input bias current
pA
AC input impedance (fIN=100kHz)
Input common mode rejection ratio
Power supply rejection ratio
500
—
—
70
70
—
—
—
—
—
—
69
MΩ
dB
—
—
—
dB
Slew rate (ΔVIN=100mV) — Low-power mode
Slew rate (ΔVIN=100mV) — High speed mode
0.1
1
—
V/μs
V/μs
MHz
MHz
dB
SR
—
GBW
GBW
AV
Unity gain bandwidth — Low-power mode 50pF 0.15
—
Unity gain bandwidth — High speed mode 50pF
DC open-loop voltage gain
Gain margin
1
—
80
30
60
—
GM
—
dB
PM
Phase margin
—
deg
6.6.7 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
—
105
100
°C
nF
Output load capacitance
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 37. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
TBD
1.2
TBD
V
nominal VDDA and temperature=25C
Voltage reference output with factory trim
Voltage reference output user trim
Voltage reference trim step
Vout
Vout
TBD
1.198
—
—
—
TBD
1.202
—
V
V
Vstep
Vdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
20
See
Figure 21
Ac
Ibg
Itr
Aging coefficient
—
—
—
—
—
—
—
—
TBD
TBD
1.1
ppm/year
Bandgap only (MODE_LV = 00) current
Tight-regulation buffer (MODE_LV =10) current
µA
mA
V
Load regulation (MODE_LV = 10) current =
1.0mA
TBD
Tstup
DC
Buffer startup time
—
—
—
—
—
100
TBD
TBD
µs
mV
dB
Line regulation (power supply rejection)
–60
Table 38. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 39. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory trim
TBD
TBD
V
TBD
Figure 21. Typical output vs.temperature
Figure 22. Typical output vs. VDD
TBD
6.7 Timers
See General switching specifications.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
53
Preliminary
Peripheral operating requirements and behaviors
6.8 Communication interfaces
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 40. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
TBD
TBD
TBD
V
VLGC
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
7
—
10
2.0
13
V
IDP_SRC
IDM_SINK
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
TBD
6.8.3 USB VREG electrical specifications
Table 41. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.
—
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
TBD
μA
Quiescent current — Standby mode, load
current equal zero
—
1
TBD
μA
Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
—
—
500
—
—
nA
μA
TBD
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
54
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 41. USB VREG electrical specifications
(continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.5
2.3
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
1
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Current limitation threshold
185
290
395
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 42. Master mode DSPI timing (low-speed mode)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle time
4 x tBCLK
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
(tSCK/2) - 4
—
—
10
—
—
—
(tSCK/2) - 4
—
-2
15
0
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
55
Preliminary
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 23. DSPI classic SPI timing — master mode
Table 43. Slave mode DSPI timing (low-speed mode)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
6.25
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBCLK
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
15
15
5
15
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 24. DSPI classic SPI timing — slave mode
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
56
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.8.5 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 44. Master mode DSPI timing (high-speed mode)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle time
2 x tBCLK
—
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(tSCK/2) − 2
(tSCK/2) + 2
ns
ns
ns
ns
ns
ns
ns
(tSCK/2) − 2
—
—
8.5
—
—
—
(tSCK/2) − 2
—
−2
TBD
0
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 25. DSPI classic SPI timing — master mode
Table 45. Slave mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBCLK
DS10
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2 + 2
ns
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
57
Peripheral operating requirements and behaviors
Table 45. Slave mode DSPI timing (high-speed mode) (continued)
Num
DS11
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK to DSPI_SOUT valid
Min.
—
0
Max.
TBD
—
Unit
ns
DSPI_SCK to DSPI_SOUT invalid
ns
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
2
—
ns
7
—
ns
—
—
14
ns
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 26. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.6
See General switching specifications.
6.8.7 UART switching specifications
See General switching specifications.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
58
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.8.8 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 46. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
0
0
400
25
20
400
—
—
3
kHz
MHz
MHz
kHz
ns
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
ns
Clock rise time
—
—
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
tOD SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
ns
SD7
SD8
tTHL
tTHL
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 27. SDHC timing
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
59
Peripheral operating requirements and behaviors
I2S switching specifications
6.8.9
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
I2S master mode timing
Table 47.
Num
Description
Min.
Max.
Unit
V
Operating voltage
I2S_MCLK cycle time
2.7
2 x tSYS
45%
5 x tSYS
45%
—
3.6
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
-2.5
—
—
15
I2S_BCLK to I2S_TXD invalid
-3
—
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
20
—
0
—
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 28. I2S timing — master mode
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
60
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
I2S slave mode timing
Table 48.
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
S11
S12
S13
S14
S15
S16
S17
S18
I2S_BCLK cycle time (input)
8 x tSYS
—
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
45%
10
3
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
—
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 29. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 49. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE
fREFmax
fELEmax
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
Electrode oscillator frequency
1
20
5.5
0.5
500
TBD
TBD
pF
1
—
—
MHz
MHz
Table continues on the next page...
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
61
Dimensions
Table 49. TSI electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
CREF
VDELTA
IREF
Internal reference capacitor
TBD
1
TBD
pF
Oscillator delta voltage
TBD
TBD
TBD
—
600
1
TBD
TBD
TBD
TBD
TBD
TBD
—
mV
μA
Reference oscillator current source base current
Electrode oscillator current source base current
Electrode capacitance measurement precision
Electrode capacitance measurement precision
2
2
3
4
5
6
IELE
1
μA
Pres5
Pres20
TBD
TBD
TBD
0.25
%
—
%
Pres100 Electrode capacitance measurement precision
—
%
MaxSens2 Maximum sensitivity @ 20 pF electrode
0
0.003
fF/count
MaxSens Maximum sensitivity
0.003
—
—
—
—
16
fF/count
bits
7
8
Res
Resolution
TCon20
Response time @ 20 pF
8
15
25
μs
ITSI_RUN Current added in run mode
ITSI_LP Low power mode current adder
—
TBD
1
—
μA
—
TBD
μA
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
3. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
4. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
5. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
6. Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
NSCN = 2; Iext = 16 (EXTCHRG = 15).
7. Typical value depends on the configuration used.
8. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
121-pin MAPBGA
Then use this document number
TBD
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
62
Freescale Semiconductor, Inc.
Pinout
8 Pinout
8.1 K50 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
•
•
PTE0
ADC1_SE4a ADC1_SE4a PTE0
ADC1_SE5a ADC1_SE5a PTE1
ADC1_SE6a ADC1_SE6a PTE2
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
I2C1_SDA
I2C1_SCL
PTE1
PTE2
UART1_CTS SDHC0_DCL
_b
K
•
PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS SDHC0_CM
_b
D
•
•
•
PTE4
PTE5
PTE6
DISABLED
DISABLED
DISABLED
PTE4
PTE5
PTE6
SPI1_PCS0
SPI1_PCS2
SPI1_PCS3
UART3_TX
UART3_RX
SDHC0_D3
SDHC0_D2
UART3_CTS I2S0_MCLK
_b
I2S0_CLKIN
•
•
•
•
•
•
•
VDD
VDD
VDD
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DP1/
OP0_DP0
ADC0_DP1/
OP0_DP0
•
•
ADC0_DM1/ ADC0_DM1/ ADC0_DM1/
OP0_DM0
OP0_DM0
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DP1/
OP1_DP0/
OP1_DM1
•
•
ADC1_DM1/ ADC1_DM1/ ADC1_DM1/
OP1_DM0
OP1_DM0
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
•
•
PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3
PGA0_DM/
PGA0_DM/
ADC1_DM3
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
63
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
PGA1_DM/
PGA1_DM/
PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3
ADC0_DM3
ADC0_DM3
•
•
•
•
•
VDDA
VDDA
VDDA
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
OP1_OUT/
CMP2_IN2/
OP1_OUT/
CMP2_IN2/
OP1_OUT/
CMP2_IN2/
ADC0_SE22/ ADC0_SE22/ ADC0_SE22/
OP0_DP2/
OP1_DP2
OP0_DP2/
OP1_DP2
OP0_DP2/
OP1_DP2
•
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
OP0_OUT/
CMP1_IN2/
OP0_OUT/
CMP1_IN2/
OP0_OUT/
CMP1_IN2/
ADC0_SE21/ ADC0_SE21/ ADC0_SE21/
OP0_DP1/
OP1_DP1
OP0_DP1/
OP1_DP1
OP0_DP1/
OP1_DP1
•
•
VREF_OUT/ VREF_OUT
CMP1_IN5/
CMP0_IN5/
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
ADC1_SE18
TRI0_OUT/
OP1_DM2
TRI0_OUT/
OP1_DM2
TRI0_OUT/
OP1_DM2
•
•
•
•
•
TRI0_DM
TRI0_DP
TRI1_DM
TRI1_DP
TRI0_DM
TRI0_DP
TRI1_DM
TRI1_DP
TRI1_OUT
TRI0_DM
TRI0_DP
TRI1_DM
TRI1_DP
TRI1_OUT/
CMP2_IN5/
ADC1_SE22
TRI1_OUT/
CMP2_IN5/
ADC1_SE22
•
•
DAC0_OUT/ DAC0_OUT
CMP1_IN3/
ADC0_SE23/
OP0_DP4/
OP1_DP4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/
OP0_DP4/
OP1_DP4
DAC1_OUT/ DAC1_OUT
CMP2_IN3/
ADC1_SE23/
OP0_DP5/
OP1_DP5
DAC1_OUT/
CMP2_IN3/
ADC1_SE23/
OP0_DP5/
OP1_DP5
•
•
•
•
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTA0
JTAG_TCLK/ TSI0_CH1
SWD_CLK/
PTA0
UART0_CTS FTM0_CH5
_b
JTAG_TCLK/ EZP_CLK
SWD_CLK
EZP_CLK
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
64
Freescale Semiconductor, Inc.
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
•
PTA2
JTAG_TDO/
TRACE_SW
O/EZP_DO
PTA2
JTAG_TDO/
TRACE_SW
O
EZP_DO
•
•
•
•
•
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
CMP2_IN0
CMP2_IN1
PTA3
UART0_RTS FTM0_CH0
_b
JTAG_TMS/
SWD_DIO
PTA4
NMI_b/
EZP_CS_b
PTA4
FTM0_CH1
FTM1_CH0
FTM1_CH1
NMI_b
EZP_CS_b
PTA12
PTA13
PTA14
CMP2_IN0
CMP2_IN1
DISABLED
PTA12
PTA13
PTA14
PTA15
I2S0_TXD
FTM1_QD_P
HA
I2S0_TX_FS FTM1_QD_P
HB
SPI0_PCS0
SPI0_SCK
UART0_TX
UART0_RX
I2S0_TX_BC
LK
•
•
•
•
PTA15
VDD
DISABLED
VDD
I2S0_RXD
VDD
VSS
VSS
VSS
PTA18
EXTAL
EXTAL
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN
0
•
PTA19
XTAL
XTAL
FTM_CLKIN
1
LPT0_ALT1
•
•
•
•
•
•
•
•
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
PTB0
RESET_b
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
FB_A29
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
/ADC0_SE8/ /ADC0_SE8/ PTB0
ADC1_SE8/
TSI0_CH0
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
FTM1_QD_P
HA
ADC1_SE8/
TSI0_CH0
•
•
•
PTB1
PTB2
PTB3
/ADC0_SE9/ /ADC0_SE9/ PTB1
ADC1_SE9/
TSI0_CH6
FTM1_QD_P
HB
ADC1_SE9/
TSI0_CH6
/
/
PTB2
PTB3
UART0_RTS
_b
FTM0_FLT3
FTM0_FLT0
ADC0_SE12/ ADC0_SE12/
TSI0_CH7
TSI0_CH7
/
/
UART0_CTS
_b
ADC0_SE13/ ADC0_SE13/
TSI0_CH8 TSI0_CH8
•
•
•
PTB6
PTB7
PTB8
/ADC1_SE12 /ADC1_SE12 PTB6
/ADC1_SE13 /ADC1_SE13 PTB7
PTB8
FB_AD23
FB_AD22
FB_AD21
UART3_RTS
_b
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
65
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
PTB9
PTB9
SPI1_PCS1
UART3_CTS
_b
FB_AD20
•
•
•
•
•
•
PTB10
PTB11
VSS
/ADC1_SE14 /ADC1_SE14 PTB10
/ADC1_SE15 /ADC1_SE15 PTB11
SPI1_PCS0
SPI1_SCK
UART3_RX
UART3_TX
FB_AD19
FB_AD18
FTM0_FLT1
FTM0_FLT2
VSS
VSS
VDD
VDD
VDD
PTB16
PTB17
/TSI0_CH9
/TSI0_CH10
/TSI0_CH9
/TSI0_CH10
PTB16
PTB17
SPI1_SOUT
SPI1_SIN
UART0_RX
UART0_TX
FB_AD17
FB_AD16
EWM_IN
EWM_OUT_
b
•
•
PTB18
PTB19
/TSI0_CH11
/TSI0_CH12
/TSI0_CH11
/TSI0_CH12
PTB18
PTB19
FTM2_CH0
FTM2_CH1
I2S0_TX_BC FB_AD15
LK
FTM2_QD_P
HA
I2S0_TX_FS FB_OE_b
FTM2_QD_P
HB
•
•
•
•
•
PTB20
PTB21
PTB22
PTB23
PTC0
PTB20
PTB21
PTB22
PTB23
PTC0
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD31
FB_AD30
FB_AD29
FB_AD28
CMP0_OUT
CMP1_OUT
CMP2_OUT
SPI0_PCS5
/
/
SPI0_PCS4
PDB0_EXTR I2S0_TXD
G
FB_AD14
FB_AD13
FB_AD12
ADC0_SE14/ ADC0_SE14/
TSI0_CH13
TSI0_CH13
•
•
PTC1
PTC2
/
/
PTC1
PTC2
SPI0_PCS3
SPI0_PCS2
UART1_RTS FTM0_CH0
_b
ADC0_SE15/ ADC0_SE15/
TSI0_CH14
TSI0_CH14
/
/
UART1_CTS FTM0_CH1
_b
ADC0_SE4b/ ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
CMP1_IN0/
TSI0_CH15
•
•
•
•
•
•
•
PTC3
VSS
/CMP1_IN1
VSS
/CMP1_IN1
VSS
PTC3
SPI0_PCS1
UART1_RX
FTM0_CH2
FB_CLKOUT
VDD
NC
VDD
VDD
PTC4
PTC5
PTC6
PTC4
PTC5
PTC6
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART1_TX
FTM0_CH3
LPT0_ALT2
FB_AD11
FB_AD10
FB_AD9
CMP1_OUT
CMP0_OUT
/CMP0_IN0
/CMP0_IN0
PDB0_EXTR
G
•
•
PTC7
PTC8
/CMP0_IN1
/
/CMP0_IN1
/
PTC7
PTC8
SPI0_SIN
FB_AD8
I2S0_MCLK
I2S0_CLKIN FB_AD7
ADC1_SE4b/ ADC1_SE4b/
CMP0_IN2
CMP0_IN2
•
•
•
PTC9
/
/
PTC9
I2S0_RX_BC FB_AD6
LK
FTM2_FLT0
ADC1_SE5b/ ADC1_SE5b/
CMP0_IN3
CMP0_IN3
PTC10
PTC11
/
/
PTC10
I2C1_SCL
I2C1_SDA
I2S0_RX_FS FB_AD5
ADC1_SE6b/ ADC1_SE6b/
CMP0_IN4 CMP0_IN4
/ADC1_SE7b /ADC1_SE7b PTC11
I2S0_RXD
FB_RW_b
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
66
Freescale Semiconductor, Inc.
Pinout
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
PTC12
PTC13
PTC12
UART4_RTS
_b
FB_AD27
FB_AD26
•
PTC13
UART4_CTS
_b
•
•
•
•
•
PTC14
PTC15
VSS
PTC14
PTC15
UART4_RX
UART4_TX
FB_AD25
FB_AD24
VSS
VDD
VSS
VDD
VDD
PTC16
PTC16
PTC17
PTC18
UART3_RX
UART3_TX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16
_BLS15_8_b
•
•
PTC17
PTC18
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24
_BLS7_0_b
UART3_RTS
_b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
•
•
•
PTC19
PTD0
PTD1
PTC19
PTD0
UART3_CTS
_b
FB_CS3_b/
FB_BE7_0_
BLS31_24_b
FB_TA_b
SPI0_PCS0
SPI0_SCK
UART2_RTS
_b
FB_ALE/
FB_CS1_b/
FB_TS_b
/ADC0_SE5b /ADC0_SE5b PTD1
UART2_CTS
_b
FB_CS0_b
•
•
•
PTD2
PTD3
PTD4
PTD2
PTD3
PTD4
SPI0_SOUT
SPI0_SIN
UART2_RX
UART2_TX
FB_AD4
FB_AD3
FB_AD2
SPI0_PCS1
UART0_RTS FTM0_CH4
_b
EWM_IN
•
PTD5
/ADC0_SE6b /ADC0_SE6b PTD5
/ADC0_SE7b /ADC0_SE7b PTD6
SPI0_PCS2
SPI0_PCS3
UART0_CTS FTM0_CH5
_b
FB_AD1
FB_AD0
EWM_OUT_
b
•
•
•
•
•
•
PTD6
VSS
UART0_RX
FTM0_CH6
FTM0_FLT0
VSS
VSS
PTD7
PTD8
PTD9
PTD10
PTD7
PTD8
PTD9
PTD10
CMT_IRO
I2C0_SCL
I2C0_SDA
UART0_TX
UART5_RX
UART5_TX
FTM0_CH7
FTM0_FLT1
FB_A16
DISABLED
DISABLED
DISABLED
FB_A17
UART5_RTS
_b
FB_A18
•
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_CTS SDHC0_CLK
FB_A19
_b
IN
•
•
•
PTD12
PTD13
PTD14
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
SPI2_SCK
SPI2_SOUT
SPI2_SIN
SDHC0_D4
SDHC0_D5
SDHC0_D6
FB_A20
FB_A21
FB_A22
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
67
Revision History
121
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
•
PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
FB_A23
8.2 K50 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
NOTE
The 121 MAPBGA ballmap assignments are currently being
developed.
9 Revision History
The following table provides a revision history for this document.
Table 50. Revision History
Rev. No.
Date
3/2011
3/2011
3/2011
Substantial Changes
2
3
4
Initial public revision
Added sections that were inadvertently removed in previous revision
Reworded IIC footnote in "Voltage and Current Operating Requirements"
table.
Added paragraph to "Peripheral operating requirements and behaviors"
section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals"
section.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
68
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Document Number: K50P121M100SF2
Rev. 4, 3/2011
Preliminary
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