MK60FN1M0VLQ15R [NXP]
RISC MICROCONTROLLER;
| 型号： | MK60FN1M0VLQ15R |
| 厂家： | 
NXP |
| 描述： | RISC MICROCONTROLLER 外围集成电路 |
| 文件： | 总94页 (文件大小：1455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number K60P144M150SF3
Rev 5, 10/2013
Freescale Semiconductor
Data Sheet: Technical Data
K60P144M150SF3
K60 Sub-Family
Supports the following:
MK60FX512VLQ15,
MK60FN1M0VLQ15,
MK60FX512VMD15,
MK60FN1M0VMD15
Key features
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES,
AES, MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per
chip
• Performance
– Up to 150 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Human-machine interface
– Low-power hardware touch sensor interface
(TSI)
• Memories and memory interfaces
– Up to 1024 KB program flash memory on non-
FlexMemory devices
– General-purpose input/output
• Analog modules
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– NAND flash controller interface
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6-
bit DAC and programmable reference input
– Voltage reference
• Timers
• Clocks
– Programmable delay block
– Two 8-channel motor control/general purpose/
PWM timers
– Two 2-channel quadrature decoder/general
purpose timers
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to
128 request sources
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2013 Freescale Semiconductor, Inc.
• Communication interfaces
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB high-/full-/low-speed On-the-Go controller with on-chip high speed transceiver
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– USB Device Charger detect
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– Two I2S modules
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Table of Contents
1 Ordering parts...........................................................................5
5.4.2
Thermal attributes...............................................24
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3 Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
5.5 Power sequencing.............................................................24
6 Peripheral operating requirements and behaviors....................25
6.1 Core modules....................................................................25
6.1.1
6.1.2
Debug trace timing specifications.......................25
JTAG electricals..................................................26
6.2 System modules................................................................29
6.3 Clock modules...................................................................29
6.3.1
6.3.2
6.3.3
MCG specifications.............................................29
Oscillator electrical specifications.......................31
32 kHz oscillator electrical characteristics..........33
6.4 Memories and memory interfaces.....................................34
6.4.1
6.4.2
6.4.3
6.4.4
Flash (FTFE) electrical specifications.................34
EzPort switching specifications...........................38
NFC specifications..............................................39
Flexbus switching specifications.........................42
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................9
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................12
5.1 AC electrical characteristics..............................................12
5.2 Nonswitching electrical specifications...............................12
6.5 Security and integrity modules..........................................45
6.6 Analog...............................................................................45
6.6.1
6.6.2
6.6.3
6.6.4
ADC electrical specifications..............................45
CMP and 6-bit DAC electrical specifications......53
12-bit DAC electrical characteristics...................55
Voltage reference electrical specifications..........58
6.7 Timers................................................................................59
6.8 Communication interfaces.................................................59
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
Ethernet switching specifications........................59
USB electrical specifications...............................61
USB DCD electrical specifications......................61
USB VREG electrical specifications...................62
ULPI timing specifications...................................62
CAN switching specifications..............................63
DSPI switching specifications (limited voltage
range).................................................................64
DSPI switching specifications (full voltage
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Voltage and current operating requirements......12
LVD and POR operating requirements...............13
Voltage and current operating behaviors............14
Power mode transition operating behaviors.......16
Power consumption operating behaviors............17
EMC radiated emissions operating behaviors....20
Designing with radiated emissions in mind.........20
Capacitance attributes........................................21
6.8.8
6.8.9
range).................................................................65
Inter-Integrated Circuit Interface (I2C) timing.....67
5.3 Switching specifications.....................................................21
5.3.1
5.3.2
Device clock specifications.................................21
General switching specifications.........................22
6.8.10 UART switching specifications............................68
6.8.11 SDHC specifications...........................................68
6.8.12 I2S/SAI switching specifications.........................69
6.9 Human-machine interfaces (HMI)......................................76
5.4 Thermal specifications.......................................................23
5.4.1 Thermal operating requirements.........................23
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6.9.1
TSI electrical specifications................................76
8.2 K60 Signal Multiplexing and Pin Assignments..................78
8.3 K61 Signal Multiplexing and Pin Assignments..................84
8.4 K60 pinouts.......................................................................90
9 Revision History........................................................................92
7 Dimensions...............................................................................77
7.1 Obtaining package dimensions.........................................77
8 Pinout........................................................................................77
8.1 Pins with active pull control after reset..............................77
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Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK60 and MK60
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
• K60
Key attribute
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 512 = 512 KB
• 1M0 = 1 MB
Table continues on the next page...
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Terminology and guidelines
Field
Description
Values
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 15 = 150 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK60FN1M0VLQ15
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
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Terminology and guidelines
3.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
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Terminology and guidelines
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
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Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
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Ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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Ratings
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
1
2
3
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage1
Digital supply current
IDD
300
5.5
mA
V
VDIO
Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2
–0.3
VAIO
Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3
VDD + 0.3
V
ID
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
VDD – 0.3
–0.3
25
VDD + 0.3
3.63
mA
V
VDDA
VUSB0_DP
VUSB1_DP
VUSB0_DM
VUSB1_DM
VREGIN
VBAT
USB0_DP input voltage
V
USB1_DP input voltage
–0.3
3.63
V
USB0_DM input voltage
–0.3
3.63
V
USB1_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
1. It applies for all port pins.
Freescale Semiconductor, Inc.
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General
2. It covers digital pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
Table continues on the next page...
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General
Notes
Table 1. Voltage and current operating requirements (continued)
Symbol
VBAT
Description
Min.
Max.
Unit
RTC battery supply voltage
Input high voltage (digital pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
1.71
3.6
V
VIH
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage (digital pins)
• 2.7 V ≤ VDD ≤ 3.6 V
—
—
0.35 × VDD
0.3 × VDD
V
V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
IICDIO
Input hysteresis (digital pins)
0.06 × VDD
-5
—
—
V
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
mA
IICAIO
Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC
injection current — single pin
mA
-5
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
V
4
VDD voltage required to retain RAM
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
—
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
2. Open drain outputs must be pulled to VDD.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
Table continues on the next page...
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General
Table 2. LVD and POR operating requirements (continued)
Symbol Description
• Level 3 falling (LVWV=10)
Min.
Typ.
Max.
Unit
Notes
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
Internal low power oscillator period
factory trimmed
0.97
900
1.00
1.03
V
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description
VOH Output high voltage — high drive strength
Min.
Typ.
Max.
Unit
Notes
—
—
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
—
—
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
Output high current total for all ports
—
—
—
—
100
100
mA
mA
IOHT_io60 Output high current total for fast digital ports
VOL Output low voltage — high drive strength
—
—
0.5
V
Table continues on the next page...
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General
Notes
Table 4. Voltage and current operating behaviors (continued)
Symbol Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
Min.
Typ.
Max.
Unit
—
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1 mA
—
—
—
—
0.5
0.5
V
V
IOLT
Output low current total for all ports
—
—
—
—
100
100
mA
mA
IOLT_io60 Output low current total for fast digital ports
IINA
Input leakage current, analog pins and digital
pins configured as analog inputs
1,
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
—
—
—
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
IIND
Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
2,
• All digital pins
—
0.002
0.5
μA
• VIN = VDD
—
—
0.002
0.004
0.5
1
μA
μA
• All digital pins except PTD7
• PTD7
IIND
Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
2, 3,
—
—
—
—
18
12
8
26
19
13
6
μA
μA
μA
μA
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
3
IIND
Input leakage current, digital pins
• VDD < VIN < 5.5 V
2, 3
2, 5
—
1
50
μA
ZIND
Input impedance examples, digital pins
• VDD = 3.6 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
RPU
RPD
Internal pullup resistors
20
20
—
—
50
50
kΩ
kΩ
6
7
Internal pulldown resistors
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
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General
2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See
Figure 1.
5. Measured at VDD supply voltage = VDD min and Vinput = VSS
6. Measured at VDD supply voltage = VDD min and Vinput = VDD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 150 MHz
• Bus clock = 75 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
1
μs
—
—
300
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
1.7 V / (VDD
slew rate)
—
—
—
160
114
114
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
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General
Notes
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
—
5.0
μs
• LLS → RUN
—
—
5
μs
μs
• VLPS → RUN
• STOP → RUN
4.8
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
—
—
59.6
59.6
180
185
mA
mA
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
—
—
89.9
89.9
205
210
mA
mA
• @ 1.8V
• @ 3.0V
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
40.9
19.6
95
65
mA
mA
2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
1.3
3.0
7.5
3.8
27
42
mA
mA
mA
• @ 70°C
• @ 105°C
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
—
—
1.4
2.2
32
38
22
mA
mA
mA
5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
IDD_VLPW Very-low-power wait mode current at 3.0 V
0.926
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
0.25
0.85
2.4
1.3
7.6
mA
mA
mA
• @ –40 to 25°C
• @ 70°C
12.54
• @ 105°C
Table continues on the next page...
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General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_LLS Low leakage stop mode current at 3.0 V
—
—
—
0.25
0.85
2.4
1.3
7.6
mA
mA
mA
• @ –40 to 25°C
• @ 70°C
12.54
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
6
—
—
—
5.6
30.1
120.8
20
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
137
246
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
—
3.2
14
40
60
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
11.8
51.2
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
2.8
8.7
12
29
43
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
39.3
• @ 105°C
IDD_VBAT Average current when CPU is not accessing RTC
registers at 3.0 V
7
—
—
—
0.91
1.5
1.1
1.85
4.3
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
4.3
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
4. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
7. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies.
• USB regulator disabled
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• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
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General
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
VRE3
VRE4
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
0.15–50
50–150
21
24
29
28
dBμV
dBμV
dBμV
dBμV
, ,
150–500
500–1000
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
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General
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
Input capacitance: analog pins
Input capacitance: digital pins
Input capacitance: fast digital pins
7
7
9
pF
pF
pF
CIN_D
—
CIN_D_io60
—
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
150
—
MHz
MHz
fSYS_USBFS
System and core clock when Full Speed USB in
operation
20
fSYS_USBHS
fENET
System and core clock when High Speed USB in
operation
60
—
MHz
MHz
System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
5
—
—
75
50
25
25
50
—
—
—
—
fBUS
FB_CLK
fFLASH
Bus clock
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
fLPTMR
LPTMR clock
VLPR mode1
System and core clock
Bus clock
fSYS
fBUS
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
fLPTMR
FlexBus clock
Flash clock
4
0.5
4
LPTMR clock
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
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General
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
ns
ns
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
3
3
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
14
8
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
Port rise and fall time (low drive strength)
• Slew disabled
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
14
8
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
tio50
Port rise and fall time (high drive strength)
• Slew disabled
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
7
3
ns
ns
• Slew enabled
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
28
14
ns
ns
tio50
Port rise and fall time (low drive strength)
• Slew disabled
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Table 10. General switching specifications (continued)
Symbol
Description
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
Min.
Max.
Unit
Notes
—
18
ns
—
—
9
ns
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
48
24
ns
ns
—
—
6
tio60
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
6
3
ns
ns
—
—
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
28
14
ns
ns
—
—
7
tio60
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
18
6
ns
ns
—
—
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
48
24
ns
ns
—
—
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
6. 25 pF load
7. 15 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Die junction temperature
Ambient temperature
TA
105
°C
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General
5.4.2 Thermal attributes
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
45
36
36
30
24
50
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
30
41
27
17
Single-layer
(1s)
RθJMA
RθJMA
RθJB
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
—
Thermal
resistance,
junction to
board
—
—
RθJC
Thermal
resistance,
junction to case
9
2
10
2
°C/W
°C/W
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
5.5 Power sequencing
Voltage supplies must be sequenced in the proper order to avoid damaging internal
diodes. There is no limit on how long after one supply powers up before the next supply
must power up. Note that VDD and VDD_INT can use the same power source.
The power-up sequence is:
1. VDD
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2. VDD_INT
3. VDDA
4. VDD_DDR
The power-down sequence is the reverse:
1. VDD_DDR
2. VDDA
3. VDD_INT
4. VDD
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
3
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
2
ns
Figure 5. TRACE_CLKOUT specifications
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Peripheral operating requirements and behaviors
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
2.4
—
—
8
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 14. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
MHz
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Table 14. JTAG full voltage range electricals (continued)
Symbol
Description
• Boundary Scan
Min.
Max.
10
Unit
0
• JTAG and CJTAG
• Serial Wire Debug
0
0
20
40
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
2.4
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
25
25
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
22.1
22.1
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 7. Test clock input timing
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Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 9. Test Access Port timing
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Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 10. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
—
0.2
4.5
0.5
—
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
fintf_ft
fintf_t
floc_low
floc_high
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
kHz
kHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
—
—
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
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Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
4
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL0,1
fpll_ref
PLL reference frequency range
8
180
90
90
—
—
—
16
360
180
180
—
MHz
MHz
fvcoclk_2x VCO output frequency
fvcoclk
fvcoclk_90 PLL quadrature output frequency
Ipll PLL0 operating current
PLL output frequency
—
—
MHz
MHz
2.8
4.7
2.3
mA
mA
mA
• VCO @ 180 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 22)
Ipll
PLL0 operating current
6
6
6
—
—
—
—
—
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
Ipll
PLL1 operating current
• VCO @ 180 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 22)
Ipll
PLL1 operating current
—
—
3.6
—
mA
s
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
tpll_lock
Lock detector detection time
PLL period jitter (RMS)
100 × 10-6
+ 1075(1/
fpll_ref
)
Jcyc_pll
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Table 15. MCG specifications (continued)
Symbol Description
• fvco = 180 MHz
Min.
Typ.
Max.
Unit
Notes
—
100
—
ps
• fvco = 360 MHz
—
75
—
ps
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 180 MHz
—
—
600
300
—
—
ps
ps
• fvco = 360 MHz
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6. Excludes any oscillator currents that are also consuming power while PLL is in operation.
6.3.2 Oscillator electrical specifications
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
—
Typ.
—
Max.
—
Unit
Notes
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
2, 3
2
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
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Table 17. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
—
8
MHz
1
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
8
—
32
MHz
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
60
60
—
MHz
%
2, 3
,
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
1000
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
500
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
Parasitical capacitance of EXTAL32 and XTAL32
Peak-to-peak amplitude of oscillation
100
5
MΩ
pF
V
Cpara
—
7
1
Vpp
—
0.6
—
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
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6.3.3.2 32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
vec_extal32 Externally provided input clock amplitude
700
VBAT
mV
3
1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm8
Program Phrase high-voltage time
thversscr Erase Flash Sector high-voltage time
thversblk128k Erase Flash Block high-voltage time for 128 KB
thversblk256k Erase Flash Block high-voltage time for 256 KB
—
13
113
ms
ms
ms
—
104
208
1808
3616
1
1
—
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk128k
trd1blk256k
• 128 KB data flash
—
—
—
—
0.5
1.0
ms
ms
• 256 KB program flash
trd1sec4k Read 1s Section execution time (4 KB flash)
tpgmchk Program Check execution time
—
—
—
—
100
80
μs
μs
1
1
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Table 21. Flash command timing specifications (continued)
Symbol Description
trdrsrc Read Resource execution time
tpgm8
Min.
—
Typ.
—
Max.
40
Unit
μs
Notes
Program Phrase execution time
Erase Flash Block execution time
• 128 KB data flash
—
70
150
μs
2
tersblk128k
tersblk256k
—
—
110
220
925
ms
ms
• 256 KB program flash
1850
tersscr
Erase Flash Sector execution time
—
—
15
20
115
—
ms
ms
tpgmsec4k Program Section execution time (4KB flash)
Read 1s All Blocks execution time
trd1allx
trd1alln
• FlexNVM devices
—
—
—
—
3.4
3.4
ms
ms
• Program flash only devices
trdonce
Read Once execution time
—
—
—
—
—
70
30
—
μs
μs
ms
μs
1
tpgmonce Program Once execution time
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
650
—
5600
30
2
1
tvfykey
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
• control code 0x02
• control code 0x04
• control code 0x08
Program Partition for EEPROM execution time
• 64 KB FlexNVM
tpgmpart64k
tpgmpart256k
—
—
235
240
—
—
ms
ms
• 256 KB FlexNVM
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram64k
tsetram128k
tsetram256k
—
—
—
—
205
1.6
2.7
4.8
—
μs
ms
ms
ms
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
2.5
3.8
6.2
teewr8bers Byte-write to erased FlexRAM location execution
time
—
140
225
μs
3
Byte-write to FlexRAM execution time:
teewr8b64k
teewr8b128k
teewr8b256k
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
400
450
525
1700
1800
2000
μs
μs
μs
teewr16bers 16-bit write to erased FlexRAM location
execution time
—
140
225
μs
16-bit write to FlexRAM execution time:
teewr16b64k
—
400
1700
μs
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol Description
teewr16b128k • 64 KB EEPROM backup
teewr16b256k
Min.
Typ.
Max.
Unit
Notes
—
450
1800
μs
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
525
2000
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
180
275
μs
32-bit write to FlexRAM execution time:
teewr32b64k
teewr32b128k
teewr32b256k
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
475
525
600
1850
2000
2200
μs
μs
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current
adder during high
voltage flash
programming
operation
—
3.5
7.5
mA
IDD_ERS
Average current
adder during high
voltage flash erase
operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
10 K
100
50 K
2
FlexRAM as EEPROM
Table continues on the next page...
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Table 23. NVM reliability specifications (continued)
Symbol Description
Min.
5
Typ.1
Max.
—
Unit
years
years
cycles
Notes
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
nnvmcycee Cycling endurance for EEPROM backup
Write endurance
50
20
100
50 K
—
20 K
—
2
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
70 K
630 K
2.5 M
10 M
175 K
1.6 M
6.4 M
25 M
—
—
—
—
writes
writes
writes
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycee
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
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• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition
command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
Figure 11. EEPROM backup writes to FlexRAM
6.4.2 EzPort switching specifications
Table 24. EzPort switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
—
2 x tEZP_CK
5
fSYS/8
—
MHz
ns
—
ns
Table continues on the next page...
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Table 24. EzPort switching specifications (continued)
Num
EP4
EP5
EP6
EP7
EP8
EP9
Description
EZP_CK high to EZP_CS input invalid (hold)
Min.
Max.
Unit
ns
5
—
—
—
16
—
12
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
2
5
ns
ns
—
0
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
ns
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 12. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
Tinput clock
TNFC = TL + TH
=
SCALER
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Peripheral operating requirements and behaviors
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
=
SCALER
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means TH = TL. In case the reciprocal of SCALER is not an integer:
TNFC
TL = (1 + SCALER / 2) x
2
TNFC
TH = (1 – SCALER / 2) x
2
For example, if SCALER is 0.2, then TH = TL = TNFC/2.
TNFC
TH TL
However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC
.
TNFC
TH TL
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 25. NFC specifications
Num
tCLS
tCLH
tCS
Description
Min.
2TH + TL – 1
TH + TL – 1
2TH + TL – 1
TH + TL
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NFC_CLE setup time
NFC_CLE hold time
NFC_CEn setup time
NFC_CEn hold time
NFC_WP pulse width
NFC_ALE setup time
NFC_ALE hold time
Data setup time
—
—
tCH
—
tWP
tALS
tALH
tDS
TL – 1
—
2TH + TL
TH + TL
—
—
TL – 1
—
tDH
Data hold time
TH – 1
—
tWC
tWH
Write cycle time
TH + TL – 1
TH – 1
—
NFC_WE hold time
—
Table continues on the next page...
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Table 25. NFC specifications (continued)
Num
tRR
Description
Min.
4TH + 3TL + 90
TL + 1
Max.
—
Unit
ns
Ready to NFC_RE low
NFC_RE pulse width
Read cycle time
tRP
—
ns
tRC
TL + TH – 1
TH – 1
—
ns
tREH
tIS
NFC_RE high hold time
Data input setup time
—
ns
11
—
ns
NFC_CLE
tCLS
tCS
tCLH
tCH
NFC_CEn
NFC_WE
NFC_IOn
tWP
tDS
tDH
Figure 13. Command latch cycle timing
NFC_ALE
NFC_CEn
NFC_WE
NFC_IOn
tALS
tCS
tALH
tCH
tWP
tDS
tDH
address
Figure 14. Address latch cycle timing
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Peripheral operating requirements and behaviors
tCS
tCH
tWC
NFC_CEn
NFC_WE
NFC_IOn
tWP
tDS
tWH
tDH
data
data
data
Figure 15. Write data latch cycle timing
tCH
tRC
tRP
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tREH
tIS
data
data
data
tRR
Figure 16. Read data latch cycle timing in non-fast mode
tCH
tRC
tRP
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tREH
tIS
data
data
data
tRR
Figure 17. Read data latch cycle timing in fast mode
6.4.4 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
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The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 26. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
11.5
—
ns
0.5
8.5
0.5
ns
1
2
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 27. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
13.5
—
ns
0
ns
1
2
13.7
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
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Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 18. FlexBus read timing diagram
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Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 19. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
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Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 28 and Table 29 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 30 and
Table 31.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 28. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
Delta to VSS (VSS – VSSA
)
0
2
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
CADIN
Input capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
3
4
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
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Peripheral operating requirements and behaviors
Table 28. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 20. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
IDDA_ADC Supply current
ADC
Conditions1.
Min.
0.215
1.2
Typ.
—
Max.
1.7
Unit
mA
Notes
3
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
2.4
4.0
5.2
3.9
MHz
MHz
MHz
tADACK = 1/
fADACK
asynchronous
fADACK
2.4
6.1
clock source
3.0
7.3
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Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
Typ.
Max.
Unit
Notes
• ADLPC = 0, ADHSC = 0
4.4
6.2
9.5
MHz
• ADLPC = 0, ADHSC = 1
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB
1.4
Differential non-
linearity
• 12-bit modes
—
0.7
–1.1 to
+1.9
LSB3
4
4
–0.3 to 0.5
• <12-bit modes
• 12-bit modes
—
—
0.2
1.0
INL
Integral non-
linearity
–2.7 to
+1.9
LSB3
–0.7 to
+0.5
• <12-bit modes
—
0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB3
LSB3
VADIN
VDDA
=
4
Quantization
error
0.5
ENOB
Effective number 16-bit differential mode
of bits
• Avg = 32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
—
—
-94
-85
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
5
82
78
95
—
—
dB
16-bit single-ended mode
• Avg = 32
90
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
Table continues on the next page...
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Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
Typ.
Max.
Unit
Notes
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
VTEMP25 Temp sensor
voltage
25 °C
6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
3. 1 LSB = (VREFH - VREFL)/2N
4. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
5. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
6. ADC conversion clock < 3 MHz
Figure 21. Typical ENOB vs. ADC_CLK for 16-bit differential mode
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Peripheral operating requirements and behaviors
Figure 22. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 30. 16-bit ADC with PGA operating conditions
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Typ.1
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
V
2, 3
T
T
T
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
V
Input Common
Mode range
RPGAD
Differential input Gain = 1, 2, 4, 8
—
—
—
—
128
64
—
—
—
—
kΩ
IN+ to IN-4
impedance
Gain = 16, 32
Gain = 64
32
RAS
TS
Analog source
resistance
100
Ω
µs
5
6
7
ADC sampling
time
1.25
—
—
—
Crate
ADC conversion ≤ 13 bit modes
18.484
450
Ksps
rate
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
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Table 30. 16-bit ADC with PGA operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
16 bit modes
37.037
—
250
Ksps
8
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
Table 31. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
IDDA_PGA Supply current
Low power
—
420
644
μA
2
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
—
1.54
0.57
—
—
μA
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
G
Gain4
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
0.95
1.9
1
2
1.05
2.1
R
AS < 100Ω
3.8
4
4.2
7.6
8
8.4
15.2
30.0
58.8
16
31.6
63.3
16.6
33.2
67.8
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
4
kHz
kHz
40
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Table 31. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
PSRR
Power supply
rejection ratio
Gain=1
—
-84
—
dB
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
CMRR
VOFS
Common mode
rejection ratio
• Gain=1
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
Input offset
voltage
• Chopping disabled
(ADC_PGA[PGACHPb]
=1)
—
—
2.4
0.2
—
—
mV
mV
Output offset =
VOFS*(Gain+1)
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
TGSW
Gain switching
settling time
—
—
10
µs
5
dG/dT
Gain drift over full
temperature range
• Gain=1
• Gain=64
—
—
—
—
6
31
10
42
ppm/°C
ppm/°C
%/V
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
0.07
0.21
0.31
VDDA from 1.71
to 3.6V
0.14
%/V
EIL
Input leakage
error
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF Maximum
differential input
V
6
signal swing
where VX = VREFPGA × 0.583
SNR
THD
Signal-to-noise
ratio
• Gain=1
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32
Total harmonic
distortion
• Gain=1
85
49
100
95
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32,
fin=100Hz
SFDR
ENOB
Spurious free
dynamic range
• Gain=1
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
• Gain=64
Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
11.6
8.0
13.4
13.6
9.6
—
—
—
bits
bits
bits
16-bit
differential
mode,fin=100Hz
7.2
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Table 31. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
• Gain=64, Average=8
Min.
Typ.1
Max.
Unit
Notes
6.3
9.6
—
bits
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
12.8
11.0
7.9
14.5
14.3
13.8
13.1
12.5
11.5
10.6
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
7.3
6.8
6.8
7.5
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
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Table 32. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
—
Typ.
—
Max.
40
Unit
μs
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
IDAC6b
INL
—
7
—
μA
LSB3
–0.5
–0.3
—
0.5
0.3
DNL
—
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 23. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 24. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 33. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
TA
Desciption
Min.
1.71
1.13
Max.
3.6
Unit
V
Notes
Supply voltage
Reference voltage
Temperature
3.6
V
1
Operating temperature
range of the device
°C
CL
IL
Output load capacitance
Output load current
—
—
100
1
pF
2
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
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Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 34. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
150
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
—
100
15
0.7
—
700
200
30
μA
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
μs
1
1
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
1
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
100
VDACR
8
mV
mV
LSB
LSB
LSB
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
—
2
3
4
Differential non-linearity error — VDACR > 2
V
—
1
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
0.000421
—
—
250
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
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Figure 25. Typical INL error vs. digital code
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Peripheral operating requirements and behaviors
Figure 26. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 35. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
1.71
3.6
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
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Table 36. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ihp
Bandgap only current
—
—
—
—
80
1
µA
mA
mV
High-power buffer current
1
1, 2
ΔVLOAD Load regulation
• current = + 1.0 mA
—
—
2
5
—
—
• current = - 1.0 mA
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 37. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 38. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
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Peripheral operating requirements and behaviors
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 39. MII signal switching specifications
Symbol
—
Description
Min.
—
Max.
25
Unit
MHz
RXCLK frequency
RXCLK pulse width high
MII1
35%
65%
RXCLK
period
RXCLK
period
ns
MII2
RXCLK pulse width low
35%
65%
MII3
MII4
—
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
5
5
—
—
ns
—
25
MHz
MII5
TXCLK pulse width high
35%
65%
TXCLK
period
TXCLK
period
ns
MII6
TXCLK pulse width low
35%
65%
MII7
MII8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
2
—
—
25
ns
MII6
MII5
MII7
TXCLK (input)
MII8
Valid data
TXD[n:0]
TXEN
Valid data
Valid data
TXER
Figure 27. RMII/MII transmit signal timing diagram
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Peripheral operating requirements and behaviors
MII2
MII3
MII1
MII4
RXCLK (input)
RXD[n:0]
RXDV
Valid data
Valid data
Valid data
RXER
Figure 28. RMII/MII receive signal timing diagram
6.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 40. RMII signal switching specifications
Num
—
Description
Min.
—
Max.
50
Unit
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
MHz
RMII1
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RMII7
RMII8
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
4
2
—
—
—
15
ns
ns
ns
ns
4
RMII_CLK to TXD[1:0], TXEN valid
—
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
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Peripheral operating requirements and behaviors
6.8.3 USB DCD electrical specifications
Table 41. USB DCD electrical specifications
Symbol
VDP_SRC
VLGC
Description
Min.
0.5
Typ.
—
Max.
0.7
Unit
V
USB_DP source voltage (up to 250 μA)
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
—
2.0
V
IDP_SRC
IDM_SINK
7
10
13
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.325
6.8.4 USB VREG electrical specifications
Table 42. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
—
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125
186
μA
Quiescent current — Standby mode, load current
equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
3
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
3. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
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6.8.5 ULPI timing specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin
Interface. Control and data timing requirements for the ULPI pins are given in the
following table. These timings apply to synchronous mode only. All timings are
measured with respect to the clock as seen at the USB_CLKIN pin.
Table 43. ULPI timing specifications
Num
Description
Min.
Typ.
Max.
Unit
USB_CLKIN
operating
—
60
—
MHz
frequency
USB_CLKIN duty
cycle
—
—
5
50
16.67
—
—
—
—
—
9.5
—
%
ns
ns
ns
ns
ns
U1
U2
U3
U4
U5
USB_CLKIN clock
period
Input setup (control
and data)
Input hold (control
and data)
1
—
Output valid
(control and data)
—
1
—
Output hold (control
and data)
—
U1
USB_CLKIN
U2
U3
ULPI_DIR/ULPI_NXT
(control input)
ULPI_DATAn (input)
U5
U4
ULPI_STP
(control output)
ULPI_DATAn (output)
Figure 29. ULPI timing diagram
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Peripheral operating requirements and behaviors
6.8.6 CAN switching specifications
See General switching specifications.
6.8.7 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 44. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
15
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 30. DSPI classic SPI timing — master mode
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Table 45. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
15
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
10
—
—
—
14
14
ns
ns
2
ns
7
ns
—
—
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 31. DSPI classic SPI timing — slave mode
6.8.8 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 46. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DSPI_SCK output cycle time
4 x tBUS
—
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 46. Master mode DSPI timing (full voltage range) (continued)
Num
DS2
DS3
Description
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
Min.
Max.
Unit
ns
Notes
(tSCK/2) - 4 (tSCK/2) + 4
(tBUS x 2) −
4
—
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
20.5
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 32. DSPI classic SPI timing — master mode
Table 47. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
19
19
ns
ns
2
ns
7
ns
—
—
ns
ns
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DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
Last data
DSPI_SOUT
Data
Data
DS13
First data
DSPI_SIN
Figure 33. DSPI classic SPI timing — slave mode
6.8.9 Inter-Integrated Circuit Interface (I2C) timing
Table 48. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
Data set-up time
tHD; DAT
tSU; DAT
tr
0
250
—
3.45
—
0
1002
0.91
—
µs
ns
ns
ns
µs
µs
6
3
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
20 +0.1Cb
20 +0.1Cb
0.6
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
4. Cb = total capacitance of the one bus line in pF.
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Peripheral operating requirements and behaviors
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tHD; STA
tSU; STO
S
SR
P
S
tHD; DAT
tHIGH
Figure 34. Timing definition for fast and standard mode devices on the I2C bus
6.8.10 UART switching specifications
See General switching specifications.
6.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 49. SDHC switching specifications over a limited operating voltage
range
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
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Table 50. SDHC switching specifications over the full operating voltage
range
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
—
—
ns
ns
1.3
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 35. SDHC timing
6.8.12 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
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Peripheral operating requirements and behaviors
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.12.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 51. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
80
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 36. I2S/SAI timing — master modes
Table 52. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
S15
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
2
—
ns
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
—
—
21
15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
0
—
—
—
25
ns
ns
ns
ns
4.5
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 37. I2S/SAI timing — slave modes
6.8.12.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 53. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
80
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
15
—
—
ns
ns
ns
0
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K60 Sub-Family, Rev5, 10/2013.
72
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 38. I2S/SAI timing — master modes
Table 54. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
S15
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
2
—
ns
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
—
—
24
20.6
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
0
—
—
—
25
ns
ns
ns
ns
5.8
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
73
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 39. I2S/SAI timing — slave modes
6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 55. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
45%
—
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
45
—
—
ns
ns
ns
-1.6
45
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K60 Sub-Family, Rev5, 10/2013.
74
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 40. I2S/SAI timing — master modes
Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
3
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
63
—
—
—
72
ns
ns
ns
ns
ns
30
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
75
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 41. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 57. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE Target electrode capacitance range
Min.
1.71
1
Typ.
—
20
8
Max.
3.6
500
15
Unit
V
Notes
pF
1
3
2, 4
fREFmax Reference oscillator frequency
fELEmax Electrode oscillator frequency
—
MHz
MHz
pF
—
1
1.8
—
CREF
VDELTA
IREF
Internal reference capacitor
Oscillator delta voltage
—
1
—
600
—
mV
μA
2, 5
2,
Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
—
—
2
3
36
50
• 32 μA setting (REFCHRG = 15)
IELE
Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
μA
2,
—
—
2
36
3
50
• 32 μA setting (EXTCHRG = 15)
Pres5
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
1.46
—
38400
38400
38400
—
fF/count
fF/count
fF/count
fF/count
bits
8
9
Pres20 Electrode capacitance measurement precision
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
—
10
11
0.008
—
Res
Resolution
16
TCon20
Response time @ 20 pF
8
15
25
μs
12
13
ITSI_RUN Current added in run mode
ITSI_LP Low power mode current adder
—
55
—
μA
—
1.3
2.5
μA
K60 Sub-Family, Rev5, 10/2013.
76
Freescale Semiconductor, Inc.
Dimensions
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
7. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
9. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
I
ext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
ext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
I
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
10. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
11. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
98ASA00222D
144-pin MAPBGA
8 Pinout
8.1 Pins with active pull control after reset
The following pins are actively pulled up or down after reset:
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
77
Pinout
Table 58. Pins with active pull control after reset
Pin
Active pull direction after reset
PTA0
pulldown
pullup
pullup
pullup
pullup
PTA1
PTA3
PTA4
RESET_b
8.2 K60 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
—
L5
RTC_
RTC_
RTC_
WAKEUP_B
WAKEUP_B
WAKEUP_B
—
—
—
—
1
M5
A10
B10
C10
D3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PTE0
ADC1_SE4a
ADC1_SE5a
ADC1_SE4a
ADC1_SE5a
PTE0
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
2
D2
PTE1/
PTE1/
LLWU_P0
LLWU_P0
3
4
D1
E4
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE7a
ADC1_SE6a
ADC1_SE7a
PTE2/
LLWU_P1
SPI1_SCK
SPI1_SIN
UART1_CTS_
b
SDHC0_DCLK
SDHC0_CMD
PTE3
PTE3
UART1_RTS_
b
SPI1_SOUT
5
6
7
E5
F6
E3
VDD
VSS
VDD
VDD
VSS
VSS
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
UART3_RX
SDHC0_D3
8
9
E2
E1
PTE5
PTE6
DISABLED
DISABLED
PTE5
PTE6
SPI1_PCS2
SPI1_PCS3
SDHC0_D2
I2S0_MCLK
FTM3_CH0
FTM3_CH1
UART3_CTS_
b
USB_SOF_
OUT
10
F4
PTE7
DISABLED
PTE7
UART3_RTS_
b
I2S0_RXD0
FTM3_CH2
11
12
F3
F2
PTE8
PTE9
ADC2_SE16
ADC2_SE17
ADC2_SE16
ADC2_SE17
PTE8
PTE9
I2S0_RXD1
I2S0_TXD1
UART5_TX
UART5_RX
I2S0_RX_FS
FTM3_CH3
FTM3_CH4
I2S0_RX_
BCLK
13
F1
PTE10
DISABLED
PTE10
UART5_CTS_
b
I2S0_TXD0
FTM3_CH5
K60 Sub-Family, Rev5, 10/2013.
78
Freescale Semiconductor, Inc.
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
14
15
G4
PTE11
ADC3_SE16
ADC3_SE17
ADC3_SE16
ADC3_SE17
PTE11
UART5_RTS_
b
I2S0_TX_FS
FTM3_CH6
FTM3_CH7
G3
PTE12
PTE12
I2S0_TX_
BCLK
16
17
18
19
20
21
22
23
E6
F7
H3
H1
H2
G1
G2
J1
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
24
25
26
J2
K1
K2
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
27
28
29
30
L1
L2
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
M1
M2
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
31
32
33
34
35
H5
G5
G6
H6
K3
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
79
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
36
37
J3
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
M3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
38
39
L3
L4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
40
41
42
43
44
45
M7
M6
L6
—
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
VDD
VDD
VDD
—
VSS
VSS
VSS
M4
PTE24
ADC0_SE17/
EXTAL1
ADC0_SE17/
EXTAL1
PTE24
CAN1_TX
CAN1_RX
UART4_TX
UART4_RX
I2S1_TX_FS
EWM_OUT_b
EWM_IN
I2S1_RXD1
I2S1_TXD1
46
47
48
K5
K4
J4
PTE25
PTE26
PTE27
ADC0_SE18/
XTAL1
ADC0_SE18/
XTAL1
PTE25
PTE26
PTE27
I2S1_TX_
BCLK
ADC3_SE5b
ADC3_SE4b
ADC3_SE7a
ADC3_SE5b
ENET_1588_
CLKIN
UART4_CTS_
b
I2S1_TXD0
RTC_CLKOUT USB_CLKIN
ADC3_SE4b
UART4_RTS_
b
I2S1_MCLK
49
50
H4
J5
PTE28
PTA0
ADC3_SE7a
TSI0_CH1
PTE28
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
51
52
J6
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
K6
JTAG_TDO/
TRACE_SWO/
EZP_DO
UART0_TX
JTAG_TDO/
TRACE_SWO
EZP_DO
53
54
55
K7
L7
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_
b
FTM0_CH0
FTM0_CH1
FTM0_CH2
JTAG_TMS/
SWD_DIO
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
NMI_b
EZP_CS_b
M8
PTA5
DISABLED
PTA5
USB_CLKIN
ULPI_CLK
RMII0_RXER/
MII0_RXER
CMP2_OUT
I2S0_TX_
BCLK
JTAG_TRST_
b
56
57
58
E7
G7
J7
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
ADC3_SE6a
ADC3_SE6a
PTA6
FTM0_CH3
I2S1_RXD0
TRACE_
CLKOUT
K60 Sub-Family, Rev5, 10/2013.
80
Freescale Semiconductor, Inc.
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
59
60
61
62
63
64
65
66
J8
K8
L8
PTA7
ADC0_SE10
ADC0_SE11
ADC3_SE5a
ADC3_SE4a
ADC3_SE15
CMP2_IN0
CMP2_IN1
CMP3_IN0
ADC0_SE10
ADC0_SE11
ADC3_SE5a
ADC3_SE4a
ADC3_SE15
CMP2_IN0
CMP2_IN1
CMP3_IN0
PTA7
ULPI_DIR
FTM0_CH4
FTM1_CH0
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
I2S1_RX_
BCLK
TRACE_D3
TRACE_D2
TRACE_D1
TRACE_D0
PTA8
PTA8
ULPI_NXT
ULPI_STP
ULPI_DATA0
ULPI_DATA1
CAN0_TX
I2S1_RX_FS
MII0_RXD3
MII0_RXD2
MII0_RXCLK
FTM1_QD_
PHA
PTA9
PTA9
FTM1_QD_
PHB
M9
L9
PTA10
PTA11
PTA12
PTA10
PTA11
PTA12
FTM2_QD_
PHA
FTM2_QD_
PHB
K9
J9
RMII0_RXD1/
MII0_RXD1
I2S0_TXD0
FTM1_QD_
PHA
PTA13/
LLWU_P4
PTA13/
LLWU_P4
CAN0_RX
SPI0_PCS0
RMII0_RXD0/
MII0_RXD0
I2S0_TX_FS
FTM1_QD_
PHB
L10
PTA14
PTA14
RMII0_CRS_
DV/
I2S0_RX_
BCLK
I2S0_TXD1
MII0_RXDV
67
68
L11
K10
PTA15
PTA16
CMP3_IN1
CMP3_IN2
CMP3_IN1
CMP3_IN2
PTA15
PTA16
SPI0_SCK
UART0_RX
RMII0_TXEN/
MII0_TXEN
I2S0_RXD0
SPI0_SOUT
UART0_CTS_
b/
RMII0_TXD0/
MII0_TXD0
I2S0_RX_FS
I2S0_RXD1
UART0_COL_
b
69
K11
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_
b
RMII0_TXD1/
MII0_TXD1
I2S0_MCLK
70
71
72
73
E8
G8
VDD
VDD
VDD
VSS
VSS
VSS
M12
M11
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
LPTMR0_
ALT1
74
75
76
77
78
79
80
81
L12
K12
J12
J11
J10
H12
H11
H10
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
RESET_b
RESET_b
CMP3_IN4
CMP3_IN5
ADC2_SE15
ADC2_SE14
ADC2_SE13
ADC2_SE12
CMP3_IN4
CMP3_IN5
ADC2_SE15
ADC2_SE14
ADC2_SE13
ADC2_SE12
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
I2C0_SCL
MII0_TXD2
MII0_TXCLK
MII0_TXD3
MII0_CRS
MII0_TXER
MII0_COL
FB_A29
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
PTB0/
LLWU_P5
FTM1_CH0
FTM1_CH1
RMII0_MDIO/
MII0_MDIO
FTM1_QD_
PHA
82
H9
PTB1
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
PTB1
I2C0_SDA
RMII0_MDC/
MII0_MDC
FTM1_QD_
PHB
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
81
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
83
84
G12
PTB2
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2
I2C0_SCL
I2C0_SDA
UART0_RTS_
b
ENET0_1588_
TMR0
FTM0_FLT3
FTM0_FLT0
G11
PTB3
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3
UART0_CTS_
b/
ENET0_1588_
TMR1
UART0_COL_
b
85
86
G10
G9
PTB4
PTB5
ADC1_SE10
ADC1_SE11
ADC1_SE10
ADC1_SE11
PTB4
PTB5
ENET0_1588_
TMR2
FTM1_FLT0
FTM2_FLT0
ENET0_1588_
TMR3
87
88
89
F12
F11
F10
PTB6
PTB7
PTB8
ADC1_SE12
ADC1_SE13
DISABLED
ADC1_SE12
ADC1_SE13
PTB6
PTB7
PTB8
FB_AD23
FB_AD22
FB_AD21
UART3_RTS_
b
90
91
F9
PTB9
DISABLED
PTB9
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
UART3_CTS_
b
FB_AD20
FB_AD19
FB_AD18
E12
PTB10
ADC1_SE14
ADC1_SE14
PTB10
PTB11
UART3_RX
I2S1_TX_
BCLK
FTM0_FLT1
FTM0_FLT2
92
93
94
95
96
97
E11
H7
PTB11
VSS
ADC1_SE15
VSS
ADC1_SE15
VSS
UART3_TX
I2S1_TX_FS
F5
VDD
VDD
VDD
E10
E9
PTB16
PTB17
PTB18
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB16
PTB17
PTB18
SPI1_SOUT
SPI1_SIN
CAN0_TX
UART0_RX
UART0_TX
FTM2_CH0
I2S1_TXD0
I2S1_TXD1
FB_AD17
FB_AD16
FB_AD15
EWM_IN
EWM_OUT_b
D12
I2S0_TX_
BCLK
FTM2_QD_
PHA
98
D11
D10
D9
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
TSI0_CH12
ADC2_SE4a
ADC2_SE5a
DISABLED
DISABLED
TSI0_CH12
ADC2_SE4a
ADC2_SE5a
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_
PHB
99
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD31/
NFC_DATA15
CMP0_OUT
CMP1_OUT
CMP2_OUT
CMP3_OUT
I2S0_TXD1
I2S0_TXD0
I2S0_TX_FS
100
101
102
103
104
105
FB_AD30/
NFC_DATA14
C12
C11
B12
B11
A12
FB_AD29/
NFC_DATA13
SPI0_PCS5
FB_AD28/
NFC_DATA12
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
PDB0_EXTRG
FB_AD14/
NFC_DATA11
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
UART1_RTS_
b
FTM0_CH0
FTM0_CH1
FB_AD13/
NFC_DATA10
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
UART1_CTS_
b
FB_AD12/
NFC_DATA9
106
A11
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
107
108
H8
—
VSS
VDD
VSS
VDD
VSS
VDD
K60 Sub-Family, Rev5, 10/2013.
82
Freescale Semiconductor, Inc.
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
109
110
111
112
113
114
115
116
117
118
A9
D8
C8
B8
A8
D7
C7
B7
A7
D6
PTC4/
LLWU_P8
DISABLED
DISABLED
CMP0_IN0
CMP0_IN1
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
I2S0_RXD0
FB_AD11/
NFC_DATA8
CMP1_OUT
CMP0_OUT
I2S0_MCLK
I2S1_TX_
BCLK
PTC5/
LLWU_P9
PTC5/
LLWU_P9
LPTMR0_
ALT2
FB_AD10/
NFC_DATA7
I2S1_TX_FS
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_EXTRG I2S0_RX_
BCLK
FB_AD9/
NFC_DATA6
PTC7
PTC8
PTC9
PTC10
PTC7
PTC8
PTC9
PTC10
USB_SOF_
OUT
I2S0_RX_FS
FB_AD8/
NFC_DATA5
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
FTM3_CH4
FTM3_CH5
FTM3_CH6
FTM3_CH7
I2S0_MCLK
FB_AD7/
NFC_DATA4
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
I2S0_RX_
BCLK
FB_AD6/
NFC_DATA3
FTM2_FLT0
I2S1_MCLK
ADC1_SE6b
ADC1_SE7b
DISABLED
DISABLED
ADC1_SE6b
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
FB_AD5/
NFC_DATA2
PTC11/
LLWU_P11
ADC1_SE7b
PTC11/
LLWU_P11
I2S0_RXD1
FB_RW_b/
NFC_WE
PTC12
PTC13
PTC12
PTC13
UART4_RTS_
b
FB_AD27
FTM3_FLT0
UART4_CTS_
b
FB_AD26
119
120
121
122
123
C6
B6
—
PTC14
PTC15
VSS
DISABLED
DISABLED
VSS
PTC14
PTC15
UART4_RX
UART4_TX
FB_AD25
FB_AD24
VSS
VDD
—
VDD
VDD
A6
PTC16
DISABLED
PTC16
PTC17
CAN1_RX
CAN1_TX
UART3_RX
UART3_TX
ENET0_1588_ FB_CS5_b/
NFC_RB
TMR0
FB_TSIZ1/
FB_BE23_16_
b
124
125
D5
C5
PTC17
DISABLED
DISABLED
ENET0_1588_ FB_CS4_b/
NFC_CE0_b
NFC_CE1_b
TMR1
FB_TSIZ0/
FB_BE31_24_
b
PTC18
PTC19
PTC18
PTC19
UART3_RTS_
b
ENET0_1588_ FB_TBST_b/
TMR2
FB_CS2_b/
FB_BE15_8_b
126
127
B5
A5
DISABLED
DISABLED
UART3_CTS_
b
ENET0_1588_ FB_CS3_b/
FB_TA_b
TMR3
FB_BE7_0_b
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS_
b
FTM3_CH0
FB_ALE/
FB_CS1_b/
FB_TS_b
I2S1_RXD1
128
129
130
131
D4
C4
B4
A4
PTD1
ADC0_SE5b
DISABLED
DISABLED
DISABLED
ADC0_SE5b
PTD1
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_CTS_
b
FTM3_CH1
FTM3_CH2
FTM3_CH3
FTM0_CH4
FB_CS0_b
FB_AD4
FB_AD3
I2S1_RXD0
PTD2/
LLWU_P13
PTD2/
LLWU_P13
UART2_RX
I2S1_RX_FS
PTD3
PTD3
UART2_TX
I2S1_RX_
BCLK
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_
b
FB_AD2/
NFC_DATA1
EWM_IN
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
83
Pinout
144
LQFP
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
132
A3
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_
FTM0_CH5
FB_AD1/
EWM_OUT_b
b/
NFC_DATA0
UART0_COL_
b
133
A2
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_CH7
FB_AD0
FTM0_FLT0
FTM0_FLT1
134
135
136
137
M10
F8
VSS
VSS
VSS
VDD
VDD
PTD7
PTD8
VDD
A1
DISABLED
DISABLED
PTD7
PTD8
CMT_IRO
I2C0_SCL
UART0_TX
UART5_RX
C9
FB_A16/
NFC_CLE
138
139
140
B9
B3
B2
PTD9
DISABLED
DISABLED
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17/
NFC_ALE
PTD10
PTD11
PTD10
PTD11
UART5_RTS_
b
FB_A18/
NFC_RE
SPI2_PCS0
UART5_CTS_
b
SDHC0_
CLKIN
FB_A19
141
142
143
144
B1
C3
C2
C1
PTD12
PTD13
PTD14
PTD15
DISABLED
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
PTD15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FTM3_FLT0
SDHC0_D4
SDHC0_D5
SDHC0_D6
SDHC0_D7
FB_A20
FB_A21
FB_A22
FB_A23
SPI2_PCS1
8.3 K61 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
D3
D2
PTE0
ADC1_SE4a
ADC1_SE5a
ADC1_SE4a
ADC1_SE5a
PTE0
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
PTE1/
PTE1/
LLWU_P0
LLWU_P0
D1
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
SPI1_SIN
UART1_CTS_b SDHC0_DCLK
UART1_RTS_b SDHC0_CMD
E4
E5
F6
E3
PTE3
VDD
VSS
ADC1_SE7a
VDD
ADC1_SE7a
VDD
PTE3
SPI1_SOUT
VSS
VSS
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
UART3_RX
SDHC0_D3
SDHC0_D2
E2
E1
PTE5
PTE6
DISABLED
DISABLED
PTE5
PTE6
SPI1_PCS2
SPI1_PCS3
FTM3_CH0
FTM3_CH1
UART3_CTS_b I2S0_MCLK
USB_SOF_
OUT
K60 Sub-Family, Rev5, 10/2013.
84
Freescale Semiconductor, Inc.
Pinout
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
F4
F3
F2
F1
G4
G3
E6
F7
H3
H1
H2
G1
G2
J1
PTE7
DISABLED
ADC2_SE16
ADC2_SE17
DISABLED
ADC3_SE16
ADC3_SE17
VDD
PTE7
UART3_RTS_b I2S0_RXD0
FTM3_CH2
FTM3_CH3
FTM3_CH4
FTM3_CH5
FTM3_CH6
FTM3_CH7
PTE8
ADC2_SE16
ADC2_SE17
PTE8
I2S0_RXD1
I2S0_TXD1
UART5_TX
UART5_RX
I2S0_RX_FS
PTE9
PTE9
I2S0_RX_BCLK
PTE10
PTE11
PTE12
VDD
PTE10
PTE11
PTE12
UART5_CTS_b I2S0_TXD0
UART5_RTS_b I2S0_TX_FS
I2S0_TX_BCLK
ADC3_SE16
ADC3_SE17
VDD
VSS
VSS
VSS
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
USB0_DP
USB0_DM
VOUT33
VREGIN
VREGIN
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
J2
K1
K2
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
L1
L2
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
M1
M2
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
H5
G5
G6
H6
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
85
Pinout
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K3
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
J3
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
M3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
L3
L4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
L5
TAMPER0/
RTC_
TAMPER0/
RTC_
TAMPER0/
RTC_
WAKEUP_B
WAKEUP_B
WAKEUP_B
K5
K4
J4
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
H4
M4
M7
M6
L6
EXTAL32
VBAT
EXTAL32
VBAT
EXTAL32
VBAT
J5
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_
b/
UART0_COL_b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
J6
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
K6
JTAG_TDO/
TRACE_SWO/
EZP_DO
JTAG_TDO/
TRACE_SWO
EZP_DO
K7
L7
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_b FTM0_CH0
FTM0_CH1
JTAG_TMS/
SWD_DIO
PTA4/
NMI_b/
PTA4/
NMI_b
EZP_CS_b
LLWU_P3
EZP_CS_b
LLWU_P3
M8
PTA5
DISABLED
PTA5
USB_CLKIN
FTM0_CH2
RMII0_RXER/
MII0_RXER
CMP2_OUT
I2S0_TX_BCLK JTAG_TRST_b
E7
G7
J7
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
ADC3_SE6a
ADC3_SE6a
PTA6
PTA7
ULPI_CLK
ULPI_DIR
FTM0_CH3
FTM0_CH4
I2S1_RXD0
TRACE_
CLKOUT
J8
PTA7
ADC0_SE10
ADC0_SE10
I2S1_RX_BCLK
TRACE_D3
K60 Sub-Family, Rev5, 10/2013.
86
Freescale Semiconductor, Inc.
Pinout
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K8
PTA8
ADC0_SE11
ADC3_SE5a
ADC3_SE4a
ADC3_SE15
CMP2_IN0
CMP2_IN1
CMP3_IN0
ADC0_SE11
ADC3_SE5a
ADC3_SE4a
ADC3_SE15
CMP2_IN0
CMP2_IN1
CMP3_IN0
PTA8
ULPI_NXT
ULPI_STP
ULPI_DATA0
ULPI_DATA1
CAN0_TX
FTM1_CH0
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
I2S1_RX_FS
MII0_RXD3
MII0_RXD2
MII0_RXCLK
FTM1_QD_
PHA
TRACE_D2
TRACE_D1
TRACE_D0
L8
PTA9
PTA9
FTM1_QD_
PHB
M9
L9
PTA10
PTA11
PTA12
PTA10
PTA11
PTA12
FTM2_QD_
PHA
FTM2_QD_
PHB
K9
J9
RMII0_RXD1/
MII0_RXD1
I2S0_TXD0
FTM1_QD_
PHA
PTA13/
LLWU_P4
PTA13/
LLWU_P4
CAN0_RX
RMII0_RXD0/
MII0_RXD0
I2S0_TX_FS
FTM1_QD_
PHB
L10
PTA14
PTA14
SPI0_PCS0
RMII0_CRS_
DV/
I2S0_RX_BCLK I2S0_TXD1
MII0_RXDV
L11
K10
PTA15
PTA16
CMP3_IN1
CMP3_IN2
CMP3_IN1
CMP3_IN2
PTA15
PTA16
SPI0_SCK
UART0_RX
RMII0_TXEN/
MII0_TXEN
I2S0_RXD0
SPI0_SOUT
UART0_CTS_
b/
UART0_COL_b
RMII0_TXD0/
MII0_TXD0
I2S0_RX_FS
I2S0_MCLK
I2S0_RXD1
K11
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_b RMII0_TXD1/
MII0_TXD1
E8
G8
VDD
VDD
VDD
VSS
VSS
VSS
M12
M11
L12
K12
J12
J11
J10
H12
H11
H10
PTA18
PTA19
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
EXTAL0
EXTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
XTAL0
XTAL0
LPTMR0_ALT1
RESET_b
CMP3_IN4
CMP3_IN5
ADC2_SE15
ADC2_SE14
ADC2_SE13
ADC2_SE12
RESET_b
CMP3_IN4
CMP3_IN5
ADC2_SE15
ADC2_SE14
ADC2_SE13
ADC2_SE12
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
I2C0_SCL
MII0_TXD2
MII0_TXCLK
MII0_TXD3
MII0_CRS
MII0_TXER
MII0_COL
FB_A29
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
PTB0/
LLWU_P5
FTM1_CH0
FTM1_CH1
RMII0_MDIO/
MII0_MDIO
FTM1_QD_
PHA
H9
PTB1
PTB2
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
PTB1
PTB2
I2C0_SDA
I2C0_SCL
RMII0_MDC/
MII0_MDC
FTM1_QD_
PHB
G12
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
UART0_RTS_b ENET0_1588_
TMR0
FTM0_FLT3
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
87
Pinout
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
G11
PTB3
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3
I2C0_SDA
UART0_CTS_
b/
ENET0_1588_
TMR1
FTM0_FLT0
UART0_COL_b
G10
G9
PTB4
ADC1_SE10
ADC1_SE11
ADC1_SE10
ADC1_SE11
PTB4
PTB5
ENET0_1588_
TMR2
FTM1_FLT0
FTM2_FLT0
PTB5
ENET0_1588_
TMR3
F12
F11
F10
F9
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
VSS
ADC1_SE12
ADC1_SE13
DISABLED
DISABLED
ADC1_SE14
ADC1_SE15
VSS
ADC1_SE12
ADC1_SE13
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
FB_AD23
FB_AD22
FB_AD21
FB_AD20
UART3_RTS_b
UART3_CTS_b
UART3_RX
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
E12
E11
H7
ADC1_SE14
ADC1_SE15
VSS
I2S1_TX_BCLK FB_AD19
FTM0_FLT1
FTM0_FLT2
UART3_TX
I2S1_TX_FS
FB_AD18
F5
VDD
VDD
VDD
E10
E9
PTB16
PTB17
PTB18
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB16
PTB17
PTB18
SPI1_SOUT
SPI1_SIN
CAN0_TX
UART0_RX
UART0_TX
FTM2_CH0
I2S1_TXD0
I2S1_TXD1
FB_AD17
FB_AD16
EWM_IN
EWM_OUT_b
D12
I2S0_TX_BCLK FB_AD15
FTM2_QD_
PHA
D11
D10
D9
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
TSI0_CH12
ADC2_SE4a
ADC2_SE5a
DISABLED
DISABLED
TSI0_CH12
ADC2_SE4a
ADC2_SE5a
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_
PHB
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD31/
NFC_DATA15
CMP0_OUT
CMP1_OUT
CMP2_OUT
CMP3_OUT
I2S0_TXD1
I2S0_TXD0
I2S0_TX_FS
FB_AD30/
NFC_DATA14
C12
C11
B12
B11
A12
FB_AD29/
NFC_DATA13
SPI0_PCS5
FB_AD28/
NFC_DATA12
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
PDB0_EXTRG
FB_AD14/
NFC_DATA11
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
UART1_RTS_b FTM0_CH0
UART1_CTS_b FTM0_CH1
FB_AD13/
NFC_DATA10
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
FB_AD12/
NFC_DATA9
A11
PTC3/
CMP1_IN1
CMP1_IN1
PTC3/
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_BCLK
LLWU_P7
LLWU_P7
H8
A9
VSS
VSS
VSS
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART1_TX
FTM0_CH3
I2S0_RXD0
FB_AD11/
NFC_DATA8
CMP1_OUT
CMP0_OUT
I2S0_MCLK
I2S1_TX_BCLK
I2S1_TX_FS
D8
C8
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
PTC5/
LLWU_P9
LPTMR0_ALT2
PDB0_EXTRG
FB_AD10/
NFC_DATA7
PTC6/
LLWU_P10
CMP0_IN0
PTC6/
LLWU_P10
I2S0_RX_BCLK FB_AD9/
NFC_DATA6
K60 Sub-Family, Rev5, 10/2013.
88
Freescale Semiconductor, Inc.
Pinout
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
B8
A8
D7
C7
B7
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS
I2S0_MCLK
FB_AD8/
NFC_DATA5
PTC8
PTC9
PTC10
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
PTC8
PTC9
PTC10
FTM3_CH4
FTM3_CH5
FTM3_CH6
FTM3_CH7
FB_AD7/
NFC_DATA4
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
I2S0_RX_BCLK FB_AD6/
NFC_DATA3
FTM2_FLT0
I2S1_MCLK
ADC1_SE6b
ADC1_SE6b
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
FB_AD5/
NFC_DATA2
PTC11/
LLWU_P11
ADC1_SE7b
ADC1_SE7b
PTC11/
LLWU_P11
I2S0_RXD1
FB_RW_b/
NFC_WE
A7
D6
C6
B6
A6
PTC12
PTC13
PTC14
PTC15
PTC16
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTC12
PTC13
PTC14
PTC15
PTC16
UART4_RTS_b
UART4_CTS_b
UART4_RX
FB_AD27
FB_AD26
FB_AD25
FB_AD24
FTM3_FLT0
UART4_TX
CAN1_RX
CAN1_TX
UART3_RX
ENET0_1588_
TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_b
NFC_RB
D5
C5
PTC17
PTC18
PTC19
DISABLED
DISABLED
PTC17
PTC18
PTC19
UART3_TX
ENET0_1588_
TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_b
NFC_CE0_b
NFC_CE1_b
UART3_RTS_b ENET0_1588_
TMR2
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
B5
A5
DISABLED
DISABLED
UART3_CTS_b ENET0_1588_
TMR3
FB_CS3_b/
FB_BE7_0_b
FB_TA_b
PTD0/
PTD0/
SPI0_PCS0
UART2_RTS_b FTM3_CH0
FB_ALE/
I2S1_RXD1
LLWU_P12
LLWU_P12
FB_CS1_b/
FB_TS_b
D4
C4
PTD1
ADC0_SE5b
DISABLED
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_b FTM3_CH1
FB_CS0_b
FB_AD4
I2S1_RXD0
PTD2/
LLWU_P13
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
UART2_TX
FTM3_CH2
FTM3_CH3
I2S1_RX_FS
B4
A4
PTD3
DISABLED
DISABLED
PTD3
SPI0_SIN
FB_AD3
I2S1_RX_BCLK
EWM_IN
PTD4/
PTD4/
SPI0_PCS1
UART0_RTS_b FTM0_CH4
FB_AD2/
LLWU_P14
LLWU_P14
NFC_DATA1
A3
A2
PTD5
ADC0_SE6b
ADC0_SE7b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI0_PCS2
SPI0_PCS3
UART0_CTS_
b/
UART0_COL_b
FTM0_CH5
FTM0_CH6
FB_AD1/
NFC_DATA0
EWM_OUT_b
FTM0_FLT0
PTD6/
PTD6/
UART0_RX
FB_AD0
LLWU_P15
LLWU_P15
M10
F8
VSS
VSS
VSS
VDD
VDD
PTD7
PTD8
VDD
A1
DISABLED
DISABLED
PTD7
PTD8
CMT_IRO
I2C0_SCL
UART0_TX
UART5_RX
FTM0_CH7
FTM0_FLT1
C9
FB_A16/
NFC_CLE
B9
PTD9
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17/
NFC_ALE
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
89
Pinout
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
B3
PTD10
DISABLED
PTD10
UART5_RTS_b
FB_A18/
NFC_RE
FB_A19
FB_A20
FB_A21
FB_A22
FB_A23
B2
B1
PTD11
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
NC
PTD11
PTD12
PTD13
PTD14
PTD15
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
UART5_CTS_b SDHC0_CLKIN
PTD12
PTD13
PTD14
PTD15
NC
FTM3_FLT0
SDHC0_D4
SDHC0_D5
SDHC0_D6
SDHC0_D7
C3
C2
C1
SPI2_PCS1
M5
A10
B10
C10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8.4 K60 pinouts
The figure below shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K60 Sub-Family, Rev5, 10/2013.
90
Freescale Semiconductor, Inc.
Pinout
PTE0
1
108
107
106
105
104
103
102
101
100
99
VDD
VSS
PTE1/LLWU_P0
2
PTE2/LLWU_P1
3
PTC3/LLWU_P7
PTC2
PTE3
4
VDD
5
PTC1/LLWU_P6
PTC0
VSS
6
PTE4/LLWU_P2
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE5
8
PTE6
9
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
98
PTE9
97
PTE10
96
PTE11
95
PTE12
94
VDD
VSS
93
VSS
PTB11
PTB10
PTB9
92
VSS
USB0_DP
91
90
USB0_DM
PTB8
89
VOUT33
PTB7
88
VREGIN
PTB6
87
PGA2_DP/ADC2_DP0/ADC3_DP3/ADC0_DP1
PGA2_DM/ADC2_DM0/ADC3_DM3/ADC0_DM1
PGA3_DP/ADC3_DP0/ADC2_DP3/ADC1_DP1
PGA3_DM/ADC3_DM0/ADC2_DM3/ADC1_DM1
PGA0_DP/ADC0_DP0/ADC1_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA1_DM/ADC1_DM0/ADC0_DM3
VDDA
PTB5
86
PTB4
85
PTB3
84
PTB2
83
PTB1
82
PTB0/LLWU_P5
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
81
80
79
78
VREFH
77
VREFL
76
VSSA
75
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
74
73
Figure 42. K60 144 LQFP Pinout Diagram
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
91
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
PTC4/
LLWU_P8
PTC3/
LLWU_P7
PTD6/
LLWU_P15
PTD4/
LLWU_P14
PTD0/
LLWU_P12
A
B
C
D
E
F
PTC8
NC
PTC2
A
B
C
D
E
F
PTD7
PTD12
PTD15
PTD5
PTC16
PTC12
PTC11/
LLWU_P11
PTC1/
LLWU_P6
PTD11
PTD14
PTD10
PTD13
PTE0
PTD3
PTC19
PTC18
PTC17
VDD
PTC15
PTC14
PTC13
VDD
PTC7
PTD9
PTD8
PTB21
PTB17
PTB9
PTB5
PTB1
NC
NC
PTC0
PTB22
PTB18
PTB10
PTB6
PTD2/
LLWU_P13
PTC6/
LLWU_P10
PTC10
PTC9
VDD
PTB23
PTB19
PTB11
PTB7
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTC5/
LLWU_P9
PTD1
PTE3
PTB20
PTB16
PTB8
PTB4
PTE4/
LLWU_P2
PTE6
PTE10
PTE5
PTE9
VDD
VDD
VSS
PTE8
PTE12
VSS
PTE7
VDD
VSS
VSS
G
H
J
G
H
J
VOUT33
VREGIN
PTE11
PTE28
PTE27
PTE26
VREFH
VDDA
PTA0
VREFL
VSSA
PTA1
PTA2
VBAT
VSS
PTB3
PTB2
PTB0/
LLWU_P5
USB0_DP
PGA2_DP/
USB0_DM
PGA2_DM/
VSS
VSS
PTA29
PTA26
PTA17
PTA15
PTA28
PTA25
PTA24
RESET_b
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC2_DP0/ ADC2_DM0/
ADC3_DP3/ ADC3_DM3/
PTA13/
LLWU_P4
PTA6
PTA3
PTA7
PTA8
PTA9
PTA27
PTA16
PTA14
ADC0_DP1
ADC0_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DP/
ADC2_DP3/
ADC1_DP1
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
K
L
K
L
PTE25
RTC_
PTA12
PTA11
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/ WAKEUP_B
ADC1_SE23
PGA0_DP/
PGA0_DM/ DAC0_OUT/
ADC0_DP0/ ADC0_DM0/ CMP1_IN3/
PTA4/
LLWU_P3
ADC1_DP3
ADC1_DM3 ADC0_SE23
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PGA1_DP/
ADC1_DP0/ ADC1_DM0/
ADC0_DP3
PGA1_DM/
M
M
PTE24
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
ADC0_DM3
1
2
3
4
5
6
7
8
9
10
11
12
Figure 43. K60 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 59. Revision History
Rev. No.
Date
Substantial Changes
3
3/2012
Initial public release
Table continues on the next page...
K60 Sub-Family, Rev5, 10/2013.
92
Freescale Semiconductor, Inc.
Revision History
Table 59. Revision History (continued)
Rev. No.
Date
Substantial Changes
4
5
10/2012
10/2013
Replaced TBDs throughout.
Changes for 4N96B mask set:
• Min VDD operating requirement specification updated to support operation down to
1.71V.
New specifications:
• Added Vodpu specification.
• Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specficiations. They have been
replaced by new Iina, Iind, and Zind specifications.
• Fpll_ref_acc specification has been added.
• I2C module was previously covered by the general switching specifications. To provide
more detail on I2C operation a dedicated Inter-Integrated Circuit Interface (I2C) timing
section has been added.
Modified specifications:
• Vref_ddr max spec has been updated.
• Tpor spec has been split into two specifications based on VDD slew rate.
• Trd1allx and Trd1alln max have been updated.
• 16-bit ADC Temp sensor slope and Temp sensor voltage (Vtemp25) have been
modified. The typical values that were listed previously have been updated, and min
and max specifications have been added.
Corrections:
• Some versions of the datasheets listed incorrect clock mode information in the
"Diagram: Typical IDD_RUN operating behavior section." These errors have been
corrected.
• Fintf_ft specification was previously shown as a max value. It has been corrected to be
shown as a typical value as originally intended.
• Corrected DDR write and read timing diagrams to show the correct location of the Tcmv
specification.
• SDHC peripheral 50MHz high speed mode options were left out of the last datasheet.
These have been added to the SDHC specifications section.
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc.
93
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Document Number: K60P144M150SF3
Rev. 5
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