MK64FN1M0VLL12_技术文档

NXP Semiconductors

Data Sheet: Technical Data

K64P144M120SF5

Rev. 7, 10/2016

Kinetis K64F Sub-Family Data

MK64FN1M0Vxx12

MK64FX512Vxx12

Sheet

120 MHz ARM® Cortex®-M4-based Microcontroller with FPU

The K64 product family members are optimized for cost-sensitive

applications requiring low-power, USB/Ethernet connectivity, and

up to 256 KB of embedded SRAM. These devices share the

comprehensive enablement and scalability of the Kinetis family.

121 XFBGA

8 x 8 x 0.5 mm Pitch 20 x 20 x 1.6 mm Pitch

144 LQFP

0.65 mm

0.5 mm

This product offers:

• Run power consumption down to 250 μA/MHz. Static

power consumption down to 5.8 μA with full state retention

and 5 μs wakeup. Lowest Static mode down to 339 nA

• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO

Vreg, with USB device crystal-less operation

144 MAPBGA

13 x 13 x 1.46 mm 14 x 14 x 1.7 mm Pitch

Pitch 1 mm 0.5 mm

100 QFP

• 10/100 Mbit/s Ethernet MAC with MII and RMII interfaces

Performance

• Up to 120 MHz ARM® Cortex®-M4 core with DSP

Communication interfaces

• Ethernet controller with MII and RMII interface

• USB full-/low-speed On-the-Go controller

• Controller Area Network (CAN) module

• Three SPI modules

• Three I2C modules. Support for up to 1 Mbit/s

• Six UART modules

instructions and floating point unit

Memories and memory interfaces

• Up to 1 MB program flash memory and 256 KB RAM

• Upto 128 KB FlexNVM and 4 KB FlexRAM on devices

with FlexMemory

• Secure Digital Host Controller (SDHC)

• I2S module

• FlexBus external bus interface

System peripherals

Timers

• Multiple low-power modes, low-leakage wake-up unit

• Memory protection unit with multi-master protection

• 16-channel DMA controller

• Two 8-channel Flex-Timers (PWM/Motor control)

• Two 2-channel FlexTimers (PWM/Quad decoder)

• IEEE 1588 timers

• External watchdog monitor and software watchdog

• 32-bit PITs and 16-bit low-power timers

• Real-time clock

• Programmable delay block

Security and integrity modules

• Hardware CRC module

• Hardware random-number generator

• Hardware encryption supporting DES, 3DES, AES,

MD5, SHA-1, and SHA-256 algorithms

• 128-bit unique identification (ID) number per chip

Clocks

• 3 to 32 MHz and 32 kHz crystal oscillator

• PLL, FLL, and multiple internal oscillators

• 48 MHz Internal Reference Clock (IRC48M)

Analog modules

Operating Characteristics

• Two 16-bit SAR ADCs

• Two 12-bit DACs

• Three analog comparators (CMP)

• Voltage reference

• Voltage range: 1.71 to 3.6 V

• Flash write voltage range: 1.71 to 3.6 V

• Temperature range (ambient): –40 to 105°C

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Ordering Information1

Memory

Part Number

Maximum number of I\O's

Flash

SRAM (KB)

MK64FX512VLL12

MK64FN1M0VLL12

MK64FX512VDC12

MK64FN1M0VDC12

MK64FX512VLQ12

MK64FN1M0VLQ12

MK64FX512VMD12

MK64FN1M0VMD12

512 KB

1 MB

256

66

512 KB

1 MB

83

512 KB

1 MB

100

512 KB

1 MB

1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.

Related Resources

Type

Selector

Guide

Description

Resource

Solution Advisor

The NXP Solution Advisor is a web-based tool that features interactive

application wizards and a dynamic product selector.

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

K60PB¹

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

K64P144M120SF5RM ¹

K64P144M120SF5¹

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

Package

drawing

Package dimensions are provided in package drawings.

• MAPBGA 144-pin:

98ASA00222D¹

• LQFP 144-pin:

98ASS23177W¹

• LQFP 100-pin:

98ASS23308W¹

• XFBGA 121-pin:

98ASA00595D¹

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

2

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Kinetis K64 Family

ARM^®Cortex™-M4

Core

System

Memories and Memory Interfaces

Clocks

Internal

Program

flash

Phase-

locked loop

and external

watchdogs

RAM

Debug

interfaces

Memory

protection

Frequency-

locked loop

External

bus

FlexMemory

DSP

Serial

Low/high

frequency

oscillators

Interrupt

controller

Floating-

point unit

programming

DMA

interface

Internal

reference

clocks

Low-leakage

wakeup

Security

Communication Interfaces

Human-Machine

Interface (HMI)

Analog

Timers

and Integrity

I²C

I²S

x3

Timers

x2 (8ch)

x2 (2ch)

16-bit ADC

CRC

GPIO

x2

Random

number

Analog

comparator

x3

UART

x6

Secure

Digital

Programmable

delay block

generator

Hardware

encryption

SPI

x3

6-bit DAC

x3

USB OTG

LS/FS

Periodic

interrupt

timers

12-bit DAC

x2

CAN

x1

USB LS/FS

transceiver

Low power

timer

IEEE 1588

Ethernet

Voltage

reference

USB charger

detect

Independent

real-time

clock

USB voltage

regulator

IEEE 1588

Timers

Figure 1. K64 block diagram

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

3

NXP Semiconductors

Table of Contents

1 Ratings....................................................................................5

3.6.2

3.6.3

3.6.4

CMP and 6-bit DAC electrical specifications.....44

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................6

12-bit DAC electrical characteristics................. 46

Voltage reference electrical specifications........49

3.7 Timers..............................................................................50

3.8 Communication interfaces............................................... 50

3.8.1

3.8.2

3.8.3

3.8.4

3.8.5

3.8.6

Ethernet switching specifications...................... 51

USB electrical specifications.............................53

USB DCD electrical specifications.................... 53

USB VREG electrical specifications..................54

CAN switching specifications............................ 54

DSPI switching specifications (limited voltage

range)................................................................55

DSPI switching specifications (full voltage

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

Voltage and current operating requirements.....6

LVD and POR operating requirements............. 8

Voltage and current operating behaviors.......... 8

Power mode transition operating behaviors......10

Power consumption operating behaviors..........11

EMC radiated emissions operating behaviors...16

Designing with radiated emissions in mind....... 17

Capacitance attributes...................................... 17

3.8.7

range)................................................................56

Inter-Integrated Circuit Interface (I2C) timing....58

UART switching specifications..........................60

3.8.8

3.8.9

2.3 Switching specifications...................................................17

3.8.10 SDHC specifications......................................... 60

3.8.11 I2S switching specifications.............................. 61

4 Dimensions............................................................................. 67

4.1 Obtaining package dimensions....................................... 67

5 Pinout......................................................................................67

5.1 K64 Signal Multiplexing and Pin Assignments.................67

5.2 Unused analog interfaces................................................75

5.3 K64 Pinouts..................................................................... 76

6 Ordering parts......................................................................... 81

6.1 Determining valid orderable parts....................................81

7 Part identification.....................................................................82

7.1 Description.......................................................................82

7.2 Format............................................................................. 82

7.3 Fields............................................................................... 82

7.4 Example...........................................................................83

8 Terminology and guidelines.................................................... 83

8.1 Definitions........................................................................83

8.2 Examples.........................................................................84

8.3 Typical-value conditions.................................................. 84

8.4 Relationship between ratings and operating

2.3.1

2.3.2

Device clock specifications............................... 17

General switching specifications.......................18

2.4 Thermal specifications.....................................................19

2.4.1

2.4.2

Thermal operating requirements.......................19

Thermal attributes............................................. 20

3 Peripheral operating requirements and behaviors.................. 21

3.1 Core modules.................................................................. 21

3.1.1

3.1.2

Debug trace timing specifications..................... 21

JTAG electricals................................................22

3.2 System modules.............................................................. 25

3.3 Clock modules................................................................. 25

3.3.1

3.3.2

3.3.3

3.3.4

MCG specifications........................................... 25

IRC48M specifications...................................... 27

Oscillator electrical specifications..................... 28

32 kHz oscillator electrical characteristics.........30

3.4 Memories and memory interfaces................................... 31

3.4.1

3.4.2

3.4.3

Flash (FTFE) electrical specifications............... 31

EzPort switching specifications.........................36

Flexbus switching specifications....................... 36

3.5 Security and integrity modules........................................ 39

3.6 Analog............................................................................. 39

requirements....................................................................85

8.5 Guidelines for ratings and operating requirements..........85

9 Revision History...................................................................... 86

3.6.1

ADC electrical specifications.............................40

4

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Ratings

1 Ratings

1.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

260

245

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

Solder temperature, leaded

1

2

T_SDR

°C

—

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol

V_HBM

Description

Min.

-2000

-500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

I_LAT

Latch-up current at ambient temperature of 105°C

-100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

5

NXP Semiconductors

General

Symbol

Description

Min.

–0.3

—

Max.

3.8

Unit

V

V_DD

I_DD

Digital supply voltage

Digital supply current

185

mA

V

V_DIO

Digital input voltage (except RESET, EXTAL, and XTAL)

–0.3

5.5

V_{DRTC_WAKEU}RTC Wakeup input voltage

V_BAT+ 0.3

V

P

V_AIO

I_D

Analog¹, RESET, EXTAL, and XTAL input voltage

–0.3

–25

V_DD+ 0.3

25

V

mA

V

Maximum current single pin limit (applies to all digital pins)

Analog supply voltage

V_DDA

V_DD– 0.3

–0.3

V_DD+ 0.3

3.63

V_{USB0_DP}

V_{USB0_DM}

V_REGIN

V_BAT

USB0_DP input voltage

V

USB0_DM input voltage

–0.3

3.63

V

USB regulator input

–0.3

6.0

V

RTC battery supply voltage

–0.3

3.8

V

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

6

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

General

Notes

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.71

–0.1

1.71

Max.

3.6

0.1

3.6

Unit

V

Supply voltage

V_DDA

Analog supply voltage

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

V

V_BAT

V_IH

RTC battery supply voltage

Input high voltage

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICDIO

Input hysteresis

0.06 × V_DD

-5

—

V

Digital pin negative DC injection current — single pin

• V_IN< V_SS-0.3V

1

3

mA

I_ICAIO

Analog², EXTAL, and XTAL pin DC injection current

— single pin

mA

-5

—

• V_IN< V_SS-0.3V (Negative current injection)

• V_IN> V_DD+0.3V (Positive current injection)

—

+5

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

-25

—

mA

• Negative current injection

• Positive current injection

+25

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V

4

V_DDvoltage required to retain RAM

V_RFVBATV_BATvoltage required to retain the VBAT register file V_{POR_VBAT}

—

1. All 5 V tolerant digital I/O pins are internally clamped to V_SSthrough an ESD protection diode. There is no diode

connection to V_DD. If V_INis less than V_{DIO_MIN}, a current limiting resistor is required. If V_INgreater than V_{DIO_MIN}

(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC

injection current limiting resistor is calculated as R=(V_{DIO_MIN}-V_IN)/|I_ICDIO|.

2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL

and XTAL are analog pins.

3. All analog pins are internally clamped to V_SSand V_DDthrough ESD protection diodes. If V_INis less than V_{AIO_MIN}or

greater than V_{AIO_MAX}, a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R=(V_{AIO_MIN}-V_IN)/|I_ICAIO|. The positive injection current limiting resistor is calculated as R=(V_IN-

V_{AIO_MAX})/|I_ICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative

injection currents.

4. Open drain outputs must be pulled to VDD.

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

7

NXP Semiconductors

General

2.2.2 LVD and POR operating requirements

Table 2. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling VDD POR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_{POR_VBAT}Falling VBAT supply POR detect voltage

0.8

1.1

1.5

V

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — high drive strength

Table continues on the next page...

8

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

General

Notes

Table 4. Voltage and current operating behaviors (continued)

Symbol

Description

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -8mA

Min.

Max.

Unit

V_DD– 0.5

—

V

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -3mA

V_DD– 0.5

—

V

Output high voltage — low drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -2mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -0.6mA

V_DD– 0.5

—

V

I_OHT

Output high current total for all ports

—

100

—

mA

V

V_{OH_RTC_WA}Output high voltage — high drive strength

V_BAT– 0.5

KEUP

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OH= -10mA

—

V

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OH= -3mA

Output high voltage — low drive strength

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OH= -2mA

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OH= -0.6mA

V_BAT– 0.5

—

V

I_{OH_RTC_WAK}Output high current total for RTC_WAKEUP pins

—

100

mA

EUP

V_OL

Output low voltage — high drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 9mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 3mA

—

0.5

V

Output low voltage — low drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 2mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 0.6mA

—

0.5

V

I_OLT

Output low current total for all ports

—

100

0.5

mA

V

V_{OL_RTC_WA}Output low voltage — high drive strength

KEUP

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OL= 10mA

V

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OL= 3mA

Output low voltage — low drive strength

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OL= 2mA

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OL= 0.6mA

—

0.5

V

I_{OL_RTC_WAK}Output low current total for RTC_WAKEUP pins

—

100

1

mA

μA

EUP

I_IN

Input leakage current (per pin) for full temperature

range

1

I_IN

Input leakage current (per pin) at 25°C

—

0.025

1

μA

I_{IN_RTC_WAK}Input leakage current (per RTC_WAKEUP pin) for full

temperature range

EUP

I_{IN_RTC_WAK}Input leakage current (per RTC_WAKEUP pin) at

—

0.025

μA

25°C

EUP

Table continues on the next page...

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

9

NXP Semiconductors

General

Table 4. Voltage and current operating behaviors (continued)

Symbol

I_OZ

Description

Min.

—

Max.

0.25

Unit

μA

Notes

Hi-Z (off-state) leakage current (per pin)

I_{OZ_RTC_WAK}Hi-Z (off-state) leakage current (per RTC_WAKEUP

—

μA

pin)

EUP

R_PU

R_PD

Internal pullup resistors (except RTC_WAKEUP pins)

20

50

kΩ

2

3

Internal pulldown resistors (except RTC_WAKEUP

pins)

1. Measured at VDD=3.6V

2. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

3. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_DD

2.2.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 100 MHz

• Bus clock = 50 MHz

• FlexBus clock = 50 MHz

• Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point V_DD

reaches 1.71 V to execution of the first instruction

across the operating temperature range of the chip.

—

300

μs

—

156

78

μs

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS2 → RUN

• VLLS3 → RUN

• LLS → RUN

78

4.8

4.5

• VLPS → RUN

• STOP → RUN

10

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

General

2.2.5 Power consumption operating behaviors

NOTE

The maximum values represent characterized results

equivalent to the mean plus three times the standard

deviation (mean + 3 sigma).

Table 6. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_RUN}Run mode current — all peripheral clocks

disabled, code executing from flash

—

31.1

31

36.65

36.75

mA

• @ 1.8V

• @ 3.0V

I_{DD_RUN}Run mode current — all peripheral clocks

enabled, code executing from flash

3, 4

—

42.7

48.35

mA

• @ 1.8V

• @ 3.0V

• @ 25°C

• @ 105°C

—

40

41.60

51.50

mA

48.33

I_{DD_WAIT}Wait mode high frequency current at 3.0 V —

all peripheral clocks disabled

—

17.9

6.9

—

mA

2

5

6

7

8

I_{DD_WAIT}Wait mode reduced frequency current at 3.0 V

— all peripheral clocks disabled

I_{DD_VLPR}Very-low-power run mode current at 3.0 V —

all peripheral clocks disabled

1.0

I_{DD_VLPR}Very-low-power run mode current at 3.0 V —

all peripheral clocks enabled

1.7

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V —

all peripheral clocks disabled

0.678

I_{DD_STOP}Stop mode current at 3.0 V

• @ –40 to 25°C

—

0.49

1.18

3.0

1.24

4.3

mA

• @ 70°C

12.5

• @ 105°C

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

—

57

139.31

679.33

1869.85

μA

• @ –40 to 25°C

• @ 70°C

291

927.3

• @ 105°C

I_{DD_LLS}Low leakage stop mode current at 3.0 V

9

Table continues on the next page...

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

11

NXP Semiconductors

General

Table 6. Power consumption operating behaviors (continued)

Symbol Description

• @ –40 to 25°C

Min.

Typ.

Max.

Unit

Notes

—

5.8

10.48

μA

• @ 70°C

—

26.7

47.99

μA

• @ 105°C

114.9

196.49

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

—

4.4

21

5.54

36.46

150.17

μA

• @ –40 to 25°C

• @ 70°C

90.2

• @ 105°C

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

—

2.1

2.34

10.36

46.74

μA

• @ –40 to 25°C

• @ 70°C

6.84

29.4

• @ 105°C

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

—

0.817

3.97

21.3

0.86

5.77

μA

• @ –40 to 25°C

• @ 70°C

33.99

• @ 105°C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

—

0.52

3.67

0.62

5.7

μA

• @ –40 to 25°C

• @ 70°C

21.20

34.9

• @ 105°C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

—

0.339

3.36

20.3

0.412

4.2

μA

• @ –40 to 25°C

• @ 70°C

29.9

• @ 105°C

I_{DD_VBAT}Average current with RTC and 32 kHz disabled

• @ 1.8 V

• @ –40 to 25°C

• @ 70°C

—

0.16

0.55

2.5

0.19

0.72

3.68

μA

• @ 105°C

• @ 3.0 V

—

0.18

0.66

2.92

0.21

0.86

4.30

μA

• @ –40 to 25°C

• @ 70°C

• @ 105°C

Table continues on the next page...

12

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

General

Table 6. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VBAT}Average current when CPU is not accessing

RTC registers

10

• @ 1.8 V

• @ –40 to 25°C

• @ 70°C

—

0.59

1.0

0.70

1.30

4.42

μA

• @ 105°C

• @ 3.0 V

3.0

• @ –40 to 25°C

• @ 70°C

—

0.71

1.22

3.5

0.84

1.59

5.15

μA

• @ 105°C

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for

PEE mode. All peripheral clocks disabled.

3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured

for PEE mode. All peripheral clocks enabled.

4. Max values are measured with CPU executing DSP instructions.

5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI

mode.

6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled. Code executing from flash.

7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks enabled but peripherals are not in active operation. Code executing from flash.

8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled.

9. Data reflects devices with 256 KB of RAM.

10. Includes 32kHz oscillator current and RTC operation.

Table 7. Low power mode peripheral adders — typical value

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

I_IREFSTEN4MHz

4 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 4 MHz IRC enabled.

56

µA

I_{IREFSTEN32KHz}

I_EREFSTEN4MHz

I_{EREFSTEN32KHz}

32 kHz internal reference clock (IRC)

adder. Measured by entering STOP

mode with the 32 kHz IRC enabled.

52

µA

uA

External 4 MHz crystal clock adder.

Measured by entering STOP or VLPS

mode with the crystal enabled.

206

228

237

245

251

258

External 32 kHz crystal clock adder by

means of the OSC0_CR[EREFSTEN

and EREFSTEN] bits. Measured by

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Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

13

NXP Semiconductors

General

Table 7. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

entering all modes with the crystal

enabled.

440

490

510

490

560

540

560

570

610

580

680

VLLS1

VLLS3

nA

LLS

VLPS

STOP

I_48MIRC

I_CMP

48 Mhz internal reference clock

350

22

350

22

350

22

350

22

350

22

350

22

µA

CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and

a single external input for compare.

Includes 6-bit DAC power

consumption.

I_RTC

RTC peripheral adder measured by

placing the device in VLLS1 mode with

external 32 kHz crystal enabled by

means of the RTC_CR[OSCE] bit and

the RTC ALARM set for 1 minute.

Includes ERCLK32K (32 kHz external

crystal) power consumption.

432

357

388

475

532

810

nA

I_UART

UART peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source

waiting for RX data at 115200 baud

rate. Includes selected clock source

power consumption.

66

µA

MCGIRCLK (4 MHz internal reference

clock)

214

45

237

45

246

45

254

45

260

45

268

45

OSCERCLK (4 MHz external crystal)

I_BG

Bandgap adder when BGEN bit is set

and device is placed in VLPx, LLS, or

VLLSx mode.

µA

I_ADC

ADC peripheral adder combining the

measured values at V_DDand V_DDAby

placing the device in STOP or VLPS

mode. ADC is configured for low power

mode using the internal clock and

continuous conversions.

42

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

14

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

General

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Run Mode Current Consumption vs Core Frequency

Temp (C)=25, V =3.6V, CACHE=ENABLE, Code Residence=Flash

DD

40.00E-03

35.00E-03

30.00E-03

25.00E-03

20.00E-03

15.00E-03

10.00E-03

5.00E-03

All Peripheral Clk Gates

ALLOFF

ALLON

Clk Ratio

Core-Bus-

000.00E+00

Flaxbus-Flash

'1-1-1

1

'1-1-1

2

'1-1-1

4

'1-1-1

6.25

'1-1-1

12.5

'1-1-1

25

'1-1-2

50

'1-2-3

75

'1-2-4

100

'1-2-5

120

Core Freq (MHz)

Figure 3. Run mode supply current vs. core frequency

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

15

NXP Semiconductors

General

Very Low Power Run (VLPR) Current vs Core Frequency

Temp (C)=25, V =3.6V, CACHE=ENABLE, Code Residence=Flash

DD

1.40E-03

1.20E-03

1.00E-03

800.00E-06

600.00E-06

400.00E-06

200.00E-06

000.00E+00

All Peripheral Clk Gates

ALLOFF

ALLON

Clk Ratio

Core-Bus-Flash

'1-1-2

'1-1-1

'1-2-4

'1-1-4

2

'1-1-2

'1-2-4

'1-1-4

Core Freq (MHz)

1

4

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 8. EMC radiated emissions operating behaviors

Symbol

Description

Frequency

band

Typ.

Unit

Notes

(MHz)

144 LQFP

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

16

22

21

16

L

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement

of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and

16

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

General

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.

The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,

from among the measured orientations in each frequency range.

2. V_DD= 3.3 V, T_A= 25 °C, f_OSC= 12 MHz (crystal), f_SYS= 96 MHz, f_BUS= 48MHz

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com.

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 9. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

7

C_{IN_D}

—

pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 10. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

Normal run mode

f_SYS

System and core clock

—

120

—

MHz

System and core clock when Full Speed USB in

operation

20

f_ENET

System and core clock when ethernet in operation

MHz

• 10 Mbps

• 100 Mbps

5

—

60

50

25

50

—

f_BUS

Bus clock

MHz

FB_CLK

f_FLASH

FlexBus clock

Flash clock

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Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

17

NXP Semiconductors

General

Table 10. Device clock specifications (continued)

Symbol

Description

Min.

Max.

Unit

Notes

f_LPTMR

LPTMR clock

—

25

MHz

VLPR mode¹

f_SYS

f_BUS

System and core clock

Bus clock

—

4

MHz

FB_CLK

f_FLASH

FlexBus clock

4

Flash clock

0.8

16

25

16

8

f_ERCLK

f_{LPTMR_pin}

External reference clock

LPTMR clock

f_{LPTMR_ERCLK}LPTMR external reference clock

f_{FlexCAN_ERCLK}FlexCAN external reference clock

f_{I2S_MCLK}

f_{I2S_BCLK}

I2S master clock

I2S bit clock

12.5

4

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

CAN, CMT, IEEE 1588 timer, timers, and I²C signals.

Table 11. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

100

50

—

ns

3

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External reset pulse width (digital glitch filter disabled)

100

2

—

Mode select (EZP_CS) hold time after reset

deassertion

Bus clock

cycles

Port rise and fall time (high drive strength) - 3 V

• Slew disabled

4

• 1.71 ≤ V_DD≤ 2.7V

—

8

6

ns

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

—

18

ns

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18

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

General

Notes

4

Table 11. General switching specifications (continued)

Symbol

Description

• 1.71 ≤ V_DD≤ 2.7V

Min.

Max.

Unit

—

12

ns

• 2.7 ≤ V_DD≤ 3.6V

Port rise and fall time (high drive strength) - 5 V

• Slew disabled

• 1.71 ≤ V_DD≤ 2.7V

—

6

4

ns

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

—

24

14

ns

• 2.7 ≤ V_DD≤ 3.6V

Port rise and fall time (low drive strength) - 3 V

• Slew disabled

5

• 1.71 ≤ V_DD≤ 2.7V

—

12

6

ns

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

—

24

16

ns

• 2.7 ≤ V_DD≤ 3.6V

Port rise and fall time (low drive strength) - 5 V

• Slew disabled

5

• 1.71 ≤ V_DD≤ 2.7V

—

17

10

ns

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

—

36

20

ns

• 2.7 ≤ V_DD≤ 3.6V

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses

may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter

pulses can be recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,

and VLLSx modes.

4. 25 pF load

5. 15 pF load

2.4 Thermal specifications

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

19

NXP Semiconductors

General

2.4.1 Thermal operating requirements

Table 12. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Die junction temperature

Ambient temperature¹

T_A

105

°C

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis:

T_J= T_A+ R_θJAx chip power dissipation

2.4.2 Thermal attributes

Table 13. Thermal attributes

Board type

Symbol

Descriptio 144 LQFP

n

144

MAPBGA

121

XFBGA

100 LQFP

51

Unit

°C/W

Notes

Single-layer R_θJA

(1s)

Thermal

51

43

42

36

38.1

33.3

1

resistance,

junction to

ambient

(natural

convection)

Four-layer

(2s2p)

R_θJA

Thermal

21.6

30.8

18

21.1

26.2

17.8

39

41

32

°C/W

resistance,

junction to

ambient

(natural

convection)

Single-layer R_θJMA

(1s)

Thermal

resistance,

junction to

ambient

(200 ft./min.

air speed)

Four-layer

(2s2p)

R_θJMA

Thermal

resistance,

junction to

ambient

(200 ft./min.

air speed)

—

R_θJB

Thermal

resistance,

junction to

board

30

11

16.5

8.9

16.3

12

24

11

°C/W

2

3

R_θJC

Thermal

resistance,

Table continues on the next page...

20

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 13. Thermal attributes (continued)

Board type

Symbol

Descriptio 144 LQFP

n

144

MAPBGA

121

XFBGA

100 LQFP

Unit

Notes

junction to

case

—

Ψ_JT

Thermal

characteriza

tion

2

0.9

0.2

2

°C/W

4

parameter,

junction to

package top

outside

center

(natural

convection)

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test

Method Environmental Conditions—Forced Convection (Moving Air).

2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material

between the top of the package and the cold plate.

4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 14. Debug trace operating behaviors

Symbol

T_cyc

T_wl

Description

Min.

Max.

Unit

MHz

ns

Clock period

Frequency dependent

Low pulse width

High pulse width

Clock and data rise time

Clock and data fall time

Data setup

2

—

3

T_wh

T_r

ns

—

1.5

1

ns

T_f

3

ns

T_s

—

ns

T_h

Data hold

ns

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

21

NXP Semiconductors

Peripheral operating requirements and behaviors

TRACECLK

T

r

T

f

T

wh

T

wl

T

cyc

Figure 5. TRACE_CLKOUT specifications

TRACE_CLKOUT

TRACE_D[3:0]

Ts

Th

Ts

Th

Figure 6. Trace data specifications

3.1.2 JTAG electricals

Table 15. JTAG limited voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

2.7

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

25

50

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

20

10

—

ns

• JTAG and CJTAG

• Serial Wire Debug

J4

J5

TCLK rise and fall times

—

20

2.6

—

8

3

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

—

25

—

J6

J7

J8

J9

J10

1

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22

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 15. JTAG limited voltage range electricals (continued)

Symbol

J11

Description

Min.

—

Max.

17

Unit

ns

TCLK low to TDO data valid

TCLK low to TDO high-Z

TRST assert time

J12

—

17

ns

J13

100

8

—

ns

J14

TRST setup time (negation) to TCLK high

—

ns

Table 16. JTAG full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

20

40

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

25

—

ns

• JTAG and CJTAG

• Serial Wire Debug

12.5

J4

J5

TCLK rise and fall times

—

20

0

3

—

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

J6

—

J7

—

8

25

—

J8

J9

J10

J11

J12

J13

J14

2.9

—

100

8

—

22.1

—

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

—

J2

J4

J3

TCLK (input)

J4

Figure 7. Test clock input timing

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

23

NXP Semiconductors

Peripheral operating requirements and behaviors

TCLK

J5

J6

Input data valid

Data inputs

Data outputs

J7

Output data valid

J8

J7

Output data valid

Figure 8. Boundary scan (JTAG) timing

TCLK

TDI/TMS

TDO

J9

J10

Input data valid

J11

Output data valid

J12

J11

TDO

Output data valid

TDO

Figure 9. Test Access Port timing

24

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

TCLK

TRST

J14

J13

Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG specifications

Table 17. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}

f_{ints_t}

I_ints

Internal reference frequency (slow clock) —

factory trimmed at nominal VDD and 25 °C

—

32.768

—

kHz

Internal reference frequency (slow clock) —

user trimmed

31.25

—

39.0625

kHz

Internal reference (slow clock) current

—

20

—

µA

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

0.3

0.6

%f_dco

1

Δf_{dco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM only

—

0.2

0.5

%f_dco

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

0.5

0.3

2

1

%f_dco

¹, 2

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

f_{intf_ft}

f_{intf_t}

I_intf

Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

—

3

4

—

5

MHz

µA

Internal reference frequency (fast clock) —

user trimmed at nominal VDD and 25 °C

—

25

Internal reference (fast clock) current

—

Table continues on the next page...

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25

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 17. MCG specifications (continued)

Symbol Description

f_{loc_low}Loss of external clock minimum frequency —

RANGE = 00

Min.

Typ.

Max.

Unit

Notes

(3/5) x

f_{ints_t}

—

kHz

f_{loc_high}Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

—

kHz

FLL

f_{fll_ref}

f_dco

FLL reference frequency range

31.25

20

—

39.0625

25

kHz

DCO output

Low range (DRS=00)

20.97

MHz

3, 4

frequency range

640 × f_{fll_ref}

Mid range (DRS=01)

1280 × f_{fll_ref}

40

60

80

—

41.94

62.91

83.89

23.99

47.97

71.99

95.98

50

75

100

—

MHz

ps

Mid-high range (DRS=10)

1920 × f_{fll_ref}

High range (DRS=11)

2560 × f_{fll_ref}

f_{dco_t_DMX3}DCO output

Low range (DRS=00)

732 × f_{fll_ref}

5, 6

frequency

2

Mid range (DRS=01)

1464 × f_{fll_ref}

—

Mid-high range (DRS=10)

2197 × f_{fll_ref}

—

High range (DRS=11)

2929 × f_{fll_ref}

—

J_{cyc_fll}

FLL period jitter

—

180

150

—

• f_DCO= 48 MHz

• f_DCO= 98 MHz

t_{fll_acquire}FLL target frequency acquisition time

—

1

ms

7

PLL

f_vco

I_pll

VCO operating frequency

48.0

—

120

—

MHz

µA

PLL operating current

8

1060

• PLL @ 96 MHz (f_{osc_hi_1}= 8 MHz, f_{pll_ref}

= 2 MHz, VDIV multiplier = 48)

I_pll

PLL operating current

—

600

—

µA

• PLL @ 48 MHz (f_{osc_hi_1}= 8 MHz, f_{pll_ref}

= 2 MHz, VDIV multiplier = 24)

f_{pll_ref}

PLL reference frequency range

PLL period jitter (RMS)

• f_vco= 48 MHz

2.0

4.0

MHz

J_{cyc_pll}

9

—

120

80

—

ps

• f_vco= 120 MHz

J_{acc_pll}

PLL accumulated jitter over 1µs (RMS)

Table continues on the next page...

26

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

Table 17. MCG specifications (continued)

Symbol Description

• f_vco= 48 MHz

Min.

Typ.

Max.

Unit

Notes

—

1350

—

ps

• f_vco= 120 MHz

—

600

—

ps

D_lock

D_unl

Lock entry frequency tolerance

Lock exit frequency tolerance

Lock detector detection time

1.49

4.47

—

2.98

5.97

150 × 10^-6

+ 1075(1/

%

s

t_{pll_lock}

10

f_{pll_ref}

)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. 2 V <= VDD <= 3.6 V.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency

deviation (Δf_{dco_t}) over voltage and temperature should be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Excludes any oscillator currents that are also consuming power while PLL is in operation.

9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this

specification assumes it is already running.

3.3.2 IRC48M specifications

Table 18. IRC48M specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Notes

Supply voltage

I_DD48M

f_irc48m

Supply current

400

48

500

—

μA

Internal reference frequency

—

MHz

Δf_{irc48m_ol_lv}Open loop total deviation of IRC48M frequency at

low voltage (VDD=1.71V-1.89V) over full

temperature

1

—

0.5

1.5

2.0

%f_irc48m

• Regulator disable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)

• Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M frequency at

high voltage (VDD=1.89V-3.6V) over full

temperature

1

—

0.5

1.5

%f_irc48m

• Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)

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27

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 18. IRC48M specifications (continued)

Symbol

Description

Min.

Typ.

0.5

—

Max.

1.0

Unit

%f_irc48m

%f_host

Notes

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M frequency at

high voltage (VDD=1.89V-3.6V) over 0 to 85 °C

• Regulator enable

1

—

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)

Δf_{irc48m_cl}Closed loop total deviation of IRC48M frequency

—

0.1

2

3

over voltage and temperature

J_{cyc_irc48m}Period Jitter (RMS)

—

35

2

150

3

ps

μs

t_irc48mst

Startup time

1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard

deviation (mean 3 sigma)

2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It

is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover

function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).

3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the

clock by setting USB_CLK_RECOVER_IRC_EN[IRC_EN]=1.

3.3.3 Oscillator electrical specifications

3.3.3.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_DD

Supply voltage

1.71

—

3.6

V

I_DDOSC

Supply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSC

Supply current — high-gain mode (HGO=1)

1

• 32 kHz

—

25

400

500

2.5

3

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

Table continues on the next page...

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

28

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 19. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

—

Typ.

—

Max.

—

Unit

Notes

2, 3

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

Feedback resistor — low-frequency, low-power

mode (HGO=0)

—

MΩ

kΩ

2, 4

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-power

mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

0

—

kΩ

V

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

0.6

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_xand C_ycan be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other device.

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

29

NXP Semiconductors

Peripheral operating requirements and behaviors

3.3.3.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

3

8

—

8

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

50

60

—

MHz

%

1, 2

3, 4

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

register being set.

NOTE

The 32 kHz oscillator works in low power mode by default

and cannot be moved into high power/gain mode.

3.3.4 32 kHz oscillator electrical characteristics

3.3.4.1 32 kHz oscillator DC electrical specifications

Table 21. 32kHz oscillator DC electrical specifications

Symbol

V_BAT

R_F

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

Internal feedback resistor

100

—

MΩ

Table continues on the next page...

30

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

Table 21. 32kHz oscillator DC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

C_para

Parasitical capacitance of EXTAL32 and

XTAL32

—

5

7

pF

1

V_pp

Peak-to-peak amplitude of oscillation

—

0.6

—

V

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

3.3.4.2 32 kHz oscillator frequency specifications

Table 22. 32 kHz oscillator frequency specifications

Symbol Description

Min.

—

Typ.

32.768

1000

32.768

—

Max.

—

Unit

kHz

ms

Notes

f_{osc_lo}

t_start

Oscillator crystal

Crystal start-up time

—

1

2

f_{ec_extal32}Externally provided input clock frequency

v_{ec_extal32}Externally provided input clock amplitude

—

kHz

mV

700

V_BAT

2, 3

1. Proper PC board layout procedures must be followed to achieve specifications.

2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

3. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the

applied clock must be within the range of V_SSto V_BAT

.

3.4 Memories and memory interfaces

3.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps

are active and do not include command overhead.

Table 23. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

Max.

18

Unit

μs

Notes

t_hvpgm8Program Phrase high-voltage time

t_hversscrErase Flash Sector high-voltage time

t_hversblk128kErase Flash Block high-voltage time for 128 KB

t_hversblk512kErase Flash Block high-voltage time for 512 KB

—

13

113

904

3616

ms

1

—

104

416

—

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

31

NXP Semiconductors

Peripheral operating requirements and behaviors

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 24. Flash command timing specifications

Symbol Description

Read 1s Block execution time

Min.

Typ.

Max.

Unit

Notes

t_rd1blk128k

t_rd1blk512k

• 128 KB data flash

—

0.5

1.8

ms

• 512 KB program flash

t_rd1sec4kRead 1s Section execution time (4 KB flash)

—

90

100

95

μs

1

t_pgmchk

t_rdrsrc

Program Check execution time

Read Resource execution time

Program Phrase execution time

Erase Flash Block execution time

• 128 KB data flash

40

t_pgm8

150

2

t_ersblk128k

t_ersblk512k

—

110

435

925

ms

• 512 KB program flash

3700

t_ersscr

Erase Flash Sector execution time

—

15

5

115

—

ms

2

t_pgmsec1kProgram Section execution time (1KB flash)

Read 1s All Blocks execution time

t_rd1allx

t_rd1alln

• FlexNVM devices

—

2.2

3.4

ms

• Program flash only devices

t_rdonce

Read Once execution time

—

70

30

—

μs

ms

μs

1

t_pgmonceProgram Once execution time

t_ersall

Erase All Blocks execution time

Verify Backdoor Access Key execution time

Swap Control execution time

• control code 0x01

870

—

7400

30

2

1

t_vfykey

t_swapx01

t_swapx02

t_swapx04

t_swapx08

—

200

70

—

150

30

μs

• control code 0x02

• control code 0x04

• control code 0x08

Program Partition for EEPROM execution time

• 32 KB FlexNVM

t_pgmpart32k

t_pgmpart128k

—

70

75

—

ms

• 128 KB FlexNVM

Set FlexRAM Function execution time:

• Control Code 0xFF

t_setramff

t_setram32k

t_setram64k

t_setram128k

—

70

0.8

1.3

2.4

—

μs

ms

• 32 KB EEPROM backup

• 64 KB EEPROM backup

• 128 KB EEPROM backup

1.2

1.9

3.1

Table continues on the next page...

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32

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 24. Flash command timing specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_eewr8bersByte-write to erased FlexRAM location

execution time

—

175

275

μs

3

Byte-write to FlexRAM execution time:

t_eewr8b32k

t_eewr8b64k

t_eewr8b128k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

• 128 KB EEPROM backup

—

385

475

650

1700

2000

2350

μs

t_eewr16bers16-bit write to erased FlexRAM location

execution time

—

175

275

μs

16-bit write to FlexRAM execution time:

t_eewr16b32k

t_eewr16b64k

t_eewr16b128k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

• 128 KB EEPROM backup

—

385

475

650

1700

2000

2350

μs

t_eewr32bers32-bit write to erased FlexRAM location

execution time

—

360

550

μs

32-bit write to FlexRAM execution time:

t_eewr32b32k

t_eewr32b64k

t_eewr32b128k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

• 128 KB EEPROM backup

—

630

810

2000

2250

2650

μs

1200

1. Assumes 25MHz or greater flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

3.4.1.3 Flash high voltage current behaviors

Table 25. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage flash

programming operation

—

3.5

7.5

mA

I_{DD_ERS}

Average current adder during high voltage flash

erase operation

—

1.5

4.0

mA

3.4.1.4 Reliability specifications

Table 26. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

5

50

—

years

Table continues on the next page...

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33

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 26. NVM reliability specifications (continued)

Symbol Description

Min.

20

Typ.¹

Max.

—

Unit

years

cycles

Notes

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

100

10 K

50 K

—

2

Data Flash

t_nvmretd10kData retention after up to 10 K cycles

t_nvmretd1kData retention after up to 1 K cycles

n_nvmcycdCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

2

FlexRAM as EEPROM

t_nvmretee100Data retention up to 100% of write endurance

t_nvmretee10Data retention up to 10% of write endurance

n_nvmcyceeCycling endurance for EEPROM backup

Write endurance

5

50

—

years

cycles

20

100

50 K

20 K

2

3

n_nvmwree16

n_nvmwree128

n_nvmwree512

n_nvmwree2k

n_nvmwree4k

• EEPROM backup to FlexRAM ratio = 16

• EEPROM backup to FlexRAM ratio = 128

• EEPROM backup to FlexRAM ratio = 512

• EEPROM backup to FlexRAM ratio = 2,048

• EEPROM backup to FlexRAM ratio = 4,096

140 K

1.26 M

5 M

400 K

3.2 M

12.8 M

50 M

—

writes

20 M

40 M

100 M

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T_j≤ 125°C.

3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the

cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values

assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.

3.4.1.5 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set

size can be set to any of several non-zero values.

The bytes not assigned to data flash via the FlexNVM partition code are used by the

FTFE to obtain an effective endurance increase for the EEPROM data. The built-in

EEPROM record management system raises the number of program/erase cycles that

can be attained prior to device wear-out by cycling the EEPROM data through a larger

EEPROM NVM storage space.

While different partitions of the FlexNVM are available, the intention is that a single

choice for the FlexNVM partition code and EEPROM data set size is used throughout

the entire lifetime of a given application. The EEPROM endurance equation and graph

shown below assume that only one configuration is ever used.

34

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Peripheral operating requirements and behaviors

EEPROM – 2 × EEESPLIT × EEESIZE

Writes_subsystem =

× Write_efficiency × n_nvmcycee

EEESPLIT × EEESIZE

where

• Writes_subsystem — minimum number of writes to each FlexRAM location for

subsystem (each subsystem can have different endurance)

• EEPROM — allocated FlexNVM for each EEPROM subsystem based on

DEPART; entered with the Program Partition command

• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program

Partition command

• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program

Partition command

• Write_efficiency —

• 0.25 for 8-bit writes to FlexRAM

• 0.50 for 16-bit or 32-bit writes to FlexRAM

• n_nvmcycee— EEPROM-backup cycling endurance

16/32-bit

8-bit

Ratio of EEPROM Backup to FlexRAM

Figure 11. EEPROM backup writes to FlexRAM

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

35

NXP Semiconductors

Peripheral operating requirements and behaviors

3.4.2 EzPort switching specifications

Table 27. EzPort switching specifications

Num

Description

Min.

1.71

—

Max.

3.6

Unit

V

Operating voltage

EP1

EZP_CK frequency of operation (all commands except

READ)

f_SYS/2

MHz

EP1a

EP2

EP3

EP4

EP5

EP6

EP7

EP8

EP9

EZP_CK frequency of operation (READ command)

EZP_CS negation to next EZP_CS assertion

EZP_CS input valid to EZP_CK high (setup)

EZP_CK high to EZP_CS input invalid (hold)

EZP_D input valid to EZP_CK high (setup)

EZP_CK high to EZP_D input invalid (hold)

EZP_CK low to EZP_Q output valid

—

f_SYS/8

—

MHz

ns

2 x t_{EZP_CK}

5

—

ns

—

ns

2

—

ns

5

—

ns

—

0

18

—

ns

EZP_CK low to EZP_Q output invalid (hold)

EZP_CS negation to EZP_Q tri-state

ns

—

12

ns

EZP_CK

EP2

EP3

EP4

EZP_CS

EP9

EP8

EP7

EZP_Q (output)

EZP_D (input)

EP5

EP6

Figure 12. EzPort Timing Diagram

36

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

3.4.3 Flexbus switching specifications

All processor bus timings are synchronous; input setup/hold and output delay are

given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK

frequency may be the same as the internal system bus frequency or an integer divider

of that frequency.

The following timing numbers indicate when data is latched or driven onto the

external bus, relative to the Flexbus output clock (FB_CLK). All other timing

relationships can be derived from these values.

Table 28. Flexbus limited voltage range switching specifications

Num

Description

Min.

2.7

—

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

Clock period

FB_CLK

—

MHz

ns

FB1

FB2

FB3

FB4

FB5

20

Address, data, and control output valid

Address, data, and control output hold

Data and FB_TA input setup

Data and FB_TA input hold

—

11.5

—

ns

1

2

0.5

8.5

0.5

ns

—

ns

—

ns

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],

FB_ALE, and FB_TS.

2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 29. Flexbus full voltage range switching specifications

Num

Description

Min.

1.71

—

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

Clock period

FB_CLK

—

MHz

ns

FB1

FB2

FB3

FB4

FB5

1/FB_CLK

—

Address, data, and control output valid

Address, data, and control output hold

Data and FB_TA input setup

Data and FB_TA input hold

13.5

—

ns

1

2

0

ns

15.5

0.5

—

ns

—

ns

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],

FB_ALE, and FB_TS.

2. Specification is valid for all FB_AD[31:0] and FB_TA.

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

37

NXP Semiconductors

Peripheral operating requirements and behaviors

Read Timing Parameters

S0

S1

S2

S3

S0

FB1

FB_CLK

FB_A[Y]

FB_D[X]

FB_RW

FB5

FB3

Address

FB4

FB2

Address

Data

FB_TS

FB_ALE

FB_CSn

FB_OEn

FB_BEn

FB_TA

AA=1

AA=0

FB4

FB5

AA=1

AA=0

FB_TSIZ[1:0]

TSIZ

S1

S0

S2

S3

S0

Figure 13. FlexBus read timing diagram

38

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

Write Timing Parameters

FB1

FB_CLK

FB_A[Y]

FB_D[X]

FB_RW

FB2

FB3

Address

Data

FB_TS

FB_ALE

FB_CSn

FB_OEn

FB_BEn

FB_TA

AA=1

AA=0

FB4

FB5

AA=1

AA=0

FB_TSIZ[1:0]

TSIZ

Figure 14. FlexBus write timing diagram

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

39

NXP Semiconductors

Peripheral operating requirements and behaviors

3.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 30 and Table 31 are achievable on the

differential pins ADCx_DP0, ADCx_DM0.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

3.6.1.1 16-bit ADC operating conditions

Table 30. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.71

-100

1.13

Typ.¹

Max.

3.6

Unit

V

Notes

V_DDA

ΔV_DDA

ΔV_SSA

V_REFH

Supply voltage

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

0

+100

V_DDA

mV

V

2

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

ADC reference

voltage high

V_DDA

V_REFL

ADC reference

voltage low

V_SSA

V

V_ADIN

C_ADIN

Input voltage

V_REFL

—

8

V_REFH

10

V

Input

• 16-bit mode

pF

capacitance

• 8-bit / 10-bit / 12-bit

modes

—

4

5

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

3

—

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

2.0

—

18.0

12.0

MHz

4

5

ADC conversion 16-bit mode

clock frequency

ADC conversion ≤ 13-bit modes

rate

No ADC hardware averaging

20.000

37.037

—

818.330

461.467

ksps

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

5

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

40

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

SIMPLIFIED

INPUT PIN EQUIVALENT

ZADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

ZAS

leakage

due to

input

ADC SAR

ENGINE

RAS

RADIN

protection

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 15. ADC input impedance equivalency diagram

3.6.1.2 16-bit ADC electrical characteristics

Table 31. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

mA

3

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

Table continues on the next page...

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

41

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 31. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

—

Typ.²

Max.

6.8

Unit

Notes

TUE

Total unadjusted

error

• 12-bit modes

• <12-bit modes

4

LSB⁴

5

—

1.4

2.1

DNL

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

LSB⁴

5

–0.3 to

0.5

INL

Integral non-linearity

• 12-bit modes

• <12-bit modes

—

1.0

0.5

–2.7 to

+1.9

5

–0.7 to

+0.5

5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

6

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

dB

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

7

dB

—

-94

-85

—

16-bit single-ended mode

• Avg = 32

—

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

dB

82

78

95

90

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's

voltage and

Table continues on the next page...

42

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

Table 31. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 16. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

43

NXP Semiconductors

Peripheral operating requirements and behaviors

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

11.00

Averaging of 4 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 17. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

3.6.2 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

50

250

—

7

—

0.5

200

600

40

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

μA

LSB³

LSB

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

44

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

0.08

0.07

0.06

HYSTCTR

Setting

0.05

0.04

0.03

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

45

NXP Semiconductors

Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.6.3 12-bit DAC electrical characteristics

3.6.3.1 12-bit DAC operating requirements

Table 33. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

1.71

1.13

—

Max.

3.6

100

1

Unit

V

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

V

1

2

pF

mA

I_L

—

1. The DAC reference can be selected to be V_DDAor V_REFH

.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

46

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Peripheral operating requirements and behaviors

3.6.3.2 12-bit DAC operating behaviors

Table 34. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

150

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

μA

P

I_{DDA_DACH}Supply current — high-speed mode

—

100

15

700

200

30

μA

μs

P

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

1

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

t_CCDACLPCode-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-

speed mode

0.7

1

V_dacoutlDAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

—

100

mV

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

V_DACR

INL

DNL

Integral non-linearity error — high speed

mode

—

8

1

LSB

2

3

4

Differential non-linearity error — V_DACR> 2

V

Differential non-linearity error — V_DACR

VREF_OUT

=

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

60

—

0.4

0.1

0.8

0.6

90

%FSR

dB

5

—

T_CO

T_GE

A_C

Temperature coefficient offset voltage

Temperature coefficient gain error

Offset aging coefficient

3.7

—

μV/C

%FSR/C

μV/yr

Ω

6

0.000421

—

100

250

Rop

SR

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

—

V/μs

• High power (SP_HP

• Low power (SP_LP

)

1.2

1.7

—

)

0.05

0.12

CT

Channel to channel cross talk

3dB bandwidth

—

-80

dB

BW

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

40

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

47

NXP Semiconductors

Peripheral operating requirements and behaviors

6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

to 0x800, temperature range is across the full range of the device

8

6

4

2

0

-2

-4

-6

-8

0

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 20. Typical INL error vs. digital code

48

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

55

85

25

105

125

-40

Temperature °C

Figure 21. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 35. VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Supply voltage

Temperature

Min.

Max.

Unit

Notes

—

1.71

3.6

V

Operating temperature

range of the device

°C

—

C_L

Output load capacitance

100

nF

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature

range of the device.

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

49

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 36. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim at

1.192

1.195

1.198

V

1

nominal V_DDAand temperature= 25 °C

V_out

Voltage reference output with user trim at

nominal V_DDAand temperature= 25 °C

1.1945

1.195

1.1955

V

1

V_step

V_tdrift

Voltage reference trim step

—

0.5

2

—

mV

1

Temperature drift (Vmax -Vmin across the full

temperature range)

15

I_bg

I_lp

Bandgap only current

—

60

80

µA

uA

mA

µV

1

Low-power buffer current

High-power buffer current

180

480

360

960

I_hp

1

ΔV_LOADLoad regulation

• current = 1.0 mA

1, 2

—

200

—

T_stup

Buffer startup time

100

35

µs

—

1

T_{chop_osc_st}Internal bandgap start-up delay with chop

ms

oscillator enabled

up

V_vdrift

Voltage drift (Vmax -Vmin across the full voltage

range)

—

0.5

2

mV

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 37. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

50

°C

—

Table 38. VREF limited-range operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim

1.173

1.225

V

—

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

50

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Peripheral operating requirements and behaviors

3.8.1 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

3.8.1.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range

of transceiver devices.

Table 39. MII signal switching specifications

Symbol

—

Description

Min.

—

Max.

25

Unit

MHz

RXCLK frequency

RXCLK pulse width high

MII1

35%

65%

RXCLK

period

RXCLK

period

ns

MII2

RXCLK pulse width low

35%

65%

MII3

MII4

—

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

5

—

ns

—

25

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK

period

TXCLK

period

ns

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

MII6

MII5

MII7

TXCLK (input)

MII8

Valid data

TXD[n:0]

TXEN

Valid data

TXER

Figure 22. RMII/MII transmit signal timing diagram

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51

NXP Semiconductors

Peripheral operating requirements and behaviors

MII2

MII3

MII1

MII4

RXCLK (input)

RXD[n:0]

RXDV

Valid data

RXER

Figure 23. RMII/MII receive signal timing diagram

3.8.1.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a range

of transceiver devices.

Table 40. RMII signal switching specifications

Num

—

Description

Min.

—

Max.

50

Unit

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RMII8

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

—

15

ns

4

RMII_CLK to TXD[1:0], TXEN valid

—

3.8.1.3 MDIO serial management timing specifications

Table 41. MDIO serial management channel signal timing

Num

E10

E11

E12

E13

E14

E15

Characteristic

MDC cycle time

Symbol

Min

400

40

—

Max

—

Unit

ns

t_MDC

MDC pulse width

60

% t_MDC

ns

MDC to MDIO output valid

MDC to MDIO output invalid

MDIO input to MDC setup

MDIO input to MDC hold

375

—

25

10

0

ns

—

ns

—

ns

52

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

E10

E11

MDC (Output)

MDIO (Output)

MDIO (Input)

E11

E12

E13

Valid Data

E14

E15

Valid Data

Figure 24. MDIO serial management channel timing diagram

3.8.2 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards

documented by the Universal Serial Bus Implementers Forum. For the most up-to-

date standards, visit usb.org.

NOTE

The MCGPLLCLK meets the USB jitter and signaling rate

specifications for certification with the use of an external

clock/crystal for both Device and Host modes.

The MCGFLLCLK does not meet the USB jitter or

signaling rate specifications for certification.

The IRC48M meets the USB jitter and signaling rate

specifications for certification in Device mode when the

USB clock recovery mode is enabled. It does not meet the

USB signaling rate specifications for certification in Host

mode operation.

3.8.3 USB DCD electrical specifications

Table 42. USB0 DCD electrical specifications

Symbol

V_{DP_SRC}USB_DP source voltage (up to 250 μA)

V_LGCThreshold voltage for logic high

Description

Min.

0.5

Typ.

—

Max.

0.7

Unit

V

0.8

—

2.0

V

Table continues on the next page...

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

53

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 42. USB0 DCD electrical specifications (continued)

Symbol

Description

Min.

7

Typ.

10

Max.

13

Unit

μA

kΩ

V

I_{DP_SRC}

USB_DP source current

I_{DM_SINK}USB_DM sink current

50

100

—

150

24.8

0.4

R_{DM_DWN}D- pulldown resistance for data pin contact detect

V_{DAT_REF}Data detect voltage

14.25

0.25

0.33

3.8.4 USB VREG electrical specifications

Table 43. USB VREG electrical specifications

Symbol Description

Min.

2.7

—

Typ.¹

Max.

5.5

Unit

Notes

VREGIN Input supply voltage

—

V

I_DDon

I_DDstby

I_DDoff

Quiescent current — Run mode, load current

equal zero, input supply (VREGIN) > 3.6 V

125

186

μA

Quiescent current — Standby mode, load

current equal zero

—

1.1

10

μA

Quiescent current — Shutdown mode

—

650

—

4

nA

μA

• VREGIN = 5.0 V and temperature=25 °C

• Across operating voltage and temperature

I_LOADrunMaximum load current — Run mode

I_LOADstbyMaximum load current — Standby mode

—

120

1

mA

V_Reg33outRegulator output voltage — Input supply

(VREGIN) > 3.6 V

• Run mode

3

3.3

2.8

—

3.6

V

• Standby mode

2.1

V_Reg33outRegulator output voltage — Input supply

(VREGIN) < 3.6 V, pass-through mode

2

C_OUT

ESR

External output capacitor

1.76

1

2.2

—

8.16

100

μF

External output capacitor equivalent series

resistance

mΩ

I_LIM

Short circuit current

—

290

—

mA

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load

.

3.8.5 CAN switching specifications

See General switching specifications.

54

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Peripheral operating requirements and behaviors

3.8.6 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 44. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

30

Unit

V

Notes

Operating voltage

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

2 x t_BUS

—

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

(t_BUSx 2) −

2

—

ns

1

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

2

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

−2

15

0

8.5

—

ns

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 25. DSPI classic SPI timing — master mode

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 45. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

Unit

V

Operating voltage

2.7

3.6

Frequency of operation

15¹

MHz

ns

DS9

DSPI_SCK input cycle time

4 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) − 2

(t_SCK/2) + 2

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

10

—

14

ns

2

ns

7

ns

—

ns

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,

when bus clock is 60MHz, SPI clock should not be greater than 10MHz

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 26. DSPI classic SPI timing — slave mode

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Peripheral operating requirements and behaviors

3.8.7 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provides DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 46. Master mode DSPI timing (full voltage range)

Num

Description

Min.

1.71

Max.

3.6

15

Unit

V

Notes

Operating voltage

1

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

4 x t_BUS

—

(t_SCK/2) - 4 (t_SCK/2)+ 4

ns

(t_BUSx 2) −

4

—

ns

2

3

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

4

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-4.5

21

0

10

—

ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 27. DSPI classic SPI timing — master mode

Table 47. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 47. Slave mode DSPI timing (full voltage range) (continued)

Num

Description

Min.

Max.

Unit

MHz

ns

Frequency of operation

—

7.5

DS9

DSPI_SCK input cycle time

8 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) - 4

(t_SCK/2)+ 4

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

23.5

—

ns

4

—

ns

7

—

ns

—

21

19

ns

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 28. DSPI classic SPI timing — slave mode

3.8.8 Inter-Integrated Circuit Interface (I²C) timing

Table 48. I ²C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

400¹

SCL Clock Frequency

f_SCL

0

kHz

µs

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

4

—

0.6

—

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.25

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

0.6

Data hold time for I²C bus devices

t_HD; DAT

0²

3.45³

0⁴

0.9²

µs

Table continues on the next page...

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58

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 48. I ²C timing (continued)

Characteristic

Symbol

Standard Mode

Fast Mode

Unit

Minimum Maximum

Minimum

Maximum

Data set-up time

t_SU; DAT

250⁵

—

1000

300

—

100^{3, 6}

20 +0.1C_b

0.6

—

300

—

ns

µs

7

6

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

t_r

t_f

—

t_SU; STO

t_BUF

4

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the

High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.

2. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and

SCL lines.

3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. Input signal Slew = 10 ns and Output Load = 50 pF

5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

6. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT}≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax

+ t_{SU; DAT}= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is

released.

7. C_b= total capacitance of the one bus line in pF.

Table 49. I ²C 1 Mbps timing

Characteristic

Symbol

f_SCL

Minimum

Maximum

Unit

MHz

µs

SCL Clock Frequency

0

1¹

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

t_HD; STA

0.26

—

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time for I₂C bus devices

Data set-up time

t_LOW

t_HIGH

0.5

0.26

0

—

µs

ns

µs

t_SU; STA

t_HD; DAT

t_SU; DAT

t_r

—

50

—

, 2

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

20 +0.1C_b

0.26

120

—

2

t_f

t_SU; STO

t_BUF

Bus free time between STOP and START

condition

0.5

—

Pulse width of spikes that must be suppressed by

the input filter

t_SP

0

50

ns

1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins

across the full voltage range.

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59

NXP Semiconductors

Peripheral operating requirements and behaviors

2. C_b= total capacitance of the one bus line in pF.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 29. Timing definition for devices on the I²C bus

3.8.9 UART switching specifications

See General switching specifications.

3.8.10 SDHC specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

Table 50. SDHC switching specifications

Num

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

Card input clock

SD1

fpp

f_OD

t_WL

t_WH

t_TLH

t_THL

Clock frequency (low speed)

0

400

25\50

20\50

400

—

kHz

MHz

kHz

ns

Clock frequency (SD\SDIO full speed\high speed)

Clock frequency (MMC full speed\high speed)

Clock frequency (identification mode)

Clock low time

0

SD2

SD3

SD4

SD5

7

Clock high time

7

—

ns

Clock rise time

—

3

ns

Clock fall time

3

ns

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid) -5 8.3

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SD6

t_OD

ns

SD7

SD8

t_ISU

t_IH

SDHC input setup time

SDHC input hold time

5.5

0

—

ns

60

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Peripheral operating requirements and behaviors

SD3

SD6

SD2

SD1

SDHC_CLK

Output SDHC_CMD

Output SDHC_DAT[3:0]

Input SDHC_CMD

Input SDHC_DAT[3:0]

SD7

SD8

Figure 30. SDHC timing

3.8.11 I²S switching specifications

This section provides the AC timings for the I²S in master (clocks driven) and slave

modes (clocks input). All timings are given for non-inverted serial clock polarity

(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =

0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or

the frame sync (I2S_FS) shown in the figures below.

Table 51. I²S master mode timing

Num

Description

Min.

2.7

40

45%

80

45%

—

Max.

3.6

—

Unit

Operating voltage

V

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

I2S_BCLK cycle time

55%

—

MCLK period

ns

I2S_BCLK pulse width high/low

I2S_BCLK to I2S_FS output valid

I2S_BCLK to I2S_FS output invalid

I2S_BCLK to I2S_TXD valid

I2S_BCLK to I2S_TXD invalid

I2S_RXD/I2S_FS input setup before I2S_BCLK

I2S_RXD/I2S_FS input hold after I2S_BCLK

55%

15

BCLK period

ns

0

—

15

0

—

17

0

—

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Peripheral operating requirements and behaviors

S1

S2

I2S_MCLK (output)

I2S_BCLK (output)

I2S_FS (output)

I2S_FS (input)

I2S_TXD

S3

S4

S5

S7

S6

S10

S9

S7

S8

S9

S10

I2S_RXD

Figure 31. I²S timing — master mode

Table 52. I²S slave mode timing

Num

Description

Operating voltage

Min.

Max.

3.6

—

Unit

2.7

V

S11

S12

S13

S14

S15

S16

S17

S18

S19

I2S_BCLK cycle time (input)

80

45%

5

ns

I2S_BCLK pulse width high/low (input)

I2S_FS input setup before I2S_BCLK

I2S_FS input hold after I2S_BCLK

55%

—

MCLK period

ns

2

—

I2S_BCLK to I2S_TXD/I2S_FS output valid

I2S_BCLK to I2S_TXD/I2S_FS output invalid

I2S_RXD setup before I2S_BCLK

—

0

19.5

—

5

—

I2S_RXD hold after I2S_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

2

—

21

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

62

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NXP Semiconductors

Peripheral operating requirements and behaviors

S11

S12

I2S_BCLK (input)

I2S_FS (output)

I2S_FS (input)

I2S_TXD

S12

S15

S16

S13

S14

S19

S15

S16

S15

S16

S17

S18

I2S_RXD

Figure 32. I²S timing — slave modes

3.8.11.1 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 53. I2S/SAI master mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

40

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK (as an input) pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

45%

80

55%

—

MCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

55%

15

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

—

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

-1

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

15

—

ns

0

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

22.5

S10

I2S_RXD/I2S_RX_FS input hold after

I2S_RX_BCLK

0

—

ns

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63

NXP Semiconductors

Peripheral operating requirements and behaviors

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 33. I2S/SAI timing — master modes

Table 54. I2S/SAI slave mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

80

3.6

—

V

S11

S12

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

S13

S14

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

7

2

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

S15

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

—

3

25.5

—

ns

5.8

2

—

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

25

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

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NXP Semiconductors

Peripheral operating requirements and behaviors

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 34. I2S/SAI timing — slave modes

3.8.11.2 VLPR, VLPW, and VLPS mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in VLPR, VLPW, and VLPS modes.

Table 55. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

62.5

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

45%

250

55%

—

MCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

55%

45

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

—

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

45

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

45

0

S10

I2S_RXD/I2S_RX_FS input hold after

I2S_RX_BCLK

—

ns

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65

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Peripheral operating requirements and behaviors

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 35. I2S/SAI timing — master modes

Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

250

3.6

—

V

S11

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

S12

S13

S14

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

30

11

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

S15

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

—

0

ns

—

72

30

11

—

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

66

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Dimensions

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 36. I2S/SAI timing — slave modes

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

100-pin LQFP

Then use this document number

98ASS23308W

121-pin XFBGA

144-pin LQFP

98ASA00595D

98ASS23177W

98ASA00222D

144-pin MAPBGA

5 Pinout

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

67

NXP Semiconductors

Pinout

5.1 K64 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

—

L5

—

TAMPER0/ TAMPER0/

RTC_ RTC_

WAKEUP_ WAKEUP_

B

A1

100

—

PTD7 CMT_IRO

UART0_TX FTM0_CH7

FTM0_

FLT1

SPI1_SIN

A10

PTD8 I2C0_SCL

/

UART5_

RX

FB_A16

x_LLWU_

P24

x_LL

WU_

P24

A9

B1

—

PTD9 I2C0_SDA

UART5_TX

FB_A17

FB_A18

PTD1

0

UART5_

RTS_b

C2

—

PTD1 SPI2_

UART5_

CTS_b

SDHC0_

CLKIN

FB_A19

x_LLWU_

P25

1/

PCS0

x_LL

WU_

P25

C1

D2

D1

E1

—

PTD1 SPI2_SCK

2

FTM3_

FLT0

SDHC0_

D4

FB_A20

FB_A21

FB_A22

FB_A23

PTD1 SPI2_

SDHC0_

D5

3

SOUT

PTD1 SPI2_SIN

4

SDHC0_

D6

PTD1 SPI2_

SDHC0_

D7

5

PCS1

A11

—

D3

NC

1

—

K3

H4

1

ADC1_

SE4a

ADC1_

SE4a

PTE0

SPI1_

PCS1

UART1_TX SDHC0_

D1

TRACE_

CLKOUT

I2C1_SDA

I2C1_SCL

RTC_

CLKOUT

2

3

D2

D1

2

3

ADC1_

SE5a

ADC1_

SE5a

PTE1/

LLWU_P0

SPI1_

SOUT

UART1_

RX

SDHC0_

D0

TRACE_

D3

SPI1_SIN

LLWU_P0

LLWU_P1

ADC0_

DP2/

ADC0_

DP2/

PTE2/

LLWU_P1

SPI1_SCK

UART1_

CTS_b

SDHC0_

DCLK

TRACE_

D2

ADC1_

SE6a

ADC1_

SE6a

68

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

4

E4

4

ADC0_

DM2/

ADC0_

DM2/

PTE3

SPI1_SIN

UART1_

RTS_b

SDHC0_

CMD

TRACE_

D1

SPI1_

SOUT

ADC1_

SE7a

ADC1_

SE7a

5

6

7

E5

F6

E3

—

5

VDD

VSS

DISABLED

PTE4/

LLWU_P2

SPI1_

PCS0

UART3_TX SDHC0_

D3

TRACE_

D0

LLWU_P2

8

9

E2

E1

6

7

DISABLED

PTE5

SPI1_

PCS2

UART3_

RX

SDHC0_

D2

FTM3_CH0

PTE6/

x_LLWU_

P16

SPI1_

PCS3

UART3_

CTS_b

I2S0_

MCLK

FTM3_CH1 USB_

SOF_OUT

x_LLWU_

P16

10

11

12

F4

F3

F2

—

DISABLED

PTE7

UART3_

RTS_b

I2S0_

RXD0

FTM3_CH2

FTM3_CH3

FTM3_CH4

PTE8

I2S0_

RXD1

UART5_TX I2S0_RX_

FS

PTE9/

x_LLWU_

P17

I2S0_TXD1 UART5_

RX

I2S0_RX_

BCLK

x_LLWU_

P17

13

F1

—

DISABLED

PTE10/

x_LLWU_

P18

UART5_

CTS_b

I2S0_TXD0

FTM3_CH5

x_LLWU_

P18

14

15

G4

G3

—

DISABLED

PTE11

UART5_

RTS_b

I2S0_TX_

FS

FTM3_CH6

FTM3_CH7

PTE12

I2S0_TX_

BCLK

16

17

18

19

20

21

22

23

24

E6

F7

H3

H1

H2

G1

G2

J1

8

VDD

9

VSS

—

10

11

12

13

14

15

VSS

USB0_DP

USB0_DM

VOUT33

VREGIN

USB0_DP

USB0_DM

VOUT33

VREGIN

ADC0_DP1 ADC0_DP1

J2

ADC0_

DM1

ADC0_

DM1

25

26

K1

K2

16

17

ADC1_DP1 ADC1_DP1

ADC1_

DM1

ADC1_

DM1

27

L1

18

ADC0_

DP0/

ADC0_

DP0/

ADC1_DP3 ADC1_DP3

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

69

NXP Semiconductors

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

28

L2

19

ADC0_

DM0/

ADC1_

DM3

ADC0_

DM0/

ADC1_

DM3

29

30

M1

M2

20

21

ADC1_

DP0/

ADC0_DP3 ADC0_DP3

ADC1_

DP0/

ADC1_

DM0/

ADC1_

DM0/

ADC0_

DM3

ADC0_

DM3

31

32

33

34

35

H5

G5

G6

H6

K3

22

23

24

25

—

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

ADC1_

SE16/

ADC1_

SE16/

CMP2_IN2/ CMP2_IN2/

ADC0_

SE22

ADC0_

SE22

36

37

J3

—

ADC0_

SE16/

CMP1_IN2/ CMP1_IN2/

ADC0_

SE21

ADC0_

SE16/

ADC0_

SE21

M3

26

VREF_

OUT/

VREF_

OUT/

CMP1_IN5/ CMP1_IN5/

CMP0_IN5/ CMP0_IN5/

ADC1_

SE18

ADC1_

SE18

38

39

L3

L4

27

—

DAC0_

OUT/

CMP1_IN3/ CMP1_IN3/

ADC0_

SE23

DAC0_

OUT/

ADC0_

SE23

DAC1_

OUT/

DAC1_

OUT/

CMP0_IN4/ CMP0_IN4/

CMP2_IN3/ CMP2_IN3/

ADC1_

SE23

ADC1_

SE23

40

41

42

43

44

M7

M6

L6

—

28

29

30

—

XTAL32

EXTAL32

VBAT

XTAL32

EXTAL32

VBAT

VDD

—

VSS

70

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

45

46

M4

31

ADC0_

SE17

ADC0_

SE17

PTE24

UART4_TX

I2C0_SCL

I2C0_SDA

EWM_

OUT_b

K5

32

ADC0_

SE18

ADC0_

SE18

PTE25/

x_LLWU_

P21

UART4_

RX

EWM_IN

x_LLWU_

P21

47

48

K4

J4

33

—

DISABLED

PTE26

ENET_

1588_

CLKIN

UART4_

CTS_b

RTC_

CLKOUT

USB_

CLKIN

DISABLED

PTE27

UART4_

RTS_b

49

50

H4

J5

—

PTE28

PTA0

34

JTAG_

TCLK/

SWD_CLK/

EZP_CLK

UART0_

CTS_b/

UART0_

COL_b

FTM0_CH5

JTAG_

TCLK/

SWD_CLK

EZP_CLK

51

52

J6

35

36

JTAG_TDI/

EZP_DI

PTA1

PTA2

UART0_

RX

FTM0_CH6

JTAG_TDI

EZP_DI

K6

JTAG_

TDO/

UART0_TX FTM0_CH7

JTAG_

TDO/

EZP_DO

TRACE_

SWO/

TRACE_

SWO

EZP_DO

53

K7

37

JTAG_

TMS/

SWD_DIO

PTA3

UART0_

RTS_b

FTM0_CH0

FTM0_CH1

JTAG_

TMS/

SWD_DIO

54

55

L7

38

39

NMI_b/

EZP_CS_b

PTA4/

LLWU_P3

NMI_b

LLWU_P3

EZP_CS_b

M8

DISABLED

PTA5

USB_

CLKIN

FTM0_CH2 RMII0_

CMP2_

OUT

I2S0_TX_

BCLK

JTAG_

TRST_b

RXER/

MII0_

RXER

56

57

58

E7

G7

J7

40

41

—

VDD

VSS

DISABLED

PTA6

PTA7

PTA8

PTA9

FTM0_CH3

CLKOUT

TRACE_

CLKOUT

59

60

61

62

J8

K8

L8

—

ADC0_

SE10

ADC0_

SE10

FTM0_CH4

TRACE_

D3

ADC0_

SE11

ADC0_

SE11

FTM1_CH0

FTM1_

QD_PHA

TRACE_

D2

DISABLED

FTM1_CH1 MII0_RXD3

FTM2_CH0 MII0_RXD2

FTM1_

QD_PHB

TRACE_

D1

M9

DISABLED

PTA10/

x_LLWU_

P22

FTM2_

QD_PHA

TRACE_

D0

x_LLWU_

P22

63

L9

—

DISABLED

PTA11/

x_LLWU_

P23

FTM2_CH1 MII0_

RXCLK

I2C2_SDA

FTM2_

QD_PHB

x_LLWU_

P23

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

71

NXP Semiconductors

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

64

65

66

K9

J9

42

43

44

CMP2_IN0 CMP2_IN0 PTA12

CAN0_TX

CAN0_RX

FTM1_CH0 RMII0_

RXD1/

I2C2_SCL

I2C2_SDA

I2C2_SCL

I2S0_TXD0 FTM1_

QD_PHA

MII0_RXD1

CMP2_IN1 CMP2_IN1 PTA13/

FTM1_CH1 RMII0_

RXD0/

MII0_RXD0

UART0_TX RMII0_

CRS_DV/

I2S0_TX_

FS

FTM1_

QD_PHB

LLWU_P4

L10

DISABLED

PTA14

SPI0_

PCS0

I2S0_RX_

BCLK

I2S0_TXD1

MII0_

RXDV

67

68

L11

K10

45

46

DISABLED

PTA15

PTA16

SPI0_SCK

UART0_

RX

RMII0_

TXEN/

MII0_TXEN

I2S0_

RXD0

SPI0_

SOUT

UART0_

CTS_b/

UART0_

COL_b

RMII0_

TXD0/

MII0_TXD0

I2S0_RX_

FS

I2S0_

RXD1

69

K11

47

ADC1_

SE17

ADC1_

SE17

PTA17

SPI0_SIN

UART0_

RTS_b

RMII0_

TXD1/

I2S0_

MCLK

MII0_TXD1

70

71

72

E8

G8

48

49

50

VDD

VSS

M12

EXTAL0

PTA18

PTA19

FTM0_

FLT2

FTM_

CLKIN0

EXTAL0

73

M11

51

XTAL0

FTM1_

FLT0

FTM_

CLKIN1

LPTMR0_

ALT1

LPTMR0_

ALT1

74

75

76

L12

K12

J12

52

—

RESET_b

DISABLED

RESET_b

PTA24

PTA25

MII0_TXD2

FB_A29

FB_A28

MII0_

TXCLK

77

78

79

80

81

J11

J10

H12

H11

H10

—

53

DISABLED

PTA26

PTA27

PTA28

PTA29

MII0_TXD3

MII0_CRS

MII0_TXER

MII0_COL

FB_A27

FB_A26

FB_A25

FB_A24

ADC0_

SE8/

ADC1_SE8 ADC1_SE8

ADC0_

SE8/

PTB0/

LLWU_P5

I2C0_SCL

I2C0_SDA

I2C0_SCL

I2C0_SDA

FTM1_CH0 RMII0_

MDIO/

FTM1_

QD_PHA

LLWU_P5

MII0_MDIO

82

83

84

H9

54

55

56

ADC0_

SE9/

ADC1_SE9 ADC1_SE9

ADC0_

SE9/

PTB1

PTB2

PTB3

FTM1_CH1 RMII0_

MDC/

FTM1_

QD_PHB

MII0_MDC

G12

G11

ADC0_

SE12

ADC0_

SE12

UART0_

RTS_b

ENET0_

1588_

TMR0

FTM0_

FLT3

ADC0_

SE13

ADC0_

SE13

UART0_

CTS_b/

ENET0_

1588_

FTM0_

FLT0

TMR1

72

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

UART0_

COL_b

85

86

G10

G9

—

ADC1_

SE10

ADC1_

SE10

PTB4

ENET0_

1588_

TMR2

FTM1_

FLT0

ADC1_

SE11

ADC1_

SE11

PTB5

ENET0_

1588_

FTM2_

FLT0

TMR3

87

88

89

90

91

92

F12

F11

F10

F9

—

57

58

59

ADC1_

SE12

ADC1_

SE12

PTB6

PTB7

PTB8

PTB9

PTB10

PTB11

FB_AD23

FB_AD22

FB_AD21

FB_AD20

FB_AD19

FB_AD18

ADC1_

SE13

ADC1_

SE13

DISABLED

UART3_

RTS_b

DISABLED

SPI1_

PCS1

UART3_

CTS_b

E12

E11

ADC1_

SE14

ADC1_

SE14

SPI1_

PCS0

UART3_

RX

FTM0_

FLT1

ADC1_

SE15

ADC1_

SE15

SPI1_SCK

UART3_TX

FTM0_

FLT2

93

94

95

H7

F5

60

61

62

VSS

VDD

E10

DISABLED

PTB16

PTB17

PTB18

PTB19

PTB20

PTB21

PTB22

PTB23

PTC0

SPI1_

SOUT

UART0_

RX

FTM_

CLKIN0

FB_AD17

FB_AD16

FB_AD15

FB_OE_b

FB_AD31

FB_AD30

FB_AD29

FB_AD28

FB_AD14

EWM_IN

96

97

E9

63

64

65

66

67

68

69

70

71

72

DISABLED

SPI1_SIN

CAN0_TX

CAN0_RX

UART0_TX FTM_

CLKIN1

EWM_

OUT_b

D12

D11

D10

D9

FTM2_CH0 I2S0_TX_

BCLK

FTM2_

QD_PHA

98

FTM2_CH1 I2S0_TX_

FS

FTM2_

QD_PHB

99

SPI2_

PCS0

CMP0_

OUT

100

101

102

103

104

105

SPI2_SCK

CMP1_

OUT

C12

C11

B12

B11

A12

SPI2_

SOUT

CMP2_

OUT

SPI2_SIN

SPI0_

PCS5

ADC0_

SE14

ADC0_

SE14

SPI0_

PCS4

PDB0_

EXTRG

USB_

SOF_OUT

I2S0_TXD1

I2S0_TXD0

ADC0_

SE15

ADC0_

SE15

PTC1/

LLWU_P6

SPI0_

PCS3

UART1_

RTS_b

FTM0_CH0 FB_AD13

FTM0_CH1 FB_AD12

LLWU_P6

ADC0_

SE4b/

ADC0_

SE4b/

PTC2

SPI0_

PCS2

UART1_

CTS_b

I2S0_TX_

FS

CMP1_IN0 CMP1_IN0

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

73

NXP Semiconductors

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

106

A11

73

CMP1_IN1 CMP1_IN1 PTC3/

SPI0_

PCS1

UART1_

RX

FTM0_CH2 CLKOUT/

CLKOUT

I2S0_TX_

BCLK

LLWU_P7

107

108

109

H8

—

74

75

76

VSS

VDD

A9

DISABLED

PTC4/

LLWU_P8

SPI0_

PCS0

UART1_TX FTM0_CH3 FB_AD11

CMP1_

OUT

LLWU_P8

110

D8

77

DISABLED

PTC5/

LLWU_P9

SPI0_SCK

LPTMR0_

ALT2

I2S0_

RXD0

FB_AD10

CMP0_

OUT

FTM0_CH2

LLWU_P9/

LPTMR0_

ALT2

111

112

113

C8

B8

A8

78

79

80

CMP0_IN0 CMP0_IN0 PTC6/

CMP0_IN1 CMP0_IN1 PTC7

SPI0_

LLWU_P10 SOUT

PDB0_

EXTRG

I2S0_RX_

BCLK

FB_AD9

FB_AD8

FB_AD7

I2S0_

MCLK

LLWU_P10

SPI0_SIN

USB_

SOF_OUT

I2S0_RX_

FS

ADC1_

SE4b/

CMP0_IN2 CMP0_IN2

ADC1_

SE4b/

PTC8

PTC9

PTC10

FTM3_CH4 I2S0_

MCLK

114

D7

81

ADC1_

SE5b/

CMP0_IN3 CMP0_IN3

ADC1_

SE5b/

FTM3_CH5 I2S0_RX_

BCLK

FB_AD6

FTM2_

FLT0

115

116

117

118

119

C7

B7

A7

D6

C6

82

83

84

85

86

ADC1_

SE6b

ADC1_

SE6b

I2C1_SCL

I2C1_SDA

FTM3_CH6 I2S0_RX_

FS

FB_AD5

ADC1_

SE7b

ADC1_

SE7b

PTC11/

LLWU_P11

FTM3_CH7 I2S0_

RXD1

FB_RW_b

FB_AD27

FB_AD26

FB_AD25

FB_AD24

LLWU_P11

DISABLED

PTC12

PTC13

PTC14

PTC15

UART4_

RTS_b

FTM3_

FLT0

UART4_

CTS_b

UART4_

RX

120

121

122

123

B6

—

87

88

89

90

DISABLED

VSS

UART4_TX

VSS

VDD

—

VDD

A6

DISABLED

PTC16

UART3_

RX

ENET0_

1588_

TMR0

FB_CS5_b/

FB_TSIZ1/

FB_BE23_

16_

BLS15_8_

b

124

125

D5

C5

91

92

DISABLED

PTC17

PTC18

UART3_TX ENET0_

FB_CS4_b/

FB_TSIZ0/

FB_BE31_

24_BLS7_

0_b

1588_

TMR1

UART3_

RTS_b

ENET0_

1588_

FB_TBST_

b/

TMR2

FB_CS2_b/

FB_BE15_

74

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Pinout

144

100

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

QFP

MAP LQFP

BGA

8_BLS23_

16_b

126

127

B5

A5

—

DISABLED

PTC19

UART3_

CTS_b

ENET0_

1588_

TMR3

FB_CS3_b/ FB_TA_b

FB_BE7_

0_BLS31_

24_b

93

PTD0/

LLWU_P12 PCS0

SPI0_

UART2_

RTS_b

FTM3_CH0 FB_ALE/

FB_CS1_b/

LLWU_P12

FB_TS_b

128

129

D4

C4

94

95

ADC0_

SE5b

ADC0_

SE5b

PTD1

SPI0_SCK

UART2_

CTS_b

FTM3_CH1 FB_CS0_b

DISABLED

PTD2/

LLWU_P13 SOUT

SPI0_

UART2_

RX

FTM3_CH2 FB_AD4

I2C0_SCL

I2C0_SDA

LLWU_P13

LLWU_P14

130

131

B4

A4

96

97

DISABLED

PTD3

SPI0_SIN

UART2_TX FTM3_CH3 FB_AD3

PTD4/

LLWU_P14 PCS1

SPI0_

UART0_

RTS_b

FTM0_CH4 FB_AD2

EWM_IN

SPI1_

PCS0

132

A3

98

ADC0_

SE6b

ADC0_

SE6b

PTD5

SPI0_

PCS2

UART0_

CTS_b/

UART0_

COL_b

FTM0_CH5 FB_AD1

EWM_

OUT_b

SPI1_SCK

133

A2

99

ADC0_

SE7b

ADC0_

SE7b

PTD6/

LLWU_P15 PCS3

SPI0_

UART0_

RX

FTM0_CH6 FB_AD0

FTM0_

FLT0

SPI1_

SOUT

LLWU_P15

134

135

M10

F8

—

VSS

VDD

VSS

VDD

5.2 Unused analog interfaces

Table 57. Unused analog interfaces

Module name

Pins

Recommendation if unused

ADC

ADC0_DP1, ADC0_DM1, ADC1_DP1, Ground

ADC1_DM1, ADC0_DP0/ADC1_DP3,

ADC0_DM0/ADC1_DM3, ADC1_DP0/

ADC0_DP3, ADC1_DM0/ADC0_DM3,

ADC1_SE16/ADC0_SE22,

ADC0_SE16/ADC0_SE21,

ADC1_SE18

DAC ¹

USB

DAC0_OUT, DAC1_OUT

VREGIN, USB0_GND, VOUT33²

Float

Connect VREGIN and VOUT33

together and tie to ground through a 10

kΩ resistor. Do not tie directly to

ground, as this causes a latch-up risk.

USB0_DM, USB0_DP

Float

1. Unused DAC signals do not apply to all parts. See the Pinout section for details.

2. USB0_VBUS and USB0_GND are board level signals

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

75

NXP Semiconductors

Pinout

5.3 K64 Pinouts

The below figure shows the pinout diagram for the devices supported by this document.

Many signals may be multiplexed onto a single pin. To determine what signals can be

used on which pin, see the previous section.

76

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Pinout

PTE0

1

108

107

106

105

104

103

102

101

100

99

VDD

PTE1/LLWU_P0

2

VSS

PTE2/LLWU_P1

3

PTC3/LLWU_P7

PTC2

PTE3

4

VDD

5

PTC1/LLWU_P6

PTC0

VSS

6

PTE4/LLWU_P2

7

PTB23

PTB22

PTB21

PTB20

PTB19

PTB18

PTB17

PTB16

VDD

PTE5

8

PTE6

9

PTE7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

PTE8

98

PTE9

97

PTE10

96

PTE11

95

PTE12

VDD

94

VSS

93

VSS

PTB11

PTB10

PTB9

92

VSS

91

USB0_DP

90

USB0_DM

PTB8

89

VOUT33

PTB7

88

VREGIN

PTB6

87

ADC0_DP1

PTB5

86

ADC0_DM1

PTB4

85

ADC1_DP1

PTB3

84

ADC1_DM1

PTB2

83

ADC0_DP0/ADC1_DP3

ADC0_DM0/ADC1_DM3

ADC1_DP0/ADC0_DP3

ADC1_DM0/ADC0_DM3

VDDA

PTB1

82

PTB0/LLWU_P5

PTA29

PTA28

PTA27

PTA26

PTA25

PTA24

RESET_b

PTA19

81

80

79

78

VREFH

77

VREFL

76

VSSA

75

_SE16/CMP2_IN2/ADC0_SE22

_SE16/CMP1_IN2/ADC0_SE21

74

73

Figure 37. 144 LQFP Pinout Diagram

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

77

NXP Semiconductors

Pinout

1

2

3

4

5

6

7

8

9

10

11

12

PTC4/

LLWU_P8

PTC3/

LLWU_P7

PTD6/

PTD4/

LLWU_P14

PTD0/

LLWU_P12

A

B

C

D

E

F

PTC8

NC

PTC2

A

B

C

D

E

F

PTD7

PTD5

PTC16

PTC12

LLWU_P15

PTC11/

LLWU_P11

PTC1/

LLWU_P6

PTD12

PTD15

PTD11

PTD14

PTD10

PTD13

PTE0

PTD3

PTC19

PTC18

PTC17

VDD

PTC15

PTC14

PTC13

VDD

PTC7

PTD9

PTD8

PTB21

PTB17

PTB9

PTB5

PTB1

NC

PTC0

PTB22

PTB18

PTB10

PTB6

PTD2/

LLWU_P13

PTC6/

LLWU_P10

PTC10

PTC9

VDD

VSS

PTB23

PTB19

PTB11

PTB7

PTE2/

LLWU_P1

PTE1/

LLWU_P0

PTC5/

LLWU_P9

PTD1

PTE3

PTB20

PTB16

PTB8

PTB4

PTE4/

LLWU_P2

PTE6

PTE5

PTE9

VDD

VSS

PTE10

PTE8

PTE7

VDD

VSS

G

H

G

H

J

VOUT33

VREGIN

PTE12

PTE11

PTE28

PTE27

PTE26

VREFH

VDDA

PTA0

VREFL

VSSA

PTA1

VSS

PTB3

PTB2

PTB0/

LLWU_P5

USB0_DP

ADC0_DP1

ADC1_DP1

USB0_DM

ADC0_DM1

ADC1_DM1

VSS

PTA29

PTA26

PTA17

PTA15

PTA28

PTA25

PTA24

RESET_b

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

PTA13/

LLWU_P4

J

K

L

PTA6

PTA3

PTA7

PTA8

PTA9

PTA27

PTA16

PTA14

ADC1_SE16/

CMP2_IN2/

ADC0_SE22

K

L

PTE25

RTC_

PTA2

PTA12

PTA11

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/ WAKEUP_B

ADC1_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

ADC0_DP0/ ADC0_DM0/

ADC1_DM3

ADC1_DP3

PTA4/

LLWU_P3

VBAT

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

ADC1_DP0/ ADC1_DM0/

M

PTE24

NC

EXTAL32

XTAL32

PTA5

PTA10

VSS

PTA19

PTA18

ADC0_DM3

ADC0_DP3

1

2

3

4

5

6

7

8

9

10

11

12

Figure 38. 144 MAPBGA Pinout Diagram

78

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

Pinout

1

2

3

4

5

6

7

8

9

10

11

PTD4/

LLWU_P14

PTC4/

LLWU_P8

A

B

C

D

E

F

G

H

J

PTD7

PTD5

PTC19

PTC14

PTC13

PTC8

PTD9

PTD8

NC

A

B

C

D

E

F

G

H

J

PTD6/

LLWU_P15

PTC3/

LLWU_P7

PTD10

PTD12

PTD14

PTD15

PTD3

PTC18

PTC17

PTC15

PTC12

PTC10

PTC9

VDD

PTC7

PTC0

PTB19

PTB18

PTB17

PTB21

PTB2

PTB16

PTB11

PTB10

PTB9

PTB12

PTB13

PTB8

PTB7

PTB6

PTD2/

LLWU_P13

PTC11/

LLWU_P11

PTC6/

LLWU_P10

PTD11

PTC2

PTD0/

LLWU_P12

PTC5/

PTC1/

LLWU_P9 LLWU_P6

PTD13

PTE2/

PTD1

PTC16

VDD

PTE1/

LLWU_P1 LLWU_P0

PTE0

PTE3

PTE5

NC

VDD

VSS

PTB23

PTB22

PTB3

PTA1

USB0_DP USB0_DM

PTE6

VSS

VDDA

VREFH

PTE24

PTE25

VSSA

VREFL

PTE26

PTA0

PTB20

PTB1

PTB0/

LLWU_P5

VOUT33

VREGIN

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

PTE4/

LLWU_P2

ADC0_DP1 ADC0_DM1

ADC1_DP1 ADC1_DM1

PTA3

PTA17

PTA16

VSS

PTA29

RESET_b

PTA19

ADC1_SE16/

CMP2_IN2/

ADC0_SE22

PTA4/

LLWU_P3

PTA11

PTA2

PTA10

PTA14

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

ADC0_DP0/ ADC0_DM0/

ADC1_DP3 ADC1_DM3

K

L

NC

VBAT

PTA5

RTC_

PTA12

K

L

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

ADC1_DP0/ ADC1_DM0/

ADC0_DP3 ADC0_DM3

PTA13/

WAKEUP_B LLWU_P4

XTAL32

4

EXTAL32

5

VSS

6

PTA15

9

VDD

10

PTA18

11

1

2

3

7

8

Figure 39. 121 XFBGA Pinout Diagram

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

79

NXP Semiconductors

Pinout

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PTE0

VDD

2

PTE1/LLWU_P0

PTE2/LLWU_P1

PTE3

VSS

3

PTC3/LLWU_P7

PTC2

4

5

PTC1/LLWU_P6

PTC0

PTE4/LLWU_P2

PTE5

6

7

PTB23

PTB22

PTB21

PTB20

PTB19

PTB18

PTB17

PTB16

VDD

PTE6

8

VDD

9

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

USB0_DP

USB0_DM

VOUT33

VREGIN

ADC0_DP1

ADC0_DM1

ADC1_DP1

ADC1_DM1

ADC0_DP0/ADC1_DP3

ADC0_DM0/ADC1_DM3

ADC1_DP0/ADC0_DP3

ADC1_DM0/ADC0_DM3

VDDA

VSS

PTB11

PTB10

PTB9

PTB3

PTB2

PTB1

PTB0/LLWU_P5

RESET_b

PTA19

VREFH

VREFL

VSSA

Figure 40. 100 LQFP Pinout Diagram

80

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Ordering parts

1

2

3

4

5

6

7

8

9

10

11

PTC4/

LLWU_P8

A

B

C

D

E

F

PTC7

PTC9

PTC12

PTC15

PTC17

PTD1

PTD5

PTD7

PTD9

PTD14

A

B

C

D

E

F

PTC3/

LLWU_P7 LLWU_P10

PTC6/

PTC11/

LLWU_P11

PTD6/

LLWU_P15

PTC8

PTC14

PTC16

PTC19

VDD

PTC18

PTD2/

PTD3

PTD8

PTD12

PTD15

PTE3

PTC5/

PTC2

PTD4/

PTC10

PTC13

PTB22

PTB21

VSS

PTD11

PTD13

PTE2/

PTE0

LLWU_P9

LLWU_P13 LLWU_P14

PTC1/

LLWU_P6

PTD0/

PTD10

PTE1/

PTE4/

PTB23

PTB18

PTB16

PTB10

PTB7

PTC0

PTB19

PTB17

PTB11

PTB6

PTB2

PTA28

PTA24

VSS

PTE5

LLWU_P12

LLWU_P0 LLWU_P1 LLWU_P2

PTB20

VDD

VSS

VDD

PTE6

VDD

PTE7

ADC0_DP1

ADC0_DM1

VDD

PTE8

PTE9

PTE12

PTE10

VSS

PTE11

ADC0_DP0/

ADC1_DP3

G

H

J

PTB9

PTB5

PTB1

PTA27

PTA25

PTA17

PTB8

PTB4

VDD

VSS

VOUT33

USB0_DP

G

H

J

ADC0_DM0/

ADC1_DM3

VSS

PTA11

PTA8

PTA5

VDD

VREGIN USB0_DM

PTB0/

LLWU_P5

RTC_

ADC1_DP0/

ADC1_DP1

PTB3

PTA14

PTA12

PTA9

PTA7

PTA2

PTA1

PTA0

PTE28

PTE27

WAKEUP_B ADC0_DP3

ADC0_SE16/

ADC1_DM0/

CMP1_IN2/

K

L

PTA29

RESET_b

PTA19

PTA26

PTA16

PTE25

ADC1_DM1

VDDA

K

L

ADC0_DM3

ADC0_SE21

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

PTE24

VREFH

DAC1_OUT/

ADC1_SE16/

PTA13/

LLWU_P4

PTA4/

LLWU_P3

CMP0_IN4/

CMP2_IN2/

M

N

VBAT

VREFL

M

N

CMP2_IN3/

ADC0_SE22

ADC1_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

PTA18

1

VDD

2

PTA15

3

PTA10

4

PTA6

5

PTA3

6

PTE26

7

EXTAL32

8

XTAL32

9

VSSA

11

10

Figure 41. 142 CSP Pinout Diagram

6 Ordering parts

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

81

NXP Semiconductors

Part identification

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search for the

following device numbers: MK64

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format:

Q K## A M FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

K##

A

Kinetis family

Key attribute

• K64 = Ethernet with high RAM density

• D = Cortex-M4 w/ DSP

• F = Cortex-M4 w/ DSP and FPU

M

Flash memory type

• N = Program flash only

• X = Program flash and FlexMemory

FFF

Program flash memory size

• 32 = 32 KB

• 64 = 64 KB

• 128 = 128 KB

• 256 = 256 KB

• 512 = 512 KB

• 1M0 = 1 MB

• 2M0 = 2 MB

Table continues on the next page...

82

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Terminology and guidelines

Values

Field

Description

R

Silicon revision

• Z = Initial

• (Blank) = Main

• A = Revision after main

T

Temperature range (°C)

Package identifier

• V = –40 to 105

• C = –40 to 85

PP

• FM = 32 QFN (5 mm x 5 mm)

• FT = 48 QFN (7 mm x 7 mm)

• LF = 48 LQFP (7 mm x 7 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• MP = 64 MAPBGA (5 mm x 5 mm)

• LK = 80 LQFP (12 mm x 12 mm)

• LL = 100 LQFP (14 mm x 14 mm)

• MC = 121 MAPBGA (8 mm x 8 mm)

• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)

• LQ = 144 LQFP (20 mm x 20 mm)

• MD = 144 MAPBGA (13 mm x 13 mm)

CC

Maximum CPU frequency (MHz)

• 5 = 50 MHz

• 7 = 72 MHz

• 10 = 100 MHz

• 12 = 120 MHz

• 15 = 150 MHz

• 16 = 168 MHz

• 18 = 180 MHz

N

Packaging type

• R = Tape and reel

• (Blank) = Trays

7.4 Example

This is an example part number:

MK64FN1M0VMD12

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table:

Term

Definition

Rating

A minimum or maximum value of a technical characteristic that, if exceeded, may cause

permanent chip failure:

Table continues on the next page...

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

83

NXP Semiconductors

Terminology and guidelines

Term

Definition

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic

begins to exceed one of its operating ratings.

Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during

operation to avoid incorrect operation and possibly decreasing the useful life of the chip

Operating behavior

A specified value or range of values for a technical characteristic that are guaranteed during

operation if you meet the operating requirements and any other specified conditions

Typical value

A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Is representative of that characteristic during operation when you meet the typical-value

conditions or other specified conditions

NOTE: Typical values are provided as design guidelines and are neither tested nor

guaranteed.

8.2 Examples

Operating rating:

EXAMPLE

Operating requirement:

Operating behavior that includes a typical value:

EXAMPLE

84

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

NXP Semiconductors

Terminology and guidelines

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

Supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

8.4 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016

85

NXP Semiconductors

Revision History

9 Revision History

The following table provides a revision history for this document.

Table 58. Revision History

Rev. No.

Date

Substantial Changes

2

3

01/2014

04/2014

Initial public release.

• Format changes

• Updated Table 23 "Flash command timing specifications."

4

09/2014

• Updated Table 6 "Power consumption operating behavior."

• Updated Table 17 "IRC48M specifications

• Updated Table 35 "VREF full-range operating behavior"

5

6

12/2014

08/2015

• Updated Table 6 "Power consumption operating behavior."

• Added a note to the section "Power consumption operating behaviors."

• Added a footnote to the maximum SCL clock frequency value in the table "I²C timing"

• Changed the title of the table "I²C 1 MHZ timing" to "I²C 1 Mbps timing"

• Added a footnote and updated the table "IRC48M specifications" for open loop total

deviation of IRC48M frequency at high voltage and low voltage.

• Added a footnote on the ambient temperature entry to the section "Thermal operating

requirements."

• Added a note to the section "Power consumption operating behaviors" and updated

values in the table "Power consumption operating behaviors."

• Added a note to the maximum frequency value in the table "Slave mode DSPI timing

(limited voltage range)."

• Redeveloped the section "Terminology and guidelines."

7

10/2016

• Updated the values of I_{DD_STOP}and I_{DD_VLLS0}in the table "Power consumption

operating behaviors"

86

NXP Semiconductors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016


型号：	MK64FN1M0VLL12
厂家：	NXP
描述：	RISC MICROCONTROLLER 时钟外围集成电路
文件：	总87页 (文件大小：1249K)
中文：	中文翻译
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MK64FN1M0VLL12 [NXP]

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