MKL03Z32CAF4R [NXP]
Kinetis KL03 32 KB Flash;
| 型号： | MKL03Z32CAF4R |
| 厂家： | 
NXP |
| 描述： | Kinetis KL03 32 KB Flash |
| 文件： | 总59页 (文件大小：1104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
Document Number: KL03P24M48SF0
Rev. 5.1 08/2017
Kinetis KL03 32 KB Flash
MKL03ZxxVFG4
MKL03ZxxVFK4
MKL03Z32CAF4R
MKL03Z32CBF4R
48 MHz Cortex-M0+ Based Microcontroller
Supports ultra low power 48 MHz devices with up to 32 KB
Flash.
World's smallest MCU based on ARM® technology. Ideal
solution for Internet of Things edge nodes design with ultra small
form factor and ultra low power consumption. The products
offers:
16-pin QFN (FG)
3 x 3 x 0.65 Pitch 0.5 4 x 4 x 0.65 Pitch 0.5
mm mm
24-pin QFN (FK)
• Tiny footprint packages, including 1.6 x 2.0 mm2 WLCSP
• Run power consumption as low as 50 µA/MHz
• Static power consumption as low as 2.2 µA with 7.5 µs
wakeup time for full retention and lowest static mode down
to 77 nA in deep sleep
• Highly integrated peripherals, including new boot ROM and
high accurate internal voltage reference, etc
20 WLCSP
2 x 1.61 x 0.56 Pitch 0.4 mm(AF) 2 x 1.61 x
0.32 Pitch 0.4 mm (BF)
Core
• ARM® Cortex®-M0+ core up to 48 MHz
• Temperature range (ambient): -40 to 105°C for QFN
packages; -40 to 85°C for WLCSP packages
Memories
• Up to 32 KB program flash memory
Human-machine interface
• General-purpose input/output up to 22
• 2 KB SRAM
• 8 KB ROM with build-in bootloader
• 16 bytes regfile
Communication interfaces
• One 8-bit SPI module
• One LPUART module
System peripherals
• One I2C module supporting up to 1 Mbit/s, with
double buffer
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
Analog Modules
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
• 12-bit SAR ADC with internal voltage reference, up
to 818 ksps and 7 channels
• High-speed analog comparator containing a 6-bit
DAC and programmable reference input
• 1.2 V voltage reference (Vref)
Clocks
• 48 MHz high accuracy internal reference clock
• 8/2 MHz low power internal reference clock
• 32 kHz to 40 kHz crystal oscillator
• 1 kHz LPO clock
Timers
• Two 2-channel Timer/PWM modules
• One low-power timer
• Real time clock
Operating Characteristics
Security and integrity modules
• Voltage range: 1.71 to 3.6 V
• 80-bit unique identification number per chip
• Flash write voltage range: 1.71 to 3.6 V
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MKL03Z8VFG4(R)
MKL03Z16VFG4(R)
MKL03Z32VFG4(R)
MKL03Z32CAF4R
MKL03Z32CBF4R
MKL03Z8VFK4(R)
MKL03Z16VFK4(R)
MKL03Z32VFK4(R)
8
2
2
2
2
2
2
2
2
14
14
14
18
18
22
22
22
16
32
32
32
8
16
32
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Solution Advisor
Selector Guide The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Product Brief
The Product Brief contains concise overview/summary information to KL03PB1
enable quick evaluation of a device for design suitability.
Reference
Manual
The Reference Manual contains a comprehensive description of the KL03P24M48SF0RM1
structure and function (operation) of a device.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KL03P24M48SF01
Chip Errata
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KL03Z_xN86K2
Package
drawing
Package dimensions are provided in package drawings.
QFN 16-pin: 98ASA00525D1
QFN 24-pin: 98ASA00602D1
WLCSP 20-pin: 98ASA00676D1
WLCSP 20-pin (ultra thin):
98ASA00964D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the “x” replaced by
the revision of the device you are using.
Figure 1 shows the functional modules in the chip.
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NXP Semiconductors
Kinetis KL03 Family
Memories and
Memory Interfaces
ARM Cortex-M0+
Core
System
Clocks
Low
Internal
watchdog
frequency
oscillator
Program
flash
SWD
interfaces
Internal
reference
clocks
BME
RAM
ROM
Interrupt
controller
LPO
MTB
Register
file
Security
and Integrity
Human-Machine
Interface (HMI)
Analog
Communication
Interfaces
Timers
Timers
2x2ch
12-bit ADC
x1
Unique ID
I2C
x1
GPIOs
with
interrupt
Analog
comparator
Low Power
Timer
Low power
with
UART
x1
6-bit DAC
x1
RTC
SPI
x1
VREF
Figure 1. Functional block diagram
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NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
3.6 Analog............................................................................. 33
3.6.1 ADC electrical specifications............................... 33
3.6.2 CMP and 6-bit DAC electrical specifications....... 37
3.6.3 Voltage reference electrical specifications.......... 39
3.7 Timers..............................................................................40
3.8 Communication interfaces............................................... 40
3.8.1 SPI switching specifications................................ 41
3.8.2 Inter-Integrated Circuit Interface (I2C) timing...... 45
3.8.3 UART...................................................................47
4 Dimensions............................................................................. 47
4.1 Obtaining package dimensions....................................... 47
5 Pinout......................................................................................48
5.1 KL03 signal multiplexing and pin assignments................48
5.2 KL03 pinouts....................................................................49
6 Ordering parts......................................................................... 51
6.1 Determining valid orderable parts....................................51
7 Part identification.....................................................................51
7.1 Description.......................................................................51
7.2 Format............................................................................. 52
7.3 Fields............................................................................... 52
7.4 Example...........................................................................52
8 Terminology and guidelines.................................................... 53
8.1 Definition: Operating requirement....................................53
8.2 Definition: Operating behavior......................................... 53
8.3 Definition: Attribute.......................................................... 54
8.4 Definition: Rating............................................................. 54
8.5 Result of exceeding a rating............................................ 55
8.6 Relationship between ratings and operating
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 6
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....24
2.2.7 EMC Radiated Emissions Web Search
Procedure boilerplate.......................................... 25
2.2.8 Capacitance attributes.........................................25
2.3 Switching specifications...................................................25
2.3.1 Device clock specifications..................................25
2.3.2 General switching specifications......................... 26
2.4 Thermal specifications.....................................................26
2.4.1 Thermal operating requirements......................... 26
2.4.2 Thermal attributes................................................27
3 Peripheral operating requirements and behaviors.................. 27
3.1 Core modules.................................................................. 27
3.1.1 SWD electricals .................................................. 28
3.2 System modules.............................................................. 29
3.3 Clock modules................................................................. 29
3.3.1 MCG-Lite specifications.......................................29
3.3.2 Oscillator electrical specifications........................30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications..............................31
3.5 Security and integrity modules........................................ 33
requirements....................................................................55
8.7 Guidelines for ratings and operating requirements..........55
8.8 Definition: Typical value...................................................56
8.9 Typical value conditions.................................................. 57
9 Revision history.......................................................................57
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NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. QFN packages moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Table 3. WLCSP packages moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
1
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 4. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
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NXP Semiconductors
General
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Table 5. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
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NXP Semiconductors
General
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 6. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
—
—
—
—
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
—
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
–5
—
—
V
—
1
IO pin negative DC injection current—single pin
• VIN < VSS–0.3V
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
—
–25
1.2
—
—
mA
V
• Negative current injection
VRAM
VDD voltage required to retain RAM
—
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
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NXP Semiconductors
General
2.2.2 LVD and POR operating requirements
Table 7. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
—
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
—
2.70
2.80
2.90
3.00
60
2.78
2.88
2.98
3.08
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
mV
—
—
1
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
V
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
—
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
—
—
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 8. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad (except
RESET)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA
VOH
Output high voltage — High drive pad (except
RESET)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
Table continues on the next page...
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General
Notes
Table 8. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
Min.
Max.
Unit
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
100
mA
—
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
1
—
—
—
—
0.5
0.5
100
1
V
V
IOLT
IIN
Output low current total for all ports
mA
μA
—
3
Input leakage current (per pin) for full temperature
range
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
41
μA
μA
3
3
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
—
4
RPU
20
50
1. I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other
GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
VLLSx→RUN recovery uses LIRC clock mode at the default CPU and system
frequency of 8 MHz, and a bus and flash clock frequency of 4 MHz.
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9
NXP Semiconductors
General
Table 9. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Note
tPOR
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
—
—
300
μs
1
—
—
—
—
—
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
152
152
93
166
166
104
8
μs
μs
μs
μs
μs
7.5
7.5
8
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
Table 10. KL03 QFN packages power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
2
3
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
—
—
5.49
5.62
5.71
5.84
mA
mA
mA
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
3
3
3
—
—
5.16
5.27
5.37
5.48
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
6.03
6.16
6.27
6.41
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
Table continues on the next page...
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General
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
• at 25 °C
—
3.71
3.86
mA
• at 105 °C
—
3.81
3.96
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
3
—
—
2.47
2.58
2.57
2.68
mA
mA
mA
mA
mA
mA
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
3
—
—
6.43
6.56
6.69
6.82
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
—
—
—
—
—
5.71
5.82
5.94
6.05
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
3.3
3.4
3.43
3.54
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
2.28
2.38
2.37
2.48
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
6.1
6.34
6.47
6.22
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
3.14
3.27
3.23
3.36
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
—
—
3.54
3.67
3.63
3.76
Table continues on the next page...
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NXP Semiconductors
General
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
• at 25 °C
• at 105 °C
IDD_VLPRCO Very-low-power run While(1) loop in flash in
compute operation mode— 2 MHz LIRC mode,
2 MHz core/0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
—
—
—
500
188
82
750
217
123
754
μA
μA
μA
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
503
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
—
—
—
—
—
—
—
—
—
—
—
—
60
516
209
229
93
90
774
350
370
140
81
μA
μA
μA
μA
μA
μA
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 2 MHz core / 0.5 MHz flash, VDD
=
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM in all
peripheral clock disable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
31
Table continues on the next page...
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General
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral
—
clock enable, 2 MHz core / 0.5 MHz flash, VDD
=
—
—
103
1.4
154
μA
3.0 V
• at 25 °C
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
—
—
1.94
mA
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
—
—
1.02
121
1.24
181
mA
μA
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
—
—
—
—
IDD_VLPW Very-low-power wait mode current, core
—
—
59
28
97
42
μA
μA
disabled, 2 MHz system/ 0.5 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
—
—
1.53
2.03
1.18
mA
mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
—
—
0.881
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
158
164
187
219
175.7
179.48
199.54
236.43
• at 50 °C
• at 85 °C
• at 105 °C
μA
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
—
2.2
3.9
2.71
6.63
• at 50 °C
• at 85 °C
• at 105 °C
13.9
28.4
18.25
36.59
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
—
—
—
2.2
3.8
2.674
6.44
• at 50 °C
Table continues on the next page...
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General
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
• at 85 °C
—
13.2
17.37
μA
• at 105 °C
—
27.8
35.54
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
—
μA
μA
μA
—
—
—
—
1.08
1.4
1.17
1.52
3.96
8.19
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
3.45
7.02
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
—
—
—
—
—
—
—
—
—
1.47
1.82
3.93
7.6
1.56
1.94
4.44
8.77
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
—
—
—
—
1.33
1.65
3.56
6.92
1.42
1.77
4.07
8.09
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
—
—
—
—
566
788
690
839
• at 25 °C and below
• at 50°C
• at 85°C
• at 105 °C
2270
4980
2600
5820
nA
nA
nA
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
—
—
—
—
969
1059
1251
3070
6450
• at 25 °C and below
1200
2740
5610
• at 50°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
—
—
—
—
826
916
• at 25 °C and below
1040
2400
4910
1091
2730
5750
• at 50°C
• at 85°C
• at 105 °C
Table continues on the next page...
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General
Table 10. KL03 QFN packages power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
—
—
—
—
—
265
467
373
512.9
2256
5395
• at 25 °C and below
nA
• at 50 °C
• at 85 °C
• at 105 °C
1920
4540
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
4
—
—
—
—
77
350
465.70
1994
• at 25 °C and below
255
nA
• at 50 °C
• at 85 °C
• at 105 °C
1640
4080
4956
1. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation
(mean + 3 sigma).
2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
3. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
4. No brownout
Table 11. KL03 WLCSP package power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
2
3
IDD_RUNCO Running CoreMark in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
5.49
5.59
5.71
5.81
mA
mA
mA
• at 85 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
3
3
—
—
5.16
5.24
5.37
5.45
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
6.03
6.13
6.27
6.38
• at 85 °C
Table continues on the next page...
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General
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
3
—
—
3.71
3.78
3.86
3.93
mA
• at 25 °C
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
3
3
—
—
2.47
2.55
2.57
2.65
mA
mA
mA
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
6.43
6.53
6.69
6.79
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
—
—
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0
V
—
—
5.71
5.79
5.94
6.02
• at 25 °C
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0
—
—
3.3
3.43
3.50
mA
V
• at 25 °C
3.37
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
—
2.28
2.35
2.37
2.44
mA
mA
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0
V
—
—
6.1
6.34
6.44
• at 25 °C
6.19
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0
V
—
—
—
3.14
3.24
3.23
3.33
mA
Table continues on the next page...
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General
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
• at 25 °C
• at 85 °C
IDD_RUN Run mode current—48M HIRC mode, running
—
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0
—
—
3.54
3.64
3.63
3.73
mA
V
• at 25 °C
• at 85 °C
IDD_VLPRCO Very-low-power run While(1) loop in flash in
compute operation mode— 2 MHz LIRC mode,
2 MHz core/0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
—
—
—
500
188
82
750
217
123
754
μA
μA
μA
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
503
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
—
—
—
—
—
—
—
—
—
60
90
μA
μA
μA
μA
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
516
209
229
774
350
370
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM in all
peripheral clock disable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM in all
Table continues on the next page...
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General
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description
peripheral clock disable, 2 MHz core / 0.5 MHz
Min.
Typ.
Max.1
Unit
Notes
—
93
140
μA
flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock disable, 125 kHz core / 31.25
kHz flash, VDD = 3.0 V
—
—
—
—
31
103
1.4
81
μA
μA
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 2 MHz core / 0.5 MHz
flash, VDD = 3.0 V
—
154
1.94
• at 25 °C
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
—
—
mA
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
—
—
1.02
121
1.24
181
mA
μA
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
—
—
IDD_VLPW Very-low-power wait mode current, core
disabled, 2 MHz system/ 0.5 MHz bus and
flash, all peripheral clocks disabled, VDD = 3.0
V
—
—
59
28
97
42
μA
μA
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0
V
—
—
—
—
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
—
—
1.53
2.03
1.18
mA
mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
0.881
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
—
—
—
158
164
187
175.7
179.48
199.54
• at 50 °C
• at 85 °C
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
—
—
—
2.2
3.9
2.71
6.63
Table continues on the next page...
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General
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.1
Unit
Notes
• at 50 °C
—
13.9
18.25
μA
• at 85 °C
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
—
—
—
—
2.2
3.8
2.674
6.44
• at 50 °C
• at 85 °C
13.2
17.37
μA
μA
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
—
—
—
—
—
—
—
—
—
—
1.08
1.4
1.17
1.52
3.96
• at 25 °C and below
• at 50 °C
• at 85 °C
3.45
IDD_VLLS3 Very-low-leakage stop mode 3 current with
RTC current, at 3.0 V
μA
μA
—
—
—
1.47
1.82
3.93
1.56
1.94
4.44
• at 25 °C and below
• at 50 °C
• at 85 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with
RTC current, at 1.8 V
—
—
—
1.33
1.65
3.56
1.42
1.77
4.07
• at 25 °C and below
• at 50 °C
• at 85 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
—
—
—
566
788
690
839
• at 25 °C and below
• at 50°C
• at 85°C
2270
2600
nA
nA
nA
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
—
—
—
969
1200
2740
1059
1251
3070
• at 25 °C and below
• at 50°C
• at 85°C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
—
—
—
826
1040
2400
916
1091
2730
• at 25 °C and below
• at 50°C
• at 85°C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled
—
265
373
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
Table continues on the next page...
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19
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General
Table 11. KL03 WLCSP package power consumption operating behaviors (continued)
Symbol Description
• at 25 °C and below
Min.
Typ.
Max.1
Unit
Notes
—
467
512.9
• at 50 °C
• at 85 °C
—
1920
2256
nA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled
4
(SMC_STOPCTRL[PORPO] = 1) at 3 V
• at 25 °C and below
—
—
—
77
350
465.70
1994
255
nA
• at 50 °C
• at 85 °C
1640
1. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation
(mean + 3 sigma).
2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
3. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
4. No brownout
Table 12. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1051
ILIRC8MHz
8 MHz internal reference clock (LIRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz LIRC enabled,
MCG_SC[FCRDIV]=000b,
68
68
68
68
68
68
µA
MCG_MC[LIRC_DIV2]=000b.
ILIRC2MHz
2 MHz internal reference clock (LIRC)
adder. Measured by entering STOP
mode with the 2 MHz LIRC enabled,
MCG_SC[FCRDIV]=000b,
27
27
27
27
27
27
µA
MCG_MC[LIRC_DIV2]=000b.
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
• VLLS1
• VLLS3
• VLPS
• STOP
340
340
340
340
410
410
420
420
460
460
480
480
470
490
570
570
480
530
610
610
600
600
850
850
nA
nA
ILPTMR
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
200
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20
NXP Semiconductors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
General
Table 12. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1051
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
15
15
15
15
15
15
µA
Includes 6-bit DAC power consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
340
440
440
480
520
620
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
85
28
85
28
85
28
85
28
85
28
85
28
µA
• LIRC8M (8 MHz internal
reference clock)
• LIRC2M (2 MHz internal
reference clock)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
• LIRC8M (8 MHz internal
µA
93
93
93
93
93
93
reference clock)
• LIRC2M (2 MHz internal
reference clock)
35
45
35
45
35
45
35
45
35
45
35
45
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx or VLLSx
mode.
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
340
340
340
340
340
340
1. For QFN packages only.
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General
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Temperature=25, VDD=3, MCGMode=HIRC, whileloop located in Flash
All Peripheral CLKGates
CLKRatio
Flash - Core
CoreFreq (MHz)
Figure 3. Run mode supply current vs. core frequency (loop located in flash)
22
NXP Semiconductors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
General
Temperature=25, VDD=3, MCGMode=HIRC, whileloop located in SRAM
All Peripheral CLKGates
CLKRatio
Flash - Core
CoreFreq (MHz)
Figure 4. Run mode supply current vs. core frequency (loop located in SRAM)
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NXP Semiconductors
General
Temperature=25, VDD=3, MCG=LIRC8M, whileloop in SRAM
All Peripheral CLKGates
CLKRatio
Flash - Core
CoreFreq (MHz)
Figure 5. VLPR mode current vs. core frequency (loop in SRAM)
2.2.6 EMC radiated emissions operating behaviors
Table 13. EMC radiated emissions operating behaviors for 24-pin QFN package
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC/SAE level
0.15–50
50–150
5
7
5
5
N
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC 61967-2 (and SAE J1752/3) radiated radio frequency (RF) emissions measurement
standard. Typical Configuration: Appendix B: DUT Software Configuration—2. Typical Configuration.
2. VDD = 3.3 V, TA = 25 °C, firc48m = 48 MHz, fSYS = 48 MHz, fBUS = 24 MHz
3. IEC/SAE Level Maximums: N≤12 dBµV, M≤18 dBµV, L≤24 dBµV, K≤30 dBµV, I ≤ 36 dBµV, H ≤ 42 dBµV, G≤48 dBµV.
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General
2.2.7 EMC Radiated Emissions Web Search Procedure boilerplate
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for "EMC design"
2.2.8 Capacitance attributes
Table 14. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 15. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
—
4
MHz
MHz
MHz
MHz
MHz
kHz
fBUS
1
1
fFLASH
fLPTMR
fERCLK
fERCLK
Flash clock
LPTMR clock2
24
External reference clock
External reference clock
16
32.768
16
fLPTMR_ERCLK LPTMR external reference clock
MHz
MHz
MHz
fTPM
TPM asynchronous clock
8
fUART0
UART0 asynchronous clock
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General
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 16. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 17. Thermal operating requirements of WLCSP package
Symbol
TJ
Description
Min.
–40
–40
Max.
95
Unit
°C
Note
Die junction temperature
Ambient temperature
TA
85
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
Table 18. Thermal operating requirements of other packages
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Note
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
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Peripheral operating requirements and behaviors
2.4.2 Thermal attributes
Table 19. Thermal attributes
Board type
Single-layer (1S)
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
—
Symbol
RθJA
Description
16 QFN
64.2
53.3
55.4
48.9
33.5
20.9
0.2
20
WLCSP
24 QFN
60.7
48.5
51.0
43.6
30.4
9.8
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1,2
1,2,3
1,3
1,3
4
Thermal resistance, junction to
ambient (natural convection)
69.8
57.5
62.03
54.3
51.64
0.73
0.2
RθJA
Thermal resistance, junction to
ambient (natural convection)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
RθJB
RθJC
ΨJT
Thermal resistance, junction to
board
—
Thermal resistance, junction to
case
5
—
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
0.2
6
—
ΨJB
Thermal characterization
parameter, junction to package
bottom outside center (natural
convection)
22.4
―
21.8
°C/W
7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
3 Peripheral operating requirements and behaviors
3.1 Core modules
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3.1.1 SWD electricals
Table 20. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 6. Serial wire clock input timing
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Peripheral operating requirements and behaviors
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 7. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 21. HIRC48M specification
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Notes
—
Supply voltage
IDD48M
firc48m
Supply current
400
48
500
—
μA
—
Internal reference frequency
—
MHz
—
Δfirc48m_ol_lv total deviation of IRC48M frequency at low voltage
—
(VDD=1.71V-1.89V) over temperature
%firc48m
—
0.5
1.5
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Table 21. HIRC48M specification (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Δfirc48m_ol_hv total deviation of IRC48M frequency at high voltage
—
(VDD=1.89V-3.6V) over temperature
—
—
—
0.5
35
2
1.0
150
3
%firc48m
ps
Jcyc_irc48m Period Jitter (RMS)
—
1
tirc48mst
Startup time
μs
1. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by setting MCG_MC[HIRCEN] = 1. See reference manual for details.
Table 22. LIRC8M/2M specification
Symbol
VDD
Description
Supply voltage
Min.
1.08
-40
—
Typ.
—
—
14
30
2
Max.
1.47
125
17
Unit
V
Notes
—
T
Temperature range
°C
—
IDD_2M
IDD_8M
fIRC_2M
fIRC_8M
fIRC_T_2M
fIRC_T_8M
Tsu_2M
Tsu_8M
Supply current in 2 MHz mode
Supply current in 8 MHz mode
Output frequency
µA
—
—
35
µA
—
—
—
MHz
MHz
%fIRC
%fIRC
µs
—
Output frequency
—
8
—
—
VDD≥1.89 V
VDD≥1.89 V
—
Output frequency range (trimmed)
Output frequency range (trimmed)
Startup time
—
—
—
—
—
3
—
3
—
12.5
12.5
Startup time
—
µs
—
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 23. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
—
1
IDDOSC
Supply current — low-power mode
• 32 kHz
—
500
—
nA
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode
MΩ
kΩ
RS
Series resistor — low-frequency, low-power
mode
—
—
—
—
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 23. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
—
0.6
—
V
—
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 24. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode
tdc_extal Input clock duty cycle (external clock mode)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
—
40
—
50
60
—
%
—
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode
750
ms
1, 2
1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 25. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
—
1
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
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Peripheral operating requirements and behaviors
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 26. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
45
μs
—
30
μs
1
65
14
—
145
114
0.5
25
μs
—
2
tersscr
trd1all
ms
ms
μs
—
1
trdonce
—
tpgmonce Program Once execution time
65
61
—
—
μs
—
2
tersall
Erase All Blocks execution time
500
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 27. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 28. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
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Peripheral operating requirements and behaviors
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
3.6.1.1 12-bit ADC operating conditions
Table 29. 12-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
VREFH
ADC reference
voltage high
VDDA
3
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
CADIN
Input voltage
VREFL
—
—
4
VREFH
5
V
—
—
Input
capacitance
• 8-bit / 10-bit / 12-bit
modes
pF
RADIN
RAS
Input series
resistance
—
2
5
kΩ
—
4
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
—
5
kΩ
fADCK
Crate
ADC conversion ≤ 12-bit mode
clock frequency
1.0
18.0
MHz
5
6
ADC conversion ≤ 12-bit modes
rate
No ADC hardware averaging
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
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3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 8. ADC input impedance equivalency diagram
3.6.1.2 12-bit ADC electrical characteristics
Table 30. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1.
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
tADACK =
1/fADACK
MHz
MHz
MHz
MHz
2.4
clock source
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
Total
unadjusted error
• 12-bit modes
• <12-bit modes
—
—
6
3
—
6
LSB4
5
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Table 30. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
DNL
Differential non-
linearity
• 12-bit modes
—
0.9
–1.1 to
+1.9
LSB4
5
–0.3 to 0.5
• <12-bit modes
• 12-bit modes
—
—
0.4
1.5
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
• <12-bit modes
—
0.5
EFS
Full-scale error
• 12-bit modes
• <12-bit modes
• 12-bit modes
—
—
—
5
2
—
3
LSB4
VADIN
VDDA
=
5
EQ
EIL
Quantization
error
—
0.5
LSB4
mV
Input leakage
error
IIn × RAS
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
6
VTEMP25 Temp sensor
voltage
25 °C
6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
Table 31. 12-bit ADC characteristics (VREFH = VREFO, VREFL = VSSA
)
Symbol Description
Conditions1.
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
tADACK =
1/fADACK
MHz
MHz
MHz
MHz
2.4
clock source
fADACK
3.0
4.4
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Table 31. 12-bit ADC characteristics (VREFH = VREFO, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total
unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
5
1.4
Differential non-
linearity
• 12-bit modes
—
0.7
–1.1 to
+1.9
LSB4
LSB4
LSB4
5
5
–0.3 to
0.5
• <12-bit modes
• 12-bit modes
—
—
0.2
1.0
INL
EFS
Integral non-
linearity
–2.7 to
+1.9
–0.7 to
+0.5
• <12-bit modes
—
0.5
Full-scale error
• 12-bit modes
• <12-bit modes
• 12-bit modes
—
—
—
–4
–1.4
—
–5.4
–1.8
0.5
VADIN
VDDA
=
5
EQ
EIL
Quantization
error
LSB4
mV
Input leakage
error
IIn × RAS
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
6
VTEMP25 Temp sensor
voltage
25 °C
6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VREFO
2. Typical values assume VREFO = 1.2 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
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Peripheral operating requirements and behaviors
Typical ADC 12-bit Single Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
Hardware Averaging Disabled
Averaging of 8 samples
Averaging of 32 samples
0
2
4
6
8
10
12
14
16
18
20
22
ADC Clock Frequency (MHz)
Figure 9. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
Supply current, High-speed mode (EN=1,
PMODE=1)
—
200
μA
IDDLS
VAIN
VAIO
VH
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
VSS – 0.3
—
—
—
—
20
VDD
20
μA
V
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
mV
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay2
80
—
250
—
600
40
ns
μs
Table continues on the next page...
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37
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 32. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
IDAC6b
INL
Description
Min.
—
Typ.
7
Max.
—
Unit
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
μA
–0.5
–0.3
—
0.5
0.3
LSB3
LSB
DNL
—
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
38
NXP Semiconductors
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 Voltage reference electrical specifications
Table 33. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
—
1.71
3.6
Operating temperature
range of the device
°C
—
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Table 34 is tested under the condition of setting VREF_TRM[CHOPEN],
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 34. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range: 0 to 70°C)
—
50
Ac
Ibg
Ilp
Aging coefficient
—
—
—
—
—
—
—
—
400
80
uV/yr
µA
—
1
Bandgap only current
Low-power buffer current
High-power buffer current
360
1
uA
1
Ihp
mA
µV
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
2
100
—
µs
—
1
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 35. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 36. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
—
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
40
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 37. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
22
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
10
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph – 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
Table 38. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
—
—
Table continues on the next page...
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41
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 38. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol Description
Min.
Max.
Unit
Note
5
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
1024 x
tperiph
ns
—
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
96
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
52
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph – 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI master mode timing (CPHA = 0)
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NXP Semiconductors
Peripheral operating requirements and behaviors
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA = 1)
Table 39. SPI slave mode timing on slew rate disabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
3
7
—
ns
7
—
ns
8
23
23
—
0
tperiph
tperiph
25.7
—
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
ns
—
tperiph – 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
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Peripheral operating requirements and behaviors
Table 40. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph – 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 14. SPI slave mode timing (CPHA = 0)
44
NXP Semiconductors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
Peripheral operating requirements and behaviors
SS
(INPUT)
4
2
12
12
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
13
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
8
6
7
MOSI
(INPUT)
MSB IN
LSB IN
NOTE: Not defined
Figure 15. SPI slave mode timing (CPHA = 1)
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 41. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency
fSCL
0
4
1001
—
0
4002
—
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
03
2506
—
3.454
—
05
1004, 7
20 +0.1Cb
20 +0.1Cb
0.6
0.93
—
µs
ns
ns
ns
µs
µs
Data set-up time
8
7
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The PTB3 and PTB4 pins can support only the Standard mode.
2. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the
normal drive pins and VDD ≥ 2.7 V.
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45
NXP Semiconductors
Peripheral operating requirements and behaviors
3. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
4. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
5. Input signal Slew = 10 ns and Output Load = 50 pF
6. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
7. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
8. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 42. I 2C 1Mbit/s timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
0.5
0.26
—
—
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tSU; STA
tHD; DAT
tSU; DAT
tr
0.26
—
0
—
50
—
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
20 +0.1Cb
120
120
—
2
tf
20 +0.1Cb
tSU; STO
tBUF
0.26
0.5
0
Bus free time between STOP and START condition
—
Pulse width of spikes that must be suppressed by
the input filter
tSP
50
1. The maximum SCL clock frequency of 1 Mbit/s can support 200 pF bus loading when using the normal drive pins and
VDD ≥ 2.7 V.
2. Cb = total capacitance of the one bus line in pF.
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NXP Semiconductors
Dimensions
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 16. Timing definition for devices on the I2C bus
3.8.3 UART
See General switching specifications.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
16-pin QFN
Then use this document number
98ASA00525D
24-pin QFN
98ASA00602D
98ASA00676D
98ASA00964D
20-pin WLCSP
20-pin WLCSP (ultra thin)
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47
NXP Semiconductors
Pinout
5 Pinout
5.1 KL03 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
PTB3 and PTB4 are true open drain pins. The external pullup
resistor must be added to make them output correct values in
using I2C, GPIO, and LPUART0.
24
QFN
20
WLC
SP
16
QFN
Pin Name
Default
ALT0
ALT1
ALT2
TPM1_CH1
TPM1_CH0
ALT3
ALT4
ALT5
1
2
—
—
—
PTB6/
IRQ_2/
LPTMR0_ALT3
DISABLED
PTB6/
TPM_CLKIN1
IRQ_2/
LPTMR0_ALT3
—
PTB7/
IRQ_3
DISABLED
PTB7/
IRQ_3
3
4
5
6
7
B5
C5
C4
C3
D3
1
2
3
4
5
VDD
VSS
VDD
VDD
VSS
VSS
PTA3
PTA4
EXTAL0
XTAL0
DISABLED
EXTAL0
XTAL0
PTA3
PTA4
I2C0_SCL
I2C0_SDA
TPM0_CH1
I2C0_SDA
I2C0_SCL
SPI0_SS_b
LPUART0_TX
LPUART0_RX
CLKOUT
PTA5/
PTA5/
RTC_CLK_IN
RTC_CLK_IN
8
9
D5
—
6
—
—
7
PTA6
DISABLED
DISABLED
DISABLED
DISABLED
PTA6
TPM0_CH0
TPM0_CH1
TPM0_CH0
SPI0_MISO
SPI0_MISO
SPI0_SS_b
SPI0_MISO
SPI0_MOSI
PTB10
PTB11
PTB10
PTB11
10
11
—
D4
PTA7/
IRQ_4
PTA7/
IRQ_4
12
C1
8
PTB0/
IRQ_5/
LLWU_P4
ADC0_SE9
ADC0_SE9
PTB0/
IRQ_5/
LLWU_P4
EXTRG_IN
SPI0_SCK
I2C0_SCL
I2C0_SDA
13
14
D1
B1
9
PTB1/
IRQ_6
ADC0_SE8/
CMP0_IN3
ADC0_SE8/
CMP0_IN3
PTB1/
IRQ_6
LPUART0_TX
LPUART0_RX
LPUART0_RX
LPUART0_TX
10
PTB2/
IRQ_7
VREF_OUT/
CMP0_IN5
VREF_OUT/
CMP0_IN5
PTB2/
IRQ_7
15
16
D2
C2
—
—
PTA8
PTA9
ADC0_SE3
ADC0_SE2
ADC0_SE3
ADC0_SE2
PTA8
PTA9
I2C0_SCL
I2C0_SDA
SPI0_MOSI
SPI0_SCK
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NXP Semiconductors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
Pinout
24
QFN
20
WLC
SP
16
QFN
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
17
18
19
20
A1
B2
A2
B3
11
12
13
—
PTB3/
IRQ_10
DISABLED
PTB3/
IRQ_10
I2C0_SCL
LPUART0_TX
LPUART0_RX
NMI_b
PTB4/
IRQ_11
DISABLED
NMI_b
PTB4/
IRQ_11
I2C0_SDA
TPM1_CH1
TPM1_CH0
PTB5/
IRQ_12
ADC0_SE1/
CMP0_IN1
PTB5/
IRQ_12
PTA12/
IRQ_13/
ADC0_SE0/
CMP0_IN0
ADC0_SE0/
CMP0_IN0
PTA12/
IRQ_13/
TPM_CLKIN0
CLKOUT
LPTMR0_ALT2
LPTMR0_ALT2
21
22
A3
A4
—
PTB13/
CLKOUT32K
DISABLED
SWD_CLK
PTB13/
CLKOUT32K
TPM1_CH1
TPM1_CH0
RTC_CLKOUT
SWD_CLK
14
PTA0/
IRQ_0/
ADC0_SE15/
CMP0_IN2
PTA0/
IRQ_0/
LLWU_P7
LLWU_P7
23
24
B4
A5
15
16
PTA1/
IRQ_1/
LPTMR0_ALT1
RESET_b
SWD_DIO
PTA1/
IRQ_1/
LPTMR0_ALT1
TPM_CLKIN0
CMP0_OUT
RESET_b
SWD_DIO
PTA2
PTA2
5.2 KL03 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL03 signal multiplexing and pin assignments.
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Pinout
PTB4/IRQ_11
PTB3/IRQ_10
PTA9
PTB6/IRQ_2/LPTMR0_ALT3
18
17
16
15
14
13
1
2
3
4
5
6
PTB7/IRQ_3
VDD
PTA8
VSS
PTB2/IRQ_7
PTB1/IRQ_6
PTA3
PTA4
Figure 17. KL03 24-pin QFN pinout diagram
1
2
3
4
5
A
B
PTB3
PTB5
PTB13
PTA0
PTA2
PTB2
PTB4
PTA12
PTA1
VDD
C
D
PTB0
PTB1
PTA9
PTA8
PTA4
PTA5
PTA3
PTA7
VSS
PTA6
Figure 18. KL03 20-pin WLCSP pinout diagram
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Ordering parts
VDD
VSS
1
2
3
4
12
11
10
9
PTB4/IRQ_11
PTB3/IRQ_10
PTB2/IRQ_7
PTB1/IRQ_6
PTA3
PTA4
Figure 19. KL03 16-pin QFN pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to nxp.com and perform a part number search.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
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Part identification
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 43. Part number fields description
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow(full
reels for WLCSP)
• P = Prequalification
• K = Fully qualified, general market flow, 100
pieces reels (WLCSP only)
KL##
A
Kinetis family
Key attribute
• KL03
• Z = Cortex-M0+
FFF
Program flash memory size
• 8 = 8 KB
• 16 = 16 KB
• 32 = 32 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FG = 16 QFN (3 mm x 3 mm)
• AF = 20 WLCSP (2 mm x 1.61 mm x 0.56
mm)
• BF = 20 WLCSP (2 mm x 1.61 mm x 0.32
mm)
• FK = 24 QFN (4 mm x 4 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
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Terminology and guidelines
MKL03Z32VFK4
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
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Terminology and guidelines
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
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Terminology and guidelines
8.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
8.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
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Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
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Revision history
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Table 44. Typical value conditions
Symbol
TA
Description
Value
25
Unit
°C
Ambient temperature
3.3 V supply voltage
VDD
3.3
V
9 Revision history
The following table provides a revision history for this document.
Table 45. Revision history
Rev. No.
Date
Substantial Changes
3.1
4
07/2014
08/2014
Initial public release.
Changed pinout signal names ADC0_SE5, ADC0_SE6, and
ADC0_SE12 to ADC0_SE8, ADC0_SE9 and ADC0_SE15 respectively.
Table continues on the next page...
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Revision history
Table 45. Revision history (continued)
Rev. No.
Date
Substantial Changes
5
07/2017
• Added new part of MKL03Z32CBF4R and its package
information.
• Updated the Resource and its footnote to the Chip Errata in the
front page
• Updated the descriptions to the VLPW to be very low power wait
mode in the Power consumption operating behaviors
• Added a note to the TA in the Thermal operating requirements
• Updated the foot note to the Typ. of the Table 31 to be VREFO =
1.2 V
• Added I2C 1 Mbit/s timing specifications in Inter-Integrated Circuit
Interface (I2C) timing
• Updated Determining valid orderable parts
• Updated the 20-pin WLCSP package (AF) size in Fields
5.1
08/2017
Updated the Max. of MSL for WLCSP packages to 1 in the Moisture
handling ratings
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Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customerʼs technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
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WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V.
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©2014-2017 NXP B.V.
Document Number KL03P24M48SF0
Revision 5.1 08/2017
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