MKL17Z32VMP4 [NXP]
Kinetis KL17 Microcontroller;
| 型号： | MKL17Z32VMP4 |
| 厂家： | 
NXP |
| 描述： | Kinetis KL17 Microcontroller 微控制器 |
| 文件： | 总101页 (文件大小：1983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document Number: KL17P64M48SF2
Data Sheet: Technical Data
Rev. 5, 04/2015
Kinetis KL17 Microcontroller
MKL17Z32Vxx4(R)
MKL17Z64Vxx4(R)
48 MHz ARM® Cortex®-M0+ and 32/64 KB Flash
The KL17 series is optimized for cost-sensitive and battery-
powered applications requiring low-power general purpose
connectivity. The product offers:
64 LQFP (LH)
10x10x1.6 mm P .5
36 XFBGA (DA)
3.5x3.5x.5 mm P .5
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
48 & 32 QFN(FT&FM)
7x7x.65 mm P .5(FT)
5x5x.65 mm P .5(FM)
• Hardware CRC module
• Down to 46 µA/MHz in very low power run mode and 1.68
µA in stop mode (RAM + RTC retained)
64 MAPBGA (MP)
5x5x1.23 mm P .5 mm
Core Processor
Peripherals
• ARM® Cortex®-M0+ core up to 48 MHz
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
Memories
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules supporting up to 1 Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
for SPI1 and 12 Mbit/s for SPI0
• 32/64 KB program flash memory
• 8/16 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
• One FlexIO module supporting emulation of
additional UART, SPI, I2C, I2S, PWM and other
serial modules, etc.
• One 16-bit ADC module with high accurate internal
voltage reference, up to 20 channels and up to 818
ksps at equal to or less than 13-bit mode
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin SWD (serial wire debug) programming and
debug interface
• Micro trace buffer
• Bit manipulation engine
• Interrupt controller
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference
clock
• 8 MHz high accuracy (up to 3%) internal reference
clock
• 1 kHz reference clock active under all low power
modes (except VLLS0)
• 32–40 kHz and 3–32 MHz crystal oscillator
© 2014–2015 Freescale Semiconductor, Inc. All rights reserved.
Operating Characteristics
Security and Integrity
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
• 80-bit unique identification number per chip
• Advanced flash security
• Hardware CRC module
Packages
I/O
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
thickness
• 36 XFBGA 3.5mm x 3.5mm, 0.5mm pitch, 0.5mm
thickness
• 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
thickness (Package Your Way)
• Up to 54 general-purpose input/output pins
Low Power
• Down to 46 µA/MHz in very low power run mode
• Down to 1.68 µA in stop mode (RAM + RTC
retained)
• Six flexible static modes
• 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness
(Package Your Way)
NOTE
The 48 QFN and 64 MAPBGA packages supporting MKLx7ZxxVFT4 and
MKLx7ZxxVMP4 part numbers for this product are not yet available. However, these
packages are included in Package Your Way program for Kinetis MCUs. Visit
Freescale.com/KPYW for more details.
Related Resources
Type
Description
Resource
Selector Guide The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to KL1xPB1
enable quick evaluation of a device for design suitability.
Reference
Manual
The Reference Manual contains a comprehensive description of the KL17P64M48SF2RM1
structure and function (operation) of a device.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KL17P64M48SF21
Chip Errata
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
xN87M2
Package
drawing
Package dimensions are provided in package drawings.
XFBGA 36-pin: 98ASA00708D
LQFP 64-pin: 98ASS23234W
QFN 32-pin: 98ASA00615D
QFN 48-pin: 98ASA00616D
MAPBGA 64-pin: 98ASA00420D
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x”
replaced by the revision of the device you are using.
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Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering information............................................................. 4
4.3.7
Human-machine interfaces (HMI)....................38
2 Overview............................................................................... 4
2.1 System features.............................................................5
4.4 KL17 Family Pinouts......................................................38
4.5 Package dimensions......................................................43
5 Electrical characteristics........................................................51
5.1 Ratings...........................................................................51
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
ARM Cortex-M0+ core.....................................5
NVIC................................................................ 6
AWIC............................................................... 6
Memory............................................................7
Reset and boot................................................ 7
Clock options................................................... 9
Security............................................................12
Power management........................................ 12
LLWU...............................................................14
5.1.1
5.1.2
5.1.3
5.1.4
Thermal handling ratings................................. 51
Moisture handling ratings................................ 52
ESD handling ratings.......................................52
Voltage and current absolute operating
ratings..............................................................52
5.2 General.......................................................................... 53
5.2.1
5.2.2
5.2.3
5.2.4
AC electrical characteristics............................ 53
Nonswitching electrical specifications............. 53
Switching specifications...................................68
Thermal specifications.....................................69
2.1.10 Debug controller.............................................. 15
2.1.11 COP.................................................................15
2.2 Peripheral features........................................................ 16
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
BME.................................................................16
DMA and DMAMUX.........................................16
TPM................................................................. 17
ADC................................................................. 17
VREF............................................................... 18
CMP.................................................................19
RTC................................................................. 19
PIT................................................................... 20
LPTMR............................................................ 20
5.3 Peripheral operating requirements and behaviors.........70
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Core modules.................................................. 70
System modules.............................................. 72
Clock modules................................................. 72
Memories and memory interfaces................... 75
Security and integrity modules........................ 77
Analog............................................................. 77
5.4 Timers............................................................................85
5.5 Communication interfaces............................................. 85
2.2.10 CRC.................................................................21
2.2.11 UART...............................................................21
2.2.12 LPUART.......................................................... 22
2.2.13 SPI...................................................................22
2.2.14 I2C................................................................... 23
2.2.15 FlexIO.............................................................. 23
2.2.16 Port control and GPIO..................................... 24
3 Memory map......................................................................... 26
4 Pinouts.................................................................................. 27
4.1 KL17 Signal Multiplexing and Pin Assignments.............27
4.2 Pin properties.................................................................30
4.3 Module Signal Description Tables................................. 33
5.5.1
5.5.2
5.5.3
SPI switching specifications............................ 85
Inter-Integrated Circuit Interface (I2C) timing.. 89
UART...............................................................91
6 Design considerations...........................................................91
6.1 Hardware design considerations................................... 91
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Printed circuit board recommendations........... 92
Power delivery system.....................................92
Analog design..................................................93
Digital design................................................... 93
Crystal oscillator.............................................. 96
6.2 Software considerations................................................ 98
7 Part identification...................................................................99
7.1 Description.....................................................................99
7.2 Format........................................................................... 99
7.3 Fields............................................................................. 99
7.4 Example.........................................................................100
8 Revision history.....................................................................100
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Core modules.................................................. 33
System modules.............................................. 33
Clock modules................................................. 34
Analog............................................................. 34
Timer Modules.................................................35
Communication interfaces............................... 36
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
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Freescale Semiconductor, Inc.
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
Part number
Marking
Flash
(KB)
SRAM
(KB)
Pin
count
Package
GPIOs
GPIOs
ADC
(INT/HD)1 channels
(SE/DP)
(Line1/Line2)
MKL17Z64VLH4
MKL17Z32VLH4
MKL17Z64VDA4
MKL17Z32VDA4
MKL17Z64VFM4
MKL17Z32VFM4
MKL17Z64VMP4
MKL17Z32VMP4
MKL17Z64VFT4
MKL17Z32VFT4
MKL17Z64 / VLH4
MKL17Z32 / VLH4
M17M6
64
32
64
32
64
32
64
32
64
32
16
8
64
64
36
36
32
32
64
64
48
48
LQFP
LQFP
54
54
32
32
28
28
54
54
40
40
54/6
54/6
32/6
32/6
28/6
28/6
54/6
54/6
40/6
40/6
20/4
20/4
15/4
15/4
11/2
11/2
20/4
20/4
18/3
18/3
16
8
XFBGA
XFBGA
QFN
M17M5
M17M6V
M17M5V
TBD
16
8
QFN
16
8
MAPBGA
MAPBGA
QFN
TBD
TBD
16
8
TBD
QFN
1. INT: interrupt pin numbers; HD: high drive pin numbers
NOTE
The 48 QFN and 64 MAPBGA packages supporting MKLx7ZxxVFT4 and
MKLx7ZxxVMP4 part numbers for this product are not yet available.
However, these packages are included in Package Your Way program for
Kinetis MCUs. Visit Freescale.com/KPYW for more details.
2 Overview
The following figure shows the system diagram of this device
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Overview
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
Slave
Master
M0
Cortex M0+
IOPORT
ADC(16 bit 16ch)
64 KB
Flash
FMC
CMP
Debug
(SWD)
CM0+ Core
1.2 V Voltage reference
TPM0(6 channel)
TPM1(2 channel)
TPM2(2 channel)
S0
S1
NVIC
16 KB ROM
16 KB RAM
Low Power Timer
PIT
M2
RTC
4-ch
DMA
DMA
MUX
LPUART0
LPUART1
UART2
SPI0
S2
SPI1
BME
I2C0
I2C1
FlexIO
Watchdog(COP)
Register File(32 Bytes)
CRC
MCG - Lite
OSC
LLWU
RCM
SMC
PMC
HIRC48M
LIRC2M/8M
Figure 1. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1 System features
The following sections describe the high-level system features.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
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Overview
2.1.1 ARM Cortex-M0+ core
The enhanced ARM Cortex M0+ is the member of the Cortex-M series of processors
targeting microcontroller cores focused on very cost sensitive, low power applications.
It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It
also has hardware debug functionality including support for simple program trace
capability. The processor supports the ARMv6-M instruction set (Thumb) architecture
including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It
is upward compatible with other Cortex-M profile processors.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It
also differs in number of interrupt sources and supports 32 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency to up to 15
clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and
VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous
wake-up events in Stop mode and signal to clock control logic to resume system
clocking. After clock restarts, the NVIC observes the pending interrupt and performs
the normal interrupt or event processing. The AWIC can be used to wake MCU core
from Stop and VLPS modes.
Wake-up sources are listed as below:
Table 2. AWIC stop wake-up sources
Wake-up source
Description
Available system resets
RESET pin with filter mode disabled or enabled when LPO is its clock source, COP when its
clock source is enabled. COP can also work when its clock source is enabled during Stop
mode.
Low-voltage detect
Low-voltage warning
Pin interrupts
ADC
Power management controller—functional in Stop mode
Power management controller—functional in Stop mode
Port control module—any enabled pin interrupt is capable of waking the system
The ADC is functional when using internal clock source or external crystal clock
Interrupt in normal or trigger mode
CMP0
Table continues on the next page...
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Overview
Table 2. AWIC stop wake-up sources (continued)
Wake-up source
Description
Address match wakeup
I2Cx
LPUART0 , LPUART1
Any enabled interrupt can be a source as long as the module remains clocked
Active edge on RXD
UART2
RTC
Alarm or seconds interrupt
NMI
NMI pin
TPMx
LPTMR
SPIx
Any enabled interrupt can be a source as long as the module remains clocked
Any enabled interrupt can be a source as long as the module remains clocked
Slave mode interrupt
FlexIO
Any enabled interrupt can be a source as long as the module remains clocked
2.1.4 Memory
This device has the following features:
• 8/16 KB of embedded RAM accessible (read/write) at CPU clock speed with 0
wait states.
• The non-volatile memory is divided into two arrays
• 32/64 KB of embedded program memory
• 16 KB ROM (built-in bootloader to support UART, I2C, and SPI interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program
flash is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents
from debug port.
• System register file
This device contains a 32-byte register file that is powered in all power modes.
Also, it retains contents during low power modes and is reset only during a
power-on reset.
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Overview
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the footnote,
is reset by the corresponding Reset source. N means the
specific module is not reset by the corresponding Reset
source.
Table 3. Reset source
Reset
Descriptions
Modules
sources
PMC
SIM
SMC RCM LLWU Reset pin RTC LPTMR Others
is
negated
POR reset
Power-on reset (POR)
Y
Y1
N
Y
Y
Y2
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Y
Y3
Y
N
N
Y
Y
N
Y
Y
Y
System resets Low-voltage detect (LVD)
Low leakage wakeup
(LLWU) reset
External pin reset
(RESET)
Y1
Y1
Y2
Y2
Y4
Y4
Y
Y
Y
Y
Y
N
N
N
N
Y
Y
Computer operating
properly (COP) watchdog
reset
Y5
Stop mode acknowledge
error (SACKERR)
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
Software reset (SW)
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Lockup reset (LOCKUP)
MDM DAP system reset
Debug reset
Debug reset
1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Except SIM_SOPT1
3. Only if RESET is used to wake from VLLS mode.
4. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
5. Except RCM_RPFC, RCM_RPFW, RCM_FM
The CM0+ core adds support for a programmable Vector Table Offset Register
(VTOR) to relocate the exception vector table after reset. This device supports booting
from:
• internal flash
• boot ROM
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Overview
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains
read-only bits that are loaded from the NVM's option byte in the flash configuration
field. Below is boot flow chart for this device.
POR or Reset
N
RCM[FORCEROM] =00
Y
N
FOPT[BOOTPIN_OPT]=0
Y
N
BOOTCFG0 pin=0
Y
N
FOPT[BOOTSRC
_SEL]=10/11
Y
Boot from ROM
Boot from Flash
Figure 2. Boot flow chart
The blank chip is default to boot from ROM and remaps the vector table to ROM base
address, otherwise, it remaps to flash address.
2.1.6 Clock options
This chip provides a wide range of sources to generate the internal clocks. These
sources include internal resistor capacitor (IRC) oscillators, external oscillators,
external clock sources, and ceramic resonators. These sources can be configured to
provide the required performance and optimize the power consumption.
The IRC oscillators include the high-speed internal resister capacitor (HIRC)
oscillator, the low-speed internal resister capacitor (LIRC) oscillator, and the low
power oscillator (LPO).
The HIRC oscillator generates a 48 MHz clock.
The LIRC oscillator generates an 8 MHz or 2 MHz clock, and default to 8 MHz
system clock on reset. The LIRC oscillator cannot be used in any VLLS modes.
The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode.
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Overview
The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high
frequency crystals (1 MHz to 32 MHz), and ceramic resonators (1 MHz to 32 MHz). An
external clock source, DC to 48 MHz, can be used as the system clock through the
EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768
kHz) on the RTC_CLKIN pin for use with the RTC.
For more details on the clock operations and configurations, see Reference Manual.
The following figure is a high level block diagram of the clock generation.
Multipurpose Clock
Generator Lite
System
Integration
MCGPCLK
MCGIRCLK
HIRC48M
IRC_TRIMs
CG
LIRC_DIV2
LIRC
8MHz
8MHz/
2MHz
IRC
MCGOUTCLK
FCRDIV
OUTDIV1
OUTDIV4
CG
CG
Core/Platform/System clock
Bus/Flash clock
2MHz
IRCS
CLKS
System oscillator
EREFS0
OSCCLK
CG
EXTAL0
XTAL_CLK
OSC
OSCERCLK
ERCLK32K
OSC32KCLK
logic
XTAL0
RTC_CKLIN
OS32KSEL
RTCCLKOUTSEL
LPO
PMC logic
PMC
RTC
RTC_CLKOUT
1Hz
Counter logic
CG — Clock gate
Figure 3. Clock block diagram
In order to provide flexibility, many peripherals can select from multiple clock sources
for operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
The following table summarizes the clocks associated with each module.
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Overview
Table 4. Module clocks
Module
Bus interface clock
Core modules
Internal clocks
I/O interface clocks
ARM Cortex-M0+ core
Platform clock
Platform clock
Platform clock
Core clock
—
—
NVIC
DAP
—
—
SWD_CLK
System modules
DMA
DMA Mux
System clock
Bus clock
—
—
—
—
—
—
—
—
—
—
—
Port control
Bus clock
—
Crossbar Switch
Peripheral bridges
LLWU, PMC, SIM, RCM
Mode controller
MCM
Platform clock
System clock
Bus clock
—
Bus clock
LPO
—
Bus clock
Platform clock
Bus clock
—
COP watchdog
LPO, Bus Clock,
MCGIRCLK, OSCERCLK
CRC
Bus clock
Bus clock
—
—
—
Clocks
MCG_Lite
MCGOUTCLK, MCGPCLK,
MCGIRCLK, OSCERCLK,
ERCLK32K
OSC
Bus clock
OSCERCLK
—
Memory and memory interfaces
Flash Controller
Flash memory
Platform clock
Flash clock
Flash clock
—
—
—
Analog
ADC
CMP
Bus clock
Bus clock
Bus clock
OSCERCLK
—
—
—
—
—
Internal Voltage Reference
(VREF)
Timers
TPM
PIT
Bus clock
Bus clock
Bus clock
TPM clock
—
TPM_CLKIN0, TPM_CLKIN1
—
—
LPTMR
LPO, OSCERCLK,
MCGPCLK, ERCLK32K
RTC
Bus clock
ERCLK32K
RTC_CLKOUT, RTC_CLKIN
Communication interfaces
SPI0
SPI1
I2C0
Bus clock
—
—
—
SPI0_SCK
SPI1_SCK
I2C0_SCL
System clock
System Clock
Table continues on the next page...
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Overview
Table 4. Module clocks (continued)
Module
Bus interface clock
System Clock
Bus clock
Internal clocks
—
I/O interface clocks
I2C1
I2C1_SCL
—
LPUART0, LPUART1
LPUART0 clock
LPUART1 clock
—
UART2
FlexIO
Bus clock
Bus clock
—
—
FlexIO clock
Human-machine interfaces
GPIO
Platform clock
—
—
2.1.7 Security
Security state can be enabled via programming flash configuration field (0x40e). After
enabling device security, the SWD port cannot access the memory resources of the
MCU, and ROM boot loader is also limited to access flash and not allowed to read out
flash information via ROM boot loader commands.
Access interface
Secure state
Unsecure operation
SWD port
Cannot access memory source by SWD The debugger can write to the Flash
interface
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
ROM boot loader Interface (UART/I2C/ Limit access to the flash, cannot read
SPI) out flash content
Send “FlashEraseAllUnsecureh"
command or attempt to unlock flash
security using the backdoor key
This device features 80-bit unique identification number, which is programmed in
factory and loaded to SIM register after power-on reset.
2.1.8 Power management
The Power Management Controller (PMC) expands upon ARM’s operational modes of
Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can
be used to optimize current consumption for a wide range of applications. The WFI or
WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on ARM’s operational modes, See the ARM®
Cortex User Guide.
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Overview
The PMC provides Run (Run), and Very Low Power Run (VLPR) configurations in
ARM’s Run operation mode. In these modes, the MCU core is active and can access
all peripherals. The difference between the modes is the maximum clock frequency of
the system and therefore the power consumption. The configuration that matches the
power versus performance requirements of the application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop
(LLS), and Very Low Leakage Stop (VLLS) configurations in ARM’s Deep Sleep
operational mode. In these modes, the MCU core and most of the peripherals are
disabled. Depending on the requirements of the application, different portions of the
analog, logic, and memory can be retained or disabled to conserve power.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are
used to wake up the MCU from low power states. The NVIC is used to wake up the
MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU
core from STOP and VLPS modes. The LLWU is used to wake up the MCU core
from LLS and VLLSx modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, or the LLWU, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 6. Peripherals states in different operational modes
Core mode
Device mode
Descriptions
Run mode
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode
Wait
In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
Table continues on the next page...
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Overview
Table 6. Peripherals states in different operational modes (continued)
Core mode
Deep sleep
Device mode
Descriptions
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static
state. Stop mode retains all registers and SRAMs while maintaining Low
Voltage Detection protection. In Stop mode, the ADC, CMP, LPTimer, RTC,
and pin interrupts are operational. The NVIC is disabled, but the AWIC can
be used to wake up from an interrupt.
Very Low Power Stop
Low Leakage Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low
speed), ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, and DMA are
operational, LVD and NVIC are disabled, AWIC is used to wake up from
interrupt.
In LLS mode, the contents of the SRAM and the 32-byte system register file
are retained. The CMP (low speed), LLWU, LPTMR, and RTC are
operational. The ADC, CRC, DMA, FlexIO, I2C, LPUART, MCG-Lite, NVIC,
PIT, SPI, TPM, UART, and COP are static, but retain their programming. The
GPIO, and VREF are static, retain their programming, and continue to drive
their previous values.
Very Low Leakage Stop In VLLS modes, most peripherals are powered off and will resume operation
from their reset state when the device wakes up. The LLWU, LPTMR, and
RTC are operational in all VLLS modes.
In VLLS3, the contents of the SRAM and the 32-byte system register file are
retained. The CMP (low speed), and PMC are operational. The GPIO, and
VREF are not operational but continue driving.
In VLLS1, the contents of the 32-byte system register file are retained. The
CMP (low speed), and PMC are operational. The GPIO, and VREF are not
operational but continue driving.
In VLLS0, the contents of the 32-byte system register file are retained. The
PMC is operational. The GPIO is not operational but continues driving. The
POR detection circuit can be enabled or disabled.
2.1.9 LLWU
The LLWU module is used to wake MCU from low leakage power mode (LLS and
VLLSx) and functional only on entry into a low-leakage power mode. After recovery
from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU
continues to detect wake-up events until the user has acknowledged the wake-up event.
This device uses 8 external wakeup pin inputs and 4 internal modules as wakeup
sources to the LLWU module.
The following is internal peripheral and external pin inputs as wakeup sources to the
LLWU module.
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Overview
Table 7. Wakeup source
LLWU pin
LLWU_P5
Module source or pin name
PTB0
PTC1
LLWU_P6
LLWU_P7
PTC3
LLWU_P8
PTC4
LLWU_P9
PTC5
LLWU_P10
LLWU_P14
LLWU_P15
LLWU_M0IF
LLWU_M1IF
LLWU_M2IF
LLWU_M3IF
LLWU_M4IF
LLWU_M5IF
LLWU_M6IF
LLWU_M7IF
PTC6
PTD4
PTD6
LPTMR0
CMP0
Reserved
Reserved
Reserved
RTC alarm
Reserved
RTC seconds
2.1.10 Debug controller
This device supports standard ARM 2-pin SWD debug port. It provides register and
memory accessibility from the external debugger interface, basic run/halt control plus
2 breakpoints and 2 watchpoints.
It also supports trace function with the Micro Trace Buffer (MTB), which provides a
simple execution trace capability for the Cortex-M0+ processor.
2.1.11 COP
The COP monitors internal system operation and forces a reset in case of failure. It
can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator.
Optional window mode can detect deviations in program flow or system frequency.
The COP has the following features:
• Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal
reference clock, external crystal oscillator
• Can work in Stop/VLPS and Debug mode
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Overview
• Configurable for short and long timeout values, the longest timeout is up to 262
seconds
• Support window mode
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
2.2.1 BME
The Bit Manipulation Engine (BME) provides hardware support for atomic read-
modify-write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for
bit-oriented operations to peripheral registers.
The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit,
bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized
data type.
2.2.2 DMA and DMAMUX
The DMA controller module enables fast transfers of data, which provides an efficient
way to move blocks of data with minimal processor interaction. The DMA controller in
this device implements four channels which can be routed from up to 63 DMA request
sources through DMA MUX module. Some of the peripheral request sources have
asynchronous DMA capability which can be used to wake MCU from Stop mode. The
peripherals which have such capability include LPUART0, LPUART1, FlexIO, TPM0-
TPM2, ADC0, CMP0, PORTA-PORTE. The DMA channel 0 and 1 can be periodically
triggered by PIT via DMA MUX.
Main features are listed below:
• Dual-address transfers via 32-bit master connection to the system bus and data
transfers in 8-, 16-, or 32-bit blocks
• Supports programmable source and destination address and transfer size, optional
modulo addressing from 16 bytes to 256 KB
• Automatic updates of source and destination addresses
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Overview
• Auto-alignment feature for source or destination accesses allows block transfers
to occur at the optimal size based on the address, byte count,and programmed
size, which significantly improves the speed of block transfer
• Automatic single or double channel linking allows the current DMA channel to
automatically trigger a DMA request to the linked channels without CPU
intervention
For more information on asynchronous DMA, see AN4631.
2.2.3 TPM
This device contains three low power TPM modules (TPM). All TPM modules are
functional in Stop/VLPS mode if the clock source is enabled.
The TPM features include:
• TPM clock mode is selectable from external clock input or internal clock source,
HIRC48M clock, external crystal input clock or LIRC2M/8M clock.
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare,
edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
• Support selectable trigger input to optionally reset or cause the counter to start or
stop incrementing
• Support the generation of hardware triggers when the counter overflows and per
channel
2.2.4 ADC
this device contains one ADC module. This ADC module supports hardware triggers
from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports
wakeup of MCU in low power mode when using internal clock source or external
crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16-
bit, 12-bit, 10-bit, and 8-bit single-ended output modes
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Overview
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the
clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-Calibration mode
2.2.4.1 Temperature sensor
This device contains one temperature sensor internally connected to the input channel
of AD26, see Table 55 for details of the linearity factor.
The sensor must be calibrated to gain good accuracy, so as to provide good linearity,
see also AN3031. We recommend to use internal reference voltage as ADC reference
with long sample time.
2.2.5 VREF
The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically)
trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage to
external devices or used internally as a reference to analog peripherals such as the ADC
or CMP.
The VREF supports the following programmable buffer modes:
• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled
The VREF voltage output signal, bonded on VREFH for 48 QFN, 64 LQFP and 64
MAPBGA packages and on PTE30 for 32 QFN and 36 XFBGA packages, can be used
by both internal and external peripherals in low and high power buffer mode. A 100 nF
capacitor must always be connected between this pin and VSSA if the VREF is used.
This capacitor must be as close to VREFO pin as possible.
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Overview
2.2.6 CMP
The device contains one high-speed comparator and two 8-input multiplexers for both
the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes.
The CMP includes one 6-bit DAC, which provides a selectable voltage reference for
various user application cases. Besides, the CMP also has several module-to-module
interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: shorter propagation delay at the
expense of higher power and Low power with longer propagation delay
• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
• Integrated 6-bit DAC with selectable supply reference source and can be power
down to conserve power
• Two 8-to-1 channel mux
2.2.7 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the oscillator or clock directly from RTC_CLKIN pin.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
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Overview
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
2.2.8 PIT
The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It
has two independent channels and each channel has a 32-bit counter. Both channels can
be chained together to form a 64-bit counter.
Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be
used to periodically trigger DMA channel 1. Either channel can be programmed as an
ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger
DAC.
The PIT module has the following features:
• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC
2.2.9 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
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Overview
2.2.10 CRC
This device contains one cyclic redundancy check (CRC) module which can generate
16/32-bit CRC code for error detection.
The CRC module provides a programmable polynomial, WAS, and other parameters
required to implement a 16-bit or 32-bit CRC standard.
The CRC module has the following features:
• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift
register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface
2.2.11 UART
This device contains a basic universal asynchronous receiver/transmitter (UART)
module with DMA function supported. Generally, this module is used in RS-232,
RS-485, and other communications and supports LIN slave operation and ISO7816.
The UART module has the following features:
• Full-duplex operation
• 13-bit baud rate selection with /32 fractional divide, based on the module clock
frequency
• Programmable 8-bit or 9-bit data format
• Programmable transmitter output polarity
• Programmable receive input polarity
• Up to 14-bit break character transmission.
• 11-bit break character detection option
• Two receiver wakeup methods with idle line or address mark wakeup
• Address match feature in the receiver to reduce address mark wakeup ISR
overhead
• Ability to select MSB or LSB to be first bit on wire
• Support for ISO 7816 protocol to interface with SIM cards and smart cards
• Receiver framing error detection
• Hardware parity generation and checking
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Overview
• 1/16 bit-time noise detection
• DMA interface
2.2.12 LPUART
This product contains two Low-Power UART modules, both of their clock sources are
selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop
and VLPS modes. They also support 4× to 32× data oversampling rate to meet different
applications.
The LPUART module has the following features:
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4× to 32×
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
2.2.13 SPI
This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes.
FIFO function is available only on SPI1 module.
The SPI modules have the following features:
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Overview
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA
2.2.14 I2C
This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer
features, and address match to wake MCU from the low power mode.
I2C modules support DMA transfer, and the interrupt condition can trigger DMA
request when DMA function is enabled.
The I2C modules have the following features:
• Support for system management bus (SMBus) Specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Programmable input glitch filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support
• Double buffering support to achieve higher baud rate
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Overview
2.2.15 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to UART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/
Waveform generation. The module supports programmable baud rates independent of
bus clock frequency, with automatic start/stop bit generation.
The FlexIO module has the following features:
• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using
remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match
modes, and continuous data transfer
• The timing of the shifter’ shift, load and store events are controlled by the highly
flexible 16-bit timer assigned to the shifter
• Two or more shifter can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable on
a variety of internal or external trigger conditions with programmable trigger
polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional
output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation
2.2.16 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control, digital
filtering, and external interrupt functions. The GPIO data direction and output data
registers control the direction and output data of each pin when the pin is configured for
the GPIO function. The GPIO input data register displays the logic value on each pin
when the pin is configured for any digital function, provided the corresponding Port
Control and Interrupt module for that pin is enabled.
The following figure shows the basic I/O pad structure. This diagram applies to all I/O
pins except PTA20/RESET_b and those configured as pseudo open-drain outputs.
PTA20/RESET_b is a true open-drain pin without p-channel output driver or diode to
the ESD bus. Pseudo open-drain pins have the p-channel output driver disabled when
configured for open-drain operation. None of the I/O pins, including open-drain and
pseudo open-drain pins, are allowed to go above VDD.
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Overview
Digital input
IBE=1 whenever
MUX≠000
PFE
IBE
ESD
Bus
VDD
RPULL
PE
PS
Analog input
Digital output
DSE
SRE
Figure 4. I/O simplified block diagram
The PORT module has the following features:
• all PIN support interrupt enable .
• Configurable edge(rising,falling,both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable fast and slow slew rates on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
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Memory map
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. The following figure shows the system memory and
peripheral locations
0x4000_0000
Reserved
0x4000_8000
DMA controller
Reserved
0x4000_E000
Reserved
0x4000_F000
GPIO controller(alias to 0x400F_F000)
0x0000_0000
Reserved
0x4002_0000
Flash memory
DMA Channel Multiplexer
Reserved
CRC32
Flash
ROM
0x4002_1000
0x4003_2000
0x0000_0000
0x07FF_FFFF
0x1C00_0000
Code space
Reserved
0x07FF_FFFF
0x1C00_0000
Reserved
PIT
LPTPM0
LPTPM1
LPTPM2
ADC0
Reserved
RTC
Reserved
LPTMR
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x1
Boot ROM
Reserved
0x1C00_3FFF
0x1C00_4000
0x1FFF_F000
0x4003_D000
0x1FFF_F000
0x2000_0000
0x4004_0000
0x4004_1000
SRAM_L
SRAM_U
Data Space
Reserved
0x4004_7000
0x4004_8000
0x4004_9000
0x0000_A000
0x4004_B000
0x4004_C000
0x4004_D000
System register file
Reserved
SIM low power logic
SIM
0x2000_3000
0x4000_0000
0x2000_2FFF
0x4000_0000
Public
peripheral
PORT A
PORT B
PORT C
PORT D
AIPS
peripherals
0x4007_FFFF
0x400F_E000
0x400F_F000
0x4400_0000
Reserved
BME
Reserved
GPIO
0x4005_4000
0x4005_5000
0x400F_E1FF
0x400F_F000
PORT E
0x6000_0000
0xE000_0000
Reserved
LPUART0
LPUART1
Reserved
FlexIO
Reserved
MCG Lite
OSC
0x4005_F000
0x400F_FFFF
Reserved
0x4006_4000
Private
peripherals
0xE010_0000
0xF000_0000
Reserved
MTB
0x4006_5000
0x4006_6000
0x4006_7000
0xE010_0000
0xFFFF_FFFF
0xF000_1000
0xF000_2000
0xF000_3000
MTBDWT
ROM Table
MCM
0x4006_C000
I2C0
I2C1
Others
0x4007_2000
0x4007_3000
0x4007_4000
Reserved
UART2
Reserved
Reserved
CMP
VREF
Reserved
SPI0
0xF000_4000
0xF800_0000
0x4007_6000
0x4007_7000
Reserved
IOPORT
0x4007_C000
0xFFFF_FFFF
0x4007_D000
0x4007_E000
0x4007_F000
SPI1
Figure 5. Memory map
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Pinouts
4 Pinouts
4.1 KL17 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
The 48 QFN and 64 MAPBGA packages for this product are
not yet available. However, these packages are included in
Package Your Way program for Kinetis MCUs. Visit
freescale.com/KPYW for more details.
64
LQFP
36
XFB
GA
32
QFN
48
QFN
64
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
—
—
1
F2
—
9
—
1
—
—
—
—
C5
A1
VREF0
NC
VREF0_B
NC
VREF0_B
NC
A1
PTE0
DISABLED
PTE0/
CLKOUT32
K
SPI1_MISO LPUART1_
TX
RTC_
CLKOUT
CMP0_OUT I2C1_SDA
SPI1_MISO I2C1_SCL
2
B1
2
—
B1
PTE1
DISABLED
PTE1
SPI1_MOSI LPUART1_
RX
3
4
5
—
C4
C2
—
—
3
1
2
3
—
C4
E1
VDD
VDD
VSS
VDD
VSS
VSS
PTE16
ADC0_DP1/ ADC0_DP1/ PTE16
SPI0_PCS0 UART2_TX
TPM_
FXIO0_D0
ADC0_SE1
ADC0_SE1
CLKIN0
6
C1
4
4
D1
PTE17
ADC0_
DM1/
ADC0_
DM1/
PTE17
SPI0_SCK
UART2_RX TPM_
LPTMR0_
ALT3
FXIO0_D1
CLKIN1
ADC0_
SE5a
ADC0_
SE5a
7
8
D1
D2
5
6
5
6
E2
D2
PTE18
PTE19
ADC0_DP2/ ADC0_DP2/ PTE18
SPI0_MOSI
SPI0_MISO
I2C0_SDA
I2C0_SCL
SPI0_MISO FXIO0_D2
SPI0_MOSI FXIO0_D3
ADC0_SE2
ADC0_SE2
ADC0_
DM2/
ADC0_
DM2/
PTE19
ADC0_
SE6a
ADC0_
SE6a
9
E3
E2
—
—
7
8
G1
F1
PTE20
PTE21
ADC0_DP0/ ADC0_DP0/ PTE20
TPM1_CH0 LPUART0_
TX
FXIO0_D4
FXIO0_D5
ADC0_SE0
ADC0_SE0
10
ADC0_
DM0/
ADC0_
DM0/
PTE21
TPM1_CH1 LPUART0_
RX
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
27
Freescale Semiconductor, Inc.
Pinouts
64
36
32
48
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP
XFB
GA
QFN
QFN
MAP
BGA
ADC0_
SE4a
ADC0_
SE4a
11
12
E1
F1
—
—
—
—
G2
F2
PTE22
PTE23
ADC0_DP3/ ADC0_DP3/ PTE22
TPM2_CH0 UART2_TX
TPM2_CH1 UART2_RX
FXIO0_D6
FXIO0_D7
ADC0_SE3
ADC0_SE3
ADC0_
DM3/
ADC0_
DM3/
PTE23
ADC0_
SE7a
ADC0_
SE7a
13
14
14
15
16
17
D3
D3
—
7
7
9
F4
G4
G4
G3
F3
H1
VDDA
VDDA
VDDA
10
10
11
12
13
VREFH
VREFO
VREFL
VSSA
VREFH
VREFO_A
VREFL
VSSA
VREFH
VREFO_A
VREFL
VSSA
—
8
D4
D4
—
8
—
PTE29
CMP0_IN5/
ADC0_
SE4b
CMP0_IN5/
ADC0_
SE4b
PTE29
PTE30
TPM0_CH2 TPM_
CLKIN0
18
F2
9
14
H2
PTE30
ADC0_
SE23/
ADC0_
SE23/
TPM0_CH3 TPM_
CLKIN1
LPUART1_
TX
LPTMR0_
ALT1
CMP0_IN4
CMP0_IN4
19
20
21
22
23
—
—
—
F3
F4
—
—
—
10
11
—
15
16
17
18
H3
H4
H5
D3
D4
PTE31
PTE24
PTE25
PTA0
DISABLED
DISABLED
DISABLED
SWD_CLK
DISABLED
PTE31
PTE24
PTE25
PTA0
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
TPM2_CH0
I2C0_SCL
I2C0_SDA
SWD_CLK
PTA1
PTA1
LPUART0_
RX
24
E4
12
19
E5
PTA2
DISABLED
PTA2
LPUART0_
TX
TPM2_CH1
25
26
27
28
29
30
31
32
E5
F5
—
13
14
—
—
—
15
16
17
20
21
—
—
—
22
23
24
D5
G5
F5
PTA3
PTA4
PTA5
PTA12
PTA13
VDD
SWD_DIO
NMI_b
PTA3
PTA4
PTA5
PTA12
PTA13
I2C1_SCL
I2C1_SDA
TPM0_CH0
TPM0_CH1
TPM0_CH2
TPM1_CH0
TPM1_CH1
SWD_DIO
NMI_b
DISABLED
DISABLED
DISABLED
VDD
—
H6
G6
G7
H7
H8
—
C3
C4
F6
VDD
VSS
VSS
VSS
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
PTA20
LPUART1_
RX
TPM_
CLKIN0
33
E6
18
25
G8
PTA19
PTA20
XTAL0
XTAL0
LPUART1_
TX
TPM_
CLKIN1
LPTMR0_
ALT1
34
35
D5
D6
19
20
26
27
F8
F7
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8
ADC0_SE8
ADC0_SE9
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
TPM1_CH0 SPI1_MOSI SPI1_MISO
TPM1_CH1 SPI1_MISO SPI1_MOSI
36
C6
21
28
F6
PTB1
ADC0_SE9
PTB1
28
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Pinouts
64
LQFP
36
XFB
GA
32
QFN
48
QFN
64
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
37
38
39
40
—
—
—
—
—
—
—
—
29
30
31
32
E7
E8
E6
D7
PTB2
ADC0_
SE12
ADC0_
SE12
PTB2
I2C0_SCL
I2C0_SDA
TPM2_CH0
TPM2_CH1
PTB3
ADC0_
SE13
ADC0_
SE13
PTB3
PTB16
PTB17
DISABLED
PTB16
PTB17
SPI1_MOSI LPUART0_
RX
TPM_
CLKIN0
SPI1_MISO
SPI1_MOSI
DISABLED
SPI1_MISO LPUART0_
TX
TPM_
CLKIN1
41
42
43
—
—
—
—
—
—
—
—
33
D6
C7
D8
PTB18
PTB19
PTC0
DISABLED
DISABLED
PTB18
PTB19
PTC0
TPM2_CH0
TPM2_CH1
EXTRG_IN
ADC0_
SE14
ADC0_
SE14
CMP0_OUT
44
C5
22
34
C6
PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
I2C1_SDA
TPM0_CH0
TPM0_CH1
45
46
B6
B5
23
24
35
36
B7
C8
PTC2
ADC0_
SE11
ADC0_
SE11
PTC2
PTC3/
LLWU_P7
DISABLED
PTC3/
LLWU_P7
SPI1_SCK
LPUART1_
RX
TPM0_CH2 CLKOUT
47
48
49
—
—
—
—
25
—
—
37
E3
E4
B8
VSS
VDD
VSS
VSS
VDD
VDD
A6
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0 LPUART1_
TX
TPM0_CH3 SPI1_PCS0
50
51
A5
B4
26
27
38
39
A8
A7
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
CMP0_OUT
PTC6/
LLWU_P10
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI EXTRG_IN
SPI0_MISO
SPI0_MOSI
52
53
54
55
56
57
58
A4
—
—
—
—
—
—
28
—
—
—
—
—
—
40
—
—
—
—
41
42
B6
A6
B5
B4
A5
C3
A4
PTC7
PTC8
PTC9
PTC10
PTC11
PTD0
PTD1
CMP0_IN1
CMP0_IN2
CMP0_IN3
DISABLED
DISABLED
DISABLED
CMP0_IN1
CMP0_IN2
CMP0_IN3
PTC7
PTC8
PTC9
PTC10
PTC11
PTD0
PTD1
SPI0_MISO
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
SPI0_PCS0
SPI0_SCK
TPM0_CH4
TPM0_CH5
TPM0_CH0
TPM0_CH1
FXIO0_D0
FXIO0_D1
ADC0_
SE5b
ADC0_
SE5b
59
60
61
—
—
—
—
29
43
44
45
C2
B3
A3
PTD2
PTD3
DISABLED
DISABLED
DISABLED
PTD2
PTD3
SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2
SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3
SPI1_PCS0 UART2_RX TPM0_CH4
A3
PTD4/
LLWU_P14
PTD4/
LLWU_P14
FXIO0_D4
FXIO0_D5
62
63
B3
B2
30
31
46
47
C1
B2
PTD5
ADC0_
SE6b
ADC0_
SE6b
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
I2C1_SDA
PTD6/
LLWU_P15
ADC0_
SE7b
ADC0_
SE7b
PTD6/
LLWU_P15
SPI1_MOSI LPUART0_
RX
SPI1_MISO FXIO0_D6
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
29
Freescale Semiconductor, Inc.
Pinouts
64
36
32
48
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP
XFB
GA
QFN
QFN
MAP
BGA
64
A2
32
48
A2
PTD7
DISABLED
PTD7
SPI1_MISO LPUART0_
TX
I2C1_SCL
SPI1_MOSI FXIO0_D7
4.2 Pin properties
The following table lists the pin properties.
—
—
1
F2
—
9
—
1
—
—
—
—
1
—
C5
A1
B1
—
VREF0
NC
—
—
—
—
—
—
—
—
N
—
—
—
ND
ND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
—
Y
A1
B1
—
PTE0
Hi-Z
Hi-Z
—
FS
FS
—
2
2
PTE1
N
N
Y
3
—
—
3
VDD
—
—
N
—
—
N
—
—
Y
4
C4
C2
C1
D1
D2
E3
E2
E1
F1
D3
D3
—
2
C4
E1
D1
E2
D2
G1
F1
G2
F2
F4
G4
G4
G3
F3
H1
VSS
—
—
—
5
3
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFO
VREFL
VSSA
PTE29
ND
ND
ND
ND
ND
ND
ND
ND
—
Hi-Z
HI-Z
Hi-Z
HI-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
FS
FS
FS
FS
SS
SS
SS
SS
—
6
4
4
N
N
Y
7
5
5
N
N
Y
8
6
6
N
N
Y
9
—
—
—
—
7
7
N
N
Y
10
11
12
13
14
14
15
16
17
8
N
N
Y
—
—
9
N
N
Y
N
N
Y
—
—
—
—
—
N
—
—
—
—
—
N
—
—
—
—
—
Y
7
10
10
11
12
13
—
—
—
—
8
—
—
—
D4
D4
—
—
—
—
8
—
—
—
—
ND
Hi-Z
SS
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
30
Freescale Semiconductor, Inc.
Pinouts
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
F2
—
9
14
—
15
16
17
18
19
20
21
—
—
—
22
23
24
25
26
27
28
29
30
31
32
—
—
33
34
H2
H3
H4
H5
D3
D4
E5
D5
G5
F5
H6
G6
G7
H7
H8
G8
F8
F7
F6
E7
E8
E6
D7
D6
C7
D8
C6
PTE30
PTE31
PTE24
PTE25
PTA0
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
HD
HD
ND
ND
ND
ND
ND
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L
—
—
—
—
PD
—
—
PU
PU
—
—
—
—
—
—
—
PU
—
—
—
—
—
—
—
—
—
—
SS
SS
SS
SS
SS
SS
SS
FS
SS
SS
SS
SS
—
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
—
—
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
10
11
12
13
14
—
—
—
15
16
17
18
19
20
21
—
—
—
—
—
—
—
22
—
—
F3
F4
E4
E5
F5
—
PTA1
Hi-Z
Hi-Z
H
PTA2
PTA3
PTA4
H
PTA5
Hi-Z
Hi-Z
Hi-Z
—
N
N
N
—
—
N
N
N
N
N
N
N
N
N
N
N
N
N
—
PTA12
PTA13
VDD
—
C3
C4
F6
E6
D5
D6
C6
—
VSS
—
—
PTA18
PTA19
PTA20
PTB0/LLWU_P5
PTB1
Hi-Z
Hi-Z
H
SS
SS
SS
FS
FS
SS
SS
FS
FS
SS
SS
SS
SS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
N
N
N
N
N
N
N
N
N
N
PTB2
—
PTB3
—
PTB16
PTB17
PTB18
PTB19
PTC0
—
—
—
—
C5
PTC1/
LLWU_P6/
RTC_CLKIN
45
B6
23
35
B7
PTC2
ND
Hi-Z
—
SS
N
N
Y
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
31
Freescale Semiconductor, Inc.
Pinouts
46
B5
24
36
C8
PTC3/
HD
Hi-Z
—
FS
N
N
Y
LLWU_P7
47
48
49
—
—
—
—
25
—
—
37
E3
E4
B8
VSS
VDD
—
—
—
—
—
—
—
—
—
—
—
N
—
—
N
—
—
Y
A6
PTC4/
HD
Hi-Z
FS
LLWU_P8
50
51
A5
B4
26
27
38
39
A8
A7
PTC5/
LLWU_P9
ND
ND
Hi-Z
Hi-Z
—
—
FS
FS
N
N
N
N
Y
Y
PTC6/
LLWU_P10
52
53
54
55
56
57
58
59
60
61
A4
—
—
—
—
—
—
—
—
A3
28
—
—
—
—
—
—
—
—
29
40
—
—
—
—
41
42
43
44
45
B6
A6
B5
B4
A5
C3
A4
C2
B3
A3
PTC7
PTC8
PTC9
PTC10
PTC11
PTD0
PTD1
PTD2
PTD3
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
FS
SS
SS
SS
SS
FS
FS
FS
FS
FS
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
PTD4/
LLWU_P14
62
63
B3
B2
30
31
46
47
C1
B2
PTD5
ND
HD
Hi-Z
Hi-Z
—
—
FS
FS
N
N
N
N
Y
Y
PTD6/
LLWU_P15
64
A2
32
48
A2
PTD7
HD
Hi-Z
—
FS
N
N
Y
Properties
Abbreviation
Descriptions
Normal drive
High drive
Driver strength
ND
HD
Default status after POR
Hi-Z
High impendence
Table continues on the next page...
32
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Freescale Semiconductor, Inc.
Pinouts
Properties
Abbreviation
Descriptions
High level
Low level
Pullup
H
L
Pullup/ pulldown setting
after POR
PD
PU
FS
SS
N
Pulldown
Fast slew rate
Slow slew rate
Disabled
Slew rate after POR
Passive Pin Filter after
POR
Y
Enabled
Open drain
N
Disabled1
Enabled2
Yes
Y
Pin interrupt
Y
1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or
LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain
configurable.
2. PTA20 is a true open drain pin that must never be pulled above VDD.
4.3 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the module's chapter. They also briefly describe the signal function and direction.
4.3.1 Core modules
Table 9. SWD signal descriptions
Chip signal name
Module signal
name
Description
I/O
SWD_DIO
SWD_DIO
SWD_CLK
Serial Wire Debug Data Input/Output
Input /
Output
The SWD_DIO pin is used by an external debug tool for
communication and device control. This pin is pulled up
internally.
SWD_CLK
Serial Wire Clock
Input
This pin is the clock for debug logic when in the Serial Wire
Debug mode. This pin is pulled down internally.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
33
Freescale Semiconductor, Inc.
Pinouts
4.3.2 System modules
Table 10. System signal descriptions
Chip signal name
Module signal
name
Description
I/O
NMI
—
Non-maskable interrupt
I
NOTE: Driving the NMI signal low forces a non-maskable
interrupt, if the NMI function is selected on the
corresponding pin.
RESET
VDD
—
—
—
Reset bidirectional signal
MCU power
I/O
I
I
VSS
MCU ground
Table 11. LLWU signal descriptions
Chip signal name
Module signal
Description
I/O
name
LLWU_Pn
LLWU_Pn
Wakeup inputs (n = 5, 6, 7, 8, 9, 10, 14, 15)
I
4.3.3 Clock modules
Table 12. OSC signal descriptions
Chip signal name
Module signal
Description
I/O
name
EXTAL
XTAL
EXTAL0
XTAL0
External clock/Oscillator input
Oscillator output
I
O
4.3.4 Analog
This table presents the signal descriptions of the ADC0 module.
Table 13. ADC0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
ADC0_DPn
ADC0_DMn
ADC0_SEn
VREFH
DADP3–DADP0
Differential Analog Channel Inputs
I
I
I
I
DADM3–DADM0 Differential Analog Channel Inputs
ADn
Single-Ended Analog Channel Inputs
Voltage Reference Select High
VREFSH
Table continues on the next page...
34
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Pinouts
I/O
Table 13. ADC0 signal descriptions (continued)
Chip signal name
Module signal
name
Description
VREFL
VDDA
VREFSL
VDDA
Voltage Reference Select Low
Analog Power Supply
Analog Ground
I
I
I
I
VSSA
VSSA
EXTRG_IN
ADHWT
Hardware trigger
This table presents the signal descriptions of the CMP0 module.
Table 14. CMP0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
CMP0_IN[5:0]
CMP0_OUT
IN[5:0]
CMPO
Analog voltage inputs
Comparator output
I
O
Table 15. VREF signal descriptions
Chip signal name
Module signal
Description
I/O
name
VREF_OUT
VREF_OUT
Internally-generated voltage reference output
O
4.3.5 Timer Modules
Table 16. TPM0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
TPM0_CH[5:0]
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
35
Freescale Semiconductor, Inc.
Pinouts
Table 17. TPM1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM1_CH[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM_CHn
TPM channel (n = 1 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Table 18. TPM2 signal descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM2_CH[1:0]
TPM_CHn
TPM channel (n = 1 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Table 19. LPTMR0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPTMR0_ALT[3:1]
LPTMR0_ALTn
Pulse Counter Input pin
I
Table 20. RTC signal descriptions
Chip signal name
Module signal
Description
I/O
name
RTC_CLKOUT1
RTC_CLKOUT
1 Hz square-wave output or OSCERCLK
O
1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]
4.3.6 Communication interfaces
Table 21. SPI0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
SPI0_MISO
MISO
Master Data In, Slave Data Out
I/O
Table continues on the next page...
36
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Pinouts
I/O
Table 21. SPI0 signal descriptions (continued)
Chip signal name
Module signal
name
Description
SPI0_MOSI
SPI0_SCLK
SPI0_PCS0
MOSI
SPSCK
SS
Master Data Out, Slave Data In
SPI Serial Clock
I/O
I/O
I/O
Slave Select
Table 22. SPI1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
MISO
MOSI
SPSCK
SS
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_PCS0
Master Data In, Slave Data Out
Master Data Out, Slave Data In
SPI Serial Clock
I/O
I/O
I/O
I/O
Slave Select
Table 23. I2C0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
I2C0_SCL
I2C0_SDA
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
SDA
Table 24. I2C1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
I2C1_SCL
I2C1_SDA
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
SDA
Table 25. LPUART0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART0_TX
LPUART0_RX
TxD
Transmit data
Receive data
I/O
I
RxD
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Pinouts
Table 26. LPUART1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART1_TX
LPUART1_RX
TxD
Transmit data
Receive data
I/O
I
RxD
Table 27. UART2 signal descriptions
Chip signal name
Module signal
Description
I/O
name
UART2_TX
UART2_RX
TxD
Transmit data
Receive data
O
I
RxD
Table 28. FlexIO signal descriptions
Chip signal name
Module signal name
Description
I/O
FXIO0_Dx
FXIO_Dn (n=0...7)
Bidirectional FlexIO Shifter
and Timer pin inputs/outputs
I/O
4.3.7 Human-machine interfaces (HMI)
Table 29. GPIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[31:0]
PTB[31:0]
PTC[11:0]
PTD[7:0]
PORTA31–PORTA0 General-purpose input/output
PORTB31–PORTB0 General-purpose input/output
PORTC11–PORTC0 General-purpose input/output
PORTD7–PORTD0 General-purpose input/output
PORTE31–PORTE0 General-purpose input/output
I/O
I/O
I/O
I/O
I/O
PTE[31:0]
4.4 KL17 Family Pinouts
The figure below shows the 32 QFN pinouts.
38
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
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Pinouts
PTC3/LLWU_P7
PTE0
PTE1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTE16
PTB1
PTE17
PTB0/LLWU_P5
PTA20
PTE18
PTE19
VDDA VREFH
VREFL VSSA
PTA19
18
17
PTA18
Figure 6. 32 QFN Pinout diagram (transparent top view)
The figure below shows the 48 QFN pinouts.
NOTE
The 48 QFN package for this product is not yet available.
However, it is included in Package Your Way program for
Kinetis MCUs. Visit freescale.com/KPYW for more details.
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Freescale Semiconductor, Inc.
Pinouts
PTC3/LLWU_P7
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTE16
3
PTC0
PTE17
4
PTB17
PTB16
PTB3
PTE18
5
PTE19
6
PTE20
7
PTE21
PTB2
8
VDDA
PTB1
9
VREFH VREFO
VREFL
PTB0/LLWU_P5
PTA20
10
11
12
VSSA
PTA19
Figure 7. 48 QFN Pinout diagram (transparent top view)
The figure below shows the 64 MAPBGA pinouts.
NOTE
The 64 MAPBGA package for this product is not yet
available. However, it is included in Package Your Way
program for Kinetis MCUs. Visit freescale.com/KPYW for
more details.
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Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Pinouts
1
2
3
4
5
6
7
8
PTC6/
LLWU_P10 LLWU_P9
PTC5/
PTD4/
LLWU_P14
A
B
C
D
E
F
PTE0
PTD7
PTD1
PTC11
PTC8
A
B
C
D
E
F
PTD6/
LLWU_P15
PTC4/
LLWU_P8
PTE1
PTD5
PTD3
PTD0
PTA0
VSS
PTC10
VSS
PTC9
NC
PTC7
PTC2
PTB19
PTB17
PTB2
PTC1/
LLWU_P6/
RTC_CLKIN
PTC3/
LLWU_P7
PTD2
PTE19
PTE18
PTE23
PTE22
PTE17
PTE16
PTE21
PTE20
PTA1
VDD
PTA3
PTA2
PTA5
PTA4
PTB18
PTB16
PTB1
PTC0
PTB3
PTB0/
LLWU_P5
VSSA
VREFL
VDDA
PTA20
PTA19
VREFH
VREFO
G
H
PTA13
VDD
G
H
PTE29
1
PTE30
2
PTE31
3
PTE24
4
PTE25
5
PTA12
6
VSS
7
PTA18
8
Figure 8. 64 MAPBGA Pinout diagram (transparent top view)
The figure below shows the 64 LQFP pinouts:
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Freescale Semiconductor, Inc.
Pinouts
PTE0
PTE1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
VDD
3
PTC3/LLWU_P7
VSS
4
PTC2
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
5
PTC1/LLWU_P6/RTC_CLKIN
6
PTC0
7
PTB19
PTB18
PTB17
PTB16
PTB3
8
9
10
11
12
13
14
15
16
PTB2
PTB1
VREFH VREFO
VREFL
PTB0/LLWU_P5
PTA20
PTA19
VSSA
Figure 9. 64 LQFP Pinout diagram (top view)
The figure below shows the 36 XFBGA pinouts:
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Kinetis KL17 Microcontroller, Rev. 5, 04/2015
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Pinouts
1
2
3
4
5
6
PTD4/
LLWU_P14
PTC4/
LLWU_P8
PTC5/
LLWU_P9
A
B
C
D
E
F
PTE0
PTD7
PTC7
A
B
C
D
E
F
PTD6/
LLWU_P15
PTC6/
PTC3/
LLWU_P10 LLWU_P7
PTE1
PTE17
PTE18
PTE22
PTD5
VDD
PTC2
PTB1
PTC1/
LLWU_P6/
RTC_CLKIN
PTE16
PTE19
PTE21
VSS
PTB0/
LLWU_P5
VDDA/
VREFH
VREFL/
VSSA
PTA20
PTA3
PTE20
PTA2
PTA19
VREF0/
PTE30
PTE23
1
PTA0
3
PTA1
4
PTA4
5
PTA18
6
2
Figure 10. 36 XFBGA Pinout diagram (transparent top view)
4.5 Package dimensions
The following figures show the dimensions of the package options for the devices
supported by this document.
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Freescale Semiconductor, Inc.
Pinouts
Figure 11. 64-pin LQFP package dimensions 1
44
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Freescale Semiconductor, Inc.
Pinouts
Figure 12. 64-pin LQFP package dimensions 2
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
45
Freescale Semiconductor, Inc.
Pinouts
Figure 13. 64-pin MAPBGA package dimension
46
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Pinouts
Figure 14. 48-pin QFN package dimension 1
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
47
Freescale Semiconductor, Inc.
Pinouts
Figure 15. 48-pin QFN package dimension 2
48
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Freescale Semiconductor, Inc.
Pinouts
Figure 16. 36-pin XFBGA package dimension
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Freescale Semiconductor, Inc.
Pinouts
Figure 17. 32-pin QFN package dimension 1
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Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Freescale Semiconductor, Inc.
Electrical characteristics
Figure 18. 32-pin QFN package dimension 2
5 Electrical characteristics
5.1 Ratings
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Electrical characteristics
5.1.1 Thermal handling ratings
Table 30. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1.2 Moisture handling ratings
Table 31. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1.3 ESD handling ratings
Table 32. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.1.4 Voltage and current absolute operating ratings
Table 33. Voltage and current absolute operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IDD
120
mA
Table continues on the next page...
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Electrical characteristics
Table 33. Voltage and current absolute operating ratings (continued)
Symbol
VIO
Description
Min.
–0.3
–25
Max.
VDD + 0.3
25
Unit
V
IO pin input voltage
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
5.2 General
5.2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 19. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
5.2.2 Nonswitching electrical specifications
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Electrical characteristics
5.2.2.1 Voltage and current operating requirements
Table 34. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain RAM
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
5.2.2.2 LVD and POR operating requirements
Table 35. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
—
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
1
VLVW1H
VLVW2H
VLVW3H
2.62
2.72
2.82
2.70
2.80
2.90
2.78
2.88
2.98
V
V
V
• Level 2 falling (LVWV = 01)
Table continues on the next page...
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Electrical characteristics
Table 35. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW4H
• Level 3 falling (LVWV = 10)
2.92
3.00
3.08
V
• Level 4 falling (LVWV = 11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
—
—
1
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
—
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
—
—
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.2.3 Voltage and current operating behaviors
Table 36. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH
Output high voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
0.5
V
V
IOLT
Output low current total for all ports
—
100
mA
Table continues on the next page...
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Electrical characteristics
Table 36. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
64
μA
μA
2
2
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
RPU
20
50
3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
5.2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx → RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 37. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the
—
—
300
μs
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
—
—
—
—
—
—
152
152
93
166
166
104
8
μs
μs
μs
μs
μs
μs
7.5
7.5
7.5
• VLPS → RUN
• STOP → RUN
8
8
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Freescale Semiconductor, Inc.
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Electrical characteristics
5.2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent the characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while(1) test is executed with flash cache enabled.
Table 38. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUNCO Running CoreMark in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
4.79
4.94
4.98
5.14
mA
mA
mA
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
2.73
2.9
2.87
3.05
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
2
2
—
—
5.45
5.6
5.67
5.82
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
3.41
3.56
3.55
3.70
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
2
2
—
—
2.37
2.52
2.49
2.65
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
7.05
7.2
7.33
7.49
• at 105 °C
Table continues on the next page...
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Electrical characteristics
Table 38. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0
—
3.39
3.57
3.53
3.71
mA
V
• at 25 °C
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0
—
2.36
2.53
2.48
2.66
mA
V
• at 25 °C
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
1.84
2
1.93
2.10
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0
V
4.98
5.16
5.18
5.37
• at 25 °C
• at 105 °C
IDD_VLPRCO Very-low-power run core mark in flash in
compute operation mode— 8 MHz LIRC mode,
4 MHz core/1 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
—
710
251
115
91
752.6
376.5
143.75
136.5
μA
μA
μA
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
—
34
51
μA
• at 25 °C
Table continues on the next page...
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Electrical characteristics
Table 38. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD
=
—
212
318
μA
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—8 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 4 MHz core / 1 MHz flash, VDD
=
—
—
302
392.6
2.12
μA
3.0 V
• at 25 °C
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C
1.81
mA
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C
—
—
1.27
156
1.46
mA
μA
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
193.2
IDD_VLPW Very-low-power wait mode current, core
—
—
63
32
100.8
48
μA
μA
disabled, 2 MHz system/ 0.5 MHz bus and
flash, all peripheral clocks disabled, VDD = 3.0
V
• at 25 °C
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0
V
• at 25 °C
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
• at 25 °C
—
—
1.68
1.05
2.05
1.26
mA
mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
• at 25 °C
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
158.1
171
175.81
180.24
228.64
300.06
• at 50 °C
• at 85 °C
• at 105 °C
203.8
251.7
μA
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Electrical characteristics
Table 38. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
2.34
5.04
3.80
8.03
• at 50 °C
• at 85 °C
• at 105 °C
20.48
42.34
31.97
65.78
μA
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
—
—
—
—
2.33
4.95
3.80
7.94
• at 50 °C
• at 85 °C
• at 105 °C
20.18
41.93
31.57
65.17
μA
μA
IDD_LLS Low-leakage stop mode current, all peripheral
disable, at 3.0 V
—
—
—
—
—
1.71
2.59
4.46
7.55
17.03
1.96
3.30
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
7.06
10.15
22.67
IDD_LLS Low-leakage stop mode current with RTC
current, at 3.0 V
3
μA
μA
μA
—
—
—
—
—
2.27
3.1
2.52
3.81
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
4.99
8.1
7.59
10.70
22.96
17.32
IDD_LLS Low-leakage stop mode current with RTC
current, at 1.8 V
3
—
—
—
—
—
2.1
2.89
4.65
7.61
16.38
2.35
3.60
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
7.25
10.21
22.02
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
—
—
—
—
—
1.43
2.06
3.51
5.91
13.36
1.58
2.52
5.20
7.60
17.08
• at 25 °C and below
• at 50 °C
• at 70 °C
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Electrical characteristics
Table 38. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with
RTC current, at 3.0 V
3
μA
—
—
—
—
—
1.83
2.47
3.96
6.44
13.84
1.98
2.93
5.65
8.13
17.56
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with
RTC current, at 1.8 V
3
μA
—
—
—
—
—
1.68
2.27
3.66
5.97
12.92
1.83
2.73
5.35
7.66
16.64
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
—
—
—
—
—
0.84
1.19
2.03
3.54
8.53
1.06
1.33
2.62
4.13
9.98
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
μA
μA
μA
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
3
—
—
—
—
—
1.26
1.61
2.5
1.48
1.75
3.09
4.66
10.45
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
4.07
9
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
3
—
—
—
—
—
1.08
1.42
2.21
3.59
8.02
1.30
1.56
2.80
4.18
9.47
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
Table continues on the next page...
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Electrical characteristics
Table 38. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled
—
—
—
—
262
593
360
725
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• at 25 °C and below
1430
2930
7930
2014
3514
9895
nA
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled
4
—
—
—
—
87
185
549
(SMC_STOPCTRL[PORPO] = 1) at 3 V
• at 25 °C and below
417
1230
2720
7780
1230
3304
9745
nA
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
4. No brownout
Table 39. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
77
77
77
77
77
77
µA
MCG_MC[LIRC_DIV2]=000b.
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
25
25
25
25
25
25
µA
µA
MCG_MC[LIRC_DIV2]=000b.
IEREFSTEN4MHz
[C: ] External 4 MHz crystal clock adder. 206
Measured by entering STOP or VLPS
mode with the crystal enabled.
224
230
238
245
253
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
440
490
540
560
570
580
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Electrical characteristics
Table 39. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
entering all modes with the crystal
440
490
540
560
570
580
enabled.
• VLLS1
• VLLS3
• LLS
490
510
510
490
560
560
540
560
560
560
560
560
570
610
610
680
680
680
nA
• VLPS
• STOP
ILPTMR
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
200
nA
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
16
16
16
16
16
16
Includes 6-bit DAC power consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
430
500
500
530
530
760
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
96
31
96
31
96
31
96
31
96
31
96
31
µA
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
• IRC8M (8 MHz internal reference
clock)
µA
• IRC2M (2 MHz internal reference
clock)
130
130
130
130
130
130
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Electrical characteristics
Table 39. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
40
40
40
40
40
40
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx or VLLSx
mode.
45
45
45
45
45
45
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
320
320
320
320
320
320
5.2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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Electrical characteristics
Figure 20. Run mode supply current vs. core frequency
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Electrical characteristics
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Electrical characteristics
Figure 21. VLPR mode current vs. core frequency
5.2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following Freescale applications notes, available on freescale.com for
advice and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
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Electrical characteristics
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
• KL-QRUG (Kinetis L-series Quick Reference).
5.2.2.7 Capacitance attributes
Table 40. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
5.2.3 Switching specifications
5.2.3.1 Device clock specifications
Table 41. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
LPTMR clock2
1
24
16
16
16
External reference clock
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
fTPM
TPM asynchronous clock
—
—
8
8
MHz
MHz
fUART0
UART0 asynchronous clock
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
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Electrical characteristics
5.2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 42. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
5.2.4 Thermal specifications
5.2.4.1 Thermal operating requirements
Table 43. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
5.2.4.2 Thermal attributes
NOTE
The 48 QFN and 64 MAPBGA packages for this product are
not yet available. However, it is included in Package Your
Way program for Kinetis MCUs. Visit freescale.com/
KPYW for more details.
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Electrical characteristics
Table 44. Thermal attributes
Board type
Single-layer (1S)
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
—
Symbol
RθJA
RθJA
Description
32 QFN
101
33
36
XFBGA
64 LQFP
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1, 2, 3
1, 2, 3,4
1, 4, 5
1, 4, 5
6
Thermal resistance, junction to
ambient (natural convection)
81.5
54.7
71.3
50.0
58.0
45.3
1.2
71
53
60
47
35
21
5
Thermal resistance, junction to
ambient (natural convection)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
84
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
28
RθJB
RθJC
ΨJT
Thermal resistance, junction to
board
13
—
Thermal resistance, junction to
case
1.7
3
7
—
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
8
—
ΨJB
Thermal characterization
-
44.5
-
°C/W
9
parameter, junction to package
bottom (natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
4. Per JEDEC JESD51-6 with the board horizontal.
5. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s
or 2s2p board, respectively.
6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
7. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
8. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
9. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
5.3 Peripheral operating requirements and behaviors
5.3.1 Core modules
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Electrical characteristics
5.3.1.1 SWD electricals
Table 45. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 22. Serial wire clock input timing
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Electrical characteristics
SWD_CLK
J9
J10
Input data valid
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J11
Output data valid
J12
J11
Output data valid
Figure 23. Serial wire data timing
5.3.2 System modules
There are no specifications necessary for the device's system modules.
5.3.3 Clock modules
5.3.3.1 MCG-Lite specifications
Table 46. IRC48M specifications
Symbol
IDD48M
firc48m
Description
Min.
—
Typ.
400
48
Max.
500
—
Unit
μA
Notes
Supply current
Internal reference frequency
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at low
voltage (VDD=1.71V-1.89V) over temperature
—
0.5
1.5
%firc48m
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
1
2
high voltage (VDD=1.89V-3.6V) over temperature
—
—
—
0.5
35
2
1.0
150
3
%firc48m
ps
Jcyc_irc48m Period Jitter (RMS)
tirc48mst
Startup time
μs
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Electrical characteristics
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean 3 sigma).
2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable
the clock by one of the following settings:
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
Table 47. IRC8M/2M specification
Symbol
IDD_2M
Description
Supply current in 2 MHz mode
Supply current in 8 MHz mode
Output frequency
Min.
—
Typ.
14
30
2
Max.
17
Unit
µA
Notes
—
IDD_8M
—
35
µA
—
fIRC_2M
fIRC_8M
fIRC_T_2M
fIRC_T_8M
Tsu_2M
—
—
MHz
MHz
%fIRC
%fIRC
µs
—
Output frequency
—
8
—
—
Output frequency range (trimmed)
Output frequency range (trimmed)
Startup time
—
—
—
—
—
3
—
—
3
—
—
12.5
12.5
—
Tsu_8M
Startup time
—
µs
—
5.3.3.2 Oscillator electrical specifications
5.3.3.2.1 Oscillator DC electrical specifications
Table 48. Oscillator DC electrical specifications
Symbol Description
VDD Supply voltage
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
IDDOSC Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Table continues on the next page...
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Electrical characteristics
Table 48. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
—
Typ.
—
Max.
—
Unit
Notes
2, 3
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
2, 3
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
MΩ
MΩ
MΩ
kΩ
2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-
power mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
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Electrical characteristics
5.3.3.2.2 Oscillator frequency specifications
Table 49. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
32
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
48
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
5.3.4 Memories and memory interfaces
5.3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
5.3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
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Table 50. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
5.3.4.1.2 Flash timing specifications — commands
Table 51. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
45
μs
—
30
μs
1
65
14
—
145
114
0.9
25
μs
—
2
tersscr
trd1all
ms
ms
μs
1
trdonce
—
1
tpgmonce Program Once execution time
65
70
—
—
μs
—
2
tersall
tvfykey
tersallu
Erase All Blocks execution time
575
30
ms
μs
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
1
70
575
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.3.4.1.3 Flash high voltage current behaviors
Table 52. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
5.3.4.1.4 Reliability specifications
Table 53. NVM reliability specifications
Symbol Description
Min.
Program Flash
Table continues on the next page...
Typ.1
Max.
Unit
Notes
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Electrical characteristics
Table 53. NVM reliability specifications (continued)
Symbol Description
Min.
5
Typ.1
Max.
—
Unit
years
years
cycles
Notes
—
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
50
20
100
50 K
—
—
10 K
—
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.3.6 Analog
5.3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
5.3.6.1.1 16-bit ADC operating conditions
Table 54. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
-100
0
+100
+100
mV
mV
V
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
-100
0
2
VADIN
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
—
31/32 ×
VREFH
—
VREFL
—
VREFH
CADIN
Input
—
—
8
4
10
5
pF
—
capacitance
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
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Electrical characteristics
Table 54. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
18.0
MHz
4
ADC conversion 16-bit mode
clock frequency
2.0
—
—
12.0
MHz
ksps
4
5
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
818.330
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
rate
No ADC hardware averaging
37.037
—
461.467
ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 24. ADC input impedance equivalency diagram
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Electrical characteristics
5.3.6.1.2 16-bit ADC electrical characteristics
Table 55. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
2.4
clock source
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total
unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
2
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.9
0.4
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN
VDDA
=
5
Quantization
error
0.5
ENOB Effective
number of bits
16-bit differential mode
• Avg = 32
6
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise See ENOB
plus distortion
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic 16-bit differential mode
7
distortion
—
—
–94
–85
—
—
dB
dB
• Avg = 32
16-bit single-ended mode
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Electrical characteristics
Table 55. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
• Avg = 32
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
7
82
78
95
90
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
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Electrical characteristics
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 25. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 26. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
5.3.6.1.3 Voltage reference electrical specifications
Table 56. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
3.6
V
Table continues on the next page...
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Electrical characteristics
Table 56. VREF full-range operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
Table 57 is tested under the condition of setting VREF_TRM[CHOPEN],
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
Table 57. VREF full-range (-40 – 105°C) operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
Vstep
Ibg
1.1584
1.193
—
—
—
1.2376
1.197
—
V
1
1
V
0.5
—
mV
µA
mA
µV
µs
1
Bandgap only current
—
80
1
Ihp
High-power buffer current
—
—
1
1
ΔVLOAD Load regulation
Tstup Buffer startup time
Tchop_osc_st Internal bandgap start-up delay with chop
—
200
—
—
1, 2
—
100
35
—
—
ms
—
1
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 58. VREF limited-range (0 – 50°C) operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
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Electrical characteristics
5.3.6.2 CMP and 6-bit DAC electrical specifications
Table 59. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Electrical characteristics
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 28. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
5.4 Timers
See General switching specifications.
5.5 Communication interfaces
5.5.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
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Electrical characteristics
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 60. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 61. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
96
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
52
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
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Electrical characteristics
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 29. SPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 30. SPI master mode timing (CPHA = 1)
Table 62. SPI slave mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
1
2
3
fop
Frequency of operation
0
4 x tperiph
1
tSPSCK
tLead
SPSCK period
ns
2
Enable lead time
—
tperiph
—
Table continues on the next page...
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Electrical characteristics
Table 62. SPI slave mode timing on slew rate disabled pads (continued)
Num.
4
Symbol Description
tLag Enable lag time
tWSPSCK Clock (SPSCK) high or low time
Min.
Max.
—
Unit
tperiph
ns
Note
—
—
—
—
3
1
5
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Table 63. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Note
fop
tSPSCK
tLead
tLag
Frequency of operation
0
Hz
ns
1
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
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Electrical characteristics
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 31. SPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 32. SPI slave mode timing (CPHA = 1)
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Electrical characteristics
5.5.2 Inter-Integrated Circuit Interface (I2C) timing
Table 64. I2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
4001
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
02
2505
—
3.453
—
04
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
0.92
—
µs
ns
ns
ns
µs
µs
Data set-up time
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
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Design considerations
Table 65. I 2C 1Mbit/s timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tLOW
tHIGH
0.5
0.26
—
—
µs
µs
µs
µs
ns
ns
ns
µs
µs
tSU; STA
tHD; DAT
tSU; DAT
tr
0.26
—
0
—
50
—
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
20 +0.1Cb
120
120
—
2
tf
20 +0.1Cb
0.26
tSU; STO
tBUF
Bus free time between STOP and START
condition
0.5
—
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins
across the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 33. Timing definition for devices on the I2C bus
5.5.3 UART
See General switching specifications.
6 Design considerations
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Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital circuits
between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane
directly under LQFP packages; and solder the exposed pad (EP) to ground directly
under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential
segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An
option is to use the internal reference voltage (output 1.2 V typically) as the ADC
reference.
NOTE
The internal reference voltage output (VREFO) is bonded to
the VREFH pin on some packages and to PTE30 on other
packages. When the VREFO output is used, a 0.1 μF capacitor
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Design considerations
is required as a filter. Do not connect any other supply
voltage to the pin that has VREFO activated.
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
1
2
Input signal
ADCx
R
C
Figure 34. RC circuit for ADC input
High voltage measurement circuits require voltage division, current limiting, and
over-voltage protection as shown the following figure. The voltage divider formed by
R1 – R4 must yield a voltage less than or equal to VREFH. The current must be
limited to less than the injection current limit. Since the ADC pins do not have diodes
to VDD, external clamp diodes must be included to protect against transient over-
voltages.
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 35. High voltage measurement with an ADC input
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Design considerations
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially the
RESET_b pin.
• RESET_b pin
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
external RC circuit is recommended to filter noise as shown in the following figure.
The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended
capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to
reject spurious noise.
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 36. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength. The
supervisor chip must have an active high, open-drain output.
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Design considerations
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 37. Reset signal connection to external reset chip
• NMI pin
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low
level on this pin will trigger non-maskable interrupt. When this pin is enabled as
the NMI function, an external pull-up resistor (10 kΩ) as shown in the following
figure is recommended for robustness.
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
VDD
MCU
10k
NMI_b
Figure 38. NMI pin biasing
• Debug interface
This MCU uses the standard ARM SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required
(SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down),
external 10 kΩ pull resistors are recommended for system robustness. The
RESET_b pin recommendations mentioned above must also be considered.
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Design considerations
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 39. SWD debug interface
• Low leakage stop mode wakeup
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the
low leakage stop modes (LLS/VLLSx). See KL17 Signal Multiplexing and Pin
Assignments for pin selection.
• Unused pin
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators. An
external feedback is required when using high gain (HGO=1) mode.
The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or
resonator frequency is below 2MHz. Otherwise, the low power oscillator (HGO=0)
must not have any series resistance; and the high frequency, high gain oscillator with a
frequency above 2MHz does not require any series resistance.
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode.
Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for the
crystal. Typically, values of 10pf to 16pF are sufficient for 32.768kHz crystals that have
a 12.5pF CL specification. The internal load capacitor selection must not be used for
high frequency crystals and resonators.
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Design considerations
Table 66. External crystal/resonator connections
Oscillator mode
Low frequency (32.768kHz), low power
Low frequency (32.768kHz), high gain
High frequency (1-32MHz), low power
High frequency (1-32MHz), high gain
Oscillator mode
Diagram 1
Diagram 2, Diagram 4
Diagram 3
Diagram 4
OSCILLATOR
EXTAL
XTAL
1
2
CRYSTAL
Figure 40. Crystal connection – Diagram 1
OSCILLATOR
EXTAL
XTAL
1
2
RF
RS
1
2
CRYSTAL
Figure 41. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 42. Crystal connection – Diagram 3
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Design considerations
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 43. Crystal connection – Diagram 4
6.2 Software considerations
All Kinetis MCUs are supported by comprehensive Freescale and third-party hardware
and software enablement solutions, which can reduce development costs and time to
market. Featured software and tools are listed below. Visit http://www.freescale.com/
kinetis/sw for more information and supporting collateral.
Evaluation and Prototyping Hardware
• Freescale Freedom Development Platform: http://www.freescale.com/freedom
• Tower System Development Platform: http://www.freescale.com/tower
IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.freescale.com/kds
• Partner IDEs: http://www.freescale.com/kide
Development Tools
• PEG Graphics Software: http://www.freescale.com/peg
• Processor Expert Software and Embedded Components: http://www.freescale.com/
processorexpert )
Run-time Software
• Kinetis SDK: http://www.freescale.com/ksdk
• Kinetis Bootloader: http://www.freescale.com/kboot
• ARM mbed Development Platform: http://www.freescale.com/mbed
• MQX RTOS: http://www.freescale.com/mqx
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Part identification
For all other partner-developed software and tools, visit http://www.freescale.com/
partners.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 67. Part number fields description
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis family
Key attribute
• KL17
• Z = Cortex-M0+
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)1
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)1
• DA = 36 XFBGA (3.5 mm x 3.5 mm)
CC
Maximum CPU frequency (MHz)
• 4 = 48 MHz
Table continues on the next page...
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Revision history
Table 67. Part number fields description (continued)
Field
Description
Values
• R = Tape and reel
• (Blank) = Trays
N
Packaging type
1. This package for this product is not yet available. However, it is included in Package Your Way program for Kinetis
MCUs. Visit freescale.com/KPYW for more details.
7.4 Example
This is an example part number:
MKL17Z64VLH4
8 Revision history
The following table provides a revision history for this document.
Table 68. Revision history
Rev. No.
Date
Substantial Changes
4
28 January/ Initial public release
2015
• Updated the features and completed the ordering information.
• Updated Table 9 - Power consumption operating behaviors with Max. values.
• Added a note before Table 9.
• Updated Table 17 - IRC48M specifications.
• Updated Table 28. VREF full-range (-40 – 105 °C) operating behaviors with Min.,
Max., and Typical values.
• Added Table 36 - I2C 1Mbit/s timing.
4.1
5
2 February/
2015
• Moved the ordering information out of the front page to be a separate chapter.
• Added Module signal description table and Package dimension sections.
21 April/2015
• 32-pin QFN package is now standard part, added Marking information and thermal
attributes of this package
• Added Overview chapter
• Added Memory map chapter
• Added Pin properties
• Added a note to the trd1all in Flash timing specifications — commands
• Added a note to the Maximum of fSCL in the fast mode in Inter-Integrated Circuit
Interface (I2C) timing
• Added a footnote to the Δfirc48m_ol_hv in MCG-Lite specifications
• Added Design considerations chapter
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Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
How to Reach Us:
Home Page:
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freescale.com/support
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
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©2014-2015 Freescale Semiconductor, Inc.
Document Number KL17P64M48SF2
Revision 5, 04/2015
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