MKL33Z128VMP4_技术文档

Freescale Semiconductor, Inc.

Data Sheet: Technical Data

KL33P64M48SF6

Rev. 5, 08/2015

Kinetis KL33 Microcontroller

MKL33Z256Vxx4(R)

MKL33Z128Vxx4(R)

48 MHz ARM® Cortex®-M0+ and 128/256 KB Flash

The KL33 series is optimized for cost-sensitive and battery-

powered applications requiring low-power segment LCD. The

product offers:

• Low power segment LCD up to 28x8 or 32x4

• Embedded ROM with boot loader for flexible program

upgrade

• High accuracy internal voltage and clock reference

• FlexIO to support any standard and customized serial

peripheral emulation

64 LQFP

10x10 mm P 0.5 mm

64 BGA

5x5 mm P 0.5 mm

• Down to 54uA/MHz in very low power run mode and

1.96uA in deep sleep mode (RAM + RTC retained)

Core Processor

Peripherals

• ARM^®Cortex^®-M0+ core up to 48 MHz

• Segment LCD supporting up to 28x8 or 32x4

segments

Memories

• One UART module supporting ISO7816, operating

up to 1.5 Mbit/s

• Two low-power UART modules supporting

asynchronous operation in low-power modes

• Two I2C modules and I2C0 supporting up to 1

Mbit/s

• Two 16-bit SPI modules supporting up to 24 Mbit/s

• One FlexIO module supporting emulation of

additional UART, IrDA, SPI, I2C, I2S, PWM and

other serial modules, etc.

• 128/256 KB program flash memory

• 16/32 KB SRAM

• 16 KB ROM with build-in bootloader

• 32-byte backup register

System

• 4-channel asynchronous DMA controller

• Watchdog

• Low-leakage wakeup unit

• Two-pin Serial Wire Debug (SWD) programming and

debug interface

• Micro Trace Buffer

• Bit manipulation engine

• Interrupt controller

• One serial audio interface I2S

• One 16-bit 818 ksps ADC module with high

accuracy internal voltage reference (Vref) and up to

16 channels

• High-speed analog comparator containing a 6-bit

DAC for programmable reference input

• One 12-bit DAC

Clocks

• 48MHz high accuracy (up to 0.5%) internal reference

clock

• 1.2 V internal voltage reference

• 8MHz/2MHz high accuracy (up to 3%) internal

reference clock

• 1KHz reference clock active under all low-power

modes (except VLLS0)

Timers

• One 6-channel Timer/PWM module

• Two 2-channel Timer/PWM modules

• One low-power timer

• 32–40KHz and 3–32MHz crystal oscillator

• Periodic interrupt timer

• Real time clock

Freescale reserves the right to change the detail specifications as may be required to

Operating Characteristics

Security and Integrity

• Voltage range: 1.71 to 3.6 V

• Flash write voltage range: 1.71 to 3.6 V

• Temperature range: –40 to 105 °C

• 80-bit unique identification number per chip

• Advanced flash security

I/O

Packages

• Up to 54 general-purpose input/output pins (GPIO)

and 6 high-drive pad

• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm

thickness

• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm

thickness

Low Power

• Down to 54uA/MHz in very low power run mode

• Down to 1.96uA in VLLS3 mode (RAM + RTC

retained)

• Six flexible static modes

Ordering Information

Product

Part number Marking (Line1/

Line2)

Memory

Package

IO and ADC channel

Flash

SRAM

(KB)

Package

GPIOs

ADC

(KB)

count

(INT/HD)¹channels

(SE/DP)

MKL33Z128VLH4 MKL33Z128V//LH4

MKL33Z256VLH4 MKL33Z256V//LH4

128

256

128

256

16

32

16

32

64

LQFP

54

31/6

20/4

MKL33Z128VMP4

MKL33Z256VMP4

M33P7V

M33P8V

MAPBGA

1. INT: interrupt pin numbers; HD: high drive pin numbers

Related Resources

Type

Selector

Guide

Description

Resource

The Freescale Solution Advisor is a web-based tool that features

interactive application wizards and a dynamic product selector.

Solution Advisor

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

KLX3PB¹

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

KL33P64M48SF6RM¹

This document.

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

Chip Errata

The chip mask set Errata provides additional or corrective information for KINETIS_L_1N71K¹

a particular device mask set.

Package

drawing

Package dimensions are provided in package drawings.

64-LQFP: 98ASS23234W¹64

MAPBGA: 98ASA00420D¹

1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.

2

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Freescale Semiconductor, Inc.

Table of Contents

1 Ratings..................................................................................4

3.6.1 ADC electrical specifications..............................30

3.6.2 Voltage reference electrical specifications.........35

3.6.3 CMP and 6-bit DAC electrical specifications......36

3.6.4 12-bit DAC electrical characteristics.................. 38

3.7 Timers............................................................................41

3.8 Communication interfaces............................................. 41

3.8.1 SPI switching specifications...............................41

3.8.2 I2C..................................................................... 46

3.8.3 UART................................................................. 48

3.8.4 I2S/SAI switching specifications........................ 48

3.9 Human-machine interfaces (HMI)..................................52

3.9.1 LCD electrical characteristics.............................52

4 Dimensions........................................................................... 54

4.1 Obtaining package dimensions......................................54

5 Pinouts and Packaging......................................................... 54

5.1 KL33 Signal Multiplexing and Pin Assignments.............54

5.2 KL33 Family Pinouts......................................................57

6 Ordering parts....................................................................... 59

6.1 Determining valid orderable parts..................................59

7 Part identification...................................................................59

7.1 Description.....................................................................59

7.2 Format........................................................................... 60

7.3 Fields............................................................................. 60

7.4 Example.........................................................................60

8 Terminology and guidelines.................................................. 61

8.1 Definitions...................................................................... 61

8.2 Examples....................................................................... 61

8.3 Typical-value conditions................................................ 62

8.4 Relationship between ratings and operating

1.1 Thermal handling ratings............................................... 4

1.2 Moisture handling ratings...............................................4

1.3 ESD handling ratings..................................................... 4

1.4 Voltage and current operating ratings............................4

2 General................................................................................. 5

2.1 AC electrical characteristics...........................................5

2.2 Nonswitching electrical specifications............................5

2.2.1 Voltage and current operating requirements......6

2.2.2 LVD and POR operating requirements.............. 6

2.2.3 Voltage and current operating behaviors...........7

2.2.4 Power mode transition operating behaviors.......8

2.2.5 Power consumption operating behaviors...........9

2.2.6 EMC radiated emissions operating behaviors... 19

2.2.7 Designing with radiated emissions in mind........20

2.2.8 Capacitance attributes....................................... 20

2.3 Switching specifications.................................................20

2.3.1 Device clock specifications................................ 20

2.3.2 General switching specifications........................21

2.4 Thermal specifications................................................... 21

2.4.1 Thermal operating requirements........................21

2.4.2 Thermal attributes..............................................22

3 Peripheral operating requirements and behaviors................ 22

3.1 Core modules................................................................ 22

3.1.1 SWD electricals .................................................23

3.2 System modules............................................................ 24

3.3 Clock modules............................................................... 24

3.3.1 MCG-Lite specifications.....................................24

3.3.2 Oscillator electrical specifications...................... 26

3.4 Memories and memory interfaces................................. 28

3.4.1 Flash electrical specifications............................ 28

3.5 Security and integrity modules.......................................30

3.6 Analog............................................................................30

requirements..................................................................62

8.5 Guidelines for ratings and operating requirements........63

9 Revision History.................................................................... 63

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Freescale Semiconductor, Inc.

Ratings

1 Ratings

1.1 Thermal handling ratings

Table 1. Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 2. Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Table 3. ESD handling ratings

Symbol

V_HBM

Description

Min.

–2000

–500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

I_LAT

Latch-up current at ambient temperature of 105 °C

–100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Freescale Semiconductor, Inc.

General

1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings

Symbol

V_DD

I_DD

Description

Min.

–0.3

—

Max.

3.8

Unit

Digital supply voltage

Digital supply current

IO pin input voltage

V

mA

V

120

V_IO

–0.3

–25

V_DD+ 0.3

25

I_D

Instantaneous maximum current single pin limit (applies to

all port pins)

mA

V_DDA

Analog supply voltage

V_DD– 0.3

V_DD+ 0.3

V

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 1. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assume that the

output pins have the following characteristics.

• C_L=30 pF loads

• Slew rate disabled

• Normal drive strength

2.2 Nonswitching electrical specifications

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Freescale Semiconductor, Inc.

General

2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.71

–0.1

Max.

3.6

Unit

V

Notes

Supply voltage

V_DDA

Analog supply voltage

3.6

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

0.1

V

0.1

V

V_IH

Input high voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICIO

Input hysteresis

0.06 × V_DD

-3

—

V

IO pin negative DC injection current — single pin

• V_IN< V_SS-0.3V

1

mA

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16

contiguous pins

-25

—

mA

• Negative current injection

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V

2

V_DDvoltage required to retain RAM

1. All I/O pins are internally clamped to V_SSthrough a ESD protection diode. There is no diode connection to V_DD. If V_IN

greater than V_{IO_MIN}(= V_SS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If

this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting

resistor is calculated as R = (V_{IO_MIN}- V_IN)/|I_ICIO|.

2. Open drain outputs must be pulled to V_DD

.

2.2.2 LVD and POR operating requirements

Table 6. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

—

V_POR

Falling V_DDPOR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV = 01)

2.48

2.56

2.64

V

—

Low-voltage warning thresholds — high range

1

Table continues on the next page...

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Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Freescale Semiconductor, Inc.

General

Notes

Table 6. V_DDsupply LVD and POR operating requirements (continued)

Symbol Description

Min.

Typ.

Max.

Unit

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

• Level 1 falling (LVWV = 00)

2.62

2.70

2.78

V

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

2.72

2.82

2.92

2.80

2.90

3.00

2.88

2.98

3.08

V

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

60

—

mV

V

—

1

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV = 00)

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

—

1.80

1.90

2.00

2.10

40

1.86

1.96

2.06

2.16

—

V

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

V

• Level 4 falling (LVWV = 11)

V

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

mV

—

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

—

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — normal drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= –5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= –1.5 mA

1

V_DD– 0.5

—

V

V_OH

Output high voltage — high drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= –18 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= –6 mA

1

V_DD– 0.5

—

V

I_OHT

V_OL

Output high current total for all ports

—

100

mA

Output low voltage — normal drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 1.5 mA

1

—

0.5

V

V_OL

Output low voltage — high drive pad

—

0.5

V

Table continues on the next page...

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Freescale Semiconductor, Inc.

General

Table 7. Voltage and current operating behaviors (continued)

Symbol

Description

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 18 mA

Min.

Max.

Unit

Notes

—

0.5

V

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 6 mA

I_OLT

I_IN

Output low current total for all ports

—

100

1

mA

μA

Input leakage current (per pin) for full temperature

range

2

I_IN

Input leakage current (per pin) at 25 °C

—

0.025

64

μA

2

Input leakage current (total all pins) for full

temperature range

I_OZ

Hi-Z (off-state) leakage current (per pin)

Internal pullup resistors

—

1

μA

kΩ

R_PU

20

50

3

1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the

associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. Measured at V_DD= 3.6 V

3. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

2.2.4 Power mode transition operating behaviors

All specifications except t_PORand VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 48 MHz

• Bus and flash clock = 24 MHz

• HIRC clock mode

Table 8. Power mode transition operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_PORAfter a POR event, amount of time from the

—

300

μs

1

point V_DDreaches 1.8 V to execution of the first

instruction across the operating temperature

range of the chip.

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS3 → RUN

• LLS → RUN

—

152

93

166

104

8

μs

7.5

Table continues on the next page...

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Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Freescale Semiconductor, Inc.

General

Notes

Table 8. Power mode transition operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

• VLPS → RUN

—

7.5

8

μs

• STOP → RUN

—

7.5

μs

1. Normal boot (FTFA_FOPT[LPBOOT]=11)

2.2.5 Power consumption operating behaviors

The maximum values stated in the following table represent characterized results

equivalent to the mean plus three times the standard deviation (mean + 3 sigma).

NOTE

The while (1) test is executed with flash cache enabled.

Table 9. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_RUNCO}Running CoreMark in flash in compute operation

mode—48M HIRC mode, 48 MHz core / 24 MHz

flash, V_DD= 3.0 V

—

5.76

6.04

6.40

6.68

mA

• at 25 °C

• at 105 °C

I_{DD_RUNCO}Running While(1) loop in flash in compute

operation mode—48M HIRC mode, 48 MHz

core / 24 MHz flash, V_DD= 3.0 V

• at 25 °C

—

3.21

3.49

3.85

4.13

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

CoreMark in Flash all peripheral clock disable 48

MHz core/24 MHz flash, V_DD= 3.0 V

• at 25 °C

2

—

6.45

6.75

7.09

7.39

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

CoreMark in flash all peripheral clock disable, 24

MHz core/12 MHz flash, V_DD= 3.0 V

—

3.95

4.23

4.59

4.87

• at 25 °C

mA

• at 105 °C

Table continues on the next page...

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General

Table 9. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_RUN}Run mode current—48M HIRC mode, running

CoreMark in Flash all peripheral clock disable 12

MHz core/6 MHz flash, V_DD= 3.0 V

• at 25 °C

2

—

2.68

2.96

3.32

3.60

mA

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

CoreMark in Flash all peripheral clock enable 48

MHz core/24 MHz flash, V_DD= 3.0 V

• at 25 °C

2

—

8.08

8.39

8.72

9.03

mA

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

While(1) loop in flash all peripheral clock disable,

48 MHz core/24 MHz flash, V_DD= 3.0 V

• at 25 °C

—

3.90

4.21

4.54

4.85

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

While(1) loop in Flash all peripheral clock

disable, 24 MHz core/12 MHz flash, V_DD= 3.0 V

• at 25 °C

—

2.66

2.94

3.30

3.58

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, Running

While(1) loop in Flash all peripheral clock

disable, 12 MHz core/6 MHz flash, V_DD= 3.0 V

• at 25 °C

—

2.03

2.31

2.67

2.95

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, Running

While(1) loop in Flash all peripheral clock

enable, 48 MHz core/24 MHz flash, V_DD= 3.0 V

• at 25 °C

—

5.52

5.83

6.16

6.47

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

While(1) loop in SRAM all peripheral clock

disable, 48 MHz core/24 MHz flash, V_DD= 3.0 V

• at 25 °C

—

5.29

5.56

5.93

6.20

• at 105 °C

I_{DD_RUN}Run mode current—48M HIRC mode, running

While(1) loop in SRAM all peripheral clock

enable, 48 MHz core/24 MHz flash, V_DD= 3.0 V

• at 25 °C

—

6.91

7.19

7.55

7.91

• at 105 °C

Table continues on the next page...

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General

Notes

Table 9. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

826

405

154

108

39

Max.

907

486

235

189

120

Unit

μA

I_{DD_VLPRC}Very Low Power Run Core Mark in Flash in

Compute Operation mode: Core@4MHz, Flash

O

@1MHz, V_DD= 3.0 V

• at 25 °C

—

I_{DD_VLPRC}Very-low-power-run While(1) loop in SRAM in

compute operation mode— 8 MHz LIRC mode, 4

O

MHz core / 1 MHz flash, V_DD= 3.0 V

• at 25 °C

—

I_{DD_VLPRC}Very-low-power run While(1) loop in SRAM in

compute operation mode:—2 MHz LIRC mode, 2

O

MHz core / 0.5 MHz flash, V_DD= 3.0 V

• at 25 °C

—

I_{DD_VLPR}Very-low-power run mode current— 2 MHz LIRC

mode, While(1) loop in flash all peripheral clock

disable, 2 MHz core / 0.5 MHz flash, V_DD= 3.0 V

• at 25 °C

—

I_{DD_VLPR}Very-low-power run mode current— 2 MHz LIRC

mode, While(1) loop in flash all peripheral clock

disable, 125 kHz core / 31.25 kHz flash, V_DD

=

—

3.0 V

• at 25 °C

I_{DD_VLPR}Very-low-power run mode current— 8 MHz LIRC

mode, While(1) loop in flash all peripheral clock

disable, 4 MHz core / 1 MHz flash, V_DD= 3.0 V

• at 25 °C

—

249

337

416

330

418

497

μA

I_{DD_VLPR}Very-low-power run mode current— 8 MHz LIRC

mode, While(1) loop in flash all peripheral clock

enable, 4 MHz core / 1 MHz flash, V_DD= 3.0 V

• at 25 °C

I_{DD_VLPR}Very-low-power run mode current— 8 MHz LIRC

mode, While(1) loop in SRAM in all peripheral

clock disable, 4 MHz core / 1 MHz flash, V_DD

=

3.0 V

• at 25 °C

I_{DD_VLPR}Very-low-power run mode current— 8 MHz LIRC

mode, While(1) loop in SRAM all peripheral clock

enable, 4 MHz core / 1 MHz flash, V_DD= 3.0 V

• at 25 °C

—

494

166

575

247

μA

I_{DD_VLPR}Very-low-power run mode current—2 MHz LIRC

mode, While(1) loop in SRAM in all peripheral

clock disable, 2 MHz core / 0.5 MHz flash, V_DD

=

3.0 V

• at 25 °C

I_{DD_VLPR}Very-low-power run mode current—2 MHz LIRC

mode, While(1) loop in SRAM all peripheral clock

disable, 125 kHz core / 31.25 kHz flash, V_DD

=

—

50

131

μA

3.0 V

• at 25 °C

Table continues on the next page...

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Freescale Semiconductor, Inc.

General

Table 9. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLPR}Very-low-power run mode current—2 MHz LIRC

mode, While(1) loop in SRAM all peripheral clock

enable, 2 MHz core / 0.5 MHz flash, V_DD= 3.0 V

• at 25 °C

—

208

289

μA

I_{DD_WAIT}Wait mode current—core disabled, 48 MHz

system/24 MHz bus, flash disabled (flash doze

enabled), all peripheral clocks disabled,

—

1.81

1.89

mA

MCG_Lite under HIRC mode, V_DD= 3.0 V

I_{DD_WAIT}Wait mode current—core disabled, 24 MHz

system/12 MHz bus, flash disabled (flash doze

enabled), all peripheral clocks disabled,

—

1.22

172

1.39

182

mA

μA

MCG_Lite under HIRC mode, V_DD= 3.0 V

I_{DD_VLPW}Very-low-power wait mode current, core

disabled, 4 MHz system/ 1 MHz bus and flash,

all peripheral clocks disabled, V_DD= 3.0 V

I_{DD_VLPW}Very-low-power wait mode current, core

disabled, 2 MHz system/ 0.5 MHz bus and flash,

all peripheral clocks disabled, V_DD= 3.0 V

—

69

36

76

40

μA

I_{DD_VLPW}Very-low-power wait mode current, core

disabled, 125 kHz system/ 31.25 kHz bus and

flash, all peripheral clocks disabled, V_DD= 3.0 V

I_{DD_PSTOP2}Partial Stop 2, core and system clock disabled,

12 MHz bus and flash, V_DD= 3.0 V

—

1.81

1.00

2.06

1.25

mA

I_{DD_PSTOP2}Partial Stop 2, core and system clock disabled,

flash doze enabled, 12 MHz bus, V_DD= 3.0 V

I_{DD_STOP}Stop mode current at 3.0 V

• at 25 °C and below

—

161.93

181.45

236.29

390.33

171.82

191.96

271.17

465.58

• at 50 °C

• at 85 °C

• at 105 °C

μA

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

• at 25 °C and below

—

3.31

10.43

34.14

104.38

5.14

17.68

61.06

164.44

• at 50 °C

• at 85 °C

• at 105 °C

I_{DD_VLPS}Very-low-power stop mode current at 1.8 V

• at 25 °C and below

—

3.21

10.26

33.49

5.22

17.62

60.19

• at 50 °C

Table continues on the next page...

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General

Notes

Table 9. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

• at 85 °C

—

102.92

162.20

• at 105 °C

I_{DD_LLS}Low-leakage stop mode current, all peripheral

disable, at 3.0 V

μA

—

2.06

4.72

3.33

6.85

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

8.13

13.30

24.70

52.43

13.34

41.08

I_{DD_LLS}Low-leakage stop mode current with RTC

current, at 3.0 V

μA

—

2.46

5.12

3.73

7.25

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

8.53

11.78

18.91

52.83

13.74

41.48

I_{DD_LLS}Low-leakage stop mode current with RTC

current, at 1.8 V

3

—

2.35

4.91

2.70

6.75

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

8.32

11.78

18.21

51.85

13.44

40.47

I_{DD_VLLS3}Very-low-leakage stop mode 3 current, all

peripheral disable, at 3.0 V

—

1.45

3.37

5.76

9.72

30.41

1.85

4.39

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

8.48

14.30

37.50

I_{DD_VLLS3}Very-low-leakage stop mode 3 current with RTC

current, at 3.0 V

3

—

2.05

3.97

2.45

4.99

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

6.36

9.08

10.32

31.01

14.73

38.10

Table continues on the next page...

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General

Table 9. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLLS3}Very-low-leakage stop mode 3 current with RTC

current, at 1.8 V

3

μA

—

1.96

3.86

2.36

5.67

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

6.23

8.53

10.21

30.25

13.37

37.02

I_{DD_VLLS1}Very-low-leakage stop mode 1 current all

peripheral disabled at 3.0 V

—

0.66

1.78

2.55

4.83

16.42

0.80

3.87

4.26

6.64

20.49

• at 25 °C and below

• at 50°C

• at 70°C

• at 85°C

• at 105 °C

μA

I_{DD_VLLS1}Very-low-leakage stop mode 1 current RTC

enabled at 3.0 V

3

—

1.26

2.38

3.15

5.43

17.02

1.40

4.47

4.86

7.24

21.09

• at 25 °C and below

• at 50°C

• at 70°C

• at 85°C

• at 105 °C

μA

I_{DD_VLLS1}Very-low-leakage stop mode 1 current RTC

enabled at 1.8 V

3

—

1.16

1.96

2.78

4.85

15.78

1.30

2.28

3.37

6.88

18.81

• at 25 °C and below

• at 50°C

• at 70°C

• at 85°C

• at 105 °C

μA

I_{DD_VLLS0}Very-low-leakage stop mode 0 current all

peripheral disabled (SMC_STOPCTRL[PORPO]

= 0) at 3.0 V

—

0.35

1.25

2.53

4.40

16.09

0.47

1.44

3.24

5.24

19.29

• at 25 °C and below

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

I_{DD_VLLS0}Very-low-leakage stop mode 0 current all

peripheral disabled (SMC_STOPCTRL[PORPO]

= 1) at 3 V

14

Freescale Semiconductor, Inc.

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

General

Notes

Table 9. Power consumption operating behaviors

Symbol Description

• at 25 °C and below

Min.

Typ.

Max.

Unit

—

0.18

0.28

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

—

1.09

2.25

1.31

2.94

μA

4.25

5.10

15.95

19.10

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,

optimized for balanced.

3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.

Table 10. Low power mode peripheral adders — typical value

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

I_IRC8MHz

8 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 8 MHz IRC enabled,

MCG_SC[FCRDIV]=000b,

93

µA

MCG_MC[LIRC_DIV2]=000b.

I_IRC2MHz

2 MHz internal reference clock (IRC)

adder. Measured by entering STOP mode

with the 2 MHz IRC enabled,

MCG_SC[FCRDIV]=000b,

MCG_MC[LIRC_DIV2]=000b.

29

µA

I_EREFSTEN4MHz

External 4 MHz crystal clock adder.

Measured by entering STOP or VLPS

mode with the crystal enabled.

206

224

230

238

245

253

I_{EREFSTEN32KHz}

External 32 kHz crystal clock adder by

means of the OSC0_CR[EREFSTEN and

EREFSTEN] bits. Measured by entering

all modes with the crystal enabled.

• VLLS1

440

490

510

490

560

540

560

570

610

580

680

• VLLS3

• LLS

• VLPS

• STOP

nA

I_LPTMR

LPTMR peripheral adder measured by

placing the device in VLLS1 mode with

LPTMR enabled using LPO.

30

85

100

200

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General

Table 10. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

nA

µA

I_CMP

CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and a

single external input for compare.

22

Includes 6-bit DAC power consumption.

I_UART

UART peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source waiting

for RX data at 115200 baud rate. Includes

selected clock source power

consumption.

114

34

114

34

114

34

114

34

114

34

114

34

µA

• IRC8M (8 MHz internal reference

clock)

• IRC2M (2 MHz internal reference

clock)

I_TPM

TPM peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source

configured for output compare generating

100 Hz clock signal. No load is placed on

the I/O generating the clock signal.

Includes selected clock source and I/O

switching currents.

147

42

147

42

147

42

147

42

147

42

147

42

µA

• IRC8M (8 MHz internal reference

clock)

• IRC2M (2 MHz internal reference

clock)

I_BG

Bandgap adder when BGEN bit is set and

device is placed in VLPx or VLLSx mode.

45

µA

I_ADC

ADC peripheral adder combining the

measured values at V_DDand V_DDAby

placing the device in STOP or VLPS

mode. ADC is configured for low power

mode using the internal clock and

continuous conversions.

330

I_LCD

LCD peripheral adder measured by

placing the device in VLLS1 mode with

external 32 kHz crystal enabled by means

of the OSC0_CR[EREFSTEN,

4.5

µA

EREFSTEN] bits. VIREG disabled,

resistor bias network enabled, 1/8 duty

cycle, 8 x 36 configuration for driving 288

Segments, 32 Hz frame rate, no LCD

glass connected. Includes ERCLK32K (32

kHz external crystal) power consumption.

16

Freescale Semiconductor, Inc.

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

General

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode

• No GPIOs toggled

• Code execution from flash

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Figure 2. Run mode supply current vs. core frequency

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General

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General

Figure 3. VLPR mode current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP

package

Symbol

Description

Frequency

band

Typ.

Unit

Notes

(MHz)

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

11

12

10

6

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

N

2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,

150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -

Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM

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General

Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic

application code. The reported emission level is the value of the maximum measured emission, rounded up to the next

whole number, from among the measured orientations in each frequency range.

2. V_DD= 3.3 V, T_A= 25 °C, f_OSC= IRC48M, f_SYS= 48 MHz, f_BUS= 24 MHz

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 12. Capacitance attributes

Symbol

Description

Min.

Max.

Unit

C_IN

Input capacitance

—

7

pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 13. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Normal run mode

f_SYS

f_BUS

f_FLASH

f_LPTMR

System and core clock¹

Bus clock¹

Flash clock¹

—

48

24

MHz

LPTMR clock

VLPR and VLPS modes²

f_SYS

f_BUS

f_FLASH

f_LPTMR

System and core clock

Bus clock

—

4

1

MHz

Flash clock

LPTMR clock³

1

24

16

f_{LPTMR_ERCLK}LPTMR external reference clock

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General

Table 13. Device clock specifications (continued)

Symbol

Description

Min.

Max.

Unit

f_{osc_hi_2}

Oscillator crystal or resonator frequency — high frequency

mode (high range) (MCG_C2[RANGE]=1x)

—

16

MHz

f_TPM

TPM asynchronous clock

—

8

MHz

f_LPUART0/1

LPUART0/1 asynchronous clock

1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher

than the specified maximum frequency when IRC 48MHz is used as the clock source.

2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing

specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN

or from VLPR.

3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

2.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and

UART signals.

Table 14. General switching specifications

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter disabled)

— Synchronous path

1.5

—

Bus clock

cycles

1

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100

—

ns

2

GPIO pin interrupt pulse width — Asynchronous path

Port rise and fall time

16

—

ns

2

3

36

1. The synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

3. 75 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 15. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Notes

Die junction temperature

Ambient temperature

T_A

105

°C

1

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Peripheral operating requirements and behaviors

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed the maximum. The simplest method to

determine T_Jis: T_J= T_A+ R_θJA× chip power dissipation.

2.4.2 Thermal attributes

Table 16. Thermal attributes

Board type

Single-layer (1S)

Four-layer (2s2p)

Single-layer (1S)

Four-layer (2s2p)

—

Symbol

R_θJA

Description

64 LQFP

64

MAPBGA

Unit

°C/W

Notes

Thermal resistance, junction to

ambient (natural convection)

70

51

58

45

33

20

4

50.3

42.9

41.4

38.0

39.6

27.3

0.4

1

R_θJA

Thermal resistance, junction to

ambient (natural convection)

R_θJMA

R_θJB

Thermal resistance, junction to

ambient (200 ft./min. air speed)

Thermal resistance, junction to

ambient (200 ft./min. air speed)

Thermal resistance, junction to

board

2

3

4

—

R_θJC

Thermal resistance, junction to

case

—

Ψ_JT

Thermal characterization

parameter, junction to package top

outside center (natural convection)

—

Ψ_JB

Thermal characterization

-

12.6

°C/W

5

parameter, junction to package

bottom (natural convection)

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method

Environmental Conditions—Forced Convection (Moving Air).

2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material between

the top of the package and the cold plate.

4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

5. Thermal characterization parameter indicating the temperature difference between package bottom center and the

junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization

parameter is written as Psi-JB.

3 Peripheral operating requirements and behaviors

3.1 Core modules

22

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Peripheral operating requirements and behaviors

3.1.1 SWD electricals

Table 17. SWD full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

J1

SWD_CLK frequency of operation

• Serial wire debug

0

25

—

MHz

ns

J2

J3

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1/J1

20

—

ns

J4

J9

SWD_CLK rise and fall times

—

10

0

3

ns

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

—

32

—

J10

J11

J12

—

5

J2

J4

J3

SWD_CLK (input)

J4

Figure 4. Serial wire clock input timing

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Peripheral operating requirements and behaviors

SWD_CLK

SWD_DIO

J9

J10

Input data valid

J11

Output data valid

SWD_DIO

J12

SWD_DIO

J11

Output data valid

SWD_DIO

Figure 5. Serial wire data timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG-Lite specifications

Table 18. IRC48M specification

Symbol

I_DD

Description

Supply current

Output frequency

Min.

—

Typ.

400

48

Max.

500

—

Unit

µA

Notes

—

f_IRC

—

MHz

—

Δf_{irc48m_ol_lv}

Open loop total deviation of IRC48M

frequency at low voltage

(VDD=1.71V-1.89V) over temperature

1

—

0.5

1.5

%f_irc48m

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M

frequency at high voltage

1

0.5

1.0

%f_irc48m

(VDD=1.89V-3.6V) over temperature

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Peripheral operating requirements and behaviors

Table 18. IRC48M specification (continued)

Symbol

T_j

Description

Period jitter (RMS)

Startup time

Min.

—

Typ.

35

Max.

150

3

Unit

ps

Notes

—

T_su

—

2

µs

—

1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard

deviation (mean +/-3sigma).

Table 19. IRC8M/2M specification

Symbol

I_{DD_2M}

Description

Supply current in 2 MHz mode

Supply current in 8 MHz mode

Output frequency

Min.

—

Typ.

14

30

2

Max.

17

Unit

µA

Notes

—

I_{DD_8M}

—

35

µA

—

f_{IRC_2M}

f_{IRC_8M}

f_{IRC_T_2M}

f_{IRC_T_8M}

T_{su_2M}

—

MHz

%f_IRC

µs

—

Output frequency

—

8

—

Output frequency range (trimmed)

Startup time

—

3

—

3

—

12.5

—

T_{su_8M}

Startup time

—

µs

—

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Peripheral operating requirements and behaviors

Figure 6. IRC8M Frequency Drift vs Temperature curve

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

Table 20. Oscillator DC electrical specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_DD

Supply voltage

1.71

—

3.6

V

I_DDOSC

Supply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 20. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

• 24 MHz

—

1.5

—

mA

• 32 MHz

I_DDOSC

Supply current — high gain mode (HGO=1)

1

• 32 kHz

—

25

400

500

2.5

3

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-power

mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

0

—

kΩ

V

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

0.6

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

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Peripheral operating requirements and behaviors

3. C_x,C_ycan be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For

all other cases external capacitors must be used.

4. When low power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other devices.

3.3.2.2 Oscillator frequency specifications

Table 21. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

3

8

—

8

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

50

48

60

—

MHz

%

1, 2

3, 4

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

register being set.

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

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Peripheral operating requirements and behaviors

3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps

are active and do not include command overhead.

Table 22. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

13

Max.

18

Unit

μs

Notes

t_hvpgm4Longword Program high-voltage time

t_hversscrSector Erase high-voltage time

t_hversblk128kErase Block high-voltage time for 128 KB

—

1

—

113

452

ms

—

52

1

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 23. Flash command timing specifications

Symbol Description

Read 1s Block execution time

• 128 KB program flash

Min.

Typ.

Max.

Unit

Notes

1

t_rd1blk128k

—

1.7

ms

t_rd1sec1kRead 1s Section execution time (flash sector)

t_pgmchkProgram Check execution time

—

65

60

45

μs

1

t_rdrsrc

t_pgm4

Read Resource execution time

Program Longword execution time

Erase Flash Block execution time

• 128 KB program flash

30

1

145

—

2

t_ersblk128k

—

88

600

ms

t_ersscr

t_rd1all

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

14

—

114

1.8

ms

μs

2

1

t_rdonce

—

25

1

t_pgmonceProgram Once execution time

65

—

μs

—

2

t_ersall

t_vfykey

t_ersallu

Erase All Blocks execution time

175

—

1300

30

ms

μs

Verify Backdoor Access Key execution time

Erase All Blocks Unsecure execution time

1

175

1300

ms

2

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

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Peripheral operating requirements and behaviors

3.4.1.3 Flash high voltage current behaviors

Table 24. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

3.4.1.4 Reliability specifications

Table 25. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

—

2

20

100

50 K

10 K

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T_j≤ 125 °C.

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

Using differential inputs can achieve better system accuracy than using single-end

inputs.

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Peripheral operating requirements and behaviors

3.6.1.1 16-bit ADC operating conditions

Table 26. 16-bit ADC operating conditions

Symbol Description

V_DDASupply voltage

ΔV_DDASupply voltage

Conditions

Min.

1.71

-100

1.13

Typ.¹

Max.

3.6

Unit

V

Notes

Absolute

—

2

Delta to V_DD(V_DD– V_DDA

)

0

+100

V_DDA

mV

V

ΔV_SSA

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

2

V_REFH

ADC reference

voltage high

V_DDA

3

V_REFL

V_ADIN

ADC reference

voltage low

V_SSA

V

3

Input voltage

• 16-bit differential mode

• All other modes

• 16-bit mode

VREFL

—

31/32 ×

VREFH

—

VREFH

C_ADIN

Input

capacitance

—

8

4

10

5

pF

—

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

—

4

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

—

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

2.0

—

24

MHz

5

6

ADC conversion 16-bit mode

clock frequency

12.0

ADC conversion ≤ 13-bit modes

rate

No ADC hardware averaging

20.000

37.037

—

1200

ksps

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

6

rate

No ADC hardware averaging

461.467

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. VREFH can act as VREF_OUT when VREFV1 module is enabled.

4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

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Peripheral operating requirements and behaviors

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

ZADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

ZAS

leakage

due to

input

ADC SAR

ENGINE

RAS

RADIN

protection

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 7. ADC input impedance equivalency diagram

3.6.1.2 16-bit ADC electrical characteristics

Table 27. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

mA

Notes

I_{DDA_ADC}Supply current

—

3

ADC

asynchronous

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK=

1/f_ADACK

2.4

clock source

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total

unadjusted error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

• 12-bit modes

• <12-bit modes

—

0.7

0.2

1.0

0.5

–1.1 to

+1.9

–0.3 to 0.5

INL

Integral non-

linearity

–2.7 to

+1.9

LSB⁴

5

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 27. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

–0.7 to

+0.5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN

V_DDA

=

5

Quantization

error

0.5

ENOB Effective

number of bits

16-bit differential mode

• Avg = 32

6

bits

12.8

11.9

14.5

13.8

• Avg = 4

—

bits

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

• Avg = 4

Signal-to-noise See ENOB

plus distortion

SINAD

THD

6.02 × ENOB + 1.76

dB

Total harmonic 16-bit differential mode

7

dB

distortion

—

-94

-85

—

• Avg = 32

16-bit single-ended mode

• Avg = 32

SFDR

Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

dB

82

78

95

90

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage

error

I_In× R_AS

mV

I_In=

leakage

current

(refer to

the MCU's

voltage

and

current

operating

ratings)

Temp sensor

slope

Across the full temperature range

of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

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Peripheral operating requirements and behaviors

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

11.00

Averaging of 4 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

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Peripheral operating requirements and behaviors

3.6.2 Voltage reference electrical specifications

Table 28. VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Supply voltage

Temperature

Min.

Max.

Unit

V

Notes

—

3.6

Operating temperature

range of the device

°C

—

C_L

Output load capacitance

100

nF

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature

range of the device.

Table 29 is tested under the condition of setting VREF_TRM[CHOPEN],

VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.

Table 29. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim at

1.1915

1.195

1.1977

V

1

nominal V_DDAand temperature=25C

Voltage reference output — factory trim

Voltage reference output — user trim

Voltage reference trim step

V_out

1.1584

1.193

—

1.2376

1.197

—

V

1

V_step

V_tdrift

0.5

—

mV

Temperature drift (Vmax -Vmin across the full

temperature range: 0 to 70°C)

—

50

I_bg

I_lp

Bandgap only current

—

80

360

1

µA

uA

mA

µV

1

Low-power buffer current

High-power buffer current

I_hp

1

ΔV_LOADLoad regulation

• current = 1.0 mA

1, 2

—

200

—

T_stup

Buffer startup time

—

100

35

µs

—

T_{chop_osc_st}Internal bandgap start-up delay with chop

ms

oscillator enabled

up

V_vdrift

Voltage drift (Vmax -Vmin across the full

voltage range)

—

2

—

mV

1

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

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Peripheral operating requirements and behaviors

Table 30. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

50

°C

—

Table 31. VREF limited-range operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim

1.173

1.225

V

—

3.6.3 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

50

250

—

7

—

0.5

200

600

40

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

μA

LSB³

LSB

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

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Peripheral operating requirements and behaviors

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.6.4 12-bit DAC electrical characteristics

3.6.4.1 12-bit DAC operating requirements

Table 33. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

Max.

3.6

100

1

Unit

V

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

1.13

—

V

1

2

pF

mA

I_L

—

1. The DAC reference can be selected to be V_DDAor V_REFH

.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

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Peripheral operating requirements and behaviors

3.6.4.2 12-bit DAC operating behaviors

Table 34. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

250

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

μA

P

I_{DDA_DACH}Supply current — high-speed mode

—

100

15

900

200

30

μA

μs

P

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

1

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

t_CCDACLPCode-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-

speed mode

0.7

1

V_dacoutlDAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

—

100

mV

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

V_DACR

INL

DNL

Integral non-linearity error — high speed

mode

—

8

1

LSB

2

3

4

Differential non-linearity error — V_DACR> 2

V

Differential non-linearity error — V_DACR

VREF_OUT

=

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

60

—

0.4

0.1

0.8

0.6

90

%FSR

dB

5

—

T_CO

T_GE

Rop

SR

Temperature coefficient offset voltage

Temperature coefficient gain error

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

3.7

—

μV/C

%FSR/C

Ω

6

0.000421

—

250

V/μs

• High power (SP_HP

)

1.2

1.7

—

• Low power (SP_LP

)

0.05

0.12

BW

3dB bandwidth

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

40

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC

set to 0x800, temperature range is across the full range of the device

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Peripheral operating requirements and behaviors

8

6

4

2

0

-2

-4

-6

-8

0

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 12. Typical INL error vs. digital code

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Peripheral operating requirements and behaviors

1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

55

85

25

105

125

-40

Temperature °C

Figure 13. Offset at half scale vs. temperature

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

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Peripheral operating requirements and behaviors

3.8.1 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following

tables provide timing characteristics for classic SPI timing modes. See the SPI chapter

of the chip's Reference Manual for information about the modified transfer formats used

for communicating with slower peripheral devices.

All timing is shown with respect to 20% V_DDand 80% V_DDthresholds, unless noted, as

well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.

Table 35. SPI master mode timing on slew rate disabled pads

Num.

Symbol Description

Min.

Max.

Unit

Hz

Note

1

2

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

1

2

t_SPSCK

SPSCK period

2048 x

t_periph

ns

3

4

5

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

ns

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

18

0

—

ns

—

15

8

t_v

—

0

9

t_HO

t_RI

—

10

—

t_periph- 25

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

Table 36. SPI master mode timing on slew rate enabled pads

Num.

Symbol Description

Min.

Max.

Unit

Hz

Note

1

2

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

1

2

t_SPSCK

SPSCK period

2048 x

t_periph

ns

3

4

5

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

ns

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

96

0

—

ns

—

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 36. SPI master mode timing on slew rate enabled pads (continued)

Num.

Symbol Description

Min.

—

Max.

52

Unit

ns

Note

—

8

9

t_v

Data valid (after SPSCK edge)

t_HO

t_RI

Data hold time (outputs)

Rise time input

0

—

ns

—

10

—

t_periph- 25

ns

—

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

Fall time output

—

36

ns

—

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

1

SS

(OUTPUT)

3

2

10

11

4

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

8

MSB IN

LSB IN

9

MOSI

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 14. SPI master mode timing (CPHA = 0)

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Peripheral operating requirements and behaviors

1

SS

(OUTPUT)

2

10

11

4

3

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

LSB IN

MSB IN

9

8

MOSI

(OUTPUT)

2

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 15. SPI master mode timing (CPHA = 1)

Table 37. SPI slave mode timing on slew rate disabled pads

Num.

1

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Hz

Note

1

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

0

2

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

ns

2

3

1

—

t_periph

ns

—

3

4

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2.5

3.5

—

0

—

ns

7

—

ns

8

t_periph

31

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

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Peripheral operating requirements and behaviors

Table 38. SPI slave mode timing on slew rate enabled pads

Num.

1

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Hz

Note

1

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

0

2

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

ns

2

3

1

—

t_periph

ns

—

3

4

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2

7

—

ns

7

—

ns

8

—

0

t_periph

122

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

36

ns

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

SS

(INPUT)

2

12

13

4

SPSCK

(CPOL=0)

(INPUT)

5

3

SPSCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 16. SPI slave mode timing (CPHA = 0)

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Peripheral operating requirements and behaviors

SS

(INPUT)

4

2

12

13

3

SPSCK

(CPOL=0)

(INPUT)

5

SPSCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

8

6

7

MOSI

(INPUT)

MSB IN

NOTE: Not defined

Figure 17. SPI slave mode timing (CPHA = 1)

3.8.2 I²C

3.8.2.1 Inter-Integrated Circuit Interface (I2C) timing

Table 39. I2C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

400¹

SCL Clock Frequency

f_SCL

0

kHz

µs

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

4

—

0.6

—

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.25

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

0.6

Data hold time for I²C bus devices

t_HD; DAT

t_SU; DAT

t_r

0²

250⁵

—

3.45³

—

0⁴

100³, ⁶

20 +0.1C_b

0.6

0.9²

—

µs

ns

µs

Data set-up time

7

6

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

1000

300

—

300

—

t_f

—

t_SU; STO

t_BUF

4

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

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Freescale Semiconductor, Inc.

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Peripheral operating requirements and behaviors

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the

high drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.

2. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and

SCL lines.

3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. Input signal Slew = 10 ns and Output Load = 50 pF

5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

6. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT}≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax

+ t_{SU; DAT}= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is

released.

7. C_b= total capacitance of the one bus line in pF.

To achieve 1MHz I2C clock rates, consider the following recommendations:

• To counter the effects of clock stretching, the I2C baud Rate select bits can be

configured for faster than desired baud rate.

• Use high drive pad and DSE bit should be set in PORTx_PCRn register.

• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for

the SCL line to avoid clock stretching.

• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.

Table 40. I ²C 1Mbit/s timing

Characteristic

Symbol

f_SCL

Minimum

Maximum

Unit

MHz

µs

SCL Clock Frequency

0

1¹

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

t_HD; STA

0.26

—

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time for I₂C bus devices

Data set-up time

t_LOW

t_HIGH

0.5

0.26

—

µs

ns

µs

t_SU; STA

t_HD; DAT

t_SU; DAT

t_r

0.26

—

0

—

50

—

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

20 +0.1C_b

120

—

2

t_f

20 +0.1C_b

0.26

t_SU; STO

t_BUF

Bus free time between STOP and START

condition

0.5

—

Pulse width of spikes that must be suppressed by

the input filter

t_SP

0

50

ns

1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins

across the full voltage range.

2. C_b= total capacitance of the one bus line in pF.

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Peripheral operating requirements and behaviors

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 18. Timing definition for devices on the I²C bus

3.8.3 UART

See General switching specifications.

3.8.4 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are

driven) and slave mode (clocks are input). All timing is given for noninverted serial

clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync

(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync

have been inverted, all the timing remains valid by inverting the bit clock signal

(BCLK) and/or the frame sync (FS) signal shown in the following figures.

3.8.4.1 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 41. I2S/SAI master mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

40

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK (as an input) pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

45%

80

55%

—

MCLK period

ns

45%

—

55%

15.5

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

Table continues on the next page...

48

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Peripheral operating requirements and behaviors

Table 41. I2S/SAI master mode timing (continued)

Num.

Characteristic

Min.

Max.

Unit

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

0

19

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

26

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

0

—

ns

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 19. I2S/SAI timing — master modes

Table 42. I2S/SAI slave mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

1.71

80

3.6

—

V

S11

S12

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

(input)

55%

MCLK period

S13

S14

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

10

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

2

—

S15

S16

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

—

0

33

—

ns

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output

invalid

S17

I2S_RXD setup before I2S_RX_BCLK

10

—

ns

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 42. I2S/SAI slave mode timing (continued)

Num.

S18

S19

Characteristic

Min.

Max.

Unit

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

2

—

ns

—

28

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 20. I2S/SAI timing — slave modes

3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in VLPR, VLPW, and VLPS modes.

Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes

(full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

62.5

45%

250

45%

—

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

55%

—

MCLK period

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

ns

55%

45

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

S6

S7

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

I2S_TX_BCLK to I2S_TXD valid

—

45

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

(continued)

Num.

Characteristic

Min.

Max.

Unit

S8

S9

I2S_TX_BCLK to I2S_TXD invalid

0

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

—

ns

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 21. I2S/SAI timing — master modes

Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full

voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

1.71

250

3.6

—

V

S11

ns

S12

S13

S14

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

(input)

55%

MCLK period

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

30

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

2

—

S15

S16

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

—

0

87

—

ns

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output

invalid

S17

S18

S19

I2S_RXD setup before I2S_RX_BCLK

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

30

2

—

72

ns

—

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Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 22. I2S/SAI timing — slave modes

3.9 Human-machine interfaces (HMI)

3.9.1 LCD electrical characteristics

Table 45. LCD electricals

Symbol Description

f_FrameLCD frame frequency

Min.

Typ.

Max.

Unit

Notes

• GCR[FFR]=0

• GCR[FFR]=1

23.3

46.6

—

73.1

Hz

146.2

C_LCD

LCD charge pump capacitance — nominal value

—

100

—

nF

pF

V

C_BYLCDLCD bypass capacitance — nominal value

1

2

3

C_Glass

V_IREG

LCD glass capacitance

V_IREG

2000

8000

• RVTRIM=0000

• RVTRIM=1000

• RVTRIM=0100

• RVTRIM=1100

• RVTRIM=0010

• RVTRIM=1010

• RVTRIM=0110

—

0.91

0.92

0.93

0.94

0.96

0.97

0.98

0.99

—

Table continues on the next page...

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Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Peripheral operating requirements and behaviors

Table 45. LCD electricals (continued)

Symbol Description

• RVTRIM=1110

Min.

Typ.

Max.

Unit

Notes

—

1.01

—

• RVTRIM=0001

• RVTRIM=1001

• RVTRIM=0101

• RVTRIM=1101

• RVTRIM=0011

• RVTRIM=1011

• RVTRIM=0111

• RVTRIM=1111

—

1.02

1.03

1.05

1.06

1.07

1.08

1.09

—

Δ_RTRIMV_IREGTRIM resolution

—

1

3.0

—

% V_IREG

µA

I_VIREG

I_RBIAS

V_IREGcurrent adder — RVEN = 1

RBIAS current adder

• LADJ = 10 or 11 — High load (LCD glass

capacitance ≤ 8000 pF)

—

10

1

—

µA

• LADJ = 00 or 01 — Low load (LCD glass

capacitance ≤ 2000 pF)

R_RBIAS

RBIAS resistor values

• LADJ = 10 or 11 — High load (LCD glass

capacitance ≤ 8000 pF)

—

0.28

2.98

—

MΩ

• LADJ = 00 or 01 — Low load (LCD glass

capacitance ≤ 2000 pF)

VLL1

VLL2

VLL3

VLL1

VLL2

VLL3

VLL1 voltage

VLL2 voltage

VLL3 voltage

VLL1 voltage

VLL2 voltage

VLL3 voltage

—

V_IREG

2 x V_IREG

3 x V_IREG

V_DDA/ 3

V_DDA/ 1.5

V_DDA

V

4

5

1. The actual value used could vary with tolerance.

2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller

chapter within the device's reference manual.

3. V_IREGmaximum should never be externally driven to any level other than V_DD- 0.15 V

4. VLL1, VLL2 and VLL3 are a function of V_IREGonly when the regulator is enabled (GCR[RVEN]=1) and the charge

pump is enabled (GCR[CPSEL]=1).

5. VLL1, VLL2 and VLL3 are a function of V_DDAonly under either of the following conditions:

• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = V_DDA

through the internal power switch (GCR[VSUPPLY]=0).

• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is

connected to V_DDAexternally (GCR[VSUPPLY]=1).

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Dimensions

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to freescale.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

64-pin LQFP

Then use this document number

98ASS23234W

98ASA00420D

64-pin MAPBGA

5 Pinouts and Packaging

5.1 KL33 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

NOTE

VREFH can act as VREF_OUT when VREFV1 module is

enabled.

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP MAP

BGA

—

1

E4

A1

VDD

PTE0

DISABLED

LCD_P48

PTE0/

CLKOUT32K

SPI1_MISO

SPI1_MOSI

LPUART1_TX

LPUART1_RX

RTC_CLKOUT CMP0_OUT

SPI1_MISO

I2C1_SDA

I2C1_SCL

LCD_P48

LCD_P49

2

3

4

5

B1

—

PTE1

VDD

DISABLED

VDD

LCD_P49

VDD

PTE1

C4

E1

VSS

PTE16

ADC0_DP1/

ADC0_SE1

LCD_P55/

ADC0_DP1/

ADC0_SE1

PTE16

SPI0_SS

UART2_TX

TPM_CLKIN0

FXI00_D0

LCD_P55

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Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Pinouts and Packaging

64

Pin Name

Default

ALT0

ALT1

ALT2

SPI0_SCK

SPI0_MOSI

SPI0_MISO

ALT3

ALT4

ALT5

ALT6

FXIO0_D1

FXIO0_D2

FXIO0_D3

FXI00_D4

FXIO0_D5

ALT7

LCD_P56

LCD_P57

LCD_P58

LCD_P59

LCD_P60

LQFP MAP

BGA

6

7

D1

E2

D2

G1

F1

PTE17

ADC0_DM1/

ADC0_SE5a

LCD_P56/

ADC0_DM1/

ADC0_SE5a

PTE17

UART2_RX

TPM_CLKIN1

I2C0_SDA

LPTMR0_

ALT3

PTE18

PTE19

PTE20

PTE21

ADC0_DP2/

ADC0_SE2

LCD_P57/

ADC0_DP2/

ADC0_SE2

PTE18

PTE19

PTE20

PTE21

SPI0_MISO

SPI0_MOSI

8

ADC0_DM2/

ADC0_SE6a

LCD_P58/

ADC0_DM2/

ADC0_SE6a

I2C0_SCL

9

ADC0_DP0/

ADC0_SE0

LCD_P59/

ADC0_DP0/

ADC0_SE0

TPM1_CH0

TPM1_CH1

LPUART0_TX

LPUART0_RX

10

ADC0_DM0/

ADC0_SE4a

LCD_P60/

ADC0_DM0/

ADC0_SE4a

11

12

G2

F2

PTE22

PTE23

ADC0_DP3/

ADC0_SE3

ADC0_DP3/

ADC0_SE3

PTE22

PTE23

TPM2_CH0

TPM2_CH1

UART2_TX

UART2_RX

FXIO0_D6

FXIO0_D7

ADC0_DM3/

ADC0_SE7a

ADC0_DM3/

ADC0_SE7a

13

14

15

16

17

F4

G4

G3

F3

H1

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

PTE29

CMP0_IN5/

ADC0_SE4b

CMP0_IN5/

ADC0_SE4b

PTE29

PTE30

TPM0_CH2

TPM0_CH3

TPM_CLKIN0

TPM_CLKIN1

18

H2

PTE30

DAC0_OUT/

ADC0_SE23/

CMP0_IN4

DAC0_OUT/

ADC0_SE23/

CMP0_IN4

LPUART1_TX

LPTMR0_

ALT1

19

20

21

22

23

24

25

26

27

H3

H4

H5

D3

D4

E5

D5

G5

F5

PTE31

PTE24

PTE25

PTA0

PTA1

PTA2

PTA3

PTA4

PTA5

DISABLED

SWD_CLK

DISABLED

SWD_DIO

NMI_b

PTE31

PTE24

PTE25

PTA0

PTA1

PTA2

PTA3

PTA4

PTA5

TPM0_CH4

TPM0_CH0

TPM0_CH1

TPM0_CH5

TPM2_CH0

TPM2_CH1

TPM0_CH0

TPM0_CH1

TPM0_CH2

I2C0_SCL

I2C0_SDA

SWD_CLK

LPUART0_RX

LPUART0_TX

I2C1_SCL

SWD_DIO

NMI_b

I2C1_SDA

DISABLED

I2S0_TX_

BCLK

28

29

30

31

32

H6

G6

G7

H7

H8

PTA12

PTA13

VDD

DISABLED

VDD

PTA12

PTA13

TPM1_CH0

TPM1_CH1

I2S0_TXD0

I2S0_TX_FS

VDD

VSS

PTA18

EXTAL0

PTA18

LPUART1_RX

TPM_CLKIN0

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Pinouts and Packaging

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP MAP

BGA

33

G8

PTA19

XTAL0

PTA19

LPUART1_TX

TPM_CLKIN1

LPTMR0_

ALT1

34

35

F8

F7

PTA20

RESET_b

PTA20

RESET_b

LCD_P0

PTB0/

LLWU_P5

LCD_P0/

ADC0_SE8

LCD_P0/

ADC0_SE8

PTB0/

LLWU_P5

I2C0_SCL

I2C0_SDA

I2C0_SCL

I2C0_SDA

TPM1_CH0

TPM1_CH1

TPM2_CH0

TPM2_CH1

36

37

38

F6

E7

E8

PTB1

PTB2

PTB3

LCD_P1/

ADC0_SE9

LCD_P1/

ADC0_SE9

PTB1

PTB2

PTB3

LCD_P1

LCD_P2

LCD_P3

LCD_P2/

ADC0_SE12

LCD_P2/

ADC0_SE12

LCD_P3/

ADC0_SE13

39

40

41

E6

D7

D6

PTB16

PTB17

PTB18

LCD_P12

LCD_P13

LCD_P14

LCD_P12

LCD_P13

LCD_P14

PTB16

PTB17

PTB18

SPI1_MOSI

SPI1_MISO

LPUART0_RX

LPUART0_TX

TPM2_CH0

TPM_CLKIN0

TPM_CLKIN1

SPI1_MISO

SPI1_MOSI

LCD_P12

LCD_P13

LCD_P14

I2S0_TX_

BCLK

42

43

C7

D8

PTB19

PTC0

LCD_P15

PTB19

PTC0

TPM2_CH1

EXTRG_IN

I2S0_TX_FS

LCD_P15

LCD_P20

LCD_P20/

ADC0_SE14

LCD_P20/

ADC0_SE14

audioUSB_

SOF_OUT

CMP0_OUT

I2S0_TXD0

44

C6

PTC1/

LCD_P21/

PTC1/

I2C1_SCL

TPM0_CH0

LCD_P21

LLWU_P6/

RTC_CLKIN

ADC0_SE15

LLWU_P6/

RTC_CLKIN

45

46

B7

C8

PTC2

LCD_P22/

ADC0_SE11

LCD_P22/

ADC0_SE11

PTC2

I2C1_SDA

SPI1_SCK

TPM0_CH1

TPM0_CH2

I2S0_TX_FS

LCD_P22

LCD_P23

PTC3/

LLWU_P7

LCD_P23

PTC3/

LLWU_P7

LPUART1_RX

CLKOUT

I2S0_TX_

BCLK

47

48

49

E3

C5

A6

VSS

VLL3

VLL2

VLL3

VLL2

VLL3

VLL2/

LCD_P4

PTC20

PTC21

PTC22

PTC23

LCD_P4

LCD_P5

LCD_P6

LCD_P39

LCD_P24

LCD_P25

LCD_P26

LCD_P27

LCD_P40

50

51

52

53

54

55

56

57

B5

B4

A5

B8

A8

A7

B6

C3

VLL1

VLL1/

LCD_P5

VCAP2

VCAP1

VCAP2

VCAP1

LCD_P24

LCD_P25

VCAP2/

LCD_P6

VCAP1/

LCD_P39

PTC4/

LLWU_P8

LCD_P24

LCD_P25

PTC4/

LLWU_P8

SPI0_SS

LPUART1_TX

TPM0_CH3

I2S0_RXD0

I2S0_MCLK

PTC5/

LLWU_P9

PTC5/

LLWU_P9

SPI0_SCK

SPI0_MOSI

SPI0_MISO

SPI0_SS

LPTMR0_

ALT2

CMP0_OUT

I2S0_MCLK

PTC6/

LLWU_P10

LCD_P26/

CMP0_IN0

LCD_P26/

CMP0_IN0

PTC6/

LLWU_P10

EXTRG_IN

I2S0_RX_

BCLK

SPI0_MISO

SPI0_MOSI

PTC7

PTD0

LCD_P27/

CMP0_IN1

LCD_P27/

CMP0_IN1

PTC7

PTD0

audioUSB_

SOF_OUT

I2S0_RX_FS

LCD_P40

TPM0_CH0

FXI00_D0

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Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Pinouts and Packaging

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP MAP

BGA

58

A4

PTD1

LCD_P41/

PTD1

SPI0_SCK

TPM0_CH1

FXIO0_D1

LCD_P41

ADC0_SE5b

59

60

61

C2

B3

A3

PTD2

PTD3

LCD_P42

LCD_P43

LCD_P44

LCD_P42

LCD_P43

LCD_P44

PTD2

PTD3

SPI0_MOSI

SPI0_MISO

SPI1_SS

UART2_RX

UART2_TX

UART2_RX

TPM0_CH2

TPM0_CH3

TPM0_CH4

SPI0_MISO

SPI0_MOSI

FXIO0_D2

FXIO0_D3

FXI00_D4

LCD_P42

LCD_P43

LCD_P44

PTD4/

LLWU_P14

62

63

64

C1

B2

A2

PTD5

LCD_P45/

ADC0_SE6b

LCD_P45/

ADC0_SE6b

PTD5

SPI1_SCK

SPI1_MOSI

SPI1_MISO

UART2_TX

TPM0_CH5

FXIO0_D5

FXIO0_D6

FXIO0_D7

LCD_P45

LCD_P46

LCD_P47

PTD6/

LLWU_P15

LCD_P46/

ADC0_SE7b

LCD_P46/

ADC0_SE7b

PTD6/

LLWU_P15

LPUART0_RX

LPUART0_TX

SPI1_MISO

SPI1_MOSI

PTD7

LCD_P47

PTD7

5.2 KL33 Family Pinouts

Figure below shows the 64 LQFP pinouts:

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Freescale Semiconductor, Inc.

Pinouts and Packaging

PTE0

PTE1

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VLL3

2

VSS

VDD

3

PTC3/LLWU_P7

VSS

4

PTC2

PTE16

PTE17

PTE18

PTE19

PTE20

PTE21

PTE22

PTE23

VDDA

VREFH

VREFL

VSSA

5

PTC1/LLWU_P6/RTC_CLKIN

6

PTC0

7

PTB19

PTB18

PTB17

PTB16

PTB3

8

9

10

11

12

13

14

15

16

PTB2

PTB1

PTB0/LLWU_P5

PTA20

PTA19

Figure 23. 64 LQFP Pinout diagram

Figure below shows the 64 MAPBGA pinouts:

58

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Freescale Semiconductor, Inc.

Ordering parts

1

2

3

4

5

6

7

8

PTC6/

LLWU_P10

PTD4/

LLWU_P14

PTC5/

LLWU_P9

A

B

C

D

E

F

PTE0

PTD7

PTD1

VCAP1

VLL2

A

B

C

D

E

F

PTC4/

LLWU_P8

PTD6/

LLWU_P15

PTE1

PTD5

PTD3

PTD0

PTA0

VSS

VCAP2

VSS

VLL1

VLL3

PTA3

PTA2

PTA5

PTA4

PTC7

PTC2

PTB19

PTB17

PTB2

PTC1/

LLWU_P6/

RTC_CLKIN

PTC3/

LLWU_P7

PTD2

PTE19

PTE18

PTE23

PTE22

PTE17

PTE16

PTE21

PTE20

PTA1

PTB18

PTB16

PTB1

PTC0

PTB3

VDD

PTB0/

LLWU_P5

VSSA

VREFL

VDDA

VREFH

PTA20

PTA19

G

H

PTA13

VDD

G

H

PTE29

1

PTE30

2

PTE31

3

PTE24

4

PTE25

5

PTA12

6

VSS

7

PTA18

8

Figure 24. 64 MAPBGA Pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the Web. To determine the orderable

part numbers for this device, go to freescale.com and perform a part number search for

the following device numbers:

7 Part identification

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Freescale Semiconductor, Inc.

Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format:

Q KL## A FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Table 46. Part number fields descriptions

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

KL##

A

Kinetis family

Key attribute

• KL33

• Z = Cortex-M0+

FFF

R

Program flash memory size

Silicon revision

• (Blank) = Main

• A = Revision after main

T

Temperature range (°C)

Package identifier

• V = –40 to 105

PP

• LH = 64 LQFP (10 mm x 10 mm)

• MP = 64 MAPBGA (5 mm x 5 mm)

CC

N

Maximum CPU frequency (MHz)

Packaging type

• 4 = 48 MHz

• R = Tape and reel

7.4 Example

This is an example part number:

MKL33Z256VMP4

60

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

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Terminology and guidelines

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table:

Term

Definition

Rating

A minimum or maximum value of a technical characteristic that, if exceeded, may cause

permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic

begins to exceed one of its operating ratings.

Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during

operation to avoid incorrect operation and possibly decreasing the useful life of the chip

Operating behavior

A specified value or range of values for a technical characteristic that are guaranteed during

operation if you meet the operating requirements and any other specified conditions

Typical value

A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Is representative of that characteristic during operation when you meet the typical-value

conditions or other specified conditions

NOTE: Typical values are provided as design guidelines and are neither tested nor

guaranteed.

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Terminology and guidelines

8.2 Examples

Operating rating:

Operating requirement:

Operating behavior that includes a typical value:

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

3.3 V supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

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Revision History

8.4 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

9 Revision History

The following table provides a revision history for this document.

Table 47. Revision History

Rev. No.

Date

Substantial Changes

3

09 August Initial Public release

2014

• Updated Table 9 - Power consumption operating behaviors.

4

03 March

2015

• Updated the features and completed the ordering information.

• Removed thickness dimension from package diagrams.

Table continues on the next page...

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Revision History

Rev. No.

Table 47. Revision History (continued)

Date

Substantial Changes

• Updated Related Resources table to include Chip Errata resource name and

Package Drawing part numbers in the respective rows.

• Updated Table 7. Voltage and current operating behaviors.

• Specified correct max. value for I_IN.

• Updated Table - 9 Power consumption operating behaviors.

• Rows added for IDD for reset pin hold low (I_{DD_RESET_LOW}) at 1.7V and 3V.

• Measurement unit updated for I_{DD_VLLS1}from nA to μA.

• Footnote 1 was moved in the beginning of the table as text.

• Added Table - 11 EMC radiated emissions operating behaviors for 64-pin LQFP

package under section 2.2.6.

• Updated Table - 18 (IRC48M specification) and Table - 19 (IRC8M/2M specification)

under section 3.3.1 - 'MCG-Lite specifications'.

• Removed supply voltage (V_DD), temperature range (T), untrimmed (f_{IRC_UT}),

trim function (Δf_{IRC_C}, Δf_{IRC_F}) data from Table - 18 (IRC48M specification).

• Removed supply voltage (V_DD), temperature range (T) data from Table - 19

(IRC8M/2M specification).

• Added Figure 6. IRC8M Frequency Drift vs Temperature curve after Table - 19

(IRC8M/2M specification).

• Updated Table 29. VREF full-range operating behaviors.

• Removed A_c(Aging coefficient) row.

• Added T_{chop_osc_stup}parameter.

• Updated typical value of the V_outparameter.

• Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I²C.

• Added VREF specifications (V_REFHand V_REFL) to Table 26. 16-bit ADC operating

conditions.

• Removed note: “This device does not have the USB_CLKIN signal available.”

5

12 August

2015

• In Table 9. Power consumption operating behaviors:

• Updated Max. values of I_{DD_WAIT}, I_{DD_VLPW}, I_{DD_STOP}, I_{DD_VLPS}, I_{DD_LLS}

,

I_{DD_VLLS3}, I_{DD_VLLS1}, I_{DD_VLLS0}

.

• Modified unit of I_{DD_VLLS0}from nA to μA.

• Removed I_{DD_RESET_LOW}information.

• In Table 13. Device clock specifications, added a footnote for normal run mode.

• In Table 15. Thermal operating requirements, modified the footnote for Ambient

temperature.

• In Table 18. IRC48M specification, removed f_{IRC_T}data and added Δf_{irc48m_of_lv}and

Δf_{irc48m_of_hv}specifications.

• In Table 26. 16-bit ADC operating conditions, updated Max. value of f_ADCKand C_rate

.

64

Kinetis KL33 Microcontroller, Rev.5, 08/2015.

Freescale Semiconductor, Inc.


型号：	MKL33Z128VMP4
厂家：	NXP
描述：	Kinetis KL33 Microcontroller 微控制器
文件：	总65页 (文件大小：1327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MKL33Z128VMP4 [NXP]

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