MKM35Z256VLQ7_技术文档

NXP Semiconductors

Data Sheet: Technical Data

KM35P144M75SF0

Rev. 2, March 2020

Kinetis KM35 Sub-Family Data

Sheet

MKM35Z256VLL7

MKM35Z256VLQ7

MKM35Z512VLL7

MKM35Z512VLQ7

Enabling high accuracy, secure 1-, 2- and 3-phase electricity

metering solutions through a powerful analog front end (AFE),

auto-compensated iRTC with hardware tamper detection,

segment LCD controller, rich security protection and multiple low

power features in a 32-bit Arm^®Cortex^®-M0+ MCU. This product

offers:

• Enabling single-chip 1-, 2- and 3-phase metering designs

• AFE, Security and HMI. Single crystal implementation

• Single point of calibration during manufacture

• Highest accuracy metrology with regional feature support

• Multiple ƩΔ ADCs with PGA

100 LQFP

14 mm × 14 mm Pitch 20 mm × 20 mm Pitch

0.5 mm 0.5 mm

144 LQFP

• Supports neutral disconnect use case

• Compliance with WELMEC/OIML recommendations

• Memory and peripheral protection

• Hardware tamper detect with time stamping

• Low-power RTC, battery backup with tamper memory

Core

• Arm^®Cortex^®-M0+ core up to 75 MHz

Memories

• Up to 512 KB program flash memory

• Up to 64 KB SRAM

• Metering specific Memory Mapped Arithmetic Unit

(MMAU)

Operating Characteristics

Clocks

• Voltage range: 1.71 to 3.6 V (without AFE)

• Voltage range: 2.7 to 3.6 V (with AFE)

• Temperature range (ambient): –40 to 105 °C

• 75 MHz high-accuracy internal reference clock

• 32 kHz, and 4 MHz internal reference clock

• 1 kHz LPO clock

Low power features

• 32.768 kHz crystal oscillator in iRTC power domain

• 1 MHz to 32 MHz crystal oscillator

• FLL and PLL

• 13 power modes to provide power optimization

based on application requirements

• 8.82 mA @ 75 MHz run current

• Less than 220 μA very low power run current

• 6.05 μA very low power stop current

• Down to 261 nA deep sleep current

• V_BATdomain current < 1 μA with iRTC operational

• Low-power boot with less than 2.33 mA peak

current

System peripherals

• Memory Protection Unit (MPU)

• 4-channel DMA controller

• Watchdog and EWM

• Low-leakage Wakeup Unit (LLWU)

• SWD debug interface and Micro Trace Buffer (MTB)

• Bit Manipulation Engine (BME)

• Inter-peripheral Crossbar Switch (XBAR)

Communication interfaces

• 16-bit SPI modules

Analog Modules

• Low-power UART module

• UART module complying with ISO7816-3

• Basic UART module

• 4 AFE channels (4× 24-bit ƩΔ ADCs with PGA)

• 16-channel 16-bit SAR ADC with 4 result registers

• High-speed analog comparator containing a 6-bit DAC

and programmable reference input

• I²C with SMBus

• Internal 1.2 V reference voltage 10–15 ppm/℃

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Timers

• Quad Timer (QTMR)

Security and integrity modules

• Memory Mapped Cryptographic Acceleration Unit

(MMCAU) for AES encryption

• Random Number Generator (RNGA), complying

with NIST: SP800-90

• Programmable Cyclic Redundancy Check (PCRC)

• 80-bit unique identification number per chip

• Periodic Interrupt Timer (PIT)

• Low Power Timer (LPTMR)

• Programmable Delay Block (PDB)

• Independent Real Time Clock (iRTC)

Human-machine interface

• Up to 4×60 (8×56, 6×58) segment LCD controller

operating in all low-power modes

• General purpose input/output (GPIO)

The following figure shows the functional modules in the chip.

Accessed by Micro Transfer Buffer (MTB) for trace

MMAU

TCU

MMCAU

Serial

Wire

Serial

SRAM

(64 KB)

S1

S0

Wire

MTB

Debug

MPU

BME

M0

(part of PPB)

Flash

Controller

Flash

(512 KB)

Interrupt

from

Modules

IOPORT

(part of PPB)

NVIC

Port P0

Port P1

Arm ^®Cortex^®

M0+ Core

AIPS

(AHB to IPS)

GPIO

Pins

eGPIO

(dual port)

S2

Multiple

DMA

MUX

4-ch

DMA

Requests

from

M2

IPS Bus

Modules

Single Ended

Channels

SAR

ADC

AHB

Crossbar

Switch

Digital

I/Os

PIT

x2

PCRC

I2C

x2

XBAR

SMC

PDB

RNGA

Comparator

Inputs

CMP

x3

LCD

Pins

WDOG

EWM

AFE

Modulator

Clock

QTMR

SIM

SLCD

UART

x4,

LPUART

Dec

Filter

x4

MCG

Digital

I/Os

LPTMR

x2

CLK

GEN

LLWU

PMC

VREF

PLL

IRC

4 MHz

Digital

I/Os

OSC

MHz

OSC

32k

RTC

POR

SD ADC x4

+ PGA x4

SPI

x3

IRTC

IRC

32 kHz

FLL

Refer Clocking

Chapter for more

detailed diagram

on MCG

TAMPER

Core, System and

Flash Clocks

SD ADC Channels

Analog Front End

x4

Fine Compensation Clock

Modules in

VDDA Domain

Modules in

VBAT Domain

Modules in

VDD Domain

Figure 1. Functional block diagram

2

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Ordering Information

Part Number ¹

Memory

ADC

Channels

Maximum

number of

GPIOs

Security

SLCD

Package

Type

Packaging

Type

Flash SRAM

(KB)

MKM35Z256VLL

7

256

64

12

16

12

16

12

16

12

16

72

99

72

99

72

99

72

99

CRC, MMCAU,

RNG

Yes

LQFP 100

LQFP 144

LQFP 100

LQFP 144

LQFP 100

LQFP 144

LQFP 100

LQFP 144

Tray

Reel

Tray

Reel

MKM35Z256VLQ

7

256

512

64

CRC, MMCAU,

RNG

MKM35Z256VLL

7R

CRC, MMCAU,

RNG

MKM35Z256VLQ

7R

CRC, MMCAU,

RNG

MKM35Z512VLL

7

CRC, MMCAU,

RNG

MKM35Z512VLQ

7

CRC, MMCAU,

RNG

MKM35Z512VLL

7R

CRC, MMCAU,

RNG

MKM35Z512VLQ

7R

CRC, MMCAU,

RNG

1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.

Related Resources

Type

Selector

Guide

Description

Resource

The NXP Solution Advisor is a web-based tool that features interactive Solution Advisor

application wizards and a dynamic product selector.

Product Brief The Product Brief contains concise overview/summary information to

KM3xPB ¹

enable quick evaluation of a device for design suitability.

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

KM35P144M75SF0RM

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

This document:

KM35P144M75SF0

Chip Errata

The chip mask set Errata provides additional or corrective information

for a particular device mask set.

KINETIS_M_P90A

Package

Drawing

Package dimensions are provided in package drawings.

100-LQFP: 98ASS23308W ¹

144-LQFP: 98ASS23177W ¹

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

3

NXP Semiconductors

Table of Contents

1 Ratings....................................................................................5

3.4.3 Voltage reference electrical specifications.......... 30

3.4.4 AFE electrical specifications................................31

3.5 Timers..............................................................................35

3.6 Communication interfaces............................................... 35

3.6.1 I2C switching specifications.................................35

3.6.2 UART switching specifications............................ 36

3.6.3 SPI switching specifications................................ 36

3.7 Human-Machine Interfaces (HMI)....................................40

3.7.1 LCD electrical characteristics.............................. 40

4 Dimensions............................................................................. 42

4.1 Obtaining package dimensions....................................... 42

5 Pinout......................................................................................42

5.1 KM35 Signal multiplexing and pin assignments.............. 42

5.2 KM35 Pinouts.................................................................. 50

6 Ordering parts......................................................................... 51

6.1 Determining valid orderable parts....................................51

7 Part identification.....................................................................52

7.1 Description.......................................................................52

7.2 Format............................................................................. 52

7.3 Fields............................................................................... 52

7.4 Example...........................................................................53

8 Terminology and guidelines.................................................... 53

8.1 Definition: Operating requirement....................................53

8.2 Definition: Operating behavior......................................... 53

8.3 Definition: Attribute.......................................................... 54

8.4 Definition: Rating............................................................. 54

8.5 Result of exceeding a rating............................................ 55

8.6 Relationship between ratings and operating

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 6

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................6

2.2.1 Voltage and current operating requirements....... 6

2.2.2 LVD and POR operating requirements................7

2.2.3 Voltage and current operating behaviors.............8

2.2.4 Power mode transition operating behaviors........ 9

2.2.5 Power consumption operating behaviors............ 10

2.2.6 Designing with radiated emissions in mind..........12

2.2.7 Capacitance attributes.........................................12

2.3 Switching specifications...................................................12

2.3.1 Device clock specifications..................................12

2.3.2 General switching specifications......................... 13

2.4 Thermal specifications.....................................................14

2.4.1 Thermal operating requirements......................... 14

2.4.2 Thermal attributes................................................14

3 Peripheral operating requirements and behaviors.................. 14

3.1 Core modules.................................................................. 14

3.1.1 Single Wire Debug (SWD)...................................14

3.1.2 Analog Front End (AFE)...................................... 15

3.2 Clock modules................................................................. 16

3.2.1 MCG specifications..............................................16

3.2.2 Oscillator electrical specifications........................18

3.2.3 32 kHz oscillator electrical characteristics...........21

3.3 Memories and memory interfaces................................... 23

3.3.1 Flash electrical specifications..............................23

3.4 Analog............................................................................. 24

3.4.1 ADC electrical specifications............................... 24

3.4.2 CMP and 6-bit DAC electrical specifications....... 28

requirements....................................................................55

8.7 Guidelines for ratings and operating requirements..........55

8.8 Definition: Typical value...................................................56

8.9 Typical value conditions.................................................. 57

9 Revision History...................................................................... 57

4

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Ratings

1 Ratings

1.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

V_HBM

Electrostatic discharge voltage, human body model

(All pins except RESET pin)

–4000

+4000

V

Electrostatic discharge voltage, human body model

(RESET pin only)

–2500

–750

–500

–100

+2500

+750

+500

+100

V

1

V_CDM

I_LAT

Electrostatic discharge voltage, charged-device

model (for corner pins)

Electrostatic discharge voltage, charged-device

model

V

2

Latch-up current at ambient temperature of 105 °C

mA

1. Determined according to JEDEC Standard JS-001-2014, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JS-001-2014, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

5

NXP Semiconductors

General

1.4 Voltage and current operating ratings

Symbol

V_DD

Description

Min.

–0.3

–25

Max.

3.6

Unit

V

Digital supply voltage

V_DIO

Digital input voltage (except RESET, EXTAL, and XTAL)

V_DD+ 0.3

V_BAT+ 0.3

V_DD+ 0.3

25

V

V_DTamper

V_AIO

Tamper input voltage

Analog¹, RESET, EXTAL, and XTAL input voltage

V

I_D

Instantaneous maximum current single pin limit (applies to

all port pins)

mA

V_DDA

V_BAT

Analog supply voltage

V_DD– 0.3

–0.3

V_DD+ 0.3

3.6

V

RTC battery supply voltage

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

6

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

General

Notes

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

Description

Min.

2.7

Max.

3.6

0.1

3.6

Unit

V

V_DD

Supply voltage when AFE is operational

Supply voltage when AFE is NOT operational

Analog supply voltage

1.71

2.7

V

V_DDA

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

–0.1

1.71

V

V_BAT

V_IH

RTC battery supply voltage

Input high voltage

V

1

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICDIO

Input hysteresis

0.06 × V_DD

–5

—

V

Digital pin negative DC injection current — single pin

• V_IN< V_SS–0.3 V

mA

I_ICAIO

Analog², EXTAL, and XTAL pin DC injection current

— single pin

mA

–3

—

• V_IN< V_SS–0.3 V (Negative current injection)

• V_IN> V_DD+0.3 V (Positive current injection)

+3

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

–25

—

mA

V

• Negative current injection

• Positive current injection

+25

V_RFVBATV_BATvoltage required to retain the VBAT register file V_{POR_VBAT}

—

1. V_BATalways needs to be there for the chip to be operational.

2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2.2.2 LVD and POR operating requirements

Table 2. V_DDsupply LVD and POR operating requirements

Symbol Description

V_PORFalling VDD POR detect voltage

Min.

Typ.

Max.

Unit

Notes

0.8

1.1

1.5

V

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

7

NXP Semiconductors

General

Table 2. V_DDsupply LVD and POR operating requirements (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

Table 3. VBAT power operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_{POR_VBAT}Falling VBAT supply POR detect voltage

0.8

1.1

1.5

V

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — low-drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= 2.5 mA

V_DD– 0.5

—

V

I_OHT

Output high current total for all ports

—

100

mA

Table continues on the next page...

8

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

General

Notes

Table 4. Voltage and current operating behaviors (continued)

Symbol

Description

Min.

Max.

Unit

V_OL

Output low voltage — low-drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 2.5 mA

—

0.5

V

I_OLT

I_OZ

Output low current total for all ports

Hi-Z (off-state) leakage current (per pin)

Internal pull-up resistors

—

30

100

1

mA

μA

kΩ

R_PU

R_PD

60

1

2

Internal pull-down resistors

1. Measured at V_input= V_SS

.

2. Measured at V_input= V_DD

.

2.2.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 75 MHz

• Bus clock = 25 MHz

• Flash clock = 25 MHz

• Temperature: −40 °C, 25 °C, and 105 °C

• V_DD: 1.71 V, 3.3 V, and 3.6 V

Table 5. Power mode transition operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_PORAfter a POR event, amount of time from the

563

659

μs

1

point V_DDreaches 1.71 V to execute the first

instruction across the operating temperature

range of the chip.

—

370

270

5

382

275

6

μs

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS2 → RUN

• VLLS3 → RUN

• VLPS → RUN

• STOP → RUN

5

6

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

9

NXP Semiconductors

General

1. Normal boot (FTFA_OPT[LPBOOT]=1)

2.2.5 Power consumption operating behaviors

NOTE

The maximum (Max.) values stated in the following table

represent characterized results equivalent to the mean plus

three times the standard deviation (mean + 3×sigma).

Table 6. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_RUN}Run mode current — all peripheral clocks

disabled, code executing from flash

—

8.82

8.80

9.19

9.15

9.13

9.59

mA

• @ 3.0 V

• 25 °C

• –40 °C

• 105 °C

I_{DD_RUN}Run mode current — all peripheral clocks

enabled, code executing from flash

2

—

12.38

12.32

12.67

12.83

12.76

13.1

mA

• @ 3.0 V

• 25 °C

• –40 °C

• 105 °C

I_{DD_WAIT}Wait mode high frequency current at 3.0 V— all

2

peripheral clocks disabled and Flash is not in

low-power

• 25 °C

—

5.78

5.76

6.34

5.90

5.88

6.52

mA

• –40 °C

• 105 °C

I_{DD_WAIT}Wait mode high frequency current at 3.0 V— all

peripheral clocks disabled and Flash disabled

(put in low-power)

• 25 °C

—

4.56

4.98

4.6

mA

4.68

5.15

• –40 °C

• 105 °C

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

3

4

peripheral clocks disabled

• 25 °C

—

212

550

500

470

900

μA

• –40 °C

• 105 °C

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

• 25 °C

—

343

327

638

530

507

μA

• –40 °C

• 105 °C

1000

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

10

NXP Semiconductors

General

Table 6. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V — all

5

peripheral clocks disabled

• 25 °C

—

133

132

475

350

330

800

μA

• –40 °C

• 105 °C

I_{DD_STOP}Stop mode current at 3.0 V

• 25 °C

• –40 °C

• 105 °C

—

406

386

792

730

700

898

μA

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

• 25 °C

• –40 °C

• 105 °C

—

6.05

2.68

347

46

44

μA

700

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

• 25 °C

• –40 °C

• 105 °C

—

2.78

2.16

61.9

3.86

3.85

μA

85.0

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

• 25 °C

• –40 °C

• 105 °C

—

2.45

2.10

40.2

3.06

3.04

59.5

μA

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

• 25 °C

• –40 °C

• 105 °C

—

1.20

1.07

30.8

2.14

1.84

38.8

μA

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

—

0.261

0.222

29.1

0.67

0.64

38.0

μA

• 25 °C

• –40 °C

• 105 °C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

—

0.559

0.494

29.5

0.790

0.784

38.4

μA

• 25 °C

• –40 °C

• 105 °C

I_{DD_VBAT}Average current with RTC and 32 kHz disabled

at 3.0 V and VDD is OFF

• 25 °C

—

0.243

0.143

6.05

1.00

0.95

15

μA

• –40 °C

• 105 °C

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

11

NXP Semiconductors

General

Table 6. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VBAT}Average current when VDD is OFF and LFSR

and Tamper clocks set to 2 Hz.

6, 7

—

1.42

1.24

8.04

3.00

2.96

16.0

μA

• @ 3.0 V

• 25 °C

• –40 °C

• 105 °C

1. See all related analog peripheral specifications for I_DDA

.

2. 75 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FBE mode. All

peripheral clocks disabled.

3. 2 MHz core/system clock, and 1 MHz bus/flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.

Code executing while (1) loop from flash.

4. 2 MHz core/system clock, and 1 MHz bus/flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but

peripherals are not in active operation. Code executing while (1) loop from flash.

5. 2 MHz core/system clock, and 1 MHz bus/flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.

No flash accesses; some activity on DMA & RAM assumed.

6. Includes 32 kHz oscillator current and RTC operation.

7. An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in

all conditions. There is no internal power switch in RTC.

2.2.6 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com.

2. Perform a keyword search for “EMC design.”

2.2.7 Capacitance attributes

Table 7. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

Input capacitance: fast digital pins

7

9

C_{IN_D}

—

pF

C_{IN_D_io60}

—

pF

2.3 Switching specifications

12

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

General

Notes

2.3.1 Device clock specifications

Table 8. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Normal run mode

f_SYS

f_BUS

f_FLASH

f_AFE

System and core clock

Bus clock

—

75

25

6.5

MHz

Flash clock

AFE Modulator clock

VLPR mode¹

f_SYS

f_BUS

f_FLASH

f_AFE

System and core clock

Bus clock

—

4

1

MHz

Flash clock

AFE Modulator clock²

1

1.6

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2. AFE working in low-power mode.

2.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and I²C signals.

Table 9. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Asynchronous path

16

—

ns

External reset pulse width (digital glitch filter

disabled)

100

ns

2

Port rise and fall time

• Slew disabled

• 1.71 ≤ V_DD≤ 2.7 V

• 2.7 ≤ V_DD≤ 3.6 V

• Slew enabled

—

8

5

ns

• 1.71 ≤ V_DD≤ 2.7 V

• 2.7 ≤ V_DD≤ 3.6 V

—

27

16

ns

1. The greater synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

13

NXP Semiconductors

Peripheral operating requirements and behaviors

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 10. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.¹

125

Unit

°C

Die junction temperature

Ambient temperature

T_A

105

°C

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis:

T_J= T_A+ R_θJA× chip power dissipation.

2.4.2 Thermal attributes

Rating

Board Type¹

Symbol

100 LQFP

144 LQFP

Unit

Junction to

JESD51-7, 2s2p

R_θJA

48.6

41.7

°C/W

Ambient Thermal

Resistance²

Junction-to-Top of JESD51-7, 2s2p

Package Thermal

Ψ_JT

0.52

0.63

Characterization

Parameter ²

1. Thermal test board meets JEDEC specification for this package (JESD51-7).

2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report

is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is

not meant to predict the performance of a package in an application-specific environment.

3 Peripheral operating requirements and behaviors

3.1 Core modules

14

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Peripheral operating requirements and behaviors

3.1.1 Single Wire Debug (SWD)

Table 11. SWD switching characteristics at 2.7 V (2.7–3.6 V)

Symbol

SWD CLK

Description

Value

Unit

Notes

Frequency of SWD

operation

20

MHz

Inputs, t_SUI

inputs, t_HI

Data setup time

Data hold time

5

ns

1

0

after clock edge, t_DVOData valid Time

t_HOData Valid Hold

32

0

1. Input transition assumed = 1 ns. Output transition assumed = 50 pF.

Table 12. Switching characteristics at 1.7 V (1.7–3.6 V)

Symbol

SWD CLK

Description

Value

Unit

Notes

Frequency of SWD

operation

18

MHz

Inputs, t_SUI

inputs, t_HI

Data setup time

Data hold time

4.7

0

ns

1

2

1

after clock edge, t_DVOData valid Time

t_HOData Valid Hold

49.4

0

1. Input transition assumed = 1 ns. Output transition assumed = 50 pF.

2. Frequency of SWD clock (18 MHz) is applicable only in case the input setup time of the device outside is not more

than 6.15 ns, else the frequency of SWD clock would need to be lowered.

3.1.2 Analog Front End (AFE)

AFE switching characteristics at (2.7 V–3.6 V)

Case 1: Clock is coming In and Data is also coming In (XBAR ports timed with

respect to AFE clock defined at pad PTB7, PTE3, and PTK4).

Table 13. AFE switching characteristics (2.7 V–3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 10

MHz

ns

Inputs, t_SUI

inputs, t_HI

Data setup time

Data hold time

5

0

1

ns

1. Input Transition: 1 ns. Output Load: 50 pF.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

15

NXP Semiconductors

Peripheral operating requirements and behaviors

Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to

generated clock defined at the XBAR out ports).

Table 14. AFE switching characteristics (2.7 V–3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 6.2

MHz

ns

Inputs, t_SUI

inputs, t_HI

Data setup time

Data hold time

36

0

1

ns

1. Input Transition: 1 ns. Output Load: 50 pF.

AFE switching characteristics at (1.7 V–3.6 V)

Case 1: Clock is coming In and Data is also coming In (XBAR ports timed with respect

to AFE clock defined at pad PTB7, PTE3, and PTK4).

Table 15. AFE switching characteristics (1.7 V–3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 13

MHz

ns

Inputs, t_SUI

inputs, t_HI

Data setup time

Data hold time

30

5

1

ns

1. Input Transition: 1 ns. Output Load: 50 pF.

Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to

generated clock defined at XBAR out ports).

Table 16. AFE switching characteristics (1.7 V–3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 6.5

MHz

ns

Inputs, t_SUI

inputs, t_HI

Data setup time

Data hold time

36

0

1

ns

1. Input Transition: 1 ns. Output Load: 50 pF.

3.2 Clock modules

16

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Peripheral operating requirements and behaviors

3.2.1 MCG specifications

Table 17. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}

Internal reference frequency (slow clock) —

—

32.768

—

kHz

factory trimmed at nominal V_DDand 25 °C

Δf_{ints_t}

Total deviation of internal reference

frequency (slow clock) over voltage and

temperature

—

-2

+0.5/-0.7

—

%

Δf_{ints_t}

Total deviation of internal reference

frequency (slow clock) over fixed voltage

and full operating temperature range

+2

f_{ints_t}

Internal reference frequency (slow clock) —

user trimmed

31.25

—

39.0625

0.6

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature

— using SCTRIM and SCFTRIM

0.3

%f_dco

Δf_{dco_t}

Total deviation of trimmed average DCO

output frequency over voltage and

temperature

—

+0.5/-0.7

0.4

%f_dco

1

Δf_{dco_t}

Total deviation of trimmed average DCO

output frequency over fixed voltage and

temperature range of 0–70 °C

—

f_{intf_ft}

Internal reference frequency (fast clock) —

factory trimmed at nominal V_DDand 25 °C

—

4

—

MHz

%

Δf_{intf_t}

Total deviation of internal reference

frequency (fast clock) over voltage and

temperature — factory trimmed at nominal

V_DDand 25 °C

+1/-2

f_{intf_t}

Internal reference frequency (fast clock) —

user trimmed at nominal V_DDand 25 °C

3

—

5

MHz

kHz

f_{loc_low}

f_{loc_high}

Loss of external clock minimum frequency

— RANGE = 00

(3/5) x

f_{ints_t}

—

Loss of external clock minimum frequency

— RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

FLL

f_dco

DCO output

frequency

range

Low-range (DRS=00)

640 × f_{ints_t}

20

40

60

80

—

20.97

41.94

62.91

83.89

23.99

22

45

67

90

—

MHz

2, 3

Mid-range (DRS=01)

1280 × f_{ints_t}

Mid-high range (DRS=10)

1920 × f_{ints_t}

High-range (DRS=11)

2560 × f_{ints_t}

f_{dco_t_DMX32}DCO output

frequency

Low-range (DRS=00)

732 × f_{ints_t}

4, 5, 6

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

17

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 17. MCG specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Mid-range (DRS=01)

1464 × f_{ints_t}

—

47.97

—

MHz

Mid-high range (DRS=10)

2197 × f_{ints_t}

—

71.99

95.98

—

MHz

High-range (DRS=11)

2929 × f_{ints_t}

J_{cyc_fll}

FLL period jitter

—

70

—

140

1

ps

7

8

t_{fll_acquire}FLL target frequency acquisition time

ms

PLL

11.71875 12.288 14.6484375

f_vco

I_pll

VCO operating frequency

MHz

µA

PLL operating current

• IO 3.3 V current

—

300

100

—

39.0625

700

• Max core voltage current

f_{pll_ref}

PLL reference frequency range

PLL period jitter (RMS)

• f_vco= 12 MHz

31.25

32.768

kHz

ps

J_{cyc_pll}

D_lock

D_unl

Lock entry frequency tolerance

Lock exit frequency tolerance

Lock detector detection time

1.49

4.47

—

2.98

5.97

150 × 10^-6

+ 1075(1/

%

s

t_{pll_lock}

f_{pll_ref}

)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

3. Chip maximum freq is 75 MHz, so high-range of DCO cannot be used and should not be configured.

4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

6. Chip max freq is 75 MHz, so High-range of DCO cannot be used and should not be configured.

7. This specification is based on standard deviation (RMS) of period or frequency.

8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

3.2.2 Oscillator electrical specifications

18

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Peripheral operating requirements and behaviors

3.2.2.1 Oscillator DC electrical specifications

Table 18. Oscillator DC electrical specifications

Symbol Description

V_DDSupply voltage

Min.

1.71

Typ.

Max.

3.6

Unit

Notes

—

V

I_DDOSCSupply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 1 MHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSCSupply current — high-gain mode (HGO=1)

1

• 32 kHz

—

25

300

400

500

2.5

3

—

μA

• 1 MHz

• 4 MHz

μA

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-

power mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

• 1 MHz resonator

• 2 MHz resonator

—

6.6

3.3

—

kΩ

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

19

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 18. Oscillator DC electrical specifications (continued)

Symbol Description

• 4 MHz resonator

Min.

Typ.

Max.

Unit

Notes

—

0

—

kΩ

• 8 MHz resonator

• 16 MHz resonator

• 20 MHz resonator

• 32 MHz resonator

—

0

—

kΩ

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

—

0.6

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation.

3. C_xand C_ycan be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other device.

3.2.2.2 Oscillator frequency specifications

Table 19. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

1

8

—

8

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

48

60

—

MHz

%

1, 2

3, 4

50

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

ms

Table continues on the next page...

20

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 19. Oscillator frequency specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Crystal startup time — 8 MHz high-frequency

—

0.6

—

ms

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

register being set.

3.2.3 32 kHz oscillator electrical characteristics

3.2.3.1 32 kHz Oscillator Maximum Ratings

NOTE

Functional operating conditions are given in DC Electrical

Specifications. Absolute Maximum Ratings are stress ratings

only, and functional operation at the maxima is not

guaranteed. Stress beyond those listed may affect device

reliability or cause permanent damage to the device.

Table 20. 32 kHz oscillator absolute maximum ratings

Num

Symbol

Description

Min.

Max.

Unit

1

RTC oscillator

(A_IP_OSC_3v32k

VLP_NN_C90LP)

Module 3.3V

–0.3

3.6

V

V_DD33OSC

Analog Supply

Voltage

2

3

4

V_EXTAL

V_XTAL

T_A

EXTAL Input

Voltage

–0.3

–40

3.6

135

V

XTAL Input

Voltage

Operating

°C

Temperature

Range (Packaged)

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

21

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 20. 32 kHz oscillator absolute maximum ratings (continued)

Num

Symbol

Description

Min.

Max.

Unit

5

T_J

Operating

–40

135

°C

Temperature

Range (Junction)

6

T_stg

Storage

–65

150

°C

Temperature

Range

3.2.3.2 32 kHz oscillator DC electrical specifications

Table 21. 32 kHz oscillator DC electrical specifications

Symbol

V_BAT

R_F

Description

Min.

1.71

—

Typ.

—

Max.

3.6

—

Unit

V

Supply voltage

Internal feedback resistor

100

5

MΩ

pF

C_para

Parasitical capacitance of EXTAL32 and

XTAL32

—

7

1

V_pp

Peak-to-peak amplitude of oscillation

—

0.6

—

V

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

3.2.3.3 32 kHz oscillator frequency specifications

Table 22. 32 kHz Crystal and Oscillator Specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

f_{osc_lo}

Crystal

—

32.768

—

kHz

frequency

T_A

Operating

temperature

-40

—

105

500

°C

1

Total crystal

frequency

tolerance

-500

ppm

2,3

C_L

Load

capacitance

—

12.5

—

pF

2

ESR

Equivalent

series

80

kOhms

resistance

t_start

Crystal start-up

time

—

1000

32.768

—

ms

kHz

V

4

5

6

f_{ec_extal32}

v_{ec_xtal32}

External input

clock frequency

—

External input

0.7

V_DD

clock amplitude

22

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Peripheral operating requirements and behaviors

1. Full temperature range of this device. A reduced range can be chosen to meet application needs.

2. Recommended crystal specification.

3. Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.

4. Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.

5. External oscillator connected to EXTAL32K. XTAL32K must be unconnected.

6. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the

applied clock must be within the range of VSS to VDD.

3.3 Memories and memory interfaces

3.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.3.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps

are active and do not include command overhead.

Table 23. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

13

Max.

18

Unit

μs

Notes

t_hvpgm4Longword Program high-voltage time

t_hversscrSector Erase high-voltage time

—

1

—

113

ms

t_hversall

Erase All high-voltage time

—

1

1. Maximum time based on expectations at cycling end-of-life.

3.3.1.2 Flash timing specifications — commands

Table 24. Flash command timing specifications

Symbol Description

Min.

—

Typ.

—

Max.

45

Unit

μs

Notes

t_pgmchkProgram Check execution time

1

t_rdrsrc

t_pgm4

t_ersscr

t_rd1all

t_rdonce

Read Resource execution time

Program Longword execution time

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

30

μs

65

14

—

145

114

μs

—

2

ms

μs

1

—

25

—

1

t_pgmonceProgram Once execution time

65

μs

—

2

t_ersall

Erase All Blocks execution time

ms

μs

t_vfykey

Verify Backdoor Access Key execution time

—

30

1

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

23

NXP Semiconductors

Peripheral operating requirements and behaviors

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.3.1.3 Flash high voltage current behaviors

Table 25. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

3.3.1.4 Reliability specifications

Table 26. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

—

2

20

100

50 K

10 K

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T_j≤ 105 °C.

3.4 Analog

3.4.1 ADC electrical specifications

All ADC channels meet the 12-bit single-ended accuracy specifications.

3.4.1.1 16-bit ADC operating conditions

Table 27. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.71

Typ.¹

Max.

3.6

Unit

V

Notes

V_DDA

ΔV_DDA

ΔV_SSA

Supply voltage

Absolute

—

0

Delta to V_DD(V_DD– V_DDA

)

–100

+100

mV

2

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

Table continues on the next page...

24

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 27. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

V_REFH

ADC reference

voltage high

Absolute

V_DDA

V

3

V_REFL

ADC reference

voltage low

Absolute

V_SSA

V

4

V_ADIN

C_ADIN

Input voltage

V_SSA

—

8

V_DDA

10

V

Input

• 16-bit mode

pF

capacitance

• 8-bit / 10-bit / 12-bit

modes

—

4

5

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

Analog source

resistance

(external)

12-bit modes

f_ADCK< 4 MHz

5

—

f_ADCK

C_rate

ADC conversion ≤ 12-bit mode

clock frequency

1.0

2.0

—

18.0

12.0

MHz

6

7

ADC conversion 16-bit mode

clock frequency

ADC conversion ≤ 12-bit modes

rate

No ADC hardware averaging

20.000

37.037

—

818.330

461.467

kS/s

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

7

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. V_REFHis internally tied to V_DDA

4. V_REFLis internally tied to V_SSA

.

5. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

6. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

7. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

25

NXP Semiconductors

Peripheral operating requirements and behaviors

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

ZADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

leakage

ZAS

ADC SAR

ENGINE

RAS

RADIN

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 3. ADC input impedance equivalency diagram

3.4.1.2 16-bit ADC electrical characteristics

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

mA

Notes

I_{DDA_ADC}Supply current

—

3

ADC

asynchronous

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK=

1/f_ADACK

2.4

clock source

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total

unadjusted error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

+0.5

INL

Integral non-

linearity

• 12-bit modes

—

1.0

0.5

–2.7 to

+1.9

LSB⁴

5

Table continues on the next page...

26

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

–0.7 to

+0.5

• <12-bit modes

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• 12-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN

V_DDA

=

5

Quantization

error

0.5

ENOB Effective

number of bits

16-bit single-ended mode

• Avg = 32

6

bits

12.8

11.9

14.5

13.8

• Avg = 4

—

bits

12.2

11.4

13.9

13.1

—

Signal-to-noise See ENOB

plus distortion

SINAD

THD

6.02 × ENOB + 1.76

dB

Total harmonic 16-bit single-ended mode

7

dB

distortion

—

–94

—

• Avg = 32

—

–85

95

—

SFDR

Spurious free

dynamic range

16-bit single-ended mode

• Avg = 32

dB

82

78

90

E_IL

Input leakage

error

I_In× R_AS

mV

I_In=

leakage

current

(refer to

the MCU's

voltage

and

current

operating

ratings)

Temp sensor

slope

Across the full temperature range

of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

27

NXP Semiconductors

Peripheral operating requirements and behaviors

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

Averaging of 4 samples

Averaging of 32 samples

11.00

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 4. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

3.4.2 CMP and 6-bit DAC electrical specifications

Table 29. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, high-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

Output high

V_DD– 0.5

—

V

Table continues on the next page...

28

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 29. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

V_CMPOl

t_DHS

Description

Min.

—

Typ.

—

Max.

0.5

200

600

40

Unit

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

50

250

—

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

7

—

μA

LSB³

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

—

LSB

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

0.08

0.07

0.06

HYSTCTR

Setting

0.05

0.04

0.03

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 5. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

29

NXP Semiconductors

Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 6. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.4.3 Voltage reference electrical specifications

Table 30. 1.2 VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Min.

2.7 ¹

−40

Max.

3.6

Unit

V

Notes

Supply voltage

Temperature

105

°C

nF

C_L

Output load capacitance

100

2, 3

1. AFE is enabled.

2. C_Lmust be connected between VREFH and VREFL.

3. The load capacitance should not exceed 25% of the nominal specified C_Lvalue over the operating temperature range

of the device.

30

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 31. VREF full-range operating behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

VREFH

Voltage reference output with factory

trim at nominal V_DDAand temperature

= 25 °C

1.1915

1.195

1.2027

V

VREFH

Voltage reference output with —

factory trim

1.1584

—

1.2376

V

VREFH

VREFL

V_step

Voltage reference output — user trim

Voltage reference output

1.178

0.38

—

0.4

0.5

18

1.202

0.42

—

V

Voltage reference trim step

mV

V_tdrift

Temperature drift when ICOMP = 0

across full temperature range

—

ppm/ºC

Temperature drift when ICOMP = 1

across full temperature range

—

6

5

3

—

ppm/°C

1

Temperature drift when ICOMP = 1

across -40 ºC to 70 ºC

1, 2

Temperature drift when ICOMP = 1

across 0 ºC to 50 ºC

Ac

I_bg

Aging coefficient

—

–2

—

400

80

uV/yr

µA

Bandgap only current

Low-power buffer current

High-power buffer current

VREF buffer current

Load regulation

2

I_lp

0.19

0.5

2

mA

µV

I_hp

2

I_LOAD

ΔV_LOAD

3, 4

2, 5

• current = 1.0 mA

—

200

—

T_stup

Buffer startup time

—

200

20

µs

T_{chop_osc_stup}

Internal bandgap start-up delay with

chop oscilator enabled

ms

V_vdrift

Voltage drift (VREFHmax -VREFHmin

across the full voltage range)

—

0.5

—

mV

2

1. ICOMP=1 is recommended to get best temperature drift. CHOPEN bit = 1 is also recommended.

2. See the chip's Reference Manual for the appropriate settings of VREF Status and Control register.

3. 2 mA I_LOADis only achievable for above 2.7 V V_DDAcondition.

4. See the chip's Reference Manual for the appropriate settings of SIM Miscellaneous Control register.

5. Load regulation voltage is the difference between VREFH voltage with no load vs. voltage with defined load.

NOTE

Temperature drift per degree is ( (VREFHmax-VREFHmin)/

(temperature range)/VREFHmin ) in ppm/ºC.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

31

NXP Semiconductors

Peripheral operating requirements and behaviors

3.4.4 AFE electrical specifications

3.4.4.1 ΣΔ ADC + PGA specifications

Table 32. ΣΔ ADC + PGA specifications

Symbol

Description

Conditions

Min

1.5

0

Typ¹

Max

1.5

0.8

Unit

Notes

f_Nyq

Input bandwidth

Normal Mode

Low-Power Mode

1.5

kHz

1.5

V_CM

Input Common Mode

Reference

V

VIN_diff

Differential input range

Gain = 1 (PGA ON/OFF)²

Gain = 2

500

250

125

62

mV

dB

Gain = 4

Gain = 8

Gain = 16

31

Gain = 32

15

SNR

Signal to Noise Ratio

Normal Mode

90

92

• f_IN=50 Hz; gain=01, common

mode=0 V, V_pp=1000 mV (full

range diff.)

88

82

90

86

• f_IN=50 Hz; gain=02, common

mode=0 V, V_pp= 500 mV

(differential ended)

• f_IN=50 Hz; gain=04, common

mode=0 V, V_pp= 250 mV

(differential ended)

• f_IN=50 Hz; gain=08, common

mode=0 V, V_pp= 125 mV

(differential ended)

• f_IN=50 Hz; gain=16, common

mode=0 V, V_pp= 62 mV

(differential ended)

76

70

82

78

• f_IN=50 Hz; gain=32, common

mode=0 V, V_pp= 31 mV

(differential ended)

64

74

Low-Power Mode

dB

82

76

82

78

• f_IN=50 Hz; gain=01, common

mode=0 V, V_pp=1000 mV (full

range diff.)

• f_IN=50 Hz; gain=02, common

mode=0 V, V_pp= 500 mV

(differential ended)

• f_IN=50 Hz; gain=04, common

mode=0 V, V_pp= 250 mV

(differential ended )

• f_IN=50 Hz; gain=08, common

mode=0 V, V_pp= 125 mV

(differential ended )

70

64

74

70

Table continues on the next page...

32

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 32. ΣΔ ADC + PGA specifications (continued)

Symbol

Description

Conditions

Min

Typ¹

Max

Unit

Notes

• f_IN=50 Hz; gain=16, common

58

66

mode=0 V, V_pp= 62 mV

(differential ended )

• f_IN=50 Hz; gain=32, common

mode=0 V, V_pp= 31 mV

(differential ended )

52

62

78

SINAD

Signal-to-Noise +

Distortion Ratio

Normal Mode

dB

• f_IN=50 Hz; gain=01, common

mode=0 V, V_pp=500 mV

(differential ended)

Low-Power Mode

dB

74

• f_IN=50 Hz; gain=01, common

mode=0 V, V_pp=500 mV

(differential ended)

CMMR

E_offset

Common Mode Rejection

Ratio

• f_IN=50 Hz; gain=01, common

mode=0 V, Vid=100 mV

• f_IN=50 Hz; gain=32, common

mode=0 V, V_id=100 mV

70

Offset Error

Gain=01, V_pp=1000 mV (full range

diff.)

5

mV

ΔOffset_TempOffset Temperature Drift ³Gain=01, V_pp=1000 mV (full range

25 ppm/℃

75 ppm/℃

diff.)

ΔGain_TempGain Temperature Drift -

Gain error caused by

• Gain=01, V_pp=500 mV

(differential ended)

temperature drifts ⁴

• Gain=32, V_pp=15 mV

(differential ended)

PSRR_ACAC Power Supply

Rejection Ratio

Gain=01, VCC = 3 V 100 mV, f_IN

= 50 Hz

60

dB

XT

Crosstalk (with the input

of the affected channel

grounded)

Gain=01, V_id= 500 mV, f_IN= 50 Hz

-100

dB

f_MCLK

Modulator Clock

Frequency Range

Normal Mode

0.03

6.5

1.6

2.6

MHz

mA

Low-Power Mode

I_{DDA_PGA}Current consumption by

PGA (each channel)

Normal Mode (f_MCLK= 6.144 MHz,

OSR= 2048)

5

0

Low-Power Mode (f_MCLK= 0.768

MHz, OSR= 256)

I_{DDA_ADC}Current Consumption by Normal Mode (f_MCLK= 6.144 MHz,

1.4

0.5

mA

ADC (each channel)

OSR= 2048)

Low-Power Mode (f_MCLK= 0.768

MHz, OSR= 256)

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_MCLK= 6.144 MHz, OSR = 2048 for Normal mode and f_MCLK

=

768 kHz, OSR = 256 for low-power mode unless otherwise stated. All values are for reference only and are not tested

in production.

2. The full-scale input range in single-ended mode is 0.5 V_pp.

3. Represents combined offset temperature drift of the PGA, SD ADC, and Internal 1.2 VREF blocks; Defined by shorting

both differential inputs to ground.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

33

NXP Semiconductors

Peripheral operating requirements and behaviors

4. Represents combined gain temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks.

5. PGA is disabled in low-power modes.

3.4.4.2 ΣΔ ADC Standalone specifications

Table 33. ΣΔ ADC standalone specifications

Symbol

Description

Conditions

Min

1.5

0

Typ¹

Max

1.5

0.8

Unit

Notes

f_Nyq

Input bandwidth

Normal Mode

Low-Power Mode

1.5

kHz

1.5

V_CM

Input Common Mode

Reference

V

VIN_diff

Input range

Differential

500

250

mV

dB

Single-Ended

Normal Mode

SNR

Signal to Noise Ratio

88

76

90

78

• f_IN=50 Hz; common mode=0

V, V_pp= 500 mV (differential

ended )

• f_IN=50 Hz; common mode=0

V, V_pp= 500 mV (full range

se.)

Low-Power Mode

• f_IN=50 Hz; common mode=0

V, V_pp=500 mV (diff.)

• f_IN=50 Hz; common mode=0

V, V_pp=500 mV (full range

se.)

ΔGain_TempGain Temperate Drift -

Gain error caused by

• Gain bypassed V_pp= 500 mV

(differential)

• PGA bypassed V_pp= 500 mV

(differential), V_CM= 0 V

55

30

ppm/℃

temperature drifts ²

ΔOffset_TempOffset Temperate Drift -

Offset error caused by

• Gain bypassed Vpp = 500

mV (differential), V_CM= 0 V

ppm/℃

temperature drifts ³

SINAD

Signal-to-Noise +

Distortion Ratio

Normal Mode

dB

80

74

• f_IN=50 Hz; common mode=0

V, V_pp= 500 mV (diff.)

• f_IN=50 Hz; common mode=0

V, V_pp= 500 mV (full range

se.)

Low-Power Mode

• f_IN=50 Hz; common mode=0

V, V_pp=500 mV (diff.)

• f_IN=50 Hz; common mode=0

V, V_pp=500 mV (full range

se.)

CMMR

Common Mode Rejection

Ratio

• f_IN=50 Hz; common mode=0

V, V_id=100 mV

90

dB

Table continues on the next page...

34

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 33. ΣΔ ADC standalone specifications (continued)

Symbol

Description

Conditions

Min

Typ¹

Max

Unit

Notes

PSRR_ACAC Power Supply

Rejection Ratio

Gain=01, VCC = 3 V 100 mV, f_IN

= 50 Hz

60

dB

XT

Crosstalk

Gain=01, V_id= 500 mV, f_IN= 50 Hz

Normal Mode

-100

6.5

dB

f_MCLK

Modulator Clock

Frequency Range

0.03

MHz

Low-Power Mode

1.6

I_{DDA_ADC}Current Consumption by Normal Mode (f_MCLK= 6.144 MHz,

1.4

mA

ADC (each channel)

OSR= 2048)

0.5

Low-Power Mode (f_MCLK= 0.768

MHz, OSR= 256)

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_MCLK= 6.144 MHz, OSR = 2048 for Normal mode and f_MCLK

=

768 kHz, OSR = 256 for low-power mode unless otherwise stated. Typical values are for reference only and are not

tested in production.

2. Represents combined gain temperature drift of the SD ADC, and Internal 1.2 VREF blocks.

3. Represents combined offset temperature drift of the SD ADC, and Internal 1.2 VREF blocks; Defined by shorting both

differential inputs to ground.

3.4.4.3 External modulator interface

The external modulator interface on this device comprises of a Clock signal and 1-bit

data signal. Depending on the modulator device being used, the interface works as

follows:

• Clock supplied to external modulator which drives data on rising edge and the

KM35 device captures it on falling edge or next rising edge.

• Clock and data are supplied by external modulator and KM35 device can sample

it on falling edge or next rising edge.

Depending on control bit in AFE, the sampling edge is changed.

3.5 Timers

See General switching specifications.

3.6 Communication interfaces

3.6.1 I2C switching specifications

See General switching specifications.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

35

NXP Semiconductors

Peripheral operating requirements and behaviors

3.6.2 UART switching specifications

See General switching specifications.

3.6.3 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following

tables provide timing characteristics for classic SPI timing modes. See the SPI chapter

of the chip's Reference Manual for information about the modified transfer formats used

for communicating with slower peripheral devices.

All timing is shown with respect to 20% V_DDand 80% V_DDthresholds, unless noted, as

well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.

Table 34. SPI master mode timing on slew rate disabled pads

Num.

Symbol Description

Min.

Max.

Unit

Hz

Note

1

2

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

1

2

t_SPSCK

SPSCK period

2048 x

t_periph

ns

3

4

5

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

ns

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

18

0

—

ns

—

15

8

t_v

—

0

9

t_HO

t_RI

—

10

—

t_periph- 25

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. For both SPI0 and SPI1, f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

Table 35. SPI master mode timing on slew rate enabled pads

Num.

Symbol Description

f_opFrequency of operation

Min.

Max.

Unit

Note

1

f_periph/2048

f_periph/2

Hz

1

Table continues on the next page...

36

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 35. SPI master mode timing on slew rate enabled pads (continued)

Num.

Symbol Description

Min.

Max.

Unit

Note

2

t_SPSCK

SPSCK period

2 x t_periph

2048 x

t_periph

ns

2

3

4

5

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

ns

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

96

0

—

ns

—

52

8

t_v

—

0

9

t_HO

t_RI

—

10

—

t_periph- 25

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

36

ns

—

Fall time output

1. For both SPI0 and SPI1, f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

1

SS

(OUTPUT)

3

2

10

11

4

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

8

MSB IN

LSB IN

9

MOSI

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 7. SPI master mode timing (CPHA = 0)

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

37

NXP Semiconductors

Peripheral operating requirements and behaviors

1

SS

(OUTPUT)

2

10

11

4

3

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

LSB IN

MSB IN

9

8

MOSI

(OUTPUT)

2

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 8. SPI master mode timing (CPHA = 1)

Table 36. SPI slave mode timing on slew rate disabled pads

Num.

1

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Hz

Note

1

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

0

2

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

ns

2

3

1

—

t_periph

ns

—

3

4

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2.5

3.5

—

0

—

ns

7

—

ns

8

t_periph

31

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. For both SPI0 and SPI1, f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

38

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Peripheral operating requirements and behaviors

Table 37. SPI slave mode timing on slew rate enabled pads

Num.

1

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Hz

Note

1

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

0

2

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

ns

2

3

1

—

t_periph

ns

—

3

4

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2

7

—

ns

7

—

ns

8

—

0

t_periph

122

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

36

ns

—

Fall time output

1. For both SPI0 and SPI1, f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

SS

(INPUT)

2

12

13

4

SPSCK

(CPOL=0)

(INPUT)

5

3

12

13

11

SPSCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 9. SPI slave mode timing (CPHA = 0)

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

39

NXP Semiconductors

Peripheral operating requirements and behaviors

SS

(INPUT)

4

2

12

13

3

SPSCK

(CPOL=0)

(INPUT)

5

SPSCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

8

6

7

MOSI

(INPUT)

MSB IN

NOTE: Not defined

Figure 10. SPI slave mode timing (CPHA = 1)

3.7 Human-Machine Interfaces (HMI)

3.7.1 LCD electrical characteristics

Table 38. LCD electricals

Symbol Description

f_FrameLCD frame frequency

Min.

Typ.

Max.

Unit

Notes

• GCR[FFR]=0

• GCR[FFR]=1

23.3

46.6

—

73.1

Hz

146.2

C_LCD

LCD charge pump capacitance — nominal value

—

100

—

nF

pF

V

C_BYLCDLCD bypass capacitance — nominal value

1

2

3

C_Glass

V_IREG

LCD glass capacitance

V_IREG

2000

8000

• RVTRIM=0000

• RVTRIM=1000

• RVTRIM=0100

• RVTRIM=1100

• RVTRIM=0010

• RVTRIM=1010

• RVTRIM=0110

—

0.91

0.92

0.93

0.94

0.96

0.97

0.98

0.99

—

Table continues on the next page...

40

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Peripheral operating requirements and behaviors

Table 38. LCD electricals (continued)

Symbol Description

• RVTRIM=1110

Min.

Typ.

Max.

Unit

Notes

—

1.01

—

• RVTRIM=0001

• RVTRIM=1001

• RVTRIM=0101

• RVTRIM=1101

• RVTRIM=0011

• RVTRIM=1011

• RVTRIM=0111

• RVTRIM=1111

—

1.02

1.03

1.05

1.06

1.07

1.08

1.09

—

Δ_RTRIMV_IREGTRIM resolution

—

1

3.0

—

% V_IREG

µA

I_VIREG

I_RBIAS

V_IREGcurrent adder — RVEN = 1

RBIAS current adder

• LADJ = 10 or 11 — High load (LCD glass

capacitance ≤ 8000 pF)

—

10

1

—

µA

• LADJ = 00 or 01 — Low load (LCD glass

capacitance ≤ 2000 pF)

R_RBIAS

RBIAS resistor values

• LADJ = 10 or 11 — High load (LCD glass

capacitance ≤ 8000 pF)

—

0.28

2.98

—

MΩ

• LADJ = 00 or 01 — Low load (LCD glass

capacitance ≤ 2000 pF)

VLL1

VLL2

VLL3

VLL1

VLL2

VLL3

VLL1 voltage

VLL2 voltage

VLL3 voltage

VLL1 voltage

VLL2 voltage

VLL3 voltage

—

V_IREG

2 x V_IREG

3 x V_IREG

V_DDA/ 3

V_DDA/ 1.5

V_DDA

V

4

5

1. The actual value used could vary with tolerance.

2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller

chapter within the device's reference manual.

3. V_IREGmaximum should never be externally driven to any level other than V_DD- 0.15 V

4. VLL1, VLL2 and VLL3 are a function of V_IREGonly when the regulator is enabled (GCR[RVEN]=1) and the charge

pump is enabled (GCR[CPSEL]=1).

5. VLL1, VLL2 and VLL3 are a function of V_DDAonly under either of the following conditions:

• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = V_DDA

through the internal power switch (GCR[VSUPPLY]=0).

• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is

connected to V_DDAexternally (GCR[VSUPPLY]=1).

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

41

NXP Semiconductors

Dimensions

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

100-pin LQFP

Then use this document number

98ASS23308W

98ASS23177W

144-pin LQFP

5 Pinout

5.1 KM35 Signal multiplexing and pin assignments

NOTE

If use SLCD Fault Detection function, then corresponding

SLCD functions at ALT6 or ALT7 need to be enabled.

Otherwise don’t need to enable them.

Table 39. Signal Multiplexing and Pin Assignments

100

LQFP

144

LQFP

Name

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

—

143

PTI4

LCD_P4 LCD_P4

PTI4

—

LCD_P4

4

—

144

1

NC

—

2

NC

—

3

PTI5

LCD_P4 LCD_P4

PTI5

LCD_P4

5

1

4

PTA0/ LCD_P2 LCD_P2 PTA0/

—

LCD_P2

3

LLWU_P

16

3

LLWU_P

16

Table continues on the next page...

42

NXP Semiconductors

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

Pinout

ALT7

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

LQFP

Name

2

—

3

5

PTA1 LCD_P2 LCD_P2 PTA1

—

LCD_P2

4

6

PTI6

PTI7

LCD_P4 LCD_P4

PTI6

PTI7

UART2_

RX

—

LCD_P4

6

7

LCD_P4 LCD_P4

UART2_

TX

—

LCD_P4

7

8

PTA2 LCD_P2 LCD_P2 PTA2

—

LCD_P2

5

4

9

PTA3 LCD_P2 LCD_P2 PTA3

—

LCD_P2

6

5

10

PTA4/

LLWU_P

15

NMI_b LCD_P2 PTA4/

—

LCD_P2 NMI_b

7

LLWU_P

15

6

7

11

12

PTA5 LCD_P2 LCD_P2 PTA5

CMP0_

OUT

—

LCD_P2

8

PTA6/ LCD_P2 LCD_P2 PTA6/ XBAR_I

LCD_P2

9

LLWU_P

14

9

LLWU_P

14

N0

8

13

14

15

16

17

PTA7 LCD_P3 LCD_P3 PTA7 XBAR_O

—

LCD_P3

0

UT0

—

9

PTJ0

PTJ1

LCD_P4 LCD_P4

PTJ0 I2C1_SD

A

LCD_P4

8

LCD_P4 LCD_P4

PTJ1 I2C1_SC

L

LCD_P4

9

PTB0 LCD_P3 LCD_P3 PTB0

—

LCD_P3

1

—

PTJ2

LCD_P5 LCD_P5

PTJ2

—

LCD_P5

0

10

11

12

18

19

20

VDD

VSS

VDD

VSS

VDD

VSS

—

PTB1/ LCD_P3 LCD_P3 PTB1/

LLWU_P

17

LCD_P3

2

LLWU_P

17

13

14

15

16

21

22

23

24

PTB2 LCD_P3 LCD_P3 PTB2

SPI2_P

CS0

—

LCD_P3

3

PTB3 LCD_P3 LCD_P3 PTB3

SPI2_S

CK

LCD_P3

4

PTB4 LCD_P3 LCD_P3 PTB4 SPI2_MI

LCD_P3

5

SO

PTB5 LCD_P3 LCD_P3 PTB5

SPI2_M

OSI

LCD_P3

6

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

43

NXP Semiconductors

Pinout

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

LQFP

Name

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

17

25

PTB6 LCD_P3 LCD_P3 PTB6

7/ 7/

CMP1_I CMP1_I

N0 N0

—

LCD_P3

7

18

19

20

26

27

28

PTB7 LCD_P3 LCD_P3 PTB7 AFE_CL

—

LCD_P3

8

K

PTC0 LCD_P3 LCD_P3 PTC0 UART3_ XBAR_I PDB0_E

LCD_P3

9

RTS_b

PTC1 LCD_P4 LCD_P4 PTC1 UART3_

0/ 0/ CTS_b

CMP1_I CMP1_I

N1 N1

PTC2 LCD_P4 LCD_P4 PTC2 UART3_ XBAR_O

N1

XTRG

—

LCD_P4

0

21

22

29

30

—

LCD_P4

1

TX

UT1

PTC3/ LCD_P4 LCD_P4 PTC3/ UART3_

—

LCD_P4

2

LLWU_P

13

2/

CMP0_I CMP0_I

N3 N3

2/

LLWU_P

13

RX

—

23

31

PTC4 LCD_P4 LCD_P4 PTC4

—

LCD_P4

3

24

25

26

32

33

34

VBAT

—

XTAL32 XTAL32 XTAL32

EXTAL3 EXTAL3 EXTAL3

2

—

27

28

35

36

37

38

39

40

NC

VSS

NC

VSS

NC

VSS

—

TAMPE TAMPE TAMPE

R2 R2 R2

29

30

31

32

33

34

41

42

43

44

45

46

TAMPE TAMPE TAMPE

R1 R1 R1

—

TAMPE TAMPE TAMPE

R0 R0 R0

AFE_VD AFE_VD AFE_VD

DA DA DA

AFE_VS AFE_VS AFE_VS

SA SA SA

AFE_SD AFE_SD AFE_SD

ADP0 ADP0 ADP0

AFE_SD AFE_SD AFE_SD

ADM0 ADM0 ADM0

Table continues on the next page...

44

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Pinout

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

LQFP

Name

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

—

35

47

AFE_SD AFE_SD AFE_SD

ADP1 ADP1 ADP1

—

36

48

AFE_SD AFE_SD AFE_SD

ADM1 ADM1 ADM1

—

37

38

39

49

50

51

VREFH VREFH VREFH

VREFL VREFL VREFL

AFE_SD AFE_SD AFE_SD

—

ADP2/

CMP1_I CMP1_I CMP1_I

N2 N2 N2

ADP2/

40

52

AFE_SD AFE_SD AFE_SD

ADM2/ ADM2/ ADM2/

CMP1_I CMP1_I CMP1_I

—

N3

41

42

53

54

VREF

—

AFE_SD AFE_SD AFE_SD

ADP3/ ADP3/ ADP3/

CMP1_I CMP1_I CMP1_I

N4 N4 N4

43

55

AFE_SD AFE_SD AFE_SD

ADM3/ ADM3/ ADM3/

CMP1_I CMP1_I CMP1_I

—

N5

NC

N5

NC

N5

NC

—

44

56

57

58

—

PTC5/ ADC0_S ADC0_S PTC5/ UART0_

LLWU_P

12

LPTMR1

_ALT1

E0/

CMP2_I CMP2_I

N0 N0

E0/

LLWU_P RTS_b

12

45

46

59

60

PTC6 ADC0_S ADC0_S PTC6 UART0_ QTMR0_ PDB0_E

—

E1/

CMP2_I CMP2_I

N1 N1

E1/

CTS_b

TMR1

XTRG

PTC7 ADC0_S ADC0_S PTC7 UART0_ XBAR_O

E2/ E2/ TX UT2

CMP2_I CMP2_I

N2 N2

—

47

—

61

62

63

PTD0/ CMP0_I CMP0_I PTD0/ UART0_ XBAR_I

—

LLWU_P

11

N0

LLWU_P

11

RX

N2

PTJ3

PTJ4

DISABL

ED

—

PTJ3 LPUART CMP2_

0_RTS_

b

OUT

DISABL

ED

—

PTJ4 LPUART LPTMR1

0_CTS_ _ALT1

b

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

45

NXP Semiconductors

Pinout

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

LQFP

Name

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

—

48

64

PTD1

DISABL

ED

—

PTD1 UART1_ SPI0_P XBAR_O QTMR0_

—

TX

CS0

UT3

TMR3

—

49

65

PTD2/ CMP0_I CMP0_I PTD2/ UART1_ SPI0_S XBAR_I

—

LLWU_P

10

N1

—

LLWU_P

10

RX

CK

N3

—

66

67

PTJ5

DISABL

ED

PTJ5 LPUART

0_TX

—

PTJ6/ DISABL

LLWU_P

18

PTJ6/ LPUART

LLWU_P 0_RX

18

—

ED

—

50

—

68

69

70

PTJ7

DISABL

ED

—

PTJ7 LPTMR1

_ALT2

—

PTD3

DISABL

ED

PTD3 UART1_ SPI0_M LPTMR1

CTS_b

OSI

_ALT2

PTK0 ADC0_S ADC0_S PTK0 LPTMR1

—

E12

NC

E12

NC

_ALT3

—

71

72

73

74

75

NC

—

PTK1 ADC0_S ADC0_S PTK1

E13 E13

—

51

76

PTD4/ ADC0_S ADC0_S PTD4/ UART1_ SPI0_MI LPTMR1

—

LLWU_P

9

E3

LLWU_P RTS_b

9

SO

_ALT3

52

53

77

78

PTD5 ADC0_S ADC0_S PTD5 LPTMR0 QTMR0_ UART3_

E4a E4a _ALT3 TMR0 CTS_b

—

PTD6/ ADC0_S ADC0_S PTD6/ LPTMR0 CMP1_ UART3_

LLWU_P

8

E5a

LLWU_P _ALT2

8

OUT

RTS_b

54

79

PTD7/ CMP0_I CMP0_I PTD7/ I2C0_SC XBAR_I UART3_

—

LLWU_P

7

N4

LLWU_P

7

L

N4

RX

55

—

80

81

82

PTE0

DISABL

ED

—

PTE0 I2C0_SD XBAR_O UART3_ CLKOUT

—

A

UT4

TX

PTK2 ADC0_S ADC0_S PTK2 UART0_

E14 E14 TX

—

PTK3/ ADC0_S ADC0_S PTK3/ UART0_

LLWU_P

19

—

E15

LLWU_P

19

RX

56

57

83

84

PTE1 RESET_

b

—

PTE1

—

RESET_

b

PTE2

EXTAL EXTAL

PTE2 EWM_IN XBAR_I I2C1_SD

N6

—

A

Table continues on the next page...

46

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Pinout

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

LQFP

Name

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

58

85

PTE3

XTAL

PTE3 EWM_O AFE_CL I2C1_SC

—

UT_b

—

K

L

59

60

61

62

63

86

87

88

89

90

VSS

VSSA

VDDA

VDD

VSS

VSSA

VDDA

VDD

VSS

VSSA

VDDA

VDD

—

PTE4

DISABL

ED

PTE4 LPTMR0 UART2_ EWM_IN

_ALT1 CTS_b

64

65

91

92

PTE5/ DISABL

—

PTE5/ QTMR0_ UART2_ EWM_O

—

LLWU_P

6

ED

LLWU_P TMR3

6

RTS_b

UT_b

—

PTE6/ SWD_DI CMP0_I PTE6/ XBAR_I UART2_

I2C0_SC

L

SWD_DI

O

LLWU_P

5

O

N2

LLWU_P

5

N5

RX

66

67

93

94

PTE7

SWD_C ADC0_S PTE7 XBAR_O UART2_

LK E6a UT5 TX

—

I2C0_SD

A

—

SWD_C

LK

PTF0/ ADC0_S ADC0_S PTF0/ RTC_CL QTMR0_ CMP0_

—

LLWU_P

4

E7a/

CMP2_I CMP2_I

N3 N3

E7a/

LLWU_P KOUT

4

TMR2

OUT

—

68

69

95

96

PTF1 LCD_P0/ LCD_P0/ PTF1 QTMR0_ XBAR_O

ADC0_S ADC0_S TMR0 UT6

E8/ E8/

CMP2_I CMP2_I

N4 N4

—

LCD_P0

PTF2 LCD_P1/ LCD_P1/ PTF2

ADC0_S ADC0_S

CMP1_ RTC_CL

OUT KOUT

—

LCD_P1

E9/

CMP2_I CMP2_I

N5 N5

E9/

—

70

97

98

PTK4 LCD_P5 LCD_P5 PTK4

XBAR_I AFE_CL

—

LCD_P5

1

N9

K

PTK5

PTK6

DISABL

ED

—

PTK5 UART1_

RX

—

99

DISABL

ED

—

PTK6 UART1_

TX

—

100

PTF3/ LCD_P2 LCD_P2 PTF3/

SPI1_P LPTMR0 UART0_

CS0 _ALT2 RX

LCD_P2

LLWU_P

20

LLWU_P

20

71

72

101

102

PTF4 LCD_P3 LCD_P3 PTF4

SPI1_S LPTMR0 UART0_

—

LCD_P3

LCD_P4

CK

PTF5 LCD_P4 LCD_P4 PTF5 SPI1_MI I2C1_SC

SO

Table continues on the next page...

_ALT1

TX

—

L

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

47

NXP Semiconductors

Pinout

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

LQFP

Name

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

73

103

PTF6/ LCD_P5 LCD_P5 PTF6/ SPI1_M I2C1_SD

—

LCD_P5

LLWU_P

3

LLWU_P

3

OSI

A

74

—

104

105

106

PTF7 LCD_P6 LCD_P6 PTF7 QTMR0_ CLKOUT CMP2_

—

LCD_P6

TMR2

OUT

PTK7 LCD_P5 LCD_P5 PTK7 I2C0_SC XBAR_O

—

LCD_P5

2

L

UT9

PTL0 LCD_P5 LCD_P5 PTL0 I2C0_SD

—

LCD_P5

3

A

—

75

107

108

109

110

NC

—

PTG0 LCD_P7 LCD_P7 PTG0 QTMR0_ LPTMR0

LCD_P7

TMR1

_ALT3

76

77

111

112

PTG1/ LCD_P8/ LCD_P8/ PTG1/

LLWU_P ADC0_S ADC0_S LLWU_P

—

LPTMR0

_ALT1

—

LCD_P8

LCD_P9

2

E10

PTG2/ LCD_P9/ LCD_P9/ PTG2/ SPI0_P

LLWU_P ADC0_S ADC0_S LLWU_P CS0

E11 E11

PTG3 LCD_P1 LCD_P1 PTG3

E10

2

—

1

78

79

80

81

113

114

115

116

SPI0_S I2C0_SC

CK

—

LCD_P1

0

L

PTG4 LCD_P1 LCD_P1 PTG4 SPI0_M I2C0_SD

OSI

LCD_P1

1

A

PTG5 LCD_P1 LCD_P1 PTG5 SPI0_MI LPTMR0

LCD_P1

2

SO

_ALT2

PTG6/ LCD_P1 LCD_P1 PTG6/

—

LPTMR0

_ALT3

LCD_P1

3

LLWU_P

0

3

LLWU_P

0

82

83

117

118

PTG7 LCD_P1 LCD_P1 PTG7

—

LPTMR1

_ALT1

—

LCD_P1

4

PTH0 LCD_P1 LCD_P1 PTH0 LPUART

—

LCD_P1

5

0_CTS_

b

84

119

PTH1 LCD_P1 LCD_P1 PTH1 LPUART

—

LCD_P1

6

0_RTS_

b

85

86

87

120

121

122

PTH2 LCD_P1 LCD_P1 PTH2 LPUART

0_RX

—

LCD_P1

7

PTH3 LCD_P1 LCD_P1 PTH3 LPUART

LCD_P1

8

0_TX

PTH4 LCD_P1 LCD_P1 PTH4

—

LPTMR1

_ALT2

LCD_P1

9

Table continues on the next page...

48

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Pinout

ALT7

Table 39. Signal Multiplexing and Pin Assignments (continued)

100

LQFP

144

DEFAU

LT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

LQFP

Name

88

89

90

91

123

124

125

126

PTH5 LCD_P2 LCD_P2 PTH5

—

LPTMR1

_ALT3

—

LCD_P2

0

PTH6

PTH7

DISABL

ED

—

PTH6 UART1_ SPI1_P XBAR_I

CTS_b CS0 N7

—

DISABL

ED

—

PTH7 UART1_ SPI1_S XBAR_O

RTS_b CK UT7

—

PTI0/

LLWU_P

21

CMP0_I CMP0_I

PTI0/ UART1_ XBAR_I SPI1_MI SPI1_M

LLWU_P

21

—

N5

RX

N8

SO

OSI

92

—

93

127

128

129

130

PTI1

DISABL

ED

—

PTI1

UART1_ XBAR_O SPI1_M SPI1_MI

—

TX

UT8

—

OSI

—

SO

—

PTL1 LCD_P5 LCD_P5 PTL1

XBAR_I

N10

LCD_P5

4

PTL2 LCD_P5 LCD_P5 PTL2 XBAR_O

UT10

—

LCD_P5

5

PTI2/ LCD_P2 LCD_P2 PTI2/ LPUART

LLWU_P

22

LCD_P2

1

LLWU_P 0_RX

22

94

131

PTI3

LCD_P2 LCD_P2

PTI3

LPUART CMP2_

—

LCD_P2

2

0_TX

OUT

95

—

96

97

132

133

134

135

VSS

VDD

VLL3

VLL2

VSS

VDD

VLL3

VLL2/

VSS

VDD

VLL3

VLL2/

—

PTM0

—

LCD_P6

0

LCD_P6 LCD_P6

0

98

99

136

137

138

VLL1

VLL1/

LCD_P6 LCD_P6

VLL1/

PTM1

—

LCD_P6

1

VCAP2 VCAP2/ VCAP2/ PTM2

LCD_P6 LCD_P6

LCD_P6

2

100

VCAP1 VCAP1/ VCAP1/ PTM3

LCD_P6 LCD_P6

LCD_P6

3

—

139

140

141

PTL3 LCD_P5 LCD_P5 PTL3 EWM_IN

—

LCD_P5

6

PTL4 LCD_P5 LCD_P5 PTL4 EWM_O

LCD_P5

7

UT_b

PTL5/ LCD_P5 LCD_P5 PTL5/

—

LCD_P5

8

LLWU_P

23

8

LLWU_P

23

—

142

PTL6 LCD_P5 LCD_P5 PTL6

—

LCD_P5

9

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

49

NXP Semiconductors

Pinout

5.2 KM35 Pinouts

5.2.1 100-pin LQFP

The following figure represents the KM35 100 LQFP pinouts.

Figure 11. 100-pin LQFP Pinout Diagram

50

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Ordering parts

5.2.2 144-pin LQFP

The following figure represents the KM35 144 LQFP pinouts:

Figure 12. 144-pin LQFP Pinout Diagram

6 Ordering parts

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

51

NXP Semiconductors

Part identification

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search for the

following device numbers:

• MKM35Z256VLL7

• MKM35Z256VLQ7

• MKM35Z512VLL7

• MKM35Z512VLQ7

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format:

Q KM## A FFF R T PP CC N

7.3 Fields

Following table lists the possible values for each field in the part number (not all

combinations are valid):

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Pre-qualification

KM##

A

Kinetis family

Key attribute

• KM35

• Z = Cortex^®-M0+

FFF

Program flash memory size

• 256 = 256 KB

• 512 = 512 KB

R

Silicon revision

• (Blank) = Main

• A = Revision after main

Table continues on the next page...

52

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Terminology and guidelines

Values

Field

Description

Temperature range (°C)

T

• V = –40 to 105

PP

Package identifier

• LL = 100 LQFP (14 mm x 14 mm)

• LQ = 144 LQFP (20 mm × 20 mm)

CC

N

Maximum CPU frequency (MHz)

Packaging type

• 7 = 75 MHz

• R = Tape and reel

• (Blank) = Trays

7.4 Example

This is an example part number:

• MKM35Z512VLL7

8 Terminology and guidelines

8.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical

characteristic that you must guarantee during operation to avoid incorrect operation

and possibly decreasing the useful life of the chip.

8.1.1 Example

This is an example of an operating requirement:

Symbol

Description

Min.

Max.

Unit

V_DD

1.0 V core supply

voltage

0.9

1.1

V

8.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of

values for a technical characteristic that are guaranteed during operation if you meet

the operating requirements and any other specified conditions.

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

53

NXP Semiconductors

Terminology and guidelines

8.2.1 Example

This is an example of an operating behavior:

Symbol

Description

Min.

Max.

Unit

I_WP

Digital I/O weak pullup/ 10

pulldown current

130

µA

8.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are

guaranteed, regardless of whether you meet the operating requirements.

8.3.1 Example

This is an example of an attribute:

Symbol

Description

Min.

Max.

Unit

CIN_D

Input capacitance:

digital pins

—

7

pF

8.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded,

may cause permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

8.4.1 Example

This is an example of an operating rating:

54

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Terminology and guidelines

Symbol

Description

Min.

Max.

Unit

V_DD

1.0 V core supply

voltage

–0.3

1.2

V

8.5 Result of exceeding a rating

40

30

The likelihood of permanent chip failure increases rapidly as

soon as a characteristic begins to exceed one of its operating ratings.

20

10

0

Operating rating

Measured characteristic

8.6 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

8.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

55

NXP Semiconductors

Terminology and guidelines

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

8.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Given the typical manufacturing process, is representative of that characteristic

during operation when you meet the typical-value conditions or other specified

conditions

Typical values are provided as design guidelines and are neither tested nor guaranteed.

8.8.1 Example 1

This is an example of an operating behavior that includes a typical value:

Symbol

Description

Min.

Typ.

Max.

Unit

I_WP

Digital I/O weak

pullup/pulldown

current

10

70

130

µA

8.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and

temperature conditions:

56

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors

Revision History

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

T_J

150 °C

105 °C

25 °C

–40 °C

0

0.90

0.95

1.00

1.05

1.10

V_DD(V)

8.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

3.3 V supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

9 Revision History

The following table provides a revision history for this document.

Table 40. Revision History

Rev. No.

Rev.0

Rev.1

Date

Substantial Changes

08/2019

12/2019

Initial release

• Updated the footnotes of ESD handling ratings

• Updated Thermal Attributes

• Removed EzPort column from KM35 Signal Multiplexing and Pin

Assignments

Table continues on the next page...

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

57

NXP Semiconductors

Revision History

Table 40. Revision History (continued)

Rev. No.

Date

03/2020

Substantial Changes

Rev.2

• ADdedd IDD values in Power consumption operating behaviors

• EDitorial updates

• Updated Low power features in Front Matter

58

Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020

NXP Semiconductors


型号：	MKM35Z256VLQ7
厂家：	NXP
描述：	Kinetis KM35 Sub-Family Data Sheet
文件：	总59页 (文件大小：910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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