MKW38A512VFT4 [NXP]
An ultra low-power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller;型号: | MKW38A512VFT4 |
厂家: | NXP |
描述: | An ultra low-power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller |
文件: | 总95页 (文件大小:1140K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NXP Semiconductors
MKW39A512
Data Sheet: Technical Data
Rev. 7, 03/2020
MKW39/38/37 Data Sheet
MKW39A512VFT4
An ultra low-power, highly integrated Bluetooth® Low
Energy 5.0 wireless microcontroller
MKW38A512VFT4
MKW38Z512VFT4
MKW37A512VFT4
MKW37Z512VFT4
48 "Wettable" HVQFN
7x7 mm Pitch 0.5 mm
Multi-Standard Radio
System peripherals
• 2.4 GHz Bluetooth Low Energy (Bluetooth LE) version
5.0 compliant supporting up to 8 simultaneous
hardware connections and all optional features
including:
• Nine MCU low-power modes to provide power
optimization based on application requirements
• DC-DC Converter supporting Buck and Bypass
operating modes
• High speed (2M PHY)
• Long range
• Advertising Extension
• High duty cycle non-connectable advertising
• Channel selection algorithm #2
• Direct Memory Access (DMA) controller
• Computer Operating Properly (COP) watchdog
• Serial Wire Debug (SWD) Interface and Micro Trace
buffer
• Bit Manipulation Engine (BME)
• Typical Bluetooth LE Receiver Sensitivity
• Bluetooth LE 2 Mbit/s: –95.5 dBm
• Bluetooth LE 1 Mbit/s: –98 dBm
• Bluetooth LE LR 500 kbit/s: –101 dBm
• Bluetooth LE LR 125 kbit/s: –105 dBm
• Generic FSK modulation
Timers
• 16-bit Low-power Timer (LPTMR)
• 3 Timer/PWM Modules(TPM): One 4 channel TPM
and two 2 channel TPMs
• Programmable Interrupt Timer (PIT)
• Real-Time Clock (RTC)
• Data Rate: 250, 500, 1000 and 2000 kbit/s
• Modulations: GFSK BT = 0.5, MSK
• Modulation Index: 0.32, 0.5, 0.7, and 1.0
• Typical Receiver Sensitivity (250 kbit/s GFSK-
BT=0.5, h=0.5) = –101 dBm
Communication interfaces
• 2 Serial Peripheral Interface (SPI) modules
• 2 Inter-integrated Circuit (I2C) modules
• Low-power UART (LPUART) module with LIN
support (2x LPUART on KW38)
• Carrier Modulator Timer (CMT)
• FlexCAN module (with CAN FD support up to 3.2
Mbit/s baudrate) on KW38
• Programmable Transmitter Output Power: –30 dBm to
+5 dBm
• Low external component count for low-cost application
• On-chip balun with single ended bidirectional RF port
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Analog Modules
Security
• AES-128 Hardware Accelerator (AESA)
• 16-bit Analog-to-Digital Converter (ADC)
• 6-bit High-Speed Analog Comparator (CMP)
• 1.2 V Voltage Reference (VREF)
• True Random Number Generator (TRNG)
• Advanced flash security on Program Flash
• 80-bit unique identification number per chip
• 40-bit unique Media Access Control (MAC) sub-
address
MCU and Memories
• 256 KB program flash memory plus 256 KB FlexNVM
on KW39/38
• LE Secure Connections
• 512 KB program flash memory on KW37
• 8 KB FlexRAM supporting EEPROM emulation on
KW39/38
• 8 KB program acceleration RAM on KW37
• On-chip 64 KB SRAM
Clocks
• 26 and 32 MHz supported for Bluetooth LE and
Generic FSK modes
• 32.768 kHz Crystal Oscillator
• Up to 48 MHz Arm® Cortex®-M0+ core
Operating Characteristics
Low-power Consumption
• Voltage range: 1.71 V to 3.6 V
• Ambient temperature range: –40 to 105 °C
• AEC Q100 Grade 2 Automotive Qualification
• Industrial Qualification
• Transceiver current (DC-DC buck mode, 3.6 V supply)
• Typical Rx current: 6.3 mA
• Typical Tx current: 5.7 mA
• Low-power Mode (VLLS0) Current: 266.6 nA
Human-machine Interface (HMI)
• General-purpose input/output (GPIO)
KW39/38/37 Part Numbers
256 KB P-
512 KB Flash/256 Second LPUART
8 KB
Qualification
Tier
Device
CAN FD
FlexRAM Package
EEPROM
P-Flash
KB
with LIN
FlexNVM
MKW39A512VFT4 Auto AEC-Q100
Grade 2
N
Y
N
N
Y
N
Y
Y
Y
7X7 mm 48-
pin "Wettable"
HVQFN
MKW38A512VFT4 Auto AEC-Q100
Grade 2
Y
MKW38Z512VFT4
Industrial
Y
N
N
Y
Y
N
Y
N
Y
N
MKW37A512VFT4 Auto AEC-Q100
Grade 2
MKW37Z512VFT4
Industrial
N
Y
N
N
N
Related Resources
Type
Product Selector
Fact Sheet
Description
The Product Selector lets you find the right Kinetis part for your design.
The Fact Sheet gives overview of the product key features and its uses.
Reference Manual The Reference Manual contains a comprehensive description of the structure and function
(operation) of a device.
Data Sheet
Chip Errata
The Data Sheet includes electrical characteristics and signal connections.
The chip mask set Errata provides additional or corrective information for a particular device mask
set.
Package drawing
Package dimensions are available in package drawings.
2
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
3
NXP Semiconductors
Table of Contents
1
2
Introduction........................................................................... 5
6.4.1 Thermal operating requirements....................... 51
6.4.2 Thermal attributes..............................................51
6.5 Peripheral operating requirements and behaviors.........52
6.5.1 Core modules.................................................... 52
6.5.2 System modules................................................53
6.5.3 Clock modules...................................................54
6.5.4 Memories and memory interfaces..................... 57
6.5.5 Security and integrity modules.......................... 61
6.5.6 Analog............................................................... 61
6.5.7 Timers................................................................68
6.5.8 Communication interfaces................................. 68
6.5.9 Human-machine interfaces (HMI)......................73
6.6 DC-DC Converter Operating Requirements.................. 73
6.7 Ratings...........................................................................75
6.7.1 Thermal handling ratings...................................75
6.7.2 Moisture handling ratings.................................. 75
6.7.3 ESD handling ratings.........................................76
6.7.4 Voltage and current operating ratings............... 76
Pin Diagrams and Pin Assignments......................................76
7.1 KW39/37 Signal Multiplexing and Pin Assignments...... 77
7.2 KW38 Signal Multiplexing and Pin Assignments........... 79
7.3 KW39/38/37 Pinouts......................................................82
7.4 Module Signal Description Tables................................. 83
7.4.1 Core Modules.................................................... 83
7.4.2 Radio Modules...................................................84
7.4.3 System Modules................................................85
7.4.4 Clock Modules...................................................85
7.4.5 Analog Modules.................................................86
7.4.6 Timer Modules...................................................87
7.4.7 Communication Interfaces.................................87
7.4.8 Human-Machine Interfaces(HMI)...................... 89
Package Information............................................................. 89
8.1 Obtaining package dimensions......................................89
Part identification...................................................................90
9.1 Description.....................................................................90
9.2 Format........................................................................... 90
9.3 Fields............................................................................. 90
9.4 Example.........................................................................91
Feature Descriptions.............................................................6
2.1 Block Diagram............................................................... 6
2.2 Radio features............................................................... 8
2.3 Microcontroller features................................................. 9
2.4 System features.............................................................10
2.5 Peripheral features........................................................ 12
2.6 Security Features...........................................................17
Transceiver Description........................................................ 18
3.1 Transceiver Functions................................................... 18
3.2 Key Specifications......................................................... 19
3.3 Channel Map Frequency Plans .................................... 19
3.3.1 Channel Plan for Bluetooth Low Energy............19
3.3.2 Other Channel Plans ........................................ 21
Transceiver Electrical Characteristics...................................21
4.1 Radio operating conditions............................................ 21
4.2 Receiver Feature Summary...........................................22
4.3 Transmit and PLL Feature Summary.............................26
System and Power Management..........................................31
5.1 Power Management.......................................................31
5.1.1 DC-DC Converter.............................................. 32
5.2 Modes of Operation....................................................... 32
5.2.1 Power modes.....................................................32
KW39/38/37 Electrical Characteristics..................................35
6.1 AC electrical characteristics...........................................35
6.2 Nonswitching electrical specifications............................35
6.2.1 Voltage and current operating requirements..... 35
6.2.2 LVD and POR operating requirements..............36
6.2.3 Voltage and current operating behaviors...........37
6.2.4 Power mode transition operating behaviors...... 38
6.2.5 Power consumption operating behaviors.......... 39
6.2.6 Diagram: Typical IDD_RUN operating behavior46
6.2.7 SoC Power Consumption.................................. 48
6.2.8 Designing with radiated emissions in mind........49
6.2.9 Capacitance attributes.......................................49
6.3 Switching electrical specifications..................................49
6.3.1 Device clock specifications................................49
6.3.2 General switching specifications....................... 50
6.4 Thermal specifications...................................................51
3
4
5
7
6
8
9
10 Revision History.................................................................... 91
4
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Introduction
1 Introduction
The KW39/38/37 wireless microcontrollers (MCU), which includes the KW39A,
KW38A/Z and KW37A/Z families of devices, are highly integrated single-chip
devices that enable Bluetooth Low Energy 5.0 and Generic FSK connectivity for
automotive, and industrial embedded systems. To meet the stringent requirements of
automotive applications, the KW39/38/37 is fully AEC Q100 Grade 2 Automotive
Qualified. The target applications center on wirelessly bridging the embedded world
with mobile devices to enhance the human interface experience, share embedded data
between devices and the cloud and enable wireless firmware updates. Leading the
automotive applications is the Digital Key, where a smartphone can be used by the
owner as an alternative to the key FOB for unlocking and personalizing the driving
experience. For a car sharing experience, the owner can provide selective, temporary
authorization for access to the car allowing the authorized person to unlock, start, and
operate the car using their mobile device using Bluetooth LE.
The KW39/38/37 Wireless MCU integrates an Arm® Cortex-M0+ CPU with up to
512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE 5.0
and Generic FSK modulations. The Bluetooth LE radio supports up to 8 simultaneous
connections in any master/slave combination.
The KW38 includes an integrated FlexCAN module enabling seamless integration
into a cars in-vehicle or an industrial CAN communication network, enabling
communication with external control and sensor monitoring devices over Bluetooth
LE. The FlexCAN module can support CAN’s flexible data-rate (CAN FD) protocol
for increased bandwidth and lower latency required by many automotive applications.
The KW39/38/37 devices can be used as a "BlackBox" modem to add Bluetooth LE
or Generic FSK connectivity to an existing host MCU or MPU (microprocessor). The
devices may also be used as a standalone smart wireless sensor with embedded
application where no host controller is required.
The RF circuit of the KW39/38/37 is optimized to require very few external
components, achieving the smallest RF footprint possible on a printed circuit board.
Extremely long battery life is achieved through the efficiency of code execution in the
Cortex-M0+ CPU core and the multiple low-power operating modes of the
KW39/38/37. For power critical applications, an integrated DC-DC converter enables
operation from a single coin cell or Li-ion battery with a significant reduction of peak
receive and transmit current consumption.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
5
NXP Semiconductors
Feature Descriptions
2 Feature Descriptions
This section provides a simplified block diagram and highlights the KW39/38/37
features.
2.1 Block Diagram
32K Osc
32M Osc
IRC
MCG
Arm Cortex M0+ Core
4 MHz
DMA MUX
4ch DMA
IRC
32 kHz
Serial Wire Debug
DAP MDM
NVIC
WIC
FLL
DWT
MTB
IOPORT
Unified Bus
Data stream
AHBLite
AHBLite
M2A
M3
M0
Crossbar-Lite Switch (AXBS)
S3
S2
S0
S1
SIM
ADC
PIT
I2C x2
GPIO
Flash
Controller
64 KByte
SRAM
SMC
RCM
PMC
CMP
TPM x3
LPTMR
RTC
LPUART
SPI x2
BME
LTC(AESA)
Flash
256 KB
Radio
FlexNVM
256 KB
AIPS-Lite
TRNG
FlexRAM
8 KB
IPS
(for RSIM)
IPS
IPS
VREF
VDCDC_IN
DCDC
CMT
Figure 1. KW39 Detailed Block Diagram
32K Osc
32M Osc
IRC
MCG
Arm Cortex M0+ Core
DMA MUX
4 MHz
IRC
32 kHz
Serial Wire Debug
DAP MDM
NVIC
WIC
FLL
DWT
MTB
IOPORT
Unified Bus
4ch DMA
Data stream
AHBLite
AHBLite
M2A
M3
M0
Crossbar-Lite Switch (AXBS)
S3
S2
S0
S1
SIM
ADC
FlexCAN
PIT
I2C x2
GPIO
Flash
Controller
64 KByte
SRAM
SMC
RCM
PMC
CMP
TPM x3
LPTMR
RTC
LPUART x2
SPI x2
BME
LTC(AESA)
Flash
256 KB
FlexNVM
256 KB
Radio
AIPS-Lite
TRNG
FlexRAM
8 KB
IPS
(for RSIM)
IPS
IPS
VREF
VDCDC_IN
DCDC
CMT
Figure 2. KW38 Detailed Block Diagram
6
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Feature Descriptions
32K Osc
32M Osc
IRC
MCG
Arm Cortex M0+ Core
4 MHz
DMA MUX
4ch DMA
IRC
32 kHz
Serial Wire Debug
DAP MDM
NVIC
WIC
FLL
DWT
MTB
IOPORT
Unified Bus
Data stream
M3
AHBLite
AHBLite
M2A
M0
Crossbar-Lite Switch (AXBS)
S3
S2
S0
S1
SIM
ADC
PIT
I2C x2
GPIO
Flash
Controller
64 KByte
SRAM
SMC
RCM
PMC
CMP
TPM x3
LPTMR
RTC
LPUART
SPI x2
BME
LTC(AESA)
Flash
512 KB
Radio
Prg Acc RAM
8 KB
AIPS-Lite
TRNG
IPS
(for RSIM)
IPS
IPS
VREF
VDCDC_IN
DCDC
CMT
Figure 3. KW37 Detailed Block Diagram
Table 1. List of IPs in block diagrams
Acronym
Definition
Analog-to-Digital Converter
ADC
AESA
AIPS
BME
CMP
CMT
DAP
DMA
Advanced Encryption Standard Accelerator
Peripheral Bridge
Bit Manipulation Engine
Comparator
Carrier Modulator Timer
Debug Access Port
Direct Memory Access
Direct Memory Access Multiplexer
Data Watchpoint and Trace
Frequency-Locked Loop
General Purpose Input/Output
Inter-integrated Circuit
Internal Reference Clock
Low-Power Timer
DMAMUX
DWT
FLL
GPIO
I2C
IRC
LPTMR
LPUART
LTC
Low-Power UART
LP Trusted Cryptography
Multipurpose Clock Generator
Miscellaneous Debug Module
Micro Trace Buffer
MCG
MDM
MTB
NVIC
OSC
Nested Vectored Interrupt Controller
Oscillator
PIT
Periodic Interrupt Timer
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
7
NXP Semiconductors
Feature Descriptions
Table 1. List of IPs in block diagrams (continued)
Acronym
Definition
Power Management Control
PMC
PORT
Prg Acc RAM
RCM
Port Control and Interrupt
Flash Programming Acceleration RAM
Reset Control Module
RSIM
RTC
Radio System Integration Module
Real-Time Clock
SIM
System Integration Module
System Mode Controller
Serial Peripheral Interface
True Random Number Generator
Voltage Reference
SMC
SPI
TRNG
VREF
2.2 Radio features
Operating frequencies:
• 2.4 GHz ISM band (2400-2483.5 MHz)
• Medical Body Area Network frequency band (MBAN) 2360-2400 MHz
Supported standards:
• Bluetooth Low Energy Version 5.0 compliant radio supporting all mandatory and
optional features including:
• Bluetooth LE 4.2 errata
• 2 Mbit/s high-speed mode
• Long range coded PHY (125/500 kbit/s)
• Advertising Extensions
• High duty cycle non-connectable advertising
• Channel selection algorithm #2
• Support for up to 8 simultaneous Bluetooth LE hardware connections in any
master, slave combination
• Bluetooth LE Application Profiles
• Generic FSK modulation supporting data rates of 250, 500, 1000 and 2000 kbit/s
Other features:
• Programmable transmit output power up to +5 dBm with greater than 30 dB power
control dynamic range
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MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Feature Descriptions
• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK
modes
• Up to 26 devices supported by whitelist in hardware
• Up to 8 private resolvable addresses supported in hardware
• Supports DMA capture of IQ data and phase for localization applications
• Support for distance estimation and direction finding applications
• Integrated on-chip balun
• Single ended bidirectional RF port shared by transmit and receive
• Low external component count
• Supports transceiver range extension using external PA and/or LNA
2.3 Microcontroller features
Arm Cortex-M0+ CPU
• Up to 48 MHz CPU
• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline
microarchitecture for reduced power consumption and improved architectural
performance (cycles per instruction)
• Supports up to 32 interrupt request sources
• Binary compatible instruction set architecture with the Cortex-M0 core
• Thumb instruction set combines high code density with 32-bit performance
• Serial Wire Debug (SWD) reduces the number of pins required for debugging
• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using
system RAM as the destination memory
Nested Vectored Interrupt Controller (NVIC)
• 32 vectored interrupts, 4 programmable priority levels
• Includes a single non-maskable interrupt
Wake-up Interrupt Controller (WIC)
• Supports interrupt handling when system clocking is disabled in low-power
modes
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC
on entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for
wake-up as soon as a non-masked interrupt is detected
Debug Controller
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
9
NXP Semiconductors
Feature Descriptions
• Two-wire Serial Wire Debug (SWD) interface
• Hardware breakpoint unit for 2 code addresses
• Hardware watchpoint unit for 2 data items
• Micro Trace Buffer for program tracing
On-Chip Memory
• Up to 512 KB Flash
• KW39/38 contains 256 KB program flash with ECC and 256 KB FlexNVM
enabling EEPROM emulation.
• KW37 contains 512 KB program flash with ECC.
• Flash implemented as two equal blocks each of 256 KB block. Code can
execute or read from one block while the other block is being erased or
programmed on KW37 only.
• Firmware distribution protection. Program flash can be marked execute-only
on a per-sector (8 KB) basis to prevent firmware contents from being read by
third parties.
• 64 KB SRAM
• KW39/38 contains 8 KB FlexRAM enabling EEPROM emulation.
• KW37 contains 8 KB program acceleration RAM.
• Security circuitry to prevent unauthorized access to RAM and flash contents
through the debugger
2.4 System features
Power Management Control Unit (PMC)
• Programmable power saving modes
• Available wake-up from power saving modes via internal and external sources
• Integrated Power-on Reset (POR)
• Integrated Low Voltage Detect (LVD) with reset (brownout) capability
• Selectable LVD trip points
• Programmable Low Voltage Warning (LVW) interrupt capability
• Individual peripheral clocks can be gated off to reduce current consumption
• Internal Buffered bandgap reference voltage
• Factory programmed trim for bandgap and LVD
• 1 kHz Low-power Oscillator (LPO)
DC-DC Converters
10
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Feature Descriptions
• Internal switched mode power supply supporting Buck and Bypass operating
modes
• Buck operation supports external voltage sources of 2.1 V to 3.6 V
• When DC-DC is not used, the device supports an external voltage range of 1.5 V
to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_RF3 and
VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1, and VDDA pins)
• An external inductor is required to support the Buck mode
• The DC-DC Converter VDD_1P8OUT current drive for external devices (MCU
in RUN mode, Radio is enabled, other peripherals are disabled)
• Up to 45 mA in buck mode with VDD_1P8OUT = 1.8 V
• Up to 27 mA in buck mode with VDD_1P8OUT = 3.0 V
Direct Memory Access (DMA) Controller
• All data movement via dual-address transfers: read from source, write to
destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 4-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer Control Descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous
transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration
count
• Optional error terminations per channel and logically summed together to form
one error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
• Support for complex data structures
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
11
NXP Semiconductors
Feature Descriptions
DMA Channel Multiplexer (DMA MUX)
• 4 independently selectable DMA channel routers
• 2 periodic trigger sources available
• Each channel router can be assigned to 1 of the peripheral DMA sources
COP Watchdog Module
• Independent clock source input (independent from CPU/bus clock)
• Choice between two clock sources
• LPO oscillator
• Bus clock
System Clocks
• Both 26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE
and Generic FSK modes
• MCU can derive its clock either from the crystal reference oscillator or the
Frequency-locked Loop (FLL)1
• 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth Low
Energy timing in low-power modes
• Multipurpose Clock Generator (MCG)
• Internal reference clocks — Can be used as a clock source for other on-chip
peripherals
• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 3% accuracy
across full temperature range
• On-chip 4 MHz oscillator with 11% accuracy across full temperature range
• Frequency-locked Loop (FLL) controlled by internal or external reference
• 20 MHz to 48 MHz FLL output
Unique Identifiers
• 80-bit Unique ID represents a unique identifier for each chip
• 40-bit unique Media Access Control (MAC) address, which can be used to build a
unique 48-bit Bluetooth Low Energy MAC address
2.5 Peripheral features
16-bit Analog-to-Digital Converter (ADC)
• Linear successive approximation algorithm with 16-bit resolution
• Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode
1. Clock options can have restrictions based on the chosen SoC configuration.
12
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Feature Descriptions
• Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
• Input clock selection
• Operation in low-power modes for lower noise operation
• Asynchronous clock source for lower noise operation
• Selectable asynchronous hardware conversion trigger
• Automatic compare with interrupt for less-than, or greater than, or equal to
programmable value
• Temperature sensor
• Battery voltage measurement
• Hardware average function
• Selectable voltage reverence
• Self-calibration mode
High-Speed Analog Comparator (CMP)
• 6-bit DAC programmable reference generator output
• Up to eight selectable comparator inputs; each input can be compared with any
input by any polarity sequence
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of
comparator output
• Two performance modes:
• Shorter propagation delay at the expense of higher power
• Low-power, with longer propagation delay
• Operational in all MCU power modes except VLLS0 mode
Voltage Reference(VREF1)
• Programmable trim register with 0.5 mV steps, automatically loaded with factory
trimmed value upon reset
• Programmable buffer mode selection:
• Off
• Bandgap enabled/standby (output buffer disabled)
• High-power buffer mode (output buffer enabled)
• 1.2 V output at room temperature
• VREF_OUT output signal
Low-power Timer (LPTMR)
• One channel
• Operation as timer or pulse counter
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
13
NXP Semiconductors
Feature Descriptions
• Selectable clock for prescaler/glitch filter
• 1 kHz internal LPO
• External low-power crystal oscillator
• Internal reference clock
• Configurable glitch filter or prescaler
• Interrupt generated on timer compare
• Hardware trigger generated on timer compare
• Functional in all power modes
Timer/PWM (TPM)
• TPM0: 4 channels, TPM1 and TPM2: 2 channels each
• Selectable source clock
• Programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up or
up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Input capture and output compare modes
• Generation of hardware triggers
• TPM1 and TPM2: Quadrature decoder with input filters
• Global time base mode shares single time base across multiple TPM instances
Programmable Interrupt Timer (PIT)
• Up to 2 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
Real-Time Clock (RTC)
• 32-bit seconds counter with 32-bit alarm
• Can be invalidated on detection of tamper detect
• 16-bit prescaler with compensation
• Register write protection
• Hard Lock requires MCU POR to enable write access
• Soft lock requires POR or software reset to enable write/read access
• Capable of waking up the system from low-power modes
Inter-Integrated Circuit (I2C)
• Two channels
• Compatible with I2C bus standard and SMBus Specification Version 2 features
• Up to 400 kHz operation
14
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Feature Descriptions
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low-power mode
LPUART
• One channel (2 channels on KW38)
• Full-duplex operation
• Standard mark/space Non-return-to-zero (NRZ) format
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Programmable 1 or 2 stop bits
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Two receiver wake-up methods:
• Idle line wake-up
• Address mark wake-up
• Address match feature in receiver to reduce address mark wake-up ISR overhead
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise
detection
• Operation in low-power modes
• Hardware Flow Control RTS\CTS
• Functional in Stop/VLPS modes
• Break detect supporting LIN
Serial Peripheral Interface (SPI)
• Two independent SPI channels
• Master and slave mode
• Full-duplex, three-wire synchronous transfers
• Programmable transmit bit rate
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
15
NXP Semiconductors
Feature Descriptions
• Double-buffered transmit and receive data registers
• Serial clock phase and polarity options
• Slave select output
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Support for both transmit and receive by DMA
Carrier Modulator Timer (CMT)
• Four modes of operation
• Time; with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO signal
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
• Interrupt on end of cycle
• Ability to disable CMT_IRO signal and use as timer interrupt
General Purpose Input/Output (GPIO)
• Hysteresis and configurable pull up device on all input pins
• Independent pin value register to read logic level on digital pin
• All GPIO pins can generate IRQ and wake-up events
• Configurable drive strength on some output pins
• GPIO can be configured to function as a interrupt driven keyboard scanning matrix;
in the 48-pin package there are a total of 25 digital pins
FlexCAN (for KW38 only)
• Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol
specification and CAN protocol specification, Version 2.0 B
• Flexible Message Buffers (MBs); there are total 32 MBs of 8 bytes data length
each, configurable as Rx or Tx, all supporting standard and extended messages
• Programmable clock source to the CAN Protocol Interface, either peripheral clock
or oscillator clock
• Capability to select priority between mailboxes and Rx FIFO during matching
process
16
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Feature Descriptions
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either
128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual
masking capability
• Each individual MB forms by 16, 24, 40, or 72 bytes, depending on the quantity
of data bytes allocated for the message payload: 8, 16, 32, or 64 data bytes,
respectively
2.6 Security Features
Advanced Encryption Standard Accelerator(AES-128 Accelerator)
The Advanced Encryption Standard Accelerator (AESA) module is a standalone
hardware coprocessor capable of accelerating the 128-bit advanced encryption
standard (AES) cryptographic algorithms.
The AESA engine supports the following cryptographic features.
LTC includes the following features:
• Cryptographic authentication
• Message Authentication Codes (MAC)
• Cipher-based MAC (AES-CMAC)
• Extended cipher block chaining message authentication code (AES-
XCBC-MAC)
• Auto padding
• Integrity Check Value(ICV) checking
• Authenticated encryption algorithms
• Counter with CBC-MAC (AES-CCM)
• Symmetric key block ciphers
• AES (128-bit keys)
• Cipher modes:
• AES-128 modes
• Electronic Codebook (ECB)
• Cipher Block Chaining (CBC)
• Counter (CTR)
• Secure scan
True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is a hardware accelerator module that
constitutes a high-quality entropy source.
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17
NXP Semiconductors
Transceiver Description
• TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-consuming
module, such as a deterministic random number generator.
• TRNG output can be read and used by a deterministic pseudo-random number
generator (PRNG) implemented in software.
• TRNG-PRNG combination achieves NIST-compliant true randomness and
cryptographic-strength random numbers using the TRNG output as the entropy
source.
• A fully FIPS 180 compliant solution can be realized using the TRNG together with
a FIPS-compliant deterministic random number generator and the SoC-level
security.
Flash Memory Protection
The on-chip flash memory controller enables the following useful features:
• Program flash protection scheme prevents accidental program or erase of stored
data.
• Automated, built-in, program and erase algorithms with verify.
• Read access to one program flash block is possible while programming or erasing
data in the other program flash block.
3 Transceiver Description
• Direct Conversion Receiver (Zero IF)
• Constant Envelope Transmitter
• Low Transmit and Receive Current Consumption
• Low bill of material (BOM) radio
3.1 Transceiver Functions
Receive
The receiver architecture is Zero IF (ZIF) where the received signal after passing
through RF front end is down-converted to a baseband signal. The signal is filtered and
amplified before it is fed to analog-to-digital converter. The digital signal then
decimates to a baseband clock frequency before it digitally processes, demodulates and
passes on to packet processing/link-layer processing.
Transmit
18
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Transceiver Description
The transmitter transmits GFSK/FSK modulation having power and channel selection
adjustment per user application. After the channel of operation is determined, coarse
and fine-tuning is executed within the Frac-N PLL to engage signal lock. After signal
lock is established, the modulated buffered signal is routed to a multi-stage amplifier
for transmission..
3.2 Key Specifications
KW39/38/37 meets or exceeds all Bluetooth Low Energy version 5.0 performance
specifications. The key specifications for the KW39/38/37 are:
Frequency Band:
• ISM Band: 2400 to 2483.5 MHz
• MBAN Band: 2360 to 2400 MHz
Full Bluetooth Low Energy version 5.0 modulation scheme:
• Symbol rate: Uncoded PHY (1, 2 Mbit/s), Coded PHY (125, 500 kbit/s)
• Modulation: GFSK BT=0.5, h=0.5
• Receiver sensitivity: –98 dBm, typical for Bluetooth LE 1 Mbit/s, –105 dBm for
Bluetooth LE-LR 125 kbit/s; for all other modes, refer Receiver Feature
Summary.
• Programmable transmitter output power: –30 dBm to +5 dBm
Generic FSK modulation scheme:
• Symbol rate: 250, 500, 1000, and 2000 kbit/s
• Modulation(s): GFSK (modulation index = 0.32, 0.5, 0.7, and 1.0, BT = 0.5), and
MSK
• Receiver Sensitivity: Mode and data rate dependent. –101 dBm typical for GFSK
(r=250 kbit/s, BT = 0.5, h = 0.5)
3.3 Channel Map Frequency Plans
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
19
NXP Semiconductors
Transceiver Description
3.3.1 Channel Plan for Bluetooth Low Energy
This section describes the frequency plan / channels associated with 2.4 GHz ISM and
MBAN bands for Bluetooth Low Energy.
2.4 GHz ISM Channel numbering:
• Fc=2402 + k * 2 MHz, k=0,.........,39.
MBAN Channel numbering:
• Fc=2360 + k in MHz, for k=0,.....,39
where k is the channel number.
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Channel
Freq (MHz)
2402
2404
2406
2408
2410
2412
2414
2416
2418
2420
2422
2424
2426
2428
2430
2432
2434
2436
2438
2440
2442
2444
2446
2448
Channel
Freq (MHz)
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
Freq (MHz)
2390
2391
2392
2393
2394
2395
2396
2397
2398
2402
2404
2406
2408
2410
2412
2414
2416
2418
2420
2422
2424
2426
2428
2430
0
1
0
1
28
29
30
31
32
33
34
35
36
0
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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20
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
Transceiver Electrical Characteristics
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Channel
Freq (MHz)
2450
2452
2454
2456
2458
2460
2462
2464
2466
2468
2470
2472
2474
2476
2478
2480
Channel
24
Freq (MHz)
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
Freq (MHz)
2432
2434
2436
2438
2440
2442
2444
2446
2448
2450
2452
2454
2456
2476
2478
2480
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
15
16
17
18
19
20
21
22
23
24
25
26
27
37
38
39
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
2. Per FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.
3.3.2 Other Channel Plans
The RF synthesizer can be configured to use any channel frequency between 2.36 and
2.487 GHz.
4 Transceiver Electrical Characteristics
4.1 Radio operating conditions
Table 3. Radio operating conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Input Frequency
fin
2.360
—
2.480
GHz
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MKW39/38/37 Data Sheet, Rev. 7, 03/2020
21
NXP Semiconductors
Transceiver Electrical Characteristics
Table 3. Radio operating conditions (continued)
Characteristic
Symbol
TA
Min
–40
—
Typ
25
Max
105
10
Unit
°C
Ambient Temperature Range
Maximum RF Input Power
Pmax
fref
—
dBm
Crystal Reference Oscillator Frequency
26 MHz or 32 MHz
1
1. The recommended crystal accuracy is 40 ppm including initial accuracy, mechanical, temperature, and aging factors.
4.2 Receiver Feature Summary
Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Receiver General Specifications
Supply current power down on VDD_RFx supplies
Ipdn
—
—
200
1000
—
nA
Supply current Rx On with DC-DC converter enable
(Buck; VDCDC_IN = 3.6 V) , 2
IRxon
6.36
mA
Supply current Rx On with DC-DC converter disabled
(Bypass) 2
IRxon
—
17.78
—
mA
Input RF Frequency
fin
2.360
—
—
–101
—
2.4835
—
GHz
dBm
dBm
dB
GFSK Rx Sensitivity(250 kbit/s GFSK-BT=0.5, h=0.5)
Max Rx RF Input Signal Level
SENSGFSK
RFin,max
NFHG
—
10
Noise Figure for maximum gain mode @ typical
sensitivity
—
7.5
—
Receiver Signal Strength Indicator Range3
Receiver Signal Strength Indicator Resolution
Typical RSSI variation over frequency
Typical RSSI variation over temperature
Narrowband RSSI accuracy5
RSSIRange
RSSIRes
–100
—
—
1
54
—
2
dBm
dB
–2
—
—
—
–54
dB
–2
2
dB
RSSIAcc
—
–3
3
dB
Spurious Emission < 1.6 MHz offset (Measured with 100
kHz resolution and average detector. Device transmit on
RF channel with center frequency fc and spurious power
measured in 1 MHz at RF frequency f), where |f-fc|< 1.6
MHz
—
—
dBc
Spurious Emission > 2.5 MHz offset (Measured with 100
kHz resolution and average detector. Device transmit on
RF channel with center frequency fc and spurious power
measured in 1 MHz at RF frequency f), where |f-fc|> 2.5
MHz6
—
—
—
–70
—
—
dBc
Bluetooth LE coded 125 kbit/s (Long Range, 8x Spreading)
Bluetooth LE LR 125 kbit/s Sensitivity7
SENSBLELR125
Table continues on the next page...
–105
dBm
22
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Transceiver Electrical Characteristics
Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Bluetooth LE LR 125 kbit/s Co-channel Interference
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz).
COSELBLELR125
–2
dB
Adjacent/Alternate Channel Performance8
Bluetooth LE LR 125 kbit/s Adjacent +/–1 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 1
—
—
—
—
10
50
55
60
—
—
—
—
dB
dB
dB
dB
MHz
Bluetooth LE LR 125 kbit/s Adjacent +/–2 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 2
MHz
Bluetooth LE LR 125 kbit/s Alternate +/–3 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 3
MHz
Bluetooth LE LR 125 kbit/s Alternate > +/–5 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 5+
MHz
Bluetooth LE coded 500 kbit/s (Long Range, 2x Spreading)
Bluetooth LE LR 500 kbit/s Sensitivity7
SENSBLELR500
—
–101
–4
—
dBm
dB
Bluetooth LE LR 500 kbit/s Co-channel Interference
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz).
COSELBLELR500
Adjacent/Alternate Channel Performance8
Bluetooth LE LR 500 kbit/s Adjacent +/–1 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 1
—
—
—
—
9
—
—
—
—
dB
dB
dB
dB
MHz
Bluetooth LE LR 500 kbit/s Adjacent +/–2 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 2
50
55
60
MHz
Bluetooth LE LR 500 kbit/s Alternate +/–3 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 3
MHz
Bluetooth LE LR 500 kbit/s Alternate > +/–5 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 5+
MHz
Bluetooth LE uncoded 1 Mbit/s
Bluetooth LE 1 Mbit/s Sensitivity7
SENSBLE1M
—
—
–98
–7
—
—
dBm
dB
Bluetooth LE 1 Mbit/s Co-channel Interference (Wanted
signal at –67 dBm, BER <0.1%. Measurement resolution
1 MHz).
Adjacent/Alternate Channel Selectivity Performance8
COSELBLE1M
Bluetooth LE 1 Mbit/s Selectivity +/–1 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 1 MHz
0
dB
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
23
NXP Semiconductors
Transceiver Electrical Characteristics
Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Bluetooth LE 1 Mbit/s Adjacent +/–2 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 2 MHz
—
42
—
dB
Bluetooth LE 1 Mbit/s Selectivity +/–3 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 3 MHz
—
—
50
55
—
—
dB
dB
Bluetooth LE 1 Mbit/s Alternate ≥ +/–5 MHz Interference SELBLE1M, 5+ MHz
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
Intermodulation Performance
Bluetooth LE 1 Mbit/s Intermodulation with continuous
wave interferer at 3 MHz and modulated interferer is at
6 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM3-6BLE1M
—
—
–42
–23
—
—
dBm
dBm
Bluetooth LE 1 Mbit/s Intermodulation with continuous
wave interferer at 5 MHz and modulated interferer is at
10 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM5-10BLE1M
Blocking Performance
Bluetooth LE 1 Mbit/s Out of band blocking from 30 MHz
to 1000 MHz and 4000 MHz to 5000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.), 9, 10
—
—
—
—
—
—
—
—
3
3
—
—
—
—
dBm
dBm
dBm
dBm
Bluetooth LE 1 Mbit/s Out of band blocking from 1000
MHz to 2000 MHz and 3000 MHz to 4000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)
Bluetooth LE 1 Mbit/s Out of band blocking from 2001
MHz to 2339 MHz and 2484 MHz to 2999 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)10
–12
5
Bluetooth LE 1 Mbit/s Out of band blocking from 5000
MHz to 12750 MHz (Wanted signal at –67 dBm,
BER<0.1%. Interferer continuous wave signal.)10
Bluetooth LE uncoded 2 Mbit/s (High Speed)
Bluetooth LE 2 Mbit/s Sensitivity7
SENSBLE2M
—
–95.5
–7
—
dBm
dB
Bluetooth LE 2 Mbit/s Co-channel Interference (Wanted
signal at –67 dBm, BER <0.1%. Measurement resolution
2 MHz).
COSELBLE2M
Adjacent/Alternate Channel Performance8
Bluetooth LE 2 Mbit/s Adjacent +/–2 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 2 MHz.)
SELBLE2M, 2 MHz
—
—
3
—
—
dB
dB
Bluetooth LE 2 Mbit/s Alternate +/–4 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 2 MHz.)
SELBLE2M, 4 MHz
42
Table continues on the next page...
24
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Transceiver Electrical Characteristics
Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Bluetooth LE 2 Mbit/s Selectivity +/–6 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 2 MHz.)
SELBLE2M, 6 MHz
—
50
—
dB
Bluetooth LE 2 Mbit/s Selectivity ≥ +/–10 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 2 MHz.)
SELBLE2M, 10+ MHz
—
55
—
dB
Intermodulation Performance
Bluetooth LE 2 Mbit/s Intermodulation with continuous
wave interferer at 6 MHz and modulated interferer is at
12 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM6-12BLE2M
IM10-20BLE2M
—
—
–23
–24
—
—
dBm
dBm
Bluetooth LE 2 Mbit/s Intermodulation with continuous
wave interferer at 10 MHz and modulated interferer is
at 20 MHz (Wanted signal at –67 dBm, BER<0.1%.)
Blocking Performance
Bluetooth LE 2 Mbit/s Out of band blocking from 30 MHz
to 1000 MHz and 4000 MHz to 5000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)9,10
—
—
—
—
—
—
—
—
3
–6
–12
5
—
—
—
—
dBm
dBm
dBm
dBm
Bluetooth LE 2 Mbit/s Out of band blocking from 1000
MHz to 2000 MHz and 3000 MHz to 4000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)
Bluetooth LE 2 Mbit/s Out of band blocking from 2001
MHz to 2339 MHz and 2484 MHz to 2999 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)10
Bluetooth LE 2 Mbit/s Out of band blocking from 5000
MHz to 12750 MHz (Wanted signal at –67 dBm,
BER<0.1%. Interferer continuous wave signal.)10
1. All the Rx parameters are measured at the KW39/38/37 RF pins.
2. Transceiver power consumption.
3. Narrow-band RSSI mode.
4. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
5. With one point calibration over frequency and temperature.
6. Exceptions allowed for twice the reference clock frequency(fref) multiples.
7. Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.
8. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
9. Exceptions allowed for carrier frequency sub harmonics.
10. Exceptions allowed for carrier frequency harmonics.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
25
NXP Semiconductors
Transceiver Electrical Characteristics
Table 5. Receiver Specifications with Generic FSK Modulations
Adjacent/Alternate channel selectivity (dB)1
Modulation
type
Data
rate
(kb/s)
Channel
BW (kHz) sensitivity
(dBm)
Typical
Desired Interferer Interferer Interferer Interferer
Co-
channel
signal
level
at 1ꢀ
channel
at 2ꢀ
channel
at 3ꢀ
channel
at 4ꢀ
channel
(dBm) BW offset BW offset BW offset BW offset
GFSK BT =
0.5, h = 0.32
2000
1000
2000
1000
500
2000
1000
4000
2000
1000
500
–90.5
–93.5
–94
–67
–67
–67
–67
–85
–85
–85
–85
–85
39
36
46
44
43
39
44
47
50
48
47
56
56
49
43
53
55
58
52
50
59
59
56
46
56
59
61
54
53
60
60
57
50
59
61
64
–9
–8
–7
–7
–6
–6
–6
–5
–4
GFSK BT =
0.5, h = 0.5
–97
–98.5
–100
–95
250
GFSK, BT =
0.5, h = 0.7
2000
1000
1000
4000
2000
1600
–97.5
–96
GFSK, BT =
0.5, h = 1.0
1. Selectivity measured with an unmodulated blocker.
4.3 Transmit and PLL Feature Summary
• Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN
frequency bands
• Fast PLL Lock time: < 25 µs
• Reference Frequency:
• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK
modes
Table 6. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Transmitter General Specifications
Supply current power down on VDD_RFx supplies
Ipdn
—
—
200
5.7
—
—
nA
Supply current Tx On with PRF = 0 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V) , 2
ITX0dBm
mA
Supply current Tx On with PRF = 0 dBm and DC-DC
converter disabled (Bypass) 2
ITX0dBmb
ITX3.5dBm
ITX3.5dBmb
—
—
—
16
6.9
19
—
—
—
mA
mA
mA
Supply current Tx On with PRF = +3.5 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V)2
Supply current Tx On with PRF = +3.5 dBm and DC-DC
converter disabled (Bypass)2
Table continues on the next page...
26
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Transceiver Electrical Characteristics
Table 6. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Supply current Tx On with PRF = +5 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V, LDO-HF
bumped)2
ITX5dBm
—
8.0
—
mA
Supply current Tx On with PRF = +5 dBm and DC-DC
converter disabled (Bypass, LDO-HF bumped)2
ITX5dBmb
—
21
—
mA
Output RF Frequency
fRFout
2.360
—
—
+5
2.4835
—
GHz
dBm
dBm
dBm
dB
Maximum RF Output Power; LDO-HF bumped 3
Maximum RF Output power, nominal power supply 4
Minimum RF Output power, nominal power supply 4
RF Output power control range
PRF,maxV
PRF,maxn
PRF,minn
PRFCR
—
+3.5
–30
35
—
—
—
—
—
Bluetooth LE Maximum Deviation of the Center
Frequency5
Fcdev,BLE
—
3
—
kHz
Bluetooth LE Frequency Hopping Support
YES
–46
Second Harmonic of Transmit Carrier Frequency (Pout
=
TXH2
TXH3
—
—
—
—
dBm/MHz
dBm/MHz
, 6
PRF,max
)
Third Harmonic of Transmit Carrier Frequency (Pout
=
–50
6
PRF,max
)
Bluetooth LE uncoded 1 Mbit/s / coded 125 kbit/s / coded 500 kbit/s
Bluetooth LE 1 Mbit/s Tx Output Spectrum 20dB BW
TXBWBLE1M
1.0
—
MHz
kHz
Bluetooth LE 1 Mbit/s average frequency deviation using
a 00001111 modulation sequence
Δf1avg,BLE1M
250
220
Bluetooth LE 1 Mbit/s average frequency deviation using
a 01010101 modulation sequence
Δf2avg,BLE1M
kHz
Bluetooth LE 1 Mbit/s RMS FSK Error
FSKerr,BLE1M
3%
—
Bluetooth LE 1 Mbit/s Adjacent Channel Transmit Power
at 2 MHz offset, 7
PRF2MHz,BLE1M
—
—
–53
–59
dBm
dBm
Bluetooth LE 1 Mbit/s Adjacent Channel Transmit Power
at >= 3 MHz offset7
PRF3MHz,BLE1M
—
Bluetooth LE uncoded 2 Mbit/s
Bluetooth LE 2 Mbit/s Tx Output Spectrum 20dB BW
TXBWBLE2M
2.2
—
MHz
kHz
Bluetooth LE 2 Mbit/s average frequency deviation using
a 00001111 modulation sequence
Δf1avg,BLE2M
500
420
Bluetooth LE 2 Mbit/s average frequency deviation using
a 01010101 modulation sequence
Δf2avg,BLE2M
kHz
Bluetooth LE RMS FSK Error
FSKerr,BLE2M
4%
—
Bluetooth LE 2 Mbit/s Adjacent Channel Transmit Power
at 4 MHz offset7
PRF2MHz,BLE2M
—
—
–57
–60
dBm
dBm
Bluetooth LE 2 Mbit/s Adjacent Channel Transmit Power
at >= 6 MHz offset7
PRF3MHz,BLE2M
—
1. All the Tx parameters are measured at test hardware SMA connector.
2. Transceiver power consumption.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
27
NXP Semiconductors
Transceiver Electrical Characteristics
3. Measured at KW39/38/37 RF pins, with Vdd_RFx over 1.44 V and assuming an average Tx duty cycle <=24%. For Tx
output over +3.5 dBm, powered Vdd_RFx has to be higher than 1.44 V.
4. Measured at the KW39/38/37 RF pins.
5. Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.
6. Harmonic levels based on recommended 2 component match. Transmit harmonic levels depend on the quality of
matching components. Additional harmonic margin using a third matching component (1x shunt capacitor) is possible.
7. Measured at Pout = +5 dBm and recommended Tx match.
Transmit PA driver output as a function of the PA_POWER[5:0] field when measured
at the IC pins is as follows:
Figure 4. TX Pout (dBm) as function TX-PA Power Code at RF pins
Table 7. Transmit Output Power as a function of PA_POWER[5:0]
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
–30.15
–24.05
–18.06
–14.56
–12.08
T = 25 °C
–31.38
–25.25
–19.26
–15.76
–13.29
T = 105 °C
–32.25
–26.09
–20.11
–16.61
–14.15
1
2
4
6
8
Table continues on the next page...
28
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
Transceiver Electrical Characteristics
Table 7. Transmit Output Power as a function of PA_POWER[5:0] (continued)
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
–10.16
–8.59
–7.27
–6.16
–5.15
–4.25
–3.44
–2.70
–2.02
–1.39
–0.81
–0.34
0.18
T = 25 °C
–11.39
–9.82
–8.50
–7.39
–6.38
–5.48
–4.67
–3.94
–3.26
–2.64
–2.06
–1.58
–1.07
–0.59
–0.15
0.27
T = 105 °C
–12.24
–10.67
–9.36
–8.24
–7.24
–6.34
–5.53
–4.81
–4.14
–3.52
–2.95
–2.45
–1.95
–1.48
–1.04
–0.64
–0.24
0.14
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
0.66
1.10
1.52
1.92
0.65
2.30
1.03
2.67
1.39
0.49
2.99
1.71
0.80
3.32
2.04
1.14
3.63
2.35
1.44
3.92
2.64
1.74
4.19
2.91
2.00
4.44
3.17
2.27
4.68
3.41
2.51
4.90
3.64
2.74
1. Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
29
NXP Semiconductors
Transceiver Electrical Characteristics
Figure 5. TX Pout (dBm) as function TX-PA Power Code at RF pins (LDO-HF bumped)
Table 8. Transmit Output Power as a function of PA_POWER[5:0] at elevated PA supply
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
–28.48
–22.37
–16.39
–12.88
–10.38
–8.46
T = 25 °C
–29.55
–23.43
–17.45
–13.94
–11.45
–9.53
T = 105 °C
–30.38
–24.23
–18.26
–14.75
–12.27
–10.36
–8.79
1
2
4
6
8
10
12
14
16
18
20
22
24
–6.89
–7.96
–5.56
–6.63
–7.47
–4.43
–5.50
–6.34
–3.41
–4.49
–5.33
–2.51
–3.59
–4.43
–1.69
–2.77
–3.62
–0.94
–2.03
–2.89
Table continues on the next page...
30
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
System and Power Management
Table 8. Transmit Output Power as a function of PA_POWER[5:0] at elevated PA supply
(continued)
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
–0.26
0.36
0.96
1.44
1.95
2.42
2.88
3.32
3.74
4.14
4.50
4.83
5.16
5.46
5.75
6.02
6.26
6.49
6.71
T = 25 °C
–1.35
–0.72
–0.14
0.34
T = 105 °C
–2.22
–1.60
–1.03
–0.54
–0.04
0.44
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
0.85
1.32
1.77
0.88
2.20
1.31
2.62
1.71
3.01
2.09
3.38
2.45
3.71
2.78
4.04
3.11
4.35
3.41
4.64
3.70
4.91
3.96
5.16
4.22
5.40
4.45
5.62
4.67
1. Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.
5 System and Power Management
5.1 Power Management
The KW39/38/37 includes internal power management features that can be used to
control the power usage. The power management of the KW39/38/37 includes Power
Management Controller (PMC) and a DC-DC converter which can operate in a buck
or bypass configuration. The PMC is designed such that the RF radio remains in state-
retention while the core is in various stop modes. It makes sure that the device can
stay in low current consumption mode while the RF radio can wake-up quick enough
for communication.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
31
NXP Semiconductors
System and Power Management
5.1.1 DC-DC Converter
The features of the DC-DC converter include the following:
• Single inductor, multiple outputs.
• Buck mode (pin selectable; CFG=VDCDC_IN).
• Continuous or pulsed operation (hardware/software configurable).
• Power switch input to allow external control of power up, and to select DC-DC
bypass mode in which all the SoC power supplies (see Table 4) are externally
provided.
• Output signal to indicate power stable. Purpose is for the rest of the chip to be used
as a POR.
• Scaled battery output voltage suitable for SAR ADC utilization.
• Internal oscillator for support when the reference oscillator is not present.
5.2 Modes of Operation
The Arm Cortex-M0+ core in the KW39/38/37 has three primary modes of operation:
Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop
mode. Wait modes are similar to Arm sleep modes. Stop modes are similar to Arm deep
sleep modes. The very low-power run (VLPR) operation mode can drastically reduce
runtime power when the maximum bus frequency is not required to handle the
application needs.
The WFI instruction invokes both wait and stop modes. The primary modes are
augmented in a number of ways to provide lower power based on application needs.
5.2.1 Power modes
The power management controller (PMC) provides multiple power options to allow the
user to optimize power consumption for the level of functionality needed.
Depending on the stop requirements of the user application, various stop modes are
available that provide state retention, partial power down, or full power down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.
32
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
System and Power Management
For each run mode, there is a corresponding wait and stop mode. Wait modes are
similar to Arm sleep modes. Stop modes (VLPS, STOP) are similar to Arm sleep deep
mode. The very-low-power run (VLPR) operating mode can drastically reduce
runtime power when the maximum bus frequency is not required to handle the
application needs.
The three primary modes of operation are run, wait, and stop. The WFI instruction
invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System
Control Register. The primary modes are augmented in a number of ways to provide
lower power based on application needs.
Table 9. Power modes (At 25 deg C)
Power mode
Description
CPU
Radio
recovery
method
Normal Run (all
Allows maximum performance of chip.
—
Radio can be active
peripherals clock off)
Normal Wait - via
WFI
Allows peripherals to function, while allowing CPU
to go to sleep reducing power.
Interrupt
Interrupt
Normal Stop - via
WFI
Places chip in static state. Lowest power mode that
retains all registers while maintaining LVD
protection.
PStop2 (Partial Stop Core and system clocks are gated. Bus clock
Interrupt
2)
remains active. Masters and slaves clocked by bus
clock remain in Run or VLPRun mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
PStop1 (Partial Stop Core, system clocks, and bus clock are gated. All
Interrupt
—
1)
bus masters and slaves enter Stop mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
VLPR (Very Low-
power Run) (all
peripherals off)
Reduced frequency (1 MHz) Flash access mode,
regulator in low-power mode, LVD off. Internal
oscillator can provide low-power 4 MHz source for
core. (Values @2 MHz core/ 1 MHz bus and flash,
module off, execution from flash).
Radio operation is possible
only when DC-DC is
configured for continuous
mode.1 However, there may
be insufficient MIPS with a 4
MHz MCU to support much
in the way of radio operation.
Biasing is disabled when DC-DC is configured for
continuous mode in VLPR/W
VLPW (Very Low-
Similar to VLPR, with CPU in sleep to further reduce
Interrupt
Interrupt
power Wait) - via WFI power. (Values @4 MHz core/ 1 MHz bus, module
(all peripherals off)
off)
Biasing is disabled when DC-DC is configured for
continuous mode in VLPR/W
VLPS (Very Low-
Places MCU in static state with LVD operation off.
power Stop) via WFI Lowest power mode with ADC and all pin interrupts
functional. LPTMR, RTC, CMP can be operational.
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
33
NXP Semiconductors
System and Power Management
Table 9. Power modes (At 25 deg C) (continued)
Power mode
Description
CPU
Radio
recovery
method
Biasing is disabled when DC-DC is configured for
continuous mode in VLPS.
LLS3 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,
Wake-up
Interrupt
Radio SOG is in state
retention in LLSx. The
Bluetooth LE/Generic FSK
DSM2 logic can be active
using the 32 kHz clock
Stop)
CMP can be operational. All of the radio Sea of
Gates(SOG) logic is in state retention.
LLS2 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,
Wake-up
Interrupt
Stop)
CMP can be operational. 16 KB or 32 KB of
programmable RAM can be powered on. All of the
radio SOG logic is in state retention.
VLLS3 (Very Low
Leakage Stop3)
Full SRAM retention. LLWU, LPTMR, RTC, CMP
can be operational. Radio SoG logic is power gated
and Radio Tx/Rx RAM keeps state retention.
Wake-up
Reset
Radio SoG is power gated in
VLLS3/2. Radio Tx/Rx RAM
keeps state retention in
VLLS3 and can be
configurable power gated in
VLLS2. The Bluetooth LE/
Generic FSK DSM logic can
be active using the 32 KHz
clock.
VLLS2 (Very Low
Leakage Stop2)
Partial SRAM retention. 16 KB or 32 KB of
programmable RAM can be powered on. LLWU,
LPTMR, RTC, CMP can be operational. All of the
Radio SoG logic is power gated. Radio Tx/Rx
SRAM can be configurable power gated.
Wake-up
Reset
VLLS1 (Very Low
All SRAM powered off. The 32-byte system register
Wake-up
Reset
Radio operation not
supported. The Radio SOG
is power-gated in VLLS1.
Radio state is lost at VLLS1
and lower power states.
Leakage Stop1) with file remains powered for customer-critical data.
RTC + 32 kHz OSC LLWU, LPTMR, RTC, CMP can be operational.
Radio logic is power gated.
VLLS1 (Very Low
Leakage Stop1) with file remains powered for customer-critical data.
All SRAM powered off. The 32-byte system register
Wake-up
Reset
LPTMR + LPO
LLWU, LPTMR, RTC, CMP can be operational.
VLLS0 is not supported with DC-DC.
VLLS0 (Very Low
Wake-up
Reset
Radio operation not
supported. The Radio digital
is power-gated in VLLS0.
Leakage Stop0) with
Brown-out Detection
The 32-byte system register file remains powered
for customer-critical data. Disable all analog
modules in PMC and retains I/O state and DGO
state. LPO disabled, POR brown-out detection
enabled, Pin interrupt only. Radio logic is power
gated.
VLLS0 (Very Low
Leakage Stop0)
without Brown-out
Detection
VLLS0 is not supported with DC-DC buck
configuration but is supported with bypass
configuration.
Wake-up
Reset
The 32-byte system register file remains powered
for customer-critical data. Disable all analog
modules in PMC and retains I/O state and DGO
state. LPO disabled, POR brown-out detection
disabled, Pin interrupt only. Radio logic is power
gated.
1. Biasing is disabled, but the Flash is in a low-power mode for VLPx, so this configuration can realize some power savings
over use of Run/Wait/Stop.
2. DSM refers to Radio's deep sleep mode. DSM does not refer to the Arm sleep deep mode.
34
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
KW39/38/37 Electrical Characteristics
6 KW39/38/37 Electrical Characteristics
6.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 6. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
6.2 Nonswitching electrical specifications
6.2.1 Voltage and current operating requirements
Table 10. Voltage and current operating requirements
Symbol
Description
Min.
1.71
1.425
1.71
–0.1
–0.1
Max.
3.6
3.6
3.6
0.1
0.1
Unit
V
Notes
VDD
Supply voltage
VDD_1P5 DCDC VDD_1P5 output pin
VDDA Analog supply voltage
V
1
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
35
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 10. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
–3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS–0.3V
2
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
–25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
3
VDD voltage required to retain RAM
1. This limit applies in any DCDC mode.
2. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD
.
6.2.2 LVD and POR operating requirements
Table 11. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VPOR_VDD_ VDD_1P5 POR threshold
1.25
1.31
1.37
V
1P5
VLVDH
Falling low-voltage detect threshold — high
2.48
2.56
2.64
V
range (LVDV = 01)
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
Table continues on the next page...
36
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 11. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VHYSH Low-voltage inhibit reset/recover hysteresis —
—
60
—
mV
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
V
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low-power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
6.2.3 Voltage and current operating behaviors
Table 12. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
1, 2
VOH
Output high voltage — Normal drive pad (except
RESET_b)
VDD – 0.5
VDD – 0.5
VDD – 0.35
—
—
—
V
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -1 mA
VOH
Output high voltage — High drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
—
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — High drive pad
—
0.5
V
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
37
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 12. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
Min.
Max.
Unit
Notes
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
IOLT
IIN
Output low current total for all ports
—
—
100
500
mA
nA
Input leakage current (per pin) for full temperature
range
3
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
5
μA
μA
3
3
Input leakage current (total all pins) for full
temperature range
RPU
Internal pullup resistors
20
50
kΩ
4
1. PTB0-1, PTC1-4, PTC6-7, PTC16-19 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V.
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
.
6.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 13. Power mode transition operating behaviors
Symbol
Description
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8 V to execution of the first instruction across the
operating temperature range of the chip.
300
μs
1
• VLLS0 → RUN
169.0
168.9
97.3
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
Table continues on the next page...
38
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 13. Power mode transition operating behaviors (continued)
Symbol
Description
Max.
97.3
6.3
Unit
Notes
• VLLS3 → RUN
μs
• LLS → RUN
• VLPS → RUN
• STOP → RUN
μs
6.2
μs
6.2
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300
µs spec when 1) VDD_1P5 < 1.6 V at 25 °C and 125 °C. 2) 1.5V ≤ VDD_1P5 ≤ 1.8 V. For the bypass mode special
case where VDD_1P5 = VDD_1P8, TPOR did not meet the 300 µs maximum spec when the supply slew rate <=100
V/s.
6.2.5 Power consumption operating behaviors
Table 14. Power consumption operating behaviors - Bypass Mode
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
1
0
1
IDDA
Analog supply current
—
See note
mA
IDD_RUNCO_CM Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus disabled,
LPTMR running using LPO clock at 1kHz,
CoreMark benchmark code executing from
flash at 3.0 V
2, 3
6.73
3.84
9.94
6.95
mA
mA
2
3
IDD_RUNCO
Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash at
3.0 V
3, 4
2, 3
IDD_RUN_CM Run mode current - 48 MHz core/24 MHz bus
and flash, all peripheral clocks disabled,
CoreMark benchmark code executing from
flash at 3.0 V
6.72
4.46
9.93
7.50
mA
mA
4
5
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code
of while(1) loop executing from flash at 3.0 V
3, 4
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code of
while(1) loop executing from flash at 3.0 V
3, 4, 5
5.59
5.72
6.22
6.03
6.96
8.60
mA
mA
mA
at 25 °C
at 70 °C
at 105 °C
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
39
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 14. Power consumption operating behaviors - Bypass Mode (continued)
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
6
IDD_WAIT
Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at
3.0 V
4
2.48
5.70
mA
7
IDD_WAIT
Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at
3.0 V
4
1.95
5.20
mA
8
9
IDD_PSTOP2 Stop mode current with partial stop 2 clocking
option - core and system disabled / 10.5 MHz
bus at 3.0 V
4
6
2.31
5.60
mA
μA
IDD_VLPRCO_CM Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, LPTMR running using LPO
750.90
2162.15
clock at 1 kHz reference clock, CoreMark
benchmark code executing from flash at 3.0 V
10
11
12
13
14
15
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, code of while(1) loop executing
from flash at 3.0 V
7
7
157.56
1197.82
μA
IDD_VLPR_CM Very-low-power run mode current -4 MHz
core/0.8 MHz bus and flash, all peripheral
clocks disabled, CoreMark benchmark code
executing from flash at 3.0 V
749.12
176.75
2169.25
1217.35
μA
μA
IDD_VLPR
IDD_VLPR
IDD_VLPW
IDD_STOP
Very-low-power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks disabled, code of while(1) loop
executing from flash at 3.0 V
7
Very-low-power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks enabled, code of while(1) loop executing
from flash at 3.0 V
5, 7
7
225.92
115.97
1261.85
988.58
μA
μA
Very-low-power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus / flash
disabled (flash doze enabled), all peripheral
clocks disabled at 3.0 V
Stop mode current at 3.0 V
at 25 °C
233.19
334.36
714.91
395.00
1238.67
2854.74
μA
μA
μA
at 70 °C
at 105 °C
16
IDD_VLPS
Very-low-power stop mode current at Bypass
mode(3.0 V),
5.99
44.41
181.39
37.86
239.01
740.69
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
Table continues on the next page...
40
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 14. Power consumption operating behaviors - Bypass Mode (continued)
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
17
IDD_LLS3
Low-leakage stop mode 3 current at Bypass
mode(3.0 V),
3.04
16.27
61.37
7.96
54.57
185.22
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
18
19
20
21
IDD_LLS2
Low-leakage stop mode 2 current at Bypass
mode(3.0 V),
2.67
13.39
50.32
6.17
49.00
142.43
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_VLLS3
Very-low-leakage stop mode 3 current at
Bypass mode(3.0 V),
2.23
12.14
46.73
5.35
46.10
126.37
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at
Bypass mode(3.0 V),
1.67
6.58
2.53
25.82
57.92
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
25.32
IDD_VLLS2_32KB Very-low-leakage stop mode 2 current at
Bypass mode (3.0 V) (set
SMC_STOPCTRL[RAM2PO]=1 based on
IDD_VLLS2_16KB configuration),
1.84
8.10
—
—
—
μA
μA
μA
at 25 °C
at 70 °C
29.47
at 105 °C
22
IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at
Bypass mode (3.0 V) (set
_RF_Tx_RAM
RSIM_CONTROL[TXRAMPO]=1 based on
IDD_VLLS2_16KB configuration),
1.75
7.83
—
—
—
μA
μA
μA
at 25 °C
at 70 °C
28.32
at 105 °C
23
IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at
Bypass mode (3.0 V) (set
_RF_Rx_RAM
RSIM_CONTROL[RXRAMPO]=1 based on
IDD_VLLS2_16KB configuration),
1.75
7.65
—
—
—
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
27.73
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
41
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 14. Power consumption operating behaviors - Bypass Mode (continued)
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
24
IDD_VLLS1
Very-low-leakage stop mode 1 current at
Bypass mode(3.0 V),
917.42
3.24
1355.71
13.32
nA
μA
μA
at 25 °C
at 70 °C
at 105 °C
15.62
32.08
25
26
IDD_VLLS0
Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
467.55
2.78
998.32
13.05
31.48
nA
μA
μA
at 25 °C
at 70 °C
at 105 °C
15.11
IDD_VLLS0
Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
8
266.64
2.54
737.22
13.02
31.12
nA
μA
μA
at 25 °C
at 70 °C
at 105 °C
14.78
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
specifications of each module for its supply current.
2. MCG configured for FEI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for
balanced.
3. Radio is off.
4. MCG configured for FEI mode.
5. Incremental current consumption from peripheral activity is not included.
6. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized
for balanced.
7. MCG configured for BLPI mode.
8. No brownout.
Table 15. Power consumption operating behaviors - Buck Mode
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
1
0
1
IDDA
Analog supply current
—
See note
mA
IDD_RUNCO_CM Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
LPTMR running using LPO clock at 1 kHz,
CoreMark benchmark code executing from flash
at 3.0 V
2, 3
4.97
3.13
—
—
mA
mA
2
3
IDD_RUNCO Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash at 3.0
V
2, 3
2, 3
IDD_RUN_CM Run mode current - 48 MHz core/24 MHz bus
and flash, all peripheral clocks disabled,
CoreMark benchmark code executing from flash
at 3.0 V
4.88
—
mA
Table continues on the next page...
42
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 15. Power consumption operating behaviors - Buck Mode (continued)
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
4
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code of
while(1) loop executing from flash at 3.0 V
2, 3
3.37
—
mA
5
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code of
while(1) loop executing from flash at 3.0 V
2, 3, 4
4.09
4.22
4.60
—
—
—
mA
mA
mA
at 25 °C
at 70 °C
at 105 °C
6
7
8
9
IDD_WAIT
Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled at 3.0 V
2
2
2
5
2.36
2.09
2.32
—
—
—
mA
mA
mA
IDD_WAIT
Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled at 3.0 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking
option - core and system disabled / 10.5 MHz
bus at 3.0 V
IDD_VLPRCO_C Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
M
clock disabled, CoreMark benchmark code
executing from flash at 3.0 V
563.18
152.88
—
—
μA
μA
10
11
12
13
14
15
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, code of while(1) loop executing
from flash at 3.0 V
5
5
IDD_VLPR_CM Very-low-power run mode current - 4 MHz
core/0.8 MHz bus and flash, all peripheral clocks
disabled, CoreMark benchmark code executing
from flash at 3.0 V
558.88
150.33
—
—
μA
μA
IDD_VLPR
IDD_VLPR
IDD_VLPW
IDD_STOP
Very-low-power run mode current - 4 MHz core /
0.8 MHz bus and flash, all peripheral clocks
disabled, code of while(1) loop executing from
flash at 3.0 V
5
Very-low-power run mode current - 4 MHz core /
0.8 MHz bus and flash, all peripheral clocks
enabled, code of while(1) loop executing from
flash at 3.0 V
4, 5
5
207.02
113.53
—
—
μA
μA
Very-low-power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus / flash
disabled (flash doze enabled), all peripheral
clocks disabled at 3.0 V
Stop mode current at 3.0 V
at 25 °C
1.65
1.82
2.15
2.712
4.728
7.686
mA
mA
mA
at 70 °C
at 105 °C
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
43
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 15. Power consumption operating behaviors - Buck Mode (continued)
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
16
IDD_VLPS
Very-low-power stop mode current at Buck
mode(3.0 V),
7.34
58.34
276.96
39.203
252.935
836.252
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
17
18
19
20
21
IDD_LLS3
IDD_LLS2
IDD_VLLS3
Low-leakage stop mode 3 current at Buck
mode(3.0 V),
2.95
20.42
86.84
7.547
58.722
210.696
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
Low-leakage stop mode 2 current at Buck
mode(3.0 V),
2.61
13.90
47.87
5.975
49.512
139.983
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
Very-low-leakage stop mode 3 current at Buck
mode(3.0 V),
2.17
11.14
40.37
5.283
45.099
120.006
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at Buck
mode(3.0 V),
1.41
5.69
2.236
24.923
53.843
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
21.24
IDD_VLLS2_32KB Very-low-leakage stop mode 2 current at Buck
mode (3.0 V) (set
SMC_STOPCTRL[RAM2PO]=1 based on
IDD_VLLS2_16KB configuration),
1.85
7.92
—
—
—
μA
μA
μA
at 25 °C
at 70 °C
28.84
at 105 °C
22
IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at Buck
mode (3.0 V) (set
_RF_Tx_RAM
RSIM_CONTROL[TXRAMPO]=1 based on
IDD_VLLS2_16KB configuration),
1.68
7.56
—
—
—
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
27.97
Table continues on the next page...
44
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 15. Power consumption operating behaviors - Buck Mode (continued)
Mode#
Symbol
Description
Typ.
Max.
Unit
Notes
23
IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at Buck
mode (3.0 V) (set
_RF_Rx_RAM
RSIM_CONTROL[RXRAMPO]=1 based on
IDD_VLLS2_16KB configuration),
1.91
6.81
—
—
—
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
25.64
24
IDD_VLLS1
Very-low-leakage stop mode 1 current at Buck
mode(3.0 V),
976.17
2.98
1414.459
13.053
nA
μA
μA
at 25 °C
at 70 °C
at 105 °C
13.18
29.640
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See specification of each module for its supply current.
2. MCG configured for FEI mode.
3. Radio is off.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode.
Table 16. Low power mode peripheral adders — typical value (Bypass Mode)
Adder#
Symbol
Description
Temperature (°C)
25 50 70
Unit
–40
85
1
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
47.50 47.50 47.51 47.39 47.12
µA
VLPS mode with 4 MHz IRC enabled.
2
3
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
92.82 92.82 92.61 91.89 91.91
µA
mode with the 32 kHz IRC enabled.
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the RTC bits. Measured by
entering all modes with the crystal
enabled.
1.24
1.23
1.22
1.22
1.21
1.23
1.22
1.22
1.21
1.21
1.25
1.23
1.12
1.12
1.22
1.29
1.16
1.16
1.28
1.32
1.25
1.26
1.21
1.30
1.26
VLLS1
VLLS2
VLLS3
LLS2
μA
µA
LLS3
4
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
21.15 21.15 21.39 21.55 21.76
consumption.
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
45
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 16. Low power mode peripheral adders — typical value (Bypass Mode) (continued)
Adder#
Symbol
Description
Temperature (°C)
Unit
–40
25
1.24
50
70
1.32
85
5
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
1.25
1.25
1.31
µA
6
7
8
ILPUART
ILPTMR
ITPM
LPUART peripheral adder measured
by placing the device in STOP or
VLPS mode with selected clock source
waiting for Rx data at 115200 baud
rate. Includes selected clock source
power consumption.
58.73 58.73 59.13 59.32 59.67
µA
MCGIRCLK (4 MHz internal reference
clock)
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
31.32 31.30 34.49 65.73 100.58 nA
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No
load is placed on the I/O generating
the clock signal. Includes selected
clock source and I/O switching
currents.
56.93 56.92 56.99 56.92 56.84
90.49 90.48 91.85 91.74 88.16
µA
µA
MCGIRCLK (4 MHz internal reference
clock)
9
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
10
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low-
power mode using the internal clock
and continuous conversions.
347.96 347.96 346.12 347.88 346.43 µA
46
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
6.2.6 Diagram: Typical IDD_RUN operating behavior
The following data is measured from previous devices with same MCU core (Arm®
Cortex-M0+) under these conditions:
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
NOTE
The results in the following graphs are obtained using the
device in Bypass mode.
Figure 7. Run mode supply current vs. core frequency
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
47
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Figure 8. VLPR mode current vs. core frequency
6.2.7 SoC Power Consumption
Full KW39/38/37 system-on-chip (SoC) power consumption is a function of the many
configurations possible for the MCU platform and its peripherals including the 2.4 GHz
radio and the DC-DC converter. A few measured SoC configurations are as follows:
Table 17. SoC Power Consumption
MCU State
Flash State
Radio State
DC-DC State
Typical
Average IC
current
Unit
STOP
STOP
STOP
Doze
Doze
Doze
Rx
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
8.5
7.8
9.2
mA
mA
mA
Tx (at 0 dBm)
Tx (at +3.5
dBm)
STOP
RUN
RUN
Doze
Tx (at +5 dBm)1
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
10.3
10.4
9.9
mA
mA
mA
Enabled
Enabled
Rx
Tx (at 0 dBm)
Table continues on the next page...
48
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 17. SoC Power Consumption (continued)
MCU State
Flash State
Radio State
DC-DC State
Typical
Average IC
current
Unit
RUN
Enabled
Tx (at +3.5
dBm)
Buck (VDCDC_IN=3.6 V)
11.7
mA
RUN
STOP
STOP
STOP
Enabled
Doze
Tx (at +5 dBm)1
Buck (VDCDC_IN=3.6 V)
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
12.8
17.3
15.9
18.3
mA
mA
mA
mA
Rx
Doze
Tx (at 0 dBm)
Doze
Tx (at +3.5
dBm)
STOP
RUN
RUN
RUN
Doze
Tx (at +5 dBm)1
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
20.3
21.5
19.9
22.4
mA
mA
mA
mA
Enabled
Enabled
Enabled
Rx
Tx (at 0 dBm)
Tx (at +3.5
dBm)
RUN
Enabled
Tx (at +5 dBm)1
Disabled/Bypass
24.4
mA
1. MCU configured to use an FLL-based 20 MHz clock.
6.2.8 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com
2. Perform a keyword search for “KW38, HW guideline, RF system evaluation.”
6.2.9 Capacitance attributes
Table 18. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
6.3 Switching electrical specifications
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
49
NXP Semiconductors
KW39/38/37 Electrical Characteristics
6.3.1 Device clock specifications
Table 19. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
LPTMR clock2
1
24
16
16
8
External reference clock
fLPTMR_ERCLK LPTMR external reference clock
fTPM
TPM asynchronous clock
fLPUART0
LPUART0 asynchronous clock
12
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS entered from RUN or
from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
6.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO,
LPUART, CAN (for KW38 only), CMT and I2C signals.
Table 20. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5
—
Bus clock cycles
1, 2
NMI_b pin interrupt pulse width (analog filter enabled) —
Asynchronous path
200
20
—
—
—
ns
ns
ns
3
3
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled) — Asynchronous path
External RESET_b input pulse width (digital glitch filter
disabled)
100
Port rise and fall time(high drive strength)
• Slew enabled
4, 5
—
—
25
16
ns
ns
Table continues on the next page...
50
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 20. General switching specifications (continued)
Description
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew disabled
Min.
Max.
Unit
Notes
—
8
ns
—
6
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
Port rise and fall time(low drive strength)
6, 7
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew disabled
—
—
24
16
10
6
ns
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
—
—
ns
ns
1. This is the minimum pulse width that guarantees to pass through the pin synchronization circuitry in run modes.
2. The greater of synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that guarantees to be recognized.
4. PTB0, PTB1, PTC1, PTC2, PTC3, PTC4, PTC6, PTC7, PTC16, PTC17, PTC18, PTC19.
5. 75 pF load.
6. Ports A, B, and C.
7. 25 pF load.
6.4 Thermal specifications
6.4.1 Thermal operating requirements
Table 21. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
51
NXP Semiconductors
KW39/38/37 Electrical Characteristics
6.4.2 Thermal attributes
Table 22. Thermal attributes
Board type
Symbol
Description
48-pin
"Wettable"
HVQFN
Unit
Notes
Four-layer (2s2p)
—
RθJA
Thermal resistance, junction to
ambient (natural convection)
21.4
°C/W
°C/W
1, 2
1, 3
ΨJT
Thermal characterization parameter,
junction to package top (natural
convection)
0.2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
construction.
2. Determined according to JEDEC Standard JESD51-2A.
3. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2A.
The thermal characterization parameter (ΨJT) is used to determine the junction
temperature with a measurement of the temperature at the top of the package case using
the following equation:
TJ = TT + ΨJT x chip power dissipation
where TT is the thermocouple temperature at the top of the package.
6.5 Peripheral operating requirements and behaviors
6.5.1 Core modules
6.5.1.1 SWD electricals
Table 23. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
—
3
ns
ns
J4
SWD_CLK rise and fall times
Table continues on the next page...
52
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
Table 23. SWD full voltage range electricals (continued)
Symbol
J9
Description
SWD_DIO input data setup time to SWD_CLK rise
Min.
10
Max.
Unit
ns
—
J10
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
0
—
5
—
32
—
ns
J11
ns
J12
ns
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 9. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 10. Serial wire data timing
6.5.2 System modules
There are no specifications necessary for the device's system modules.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
53
NXP Semiconductors
KW39/38/37 Electrical Characteristics
6.5.3 Clock modules
6.5.3.1 MCG specifications
Table 24. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/–0.7
0.4
3
%fdco
%fdco
1, 2
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/–2
11
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
ffll_ref
fdco
DCO output
Low range (DRS = 00)
20.97
MHz
3, 4
5, 6
frequency range
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
40
—
—
—
—
41.94
23.99
47.97
180
48
—
—
—
1
MHz
MHz
MHz
ps
fdco_t_DMX3 DCO output
Low range (DRS = 00)
732 × ffll_ref
frequency
2
Mid range (DRS = 01)
1464 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
7
8
tfll_acquire FLL target frequency acquisition time
—
ms
54
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
KW39/38/37 Electrical Characteristics
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the following changes: FLL reference source or reference divider, trim value,
DMX32 bit, DRS bits, or FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
used as the reference, this specification assumes it is already running.
6.5.3.2 Reference Oscillator Specification
The KW39/38/37 has been designed to meet targeted standard specifications for
frequency error over the life of the part, which includes the temperature, mechanical
and aging effects.
The table below lists the recommended crystal specifications. Note that these are
recommendations only and deviation may be allowed. However, deviations may result
in degraded RF performance or possibly a failure to meet RF protocol certification
standards. Designers must ensure that the crystal(s) they use meet the requirements of
their application.
Table 25. Recommended Crystal and Oscillator Specification
Symbol
Description
F0 = 32.0 MHz
F0 = 26.0 MHz
Unit
Notes
Min
Typ
Max
Min
Typ
Max
TA
Operating
–40
—
105
–40
—
105
°C
1
Temperature
Crystal initial
frequency
tolerance
–10
—
—
10
25
–10
–25
—
10
24
ppm
2,3
2,4
Crystal frequency –25
stability and aging
—
ppm
Oscillator variation –12
—
—
15
50
–12
–50
—
—
16
50
ppm
ppm
5
6
Total reference
oscillator tolerance
for Bluetooth LE
applications
–50
CL
Load capacitance
7
10
13
7
10
13
pF
pF
fF
2, 7
2,7
2,7
C0
Shunt capacitance 0.469
0.67
2.05
0.871
2.665
0.42
1.435
0.6
2.05
0.78
2.665
Cm1
Motional
1.435
capacitance
Lm1
Motional
8.47
12.1
15.73
12.81
18.3
23.79
mH
2,7
inductance
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
55
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 25. Recommended Crystal and Oscillator Specification (continued)
Symbol
Description
F0 = 32.0 MHz
F0 = 26.0 MHz
Unit
Notes
Min
Typ
Max
Min
Typ
Max
Rm1
ESR
Pd
Motional
resistance
—
25
50
—
35
—
10
50
Ohms
Ohms
uW
2
Equivalent series
resistance
—
—
—
60
—
—
60
2,8
2
Maximum crystal
drive
10
200
200
TS
Trim sensitivity
6.30
—
9.00
500
11.70
—
6.39
—
9.12
500
11.86
—
ppm/pF 2,7
μs
TOSC
Oscillator Startup
Time
9
1. Full temperature range of this device. A reduced range can be chosen to meet application needs.
2. Recommended crystal specification.
3. Measured at 25 °C.
4. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over
desired lifetime of system.
5. Variation due to temperature, process, and aging of MCU.
6. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB
manufacturing variation must not exceed this value.
7. Typical is target. 30% tolerances shown.
8. ESR = Rm1 * (1 + [C0/CL])^2.
9. Time from oscillator enable to clock ready. Dependent on the complete hardware configuration of the oscillator.
Figure 11. Crystal Electrical Model
56
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
KW39/38/37 Electrical Characteristics
6.5.3.3 32 kHz Oscillator Frequency Specifications
Table 26. 32 kHz Crystal and Oscillator Specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Crystal
—
32.768
—
kHz
frequency
TA
Operating
temperature
–40
—
—
105
500
°C
1
Total crystal
frequency
tolerance
–500
ppm
2,3
CL
Load
capacitance
—
—
12.5
—
—
pF
2
2
ESR
Equivalent
series
80
kOhms
resistance
tstart
Crystal start-up
time
—
1000
32.768
—
—
ms
kHz
V
4
5
6
fec_extal32
vec_extal32
External input
clock frequency
—
—
External input
0.7
VDD
clock amplitude
1. Full temperature range of this device. A reduced range can be chosen to meet application needs.
2. Recommended crystal specification.
3. Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.
4. Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.
5. External oscillator connected to EXTAL32K. XTAL32K must be unconnected.
6. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VDD.
6.5.4 Memories and memory interfaces
6.5.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
6.5.4.1.1 Flash timing specifications — commands
Table 27. Flash command timing specifications
Symbol Description1
Read 1s Block execution time
• 256 KB program/data flash
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
—
—
2
ms
trd1sec2k Read 1s Section execution time (2 KB flash)
tpgmchk Program Check execution time
—
—
—
—
75
95
μs
μs
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
57
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 27. Flash command timing specifications (continued)
Symbol Description1
trdrsrc Read Resource execution time
tpgm8
Min.
—
Typ.
—
Max.
40
Unit
μs
Notes
Program Phrase execution time
Erase Flash Block execution time
• 256 KB program/data flash
—
90
225
μs
2
2
tersblk256k
tersscr
—
125
2125
ms
Erase Flash Sector execution time
—
—
12
10
130
—
ms
ms
tpgmsec2k Program Section execution time (2 KB flash)
Read 1s All Blocks execution time
trd1allx
trd1alln
• FlexNVM devices
—
—
—
—
3.5
3.5
ms
ms
• Program flash only devices
trdonce
Read Once execution time
—
—
—
—
—
—
90
30
—
μs
μs
tpgmonce Program Once execution time
tersall
tvfykey
tersallu
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
Swap Control execution time
• control code 0x01
262
—
4380
35
ms
μs
2
2
262
4380
ms
tswapx01
tswapx02
tswapx04
tswapx08
tswapx10
—
—
—
—
—
280
100
100
—
—
μs
μs
μs
μs
μs
• control code 0x02
235
235
35
• control code 0x04
• control code 0x08
• control code 0x10
100
235
Program Partition for EEPROM execution time
• 32 KB EEPROM backup
tpgmpart32k
tpgmpart256k
—
—
252
262
—
—
ms
ms
• 256 KB EEPROM backup
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram256k
—
—
—
115
0.8
—
μs
ms
ms
• 32 KB EEPROM backup
• 256 KB EEPROM backup
1.2
4.5
6.1
Byte-write to FlexRAM execution time:
• 32 KB EEPROM backup
3
3
3
teewr8b32k
—
—
385
1700
3800
μs
μs
teewr8b256k
• 256 KB EEPROM backup
1015
16-bit write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr16b32k
teewr16b256k
—
—
385
1700
μs
μs
• 256 KB EEPROM backup
1015
360
3800
2000
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
μs
Table continues on the next page...
58
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 27. Flash command timing specifications (continued)
Symbol Description1
32-bit write to FlexRAM execution time:
Min.
Typ.
Max.
Unit
Notes
3
teewr32b32k
teewr32b256k
• 32 KB EEPROM backup
• 256 KB EEPROM backup
—
—
630
2000
4100
μs
μs
1890
1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/
external clocks).
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. First time EERAM writes after a Reset or SETRAM command may incur additional overhead for EEE cleanup,
resulting in up to 2x the times shown.
NOTE
Under certain circumstances maximum times for writes to
FlexRAM may be exceeded. In this case the user or
application may wait, or assert reset to the FTFE module to
stop the operation.
6.5.4.1.2 Reliability specifications (Automotive)
Table 28. NVM reliability specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Program and Data Flash
tnvmret1k Data retention after up to 1 K cycles
nnvmcyc Cycling endurance
20
—
—
—
—
years
1
2
1 K
cycles
FlexRAM as Emulated EEPROM
5
tnvmretee Data retention
Write endurance
nnvmwree16
—
—
years
1, 3
4, 5, 6
• EEPROM backup to FlexRAM used ratio =
100 K
1.6 M
—
—
—
—
writes
writes
16
nnvmwree256
• EEPROM backup to FlexRAM used ratio =
256
1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.
2. Program and Erase are supported across product temperature specification. Cycling endurance is per flash sector.
3. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5
years.
4. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product
temperature specification. Greater write endurance may be achieved with larger ratios of EEPROM backup to
FlexRAM.
5. For usage of any EEE driver other than the FlexMemory feature, the endurance specification falls back to the Data
Flash endurance value of 1 K.
6. FlexMemory calculator tool is available on the NXP web site for help in estimating the maximum write endurance
achievable at specific EEPROM/FlexRAM ratios. The "In Spec" portions of the online calculator refer to the NVM
reliability specifications section of the data sheet. This calculator only applies to the Kinetis FlexMemory feature.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
59
NXP Semiconductors
KW39/38/37 Electrical Characteristics
6.5.4.1.3 Reliability specifications (Industrial)
Table 29. NVM reliability specifications
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
nnvmcycee Cycling endurance for EEPROM backup
Write endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
20 K
2
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
140 K
1.26 M
5 M
400 K
3.2 M
12.8 M
50 M
—
—
—
—
writes
writes
writes
writes
20 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ 125 °C influenced by the
cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit or
32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
6.5.4.1.4 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
60
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
KW39/38/37 Electrical Characteristics
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application.
6.5.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.5.6 Analog
6.5.6.1 ADC electrical specifications
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications. The following specification is defined with the DC-DC converter
operating in Bypass mode.
6.5.6.1.1 16-bit ADC operating conditions
Table 30. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
–100
–100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
3
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
3
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VSSA
VSSA
—
—
31/32 ×
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
kΩ
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
2
5
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
4
5
—
—
—
5
kΩ
fADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
18.0
MHz
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
61
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 30. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
fADCK
ADC conversion 16-bit mode
clock frequency
2.0
—
12.0
MHz
5
Crate
ADC conversion ≤ 13-bit modes
rate
6
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
kS/s
kS/s
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
6
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet are derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 12. ADC input impedance equivalency diagram
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KW39/38/37 Electrical Characteristics
6.5.6.1.2 16-bit ADC electrical characteristics
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC asynchronous
clock source
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
2.4
4.0
5.2
6.2
MHz tADACK =
1/fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
DNL Differential non-
linearity
• 12-bit mode; Buck
Mode6
• 12-bit mode; Bypass
Mode
—
—
0.7
0.5
–1.1 to +1.9
–1.1 to +1.9
INL
Integral non-
linearity
• 12-bit mode; Buck
Mode6
• 12-bit mode; Bypass
Mode
—
—
1.0
0.6
–2.7 to +1.9
–2.7 to +1.9
LSB4
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4 VADIN
VDDA
=
5
Quantization error
LSB4
0.5
ENOB Effective number of 16-bit differential mode; Buck
7
bits
Mode6
12
12.75
11.75
—
—
bits
• Avg = 32
• Avg = 4
11.25
16-bit single-ended mode;
Buck Mode6
• Avg = 32
• Avg = 4
11
11.5
10.5
—
—
9.5
16-bit differential mode;
Bypass Mode
• Avg = 32
• Avg = 4
12.5
13
12
—
—
11.25
16-bit single-ended mode;
Bypass Mode
11
11.75
—
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Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
• Avg = 32
• Avg = 4
10
10.5
—
Signal-to-noise
SINAD
See ENOB
6.02 × ENOB + 1.76
dB
plus distortion
THD Total harmonic
distortion
16-bit differential mode; Buck
Mode6
8
• Avg = 32
—
—
–90
–88
—
dB
16-bit single-ended mode;
Buck Mode6
• Avg = 32
—
—
—
16-bit differential mode;
Bypass Mode
• Avg = 32
—
—
–89
16-bit single-ended mode;
Bypass Mode
• Avg = 32
See ENOB
–87
Signal-to-noise
SINAD
6.02 × ENOB + 1.76
dB
dB
plus distortion
SFDR Spurious free
dynamic range
distortion
16-bit differential mode; Buck
Mode6
8
• Avg = 32
85
85
89
87
—
16-bit single-ended mode;
Buck Mode6
• Avg = 32
—
—
—
16-bit differential mode;
Bypass Mode
• Avg = 32
87
85
94
16-bit single-ended mode;
Bypass Mode
• Avg = 32
88
EIL
Input leakage error
IIn × RAS
mV
IIn =
leakage
current
(see
Voltage
and
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.67
1.74
1.81
mV/°
C
9
Table continues on the next page...
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KW39/38/37 Electrical Characteristics
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
VTEMP25 Temp sensor
voltage
25 °C
706
716
726
mV
9
1. All accuracy numbers assume that the ADC is calibrated with VREFH = VDDA
.
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low-
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N.
5. ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).
6. VREFH = Output of Voltage Reference(VREF).
7. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
9. ADC conversion clock < 3 MHz.
6.5.6.2 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Min.
Max.
Unit
V
Notes
Supply voltage
Temperature
1.71
3.6
–40 to 105
100
°C
nF
CL
Output load capacitance
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/–25% of the nominal specified CL value over the operating temperature
range of the device.
Table 33. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.190
1.1950
1.2
V
1
nominal VDDA and temperature=25 °C
Vout
Voltage reference output with user trim at
nominal VDDA and temperature=25 °C
1.1945
1.1950
1.1955
V
1
Vstep
Vtdrift
Voltage reference trim step
—
—
0.5
—
—
mV
mV
1
1
Temperature drift (Vmax -Vmin across the full
temperature range)
20
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
Low-power buffer current
High-power buffer current
1
1
Ihp
ΔVLOAD Load regulation
1, 2
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65
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KW39/38/37 Electrical Characteristics
Table 33. VREF full-range operating behaviors (continued)
Symbol Description
• current = 1.0 mA
Min.
Typ.
Max.
Unit
Notes
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax –Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
70
°C
Table 35. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vtdrift
Temperature drift (Vmax –Vmin across the limited
temperature range)
—
15
mV
6.5.6.3 CMP and 6-bit DAC electrical specifications
Table 36. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
Output high
Output low
VDD – 0.5
—
—
—
—
V
V
0.5
Table continues on the next page...
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KW39/38/37 Electrical Characteristics
Table 36. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
tDHS
Description
Min.
20
Typ.
50
250
—
Max.
200
600
40
Unit
ns
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
tDLS
80
ns
—
μs
IDAC6b
INL
—
7
—
μA
LSB3
6-bit DAC integral non-linearity
–0.5
–0.3
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
—
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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KW39/38/37 Electrical Characteristics
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.5.7 Timers
See General switching specifications.
6.5.8 Communication interfaces
6.5.8.1 CAN switching specifications
See General switching specifications.
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6.5.8.2 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. See
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 37. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
12
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
–2
8.5
—
—
—
ns
ns
ns
ns
16.2
0
1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS1
DS3
DS2
DS4
SPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
SPI_SIN
DS5
DS6
First data
Data
Last data
SPI_SOUT
Figure 15. DSPI classic SPI timing — master mode
Table 38. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
6
Unit
V
Operating voltage
2.7
Frequency of operation
MHz
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Table 38. Slave mode DSPI timing (limited voltage range) (continued)
Num
DS9
Description
DSPI_SCK input cycle time
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
DSPI_SCK to DSPI_SOUT valid
—
0
21.4
—
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
2.6
7.0
—
—
—
—
14
14
SPI_SS
DS10
DS9
SPI_SCK
(POL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
SPI_SOUT
Data
Data
DS13
First data
Last data
SPI_SIN
Figure 16. DSPI classic SPI timing — slave mode
6.5.8.3 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. See the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 39. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
12
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DSPI_SCK output cycle time
DSPI_SCK output high/low time
2 x tBUS
—
(tSCK/2) – 4 (tSCK/2) + 4
Table continues on the next page...
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Table 39. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
–1.2
23.3
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS1
DS3
DS2
DS4
SPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
SPI_SIN
DS5
DS6
First data
Data
Last data
SPI_SOUT
Figure 17. DSPI classic SPI timing — master mode
Table 40. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
6
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) – 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
29.1
—
ns
ns
3.2
7.0
—
—
—
ns
—
ns
25
25
ns
ns
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SPI_SS
DS10
DS9
SPI_SCK
DS15
DS12
DS16
DS11
(POL=0)
First data
DS14
Last data
SPI_SOUT
Data
Data
DS13
First data
Last data
SPI_SIN
Figure 18. DSPI classic SPI timing — slave mode
6.5.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 41. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
0.91
—
µs
ns
ns
Data set-up time
5,
5,
Rise time of SDA and SCL signals
1000
20 +0.1Cb
300
6
Fall time of SDA and SCL signals
Set-up time for STOP condition
tf
—
300
20 +0.1Cb
300
ns
6
tSU; STO
tBUF
4
—
—
0.6
1.3
—
—
µs
µs
Bus free time between STOP and
START condition
4.7
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF.
4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.
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5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
6. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 19. Timing definition for fast and standard mode devices on the I2C bus
6.5.8.5 LPUART
See General switching specifications.
6.5.9 Human-machine interfaces (HMI)
6.5.9.1 GPIO
The maximum input voltage on PTC0/1/2/3 is VDD+0.3V. For rest of the GPIO
specification, see General switching specifications.
6.6 DC-DC Converter Operating Requirements
Table 42. DC-DC Converter operating conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Bypass Mode Supply Voltage (RF and Analog)
VDDRF1
VDDRF2
,
,
1.425
—
3.6
Vdc
VDDRF3, VDD_1P5
Bypass Mode Supply Voltage (Digital)
VDDX, VDCDC_IN
VDDA
,
1.71
2.1
—
—
3.6
3.6
Vdc
Vdc
Buck Mode Supply Voltage 1, 2
DC-DC Inductor
Value
VDCDC_IN
—
10
—
μH
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Table 42. DC-DC Converter operating conditions (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
ESR
—
<0.2
<0.5
Ohms
1. In Buck mode, DC-DC converter needs 2.1 V minimum to start, the supply can drop to 1.8 V after DC-DC converter
settles.
2. In Buck mode, DC-DC converter generates 1.8 V at VDD_1P8OUT and 1.5 V at VDD_1P5OUT_PMCIN pins.
VDD_1P8OUT should supply to VDD1, VDD2 and VDDA. VDD_1P5OUT_PMCIN should supply to VDD_RF1 and
VDD_RF2. VDD_RF3 can be either supplied by 1.5 V or 1.8 V.
Table 43. DC-DC Converter Specifications
Characteristics
Conditions
Symbol
Min
—
Typ
—
Max
1951
1401
Unit
mW
mW
DC-DC Converter Output
Power (total power output of
1p8V and 1p5V)
VDCDC_IN above 2.7 V Pdcdc_out1
VDCDC_IN below 2.7 V Pdcdc_out2
—
—
Switching Frequency2
Half FET Threshold
Double FET Threshold
Buck Mode
DCDC_FREQ
I_half_FET
—
—
—
2
5
—
—
—
MHz
mA
I_double_FET
40
mA
DC-DC Conversion Efficiency
DCDC_EFF_buck
VDD_1P8_buck
—
90%
—
—
—
1.71
min(VDCD Vdc
C_IN_buck
, 3.5)3, 4
1.8 V Output Voltage
VDD_1P8 = 3.0 V
IDD_1P8_buck1
IDD_1P8_buck2
IDD_1P8_buck3
—
—
—
—
—
—
39
45
35
mA
mA
mA
1.5 V <= VDC_1P5
<= 1.7 V
VDCDC_IN=3.1 V
VDD_1P8 = 2.65 V
1.5 V <= VDC_1P5
<= 1.7 V
1.8 V Output Current5, 6
VDCDC_IN=2.7 V
VDD_1P8 = 1.8 V
1.5 V <= VDC_1P5
<= 1.7 V
VDCDC_IN=2.1 V
7
1.5 V Output Voltage
1.5 V Output Current5, 8
Consumed by Radio VDD_1P5_buck
IDD_1P5_buck
1.5
—
—
1.8
45
—
Vdc
mA
μs
—
DC-DC Transition Operating
Behavior
LSS➔Run
t_DCDCbuck_LSS➔R
—
50
UN
DC-DC Turn on Time
TDCDC_ON
TDCDC_SETTLE_buck
—
—
2.29
3.11
—
—
ms
DC-DC Settling Time for
increasing voltage
ms/V
Table continues on the next page...
74
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
KW39/38/37 Electrical Characteristics
Table 43. DC-DC Converter Specifications (continued)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
DC-DC Settling Time for
decreasing voltage
C = capacitance
attached to the DC-
DC V1P8 output rail.
TDCDC_SETTLE_buck
—
(C*(V1–
V2)/I2
—
s
V1 = the initial output
voltage of the DC-DC
V2 = the final output
voltage of the DC-DC
I2 = the load on the
DC-DC output
expressed in
Amperes.
1. This is the steady state DC output power. Excessive transient current load from external device will cause 1p8V and
1P5 output voltage unregulated temporary.
2. This is the frequency that is observed at LN and LP pins.
3. The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.
4. In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For
example, if VDCDC_IN = 2.1 V, maximum VDD_1P8 is 2.05 V. If VDCDC_IN = 3.6 V, maximum VDD_1P8 is 3.5 V.
5. The output current specification in buck mode represents the maximum current the DC-DC converter can deliver. The
KW39/38/37 radio and MCU blocks current consumption is not excluded. The maximum output power of the DC-DC
converter is 140 mW when VDCDC_IN is below 2.7 V and 195 mW when VDCDC_IN is above 2.7 V. The available supply
current for external device depends on the energy consumed by the internal peripherals in KW39/38/37.
6. When using DC-DC in low-power mode (pulsed mode), current load must be less than 1 mA.
7. User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case
minimum of 1.5 V is available as VDD_1P5_buck. VDD_1P5 must not be programmed higher than VDD_1P8.
8. 1.5 V is intended to supply power to KW39/38/37. It is not designed to supply power to an external device.
9. Turn on time is measured from the application of power (to DCDC_IN) till the DCDC_REG0[DCDC_STS_DC_OK] bit
is set. Code execution may begin before the DCDC_REG0[DCDC_STS_DC_OK] bit is set. The full device
specification is not guaranteed until the bit sets.
6.7 Ratings
6.7.1 Thermal handling ratings
Table 44. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
75
NXP Semiconductors
Pin Diagrams and Pin Assignments
6.7.2 Moisture handling ratings
Table 45. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
6.7.3 ESD handling ratings
Table 46. ESD handling ratings
Symbol Description
Min.
Max.
Unit
Notes
VHBM
VCDM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
2
Electrostatic discharge voltage, charged-device model
All pins except the corner pins
–500
–750
–100
500
750
V
V
Corner pins only
ILAT
Latch-up current at ambient temperature of 105 °C
+100
mA
3
1. Determined according to JEDEC Standard JS001, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JS002, Field-Induced Charged-Device Model Test Method for Electrostatic-
Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
6.7.4 Voltage and current operating ratings
Table 47. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
GND
VDD + 0.3
VDCDC
V
V
VIO_DCDC
IO pins in the DC-DC voltage domain (DCDC_CFG and
PSWITCH)
7 Pin Diagrams and Pin Assignments
76
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
7.1 KW39/37 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control and Interrupt
module is used to select the functionality for each GPIO pin. ALT0 is reserved for
analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available
digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high
impedance after reset – their input and output buffers are disabled.
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
HVQ
FN
1
PTA0
PTA1
SWD_DIO
SWD_CLK
PTA0/
RF_ACTIVE
SPI0_PCS1
SPI1_PCS0
TPM1_CH0
TPM1_CH1
SWD_DIO
SWD_CLK
2
PTA1/
RF_
STATUS
3
4
PTA2
RESET_b
PTA2
TPM0_CH3
TPM0_CH0
RESET_b
PTA16
DISABLED
PTA16/
LLWU_P4
SPI1_SOUT
SPI1_SIN
5
6
7
PTA17
DISABLED
DISABLED
ADC0_SE5
PSWITCH
PTA17/
LLWU_P5
TPM_
CLKIN1
PTA18
PTA18/
LLWU_P6
SPI1_SCK
SPI1_PCS0
TPM2_CH0
TPM2_CH1
PTA19
ADC0_SE5
PSWITCH
PTA19/
LLWU_P7
8
9
PSWITCH
DCDC_
CFG/
DCDC_
CFG/
DCDC_
CFG/
VDCDC_IN
VDCDC_IN
VDCDC_IN
10
11
12
13
DCDC_LP
DCDC_LP
DCDC_LP
DCDC_GND DCDC_GND DCDC_GND
DCDC_LN
DCDC_LN
DCDC_LN
VDD_
VDD_
VDD_
1P8OUT
1P8OUT
1P8OUT
14
15
DCDC_LN
DCDC_LN
DCDC_LN
VDD_
VDD_
VDD_
1P5OUT_
PMCIN
1P5OUT_
PMCIN
1P5OUT_
PMCIN
16
PTB0
DISABLED
PTB0/
I2C0_SCL
CMP0_OUT TPM0_CH1
CLKOUT
LLWU_P8/
RF_
RFOSC_EN
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
77
NXP Semiconductors
Pin Diagrams and Pin Assignments
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
HVQ
FN
17
PTB1
PTB2
ADC0_SE1/ ADC0_SE1/ PTB1/
DTM_RX
I2C0_SDA
DTM_TX
LPTMR0_
ALT1
TPM0_CH2
TPM1_CH0
CMT_IRO
CMP0_IN5
CMP0_IN5
RF_
PRIORITY
18
ADC0_SE3/ ADC0_SE3/ PTB2/
TPM0_CH0
TPM2_CH0
TPM2_CH1
CMP0_IN3
CMP0_IN3
RF_NOT_
ALLOWED/
LLWU_P9
19
PTB3
ADC0_SE2/ ADC0_SE2/ PTB3/
TPM0_CH1
CLKOUT
TPM1_CH1
RTC_
CMP0_IN4
CMP0_IN4
ERCLK32K/
RF_ACTIVE
CLKOUT
20
21
22
23
VDD_0
PTB16
PTB17
PTB18
VDD_0
VDD_0
EXTAL32K
XTAL32K
NMI_b
EXTAL32K
XTAL32K
PTB16
PTB17
I2C1_SCL
I2C1_SDA
I2C1_SCL
TPM2_CH0
TPM2_CH1
TPM0_CH0
ADC0_SE4/ PTB18
CMP0_IN2
TPM_
CLKIN0
NMI_b
24
25
26
27
ADC0_DP0
ADC0_DM0
ADC0_DP0/ ADC0_DP0/
CMP0_IN0 CMP0_IN0
ADC0_DM0/ ADC0_DM0/
CMP0_IN1
CMP0_IN1
VREFL/
VSSA
VREFL/
VSSA
VREFL/
VSSA
VREFH/
VREFH/
VREFH/
VREF_OUT
VREF_OUT
VREF_OUT
28
29
30
31
32
33
34
35
36
37
VDDA
VDDA
VDDA
XTAL_OUT
EXTAL
XTAL
XTAL_OUT
EXTAL
XTAL_OUT
EXTAL
XTAL
XTAL
VDD_RF3
ANT
VDD_RF3
ANT
VDD_RF3
ANT
GANT
GANT
GANT
VDD_RF2
VDD_RF1
PTC1
VDD_RF2
VDD_RF1
DISABLED
VDD_RF2
VDD_RF1
PTC1/
RF_EARLY_
WARNING
ANT_B
I2C0_SDA
LPUART0_
RTS_b
TPM0_CH2
SPI1_SCK
38
39
40
PTC2
PTC3
PTC4
DISABLED
DISABLED
DISABLED
PTC2/
LLWU_P10
TX_
SWITCH
I2C1_SCL
I2C1_SDA
EXTRG_IN
LPUART0_
RX
CMT_IRO
DTM_RX
DTM_TX
I2C0_SCL
SPI1_SOUT
SPI1_SIN
PTC3/
LLWU_P11
RX_
SWITCH
LPUART0_
TX
TPM0_CH1
TPM1_CH0
PTC4/
LLWU_P12/
RF_ACTIVE
ANT_A
LPUART0_
CTS_b
SPI1_PCS0
78
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
Pin Diagrams and Pin Assignments
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
HVQ
FN
41
PTC5
DISABLED
PTC5/
LPTMR0_
ALT2
LPUART0_
RTS_b
TPM1_CH1
LLWU_P13/
RF_NOT_
ALLOWED/
RF_
PRIORITY
42
43
PTC6
PTC7
DISABLED
DISABLED
PTC6/
LLWU_P14/
RF_
I2C1_SCL
LPUART0_
RX
TPM2_CH0
RFOSC_EN
PTC7/
LLWU_P15
SPI0_PCS2
SPI0_SCK
I2C1_SDA
I2C0_SDA
LPUART0_
TX
TPM2_CH1
TPM0_CH3
44
45
VDD_1
PTC16
VDD_1
VDD_1
DISABLED
PTC16/
LLWU_P0/
RF_
LPUART0_
RTS_b
STATUS
46
PTC17
DISABLED
PTC17/
SPI0_SOUT I2C1_SCL
LPUART0_
RX
DTM_RX
DTM_TX
LLWU_P1/
RF_EXT_
OSC_EN
47
48
PTC18
PTC19
DISABLED
DISABLED
PTC18/
LLWU_P2
SPI0_SIN
I2C1_SDA
I2C0_SCL
LPUART0_
TX
PTC19/
SPI0_PCS0
LPUART0_
CTS_b
LLWU_P3/
RF_EARLY_
WARNING
49
Ground
NA
7.2 KW38 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control and Interrupt
module is used to select the functionality for each GPIO pin. ALT0 is reserved for
analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available
digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high
impedance after reset – their input and output buffers are disabled.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
79
NXP Semiconductors
Pin Diagrams and Pin Assignments
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
HVQ
FN
1
PTA0
SWD_DIO
SWD_CLK
PTA0/
RF_ACTIVE
SPI0_PCS1
SPI1_PCS0
TPM1_CH0
TPM1_CH1
SWD_DIO
SWD_CLK
RESET_b
2
PTA1
PTA1/
RF_STATUS
3
4
PTA2
RESET_b
PTA2
TPM0_CH3
TPM0_CH0
PTA16
DISABLED
PTA16/
LLWU_P4
SPI1_SOUT
SPI1_SIN
LPUART1_
RTS_b
5
6
7
PTA17
DISABLED
DISABLED
ADC0_SE5
PSWITCH
PTA17/
LLWU_P5
LPUART1_
RX
CAN0_TX
CAN0_RX
TPM_
CLKIN1
PTA18
PTA18/
LLWU_P6
SPI1_SCK
SPI1_PCS0
LPUART1_
TX
TPM2_CH0
PTA19
ADC0_SE5
PSWITCH
PTA19/
LLWU_P7
LPUART1_
CTS_b
TPM2_CH1
8
9
PSWITCH
DCDC_CFG/ DCDC_CFG/ DCDC_CFG/
VDCDC_IN
VDCDC_IN
VDCDC_IN
10
11
12
13
DCDC_LP
DCDC_LP
DCDC_LP
DCDC_GND DCDC_GND DCDC_GND
DCDC_LN
DCDC_LN
DCDC_LN
VDD_
VDD_
VDD_
1P8OUT
1P8OUT
1P8OUT
14
15
DCDC_LN
DCDC_LN
DCDC_LN
VDD_
VDD_
VDD_
1P5OUT_
PMCIN
1P5OUT_
PMCIN
1P5OUT_
PMCIN
16
PTB0
DISABLED
PTB0/
I2C0_SCL
CMP0_OUT
TPM0_CH1
CLKOUT
CAN0_TX
LLWU_P8/
RF_
RFOSC_EN
17
18
PTB1
PTB2
ADC0_SE1/
CMP0_IN5
ADC0_SE1/
CMP0_IN5
PTB1/
RF_
PRIORITY
DTM_RX
I2C0_SDA
DTM_TX
LPTMR0_
ALT1
TPM0_CH2
TPM1_CH0
CMT_IRO
CAN0_RX
ADC0_SE3/
CMP0_IN3
ADC0_SE3/
CMP0_IN3
PTB2/
TPM0_CH0
TPM2_CH0
RF_NOT_
ALLOWED/
LLWU_P9
19
PTB3
ADC0_SE2/
CMP0_IN4
ADC0_SE2/
CMP0_IN4
PTB3/
ERCLK32K/
RF_ACTIVE
LPUART1_
RTS_b
TPM0_CH1
CLKOUT
TPM1_CH1
RTC_
CLKOUT
TPM2_CH1
20
21
VDD_0
PTB16
VDD_0
VDD_0
EXTAL32K
EXTAL32K
PTB16
PTB17
LPUART1_
RX
I2C1_SCL
I2C1_SDA
TPM2_CH0
TPM2_CH1
22
PTB17
XTAL32K
XTAL32K
LPUART1_
TX
80
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
Pin Diagrams and Pin Assignments
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
HVQ
FN
23
24
25
26
27
PTB18
NMI_b
ADC0_SE4/
CMP0_IN2
PTB18
LPUART1_
CTS_b
I2C1_SCL
TPM_
CLKIN0
TPM0_CH0
NMI_b
ADC0_DP0
ADC0_DM0
ADC0_DP0/
CMP0_IN0
ADC0_DP0/
CMP0_IN0
ADC0_DM0/ ADC0_DM0/
CMP0_IN1
CMP0_IN1
VREFL/
VSSA
VREFL/
VSSA
VREFL/
VSSA
VREFH/
VREFH/
VREFH/
VREF_OUT
VREF_OUT
VREF_OUT
28
29
30
31
32
33
34
35
36
37
VDDA
VDDA
VDDA
XTAL_OUT
EXTAL
XTAL
XTAL_OUT
EXTAL
XTAL_OUT
EXTAL
XTAL
XTAL
VDD_RF3
ANT
VDD_RF3
ANT
VDD_RF3
ANT
GANT
GANT
GANT
VDD_RF2
VDD_RF1
PTC1
VDD_RF2
VDD_RF1
DISABLED
VDD_RF2
VDD_RF1
PTC1/
RF_EARLY_
WARNING
ANT_B
I2C0_SDA
LPUART0_
RTS_b
TPM0_CH2
SPI1_SCK
38
39
40
PTC2
PTC3
PTC4
DISABLED
DISABLED
DISABLED
PTC2/
LLWU_P10
TX_SWITCH I2C1_SCL
LPUART0_
RX
CMT_IRO
DTM_RX
DTM_TX
I2C0_SCL
SPI1_SOUT
SPI1_SIN
PTC3/
LLWU_P11
RX_
I2C1_SDA
EXTRG_IN
LPUART0_
TX
TPM0_CH1
TPM1_CH0
CAN0_TX
CAN0_RX
SWITCH
PTC4/
LLWU_P12/
RF_ACTIVE
ANT_A
LPUART0_
CTS_b
SPI1_PCS0
41
PTC5
DISABLED
PTC5/
LPTMR0_
ALT2
LPUART0_
RTS_b
TPM1_CH1
LLWU_P13/
RF_NOT_
ALLOWED/
RF_
PRIORITY
42
PTC6
DISABLED
PTC6/
LLWU_P14/
RF_
I2C1_SCL
I2C1_SDA
LPUART0_
RX
TPM2_CH0
TPM2_CH1
RFOSC_EN
43
44
PTC7
DISABLED
VDD_1
PTC7/
LLWU_P15
SPI0_PCS2
LPUART0_
TX
VDD_1
VDD_1
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
81
NXP Semiconductors
Pin Diagrams and Pin Assignments
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
HVQ
FN
45
PTC16
PTC17
DISABLED
DISABLED
PTC16/
LLWU_P0/
RF_STATUS
SPI0_SCK
I2C0_SDA
I2C1_SCL
LPUART0_
RTS_b
TPM0_CH3
LPUART1_
RTS_b
46
PTC17/
SPI0_SOUT
LPUART0_
RX
DTM_RX
DTM_TX
LPUART1_
RX
LLWU_P1/
RF_EXT_
OSC_EN
47
48
PTC18
PTC19
DISABLED
DISABLED
PTC18/
LLWU_P2
SPI0_SIN
I2C1_SDA
I2C0_SCL
LPUART0_
TX
LPUART1_
TX
PTC19/
SPI0_PCS0
LPUART0_
CTS_b
LPUART1_
CTS_b
LLWU_P3/
RF_EARLY_
WARNING
49
Ground
NA
7.3 KW39/38/37 Pinouts
KW39/38/37 device pinouts are shown in the figure below.
82
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
VDD_RF1
VDD_RF2
GANT
36
35
34
33
32
31
30
29
28
27
26
25
PTA0
PTA1
1
2
49
PTA2
3
ANT
PTA16
4
VDD_RF3
XTAL
PTA17
5
PTA18
6
PTA19
EXTAL
7
PSWITCH
DCDC_CFG/VDCDC_IN
DCDC_LP
DCDC_GND
DCDC_LN
XTAL_OUT
VDDA
8
9
VREFH/VREF_OUT
VREFL/VSSA
ADC0_DM0
10
11
12
*pin 49 is ground
Figure 20. 48-pin "Wettable" HVQFN pinout diagram
7.4 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the chapter of the module. They also briefly describe the signal function and
direction.
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
83
NXP Semiconductors
Pin Diagrams and Pin Assignments
7.4.1 Core Modules
This section contains tables describing the core module signal descriptions.
Table 48. SWD Module Signal Descriptions
SoC Signal Name
SWD_DIO
Module Signal Name
SWD_DIO
Description
I/O
Serial Wire Debug Data
Input/Output1
Serial Wire Clock2
I/O
I
SWD_CLK
SWD_CLK
1. Pulled up internally by default
2. Pulled down internally by default
7.4.2 Radio Modules
This section contains tables describing the radio signals.
Table 49. Radio Module Signal Descriptions
Module Signal Name
ANT
Pin Direction
Pin Name
Pin Description
O
O
O
O
ANT
Antenna
ANT_A
ANT_A
ANT_B
Antenna selection A for Front End Module support
Antenna selection B for Front End Module support
ANT_B
RF_ACTIVE
RF_ACTIVE
An output which is asserted prior to any Radio event
and remains asserted for the duration of the event.
DTM_RX
DTM_TX
GANT
I
DTM_RX
DTM_TX
GANT
Direct Test Mode Receive
Direct Test Mode Transmit
Antenna ground
O
I
RF_STATUS
O
RF_STATUS
An output which indicates when the Radio is in an
Rx or Tx event; software can also control this signal
directly.
RF_PRIORITY
O
O
RF_PRIORITY
An output which indicates to the external WiFi
device that the Radio event is a high priority and it
needs access to the 2.4 GHz antenna.
RF_EARLY_WARNING
RF_EARLY_WARNING Bluetooth LE LL generated signal which can be
used to wake an external sensor to make a
measurement before a Bluetooth LE event.
RF_NOT_ALLOWED
RF_TX_CONF
I
I
RF_NOT_ALLOWED
RF_TX_CONF
External signal which causes the internal Radio to
cease radio activity.
Signal from an external Radio which indicates the
availability of the 2.4 GHz antenna to the internal
Radio.
NOTE: This is a GPIO, not a dedicated PIN.
RX_SWITCH
TX_SWITCH
O
O
RX_SWITCH
TX_SWITCH
Front End Module receive mode signal.
Front End Module transmit mode signal.
84
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 50. Radio Module Miscellaneous Pin Descriptions
Pin Name
Pad Direction
Pin Name
Pin Description
RF_INT_OSC_EN
I
RF_RFOSC_EN
External request to turn on the Radio's internal RF
oscillator.
RF_EXT_OSC_EN
O
RF_EXT_OSC_EN
Internal request to turn on an External oscillator for
use by the internal Radio. The request can also be
from the SoC if it is using the RF oscillator as its
clock.
7.4.3 System Modules
This section contains tables describing the system signals.
Table 51. System Module Signal Descriptions
SoC Signal Name
NMI_b
Module Signal Name
Description
Non-maskable interrupt
Reset bidirectional signal
Power supply
I/O
—
—
I
RESET_b
I/O
VDD_[1:0]
Ground
VDD
I
VSS
Ground
I
VDD_RF[3:1]
VDCDC_IN
VDD_1P8OUT
VDD_RF
VDCDC_IN
VDD_1P8
Radio power supply
VDCDC_IN
I
I
DC-DC 1.8 V Regulated
Output / Input in bypass
I/O
VDD_1P5OUT_PMCIN
VDD_1P5/VDD_PMC
DC-DC 1.5 V Regulated
Output / PMC Input in
bypass
I/O
PSWITCH
DCDC_CFG
DCDC_LP
PSWITCH
DCDC_CFG
DCDC_LP
DC-DC enable switch
I
DC-DC switch mode select
I
DC-DC inductor input
positive
I/O
DCDC_LN
DCDC_LN
DC-DC inductor input
negative
I/O
I
DCDC_GND
DCDC_GND
DC-DC ground
Table 52. LLWU Module Signal Descriptions
SoC Signal Name
Module Signal Name
LLWU_P[15:0]
Description
Wake-up inputs
I/O
LLWU_P[15:0]
I
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
85
NXP Semiconductors
Pin Diagrams and Pin Assignments
7.4.4 Clock Modules
This section contains tables for Clock signal descriptions.
Table 53. Clock Module Signal Descriptions
SoC Signal Name
EXTAL
Module Signal Name
EXTAL
Description
I/O
26 MHz/32 MHz External
clock/Oscillator input
I
I
XTAL
XTAL
26 MHz/32 MHz Oscillator
input
XTAL_OUT
XTAL_OUT
26 MHz/32 MHz Clock output O
XTAL_OUT_EN
XTAL_OUT_ENABLE
26 MHz/32 MHz Clock output I
enable for XTAL_OUT
EXTAL32K
EXTAL32K
32 kHz External clock/
Oscillator input
I
XTAL32K
CLKOUT
XTAL32K
CLKOUT
32 kHz Oscillator input
Internal clocks monitor
I
O
7.4.5 Analog Modules
This section contains tables for Analog signal descriptions.
Table 54. ADC0 Signal Descriptions
SoC Signal Name
ADC0_DM0
Module Signal Name
DADM0
Description
I/O
ADC Channel 0 Differential
Input Negative
I
I
ADC0_DP0
ADC0_SE[5:1]
VREFH
DADP0
AD[5:1]
VREFSH
ADC Channel 0 Differential
Input Positive
ADC Channel 0 Single-ended I
Input n
Voltage Reference Select
High
I
VDDA
VSSA
VDDA
VSSA
Analog Power Supply
Analog Ground
I
I
Table 55. CMP0 Signal Descriptions
SoC Signal Name
Module Signal Name
IN[5:0]
CMP0
Description
Analog voltage inputs
Comparator output
I/O
CMP0_IN[5:0]
CMP0_OUT
I
O
86
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 56. VREF Signal Descriptions
SoC Signal Name
VREF_OUT
Module Signal Name
VREF_OUT
Description
I/O
Internally generated voltage
reference output
O
7.4.6 Timer Modules
This section contains tables describing timer module signals.
Table 57. TPM0 Module Signal Descriptions
SoC Signal Name
TPM_CLKIN[1:0]
TPM0_CH[3:0]
Module Signal Name
TPM_EXTCLK
TPM_CH[3:0]
Description
External clock
TPM channel
I/O
I/O
I/O
I
I/O
Table 58. TPM1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
TPM_EXTCLK
TPM_CH[1:0]
Description
External clock
TPM channel
TPM_CLKIN[1:0]
TPM1_CH[1:0]
I
I/O
Table 59. TPM2 Module Signal Descriptions
SoC Signal Name
Module Signal Name
TPM_EXTCLK
TPM_CH[1:0]
Description
External clock
TPM channel
TPM_CLKIN[1:0]
TPM2_CH[1:0]
I
I/O
Table 60. LPTMR0 Module Signal Descriptions
SoC Signal Name
LPTMR0_ALT[2:1]
Module Signal Name
Description
I/O
I/O
LPTMR0_ALT[2:1]
Pulse counter input pin
I
Table 61. RTC Module Signal Descriptions
SoC Signal Name
RTC_CLKOUT
Module Signal Name
RTC_CLKOUT
Description
1 Hz square-wave output
O
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
87
NXP Semiconductors
Pin Diagrams and Pin Assignments
7.4.7 Communication Interfaces
This section contains tables for the signal descriptions for the communication modules.
Table 62. SPI0 Module Signal Descriptions
SoC Signal Name
SPI0_PCS0
Module Signal Name
PCS0/SS
Description
Chip Select/Slave Select
Chip Select
I/O
I/O
O
SPI0_PCS[2:1]
SPI0_SCK
PCS[2:1]
SCK
Serial Clock
I/O
I
SPI0_SIN
SIN
Data In
SPI0_SOUT
SOUT
Data Out
O
Table 63. SPI1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SPI1_PCS0
Description
Chip Select/Slave Select
Serial Clock
I/O
SPI1_PCS0
SPI1_SCK
SPI1_SIN
I/O
I/O
I
SCK
SIN
Data In
SPI1_SOUT
SOUT
Data Out
O
Table 64. I2C0 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SCL
SDA
Description
I2C serial clock line
I2C serial data line
I/O
I/O
I/O
I2C0_SCL
I2C0_SDA
I/O
I/O
Table 65. I2C1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SCL
SDA
Description
I2C serial clock line
I2C serial data line
I2C1_SCL
I2C1_SDA
I/O
I/O
Table 66. CAN0 Signal Descriptions (KW38 only)
SoC Signal Name
Module Signal Name
CAN RX
CAN TX
Description
CAN Receive Pin
CAN Transmit Pin
CAN0_RX
CAN0_TX
I
O
88
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Package Information
Table 67. LPUART0 Module Signal Descriptions
SoC Signal Name
LPUART0_CTS_b
Module Signal Name
LPUART CTS
Description
Clear To Send
I/O
I
LPUART0_RTS_b
LPUART0_RX
LPUART0_TX
LPUART RTS
LPUART RxD
LPUART TxD
Request To Send
Receive Data
Transmit Data1
O
I
I/O
1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or
transmit direction is configured for receive data
Table 68. LPUART1 Module Signal Descriptions (KW38 only)
SoC Signal Name
LPUART1_CTS_b
Module Signal Name
LPUART CTS
Description
Clear To Send
I/O
I
LPUART1_RTS_b
LPUART1_RX
LPUART1_TX
LPUART RTS
LPUART RxD
LPUART TxD
Request To Send
Receive Data
Transmit Data1
O
I
I/O
1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or
transmit direction is configured for receive data
7.4.8 Human-Machine Interfaces(HMI)
This section contains tables describing the HMI signals.
Table 69. GPIO Module Signal Descriptions
SoC Signal Name
PTA[19:16][2:0]
Module Signal Name
Description
I/O
PORTA19-16, 2-0
General Purpose Input/
Output
I/O
I/O
I/O
PTB[18:16][3:0]
PTC[19:16][7:1]
PORTB18-16, 3-0
PORTC19-16, 7-1
General Purpose Input/
Output
General Purpose Input/
Output
8 Package Information
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
89
NXP Semiconductors
Part identification
8.1 Obtaining package dimensions
Package dimensions are available in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
document number of the drawing:
Table 70. Packaging Dimensions
If you want the drawing for this package
48-pin "Wettable" HVQFN (7x7)
Then use this document number
98ASA01307D
9 Part identification
9.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
9.2 Format
Part numbers for this device have the following format:
Q KW## A FFF R T PP CC N
9.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 71. Part number fields descriptions
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KW##
Kinetis Wireless family
• KW39
• KW38
• KW37
Table continues on the next page...
90
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Revision History
Table 71. Part number fields descriptions (continued)
Field
Description
Values
A
Key attribute
• A = Automotive Qualification
• Z = Industrial Qualification
FFF
T
Program flash memory size
Temperature range (°C)
• 512 = 512 KB
• V = –40 to 105
• C = –40 to 85
PP
CC
N
Package identifier
• FT = 48 "Wettable" HVQFN (7 mm x 7 mm)
• 4 = 48 MHz
Maximum CPU frequency (MHz)
Packaging type
• (Blank) = Tray
• R = Tape and reel
9.4 Example
This is an example part number:
MKW38A512VFT4
10 Revision History
Table 72. Revision History
Rev. No.
Date
Substantial Changes
Rev 7
03/2020
• Replaced VDD_XTAL with VDD_RF3.
• Preceded Tx output power value, 5 dBM, with a plus "+" sign.
• Added "256 KB P-Flash" to the fifth column name in the KW39/38/37 Part Numbers table.
• Corrected Figure 3 to show Prg Acc RAM 8 KB in place of FlexRAM 8 KB. Also added
"Prg Acc RAM" entry in Table 1.
• Corrected accuracy percentage of on-chip 4 MHz oscillator to 11% in System Clocks.
• Updated minimum and typical values in Table 4 - Top-Level Receiver Specifications.
• Updated maximum and typical values in Table 6 - Top-Level Transmitter Specifications.
Also updated footnote 3 as follows: "Measured at KW39/38/37 RF pins, with Vdd_RFx
over 1.44 V and assuming an average Tx duty cycle <=24%. For Tx output over +3.5 dBm,
powered Vdd_RFx has to be higher than 1.44 V.".
• Added VDD_1P5 specification in Voltage and current operating requirements.
• Added VPOR_VDD_1P5 specification in LVD and POR operating requirements.
• Updated maximum value of Frequency deviation of internal reference clock to 11 in
MCG specifications.
• In Power consumption operating behaviors :
• Removed the following note: "The maximum values specified in the following tables
represent characterized results equivalent to the mean plus three times the standard
deviation (mean + 3 sigma)."
• Updated maximum values of Power consumption operating behaviors - Bypass and
Buck Modes in Table 14 and Table 15.
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
91
NXP Semiconductors
Revision History
Table 72. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Added VDD_1P5 symbol to "Bypass Mode Supply Voltage (RF and Analog)" in DC-
DC Converter operating conditions.
• Updated minimum value to 1.5 V and removed typical value in "1.5 V Voltage
Output" in Table 43. Also updated the corresponding footnote with the correct value
of 1.5 V.
Rev 6
01/2020
• Updated Low-power Mode (VLLS0) current value to 266.6 nA in front page features under
"Low-power Consumption" section.
• Updated through out typical value of Bluetooth LE Receiver Sensitivity (2 Mbit/s and 1
Mbit/s) to -95.5 dBm and -98 dBm respectively.
• Updated typical values of Top-level receiver specifications in Table 4.
• Updated typical and maximum values in Table 14 and Table 15.
• Updated typical values of Tx (at 5 dBm) radio state at STOP and RUN MCU states in SoC
Power Consumption.
• Updated VCDM ratings in ESD handling ratings. Also updated the JEDEC standard to
JS001 and JS002.
Rev 5
12/2019
• Editorial fixes.
• Specified typical value of Rx current as 6.3 mA in front page features of the Data sheet
(under Low-power Consumption section). Also added 256 KB FlexNVM column in
KW39/38/37 Part Numbers table.
• Added Table 1.
• Corrected accuracy percentage of RC oscillator and on-chip 4 MHz oscillator to 3% and
6% respectively in System Clocks.
• Updated receiver sensitivity value to -101 dBm in Key Specifications.
• In section 4.2 - Receiver Feature Summary:
• Specified typical values of IRxon with respect to DC-DC converter buck and bypass
modes in Table 4.
• Updated receiver specifications with generic FSK modulations in Table 5.
• Updated VOH - Normal drive pad in Voltage and current operating behaviors to include
output high voltage at -1 mA.
• Added the following paragraph to Power consumption operating behaviors : "The
maximum values specified in the following tables represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma)." Also
updated units of IDD_VLLS1 typical values in Table 15.
• Updated maximum values in Table 14 and Table 15. Also updated mode# 20 and 21,
IDD_VLLS2 and IDD_VLLS2_16KB_16KB, to IDD_VLLS2_16KB and IDD_VLLS2_32KB.
• Updated Run mode supply current/VLPR mode current vs. core frequency images in
Diagram: Typical IDD_RUN operating behavior.
• Updated Table 26 to include operating temperature (TA), load capacitance (CL), and ESR
specifications.
• Updated value of VDCDC_IN to 2.1 V for IDD_1P8_buck3 in 1.8V Output Current row in
Table 43.
Rev 4
08/2019
• Updated value of Typical Receiver Sensitivity to -101 dBm.
• Corrected radio block in KW39 Detailed Block Diagram. Also M1 port (connected from
AXBS to Data Stream) corrected to M3.
• Added new item ("Each individual MB is formed by 16, 24, .....") to the list of features in
FlexCAN section in Peripheral features.
• Updated typical values in Receiver Feature Summary.
• In Transmit and PLL Feature Summary :
• Specified typical value of "Bluetooth LE 2 Mbit/s Adjacent Channel Transmit Power
at 4 MHz and >=6 MHz offset".
• Updated Figure 4. TX Pout (dBm) as function TX-PA Power Code at RF pins.
Table continues on the next page...
92
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Revision History
Table 72. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated numbers of "Transmit Output Power as a function of PA_POWER[5:0]" in
Table 7 and Table 8.
• Added Figure 5. TX Pout (dBm) as function TX-PA Power Code at RF pins (LDO-HF
bumped).
• Updated numbers in Table 16.
• Replaced "EMC design" with "KW38, HW guideline, RF system evaluation" in Designing
with radiated emissions in mind.
• Updated maximum value of Δfintf_ft to 6 in MCG specifications.
• Updated Table 43 with the following:
• Added conditions, VDCDC_IN above 2.7 V and below 2.7 V, in the first row, "DC-DC
Converter Output Power".
• Updated conditions in the "1.8 V Output Current" row. Also added IDD_1P8_buck3
condition to the row and updated maximum values.
• Updated "1.5 V Output Current" maximum value to 45 mA.
• Updated footnote 5 as follows: "The output current specification in buck mode
represents..... Note that the maximum output power of the DC-DC converter is 140
mW when VDCDC_IN is below 2.7 V and 195 mW when VDCDC_IN is above 2.7 V......".
Rev 3
Rev 2
06/2019
04/2019
• Removed "Input Voltage High/Low" rows from Radio operating conditions.
• Removed the following footnote from Table 14 - "Supported through the connectivity
software in its pre-defined Deep Sleep Modes". Also updated Typical values in Table 14
and Table 15.
• Removed "Flash timing specifications – program and erase" and "Flash high voltage
current behaviors" tables.
• Updated 48-pin "Wettable" HVQFN pinout diagram - added ground pin 49 to the diagram.
• Updated typical value of Bluetooth LE Receiver sensitivity at 2 Mbit/s from -94 to -95 dBm.
• Updated pin package drawing.
• Updated Low-power Mode (VLLS0) Current value to 252 nA and typical value of Tx
current to 5.7 mA.
• Added "512 KB P-Flash" column to this table. Also modified column name to "8 KB
FlexRAM EEPROM" from 8 KB EEPROM.
• Replaced "Prg Acc RAM 8 KB" with "FlexRAM 8 KB" in KW37 Detailed Block Diagram.
• Removed "Galois counter mode (AES-GCM)" and "DES modes" features of LTC from
Security Features.
• Updated typical values in Receiver Feature Summary. Also updated measurement
resolution to 2 MHz from 1 MHz in "Bluetooth LE uncoded 2 Mbit/s (High Speed)" section.
• Updated typical values in Table 5.
• Updated typical values of ITX0dBm, ITX0dBmb, ITX3.5dBm, ITX3.5dBmb, ITX5dBm, and ITX5dBmb
Also updated minimum value of TXBWBLE2M to 2.2 MHz in Table 6.
• Removed 48-pin LQFN package from Thermal attributes and specified values for
HVQFN48. Also replaced JESD51-2 standard with JESD51-2A in footnotes.
• In Table 14 and Table 15 :
.
• Added "Mode#" column.
• Added the following measurements—IDD_RUN_CM, IDD_VLPR_CM,
IDD_VLLS2_16KB_16KB, IDD_VLLS2_16KB_RF_Tx_RAM,
IDD_VLLS2_16KB_RF_Rx_RAM.
• Updated typical values.
• Added "Adder#" column to Table 16.
• Updated minimum and maximum values of "1.5 V Output Voltage" in Table 43. Also
specified the condition as "Consumed by Radio.".
• Removed support of DIAG1-3 signals and updated "DEFAULT" column to correct
"DISABLED" status of PTA19, PTB1/2/3 pin names in Signal Multiplexing and Pin
Assignments tables.
Table continues on the next page...
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
93
NXP Semiconductors
Revision History
Table 72. Revision History (continued)
Rev. No.
Date
12/2018
Substantial Changes
Rev 1
• Updated Features list on the front page:
• Updated Typical Receiver Sensitivity value of BLE LR 500 kbit/s from -99 to -101
dBm.
• Added 0.7 in the Generic FSK modulation index.
• Updated topic Radio features.
• Restructured section 3 Transceiver Description.
• Updated Full Bluetooth Low Energy version 5.0 modulation and Generic FSK modulation
values in Key Specifications.
• Updated Table 4, Table 5, and Table 6. Added Table 8.
• Added the following footnote in : "Tx continuous wave power output at the RF pins with the
recommended matching components mounted on PCB.".
Rev 1
Draft
11/2018
• Removed the following part numbers: MKW38A512VHT4, MKW38Z512VHT4, and
MKW37Z512VHT4.
• Added the following part numbers: MKW38Z512VFT4 and MKW37Z512VFT4.
• Removed 48-pin LQFN package.
• Changed 48 "Wettable" QFN to 48 "Wettable" HVQFN throughout.
• Applied new NXP Brand Guidelines for Bluetooth Low Energy. Removed references of
BLE and replaced with Bluetooth LE.
• Updated Features list on the front page:
• Corrected Typical Receiver Sensitivity value of BLE LR 500 kbit/s from -100.5 to -99
dBm.
• Corrected Typical Receiver Sensitivity (250 kbit/s GFSK-BT=0.5, h=0.5) from -100
to -103 dBm.
• Added 8 KB program acceleration RAM on KW37 to MCU and Memories section.
• Updated topic 2.2 Radio Features.
• Updated topic 2.3 Microcontroller features in the "On-Chip Memory" section to include
support of EEPROM emulation.
• Updated values of VDD_1P8OUT=1.8 V and VDD_1P8OUT=3.0 V to 45 mA and 27 mA.
• Updated maximum value of Programmable transmitter output power to 5 dBm.
• Updated typical value of RF Output power control range to 35 dB in Table 5. Top level
Transmitter Specifications.
• Removed silicon revision (R) field from Table 71. Part number fields descriptions.
Rev 0
09/2018
Initial Internal Release
94
MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
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Document Number MKW39A512
Revision 7, 03/2020
相关型号:
MKW38Z512VFT4
An ultra low-power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller
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MKW39A512
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MKW39A512VFT4
An ultra low-power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller
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