MM912KS812AMAF_技术文档

Document Number: MM912_S812

Rev. 2.0, 8/2016

NXP Semiconductors

Data Sheet: Advance Information

S12XS MCU and multifunctional

ignition and injector driver system in

package (SiP)

912_S812

The MM912_S812 is an engine control SMARTMOS IC combining an MCU

(S12XS) and analog control die (MC33812) intended for motorcycle and other

single cylinder small engine control applications.The MCU S12XS has 8.0 KB or

12 KB RAM, and flash memory size of 128 KB or 256 KB. The S12XS family

retains many of the features of the S12XE family including error correction code

(ECC) on flash memory, a separate data-flash module for code or data storage,

a frequency modulated locked loop (IPLL) that improves the EMC performance

and a fast ATD converter.

SMALL ENGINE CONTROL SIP

Features:

• Designed to operate over the range of ~4.7 V ≤ V_PWR≤ 36 V

• Relay/injector/fuel pump driver – current limit – 4.0 A, typical

• Lamp driver – current limit – 1.5 A, typical

AF Suffix (Pb Free)

98ASA00371D

• All external outputs protected against short to battery and overcurrent

• VCC voltage pre-regulator provides +5.0 V power for the MCU

• MCU watchdog timer circuit with parallel refresh/time setting line

• ISO-9141 K-Line transceiver for communicating diagnostic messages

100 Pin LQFP-EP

V_BAT

912_S812

Relay or

other load

5.0 V

VDD

VCCSENS

LAMPOUT

ROUT

Injector

INJOUT

VCCREF

IGNFB

V_PWR

IGNSUP

IGNOUTH

IGNOUTL

ISO9141

PAD00

PAD01

PAD02

PAD03

PAD04

PAD05

PAD06

PAD07

PAD09

V_BAT

VPWR

LAMPIN

PB3

RIN

PP1

ISO9141

RESETB

WDRFSH

I/O

INJIN

I/O

INJFLT

I/O

IGNIN

I/O

MOSI

SCK

SSB

MISO

IRQB

IGNFLT

I/O

RELFLT

PM1/TXCAN

PM0/RXCAN

TEST1

TM_EN, TEST2

WD_INH

PGND

I/O

MRX

RXD

MTX

TXD

EXTAL

XTAL

VSS

DGND

Notes

1. Surge Voltage protection recommended on VPWR

2. Not all connections on MCU shown

Figure 1. 912_S812 simplified application diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

1

Orderable parts

This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are

provided on the web. To determine the orderable part numbers for this device, go to http://www.nxp.com and perform a part number

search for the following device numbers.

Table 1. Orderable part variations

Part number ⁽³⁾

MM912JS812AMAF

Temperature (T )

MCU

Flash memory

128 k

RAM

8.0 k

12 k

Package

A

S12XS

-40 to 125 °C

100 pin LQFP-EP

MM912KS812AMAF

Notes

256 k

3. To Order parts in Tape & Reel, add the R2 suffix to the part number.

Table 2. Calibration tools

Part number

Package

MC9S12XEP100 (MCU Only)

PV912NE812AMAF

S12XEP

Multiple

Contact sales for availability and quantity

S12XEP + MC33812

100 pin LQFP-EP

Notes:

1)Surge Voltage protection

recommended on VPWR

2) Not all connections on MCU

shown

V_BAT

+5 V

33812

V_BAT

MIL

VPWR

LAMPOUT

PNP

V_BAT

RELAY OR

OTHER LOAD

S12XS

VCCREF

VCCSENS

LAMPIN

RIN

VDDF

VSS1

+5 V

VDD

ROUT

INJECTOR

V_BAT

*PB3

*PT1

PAD00

PAD01

PAD02

PAD03

PAD04

PAD05

PAD06

PAD07

V_BAT

INJOUT

V_PWR

RESET

IGNSUP

IGNFB

*PT4

*PP2

*PE6

*PP0

*PA1

*PA5

RXD

TXD

VDD

VSS

WDRFSH

INJIN

INJFLT

IGNIN

IGNFLT

RELFLT

MRX

MTX

IGNOUTH

IGNOUTL

PAD09

MOSI

SCK

SS

MISO

IRQ

TXCAN

RXCAN

EXTAL

XTAL

TM_EN, TEST2

WD_INH

PGND1,2,1A,2A

DGND

ISO9141

VDDPLL

VSSPLL

VSS

EP

* I/O pins indicated are examples only and not necessarily recommendations

Figure 2. 912_S812 detailed application diagram

912_S812

2

NXP Semiconductors

2

Part identification

This section provides an explanation of the part numbers and their alpha numeric breakdown.

2.1

Description

Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the

specific part you have received.

2.2

Format and examples

Part numbers for a given device have the following format, followed by a device example:

Table 3 - Part numbering - analog EMBEDDED MCU + POWER:

MM 9 cc f xxx r v PPP RR - MM912JS812AMAF

2.3

Fields

These tables list the possible values for each field in the part number (not all combinations are valid).

Table 3. Part numbering - analog EMBEDDED MCU + POWER

FIELD

DESCRIPTION

VALUES

• MM- Qualified Device

• SM- Custom Device

• PM- Prototype Device

MM

Product Category

9

Memory Type

Micro Core

• 9 = Flash, OTP

• 12 = HC12

cc

• J 128 k

• K 256 k

f

Memory Size

xxx

Analog Core/Target

Revision

• 812 - MC33812

• (default A)

r

t

Temperature Range

Variation

• M = -40 °C to 125 °C

• (default blank)

v

PPP

RR

Package Designator

Tape and Reel Indicator

• AF - 100 lead LQFP with exposed pad

• R2

912_S812

NXP Semiconductors

3

Internal block diagram

VDDA

VSSA

VRH

VRL

VSS1

ATD

128/256K bytes Flash

4K … 12K bytes RAM

8/10/12-bit 16-channel

Analog-Digital Converter

VSS2

4K … 8K bytes Data Flash

VDDR

AN[15:0]

PAD[ 07:00]

(AD 15:8 not included)

IOC0

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

PT0

PT1

PT2

TIM

VDD

Voltage Regulator

VDDF

16-bit 8 channel

Timer

VDDPLL

PT3

PT4

PT5

PT6

PT7

CPU12X

Debug Module

Single-wire Background

Debug Module

4 address breakpoints

2 data breakpoints

BKGD

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PP0

PP1

PP2

PP3

PWM

512 Byte Trace Buffer

Clock Monitor

COP Watchdog

Periodic Interrupt

Async. Periodic Int.

PIT

Amplitude Controlled

Low Power Pierce or

Full drive Pierce

Oscillator

PLL with Frequency

Modulation option

8-bit 8 channel

EXTAL

XTAL

Pulse Width Modulator

PP4

PP5

PP6

PP7

4ch 24-bit Timer

RESETB

TEST

Reset Generation

and Test Entry

Multilevel

PM0

PM1

PM2

PM3

PM4

PM5

RXCAN

TXCAN

MISO

SSB

MOSI

SCK

CAN0

msCAN 2.0B

SPI0

Interrupt Module

XIRQB

IRQB

PE[1,0]

PE2

PE3

Synchronous Serial IF

ECLK

PE4

PM6

PM7

PE5

PE6

PE7

PS0

PS1

XCLKSB/ECLKX2

RXD

TXD

RXD

TXD

SCI0

Asynchronous Serial IF

SCI1

PS2

PS3

PS4

PS5

PS6

PS7

PA[5,1]

(PA 7:6, 4:2, 0 not included)

Asynchronous Serial IF

PB0, PB2,6

(PB 7:1 not included)

PH0

PH1

PH2

PH3

PH4

PH5

PH6

PH7

PK[7:0]

PJ0

PJ1

PJ2

PJ6

PJ7

Figure 3. MC9S12XS family block diagram

912_S812

4

NXP Semiconductors

VPWR

VCCREF

VCCSENS

V

, V

CC

PWR

V10.0 Analog

V2.5 Logic

V

CC

TM_EN

IGNSUP

IGNFB

POR, overvoltage,

undervoltage

Ignition

LOGIC CONTROL

TEST1

TEST2

TEST3

Predriver

IGNOUTH

IGNOUTL

Band Gap

Short

Protection

Oscillator

Bias

Relay and

Injector Output

INJOUT

PGND1

INJIN

V

CC

Gate Control

VClamp

~75µA

Current Limit

Temperature Limit

Short Protection

ROUT

INJFLT

IGNIN

PARALLEL

CONTROL

PGND2

V

CC

Open det. on Injector

+

–

R

S

lLimit

IGNFLT

RIN

RELFLT

Lamp Output

Gate Control

LAMPOUT

LAMPIN

VClamp

Current Limit

Temperature Limit

Short Protection

RESETB

WATCHDOG

(Open Drain)

+

–

R

S

WDRFSH

MTX

V

CC

lLimit

GND

V

ISO9141

CONTROLLER

ISO9141

CC

WD_INH

MRX

DGND

Notes

4. Pull-up and pull-down current sources are ~50 µA, unless otherwise noted

Figure 4. 33812 simplified internal block diagram

912_S812

NXP Semiconductors

5

4

Pin connections

4.1

Pinout diagram

Transparent Top View

N.C.

MTX

MRX

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD

PA5

PA1

XIRQB

PE1/IRQB

VDDPLL

XTAL

WDRFSH

TM_EN

N.C.

EXTAL

VSSPLL

VSS3

ROUT

PGND2

N.C.

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDDR

LAMPOUT

N.C.

DGND

PGND1

INJOUT

N.C.

WD_INH

TEST1

TEST2

TEST3

N.C.

RESETB

VDDX2

VSSX2

PE4

PE6

PE7

PB6

PB5

PB4

PB3

PB2

PB0

BKGD

PT7

EP

GND

Notes

5. EP, PGND1, PGND2, and DGND, must all be connected to the ground plane.

6. Compared to the MC33812 in the 32 pin SOICW package, there are no pins missing.

7. Compared to the S12XS in the 80 pin QFP package, 22 pins are missing in the SiP. These pins are: PB1, PB7, PE5, PJ2, PE2, PE3,

PA0, PA2, PA3, PA4, PA6, PA7, PAD08, PAD09, PS2, PS3, PJ7, PJ6, PP7, PP6, PP5, and PP4.

Figure 5. 33812_S812 pin connections

912_S812

6

NXP Semiconductors

4.2

Pin definitions

Table 4. 912_S812 pin definitions

Analog

or MCU

Pin name

Formal name

Description and recommendations

Unused pin, leave open

function

Unused

-

1

2

N.C.

-------

Unused pin, leave open

Input logic level ISO9141 data, from the MCU, to the ISO9141 IN/OUT pin

Connect to MCU SCI TXD output (pin 90) if using ISO9141 circuit

ISO9141 Data Input to

MCU

Analog

3

4

MTX

MRX

Input

Output logic level ISO9141 data to the MCU from the ISO9141 IN/OUT pin

Connect to MCU SCI RXD input (pin 89) if using ISO9141 circuit

ISO9141 Data Output to

MCU

Output

Logic Level input from MCU to refresh the watchdog circuit to prevent

RESETB

Analog

5

WDRFSH

Input

Watchdog Refresh

Connect to MCU I/O output (e.g. PT4 pin 48)

Used by NXP test engineering, Connect to Ground

Unused pin, leave open

Analog

6

7

8

TM_EN

N.C.

Input

Test Mode Enable

-------

-

Unused

N.C.

-------

Unused pin, leave open

Low side relay driver output driven by parallel input RIN Use ESD capacitor

where the signal goes off the PC Board.

Analog

9

ROUT

Output

Relay Driver Output

Analog

-

10

11

PGND2

N.C.

Ground

Unused

Power Ground 2

-------

Ground for the RELAY driver output Connect to Ground

Unused pin, leave open

Low side driver output for MIL (warning lamp) driven by parallel input LAMPIN.

Use an ESD capacitor where the signal goes off the PC Board

Analog

12

LAMPOUT

Output

Warning Lamp Output

-

13

14

7

N.C.

DGND

N.C.

Unused

Ground

Unused

Ground

-------

Supply Ground

-------

Unused pin, leave open

Analog

-

Used as ground for all low power signals. Connect to Ground

Unused pin, leave open

Analog

16

PGND1

Power Ground 1

Ground for INJOUT injector driver output. Connect to Ground

Low side driver output for the Injector driven by parallel input INJIN. Use an

ESD capacitor where the signal goes off the PC Board.

Analog

17

INJOUT

Output

Injector Driver Output

-

7

N.C.

Unused

-------

Unused pin, leave open

19

20

Normally tied to GND, If tied high through a pull-up, it inhibits RESETB from

occurring when a watchdog timeout occurs. Normally connect to Ground.

Analog

21

WD_INH

Input

Watchdog Inhibit

Analog

-

22

23

24

25

TEST1

TEST2

TEST3

N.C.

Input

Test 1

Test 2

Test 3

-------

MUST be tied to GND. Connect to Ground

MUST leave OPEN. Leave open

Unused pin. Leave open

Input

Unused

Low side output to drive the Gate/Base of the IGBT/Bipolar Darlington

The network used on this pin is determined by the user requirements.

Analog

26

IGNOUTL

Output

Ignition Output Low

High side output to drive the Gate/Base of IGBT/Bipolar Darlington

The network used on this pin is determined by the user requirements.

Analog

27

28

29

IGNOUTH

IGNSUP

IGNFB

Output

Input

Ignition Output High

Ignition Output Supply

Feedback from Source

Tie to +5.0 V for Darlington, tie to the V_PWRsupply for the IGBT output device

Voltage feedback from the source of the Ignition driver transistor through a

10:1 voltage divider. Use a 10:1 voltage divider (36 k/4.02 k)

Input

912_S812

NXP Semiconductors

7

Table 4. 912_S812 pin definitions

Analog

or MCU

function

Pin name

Formal name

Description and recommendations

The ISO9141 pin is a V_PWRlevel IN/OUT signal connected to a external ECU

Tester, using ISO9141 Protocol.The Output is Open drain and the Input is a

ratiometric V_PWRlevel threshold comparator. Use an ESD capacitor where

the signal goes off the PC Board.

ISO9141 K-Line

Bidirectional Serial Data

Signal

Input/

Output

Analog

30

ISO9141

Feedback to the internal VCC regulator from a external pass transistor. Must

have the minimum of a 2.2 μF capacitor

Analog

31

32

VCCSENS

VCCREF

Input

Voltage Sense from VCC

VCC Reference Base

drive

Output

Base drive voltage for an external PNP pass transistor

VPWR is the main voltage supply input for the device. It is connected to a +12

volt battery (It should have reverse battery protection and transient

suppression.) It also needs a bypass capacitor to ground (100 nF or 0.1 μF)

Supply

Input

Main Voltage Supply

Input

Analog

MCU

33

34

35

36

37

38

39

40

41

42

43

VPWR

PM4/MOSI

PM3/SSB

PM2/MISO

PM1/TXCAN

PM0/RXCAN

VSSX1

Port M, I/O pin 4 is a general purpose input or output pin. It can be configured

as the master output (during master mode) or slave input pin (during slave

mode). MOSI for the serial peripheral interface (SPI).

PM4/

SPI MOSI

I/O

Port M, I/O pin 3 is a general purpose input or output pin. It can be configured

as the slave select output pin SSB of the serial peripheral interface (SPI)

(during master mode) and chip select input (CSB) (during slave mode).

PM3/

SPI SSB

Port M, I/O pin 2 is a general purpose input or output pin. It can be configured

as the master input (during master mode) or slave output pin (during slave

mode). MISO for the serial peripheral interface (SPI).

PM2/

SPI MISO

I/O

Port M, I/O pin 1 is a general purpose input or output pin. It can be configured

as the transmit pin TXCAN of the scalable controller area network controller

(CAN).

PM1/

TXCAN

I/O

Port M, I/O pin 0 is a general purpose input or output pin. It can be configured

as the receive pin RXCAN of the scalable controller area network controller

(CAN).

PM0/

RXCAN

I/O

External ground for I/O drivers. Bypass requirements depend on how heavily

the MCU pins are loaded. All VSSX pins are connected together internally.

Connect to Ground

Ground

VSSX1

VDDX1

External power for I/O drivers. Bypass requirements depend on how heavily

the MCU pins are loaded. All VDDX pins are connected together internally.

Connect to VCC and use a 100 nF bypass capacitor to ground.

Supply

Input

VDDX1

PP3

Port P, I/O pin 3 is a general purpose input or output pin. It can be configured

as a keypad wake-up input. It can be configured as a pulse width modulator

(PWM) output channel 3.

I/O

PP3/KWP3/PWM3

Port P, I/O pin 3 is a general purpose input or output pin. It can be configured

as a keypad wake-up input. It can be configured as a pulse width modulator

(PWM) output channel 2.⁽⁸⁾

PP2

PT0⁽⁸⁾

PP2/KWP2/PWM2

PT0⁽⁸⁾

Port P, I/O pin 3 is a general purpose input or output pin. It can be configured

as a keypad wake-up input. It can be configured as a pulse width modulator

(PWM) output channel 1.⁽⁸⁾

PP1

PT1⁽⁸⁾

PP1/KWP1/PWM1

PT1⁽⁸⁾

Port P, I/O pin 3 is a general purpose input or output pin. It can be configured

as a keypad wake-up input. It can be configured as a pulse width modulator

(PWM) output channel 0.⁽⁸⁾

PP0

PP0/KWP0/PWM0

PT2⁽⁸⁾

MCU

44

45

I/O

PT2⁽⁸⁾

Port T, I/O pin 3 is a general purpose input or output pin. It can be configured

as a timer (TIM) channel 3.

PT3

PT3/IOC3

Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the

power supply for the NVM logic. These signals are connected to device pins

to allow external decoupling capacitors (220 nF, X7R ceramic). In Shutdown

mode an external supply driving VDDF/VSS can replace the voltage regulator.

VDDF 3.3 V supply

output

MCU

46

47

VDDF

VSS1

Supply

Ground

MCU

VSS1

See previous description for VDDF/VSS.

Notes

8. S12XEP signals noted for reuse of PC board for the calibration device.

912_S812

8

NXP Semiconductors

Table 4. 912_S812 pin definitions

Analog

or MCU

function

Pin name

Formal name

Description and recommendations

Port T, I/O pin 4 is a general purpose input or output pin. It can be configured

as a timer (TIM) channel 4 or pulse width modulator (PWM) output 4.

MCU

48

PT4

I/O

PT4/IOC4/PWM4

Port T, I/O pin 5 is a general purpose input or output pin. It can be configured

as a timer (TIM) channel 5, pulse width modulator (PWM) output 5, or as the

output of the API_EXTCLK.

PT5/IOC5/PWM5/

API_EXTCLK

49

PT5

I/O

Port T, I/O pin 6 is a general purpose input or output pin. It can be configured

as a timer (TIM) channel 6.

MCU

50

51

PT6

PT7

I/O

PT6/IOC6

PT7/IOC7

Port T, I/O pin 7 is a general purpose input or output pin. It can be configured

as a timer (TIM) channel 7.

The BKGD/MODC pin is used as a pseudo open-drain pin for the background

debug communication. It is used as a MCU operating mode select pin during

reset. The state of this pin is latched to the MODC bit at the rising edge of

RESETB. The BKGD pin has an internal pull-up device.

MCU

52

BKGD

BDM

BKGD/MODC

MCU

53

54

55

56

57

58

PB0

PB2

PB3

PB4

PB5

PB6

I/O

PB0

PB2

PB3

PB4

PB5

PB6

Port B, I/O pin 0 is a general purpose input or output pin.

Port B, I/O pin 2 is a general purpose input or output pin.

Port B, I/O pin 3 is a general purpose input or output pin.

Port B, I/O pin 4 is a general purpose input or output pin.

Port B, I/O pin 5 is a general purpose input or output pin.

Port B, I/O pin 6 is a general purpose input or output pin.

Port E, I/O pin 7 is a general purpose input or output pin. An internal pull-up

is enabled during reset. It can be configured to output ECLKX2.

MCU

59

60

PE7

PE6

I/O

PE7/ECLKX2

PE6

Port E, I/O pin 6 is a general purpose input or output pin.

Port E, I/O pin 4 is a general purpose input or output pin. It can be configured

to drive the internal bus clock ECLK. ECLK can be used as a timing reference.

The ECLK output has a programmable prescaler.

MCU

61

62

63

PE4

I/O

PE4/ECLK

VSSX2

External ground for I/O drivers. Bypass requirements depend on how heavily

the MCU pins are loaded. All VSSX pins are connected together

internally.Connect to Ground

VSSX2

VDDX2

Ground

External power for I/O drivers. Bypass requirements depend on how heavily

the MCU pins are loaded. All VDDX pins are connected together internally.

Connect to VCC and use a 100 nF bypass capacitor to Ground

Supply

Input

VDDX2

The RESETB pin is an active low bidirectional control signal. It acts as an

input to initialize the MCU to a known start-up state, and an output when an

internal MCU function causes a reset. The RESETB pin has an internal pull-

up device. Use external pull-up (10 k and 0.1 μF capacitor to Ground) connect

to the 33812 RESETB pin 93.

RESETB

External Reset Pin

MCU

64

RESETB

Input

Supply

Input

Power supply input to the internal voltage regulator. Connect to VCC and use

bypass capacitor, 100 nF to Ground.

MCU

65

66

VDDR

VSS3

VDDR

The voltage supply of nominally 1.8 V is derived from the internal voltage

regulator. The return current path is through the VSS3 pin. No static external

loading of these pins is permitted. Connect to Ground

VSS3

Core Ground Pin

Ground

Provides operating voltage and ground for the phased-locked loop. This

allows the supply voltage to the PLL to be bypassed independently. Internal

power and ground are generated by the internal regulator. Connect to Ground

VSSPLL

PLL Ground Pin

MCU

67

68

69

VSSPLL

EXTAL

XTAL

EXTAL is the external clock pin. On reset all the device clocks are derived

from the internal reference clock. Connect to external crystal and 18 pf

capacitor to Ground

EXTAL

Oscillator Pin

Clock Input

Clock

Output

XTAL is the crystal driver pin. On reset all the device clocks are derived from

the internal reference clock. XTAL is the oscillator output. Connect to external

crystal and 18 pf capacitor to Ground

XTAL

Oscillator Pin

912_S812

NXP Semiconductors

9

Table 4. 912_S812 pin definitions

Analog

or MCU

function

Pin name

Formal name

Description and recommendations

Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that

provide the power supply for the PLL and oscillator. These signals are

MCU

70

VDDPLL

PLL Supply Output of 3.3 V regulator connected to device pins to allow external decoupling capacitors.

(100 nF...220 nF, X7R ceramic). In Shutdown mode, an external supply

driving VDDPLL/VSSPLL can replace the voltage regulator.

Port E, I/O pin 1 is a general purpose input pin and the maskable interrupt

71

72

IRQB

I/O

PE1/IRQB

request input that provides a means of applying asynchronous interrupt

requests. This will wake-up the MCU from stop or wait mode.

Port E, I/O pin 0 is a general purpose input pin and the non-maskable interrupt

request input that provides a means of applying asynchronous interrupt

requests. This will wake-up the MCU from stop or wait mode. The XIRQ

interrupt is level sensitive and active low. As XIRQ is level sensitive while this

pin is low, the MCU will not enter STOP mode. Connect to a 10K pull-up

resistor to VCC.

MCU

XIRQB

PE0/XIRQB

MCU

73

74

PA1

PA5

I/O

PA1

PA5

Port A, I/O pin 1 is a general purpose input or output pin.

Port A, I/O pin 5 is a general purpose input or output pin.

Signals VDD/VSS2 are the primary outputs of VREG_3V3 that provide the

power supply for the core logic.These signals are connected to device pins to

MCU

75

VDD

Supply

Output of 3.3 V regulator allow external decoupling capacitors (220 nF, X7R ceramic).In Shutdown

mode, an external supply driving VDD/VSS2 can replace the voltage

regulator.

MCU

76

77

VSS2

Ground Ground of 3.3 V regulator See previous description on VDD.

PAD00 is the general purpose input or output pin and analog input AN0 of the

PAD00

A/D Input

PA/D Input

A/D Input

PAD00

PAD01

PAD02

PAD03

PAD04

PAD05

PAD06

PAD07

VDDA

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

PAD01 is the general purpose input or output pin and analog input AN1 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

MCU

78

79

80

81

82

83

84

85

PAD01

PAD02

PAD03

PAD04

PAD05

PAD06

PAD07

VDDA

PAD02 is the general purpose input or output pin and analog input AN2 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

PAD03 is the general purpose input or output pin and analog input AN3 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

PAD04 is the general purpose input or output pin and analog input AN4 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

PAD05 is the general purpose input or output pin and analog input AN5 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

PAD06 is the general purpose input or output pin and analog input AN6 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

PAD07 is the general purpose input or output pin and analog input AN7 of the

analog-to-digital converter, A/D. Use voltage divider if necessary, and ESD

protection capacitor. Use of low pass filter as necessary.

This is the power supply input pin for the analog-to-digital converter and the

voltage regulator. Connect to VCC and use a bypass capacitor, 100 nF to

Ground.

Supply

Input

Supply

Input

VRH and VRL are the reference voltage input pins for the analog-to-digital

converter.Connect to VCC and use a bypass capacitor, 100 nF to Ground.

MCU

86

87

88

VRH

VRL

VRH

VRL

Supply

Input

VRH and VRL are the reference voltage input pins for the analog-to-digital

converter. Connect to Ground.

This is the ground input pin for the analog-to-digital converter and the voltage

regulator. Connect to Ground.

VSSA

Ground

VSSA

912_S812

10

NXP Semiconductors

Table 4. 912_S812 pin definitions

Analog

or MCU

function

Pin name

Formal name

Description and recommendations

Port S, I/O pin 0 is a general purpose input or output pin. It can be configured

as the receive pin RXD of serial communication interface (SCI).

If used for ISO9141 connect to pin 4, MRX.

PS0/

SCI RXD

MCU

89

PS0/RXD

I/O

Port S, I/O pin 1 is a general purpose input or output pin. It can be configured

as the receive pin TXD of serial communication interface (SCI).

If used for ISO9141 connect to pin 3, MTX.

PS1/

SCI TXD

MCU

90

91

PS1/TXD

TEST

I/O

Input

Test

MUST leave OPEN. leave open

Port M, I/O pin 5 is a general purpose input or output pin. It can be configured

as the serial clock input pin for the serial peripheral interface (SPI) when the

SPI is in slave mode and as a serial clock output when the SPI is in master

mode.

PM5/

SPI SCK

MCU

92

93

PM5/SCK

RESETB

I/O

Logic Level ResetB signal used to reset the MCU when the watchdog circuit

RESETB Output to MCU times out, during undervoltage condition on VCC, and for initial power up and

power down. Provides RESETB to MCU on pin 64.

Analog

Output

Analog

94

95

96

97

98

INJFLT

RELFLT

IGNFLT

INJIN

Output

Input

Injector Fault

Relay Fault

Logic Level output to MCU indicating any fault in the injector circuit.

Logic Level output to MCU indicating any fault in the relay circuit.

Logic Level output to MCU indicating any fault in the ignition circuit.

Logic Level Parallel Input from the MCU to control the injector driver output

Logic Level Parallel input to activate RELAY output, ROUT

Ignition Fault

Injector Parallel Input

Relay Parallel Input

RIN

Input

Logic Level Parallel input to activate the malfunction indicator lamp output,

LAMP

Analog

99

LAMPIN

Input

LAMP Parallel Input

Logic Level Parallel Input from MCU controlling the ignition coil current flow

and spark.

Analog

-

100

EP

IGNIN

GND

Input

Ignition Parallel Input

Substrate Ground

Ground

Should be tied to the Ground plane. Connect to Ground.

912_S812

NXP Semiconductors

11

5

Electrical characteristics

5.1

Maximum ratings

Table 5. 912_S812 maximum ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Rating

Value

Unit

Notes

Electrical ratings

ESD Voltage

• Human Body Model

• Machine Model

• Charge Device Model (Corner pins)

• Charge Device Model

±2000

±200

±750

±500

V_ESD1

V_ESD2

V_ESD3

V_ESD4

(9)

V

Thermal ratings

Operating Temperature

• Ambient

-40 to 125

-40 to 150

-40 to 125

T_A

T_J

T_C

°C

• Junction

• Case

T

Storage Temperature

-55 to 150

1.7

°C

W

STG

(12)

P

D

Power Dissipation (T = 25°C)

A

(10), (11)

T_SOLDER

Peak Package Reflow Temperature During Solder Mounting

Note 11

°C

Thermal Resistance

• Junction-to-Ambient

• Junction- to-Lead

• Junction-to-Flag

R

75

8.0

1.2

θJA

θJL

°C/W

R

θJC

Notes

9. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω), the Machine Model (MM)

(C_ZAP= 200 pF, R_ZAP= 0 Ω), and the Charge Device Model (CDM), Robotic (C_ZAP= 4.0 pF).

10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

11. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

Moisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all

orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.

12. This parameter is guaranteed by design but is not production tested.

5.2

Analog MC33812 parametrics

The detailed MC33812 specifications can be found in the MC33812 data sheet. See MC33812.

5.3

Microcontroller S12XS parametrics

The detailed S12XS specifications can be found in the MC9S12XS128 reference manual. See MC9S12XS128.

912_S812

12

NXP Semiconductors

6

Packaging

6.1

Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and

perform a keyword search for the drawing’s document number.

Package

Suffix

Package outline drawing number

100-Pin LQFP-EP

AF

98ASA00371D

912_S812

NXP Semiconductors

13

.

912_S812

14

NXP Semiconductors

912_S812

NXP Semiconductors

15

912_S812

16

NXP Semiconductors

7

Revision history

Revision

Date

Description of changes

1.0

2/2013

2/2015

8/2016

• Initial release

• Changed ordering part numbers from PM to MM

• Updated document status to Advance Information

• Update document form and style

2.0

•

Updated to NXP document form and style

912_S812

NXP Semiconductors

17

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

NXP.com

Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

Document Number: MM912_S812

Rev. 2.0

8/2016


型号：	MM912KS812AMAF
厂家：	NXP
描述：	16-Bit MCU, S12XS 256K, MC33812, Ignition, Injector, Driver System In Package (SiP), QFP 100, Tray
文件：	总18页 (文件大小：438K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MM912KS812AMAF [NXP]

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