MM912 [NXP]
Intelligent integrated precision battery sensor;
| 型号： | MM912 |
| 厂家： | 
NXP |
| 描述： | Intelligent integrated precision battery sensor |
| 文件： | 总396页 (文件大小：6665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MM912_637D1
Rev. 6.0, 6/2021
NXP Semiconductors
Data sheet: Technical data
Intelligent integrated precision
battery sensor
The MM912I637 (96 kB) and MM912J637 (128 kB) are fully integrated LIN
Battery monitoring devices, based on NXP SMARTMOS and S12 MCU
Technology.
MM912_637
Battery Monitoring System
The device supports precise current measurement via an external shunt resistor,
and precise battery voltage measurement via a series resistor directly at the
battery plus pole. The integrated temperature sensor combined in the close
proximity to the battery, allows battery temperature measurement.
The integrated LIN 2.1 interface makes the sensor feedback available on the LIN
Bus.
Features
• Battery voltage measurement
• Battery current measurement in up to 8 ranges
• On chip temperature measurement
EP SUFFIX (WF-TYPE)
SOT619-25(D)
EP SUFFIX (WF-TYPE)
SOT619-16
48-PIN QFN
• Normal and two low-power modes
48-PIN QFN
• Current threshold detection and current averaging in standby => wake-up
from low-power mode
Applications
• Triggered wake-up from LIN and periodic wake-up
• Signal low pass filtering (current, voltage)
• 12 V Lead-acid battery monitoring
• PGA (programmable low-noise gain amplifier) with automatic gain control
• Accurate internal oscillator (an external quartz oscillator may be used for
extended accuracy)
• Communication via a LIN 2.1, LIN2.0 bus interface
• S12 microcontroller with 128 kByte flash, 6.0 kByte RAM, 4.0 kByte data flash
• Background debug module
• External temperature sensor option (TSUP, VTEMP)
• Optional 2nd external voltage sense input (VOPT)
• 4 x 5.0 V GPIO including one wake-up capable high voltage input (PTB3/L0)
• 8 x MCU general purpose I/O including SPI functionality
• Industry standard EMC compliance
MM912_637
VDDA
LIN
(optional)
ADC Supply
LIN Interface
AGND
ADCGND
LGND
Internal
Temp
Sense
Module
VDDL
TSUP
VTEMP
Optional Temp Sense
Input and Supply
2.5 V Supply
5.0 V Supply
VDDH
VDDD2D
VDDX
Battery
Positive Pole
+
VOPT
VSENSE
Voltage sense Module
Power Supply
VDDRX
DGND
VSSD2D
VSSRX
VSUP
Digital Ground
Reset
Battery
Negative Pole
_
ISENSEL
RESET
RESET_A
PA0/MISO
PA1/MOSI
PA2/SCK
PA3/SS
PA4
PA5
PA6
PA7
BKGD/MODC
PE0/EXTAL
PE1/XTAL
TEST
Current Sense Module
Shunt
ISENSEH
PTB0
Chassis
Ground
-5.0 V GPI/O shared
with TIMER, SCI and LIN
-PTB3 high voltage
WAKE capable
5.0 V Digital I/O
PTB1
PTB2
PTB3/L0
GNDSUB
TCLK
4
Debug and External
Oscillator
Analog Test
MCU Test
TEST_A
Figure 1. Simplified application diagram
© NXP B.V. 2021. All rights reserved.
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table of Contents
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
2
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 MM912_637 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Pin structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Thermal protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.8 Electromagnetic compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 MM912_637 - analog die overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3 Analog die - power, clock and resets - PCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4 Interrupt module - IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Current measurement - ISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.6 Voltage measurement - VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.7 Temperature measurement - TSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.8 Channel acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.9 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.10 Basic timer module - TIM (TIM16B4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.11 General purpose I/O - GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.12 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.13 Serial communication interface (S08SCIV4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.14 Life time counter (LTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
4.15 Die to die interface - target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
4.16 Embedded microcontroller - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
4.17 MCU - port integration module (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4.18 MCU - interrupt module (S12S9S12I128PIMV1V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
4.19 Memory map control (S12PMMCV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
4.20 MCU - debug module (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
4.21 MCU - security (S12XS9S12I128PIMV1V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
4.22 Background debug module (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
4.23 S12 clock, reset, and power management unit (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
4.24 MCU - serial peripheral interface (S129S12I128PIMV1V5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
4.25 128 kByte flash module (S12FTMRC128K1V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
4.26 MCU - die-to-die initiator (9S12I128PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
MM912_637 - trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.2 IFR trimming content and location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.3 Memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
6.1 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
3
4
5
6
7
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
2/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
1
Ordering information
Table 1. Ordering information
Package
Type number
Name
Description
Version
MM912I637TM2EP
MM912J637TM2EP
MM912I637TV1EP
MM912J637TV1EP
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.15 dimple, wettable flank, 7 mm x 7 mm x 0.9 mm body
SOT619-25(D)
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.1 dimple, wettable flank, 7 mm x 7 mm x 0.85 mm body
SOT619-25(D)
HVQFN48
MM912I637AM2EP
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.15 dimple, wettable flank, 7 mm x 7 mm x 0.9 mm body
SOT619-161
SOT619-161
MM912J637AM2EP
MM912I637AV1EP
MM912J637AV1EP
plastic, thermal enhanced, very thin quad flatpack, no leads, 48 terminals,
0.5 mm pitch, 0.1 dimple, wettable flank, 7 mm x 7 mm x 0.85 mm body
1
Not recommended for new design
Table 2. Ordering options
Device (1)
Maximum input
Temperature range (TA)
Flash (kB)
Analog option
voltage
MM912I637TM2EP
MM912J637TM2EP
MM912I637AM2EP(2)
MM912J637AM2EP(2)
MM912I637TV1EP
MM912J637TV1EP
MM912I637AV1EP(2)
MM912J637AV1EP(2)
96
128
96
–40 °C to 125 °C
2
1
128
96
42 V
128
96
–40 °C to 105 °C
128
Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
2. Not recommended for new design.
Table 3. Analog options
Feature
Analog option 1
Analog option 2
Cranking Mode
Not Characterized or Tested
Fully Characterized and Tested
External Wake-up (PTB3/L0)
External Temperature Sensor Option (VTEMP)
Optional 2nd External Voltage Sense Input (VOPT)
No
No
No
Yes
Yes
Yes
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
3/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
GNDSUB
GNDSUB
GNDSUB
GNDSUB
LGND
LIN
Internal Bus
TEST_A
TCLK
VSUP
RESET_A
DGND
VDDL
VDDX
VDDH
VDDD2D
VSSD2D
VDDRX
VSSRX
Internal Bus
RESET
BKGD/MODC
PA7
D D R A
P T
A
Figure 2. Sample block diagram
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
4/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
2
Pin assignment
PA6
PTE0/EXTAL
PTE1/XTAL
TEST
PTB3 / L0
1
2
36
VOPT
35
VSENSE
3
34
ADCGND
4
33
PA5
ISENSEH
5
32
PA4
ISENSEL
6
31
EP
PA3/SS
GNDSUB
7
30
PA2/SCK
PA1/MOSI
PA0/MISO
VSSRX
TSUP
8
29
VTEMP
9
28
AGND
10
11
12
27
VDDA
26
VDDRX
NC
25
Figure 3. MM912_637 pin connections
2.1
MM912_637 pin description
The following table gives a brief description of all available pins on the MM912_637 device. Refer to the highlighted chapter for detailed
information
Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
Formal Name
MCU PA6
Description
General purpose port A input or output pin 6. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
1
PA6
EXTAL in one of the optional crystal/resonator drivers and external clock pins, and the PE0
port may be used as a general purpose I/O. On reset, all the device clocks are derived from
the internal reference clock. See Section 4.23, “S12 clock, reset, and power management
unit (9S12I128PIMV1)".
2
3
PE0/EXTAL
MCU Oscillator
XTAL is one of the optional crystal/resonator drivers and external clock pins, and the PE1
port may be used as a general purpose I/O. On reset all the device clocks are derived from
the internal reference clock. See Section 4.23, “S12 clock, reset, and power management
unit (9S12I128PIMV1)".
PE1/XTAL
TEST
MCU Oscillator
MCU Test
This input only pin is reserved for test. This pin has a pull-down device. The TEST pin must
be tied to VSSRX in user mode.
4
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
5/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
Formal Name
MCU PA5
Description
General purpose port A input or output pin 5. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
5
PA5
General purpose port A input or output pin 4. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
6
7
8
9
PA4
PA3
PA2
PA1
MCU PA4
General purpose port A input or output pin 3, shared with the SS signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
MCU PA3 / SS
MCU PA2 / SCK
MCU PA1 / MOSI
General purpose port A input or output pin 2, shared with the SCLK signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
General purpose port A input or output pin 1, shared with the MOSI signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
General purpose port A input or output pin 0, shared with the MISO signal of the integrated
SPI interface. See Section 4.17, “MCU - port integration module (9S12I128PIMV1)".
10
11
12
PA0
MCU PA0 / MISO
MCU 5.0 V Ground
MCU 5.0 V Supply
VSSRX
VDDRX
External ground for the MCU - VDDRX return path.
5.0 V MCU power supply. MCU core- (internal 1.8 V regulator) and flash (internal 2.7 V
regulator) supply. This pin must be connected to VDDX.
13
14
15
16
VSSD2D
VDDD2D
NC
MCU 2.5 V Ground
MCU 2.5 V Supply
Not connected
External ground for the MCU - VDDD2D return path.
2.5 V MCU power supply. Die to die buffer supply. This pin must be connected to VDDH.
This pin must be grounded in the application.
GNDSUB
Substrate Ground
Substrate ground connection to improve EMC behavior.
Voltage Regulator Output
5.0 V
5.0 V main voltage regulator output pin. An external capacitor (CVDDX) is needed. See
Section 4.3, “Analog die - power, clock and resets - PCR".
17
18
VDDX
DGND
This pin is the device digital ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
Digital Ground
2.5 V high power main voltage regulator output pin to be connected with the VDDD2D MCU
pin. An external capacitor (CVDDH) is needed. See Section 4.3, “Analog die - power, clock
and resets - PCR".
Voltage Regulator Output
2.5 V
19
VDDH
20
21
22
23
GNDSUB
VSUP
LIN
Substrate Ground
Power Supply
LIN Bus I/O
Substrate ground connection to improve EMC behavior.
This pin is the device power supply pin. A reverse battery protection diode is required. See
Section 4.3, “Analog die - power, clock and resets - PCR".
This pin represents the single-wire bus transmitter and receiver. See Section 4.12, “LIN".
This pin is the device LIN ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
LGND
LIN Ground Pin
24
25
NC
NC
Not connected (reserved)
Not connected
This pin must be grounded in the application.
This pin must be grounded in the application.
Low power analog voltage regulator output pin, permanently supplies the analog front end.
An external capacitor (CVDDA) is needed. See Section 4.3, “Analog die - power, clock and
resets - PCR".
Analog Voltage Regulator
Output
26
VDDA
This pin is the device analog voltage regulator and LP oscillator ground connection. See
Section 4.3, “Analog die - power, clock and resets - PCR".
27
28
AGND
Analog Ground
External temperature sensor input. See Section 4.7, “Temperature measurement -
TSENSE".
VTEMP
Temperature Sensor Input
Temperature Sensor Supply Supply for the external temperature sensor. TSUP frequency compensation option to allow
29
30
31
TSUP
Output
capacitor CTSUP. See Section 4.7, “Temperature measurement - TSENSE".
GNDSUB
ISENSEL
Substrate Ground
Substrate ground connection to improve EMC behavior.
Current sense input “Low”. This pin is used in combination with ISENSEH to measure the
voltage drop across a shunt resistor. See Section 4.5, “Current measurement - ISENSE".
Current Sense L
MM912_637D1
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Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
Formal Name
Current Sense H
Description
Current sense input “high”. This pin is used in combination with ISENSEL to measure the
voltage drop across a shunt resistor. See Section 4.5, “Current measurement - ISENSE".
32
ISENSEH
Analog Digital Converter
Ground
Analog digital converter ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
33
ADCGND
Precision battery voltage measurement input. This pin can be connected directly to the
battery line for voltage measurements. The voltage preset at this input is scaled down by
an internal voltage divider. The pin is self protected against reverse battery connections.
An external resistor (RVSENSE) is needed for protection. See Section 4.6, “Voltage
measurement - VSENSE".
34
35
VSENSE
VOPT
Voltage Sense
Optional Voltage Sense
Optional voltage measurement input. See Section 4.6, “Voltage measurement - VSENSE".
This is the high voltage general purpose input pin 3, based on VDDX with the following
shared functions:
• Internal clamping structure to operate as a high voltage input (L0). When used as high
voltage input, a series resistor (RL0) and capacitor to GND (CL0) must be used to protect
against automotive transients, when used to connect outside the PCB.
General Purpose Input 3 -
High Voltage Input 0
• 5.0 V (VDDX) digital port input
36
PTB3 / L0
• Selectable internal pull-down resistor
• Selectable wake-up input during low power mode.
• Selectable timer channel input
• Selectable connection to the LIN / SCI (Input only)
See Section 4.11, “General purpose I/O - GPIO".
This is the general purpose I/O pin 2 based on VDDX with the following shared functions:
• Bidirectional 5.0 V (VDDX) digital port I/O
• Selectable internal pull-up resistor
• Selectable timer channel input/output
• Selectable connection to the LIN / SCI
See Section 4.11, “General purpose I/O - GPIO".
37
38
39
PTB2
PTB1
PTB0
General Purpose I/O 2
General Purpose I/O 1
General Purpose I/O 0
This is the general purpose I/O pin 1, based on VDDX with the following shared functions:
• Bidirectional 5.0 V (VDDX) digital port I/O
• Selectable internal pull-up resistor
• Selectable timer channel input/output
• Selectable connection to the LIN / SCI
See Section 4.11, “General purpose I/O - GPIO".
This is the general purpose I/O pin 0 based on VDDX with the following shared functions:
• Bidirectional 5.0 V (VDDX) digital port I/O
• Selectable internal pull-up resistor
• Selectable timer channel input/output
• Selectable connection to the LIN / SCI
See Section 4.11, “General purpose I/O - GPIO".
40
41
TCLK
Test Clock Input
Test mode clock input pin for Test mode only. This pin must be grounded in user mode.
Substrate ground connection to improve EMC behavior.
GNDSUB
Substrate Ground
Low Power Voltage
Regulator Output
2.5 V low power voltage regulator output pin. See Section 4.3, “Analog die - power, clock
and resets - PCR".
42
43
44
VDDL
TEST_A
DGND
Test Mode
Analog die Test mode pin for Test mode only. This pin must be grounded in user mode.
This pin is the device digital ground connection. See Section 4.3, “Analog die - power, clock
and resets - PCR".
Digital Ground
Reset output pin of the analog die in Normal mode. Bidirectional reset I/O of the analog die
in Stop mode. Active low signal with internal pull-up to VDDX. This pin must be connected
to RESET. See Section 4.3, “Analog die - power, clock and resets - PCR".
45
RESET_A
Reset I/O
MM912_637D1
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Table 4. MM912_637 pin description (continued)
Pin #
Pin Name
Formal Name
Description
Bidirectional reset I/O pin of the MCU die. Active low signal with internal pull-up to VDDRX.
This pin must be connected to RESETA. See Section 4.3, “Analog die - power, clock and
resets - PCR".
46
RESET
MCU Reset
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. It is used as an MCU operating mode select pin during reset. The state of
this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pull-up
device. See Section 4.20, “MCU - debug module (9S12I128PIMV1)".
MCU Background Debug
and Mode
47
48
BKGD
PA7
General purpose port A input or output pin 7. See Section 4.17, “MCU - port integration
module (9S12I128PIMV1)".
MCU PA7
2.2
Recommended external components
Figure 4 and Table 5 list the required / recommended / optional external components for the application.
Battery
Plus Pole
D1
RVOPT
RVSENSE
CVBAT
Battery
Minus Pole
VDDL
VDDD2D
VDDH
RISENSEL
VDDRX
VDDX
ISENSEL
CISENSEL
RSHUNT
CISENSEHL
CVDDX
RISENSEH
DGND
VSSD2D
VSSRX
ISENSEH
CVDDH
CISENSEH
RESET
Chassis
Ground
RESETA
VTEMP
TSUP
RVTEMP
LIN
LIN
VDDA
CLIN
CVDDA
CTSUP
LGND
AGND
ADCGND
PTB3 / L0
RL0
CL0
Note: Module GND connected to Battery Minus or Chassis Ground– based on configuration.
Figure 4. Required/recommended external components
Table 5. Required/recommended external components
Name
Description
Value
n.a.
Connection
VSUP-VBAT
Comment
D1
Reverse Battery Diode
Battery Blocking Capacitor
VSENSE Current Limitation
VOPT Current Limitation
Current Shunt Resistor
CVBAT
RVSENSE
RVOPT
4.7 µF/100 nF
2.2 k
VSUP-GND
Ceramic
VSENSE-VBAT
VOPT-signal
2.2 k
optional(3)
RSHUNT
100 µ
ISENSEH-ISENSEL
MM912_637D1
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Table 5. Required/recommended external components
Name
Description
EMC Resistor
Value
500 max
500 max
TBD
Connection
Comment
RISENSEL
select for best EMC performance
select for best EMC performance
select for best EMC performance
select for best EMC performance
select for best EMC performance
RISENSEH
CISENSEL
CISENSEHL
CISENSEH
CVDDH
CVDDX
CVDDA
CVDDL
CLIN
EMC Resistor
EMC Capacitor
EMC Capacitor
TBD
EMC Capacitor
TBD
Blocking Capacitor
Blocking Capacitor
Blocking Capacitor
Blocking Capacitor
LIN Bus Filter
1.0 µF
220 nF
47 nF
VDDH-GND
VDDX-GND
VDDA-GND
VDDL-GND
LIN-LGND
L0
n.a.
not required
not required
n.a.
RL0
PTB3 / L0 Current Limitation
PTB3 / L0 ESD Protection
Blocking Capacitor
VTEMP Current Limitation
47 k
47 nF
CL0
L0-GND
220 pF
20 k
TSUP-GND
VTEMP-signal
not required(4)
optional(3)
CTSUP
RVTEMP
Notes
3. Required if extended EMC protection is needed
4. If an external temperature sensor is used, EMC compliance may require the addition of CTSUP. In this case the ECAP bit must be set to ensure the
stability of the TSUP power supply circuit. See Section 4.7.1.2, “Block diagram".
2.3
Pin structure
Table 6 documents the individual pin characteristic.
Table 6. Pin type/structure
Alternative pin
Pin #
Pin name
Power supply
Structure
function
1
2
PA6
PE0
n.a.
VDDRX
VDDRX
VDDRX
n.a.
n.a.
EXTAL
XTAL
n.a.
PUPEE / OSCPINS_EN
3
PE1
PUPEE / OSCPINS_EN
4
TEST
PA5
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
GND
5
n.a.
VDDRX
VDDRX
VDDRX
VDDRX
VDDRX
VDDRX
6
PA4
n.a.
7
PA3
SS
8
PA2
SCK
MOSI
MISO
n.a.
9
PA1
10
11
12
13
14
PA0
VSSRX
VDDRX
VSSD2D
VDDD2D
n.a.
n.a.
GND
n.a.
MM912_637D1
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Table 6. Pin type/structure
Alternative pin
function
Pin #
Pin name
Power supply
Structure
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC
GNDSUB
VDDX
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
GND
VDDX
GND
DGND
VDDH
B2B-Diode to GNDSUB
Negative Clamp Diode, Dynamic ESD (transient protection)
GNDSUB
VDDH
GND
GNDSUB
VSUP
VSUP
VSUP
GND
Negative Clamp Diode, >42 V ESD
No Negative Clamping Diode (-40 V), >42 V ESD
B2B-Diode to GNDSUB
LIN
LGND
NC
n.a.
Negative Clamp Diode, >15 V ESD
n.a.
NC
n.a.
VDDA
VDDA
GND
Negative Clamp Diode, Dynamic ESD (transient protection)
B2B-Diode to GNDSUB
AGND
VTEMP
TSUP
VDDA
TSUP
GND
Negative Clamp Diode, >6.0 V ESD
Negative Clamp Diode, Dynamic ESD (transient protection)
GND
GNDSUB
ISENSEL
ISENSEH
ADCGND
VSENSE
VOPT
n.a.
Negative Clamp Diode, 2nd Clamp Diode to VDDA
Negative Clamp Diode, 2nd Clamp Diode to VDDA
B2B-Diode to GNDSUB
n.a.
GND
n.a.
No Negative Clamping Diode (-40 V), >42 V ESD
No Negative Clamping Diode (-40 V), >42 V ESD
Negative Clamp Diode, >6.0 V ESD
Negative Clamp, Dynamic 5.5 V ESD
Negative Clamp, Dynamic 5.5 V ESD
Negative Clamp, Dynamic 5.5 V ESD
Negative Clamp, Dynamic 5.5 V ESD
GND
n.a.
PTB3 / L0
PTB2
VDDRX
VDDRX
VDDRX
VDDRX
VDDRX
GND
PTB1
PTB0
TCLK
GNDSUB
VDDL
VDDL
VDDRX
GND
Negative Clamp Diode, Dynamic ESD (transient protection)
Negative Clamp, positive 10 V Clamp
B2B-Diode to GNDSUB
TEST_A
DGND
RESET_A
RESET
BKGD
VDDRX
VDDRX
VDDRX
VDDRX
Negative Clamp, positive 10 V Clamp
Pull-up
MODC
BKPUE
PA7
n.a.
MM912_637D1
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3
Electrical characteristics
3.1
General
This section contains electrical information for the microcontroller, as well as the MM912_637 analog die.
3.2
Absolute maximum ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside these maximums is not guaranteed. Stress
beyond these limits may affect the reliability, or cause permanent damage of the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal
precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect to ground, unless otherwise
noted.
Table 7. Absolute maximum electrical ratings - analog die
Ratings
Symbol
Value
-0.3 to 42
Unit
V
VVSUP
VSUP pin voltage
VSENSE pin voltage with 2.2 k serial resistor (5)
VOPT pin voltage with 2.2 k serial resistor
VTEMP pin voltage
-16 to 42
V
VVSENSE
VVOPT
-16 to 42
V
VVTEMP
VISENSE
IISENSE
VBUS
-0.3 to VDDA+0.25
-0.5 to VDDA+0.25
-1 to 1
V
ISENSEH and ISENSEL pin voltage
ISENSEH and ISENSEL pin current
LIN pin voltage
V
mA
V
-33 to 42
IBUSLIM
LIN pin current (internally limited)
L0 pin voltage with RPTB3
Input / Output pins PTB[0:2] voltage
Pin voltage at VDDX
on page 16
mA
V
V
-0.3 to 42 max.
-0.3 to VDDX+0.5
-0.3 to 5.75
PTB3
VPTB0-2
VDDX
V
V
VDDH
Pin voltage at VDDH
-0.3 to 2.75
V
I
VDDH output current
internally limited
internally limited
-0.3 to VDDX+0.5
-0.3 to VDDX+0.5
A
VDDH
I
VDDX output current
A
VDDX
V
TCLK pin voltage
V
TCLK
V
RESET_A pin voltage
V
IN
Notes
5. It has to be assured by the application circuit that these limits will not be exceeded, e.g. by ISO pulse 1.
Table 8. Maximum electrical ratings - MCU die (continued)
Ratings
Symbol
VDDRX
VDDD2D
VIN
Value
Unit
V
5.0 V supply voltage
2.5 V supply voltage
Digital I/O input voltage (PTA0...7)
EXTAL, XTAL
-0.3 to 6.0
-0.3 to 3.6
-0.3 to 6.0
-0.3 to 2.16
-25 to 25
V
V
VIN
V
Instantaneous maximum current single pin limit for all digital I/O pins(6)
ID
mA
MM912_637D1
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Table 8. Maximum electrical ratings - MCU die (continued)
Ratings
Symbol
Value
Unit
Instantaneous maximum current single pin limit for EXTAL, XTAL
IDL
-25 to 25
mA
Notes
6. All digital I/O pins are internally clamped to VSSRX and VDDRX
.
Table 9. Maximum thermal ratings
Ratings
Symbol
Value
-55 to 150
25 typ.
Unit
C
TSTG
Storage temperature
Package thermal resistance (7)
C/W
R
JA
Notes
7. R JA value is derived using a JEDEC 2s2p test board
3.3
Operating conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 10. Operating conditions (8)
Ratings
Symbol
Value
Unit
VSUP
3.5 to 28
V
Functional operating supply voltage - Device is fully functional. All features are
operating.
VSUPL
2.5 to 3.5
V
Extended range for RAM Content is guaranteed. Other device functionary is
limited. With cranking mode enabled (seeSection 4.3.3.4, “Low-voltage
operation - cranking mode device option").
Functional operating VSENSE voltage (9)
Functional operating VOPT voltage
External temperature sense input - VTEMP
LIN output voltage range
0 to 28
0 to 28
V
V
VSENSE
VOPT
VTEMP
VVSUP_LIN
VISENSE
VDDRX
VDDD2D
fOSC
0 to 1.25
V
7.0 to 18
V
ISENSEH / ISENSEL terminal voltage
MCU 5.0 V supply voltage
-0.3 to 0.3
3.13 to 5.5
2.25 to 3.6
4.0 to 16
V
V
MCU 2.5 V supply voltage
V
MCU oscillator
MHz
MHz
C
C
C
MCU bus frequency
fBUS
max. 32.768
-40 to 125
-40 to 150
-40 to 150
T
A
Operating ambient temperature
Operating junction temperature - analog die
Operating junction temperature - MCU die
T
J_A
T
J_M
Notes
8. The parametric data are guaranteed while the pins are within Operating Conditions. Other conditions are presented at the top of the parametric tables
or noted into parameters.
9. Values VSENSE > 28 V are flagged in the VSENSE
MM912_637D1
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3.4
Supply currents
This section describes the current consumption characteristics of the device, as well as the conditions for the measurements.
3.4.1
Measurement conditions
All measurements are without output loads. The currents are measured in MCU special single chip mode, and the CPU code is executed
from RAM, unless otherwise noted.
For Run and Wait current measurements, PLL is on and the reference clock is the IRC1M, trimmed to 1.024 MHz. The bus frequency is
32.768 MHz and the CPU frequency is 65.536 MHz. Table 11 and Table 12 show the configuration of the CPMU module for Run, Wait,
and Stop current measurements. Table 13 shows the configuration of the peripherals for run current measurements
Table 11. CPUM configuration for run/wait and full stop current measurement
CPMU register
CPMUSYNR
CPMUPOSTDIV
CPMUCLKS
Bit settings/conditions
VCOFRQ[1:0]=01,SYNDIV[5:0] = 32.768 MHz
POSTDIV[4:0]=0,
PLLSEL=1
CPMUOSC
OSCE=0, Reference clock for PLL is fREF=fIRC1M trimmed to 1.024 MHz
Table 12. CPMU configuration for pseudo stop current measurements
CPMU register
Bit settings/conditions
CPMUCLKS
CPMUOSC
CPMURTI
PLLSEL=0, PSTP=1, PRE=PCE=RTIOSCSEL=COPOSCSEL=1
OSCE=1, External square wave on EXTAL fEXTAL=16 MHz, VIH= 1.8 V, VIL=0 V
RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111;
CPMUCOP
WCOP=1, CR[2:0]=111
Table 13. MCU peripheral configurations for run supply current measurements
Peripheral
SPI
Configuration
configured to master mode, continuously transmit data (0x55 or 0xAA) at 4.0 Mbit/s
continuously read data
D2DI
COP
COP Watchdog Rate 224
RTI
enabled, RTI Control Register (RTICTL) set to $FF
The module is disabled.
DBG
Table 14. Analog die configurations for normal mode supply current measurements
Peripheral
D2D
Configuration
maximum frequency (32.768 MHz)
LIN
enabled, 50% dominant, 50% recessive
TIMER
LTC
enabled, all channels active in output compare mode with minimum timeout
enabled, maximum timeout
SCI
continuously transmitting data (0x55 or 0xAA) with 19.2 kBit/s
current/voltage: highest sampling rate (8.0 kHz), LPF enabled, chopper and compensation enabled, automatic gain
adjustment enabled temperature: internal temperature measurement enabled, 1.0 kHz sampling rate
Acquisition Channels
MM912_637D1
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Table 15. Supply currents(10)
Ratings
Symbol
Min.
Typ.(12)
Max.
Unit
MM912_637 combined consumption
IRUN
Normal mode current both dice
25
mA
ISTOP
Stop Mode current measured at VSUP
Continuous base current (12)
-40 °C iSTOP_S
–
–
–
100
105
106
120
190
230
85 °C (11)
125 °C
Pseudo Stop Current, RTI and COP enabled (12)
-40 °C iSTOP_S
–
–
–
410
450
520
490
520
590
85 °C (11)
µA
125 °C
Stop Current during Cranking Mode
-40 °C iSTOP_S
85 °C (11)
125 °C
–
–
–
–
105
125
185
130
230
270
Current adder during current trigger event - (typ. 10 ms duration(14), temperature
measurement = OFF)
1500
1750
ISLEEP
Sleep Mode measured at VSUP
-40 °C iSTOP_S
85 °C (11)
–
–
–
–
60
60
80
80
130
140
1750
µA
125 °C
Current adder during current trigger event - (typ. 10 ms duration (14), temperature
measurement = OFF)
1500
Analog die contribution - excluding MCU and external load current, (3.5 V VSUP 28 V; -40 °C TA 125 °C)
INORMAL
Normal mode current measured at VSUP
MCU die contribution, VDDRX = 5.5 V
Run Current, TA 125 °C
1.5
4.0
mA
IRUN
13.5
7.0
18.8
8.8
mA
mA
IWAIT
Wait current, TA 125 °C
Notes
10. See Table 11, Table 12, Table 13, and Table 14 for conditions. Currents measured in Test mode with external loads (100 pF) and the external clock
at 64 MHz.
11. Not tested in production, guaranteed by characterization
12. Typical values noted reflect the approximate parameter mean at TA = 25 °C.
13. From VSUP 6.0 to 28 V
14. Duration based on channel configuration. 10ms typical for Decimation Factor = 512, Chopper = ON.
MM912_637D1
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3.5
Static electrical characteristics
All characteristics noted under conditions 3.5 V VSUP28 V, -40 C TA125 C, unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
3.5.1
Static electrical characteristics analog die
Table 16. Static electrical characteristics - power supply
Ratings
Symbol
Min.
1.75
1.85
Typ.
1.9
Max.
2.1
Unit
VPORL
Low Voltage Reset L (POR) Assert (measured on VDDL)
Cranking Mode Disabled
V
VPORH
Low Voltage Reset L (POR) Deassert (measured on VDDL)
Cranking Mode Disabled
V
V
2.1
2.35
VPORCL
Low Voltage Reset L (POR) Assert (measured on VDDL)
Cranking Mode Enabled(15)
1.0
1.9
2.0
2.5
2.7
1.9
2.05
1.3
2.05
2.15
2.75
2.95
2.075
2.175
1.7
2.2
2.3
3.0
3.25
2.2
2.3
VLVRAL
VLVRAH
VLVRXL
VLVRXH
VLVRHL
VLVRHH
VUVIL
Low Voltage Reset A (LVRA) Assert (measured on VDDA)
Low Voltage Reset A (LVRA) Deassert (measured on VDDA)
Low Voltage Reset X (LVRX) Assert (measured on VDDX)
Low Voltage Reset X (LVRX) Deassert (measured on VDDX)
Low Voltage Reset H (LVRH) Assert (measured on VDDH)
Low Voltage Reset H (LVRH) Deassert (measured on VDDH)
V
V
V
V
V
V
Undervoltage Interrupt (UVI) Assert (measured on VSUP), Cranking Mode
Disabled
4.55
4.7
5.2
5.4
3.6
6.1
6.2
4.0
4.1
V
V
V
VUVIH
VUVCIL
VUVCIH
VTH
Undervoltage Interrupt (UVI) Deassert (measured on VSUP), Cranking Mode
Disabled
Undervoltage Cranking Interrupt (UVI) Assert (measured on VSUP) Cranking
Mode Enabled
3.4
Undervoltage Cranking Interrupt (UVI) Deassert (measured on VSUP) Cranking
Mode Enabled
3.5
3.8
28
V
V
VSENSE/VOPT High Voltage Warning Threshold Assert(16)
Notes
15. Deassert with Cranking off = VPORH
16. 5.0 V < VSUP < 28 V, Digital Threshold at the end of channel chain (incl. compensation)
Table 17. Static electrical characteristics - resets
Ratings
Low-state Output Voltage IOUT = 2.0 mA
Symbol
Min.
Typ.
Max.
0.8
Unit
V
VOL
RRPU
VIL
Pull-up Resistor
25
50
k
V
Low-state Input Voltage
High-state Input Voltage
Reset Release Voltage (VDDX)
RESET_A pin Current Limitation
0.3VDDX
VIH
0.7VDDX
0
V
VRSTRV
ILIMRST
0.02
1.0
10
V
mA
MM912_637D1
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Table 18. Static electrical characteristics - voltage regulator outputs
Ratings
Symbol
Min.
Typ.
Max.
Unit
Analog Voltage Regulator - VDDA(17)
VDDA
IVDDA
Output Voltage 1.0 mA I
1.5 mA
2.25
2.5
2.75
10
V
VDDA
Output Current Limitation
mA
Low Power Digital Voltage Regulator - VDDL(17)
Output Voltage
VDDL
2.25
2.4
2.5
2.5
2.75
V
High Power Digital Voltage Regulator - VDDH(18)
VDDH
IVDDH
Output Voltage 1.0 mA I
30 mA
2.75
65
V
VDDH
Output Current Limitation
mA
5.0 V Voltage Regulator - VDDX(18)
VDDX
IVDDX
Output Voltage 1.0 mA I
30 mA
3.15
45
5.0
60
5.9
80
V
VDDX
Output Current Limitation
mA
Notes
17. No additional current must be taken from those outputs.
18. The specified current ranges does include the current for the MCU die. No external loads recommended.
Table 19. Static electrical characteristics - LIN physical layer interface - LIN
Ratings
Symbol
Min.
Typ.
Max.
Unit
IBUSLIM
Current Limitation for Driver dominant state. VBUS = 18 V
40
120
200
mA
IBUS_PAS_DOM
IBUS_PAS_REC
IBUS_NO_GND
IBUS_NO_BAT
Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE
Driver OFF; VBUS = 0 V; VBAT = 12 V
;
;
-1.0
mA
µA
Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE
Driver OFF; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT
20
Input Leakage Current; GND Disconnected; GNDDEVICE = VSUP
0 < V < 18 V; VBAT = 12 V
;
-1.0
1.0
mA
µA
BUS
Input Leakage Current; V
disconnected; VSUP_DEVICE = GND; 0 <
BAT
100
0.4
V
< 18 V
BUS
VBUSDOM
VBUSREC
VBUS_CNT
VBUS_HYS
DSER_INT
RSLAVE
Receiver Input Voltage; Receiver Dominant State
Receiver Input Voltage; Receiver Recessive State
Receiver Threshold Center (VTH_DOM + VTH_REC)/2
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM
Voltage Drop at the serial Diode
VSUP
VSUP
VSUP
VSUP
V
0.6
0.475
0.5
0.525
0.175
1.0
)
0.3
20
0.7
30
LIN Pull-up Resistor
60
k
VDOM
Low Level Output Voltage, IBUS=40 mA
High Level Output Voltage, IBUS=-10 µA, RL=33 k
J2602 Detection Deassert Threshold for VSUP level
J2602 Detection Assert Threshold for VSUP level
J2602 Detection Hysteresis
0.3
VSUP
V
VREC
VSUP-1
5.9
VJ2602H
VJ2602L
VJ2602HYS
VLINWUP
6.3
6.2
6.7
6.6
250
6.0
V
5.8
V
70
190
5.25
mV
V
BUS Wake-up Threshold
4.0
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Table 20. Static electrical characteristics - high voltage input - PTB3 / L0
Ratings
Symbol
VWTHR
VIH
Min.
1.3
Typ.
Max.
3.4
Unit
V
Wake-up Threshold - Rising Edge
Input High Voltage (digital Input)
Input Low Voltage (digital Input)
Input Hysteresis
2.6
0.7VDDX
VSS-0.3
50
VDDX+0.3
0.35VDDX
200
V
VIL
V
VHYS
VL0CLMP
IIN
140
6.0
mV
V
Internal Clamp Voltage
4.9
7.0
Input Current PTB3 / L0 (VIN = 42 V; RL0=47 k)
Internal pull-down resistance(19)
PTB3 / L0 Series Resistor
1.1
mA
k
k
nF
RPD
50
100
47
200
RPTB3
CL0
42.3
42.3
51.7
PTB3 / L0 Capacitor
47
51.7
Notes
19. Disabled by default.
Table 21. Static electrical characteristics - general purpose I/O - PTB[0...2]
Ratings
Symbol
Min.
0.7VDDX
VSS-0.3
50
Typ.
Max.
VDDX+0.3
0.35VDDX
200
Unit
V
VIH
VIL
Input High Voltage
Input Low Voltage
Input Hysteresis
V
VHYS
IIN
140
mV
Input Leakage Current (pins in high-impedance input mode)
(VIN = VDDX or VSSX
-1.0
1.0
µA
)
VOH
VOL
Output High Voltage (pins in output mode) Full drive IOH = –5.0 mA
Output Low Voltage (pins in output mode) Full drive IOL = 5.0 mA
Internal Pull-up Resistance (VIH min. > Input voltage > VIL max)(20)
Input Capacitance
VDDX-0.8
V
V
0.8
50
RPUL
CIN
25
37.5
6.0
k
pF
mA
pF
Maximum Current All PTB Combined(21)
-17
17
IBMAX
COUT
Output Drive strength at 10 MHz
100
Notes
20. Disabled by default.
21. Overall VDDR Regulator capability to be considered.
Table 22. Static electrical characteristics - current sense module(22) (continued)
Ratings
Symbol
Min.
Typ.
Max.
0.5
Unit
IGAINERR
Gain Error
with temperature based gain compensation adjustment(23), (24)
-0.5
+/-0.1
%
Offset Error(25) (26)
,
0.5
µV
µV
IOFFSETERR
IRES
Resolution
0.1
ISENSEH, ISENSEL
terminal voltage
VINC
VIND
-300
-200
300
200
mV
differential signal voltage range
ISENSE_DLC
Differential Leakage Current: differential voltage between ISENSEH/
ISENSEL, 200 mV
-2.0
2.0
nA
µV
IRESWAKE
Wake-up Current Threshold Resolution
0.2
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Table 22. Static electrical characteristics - current sense module(22) (continued)
Ratings
Resistor Threshold for OPEN Detection
Notes
Symbol
Min.
Typ.
Max.
Unit
ROPEN
0.8
1.25
1.8
M
22. 3.5 V VSUP 28 V, after applying default trimming values - see Section 5, “MM912_637 - trimming".
23. Gain Compensation adjustment on calibration request interrupt with TCALSTEP
24. 0.65%, including lifetime drift for gain 256 and 512
25. Chopper Mode = ON, Gain with automatic gain control enabled
26. Parameter not tested. Guaranteed by design and characterization
Table 23. Static electrical characteristics - voltage sense module(27)
Ratings
Symbol
Min.
Typ.
Max.
Unit
Gain Error(28)
VGAINERR
18 V VIN 28 V
-0.5
-0.25
-0.15
0.1
0.1
0.1
0.5
0.25
0.15
%
3.5 V VIN 5.0 V(29)
5.0 V VIN 18 V(29),(31)
Offset Error(30),(32)
-1.5
1.5
0.5
mV
mV
VOFFSETERR
VRES
Resolution with RVSENSE = 2.2 k
Notes
27. 3.5 V VSUP 28 V, after applying default trimming values - see Section 5, “MM912_637 - trimming".
28. Including resistor mismatch drift
29. Gain Compensation adjustment on calibration request interrupt with TCALSTEP
30. Chopper Mode = ON.
31. 0.2%, including lifetime drift
32. Parameter not tested. Guaranteed by design and characterization.
Table 24. Static electrical characteristics - temperature sense module(33)
Ratings
Symbol
Min.
Typ.
Max.
Unit
TRANGE
Measurement Range
-40
150
°C
TACC
Accuracy
-40 °C TA 60 °C(34)
-40 °C TA 50 °C
-2.0
-3.0
2.0
3.0
K
TRES
VTSUP
Resolution
8.0
1.25
220
mK
V
TSUP Voltage Output, 10 µA I
TSUP Capacitor with ECAP = 1
100 µA
1.1875
209
1.3125
231
TSUP
CTSUP
pF
K
TCALSTEP
Max Calibration Request Interrupt Temperature Step
-25
25
Notes
33. 3.5 V VSUP 28 V, after applying default trimming values - see Section 5, “MM912_637 - trimming".
34. Temperature not tested in production. Guaranteed by design and characterization.
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3.5.2
Static electrical characteristics MCU die
Table 25. Static electrical characteristics - MCU
Ratings
Symbol
Min.
0.6
-
Typ.
0.9
Max.
-
Unit
V
VPORA
Power On Reset Assert (measured on VDDRX)
Power On Reset Deassert (measured on VDDRX)
Low Voltage Reset Assert (measured on VDDRX)
Low Voltage Reset Deassert (measured on VDDRX)
Low Voltage Interrupt Assert (measured on VDDRX)
Low Voltage Interrupt Deassert (measured on VDDRX)
VPORD
VLVRA
VLVRD
VLVIA
0.95
3.06
3.09
4.21
4.34
1.6
-
V
2.97
-
V
3.3
4.36
4.49
V
4.06
4.19
V
VLVID
V
Table 26. Static electrical characteristics - oscillator (OSCLCP)
Ratings
Symbol
iOSC
Min.
Typ.
Max.
Unit
A
pF
Startup Current
100
Input Capacitance (EXTAL, XTAL pins)
EXTAL Pin Input Hysteresis
CIN
7.0
180
0.9
VHYS,EXTAL
VPP,EXTAL
—
—
—
—
mV
V
EXTAL Pin oscillation amplitude (loop controlled Pierce)
Table 27. 5.0 V I/O characteristics for all I/O pins except EXTAL, XTAL, TEST, D2DI, and supply pins
(4.5 V < VDDRX < 5.5 V; TJ: –40 °C to +150 °C, unless otherwise noted) (continued)
Ratings
Symbol
VIH
Min.
0.65*VDDRX
—
Typ.
—
Max.
Unit
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Input Hysteresis
—
VDDRX+0.3
0.35*VDDRX
—
V
V
VIH
—
VIL
—
—
V
VIL
VSSRX–0.3
—
V
V
250
—
mV
HYS
IIN
Input Leakage Current (pins in high-impedance input mode)(35)
= V or V
A
V
–1.00
—
1.00
IN
DDRX
SSRX
Input Leakage Current (pins in high-impedance input mode)(36)
V
= V or V
1.0
1.0
8.0
14
26
32
40
60
74
92
240
IN
DDX
SSX
TA = –40 C
TA = 25 C
TA = 70 C
TA = 85 C
TA = 105 C
TA = 110 C
TA = 120 C
TA = 125 C
TA = 130 C
TA = 150 C
IIN
nA
Output High Voltage (pins in output mode), I
= –4.0 mA
VOH
VOL
IPUL
IPDH
Cin
VDDRX – 0.8
—
—
—
—
7
—
0.8
-130
130
—
V
OH
Output Low Voltage (pins in output mode), I
OL
= 4.0 mA
—
-10
10
—
V
Internal Pull-up Current, VIH min > input voltage > VIL max
Internal Pull-down Current, VIH min > input voltage > VIL max
Input Capacitance
A
A
pF
MM912_637D1
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Table 27. 5.0 V I/O characteristics for all I/O pins except EXTAL, XTAL, TEST, D2DI, and supply pins
(4.5 V < VDDRX < 5.5 V; TJ: –40 °C to +150 °C, unless otherwise noted) (continued)
Ratings
Symbol
Min.
Typ.
Max.
Unit
Injection Current(37)
Single pin limit
IICS
IICP
–2.5
–25
—
2.5
25
mA
Total device Limit, sum of all injected currents
Notes
35. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8.0 C to 12 C in the
temperature range from 50 C to 125 C.
36. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8.0 C to 12 C in the
temperature range from 50 C to 125 C.
37. Refer to Section 3.5.2.1, “Current injection" for more details
3.5.2.1
Current injection
The power supply must maintain regulation within the VDDX operating range during instantaneous and operating maximum current
conditions. If positive injection current (VIN > VDDX) is greater than IDDX, the injection current may flow out of VDDX and could result in
the external power supply going out of regulation. Ensure that the external VDDX load will shunt current greater than the maximum injection
current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if the clock rate is very
low, which would reduce overall power consumption.
3.6
Dynamic electrical characteristics
Dynamic characteristics noted under conditions 3.5 V VSUP28 V, -40 C TA125 C, unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
3.6.1
Dynamic electrical characteristics analog die
Table 28. Dynamic electrical characteristics - modes of operation
Ratings
Symbol
Min.
Typ.
Max.
Unit
fOSCL
Low Power Oscillator Frequency
—
512
—
kHz
fTOL_A
Low Power Oscillator Tolerance over full temperature range
Analog Option 2
Analog Option 1
-4.0
-5.0
—
—
4.0
5.0
%
%
Low Power Oscillator Tolerance - synchronized ALFCLK(38)
ALF clock cycle = 1.0 ms
fTOLC_A
fTOL-0.2
fTOL-0.1
fTOL-0.05
fTOL-0.025
fTOL+0.2
fTOL+0.1
fTOL+0.05
fTOL+0.025
ALF clock cycle = 2.0 ms
ALF clock cycle = 4.0 ms
ALF clock cycle = 8.0 ms
fTOL
Notes
38. Parameter not tested. Guaranteed by design and characterization.
Table 29. Dynamic electrical characteristics - die to die interface - D2D
Ratings
Symbol
Min.
Typ.
Max.
Unit
fD2D
Operating Frequency (D2DCLK, D2D[0:3])
—
—
32.768
MHz
Table 30. Dynamic electrical characteristics - resets
Ratings
Symbol
Min.
1.0
—
Typ.
2.0
32
Max.
3.2
Unit
µs
tRSTDF
Reset Deglitch Filter Time
tRSTRT
Reset Time for watchdog and Hardware Reset (RESETA pin set low)
—
µs
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Table 31. Dynamic electrical characteristics - wake-up / cyclic sense
Ratings
Cyclic Wake-up Time(39)
Symbol
Min.
Typ.
—
Max.
TIM4CH
16Bit
Unit
ms
t
ALFCLK
ALFCLK
WAKEUP
tSTEP
Cyclic Current Measurement Step Width(40)
—
ms
Notes
39. Cyclic wake-up on ALFCLK clock based 16 Bit TIMER with maximum 128x prescaler (min 1x)
40. Cyclic wake-up on ALFCLK clock with 16 Bit programmable counter
Table 32. Dynamic electrical characteristics - window watchdog
Ratings
Initial Non-window Watchdog Timeout
Symbol
Min.
Typ.
Max.
Unit
tIWDTO
see Figure 39
ms
Table 33. Dynamic electrical characteristics - LIN physical layer interface - LIN (continued)
Ratings
Bus Wake-up Deglitcher (Sleep and Stop Mode)
Fast Bit Rate (Programming Mode)
Symbol
Min.
60
Typ.
80
—
Max.
100
100
6.0
Unit
µs
tPROPWL
BRFAST
tRX_PD
—
kBit/s
µs
Propagation delay of receiver
—
—
tRX_SYM
Symmetry of receiver propagation delay rising edge w.r.t. falling edge
-2.0
—
2.0
µs
LIN driver - 20.0 kBit/s; bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660 / 10 nF;500
D1
Duty Cycle 1:
THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP
7.0 V VSUP18 V; tBIT = 50 µs;
0.396
—
—
—
D1 = tBUS_REC(MIN)/(2 x tBIT
)
D2
Duty Cycle 2:
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP
—
0.581
7.6 V VSUP18 V; tBit = 50 µs
D2 = tBUS_REC(MAX)/(2 x tBIT
)
LIN driver - 10.0 kBit/s; bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660 / 10 nF;500
D3
Duty Cycle 3:
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7.0 V VSUP18 V; tBit = 96 µs
0.417
—
—
—
D3 = tBUS_REC(MIN)/(2 x tBIT
)
D4
Duty Cycle 4:
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
—
0.590
7.6 V VSUP18 V; tBIT = 96 µs
D4 = tBUS_REC(MAX)/(2 x tBIT
)
LIN Transmitter Timing, (VSUP from 7.0 to 18 V) - See Figure 5
tTRAN_SYM
Transmitter Symmetry
tTRAN_SYM < MAX(ttran_sym60%, tTRAN_SYM40%)
tTRAN_SYM60% = tTRAN_PDF60% - tTRAN_PDR60%
tTRAN_SYM40% = tTRAN_PDF40% - tTRAN_PDR40%
-7.25
0
7.25
µs
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TX
BUS
60%
40%
ttran_pdf60%
ttran_pdf40%
ttran_pdr40%
ttran_pdr60%
Figure 5. LIN transmitter timing
Table 34. Dynamic electrical characteristics - general purpose I/O - PTB3 / L0]
Ratings
Symbol
Min.
Min.
Typ.
Max.
Unit
tWUPF
Wake-up Glitch Filter Time
20
µs
Table 35. Dynamic electrical characteristics - general purpose I/O - PTB[0...2]
Ratings
Symbol
Typ.
Max.
10
Unit
MHz
ns
fPTB
GPIO Digital Frequency
Propagation Delay - Rising Edge(41)
Rise Time - Rising Edge(41)
20
tPDr
tRISE
tPDf
17.5
20
ns
Propagation Delay - Falling Edge(41)
Rise Time - Falling Edge(41)
ns
tFALL
17.5
ns
Notes
41. Load PTBx = 100 pF
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Table 36. Dynamic Electrical Characteristics - Current Sense Module
Ratings
Symbol
Min
Typ
Max
Unit
Frequency Attenuation(42),(43)
<100 Hz (fPASS
>500 Hz (fSTOP
)
)
dB
3.0
8.0
40
Signal Update Rate(44)
0.5
kHz
µs
fIUPDATE
fIVMATCH
tGC
Signal Path Match with Voltage Channel
Gain Change Duration (Automatic GCB active)(45)
2.0
14
µs
Notes
42. Characteristics identical to Voltage Sense Module
43. With default LPF coefficients
44. After passing decimation filter
45. Parameter not tested. Guaranteed by design and characterization.
Table 37. Dynamic electrical characteristics - voltage sense module
Ratings
Symbol
Min.
Typ.
Max.
Unit
Frequency attenuation(46),(47)
95...105 Hz (fPASS
>500 Hz (fSTOP
)
dB
3.0
8.0
)
40
Signal update rate(48)
0.5
kHz
µs
fVUPDATE
fIVMATCH
Signal path match with Current Channel(49)
2.0
Notes
46. Characteristics identical to Voltage Sense Module
47. With default LPF coefficients
48. After passing decimation filter
49. Parameter not tested. Guaranteed by design and characterization.
Table 38. Dynamic electrical characteristics - temperature sense module
Ratings
Symbol
fTUPDATE
Min.
Typ.
Max.
Unit
Signal Update Rate(50)
Notes
1.0
4.0
kHz
50. 1.0 kHz with Chopper Enabled, 4.0 kHz with Chopper Disabled (fixed decimeter = 128)
3.6.2
Dynamic electrical characteristics MCU die
3.6.2.1
NVM
3.6.2.1.1
Timing parameters
The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this
derived clock must be set within the limits specified as fNVMOP. The NVM module does not have any means to monitor the frequency, and
will not prevent program or erase operations at frequencies above or below the specified minimum. When attempting to program or erase
the NVM module at a lower frequency, a full program or erase transition is not assured.
The following sections provide equations which can be used to determine the time required to execute specific flash commands. All timing
parameters are a function of the bus clock frequency, fNVMBUS. All program and erase times are also a function of the NVM operating
frequency, fNVMOP. A summary of key timing parameters can be found in Table 39.
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3.6.2.1.1.1 Erase verify all blocks (blank check) (FCMD=0x01)
The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address
zero. It takes one bus cycle per phrase to verify, plus a setup of the command. Assuming that no non-blank location is found, then the time
to erase verify all blocks is given by:
1
-------------------
tcheck = 35500
fNVMBUS
3.6.2.1.1.2 Erase verify block (blank check) (FCMD=0x02)
The time required to perform a blank check is dependent on the location of the first non-blank word starting at relative address zero. It
takes one bus cycle per phrase to verify, plus a setup of the command.
Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by:
1
-------------------
tpcheck = 33500
fNVMBUS
Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by:
1
-------------------
tdcheck = 2800
fNVMBUS
3.6.2.1.1.3 Erase verify p-flash section (FCMD=0x03)
The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified (NVP) and is given by:
1
-------------------
t 450 + NVP
fNVMBUS
3.6.2.1.1.4 Read once (FCMD=0x04)
The maximum read once time is given by:
1
-------------------
t = 400
fNVMBUS
3.6.2.1.1.5 Program p-flash (FCMD=0x06)
The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is dependent on the bus frequency,
fNVMBUS, as well as on the NVM operating frequency, fNVMOP
.
The typical phrase programming time is given by:
1
1
-----------------
-------------------
tppgm 164
+ 2000
fNVMOP
fNVMBUS
The maximum phrase programming time is given by:
1
1
-----------------
-------------------
tppgm 164
+ 2500
fNVMOP
fNVMBUS
3.6.2.1.1.6 Program once (FCMD=0x07)
The maximum time required to program a P-Flash Program Once field is given by:
1
1
-----------------
-------------------
t 164
+ 2150
fNVMOP
fNVMBUS
3.6.2.1.1.7 Erase all blocks (FCMD=0x08)
The time required to erase all blocks is given by:
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1
1
-----------------
-------------------
tmass 100100
+ 70000
fNVMOP
fNVMBUS
3.6.2.1.1.8 Erase p-flash block (FCMD=0x09)
The time required to erase the P-Flash block is given by:
1
1
-----------------
-------------------
tpmass 100100
+ 67000
fNVMOP
fNVMBUS
3.6.2.1.1.9 Erase p-flash sector (FCMD=0x0A)
The typical time to erase a 512-byte P-Flash sector is given by:
1
1
-----------------
-------------------
tpera 20020
+ 700
fNVMOP
fNVMBUS
The maximum time to erase a 512-byte P-Flash sector is given by:
1
1
-----------------
-------------------
tpera 20020
+ 1400
fNVMOP
fNVMBUS
3.6.2.1.1.10 Unsecure flash (FCMD=0x0B)
The maximum time required to erase and unsecure the Flash is given by:
(for 128 kByte P-Flash and 4.0 kByte D-Flash)
1
1
-----------------
-------------------
tuns 100100
+ 70000
fNVMOP
fNVMBUS
3.6.2.1.1.11 Verify backdoor access key (FCMD=0x0C)
The maximum verify back door access key time is given by:
1
-------------------
t = 400
fNVMBUS
3.6.2.1.1.12 Set user margin level (FCMD=0x0D)
The maximum set user margin level time is given by:
1
-------------------
t = 350
fNVMBUS
3.6.2.1.1.13 Set field margin level (FCMD=0x0E)
The maximum set field margin level time is given by:
1
-------------------
t = 350
fNVMBUS
3.6.2.1.1.14 Erase verify d-flash section (FCMD=0x10)
The time required to Erase Verify D-Flash for a given number of words NW is given by:
1
-------------------
tdcheck 450 + NW
fNVMBUS
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3.6.2.1.1.15 Program d-flash (FCMD=0x11)
D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary,
since programming across a row boundary requires extra steps. The D-Flash programming time is specified for different cases: 1,2,3,4
words and 4 words across a row boundary. The typical D-Flash programming time is given by the following equation, where NW denotes
the number of words; BC=0 if no row boundary is crossed and BC=1, if a row boundary is crossed:
1
1
-----------------
-------------------
tdpgm 14 + 54 NW + 14 BC
+ 500 + 525 NW + 100 BC
fNVMOP
fNVMBUS
The maximum D-Flash programming time is given by:
1
1
-----------------
-------------------
tdpgm 14 + 54 NW + 14 BC
+ 500 + 750 NW + 100 BC
fNVMOP
fNVMBUS
3.6.2.1.1.16 Erase d-flash sector (FCMD=0x12)
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given by:
1
1
-----------------
-------------------
tdera 5025
+ 700
fNVMOP
fNVMBUS
Maximum D-Flash sector erase times is given by:
1
1
-----------------
-------------------
tdera 20100
+ 3400
fNVMOP
fNVMBUS
The D-Flash sector erase time is ~5.0 ms on a new device and can extend to ~20 ms as the flash is cycled.
Table 39. NVM timing characteristics (FTMRC)
Rating
Symbol
fNVMBUS
fNVMOP
tMASS
Min.
1.0
0.8
—
Typ.(51)
—
Max.(52)
32.768
1.05
130
Unit(53)
MHz
MHz
ms
Bus Frequency
Operating Frequency
1.0
Erase All Blocks (mass erase) Time
Erase Verify All Blocks (blank check) Time
Unsecure Flash Time
100
—
tCHECK
tUNS
—
35500
130
tCYC
ms
—
100
100
—
P-flash Block Erase Time
tPMASS
tPCHECK
tPERA
—
130
ms
P-flash Erase Verify (blank check) Time
P-flash Sector Erase Time
—
33500
26
tCYC
ms
—
20
P-flash Phrase Programming Time
D-flash Sector Erase Time
tPPGM
—
226
5(54)
—
285
s
tDERA
—
26
ms
D-flash Erase Verify (blank check) Time
D-flash One Word Programming Time
D-flash Two Word Programming Time
D-flash Three Word Programming Time
D-flash Four Word Programming Time
D-flash Four Word Programming Time Crossing Row Boundary
tDCHECK
tDPGM1
tDPGM2
tDPGM3
tDPGM4
tDPGM4C
—
2800
107
tCYC
s
—
100
170
241
311
328
—
185
s
—
262
s
—
339
s
—
357
s
Notes
51. Typical program and erase times are based on typical fNVMOP and maximum fNVMBUS
52. Maximum program and erase times are based on minimum fNVMOP and maximum fNVMBUS
53. tCYC = 1 / fNVMBUS
54. Typical value for a new device
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3.6.2.1.2
NVM reliability parameters
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors, and burn-in to screen early
life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase
cycle count on the sector is incremented every time a sector or mass erase event is executed.
Table 40. NVM reliability characteristics(55)
Rating
Symbol
tNVMRET
nFLPE
Min.
20
Typ.
Max.
—
Unit
Years
Cycles
Years
Data retention at an average junction temperature of TJAVG = 85 C(55) after up to
100(57)
100 K(58)
100(57)
10,000 program/erase cycles
Program Flash number of program/erase cycles (-40 C TJ 150 C
10 K
5.0
—
Data retention at an average junction temperature of TJAVG = 85 C(55) after up to
tNVMRET
—
50,000 program/erase cycles
Data retention at an average junction temperature of TJAVG = 85 C(55) after up to
10,000 program/erase cycles
tNVMRET
10
100(57)
—
Years
Data retention at an average junction temperature of TJAVG = 85 C(55) after less than
tNVMRET
nFLPE
20
100(57)
—
—
Years
100 program/erase cycles
Data Flash number of program/erase cycles (-40 C TJ 150C
50 K
500 K(58)
Cycles
Notes
55. Conditions are shown in Table 10, unless otherwise noted
56. TJAVG does not exceed 85 C in a typical temperature profile over the lifetime of a consumer, industrial, or automotive application.
57. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the
Arrhenius equation. For additional information on how NXP defines Typical Data Retention, refer to Engineering Bulletin EB618
58. Spec table quotes typical endurance evaluated at 25C for this product family. For additional information on how NXP defines Typical Endurance,
refer to Engineering Bulletin EB619.
3.6.2.2
Phase locked loop
Jitter definitions
3.6.2.2.1
With each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature, and
other factors, cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock
periods as illustrated in Figure 6.
1
2
3
N-1
N
0
t
min1
t
nom
t
max1
t
minN
t
maxN
Figure 6. Jitter definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
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Defining the jitter as:
t
N
t
N
max
min
----------------------
----------------------
, 1 –
JN = max 1 –
N t
N t
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
-------
JN =
N
J(N)
1
5
10
20
N
Figure 7. Maximum bus clock jitter approximation
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent.
3.6.2.2.2
Electrical characteristics for the PLL
Table 41. PLL characteristics
Rating
Symbol
fVCORST
fVCO
Min
8
Typ
Max
Unit
MHz
MHz
VCO Frequency During System Reset
VCO Locking Range
Lock Detection
32
65.536
1.5
32.768
0
(59)
LOCK
UNL
tLOCK
j1
|
%
(59)
Un-lock Detection
|
0.5
2.5
%
Time to Lock
150 + 256/fREF
1.2
s
Jitter Fit Parameter 1(60)
%
Notes
59. % deviation from target frequency
60. fREF = 1.024 MHz, fBUS = 32.768 MHz equivalent fPLL = 65.536 MHz, REFRQ=00, SYNDIV=$1F, VCOFRQ=01, POSTDIV=$00
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3.6.2.3
Reset, oscillator and internal clock generation
Table 42. Dynamic electrical characteristics - MCU clock generator
Ratings
Symbol
fBUS
Min.
—
Typ.
—
Max.
32.768
—
Unit
MHz
MHz
Bus Frequency
Internal Reference Frequency
fIRC1M_TRIM
—
1.024
Internal Clock Frequency Tolerance(61),(62)
Analog Option 2
fTOL
-1.0
-1.2
—
—
1.0
1.2
%
Analog Option 1
Clock Frequency Tolerance with External Oscillator(63)
Crystal Oscillator Range
tTOLEXT
fOSC
-0.5
4.0
—
0.5
16
%
MHz
ms
Oscillator Start-up Time (LCP, 4.0 MHz)(64)
Oscillator Start-up Time (LCP, 8.0 MHz)(64)
Oscillator Start-up Time (LCP, 16 MHz)(64)
Clock Monitor Failure Assert Frequency
tUPOSC
tUPOSC
tUPOSC
fCMFA
2.0
1.6
1.0
400
10
—
8.0
5.0
1000
ms
—
ms
200
kHz
Notes
61. -40 C TA125 C
62. 1.3%, including lifetime drift
63. Dependent on the external OSC
64. These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements
3.6.2.4
Reset characteristics
Table 43. Reset and stop characteristics(65)
Rating
Symbol
PWRSTL
nRST
Min.
Typ.
Max.
Unit
tVCORST
tVCORST
s
Reset Input Pulse Width, minimum input time
Startup from Reset
2.0
768
50
STOP Recovery Time
tSTP_REC
Notes
65. Conditions are shown in Table 10 unless otherwise noted
3.6.2.5
SPI timing
This section provides electrical parameters and ratings for the SPI. The measurement conditions are listed in Table 44.
Table 44. Measurement conditions
Description
Value
Full drive mode
50
Unit
—
Drive mode
(66)
Load capacitance CLOAD , on all outputs
pF
Notes
66. Conditions are shown in Table 10 unless otherwise noted
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3.6.2.5.1
Master mode
The timing diagram for master mode with transmission format CPHA = 0 is depicted in Figure 8.
SS
(Output)
2
1
12
12
13
13
3
SCK
(CPOL = 0)
4
(Output)
4
SCK
(CPOL = 1)
(Output)
5
6
MISO
(Input)
Bit MSB-1... 1
9
MSB IN2
10
MSB OUT2
LSB IN
11
MOSI
(Output)
Bit MSB-1... 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
Figure 8. SPI master timing (CPHA = 0)
The timing diagram for master mode with transmission format CPHA=1 is depicted in Figure 9.
SS
(Output)
1
12
12
13
13
3
2
SCK
(CPOL = 0)
(Output)
4
4
SCK
(CPOL = 1)
(Output)
5
6
MISO
(Input)
Bit MSB-1... 1
MSB IN2
LSB IN
11
9
MOSI
(Output)
Port Data
Bit MSB-1... 1
Master LSB OUT
Port Data
Master MSB OUT2
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure 9. SPI master timing (CPHA = 1)
The timing characteristics for master mode are listed in Table 45.
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Table 45. SPI master mode timing characteristics
Num
1
C
D
D
D
D
D
D
D
D
D
D
D
D
Characteristic
Symbol
fSCK
tSCK
tLEAD
tLAG
tWSCK
tSU
Min.
1/2048
2.0
—
Typ.
—
Max.
12
2048
—
Unit
fBUS
tBUS
tSCK
tSCK
tSCK
ns
SCK Frequency
SCK Period
1
—
2
Enable Lead Time
Enable Lag Time
1/2
1/2
1/2
—
3
—
—
4
Clock (SCK) High or Low Time
Data Setup Time (inputs)
Data Hold Time (inputs)
—
—
5
8.0
8.0
—
—
6
tHI
—
—
ns
9
Data Valid After SCK Edge
Data Valid After SS Fall (CPHA = 0)
Data Hold Time (outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
tVSCK
tVSS
tHO
—
29
ns
10
11
12
13
—
—
15
ns
20
—
—
ns
tRFI
—
—
8.0
8.0
ns
tRFO
—
—
ns
3.6.2.5.2
Slave mode
The timing diagram for slave mode with transmission format CPHA = 0 is depicted in Figure 10.
SS
(Input)
1
12
12
13
13
3
SCK
(CPOL = 0)
(Input)
4
4
2
SCK
(CPOL = 1)
10
7
(Input)
8
9
11
11
MISO
(Output)
See
See
Note
Bit MSB-1... 1
Slave LSB OUT
Slave MSB
6
Note
5
MOSI
(Input)
Bit MSB-1... 1
MSB IN
LSB IN
NOTE: Not defined
Figure 10. SPI slave timing (CPHA = 0)
The timing diagram for slave mode with transmission format CPHA = 1 is depicted in Figure 11.
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SS
(Input)
3
1
12
13
2
SCK
(CPOL = 0)
(Input)
4
4
12
11
13
SCK
(CPOL = 1)
(Input)
8
9
MISO
See
Bit MSB-1... 1
Slave MSB OUT
Slave LSB OUT
LSB IN
Note
(Output)
7
5
6
MOSI
(Input)
MSB IN
Bit MSB-1... 1
NOTE: Not defined
Figure 11. SPI slave timing (CPHA = 1)
The timing characteristics for slave mode are listed in Table 46.
Table 46. SPI slave mode timing characteristics
Num
1
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Characteristic
Symbol
fSCK
tSCK
tLEAD
tLAG
tWSCK
tSU
Min.
DC
4.0
4.0
4.0
4.0
8.0
8.0
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
14
Unit
fBUS
fBUS
fBUS
fBUS
fBUS
ns
SCK Frequency
SCK Period
1
2
Enable Lead Time
—
3
Enable Lag Time
—
4
Clock (SCK) High or Low Time
Data Setup Time (inputs)
Data Hold Time (inputs)
Slave Access Time (time to data active)
Slave MISO Disable Time
Data Valid After SCK Edge
Data Valid After SS Fall
Data Hold Time (outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
5
—
6
tHI
—
ns
7
tA
20
22
ns
8
tDIS
—
ns
(67)
(67)
9
tVSCK
tVSS
tHO
—
29 + 0.5 tBUS
ns
10
11
12
13
—
29 + 0.5 tBUS
ns
20
—
ns
tRFI
—
8.0
8.0
ns
tRFO
—
ns
Notes
67. 0.5 tBUS added due to internal synchronization delay
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3.7
Thermal protection characteristics
Characteristics noted under conditions 3.5 V VSUP28 V, -40 C TA125 C, unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Table 47. Thermal characteristics
Ratings
Symbol
Min
Typ
Max
Unit
VDDH/VDDA/VDDX High Temperature Warning (HTI)
T
Threshold
Hysteresis
HTI
110
125
10
140
°C
T
HTI_H
VDDH/VDDA/VDDX Overtemperature Shutdown
T
Threshold
Hysteresis
SD
155
150
165
10
180
180
°C
T
SD_H
TLINSD
LIN Overtemperature Shutdown
165
20
°C
°C
TLINSD_HYS
LIN Overtemperature Shutdown Hysteresis
3.8
Electromagnetic compatibility (EMC)
All ESD testing is in conformity with the CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device
qualification, ESD stresses are performed for the Human Body Model (HBM), Machine Model (MM), Charge Device Model (CDM), as well
as LIN transceiver specific specifications.
A device will be defined as a failure, if after exposure to ESD pulses, the device no longer meets the device specification. Complete DC
parametric and functional testing is performed per the applicable device specification at room temperature, followed by hot temperature,
unless specified otherwise in the device specification. The immunity against transients for the LIN, PTB3/L0, VSENSE, ISENSEH,
ISENSEL, and VSUP, is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification (ISO7637-2),
refer to the LIN Conformance Test Certification Report - available as separate document.
Table 48. Electromagnetic compatibility
Ratings
Symbol
Value/limit
Unit
ESD - Human Body Model (HBM) following AEC-Q100 / JESD22-A114
(C
= 100 pF, R
- LIN (all GNDs shorted)
- All other Pins
= 1500 )
ZAP
ZAP
VHBM
kV
±8.0
±2.0
ESD - Charged Device Model (CDM) following AEC-Q100
Corner Pins
All other Pins
VCDM
±750
±500
V
ESD - Machine Model (MM) following AEC-Q100 (C
= 200 pF, R
= 0 ), All Pins
VMM
ILAT
±200
±100
V
ZAP
ZAP
Latch-up current at TA = 125 C(68)
mA
ESD GUN - LIN Conformance Test Specification(69), unpowered, contact discharge. (C
=
ZAP
150 pF, R
= 330 ); LIN (no bus filter CBUS); VSENSE with serial RVSENSE; VSUP with
± 6000
± 6000
V
V
ZAP
CVSUP; PTB3 with serial RPTB3
ESD GUN - IEC 61000-4-2 Test Specification(70), unpowered, contact discharge. (C
=
ZAP
150 pF, R
= 330 ); LIN (no bus filter CBUS); VSENSE with serial RVSENSE; VSUP with
ZAP
CVSUP; PTB3 with serial RPTB3
ESD GUN - ISO10605(70), unpowered, contact discharge, C
= 150 pF,
ZAP
R
= 2.0 kLIN (no bus filter CBUS); VSENSE with serial RVSENSE; VSUP with CVSUP
;
± 8000
± 8000
V
V
ZAP
PTB3 with serial RPTB3
ESD GUN - ISO10605(70), powered, contact discharge, C
= 330 pF, R
= 2.0 kLIN (no
ZAP
ZAP
bus filter CBUS); VSENSE with serial RVSENSE; VSUP with CVSUP; PTB3 with serial RPTB3
Notes
68. Input Voltage Limit = -2.5 to 7.5 V
69. Certification available on request
70. Tested internally only, following the reference document test procedure.
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4
Functional description and application information
This chapter describes the MM912_637 dual die device functions on a block by block base. The following symbols are shown on all
module cover pages to distinguish between the module location being the MCU die or the analog die:
The documented module is physically located on the Analog die. This applies to Section 4.2, “MM912_637 - analog die
overview" through Section 4.15, “Die to die interface - target".
MCU
ANALOG
The documented module is physically located on the Microcontroller die. This applies to Section 4.2, “MM912_637 - analog
die overview" through Section 4.26, “MCU - die-to-die initiator (9S12I128PIMV1)".
Sections concerning both die or the complete device will not have a specific indication (e.g. Section 5, “MM912_637 - trimming").
4.1
Introduction
Many types of electronic control units (ECUs) are connected to and supplied from the main car battery in modern cars. Depending on the
cars mode of operation (drive, start, stop, standby), the battery must deliver different currents to the different ECUs. The vehicle power
management has several sub-functions, like control of the set-point value of the power generator, dynamic load management during drive,
start, stop, and standby mode.
The Application Specific Integrated Circuit (ASIC) allows for two application circuits, depending on whether the bias current of the
MM912_637 itself shall be included into the current measurement.
Battery Plus Pole
CBAT
RSENSE
Battery Minus Pole
ISENSEL
RSHUNT
LIN
LIN
ISENSEH
CLIN
Chassis Ground
Figure 12. Typical IBS application (device GND = chassis GND)
Battery Plus Pole
CBAT
RSENSE
Battery Minus Pole
ISENSEL
RSHUNT
LIN
LIN
ISENSEH
CLIN
Chassis Ground
Figure 13. Typical IBS application (device GND = battery minus)
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The vehicle power system needs actual measurement data from the battery, mainly voltage, current, and temperature. Out of these
measurement data, it needs calculated characteristics, such as dynamic internal battery resistance. Therefore, an intelligent battery
sensor (IBS) module is required.
To efficiently measure the battery voltage, current, and temperature, the IBS module is directly connected to and supplied from the battery.
It is located directly on the negative pole of the battery; the supply of the IBS module comes from 'KL30'. The battery current is measured
via a low-ohmic shunt resistor, connected between the negative pole of the battery and the chassis ground of the car. The battery voltage
is measured at 'KL30'.
The data communication between the IBS module and the higher level ECU is done via a LIN interface. The MM912_637 is able to
measure its junction temperature. That temperature is the basis for a model in software that calculates the battery temperature out of the
junction temperature. An optional external temperature sense input is provided as well.
4.1.1
Device register map
Table 49 shows the device register memory map overview.
Table 49. Device register memory map overview
Address
Module
Size (Bytes)
0x0000–0x0003
0x0004–0x0009
0x000A–0x000B
0x000C–0x000D
0x000E–0x000F
0x0010–0x0015
0x0016–0x0019
0x001A–0x001B
0x001C–0x001E
0x001F
PIM (port integration module)
Reserved
4
6
MMC (memory map control)
PIM (port integration module)
Reserved
2
2
2
MMC (memory map control)
Reserved
8
2
Device ID register
Reserved
2
4
INT (interrupt module)
DBG (debug module)
Reserved
1
0x0020–0x002F
0x0030–0x0033
0x0034–0x003F
0x0040–0x00D7
0x00D8–0x00DF
0x00E0–0x00E7
0x00E8–0x00EF
0x00F0–0x00FF
0x0100–0x0113
0x0114–0x011F
0x0120–0x017F
0x0180–0x01EF
0x01F0–0x01FC
0x01FD–0x01FF
0x0200-0x02FF
0x0300–0x03FF
16
4
CPMU (clock and power management)
Reserved
12
152
8
D2DI (die 2 die initiator)
Reserved
32
8
SPI (serial peripheral interface)
Reserved
32
20
12
96
112
13
3
FTMRC control registers
Reserved
PIM (port integration module)
Reserved
CPMU (clock and power management)
Reserved
D2DI (die 2 die initiator, blocking access window)
D2DI (die 2 die initiator, non-blocking write window)
256
256
MM912_637D1
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Data sheet: Technical data
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MM912_637
Intelligent integrated precision battery sensor
NOTE
The reserved register space shown in Table 49 is not allocated to any module. This register space is
reserved for future use. Writing to these locations has no effect. Read access to these locations
returns a zero.
4.1.2
Detailed module register map
Table 50 to Table 63 show the detailed module maps of the MM912_637.
Table 50. 0x0000–0x0009 port integration module (PIM) 1 of 3
Address
Name
Bit 7
PA7
0
Bit 6
PA6
0
Bit 5
PA5
0
Bit 4
PA4
0
Bit 3
PA3
0
Bit 2
PA2
0
Bit 1
Bit 0
R
0x0000
PTA
PA1
PA0
W
R
0x0001
0x0002
0x0003
PTE
DDRA
PE1
PE0
W
R
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
DDRA0
W
R
DDRE
DDRE1
0
DDRE0
0
W
R
0
0
0
0
0
0
0x0004-0x
0009
Reserved
W
Table 51. 0x000A–0x000B memory map control (MMC) 1 of 2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
0
0
0
0
0
0x000A
Reserved
W
R
0
0
0
0
0
0
0
0x000B
MODE
MODC
W
Table 52. 0x000C–0x000F port integration module (PIM) map 2 of 3
Address
Name
Bit 7
Bit 6
BKPUE
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PDPEE
0
Bit 0
R
0
0
0
0
0
0
0x000C
PUCR
W
R
0
0
0
0
0
0
0
0
0x000D
RDRIV
RDRD
0
RDRC
0
W
R
0
0
0x000E-0x
000F
Reserved
W
MM912_637D1
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MM912_637
Intelligent integrated precision battery sensor
Table 53. 0x0010–0x0019 memory map control (MMC) 2 of 2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
0
0
0
0
0
0x0010
Reserved
W
R
0x0011
DIRECT
Reserved
PPAGE
DP15
0
DP14
0
DP13
0
DP12
0
DP11
0
DP10
0
DP9
0
DP8
0
W
R
0x0012-0x
0014
W
R
0
0
0
0
0
0
0
0
0x0015
PIX3
0
PIX2
0
PIX1
0
PIX0
0
W
R
0x0016-0x
0019
Reserved
W
Table 54. 0x001A–0x001E miscellaneous peripheral
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
PARTIDH
0x001A
PARTIDH
W
R
PARTIDL
0x001B
PARTIDL
Reserved
W
R
0
0
0
0
0
0
0
0
0x001C-0x
001E
W
Table 55. 0x001F interrupt module (S12SINT)
R
0x001F
IVBR
IVB_ADDR[7:0]
W
Table 56. 0x0020–0x002F debug module (S12XDBG)
Address
Name
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
DBGBRK
0
Bit 2
Bit 1
Bit 0
R
0
0
0x0020
DBGC1
ARM
BDM
0
COMRV
W
R
TRIG
0
TBF(71)
0
0
SSF2
SSF1
0
SSF0
0x0021
0x0022
0x0023
0x0024
0x0025
DBGSR
DBGTCR
DBGC2
W
R
0
0
0
0
TSOURCE
0
TRCMOD
TALIGN
W
R
0
0
0
ABCM
W
R
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
DBGTBH
DBGTBL
W
R
W
MM912_637D1
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MM912_637
Intelligent integrated precision battery sensor
Table 56. 0x0020–0x002F debug module (S12XDBG) (continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
TBF(71)
0
CNT
0x0026
DBGCNT
W
R
0
0
0
0
0
0
0
0
0x0027
0x0027
DBGSCRX
DBGMFR
DBGACTL
DBGBCTL
DBGCCTL
DBGXAH
DBGXAM
DBGXAL
DBGADH
DBGADL
SC3
0
SC2
MC2
SC1
MC1
SC0
MC0
W
R
W
R
0x0028(72)
0x0028(73)
0x0028(74)
0x0029
SZE
SZ
TAG
TAG
BRK
BRK
RW
RW
RWE
RWE
NDB
0
COMPE
COMPE
COMPE
Bit 16
Bit 8
W
R
SZE
0
SZ
0
W
R
0
TAG
0
BRK
0
RW
0
RWE
0
W
R
0
0
Bit 17
W
R
0x002A
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
W
R
0x002B
Bit 0
W
R
0x002C
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 8
W
R
0x002D
Bit 0
W
R
0x002E
DBGADHM
DBGADLM
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
W
R
0x002F
Notes
W
71. This bit is visible at DBGCNT[7] and DBGSR[7]
72. This represents the contents if the Comparator A control register is blended into this address.
73. This represents the contents if the Comparator B control register is blended into this address.
74. This represents the contents if the Comparator C control register is blended into this address.
Table 57. 0x0034–0x003F Clock and Power Management (CPMU) 1 of 2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
CPMU
SYNR
0x0034
VCOFRQ[1:0]
SYNDIV[5:0]
W
R
0
0
CPMU
REFDIV
0x0035
REFFRQ[1:0]
REFDIV[3:0]
W
MM912_637D1
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MM912_637
Intelligent integrated precision battery sensor
Table 57. 0x0034–0x003F Clock and Power Management (CPMU) 1 of 2 (continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
CPMU
POSTDIV
0x0036
POSTDIV[4:0]
W
R
LOCK
0
UPOSC
0
0x0037
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
0x003E
0x003F
CPMUFLG
CPMUINT
CPMUCLKS
CPMUPLL
CPMURTI
CPMUCOP
Reserved
RTIF
RTIE
PORF
0
LVRF
0
LOCKIF
ILAF
0
OSCIF
OSCIE
W
R
LOCKIE
0
W
R
0
RTI
COP
PLLSEL
0
PSTP
0
PRE
0
PCE
0
OSCSEL
OSCSEL
W
R
0
0
FM1
FM0
W
R
RTDEC
RTR6
RTR5
RTR4
0
RTR3
0
RTR2
RTR1
RTR0
W
R
0
WCOP
0
RSBCK
0
CR2
0
CR1
0
CR0
0
W
R
WRTMASK
0
0
0
0
0
W
R
0
0
0
0
0
0
Reserved
W
R
0
0
6
0
5
0
4
0
3
0
2
0
1
0
CPMU
ARMCOP
W
Bit 7
Bit 0
Table 58. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) 1 of 3
Address
Name
Bit 7
Bit 6
D2DCW
0
Bit 5
D2DSWAI
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
0x00D8
D2DCTL0
D2DEN
D2DCLKDIV[1:0]
W
R
0
0x00D9
0x00DA
0x00DB
0x00DC
0x000D
0x00DE
D2DCTL1
D2DSTAT0
D2DSTAT1
D2DADRHI
D2DADRLO
D2DDATAHI
D2DIE
TIMOUT[3:0]
W
R
ACKERF
D2DBSY
SZ8
CNCLF
TIMEF
0
TERRF
PARF
PAR1
PAR0
ERRIF
D2DIF
W
R
0
0
0
0
0
0
0
0
0
0
W
R
RWB
NBLK
W
R
ADR[7:0]
W
R
DATA[15:8]
W
MM912_637D1
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MM912_637
Intelligent integrated precision battery sensor
Table 58. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) 1 of 3 (continued)
R
DATA[7:0]
0x00DF
D2DDATALO
W
Table 59. 0x00E8–0x00EF serial peripheral interface (SPI)
Address
Name
Bit 7
SPIE
0
Bit 6
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
R
0x00E8
SPICR1
SPE
MSTR
CPOL
SSOE
LSBFE
W
R
0x00E9
0x00EA
0x00EB
0x00EC
0x00ED
0x00EE
0x00EF
SPICR2
SPIBR
XFRW
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
R
0
SPPR2
0
SPPR1
SPTEF
SPPR0
MODF
SPR2
0
SPR1
0
SPR0
0
W
R
SPIF
0
SPISR
W
R
R15
T15
R7
T7
R14
T14
R6
T6
R13
T13
R5
T5
R12
T12
R4
T4
R11
T11
R3
T3
R10
T10
R2
T2
R9
T9
R1
T1
0
R8
T8
R0
T0
0
SPIDRH
SPIDRL
Reserved
Reserved
W
R
W
R
0
0
0
0
0
0
W
R
0
0
0
0
0
0
0
0
W
Table 60. 0x0100–0x0113 flash control & status register FTMRC
Address
Name
Bit 7
Bit 6
Bit 5
FDIV5
RNV5
Bit 4
FDIV4
RNV4
Bit 3
FDIV3
RNV3
Bit 2
FDIV2
RNV2
Bit 1
FDIV1
SEC1
Bit 0
FDIV0
SEC0
R
FDIVLD
0x0100
FCLKDIV
FDIVLCK
KEYEN0
W
R
KEYEN1
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
FSEC
FCCOBIX
Reserved
FCNFG
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCOBIX2
0
CCOBIX1
0
CCOBIX0
0
W
R
0
W
R
0
0
0
0
CCIE
0
IGNSF
0
FDFD
FSFD
W
R
FERCNFG
FSTAT
DFDIE
SFDIE
W
R
MGBUSY
RSVD
MGSTAT1
MGSTAT0
CCIF
ACCERR
FPVIOL
W
MM912_637D1
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MM912_637
Intelligent integrated precision battery sensor
Table 60. 0x0100–0x0113 flash control & status register FTMRC (continued)
R
0
0
RNV6
0
0
0
0
0
0x0107
0x0108
0x0109
0x010A
0x010B
FERSTAT
FPROT
DFDIF
FPLS1
DPS1
SFDIF
FPLS0
DPS0
W
R
FPOPEN
DPOPEN
CCOB15
FPHDIS
0
FPHS1
0
FPHS0
DPS3
FPLDIS
DPS2
W
R
DFPROT
FCCOBHI
FCCOBLO
Reserved
FOPT
W
R
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
W
R
CCOB7
0
CCOB6
0
CCOB5
0
CCOB4
0
CCOB3
0
CCOB2
0
CCOB1
0
CCOB0
0
W
R
0x010C-0x
010F
W
R
NV7
0
NV6
0
NV5
0
NV4
0
NV3
0
NV2
0
NV1
0
NV0
0
0x0110
W
R
0x0111-
0x0113
Reserved
W
Table 61. 0x0120 port integration module (PIM) 2 of 2
Address
Name
Bit 7
PTIA7
0
Bit 6
PTIA6
0
Bit 5
PTIA5
0
Bit 4
PTIA4
0
Bit 3
PTIA3
0
Bit 2
PTIA2
0
Bit 1
Bit 0
R
0x0120
PTIA
PTIA1
PTIA0
W
R
0x0121
PTIE
PTIE1
0
PTIE0
0
W
R
0
0
0
0
0
0
0x0122-
0x017F
Reserved
W
Table 62. 0x01F0–0x01FF clock and power management (CPMU) 2of 2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
0
0
0
0
0
0x01F0
Reserved
W
R
0
0
0
0
0
0
0
0
0
0
0
LVDS
CPMU
LVCTL
0x01F1
LVIE
0
LVIF
0
W
R
0
0
0x01F2-
0x01F7
Reserved
W
R
CPMU
IRCTRIMH
0x01F8
0x01F9
TCTRIM[3:0]
IRCTRIM[9:8]
W
R
CPMU
IRCTRIML
IRCTRIM[7:0]
W
MM912_637D1
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MM912_637
Intelligent integrated precision battery sensor
Table 62. 0x01F0–0x01FF clock and power management (CPMU) 2of 2 (continued)
OSCPINS_
R
EN
0x01FA
CPMUOSC
OSCE
0
OSCBW
0
OSCFILT[4:0]
0
W
R
0
0
0
0
0
0
0
0
0x01FB
0x01FC
CPMUPROT
Reserved
PROT
0
W
R
0
0
0
W
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3
Offset(75)
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
HTIEM
HTIE
HTF
UVIEM
UVIE
UVF
HWRM
0
0
PFM[1:0]
PF[1:0]
OPMM[1:0]
PCR_CTL
PCR Control Register
0x00
0
0
OPM[1:0]
W
R
HWR
HWRF
PCR_SR (hi)
WDRF
HVRF
LVRF
WULTCF
WLPMF
0x02
0x03
PCR Status Register
W
Write 1 will clear the flags
WUPTB3 WUPTB2 WUPTB1 WUPTB0
WUAHTH
F
PCR_SR (lo)
R
WUCTHF WUCALF WULINF
F
F
F
F
PCR Status Register
W
R
Write 1 will clear the flags
W
R
PCR_PRESC
PCR 1.0 ms prescaler
0x04
PRESC[15:0]
W
R
PCR_WUE (hi)
Wake-up Enable Register
PCR_WUE (lo)
0x06
0x07
WUAHTH WUCTH
WUCAL
0
WULIN
0
WUPTB3 WUPTB2 WUPTB1 WUPTB0
W
R
0
0
0
0
0
WULTC
Wake-up Enable Register
INT_SRC (hi)
W
R
TOV
CH3
CH2
CAL
0
CH1
LTC
0
CH0
CVMI
LTI
RX
HTI
TX
UVI
ERR
0x08
Interrupt source register
INT_SRC (lo)
W
R
0
0
0
0
0
0
0x09
Interrupt source register
INT_VECT
W
R
IRQ[3:0]
0x0A
Interrupt vector register
W
R
0
0
0
0
0
0
0x0B
Reserved
W
R
INT_MSK (hi)
Interrupt mask register
INT_MSK (lo)
0x0C
TOVM
0
CH3M
0
CH2M
CALM
CH1M
LTCM
CH0M
CVMM
LTIM
RXM
HTIM
TXM
UVIM
W
R
0x0D
ERRM
Interrupt mask register
W
MM912_637D1
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Data sheet: Technical data
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NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
4
11
3
10
9
1
8
0
7
6
5
2
TRIM_ALF (hi)
R
W
R
PRDF
0
0
APRESC[12:8]
0x0E
Trim for accurate 1.0 ms low freq
clock
TRIM_ALF (lo)
APRESC[7:0]
0x0F
0x10
Trim for accurate 1.0 ms low freq
clock
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
WDTOM[2:0]
WDTO[2:0]
WDOFF
WD_CTL
Watchdog control register
Reserved
0
W
R
WD_SR
0
0
WDWO
0
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
Watchdog status register
W
R
0
0
Reserved
W
R
WD_RR
WDR[7:0]
Watchdog rearm register
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
W
R
W
R
W
R
SCIBD (hi)
SCI Baud Rate Register
SCIBD (lo)
LBKDIE RXEDGIE
SBR12
SBR4
M
SBR11
SBR10
SBR2
ILT
SBR9
SBR1
PE
SBR8
SBR0
PT
W
R
SBR7
SBR6
0
SBR5
RSRC
SBR3
0
SCI Baud Rate Register
SCIC1
W
R
LOOPS
SCI Control Register 1
SCIC2
W
R
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
SCI Control Register 2
SCIS1
W
R
TDRE
RDRF
IDLE
OR
SCI Status Register 1
SCIS2
W
R
0
RAF
LBKDIF
R8
RXEDGIF
T8
RXINV
TXINV
RWUID
ORIE
BRK13
NEIE
LBKDE
FEIE
SCI Status Register 2
SCIC3
W
R
TXDIR
PEIE
SCI Control Register 3
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
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NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCID
SCI Data Register
TIOS
R
W
R
R7
R6
R5
R4
R3
R2
R1
R0
0x1F
T7
0
T6
0
T5
0
T4
0
T3
T2
T1
T0
0x20
IOS3
IOS2
IOS1
IOS0
Timer Input Capture/Output
Compare Select
W
CFORC
Timer Compare Force Register
OC3M
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
FOC3
FOC2
FOC1
FOC0
OC3M3
OC3D3
OC3M2
OC3D2
OC3M1
OC3D1
OC3M0
OC3D0
Output Compare 3 Mask Register
OC3D
W
R
Output Compare 3 Data Register
TCNT (hi)
W
R
Timer Count Register
TCNT (lo)
W
R
TCNT[15:0]
Timer Count Register
TSCR1
W
R
0
0
0
0
0
0
0
0
TEN
0
TFFCA
0
Timer System Control Register 1
TTOV
W
R
TOV3
OM1
TOV2
OL1
TOV1
OM0
TOV0
OL0
Timer Toggle Overflow Register
TCTL1
W
R
OM3
OL3
OM2
OL2
Timer Control Register 1
TCTL2
W
R
EDG3B
0
EDG3A
0
EDG2B
0
EDG2A
0
EDG1B
C3I
EDG1A
C2I
EDG0B
C1I
EDG0A
C0I
Timer Control Register 2
TIE
W
R
Timer Interrupt Enable Register
TSCR2
W
R
0
0
0
0
0
0
0
0
0
TOI
0
TCRE
PR2
PR1
PR0
Timer System Control Register 2
TFLG1
W
R
C3F
0
C2F
0
C1F
0
C0F
0
Main Timer Interrupt Flag 1
TFLG2
W
R
TOF
Main Timer Interrupt Flag 2
TC0 (hi)
W
R
0x2E
0x2F
Timer Input Capture/Output
Compare Register 0
W
R
TC0[15:0]
TC0 (lo)
Timer Input Capture/Output
Compare Register 0
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
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NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
TC1 (hi)
R
W
R
0x30
Timer Input Capture/Output
Compare Register 1
TC1[15:0]
TC2[15:0]
TC3[15:0]
TC1 (lo)
0x31
0x32
0x33
0x34
0x35
Timer Input Capture/Output
Compare Register 1
W
R
TC2 (hi)
Timer Input Capture/Output
Compare Register 2
W
R
TC2 (lo)
Timer Input Capture/Output
Compare Register 2
W
R
TC3 (hi)
Timer Input Capture/Output
Compare Register 3
W
R
TC3 (lo)
Timer Input Capture/Output
Compare Register 3
W
TIMTST
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x36
0x37
0x38
0x39
0x3A
0x3B
TCBYP
0
Timer Test Register
Reserved
W
R
LTC_CTL (hi)
Life Time Counter control register
LTC_CTL (lo)
0
0
0
0
0
0
W
R
LTCIEM
LTCEM
LTCIE
LTCE
0
Life Time Counter control register
LTC_SR
W
R
LTCOF
1 will clr
0
Life Time Counter status register
W
R
0
Reserved
W
R
W
R
LTC_CNT1
Life Time Counter Register
0x3C
0x3E
LTC[31:16]
LTC[15:0]
W
R
W
R
LTC_CNT0
Life Time Counter Register
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
45/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
DIR2M
DIR2
0
DIR1M
DIR1
0
DIR0M
DIR0
0
PE3M
PE2M
PE1M
PE0M
GPIO_CTL
GPIO control register
0x40
0
0
0
0
PE3
PE2
PE1
PE0
W
R
GPIO_PUC
GPIO pull up/down configuration
GPIO_DATA
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
PDE3
PD3
PUE2
PD2
PUE1
PD1
PUE0
PD0
W
R
0
0
0
GPIO port data register
GPIO_IN0
W
R
0
TCAP3
TCAP2
TCAP1
TCAP0
SCIRX
SCITX
SCIRX
SCITX
SCIRX
SCITX
LINTX
LINRX
LINTX
LINRX
LINTX
Port 0 input configuration
GPIO_OUT0
W
R
0
PTBX0
0
WKUP
0
TCOMP3 TCOMP2 TCOMP1 TCOMP0
Port 0 output configuration
GPIO_IN1
W
R
TCAP3
TCAP2
TCAP1
TCAP0
Port 1 input configuration
GPIO_OUT1
W
R
0
PTBX1
0
WKUP
0
TCOMP3 TCOMP2 TCOMP1 TCOMP0
Port 1 output configuration
GPIO_IN2
W
R
TCAP3
TCAP2
TCAP1
TCAP0
Port 2 input configuration
GPIO_OUT2
W
R
0
PTBX2
0
WKUP
TCOMP3 TCOMP2 TCOMP1 TCOMP0
LINRX
0
Port 2 output configuration
GPIO_IN3
W
R
PTWU
0
PTWU
0
TCAP3
0
TCAP2
0
TCAP1
0
TCAP0
0
Port 3 input configuration
W
R
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
0
0
0
0
W
R
OTIEM
TXDM
LVSDM
ENM
SRSM[1:0]
LIN_CTL
LIN control register
0x50
OTIE
TXD
LVSD
EN
SRS[1:0]
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
46/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LIN_SR (hi)
LIN status register
LIN_SR (lo)
R
W
R
OT
0
HF
0
UV
0
0
0
0x52
Write 1 will clear the flags
RDY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RX
TX
0x53
0x54
0x55
0x56
0x57
LIN status register
LIN_TX
W
R
0
0
0
0
FROMPT
B
FROMSCI
LIN transmit line definition
LIN_RX
W
R
TOPTB
0
TOSCI
0
LIN receive line definition
W
R
Reserved
Reserved
W
R
0
0
W
R
0
0
0
0
W
R
AHCRM
0
OPTEM
OPENEM CVMIEM ETMENM ITMENM
VMENM
CMENM
ACQ_CTL
Acquisition control register
0x58
OPTE
PGAG
OPENE
VMOW
CVMIE
CMOW
ETMEN
ETM
ITMEN
ITM
VMEN
VM
CMEN
CM
W
R
AHCR
AVRF
ACQ_SR (hi)
Acquisition status register
ACQ_SR (lo)
0x5A
0x5B
W
R
Write 1 will clear the flags
OPEN
0
0
0
0
0
VTH
0
ETCHOP
ITCHOP
VCHOP
CCHOP
Acquisition status register
W
R
0
0
0
0
ETCHOP
M
CVCHOP
M
W
TCOMPM VCOMPM CCOMPM LPFENM
ITCHOPM
AGENM
ACQ_ACC1
Acquisition chain control 1
0x5C
0x5E
R
W
R
TCOMP
VCOMP
CCOMP
0
LPFEN
0
ETCHOP
0
ITCHOP CVCHOP
AGEN
0
0
0
0
0
W
R
ZEROM
ECAPM
TADCGM VADCGM CADCGM
TDENM
VDENM
CDENM
ACQ_ACC0
Acquisition chain control 0
ZERO
0
ECAP
0
TADCG
0
VADCG
0
CADCG
0
TDEN
VDEN
CDEN
W
R
ACQ_DEC
Decimation rate
ACQ_BGC
0x60
0x61
0x62
0x63
DEC[2:0]
BG2EN
W
R
0
0
0
0
BG3EN
BG1EN
BGADC[1:0]
BGLDO
0
BandGap control
ACQ_GAIN
W
R
0
0
IGAIN[2:0]
PGA gain
W
R
ACQ_GCB
D[7:0]
GCB threshold
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
47/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
ACQ_ITEMP (hi)
R
W
R
ITEMP[15:8]
0x64
Internal temperature
measurement
ACQ_ITEMP (lo)
ITEMP[7:0]
EEMP[15:8]
EEMP[7:0]
0x65
0x66
0x67
Internal temperature
measurement
W
R
ACQ_ETEMP (hi)
External temperature
measurement
W
R
ACQ_ETEMP (lo)
External temperature
measurement
W
R
W
R
0
0
0
0
0
0
0
0
0x68
0x69
Reserved
ACQ_CURR1
CURR[23:16]
CURR[15:8]
CURR[7:0]
VOLT[15:8]
VOLT[7:0]
0
Current measurement
W
R
W
R
ACQ_CURR0
Current measurement
0x6A
0x6C
W
R
W
R
ACQ_VOLT
Voltage measurement
W
R
ACQ_LPFC
0
0
0
0
0
0
0x6E
0x6F
LPFC[3:0]
Low pass filter coefficient number
W
R
0
0
0
0
0
Reserved
W
R
ACQ_TCMP
Low power trigger current
measurement period
W
R
0x70
0x72
TCMP[15:0]
W
R
ACQ_THF
THF[7:0]
Low power current threshold
filtering period
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x73
0x74
Reserved
ACQ_CVCR (hi)
0
0
I and V chopper control register
W
DBTM[1:0]
IIRCM[2:0]
PGAFM
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
48/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
5
12
4
11
3
10
2
9
1
8
0
7
6
ACQ_CVCR (lo)
I and V chopper control register
ACQ_CTH
R
W
R
0
0
0x75
DBT[1:0]
IIRC[2:0]
PGAF
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
CTH[7:0]
Low power current threshold
W
R
0
0
0
0
0
0
0
0
0
Reserved
W
R
ACQ_AHTH1 (hi)
Low power Ah counter threshold
ACQ_AHTH1 (lo)
W
R
AHTH[30:16]
AHTH[15:0]
Low power Ah counter threshold
ACQ_AHTH0 (hi)
W
R
Low power Ah counter threshold
ACQ_AHTH0 (lo)
W
R
Low power Ah counter threshold
ACQ_AHC1 (hi)
W
R
AHC[31:24]
AHC[23:16]
AHC[15:8]
AHC[7:0]
Low power Ah counter
ACQ_AHC1 (lo)
W
R
Low power Ah counter
ACQ_AHC0 (hi)
W
R
Low power Ah counter
ACQ_AHC0 (lo)
W
R
Low power Ah counter
LPF_A0 (hi)
W
R
A0 filter coefficient
LPF_A0 (lo)
W
R
A0[15:0]
A1[15:0]
A2[15:0]
A0 filter coefficient
LPF_A1 (hi)
W
R
A1 filter coefficient
LPF_A1 (lo)
W
R
A1 filter coefficient
LPF_A2 (hi)
W
R
A2 filter coefficient
LPF_A2 (lo)
W
R
A2 filter coefficient
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
49/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
LPF_A3 (hi)
A3 filter coefficient
LPF_A3 (lo)
R
W
R
0x86
A3[15:0]
A4[15:0]
A5[15:0]
A6[15:0]
A7[15:0]
A8[15:0]
A9[15:0]
A10[15:0]
A11[15:0]
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
A3 filter coefficient
LPF_A4 (hi)
W
R
A4 filter coefficient
LPF_A4 (lo)
W
R
A4 filter coefficient
LPF_A5 (hi)
W
R
A5 filter coefficient
LPF_A5 (lo)
W
R
A5 filter coefficient
LPF_A6 (hi)
W
R
A6 filter coefficient
LPF_A6 (lo)
W
R
A6 filter coefficient
LPF_A7 (hi)
W
R
A7 filter coefficient
LPF_A7 (lo)
W
R
A7 filter coefficient
LPF_A8 (hi)
W
R
A8 filter coefficient
LPF_A8 (lo)
W
R
A8 filter coefficient
LPF_A9 (hi)
W
R
A9 filter coefficient
LPF_A9 (lo)
W
R
A9 filter coefficient
LPF_A10 (hi)
W
R
A10 filter coefficient
LPF_A10 (lo)
W
R
A10 filter coefficient
LPF_A11 (hi)
W
R
A11 filter coefficient
LPF_A11 (lo)
W
R
A11 filter coefficient
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
50/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
LPF_A12 (hi)
A12 filter coefficient
LPF_A12 (lo)
R
W
R
0x98
A12[15:0]
A13[15:0]
A14[15:0]
A15[15:0]
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
A12 filter coefficient
LPF_A13 (hi)
W
R
A13 filter coefficient
LPF_A13 (lo)
W
R
A13 filter coefficient
LPF_A14 (hi)
W
R
A14 filter coefficient
LPF_A14 (lo)
W
R
A14 filter coefficient
LPF_A15 (hi)
W
R
A15 filter coefficient
LPF_A15 (lo)
W
R
A15 filter coefficient
W
R
0
0
0
0
0
0
0
W
R
BGCALM[1:0]
PGAZM
PGAOM
DIAGVM
DIAGIM
CALIEM
CALIE
COMP_CTL
Compensation control register
0xA0
BGCAL[1:0]
PGAZ
0
PGAO
DIAGV
0
DIAGI
0
W
R
COMP_SR
Compensation status register
COMP_TF
0
0
BGRF
PGAOF
0
CALF
0xA2
0xA3
W
R
Write 1 will clear the flags
0
0
0
0
TMF[2:0]
Temperature filtering period
W
R
W
R
COMP_TMAX
Max temp before recalibration
0xA4
0xA6
TCMAX[15:0]
TCMIN[15:0]
W
R
W
R
COMP_TMIN
Min temp before recalibration
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xA8
0xA9
Reserved
Reserved
W
R
W
MM912_637D1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Data sheet: Technical data
Rev. 6.0 — 6/2021
51/396
NXP Semiconductors
MM912_637
Intelligent integrated precision battery sensor
Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
COMP_VO
Offset voltage compensation
COMP_IO
R
W
R
0xAA
VOC[7:0]
COC[7:0]
0xAB
0xAC
Offset current compensation
W
R
0
0
0
0
0
0
VSGC[9:8]
COMP_VSG
Gain voltage compensation
vsense channel
W
R
VSGC[7:0]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xAE
0xAF
Reserved
Reserved
W
R
W
R
IGC4[9:8]
IGC8[9:8]
IGC16[9:8]
IGC32[9:8]
IGC64[9:8]
W
R
COMP_IG4
Gain current compensation 4
0xB0
0xB2
0xB4
0xB6
0xB8
IGC4[7:0]
IGC8[7:0]
IGC16[7:0]
IGC32[7:0]
IGC64[7:0]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
COMP_IG8
Gain current compensation 8
W
R
W
R
COMP_IG16
Gain current compensation 16
W
R
W
R
COMP_IG32
Gain current compensation 32
W
R
W
R
COMP_IG64
Gain current compensation 64
W
R
IGC128[9:8]
W
R
COMP_IG128
Gain current compensation 128
0xBA
IGC128[7:0]
W
MM912_637D1
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
9
1
8
0
7
6
5
4
3
2
R
W
R
0
0
0
0
0
0
IGC256[9:8]
COMP_IG256
Gain current compensation 256
0xBC
IGC256[7:0]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IGC512[9:8]
W
R
COMP_IG512
Gain current compensation 512
0xBE
0xC0
0xC2
0xC4
0xC6
0xC8
0xCA
IGC512[7:0]
W
R
0
PGAOC4[10:8]
W
R
COMP_PGAO4
Offset PGA compensation 4
PGAOC4[7:0]
W
R
0
0
PGAOC8[10:8]
PGAOC16[10:8]
PGAOC32[10:8]
PGAOC64[10:8]
PGAOC128[10:8]
PGAOC256[10:8]
W
R
COMP_PGAO8
Offset PGA compensation 8
PGAOC8[7:0]
W
R
0
0
W
R
COMP_PGAO16
Offset PGA compensation 16
PGAOC16[7:0]
W
R
0
0
W
R
COMP_PGAO32
Offset PGA compensation 32
PGAOC32[7:0]
W
R
0
0
W
R
COMP_PGAO64
Offset PGA compensation 64
PGAOC64[7:0]
W
R
0
0
W
R
COMP_PGAO128
Offset PGA compensation 128
PGAOC128[7:0]
W
R
0
0
W
R
COMP_PGAO256
Offset PGA compensation 256
0xCC
PGAOC256[7:0]
W
MM912_637D1
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
2
9
1
8
0
7
6
5
4
3
R
W
R
0
0
0
0
0
PGAOC512[10:8]
COMP_PGAO512
Offset PGA compensation 512
0xCE
PGAOC512[7:0]
ITOC[7:0]
W
R
COMP_ITO
0xD0
0xD1
0xD2
Internal temp. offset
compensation
W
COMP_ITG
Internal temp. gain compensation
COMP_ETO
R
W
R
ITGC[7:0]
ETOC[7:0]
External temp. offset
compensation
W
R
COMP_ETG
0xD3
ETGC[7:0]
External temp. gain
compensation
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
MM912_637D1
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0xDF
Reserved
TRIM_BG0 (hi)
Trim bandgap 0
TRIM_BG0 (lo)
Trim bandgap 0
TRIM_BG1 (hi)
Trim bandgap 1
TRIM_BG1 (lo)
Trim bandgap 1
TRIM_BG2 (hi)
Trim bandgap 2
TRIM_BG2 (lo)
Trim bandgap 2
TRIM_LIN
0
0
0
0
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
TCIBG2[2:0]
IBG2[2:0]
TCIBG1[2:0]
IBG1[2:0]
W
R
W
R
UBG3
0
DBG3
0
TCBG2[2:0]
0
TCBG1[2:0]
SLPBG[2:0]
W
R
0
0
W
R
V1P2BG2[3:0]
V2P5BG2[3:0]
V1P2BG1[3:0]
V2P5BG1[3:0]
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LIN
Trim LIN
W
R
TRIM_LVT
LVT
Trim low voltage threshold
TRIM_OSC (hi)
Trim LP oscillator
TRIM_OSC (lo)
Trim LP oscillator
W
R
W
R
LPOSC[12:0]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
R
W
R
W
R
W
R
W
R
W
R
W
MM912_637D1
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Table 63. Analog die registers - 0x0200–0x02FF D2D blocking access (D2DI) 2 of 3/0x0300–0x03FF D2D non blocking access
(D2DI) 3 of 3 (continued)
Offset(75)
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0xF1
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
0xFF
W
Notes
75. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
4.2
MM912_637 - analog die overview
Introduction
4.2.1
MM912_637D1
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The MM912_637 analog die implements all system base functionality to operate the integrated microcontroller, and delivers application
specific input capturing.
Analog
VSUP
Watchdog
VDDA
GPIO
Oscillator
Timer
Bias
SCI
Regulator(s)
Digital
GNDA
MMC
LIN
LIN
LGND
D2DCLK
D2DINT
MCU
Die
D2D
Interface
Wake Up /
Power Down
Fuse
Box
VFUSE
GNDSUB
ADCGND
Gain and offset compensation
Prog. Low pass filter
Gain and offset
compensation
Interrupt
Control
DECV
DECC
RESET_A
Test
Interface
TCLK
Battery Voltage Battery Current
Measurement Measurement
Temperature
Measurement
TSUP
TEST_A
Figure 14. Analog die block overview
The following chapters describe the analog die functionality on a module by module basis.
4.2.2
Analog die options
NOTE
This document describes the features and functions of Analog Option 2 (all modules available and
tested). Beyond this chapter, there will be no additional note or differentiation between the different
implementations.
The following section describes the differences between analog die options 1 and 2.
Table 64. Analog options
Feature
Analog option 1
Analog option 2
Cranking Mode
Not Characterized or Tested
Fully Characterized and Tested
External Wake-up (PTB3/L0)
No
No
No
Yes
Yes
Yes
External Temperature Sensor Option (VTEMP)
Optional 2nd External Voltage Sense Input (VOPT)
4.2.2.1
Cranking mode
For devices with Analog Option 1 (Cranking mode not characterized), the following considerations are to be made:
4.2.2.1.1
Data sheet considerations
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In Analog Option 1 devices, Operation in Cranking mode is neither characterized not tested. All data sheet parameters and descriptions
relating to Cranking mode operation apply to Analog Option 2 devices only.
4.2.2.2
External wake-up (PTB3/L0)
For devices with Analog Option 1 (External Wake-up not available), the following considerations are to be made:
4.2.2.2.1
Register considerations
Table 65. Wake-up enable register (PCR_WUE (hi))
Offset (76) 0x06
Access: User read/write
1 0
7
WUAHTH
0
6
WUCTH
0
5
WUCAL
0
4
WULIN
0
3
WUPTB3
0
2
WUPTB2
0
R
W
WUPTB1
0
WUPTB0
0
Reset
Notes
76. Offset related to 0x0200 for blocking access and 0x300 for non-blocking access within the global address space.
For Analog Option 1 devices, WUPTB3 must be set to 0 (wake-up on a GPIO 3 event disabled).
4.2.2.3
External temperature sensor option (VTEMP)
For devices with Analog Option 1 (External Temperature Sensor Option not available), the following considerations are to be made:
4.2.2.3.1
Pinout considerations
Pin
Pin name for option 2
VTEMP
Pin name for option 1
Comment
28
29
NC
NC
NC pin should be connected to GND
Pin should be left unconnected
TSUP
4.2.2.3.2
Register considerations
Table 66. Acquisition control register (ACQ_CTL)
Offset (77) (78)
0x58
,
Access: User read/write
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
R
W
AHCRM
0
OPTEM
0
OPENEM
0
CVMIEM
0
ETMENM
0
ITMENM
0
VMENM
0
CMENM
0
Reset
7
0
6
OPTE
0
5
OPENE
0
4
CVMIE
0
3
ETMEN
0
2
ITMEN
0
1
VMEN
0
0
CMEN
0
R
W
AHCR
0
Reset
Notes
77. Offset related to 0x0200 for blocking access and 0x300 for non-blocking access within the global address space.
78. This register is 16-bit access only.
For Analog Option 1 devices, ETMEN must be set to 0 (external temperature measurement disabled).
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4.2.2.4
Optional 2nd external voltage sense input (VOPT)
For devices with Analog Option 1 (Optional 2nd External Voltage Sense Input not available), the following considerations are to be made:
4.2.2.4.1
Pinout considerations
Pin
28
Pin name for option 2
Pin name for option 1
Comment
VOPT
NC
NC pin should be connected to GND
4.2.2.4.2
Register considerations
Table 67. Acquisition control register (ACQ_CTL)
Offset (79) (80)
0x58
,
Access: User read/write
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
R
W
AHCRM
0
OPTEM
0
OPENEM
0
CVMIEM
0
ETMENM
0
ITMENM
0
VMENM
0
CMENM
0
Reset
7
0
6
OPTE
0
5
OPENE
0
4
CVMIE
0
3
ETMEN
0
2
ITMEN
0
1
VMEN
0
0
CMEN
0
R
W
AHCR
0
Reset
Notes
79. Offset related to 0x0200 for blocking access and 0x300 for non-blocking access within the global address space.
80. This register is 16-bit access only.
For Analog Option 1 devices, OPTE must be set to 0 (VSENSE routed to ADC).
4.3
Analog die - power, clock and resets - PCR
Introduction
4.3.1
The following chapter describes the MM912_637’s system base functionality primary location on the analog die. The chapter is divided in
the following sections:
1. 4.3.2, “Device operating modes"
2. 4.3.3, “Power management"
3. 4.3.4, “Wake-up sources"
4. 4.3.5, “Device clock tree"
5. 4.3.6, “System resets"
6. 4.3.7, “PCR - memory map and registers"
4.3.2
Device operating modes
The MM912_637 features three main operation modes: normal operation, stop mode, and sleep mode. The full signal conditioning and
measurements are permanently running in normal operation mode. The total current consumption of the MM912_637 is reduced in the
two low power modes.
The analog die of the MM912_637 is still partially active and able to monitor the battery current, temperature, activities on the LIN interface
and L0 terminal, during both low power modes.
4.3.2.1
Operating mode overview
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•
Normal Mode
—
—
—
—
All device modules active
Microcontroller fully supplied
D2DCLK active analog die clock source
Window watchdog clocked by the low power oscillator (LPCLK) to operate on independent clock
•
Stop Mode
—
—
—
—
—
MCU in low power mode, MCU regulator supply (VDDX) with reduced current capability
D2D interface supply disabled (VDDH=OFF)
Unused analog blocks disabled
Watchdogs = OFF
LIN wake-up, calibration request wake-up, cyclic wake-up, external wake-up, current threshold wake-up, and lifetime
counter wake-up optional
—
Current Measurement / current averaging and temperature measurement optional
•
•
Sleep Mode
—
—
—
—
MCU powered down (VDDH and VDDX = OFF)
Unused Analog Blocks disabled
Watchdogs = OFF
LIN wake-up, calibration request wake-up, cyclic wake-up, external wake-up, current threshold wake-up, and lifetime
counter wake-up optional
—
Current measurement / current averaging and temperature measurement optional
Intermediate Mode
—
Every transition from Stop or Sleep into Normal mode will go through an intermediate mode where the analog die clock is
not yet switched to the D2D clock. If required, the MM912_637 analog die can be put back to low power mode without
changing the frequency domain.
•
•
•
Reset Mode
—
Every reset source within the analog die will bring the system into a Reset state
Power On Reset Mode
—
For both low voltage thresholds are defined to indicate a loss of internal state.
Cranking Mode(81)
Special Mode implemented to guarantee the RAM content being valid though very low power conditions.
—
Notes
81. Not available on all device derivatives
4.3.2.2
Operating mode transitions
The device operating modes are controlled by the microcontroller, as well as external and internal wake-up sources. Figure 15 shows the
basic principal.
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POR
ANALOG: VDDL > VPORH
MCU: VDDRX>VPORD
ANALOG: VDDL < VPORL
MCU: VDDRX<VPORA
ANALOG: VDDL < VPORL
MCU: VDDRX<VPORA
RESET
Cranking
Event
Cranking Mode1
Reset Event
gone
Reset Event
Cranking
RESET
Event
RESET
Event
Cranking Event
gone
Event
MCU
Intermediate
Mode
Cranking
Event
Intermediate
Mode
Intermediate
Mode
Wake-up
Event
(MCU
Normal Mode
Wake-up
Event
MCU IRQ
MCU
Power On)
MCU
MCU
MCU
Stop Mode
Sleep Mode
1) Cranking Mode not available on all device derivatives
Figure 15. Modes of operation - transitions
4.3.2.3
Power on reset - POR
During system startup, or in any other case when MCU_VDD drops below VPORA (MCU), or VDDL drops below VPORL (analog die), a
Power On Reset (POR) condition is reached. The MCU (PORF) / analog die (LVRF) will indicate this state, setting the corresponding
power on reset flag. The primary consequence of entering POR is that the RAM or analog register content can no longer be guaranteed.
4.3.2.4
RESET - mode
If any of the analog die reset conditions are present, the MM912_637 analog die will enter Reset mode. During that mode, the analog die
will issue the RESET_A pin to be pulled down to reset the microcontroller die. Entering Reset mode will reset the analog die registers to
their default values.
The cause of the last reset is flagged in the PCR status register (PCR_SR (hi)).
4.3.2.5
Normal mode
During Normal mode operation, all modules are operating and the microcontroller is fully supplied.
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(82)
4.3.2.6
Cranking mode
A specific power down behavior has been implemented to allow the MCU memory (RAM) content to be guaranteed during very low supply
voltage conditions. The difference between the device behavior, with or without the cranking mode feature enabled, is described in Section
4.3.3.3, “Power up/power down behavior".
Notes
82. Not available on all device derivatives
4.3.2.7
Intermediate mode
As the channel acquisition and the timer modules are switched to the LPCLK, while the MM912_637 is operating in one of the two low
power modes, the Intermediate mode has been implemented, to be able to go back to low power mode without the transition into the D2D
Clock domain.
NOTE
The flag indicating the last wake-up source must be cleared before re-entering low power mode!
Once awakened, the MCU instructs the analog die to transit to Normal mode by writing “00” to the OPM bits in the PCR Control Register.
See Figure 16 for details.
STOP MODE
SLEEP MODE
VDDH = OFF
VDDH & VDDX = OFF
VDDX = Limited
TIM / AQ = LPCLK
TIM / AQ = LPCLK
MCU = OFF
MCU = STOP
Wake-up
Event
Wake-up
Event
INTERMEDIATE MODE
1. VDDH = ON
INTERMEDIATE MODE
1. VDDH & VDDX = ON
2. MCU => Power On
“01”
“10”
2. VDDX = Full
3. MCU => IRQ
(83)
MCU can access D2D
TIM / AQ are still on LPCLK domain
(e.g. check Wake-up source)
Write OPM[1:0] Bits in the PCR Control Register
“00”
NORMAL MODE
TIM / AQ = based on D2D Clock
Notes
83. As the Life Time Counter has to be configured into normal mode (no access to LTC_CNT[1..0] is
possible during intermediate mode), if not reconfigured it will continue to increment starting from 0.
Figure 16. Low power mode to normal mode transition through the intermediate mode
4.3.2.8
Low-power modes
In low power mode, the MM912_637 is still active to monitor the battery current (triggered current measurement for current threshold
detection and current accumulator function), and activities on the LIN interface and wake-up inputs. A cyclic wake-up using timer module
is implemented for timed wake-up. Temperature measurements are optional to detect an out of calibration condition.
The Life Time counter is also incremented during Low Power mode, to issue a Wake-up on overflow. See Section 4.14, “Life time counter
(LTC)" for additional details.
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The average current consumption is reduced, and based on the actual low power mode, the active modules, and the wake-up timing.
NOTE
To avoid any lock condition, no analog die interrupt should be enabled or pending when entering
LPM. To accomplish that condition, the analog die interrupts should be masked and served before
writing the PCR_CTL register.
The MCU interrupts should be enabled right before the STOP command, to avoid any interrupt to be
handled in between.
A wake-up from any of the low power modes will reset the window watchdog equal to a standard
reset.
4.3.2.8.1
Sleep mode
Writing the PCR Control Register (PCR_CTL) with OPM=10, the MM912_637 will enter Sleep mode with the configured wake-up sources
(see Section 4.3.4, “Wake-up sources").
NOTE
The power supply to the MCU will be turned off during Sleep mode. To safely approach this condition,
the MCU should be put into a safe state (e.g STOP).
During Sleep mode, the only active voltage regulator is VDDL, supplying the low power oscillator (LPOSC), and the permanently supplied
digital blocks.
When an enabled wake-up condition occurs, the shutdown voltage regulators are re-enabled, and once their outputs are above reset
threshold, the RESET_A signal is released, and the microcontroller will start its normal operation. The wake-up source is flagged in the
PCR Status Register (PCR_SR (hi)).
The microcontroller has to move from intermediate mode to Normal mode, by writing the OPM=00, to allow a controlled transition into the
D2D Clock domain.
4.3.2.8.2
Stop mode
Writing the PCR Control Register (PCR_CTL) with OPM=01, the MM912_637 analog die will enter Stop mode with the configured wake-up
sources (see Section 4.3.4, “Wake-up sources"), after the D2DCLK signal has been stopped by the MCU die entering Stop.
NOTE
After writing the PCR Control Register (PCR_CTL) with OPM=01, the register content of the SCI
(S08SCIV4) and TIMER (TIM16B4C) module registers are read only until Normal mode is entered
again. This is important in case the MCU does not effectively enter STOP, due to an IRQ pending
from one of the two blocks. (Having any analog die IRQ allowed when entering Low Power mode is
not recommended).
During Stop mode, the MM912_637 has the same behavior as during Sleep mode, except VDDX is still powered by the internal Clamp_5v,
to supply the MCU STOP mode current. As this current is limited, the MCU die must be switched into STOP mode after sending the Stop
command for the analog die.
If any enabled wake up condition occurs, the shutdown voltage regulators are re-enabled, and once their outputs are above the reset
threshold, VDDX is switched to the main regulator, an D2D interrupt (D2DINT) is issued to wake-up the MCU, and the microcontroller will
continue its normal operation. The wake-up source is flagged in the PCR Status Register (PCR_SR (hi)).
The microcontroller has to acknowledge the Normal mode by writing the OPM=00. This allows a controlled transition into the D2D Clock
domain. If the clock domain transition is not required, the microcontroller may issue a sleep / stop mode entry instead (see Section 4.3.5,
“Device clock tree" for details on the limitations during the intermediate state).
At start up or after wake-up, it is required to wait to ensure the PLL is locked, if the PLL is enabled previous to accessing the analog die
through the D2D interface.
NOTE
After writing the PCR Control Register (PCR_CTL) with OPM=01, writing OPM=00 (Normal mode) is
allowed to wake-up the analog die. The reduced current capability of the MCU regulator supply
(VDDX) has to be considered.
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4.3.3
Power management
To support the various operating modes and modules in the MM912_637, the following power management architecture has been
implemented.
POR
VPORH / VPORL
VDDL
VDDL
Flash
LVRA
VLVRAH / VLVRAL
Clamp5v
VDDF
VDDA
VDDX
VDDA
VDDX
LVR
VLVRA / VLVRD
VDDRX
D2D
LVI
VLVIA / VLVID
VSUP
LVRX
VLVRXH / VLVRXL
VDD
UVI
VUVIH / VUVIL
VDDH
VDDH
POR
VPORA / VPORD
VDDD2D
LVRH
VLVRHH / VLVRHL
Core
MCU
Analog Die
Figure 17. System voltage monitoring
4.3.3.1
Detailed power block description
See recommended external components under Section 2.2, “Recommended external components"”.
4.3.3.1.1
VSUP
VSUP is the system power supply input, and must be reverse battery protected by an external diode. VSUP is monitored for undervoltage
conditions (UVI). Once VSUP drops below V
an undervoltage interrupt (LVI) is issued.
UVIL
NOTE
If the device has the cranking mode feature enabled, the undervoltage threshold would be V
UVCIL
instead of V
.
UVIL
4.3.3.1.2
VDDL
VDDL is the low power 2.5 V digital supply voltage, supplying the permanently active blocks. It is based on the internal Clamp5v voltage
and always on. It is available externally, but must not be connected to any load.
4.3.3.1.3
VDDX
VDDX is the Normal mode 5.0 V regulator output, suppling the LIN block and the microcontroller via the VDDX pin. During STOP and
SLEEP mode operation, the VDDX regulator is shut down (Clamp5v does supply the MCU during STOP mode).
4.3.3.1.4
VDDH
VDDH is the Normal mode 2.5 V regulator output, suppling only active blocks during Normal mode and the MCU Die to Die Interface, via
the VDDH terminal. The VDDH regulator is shut down during both low power modes.
4.3.3.1.5
VDDA
VDDA is the 2.5 V analog supply voltage, active during Normal mode and I/T acquisitions. No external load must be connected to the
VDDA terminal.
4.3.3.2
Power supply by module
The following table summarized the active regulators vs. module for the different operating modes.
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Table 68. Power supply by module
Module/block
VDDH
VDDA
VDDL
VDDX
(84)
Gain Control Block (GCB)
X
X
X
X
X
X
(85)
Programmable Gain Amplifier (PGA)
(85)
I/T - ADC Converters
(84)
V - ADC Converters
(85)
Temperature Sensor
(84)
LIN
X
X
(84)
D2D
X
X
(86)
LPOSC
X
X
(86)
Permanent Digital
(84)
Normal Mode Digital
Notes
84. Enabled in Normal Mode only
85. Enabled when a measuring in Low Power mode and always in Normal mode
86. Permanently enabled
4.3.3.3
Power up/power down behavior
Several system voltage monitors have been implemented in both die, to guarantee a defined power up and power down system behavior.
See Figure 17 for the various sensing points. The individual threshold levels are specified in Table 16 for the analog die, and Table 25 for
the microcontroller.
NOTE
To differentiate between the MCU and analog die thresholds, the following symbol scheme is defined:
V
V
V
V
- MCU Assert Level (lower threshold for low voltage events)
xxxxA
xxxxD
xxxxH
xxxxL
- MCU Deassert Level (higher threshold for low voltage events)
- Analog Die High Threshold Level (deassert threshold for low voltage events)
- Analog Die Low Threshold Level (assert threshold for low voltage events)
4.3.3.4
Low-voltage operation - cranking mode device option
Based on the device option (“Cranking” or “Non-cranking”), the MM912_637 will behave different during “Loss of Power” conditions. The
“Cranking” option is an option, allowing lower voltage operations to guarantee the MCU memory content during a standard cranking
situation.
As illustrated in Figure 18, the cranking mode is introduced to maintain both die in a STOP mode alike state. The MCU die will remain in
STOP with the RAM content being guaranteed until the PORA level is reached for the VDDRX supply.
The analog die will enter “Cranking Mode” upon the MCU command out of Normal Mode, or when it reaches V
with the LVT bit set in the TRIM_LVT register.
during STOP Mode,
UVCIL
NOTE
Executing STOP with VSUP < V
Mode.
and LVT = 1, the MM912_637 will immediately enter Cranking
UVCIL
During Cranking Mode, the analog die will gate its internal oscillator to stop all ongoing acquisitions during the low power condition.
Returning from Cranking mode will appear as a wake-up from undervoltage interrupt (UVI=1). The analog die will be in Intermediate mode
after wake-up, and could be sent into Normal mode (Stop, Sleep), by writing the OPM bits.
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Device with Cranking Mode Enabled
Device with Cranking Mode Disabled
Normal /
Intermediate
Mode
Normal /
Stop / Sleep
Intermediate
Mode
Stop / Sleep
Mode
Mode
High Precision
Comparator always on
in Normal /
High Precision
Comparator => ON
Under Voltage IRQ
(UVI) issued.
Inactive during Stop /
Sleep
VUVIL
Intermediate Mode
Handle IRQ, prepare
for Cranking Mode
Inactive during Stop /
Sleep
Handle IRQ, prepare
for Cranking Mode
Inactive during Stop /
Sleep
VLVIA
Cranking Mode Entry
without MCU
interaction. MCU will
stay in STOP mode or
turned off.
Inactive for Non
Cranking Mode Device
Option
Inactive for Non
Cranking Mode Device
Option
Under Voltage IRQ
(UVI) issued.
VUVCIL
MCU initiates rapid shutdown
to Cranking Mode (OPM=11) and
enters STOP.
CRANKING MODE
(MCU = Stop or Off,
Analog = Cranking Mode
LPOSC gated => operation stopped)
MCU in LVR, Analog
Die remains in Low
Power Mode
Inactive during Stop /
Sleep
Inactive during Cranking Mode
Inactive during Cranking Mode
Inactive during Cranking Mode
VLVRA
LOW VOLTAGE RESET at VDDX
=> Analog Die + MCU in Reset Mode
VLVRXL
VLVRHL
VLVRAL
System remains in Reset
Mode
MCU POR, RAM invalid,
Analog Die Remains in
Cranking Mode
MCU POR, RAM invalid, Both
Dice Remain in Reset Mode
VPORA
Inactive for Cranking Mode
Device Option
Analog Die Power On Reset
VPORL
Inactive for Non - Cranking
Mode Device Option
Analog Die Power On Reset
VPORCL
Figure 18. Power down sequence
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4.3.4
Wake-up sources
Several wake-up sources have been implemented in the MM912_637, to exit from Sleep or Stop mode. Figure 19 shows the wake-up
sources and the corresponding configuration and status bits.
To indicate the internal wake-up signal, a routing of the internal wake-up signal to the PTBx output (WKUP) is implemented. See
Section 4.11, “General purpose I/O - GPIO", for additional details on the required configuration.
GPIO
WKUP
TIM4CH
TCOMP3..0
PTB0
I/O
WUPTB0
Output Compare CH3
TCOMP3..0
Output Compare CH2
Sytem
Wake
Up
PTB1
I/O
Output Compare CH1
Output Compare CH0
WUPTB1
WUPTB2
TCOMP3..0
PTB2
I/O
=1
WLPMF
WUPTB0F
WUPTB1F
WUPTB2F
WUPTB3F
WULINF
L0
PTB3
I/O
PTWU
WUPTB3
WUAHTHF
WUCTHF
WUCALF
WULTCF
LIN
WULIN
LIN Wake Up detected
WUAHTH
WUCTH
WUCAL
Current Trigger
Current Accumulator
Threshold reached
Current
Threshold reached
Calibration Request
Life Time Counter
WULTC
Life Time Counter
Overflow
Figure 19. Wake-up sources
4.3.4.1
Wake-up source details
Cyclic current acquisition/calibration temperature check
4.3.4.1.1
A configurable (ACQ_TCMP) independent low power mode counter/trigger, based on the ALFCLK, has been implemented to trigger a
cyclic current measurement during the low power modes. To validate that the temperature is still within the calibration range, the
temperature measurement can be enabled during this event as well.
As a result of the cyclic conversions, three wake-up conditions are implemented.
•
•
•
Current Threshold Wake-up
Current Averaging Wake-up
Calibration Request Wake-up
The configuration of the counter and the cyclic measurements is part of the acquisition paragraph (see Section 4.8, “Channel acquisition").
The actual cyclic measurement does not wake-up the microcontroller unless one of the three wake-up conditions become valid.
4.3.4.1.1.1 Current threshold wake-up
Every cyclic current measurement result (absolute content of the ADC result I_CURR register) is compared with a programmable
unsigned current threshold (CTH in the ACQ_CTH register).
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The comparison is done with the CTH content left - shifted by 1, as shown in Table 69.
Table 69. Current Threshold Comparison
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
CTH[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CTH[7:0]
0
ABS(CURR[23:0])
X
ABS(CURR[23:0])
If the absolute result is greater or equal to the programmed and shifted threshold, a filter counter is incremented (decremented if below).
If the filter counter (8-Bit) reaches the programmable low power current threshold filtering period (ACQ_THF), a wake-up initiated if the
Current Threshold Wake-up is enabled (WUCTH). The filter counter is reset every time a low power mode is entered. The implementation
is shown in Figure 20.
The wake-up source is flagged with the WUCTHF Bit.
Figure 20. Current threshold - wake-up counter
4.3.4.1.1.2 Current ampere hour threshold wake-up
As shown in Figure 21, every cyclic current measurement (signed content of the ADC result ACQ_CURR register) is added to the 32-Bit
(signed) current accumulator (ACQ_AHC) (both in two’s complement format). If the absolute accumulator value reaches (|ACQ_AHC|
ACQ_AHTH), the absolute programmable 31-Bit current threshold (ACQ_AHTH), a wake-up is initiated if the Current AH Threshold
Wake-up is enabled (WUAHTH). The accumulator could be reset by writing 1 into the AHCR register.
The Ampere Hour Counter is counting after wake-up. In normal mode, the accumulator register ACQ_AHC can be read out anytime. The
wake-up source is flagged with the WUAHTHF Bit.
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Ah counter
Accu
threshold
(progr.)
actual
measured
current
uC
wake-up
measurement
interval
t
start low-power mode = reset of
Ah counter
Figure 21. Ah counter function
4.3.4.1.1.3 Calibration request wake-up
Once the temperature measured during the cyclic sense is indicating a potential “out of calibration” situation, a wake-up is issued if the
Calibration Request Wake-up is enabled (WUCAL). For additional details, refer to Section 4.8.5, “Calibration". The wake-up source is
flagged with the WUCALF Bit.
4.3.4.1.2
Timed wake-up
To generate a programmable wake-up timer, the integrated 4 Channel Timer Module is supplied, during both low power modes and
running on the ALFCLK clock. To wake-up from one of the low power modes, the output compare signal (OC) of any of the 4 channels
can be routed to the PTB[2:0] logic (standard feature also in Normal mode). Enabling the corresponding Wake-up Enable Bit (WUPTBx)
will generate the wake up, once the timer output compare becomes active.
NOTE
Only the internal GPIO logic is active during the low power modes. The Port I/O structures will not be
active.
To allow an accurate wake-up configuration during the clock transition, the timer should be configured before entering one of the low power
modes, without the Timer Enable Bit (TEN) being set. Setting the Timer Wake-up Enable Bit (WUPTB) will enable the TIMER interrupts
as wake-up sources, and cause the Timer Enable Bit (TEN) to be set, once the timer clock domain was changed to the ALFCLK clock
supplied by LPOSC.
During low-power mode, only current and temperature measurements are performed, so only the current measurement channel is active
with the temperature channel being optional - the voltage measurement channel is inactive. To reduce further the power consumption,
only triggered current measurements are done. For this purpose, an independent Timer Module is used to periodically start a current
measurement after a programmable time (ACQ_TCMP).
4.3.4.1.3
Wake-up from LIN
During Low Power mode, operation of the transmitter of the physical layer is disabled. The receiver remain, active and able to detect
wake-up events on the LIN bus line. For further details, refer to Section 4.12, “LIN". Adominant level longer than t followed by a rising
WUPF
edge, will generate a wake-up event if the WULIN is enabled. The wake-up source is flagged with the WULINF Bit.
NOTE
If the LIN module is disabled (LIN_CTL:EN=0), no wake-up will be issued after the dominant to
recessive transition, when the device goes to low power mode, while the LIN bus is in the DOMINANT
STATE.
If the LIN module is enabled (LIN_CTL:EN=1), the device will wake-up after the dominant to recessive
transition, when the device goes to low power mode, while the LIN bus is in the DOMINANT STATE.
A full dominant -> recessive -> dominant sequence, during low power mode, will wake-up the device
in both cases.
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4.3.4.1.4
Wake-up on wake-up pin high level
Once a Wake-up signal (high level) is detected on the PTB3/L0 input, with the Wake-up Enable Bit (WUPTB3) and the port configuration
bit (PTWU) set, a wake-up is issued. The wake-up source is flagged with the WUPTB3F Bit.
4.3.4.1.5
Wake-up on life time counter overflow
The life time counter continues to run during low power mode, if configured. Once the counter overflows with the life time counter wake-up
enabled (WULTC=1), a wake-up is issued. The wake-up source is flagged with the WULTC Bit. Life Time Counter has to be configured in
Normal mode only.
4.3.4.1.6
General wake-up indicator
To indicate the system has been awakened after power up, the WLPMF flag will be set.
4.3.5
Device clock tree
4.3.5.1
Clock scheme overview
There are two system oscillators implemented. The low power oscillator is located on the analog die, and is supplied permanently and has
a nominal frequency of f (512 kHz), providing a LPCLK clock signal. It is primarily used in low power mode, and as an independent
OSCL
clock source for the watchdog during Normal mode.
The high power oscillator is basically the internal or external microcontroller oscillator (active only during normal mode). The high power
oscillator is distributed to the analog die via the D2DCLK (via configurable MCU prescalers), and there it’s divided into two clocks
(D2DSCLK and D2DFCLK), based on the PRESC[15:0] prescaler. For the D2DSCLK, an additional 2 Bit divider PF[1:0] is implemented
(87). During Normal mode, D2DSCLK is continuously synchronizing the LPCLK, to create the accurate ALFCLK (See Section 4.3.5.2,
“ALFCLK calibration"), D2DCLK is the clock source of the TIM16B4C (Timer), and S08SCIV4 (SCI) module with a fixed by 4 divider.
Notes
87. PF[1:0] is not implemented as a simple divider. To accomplish a D2DSCLK period ranging from 1.0 ms to 8.0 ms, the following scheme is used: 00 -
1; 01 - 2; 10 - 4; 11 - 8.
D2DSCLK - D2D Slow Clock (1... 0.125 kHz)
Eqn. 1
D2DCLK
2PF1 0 PRESC15 0
------------------------------------------------------------------------
D2DSCLK =
D2DFCLK - D2D Fast Clock (512 kHz)
Eqn. 2
D2DCLK
2 PRESC15 10 + PRESC9
---------------------------------------------------------------------------------------
D2DFCLK =
During low power mode, D2DCLK is not available. The low power oscillator is the only system clock. Figure 22 and Figure 23 show the
different clock sources for normal and low power mode.
NOTE
D2DFCLK has to be set to match 512 kHz, resulting in D2DSCLK being 1.0, 2.0, 4.0, or 8.0 kHz,
based on PF[1:0]
The minimum value for PRESC[15:0] has to be 0x0400. Any value lower than 0x0400 will result in
faulty behavior and is not recommended. Values of 0x0003 or less are not stored by the internal logic.
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WDTO[2:0]=100
tIWDTO
tWDTO
Window
Watchdog
LPOSC
(fOSCL)
WDTO[2:0]
LP CLK Synch
LPCLK
Life Time Counter
ALFCLK
D2DSCLK
PF[1:0]
trim_lposc
Channel
D2DFCLK
Acquisition
PRESC[15:0]
D2D Interface
TIM16B4C
(Timer)
D2DCLK
[15:10]
[9:0]
S08SCIV4
(SCI)
DIV4
Figure 22. Clock tree overview - normal mode
Life Time Counter
LPOSC
LP CLK Synch
LPCLK
ALFCLK
TIM16B4C
(Timer)
trim_lposc
Current Trigger
Channel
Acquisition
Figure 23. Clock tree overview - low power modes
4.3.5.2
ALFCLK calibration
To increase the accuracy of the 1.0 kHz (or 2.0, 4.0, 8.0 kHz based on PF[1:0]) system clock (ALFCLK), the low power oscillator (LPCLK)
is synchronized to the more precise D2DCLK, via the D2DSCLK signal. The “Calibrated Low Power Clock” (ALFCLK) could be trimmed
to the D2DCLK accuracy plus a maximum error adder of 1 LPCLK period, by internally counting the number of periods of the LPCLK
(512 kHz) during a D2DSCLK period. The APRESC[12:0] register will represent the calculated internal prescaler. The PRDF bit (Prescaler
Ready flag) will indicate the synchronization complete after a power up or prescaler (PRESC/PF) change.
The adjustment is continuously performed during Normal mode. During low power mode (STOP or SLEEP), the last adjustment factor
would be used.
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D2DCLK
PRESC[15:0]+PF[1:0] Counter based ms clock (D2DSCLK) period
LPCLK
1
2
3
4
5
6
7
8
9
APRESC[12:0]
PRDF
0x0200 (512d) default
0
0x0009 (9d)
1
Synch
Start
Synch
Finished
Figure 24. ALF clock calibration procedure during normal mode
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
LPCLK
PRDF
0
?
1
APRESC[12:0]
0x0009 (9d)
ALFCLK
Figure 25. ALFCLK after calibration
4.3.5.3
Recommended clock settings
Considering the system is running on the internal oscillator, Table 70 shows the recommended clock settings to achieve the optimal
512 kHz D2DFCLK. For details on the MCU divider settings, including POSTDIV and SYNDIV, see Section 4.23, “S12 clock, reset, and
power management unit (9S12I128PIMV1)". The D2D initiator module includes D2DCLKDIV see Section 4.26, “MCU - die-to-die initiator
(9S12I128PIMV1)".
Table 70. Recommended clock settings
fD2D / MHz
POSTDIV for (SYNDIV=fVCO in MHz)
32.768
31.744
30.720
29.696
28.672
27.648
26.624
16.384
8.192
7.168
0
64
62
60
58
56
54
52
63;64
61;62
59;60
57;58
55;56
53;54
51;52
0
15.360 10.240
0
0
14.336
9.216
0
0
13.312
0
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Table 70. Recommended clock settings (continued)
fD2D / MHz
POSTDIV for (SYNDIV=fVCO in MHz)
25.600
0
50
48
46
44
42
40
48
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
49;50
47;48
45;46
43;44
41;42
39;40
47;48
35;36
33;34
31;32
29;30
27;28
25;26
23;24
21;22
19;20
17;18
15;16
13;14
11;12
9;10
24.576
23.552
22.528
21.504
20.480
19.456
18.432
17.408
16.384
15.360
14.336
13.312
12.288
11.264
10.240
9.216
12.288
11.264
10.240
9.216
8.192
7.168
6.144
5.120
4.096
3.072
2.048
8.192
7.168
6.144
5.120
4.096
3.072
2.048
6.144
5.120
4.096
3.072
2.048
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
2
1
2
1
2
8.192
3
2
3
1
7.168
3
2
6
6.144
4
5
5.120
4
3
4
4.096
7
6
5
7
3
7
7;8
3.072
9
8
5
8
6
5;6
2.048
15
14
13
12
11
10
9
4
4
Notes
88. For D2DCLKDIV=1
4.3.6
System resets
To guarantee safe operation, several RESET sources have been implemented in the MM912_637 device. Both the MCU and the analog
die are designed to initiate reset events on internal sources and the MCU is capable of being reset by external events including the analog
die reset output. The analog die can be reset through RESETA in stop and cranking mode only. In normal mode, the MCU can reset the
analog die only by writing 1 into HWR bit (remind the mask bit HWRM).
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4.3.6.1
Device reset overview
The MM912_637 reset concept includes two external reset signals, RESET (MCU) and RESET_A (analog Die). Figure 26 illustrates the
general configuration.
Power-On Reset
Hardware Reset
(POR)
Low Voltage
Reset (LVR)
Watchdog Reset
External pin
RESET
Low Voltage
Reset
Illegal Address
Reset
Thermal
Shutdown Reset
Clock monitor
reset
COP watchdog
reset
MCU
Analog Die
Figure 26. Device reset overview
Both RESET and RESET_A signals are low active I/Os, based on the 5.0 V supply (VDDRX for RESET and VDDX for RESET_A).
4.3.6.2
Analog die reset implementation
There are 7 internal reset sources implemented in the analog die of the MM912_637 that causing the internal analog die status to be reset
to default (Internal analog RST), and to trigger an external reset, activating the RESET_A pin. In addition, during stop and cranking mode,
an external reset at the RESET_A pin will also reset the analog die.
VDDLR
RESET_A
1
VDDHR
0
0
1
WDR
Cranking
Mode
tRSTRT
LPM
HWR
TSDR
VDDXR
1
VDDAR
0
Measure
LPM = Low Power Mode
during LPM
Figure 27. Analog die reset implementation
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The WDR and HWR will issue a reset on the RESET_A pin during t
(see Table 30). The other reset VDDLR, VDDHR, VDDXR,
RSTRT
VDDAR, and TSDR will drive the RESET_A pin as long as the condition is present. During cranking mode (89), only the VDDLR is active.
During Low Power modes, only VDDXR and VDDAR are active reset sources. VDDAR is only active during active measurement in LPM.
VDDXR and VDDAR are not active in Normal mode.
Notes
89. Not available on all device derivatives
4.3.6.3
Reset source summary
•
•
•
HWR - Hardware Reset
—
Forced internal reset caused by writing the HWR bit in the PCR_CTL register. The source will be indicated by the HWRF bit.
WDR - Watchdog Reset
Window watchdog failure. The source will be indicated by the WDRF bit.
LVR - Low Voltage Reset
—
—
The Voltage at the VDDL, VDDH, VDDX, or VDDA has dropped below its reset threshold level. The source will be indicated
for the VDDL by the LVRF + HVRF, for the VDDA by the AVRF, and for the VDDH by the HVRF bit. VDDX resets are not
indicated via individual reset flags. See Figure 27 for dependencies.
•
•
TSDR - Temperature Shutdown Reset
—
The critical shutdown temperature threshold has been reached. VDDA, VDDX, and VDDH will be disabled as long as the
overtemperature condition is pending(90) and the reset source is indicated by the HTF bit.
External Reset
During stop and cranking(90) mode, a low signal at the RESET_A pin will reset the analog die. Since this condition can only
be initiated by the microcontroller, no specific indicator flag is implemented.
—
Notes
90. Resulting in a VDDH Low Voltage Reset taking over the reset after the 2 LPCLK reset pulse
TSDR
WDR
HTF
WDRF
HWRF
HVRF
LVRF
AVRF
HWR
VDDHR
VDDLR
VDDAR
VDDXR
No Flag Indicator
Figure 28. Reset status information
4.3.7
PCR - memory map and registers
4.3.7.1
Overview
This section provides a detailed description of the memory map and registers.
4.3.7.2
Module memory map
The memory map for the Analog Die - Power, Clock and Resets - PCR module is given in Table 63
Table 71. Module Memory Map
Offset
Name
7
6
5
4
3
2
1
0
(91),(92)
R
W
R
0
0
0
HWRM
0
0
0
0
0
0
0
0
0
HTIEM
UVIEM
PFM[1:0]
PF[1:0]
OPMM[1:0]
OPM[1:0]
PCR_CTL
PCR Control Register
0x00
HTIE
UVIE
W
HWR
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Table 71. Module Memory Map
Offset
Name
7
6
5
4
3
2
1
0
(91),(92)
PCR_SR (hi)
0x02
R
W
R
HTF
UVF
HWRF
WDRF
HVRF
LVRF
WULTCF
WLPMF
PCR Status Register
Write 1 will clear the flags
WULINF WUPTB3F WUPTB2F WUPTB1F WUPTB0F
PCR_SR (lo)
0x03
WUAHTHF WUCTHF
WUCALF
PCR Status Register
W
R
Write 1 will clear the flags
W
R
PCR_PRESC
0x04
PRESC[15:0]
PCR 1.0 ms prescaler
W
R
PCR_WUE (hi)
0x06
WUAHTH
WULTC
WUCTH
0
WUCAL
0
WULIN
0
WUPTB3
0
WUPTB2
0
WUPTB1
0
WUPTB0
0
Wake-up Enable Register
W
R
PCR_WUE (lo)
0x07
Wake-up Enable Register
W
TRIM_ALF (hi)
0x0E
R
W
R
PRDF
0
0
APRESC[12:8]
Trim for accurate 1.0 ms low freq clock
TRIM_ALF (lo)
0x0F
APRESC[7:0]
Trim for accurate 1.0 ms low freq clock
W
Notes
91. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
92. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
4.3.7.3
Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.3.7.3.1
PCR control register (PCR_CTL)
Table 72. PCR control register (PCR_CTL)
Offset
,
0x00
Access: User read/write
(93) (94)
15
14
13
12
0
11
0
10
0
9
8
0
R
W
0
0
0
0
HTIEM
UVIEM
HWRM
0
PFM[1:0]
PF[1:0]
OPMM[1:0]
Reset
0
7
0
6
0
0
0
3
0
2
0
1
0
0
5
0
4
R
W
0
HTIE
0
UVIE
0
OPM[1:0]
0
HWR
0
0
Reset
0
0
0
0
Notes
93. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
94. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
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Table 73. PCR control register (PCR_CTL) - register field descriptions
Field
Description
High temperature interrupt enable mask
0 - writing the HTIE bit will have no effect
1 - writing the HTIE bit will be effective
15
HTIEM
Supply undervoltage interrupt enable mask
0 - writing the UVIE bit will have no effect
1 - writing the UVIE bit will be effective
14
UVIEM
Hardware reset mask
0 - writing the HWR bit will have no effect
1 - writing the HWR bit will be effective
13
HWRM
12
Reserved
Reserved. Must remain “0”
Prescaler factor mask
00,01,10 - writing the PF bits will have no effect
1 - writing the PF bits will be effective
11-10
PFM[1:0]
Operation mode mask
00,01,10 - writing the OPM bits will have no effect
11 - writing the OPM bits will be effective
9-8
OPMM[1:0]
High Temperature Interrupt enable. Writing only effective with corresponding mask bit HTIEM set.
0 - High temperature interrupt (HTI) enabled
1 - High temperature interrupt (HTI) disabled
7
HTIE
Low supply voltage interrupt enable. Writing only effective with corresponding mask bit UVIEM set.
0 - Low supply voltage interrupt (UVI) enabled
1 - Low supply voltage interrupt (UVI) disabled
6
UVIE
Hardware Reset. Writing only effective with corresponding mask bit HWRM set. Write only.
0 - No effect
1 - All analog die digital logic is reset and external reset (RESET_A) is set to reset the MCU.
5
HWR
4
Reserved. Must remain “0”
Reserved
1.0 ms Prescaler. Writing only effective with corresponding mask bits PFM set to 11.
00 - 1
01 - 2
10 - 4
11 - 8
3-2
PF[1:0]
Operation mode select. Writing only effective with “11” mask bits OPMM set to 11.
00 - Normal mode
1-0
01 - Stop mode
OPM[1:0]
10 - Sleep mode
11 with Cranking feature disabled - same effect as 01 (STOP mode)
11 with Cranking feature enabled - Cranking mode
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4.3.7.3.2
PCR status register (PCR_SR (hi))
Table 74. PCR status register (PCR_SR (hi))
Offset(95)
Access: User read/write
0x02
7
6
5
4
3
2
1
0
R
W
HTF
UVF
HWRF
WDRF
HVRF
LVRF
WULTCF
WLPMF
Write 1 will clear the flags(96)
0/1 0/1
Reset
0
0
0/1
0/1
0
0
Notes
95. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
96. HTF and UVF represent the current status and cannot be cleared. Writing 1 to HTF / UVF will clear the Interrupt flag in the Interrupt Source Register
and Interrupt Vector Register instead.
Table 75. PCR status register (PCR_SR (hi)) - register field descriptions
Field
Description
High Temperature Condition Flag. This bit is set once a temperature warning is detected, or the last reset being caused by a temperature
shutdown event (TSDR). Writing HTF=1 will clear the flag and the interrupt flag in the Interrupt Source Register and Interrupt Vector
Register, if the condition is gone.
7
HTF
0 - No High Temperature condition detected.
1 - High Temperature condition detected or last reset = TSDR.
Supply Undervoltage Condition Flag. This bit is set once a undervoltage warning is detected. Writing UVF=1 will clear the flag and the
Interrupt flag in the Interrupt Source Register and Interrupt Vector Register, if the condition is gone (UVF=0).
6
0 - No undervoltage condition detected.
1 - Undervoltage condition detected.
UVF
Hardware Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by a HWR command.
5
HWRF
Watchdog Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by the analog die window watchdog.
4
WDRF
VDDH Low Voltage Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
3
HVRF
1 - Last reset was caused by a low voltage condition at the VDDH regulator. (LVRF = 0)
1 - Last reset was caused by a low voltage condition at the VDDL regulator. (LVRF = 1)
VDDL Low Voltage (POR) Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by a low voltage condition at the VDDL regulator. (Power on Reset - POR)
2
LVRF
Life Time Counter Wake-up Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last Wake-up was caused by a life time counter overflow
1
WULTCF
Wake-up after Low Power Mode Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after Low Power mode.
0
WLPMF
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4.3.7.3.3
PCR status register (PCR_SR (lo))
Table 76. PCR status register (PCR_SR (lo))
Offset(97)
Access: User read/write
0x03
7
6
5
4
3
2
1
0
R
W
WUAHTHF
WUCTHF
WUCALF
WULINF
WUPTB3F
WUPTB2F
WUPTB1F
WUPTB0F
Write 1 will clear the flags
Reset
0
0
0
0
0
0
0
0
Notes
97. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 77. PCR status register (PCR_SR (lo)) - register field descriptions
Field
Description
Wake-up on Ah counter threshold Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after Ah counter threshold reached.
7
WUAHTHF
Wake-up on current threshold Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after current threshold reached.
6
WUCTHF
Wake-up on calibration request flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after calibration request.
5
WUCALF
Wake-up on LIN flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after LIN wake-up detected
4
WULINF
Wake-up on GPIO 3 event (L0 external wake-up) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 3 event
3
WUPTB3F
Wake-up on GPIO 2 event (TIMER output compare) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 2 event
2
WUPTB2F
Wake-up on GPIO 1 event (TIMER output compare) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 1 event
1
WUPTB1F
Wake-up on GPIO 0 event (TIMER output compare) flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Indicates wake-up after GPIO 0 event
0
WUPTB0F
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4.3.7.3.4
PCR 1.0 ms prescaler (PCR_PRESC)
Table 78. PCR 1.0 ms Prescaler (PCR_PRESC)
Offset (98),(99)
Access: User read/write
0x04
15
14
13
12
11
10
9
8
R
W
PRESC[15:8]
PRESC[7:0]
Reset
0
7
1
6
1
5
1
4
1
3
1
2
0
1
1
0
R
W
Reset
0
0
0
0
0
0
0
0
Notes
98. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
99. This Register is 16 Bit access only.
Table 79. PCR 1.0 ms prescaler (PCR_PRESC) - register field descriptions
Field
Description
15-0
PRESC[15:0]
1.0 ms Prescaler, used to derive D2DSCLK and D2DFCLK from the D2DCLK signal. See 4.3.5, “Device clock tree" for details.
4.3.7.3.5
Wake-up enable register (PCR_WUE (hi))
Table 80. Wake-up enable register (PCR_WUE (hi))
Offset(100)
Access: User read/write
1 0
0x06
7
WUAHTH
0
6
WUCTH
0
5
WUCAL
0
4
WULIN
0
3
WUPTB3
0
2
WUPTB2
0
R
W
WUPTB1
0
WUPTB0
0
Reset
Notes
100. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 81. Wake-up enable register (PCR_WUE (hi)) - register field descriptions
Field
Description
7
0 - Wake-up on Ah counter disabled
1 - Wake-up on Ah counter enabled
WUAHTH
6
0 - Wake-up on current threshold disabled
1 - Wake-up on current threshold enabled
WUCTH
5
0 - Wake-up on calibration request disabled
1 - Wake-up on calibration request enabled
WUCAL
4
0 - Wake-up on LIN disabled
1 - Wake-up on LIN enabled
WULIN
3
0 - Wake-up on GPIO 3 event disabled
1 - Wake-up on GPIO 3 event enabled
WUPTB3
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Table 81. Wake-up enable register (PCR_WUE (hi)) - register field descriptions (continued)
Field
Description
2
0 - Wake-up on GPIO 2 event disabled
1 - Wake-up on GPIO 2 event enabled
WUPTB2
1
0 - Wake-up on GPIO 1 event disabled
1 - Wake-up on GPIO 1 event enabled
WUPTB1
0
0 - Wake-up on GPIO 0 event disabled
1 - Wake-up on GPIO 0 event enabled
WUPTB0
4.3.7.3.6
Wake-up enable register (PCR_WUE (lo))
Table 82. Wake-up enable register (PCR_WUE (lo))
Offset(101)
Access: User read/write
0x07
7
WULTC
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
Notes
101. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 83. Wake-up enable register (PCR_WUE (lo)) - register field descriptions
Field
Description
7
0 - Wake-up on Life Timer Counter Overflow disabled
1 - Wake-up on Life Timer Counter Overflow enabled
WULTC
4.3.7.3.7
Trim for accurate 1.0 ms low freq clock (TRIM_ALF (hi))
Table 84. Trim for accurate 1.0 ms low freq clock (TRIM_ALF (hi))
Offset(102)
Access: User read
8
0x0E
15
14
0
13
0
12
11
10
9
R
PRDF
APRESC[12:8]
W
Notes
102. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.3.7.3.8
Trim for accurate 1.0 ms low freq clock (TRIM_ALF (lo))
Table 85. Trim for accurate 1.0 ms low freq clock (TRIM_ALF (lo))
Offset(103)
Access: User read
0
0x0F
7
6
5
4
3
2
1
R
APRESC[7:0]
W
Notes
103. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 86. Trim for accurate 1.0 ms low freq clock (TRIM_ALF (lo)) - register field descriptions
Field
Description
ALFCLK Prescaler ready Flag
0 - The ALFCLK synchronization after power up or PRESC[15:0] / PF[1:0] change is not completed.
1 - The ALFCLK synchronization is complete. The ALFCLK signal is synchronized to the D2DCLK.
15
PRDF
ALFCLK Prescaler
This read only value represents the current ALFCLK prescaler value. With the synchronization complete (PRDF=1), the prescaler is
used to create the calibrated clock for the Life Time Counter (Normal mode and Low Power mode), and Timer and Current trigger (Low
Power Mode only), based on the low power oscillator.
12-0
APRESC[12:0]
After Power Up, the APRESC register is reset to 0x0200 (512dec) until the first synchronization is complete. This will initialize the
ALFCLK to 1.0 kHz.
4.4
Interrupt module - IRQ
Introduction
4.4.1
Several interrupt sources are implemented on the analog die to indicate important system conditions. Those Interrupt events are
signalized via the D2DINT signal to the microcontroller. See Section 4.18, “MCU - interrupt module (S12S9S12I128PIMV1V1)".
4.4.2
Interrupt source identification
Once an Interrupt is signalized, there are two options to identify the corresponding source(s).
NOTE
The following Interrupt source registers (Interrupt Source Mirror and Interrupt Vector Emulation by
Priority) are indicators only. After identifying the interrupt source, the acknowledgement of the
interrupt has to be performed in the corresponding block.
4.4.2.1
Interrupt source mirror
All Interrupt sources in the MM912_637 analog die are mirrored to a special Interrupt Source Register (INT_SRC). This register is read
only and will indicate all currently pending Interrupts. Reading this register will not acknowledge any interrupt. An additional D2D access
is necessary to serve the specific module.
4.4.2.2
Interrupt vector emulation by priority
To allow a vector based interrupt handling by the MCU, the number of the highest prioritized interrupt pending is returned in the Interrupt
Vector Register (INT_VECT). Reading this register will not acknowledge an interrupt. An additional D2D access is necessary to serve the
specific module.
4.4.3
Interrupt global mask
The Global Interrupt mask registers INT_MSK (hi) and INT_MSK (lo) are implemented to allow a global enable / disable of all analog die
Interrupt sources. The individual blocks mask registers should be used to control the individual sources.
4.4.4
Interrupt sources
The following Interrupt sources are implemented on the analog die.
Table 87. Interrupt sources
IRQ
Description
UVI
HTI
Undervoltage Interrupt (or wake-up from Cranking mode)
High Temperature Interrupt
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Table 87. Interrupt sources
IRQ
Description
LTI
CH0
CH1
CH2
CH3
TOV
ERR
TX
LIN Driver Overtemperature Interrupt
TIM Channel 0 Interrupt
TIM Channel 1 Interrupt
TIM Channel 2 Interrupt
TIM Channel 3 Interrupt
TIM Timer Overflow Interrupt
SCI Error Interrupt
SCI Transmit Interrupt
RX
SCI Receive Interrupt
CVMI
LTC
CAL
Current / Voltage Measurement Interrupt
Lifetime Counter Interrupt
Calibration Request Interrupt
4.4.4.1
Undervoltage interrupt (UVI)
This maskable interrupt signalizes a undervoltage condition on the VSUP supply input. Acknowledge the interrupt by writing a 1 into the
UVF Bit in the PCR Status Register (PCR_SR (hi)). The flag cannot be cleared as long as the condition is present. To issue a new interrupt,
the condition has to vanish and occur again. The UVF Bit represents the current condition, and might not be set after an interrupt was
signalized by the interrupt source registers. See Section 4.3, “Analog die - power, clock and resets - PCR" for details on the PCR Status
Register (PCR_SR (hi)), including masking information.
NOTE
The undervoltage interrupt is not active in devices with the Cranking mode enabled. For those
devices, the undervoltage threshold is used to enable the high precision low voltage threshold during
Stop/Sleep mode. Once the device wakes up from cranking mode, the UVI flag is indicating the
wake-up source.
4.4.4.2
High temperature interrupt (HTI)
This maskable interrupt signalizes a high temperature condition on the analog die. The sensing element is located close to the major
thermal contributors, the system voltage regulators.
Acknowledge the interrupt by writing a 1 into the HTF Bit in the PCR Status Register (PCR_SR (hi)). The flag cannot be cleared as long
as the condition is present. To issue a new interrupt, the condition has to vanish and occur again. The HTF Bit represents the current
condition and might not be set after an interrupt was signalized by the interrupt source registers. See Section 4.3, “Analog die - power,
clock and resets - PCR" for details on the PCR Status Register (PCR_SR (hi)), including masking information.
4.4.4.3
LIN driver overtemperature interrupt (LTI)
Acknowledge the interrupt by reading the LIN Register - LINR. The flag cannot be cleared as long as the condition is present. To issue a
new interrupt, the condition has to vanish and occur again. See Section 4.12, “LIN" for details on the LIN Register, including masking
information.
4.4.4.4
TIM channel 0 interrupt (CH0)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.5
TIM channel 1 interrupt (CH1)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
MM912_637D1
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4.4.4.6
TIM channel 2 interrupt (CH2)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.7
TIM channel 3 interrupt (CH3)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.8
TIM timer overflow interrupt (TOV)
See Section 4.10, “Basic timer module - TIM (TIM16B4C)".
4.4.4.9
SCI error interrupt (ERR)
See Section 4.13, “Serial communication interface (S08SCIV4)".
4.4.4.10 SCI transmit interrupt (TX)
See Section 4.13, “Serial communication interface (S08SCIV4)".
4.4.4.11 SCI receive interrupt (RX)
See Section 4.13, “Serial communication interface (S08SCIV4)".
4.4.4.12 Current/voltage measurement interrupt (CVMI)
Indicates the current or voltage measurement finished (VM or CM bit set). See Section 4.8, “Channel acquisition".
4.4.4.13 Life time counter interrupt (LTC)
In case a Life Time Counter overflow occurs with the corresponding interrupt enabled, the LTC interrupt is issued. See Section 4.14, “Life
time counter (LTC)".
4.4.4.14 Calibration request interrupt (CAL)
Once a request for re-calibration is present (Temperature out of pre-set range), the Calibration Interrupt is issued. After a calibration
wake-up, the reading of ACQ_ITEMP must be done after waiting for the latency of the temperature acquisition chain. Then ACQ_ITEMP
is valid to adjust the compensation over temperature. See full documentation on the interrupt source inSection 4.8, “Channel acquisition".
4.4.5
IRQ - memory map and registers
Overview
4.4.5.1
This section provides a detailed description of the memory map and registers.
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4.4.5.2
Module memory map
The memory map for the IRQ module is given in Table 63
Table 88. Module memory map
Offset(104)
0x08
Name
7
6
5
4
3
2
1
0
INT_SRC (hi)
R
W
R
TOV
CH3
CH2
CAL
0
CH1
LTC
0
CH0
LTI
RX
HTI
TX
UVI
Interrupt source register
INT_SRC (lo)
0
0
0
0
0
0
CVMI
ERR
0x09
0x0A
0x0B
0x0C
Interrupt source register
INT_VECT
W
R
IRQ[3:0]
Interrupt vector register
W
R
0
0
0
0
0
0
Reserved
W
R
INT_MSK (hi)
Interrupt mask register
INT_MSK (lo)
TOVM
0
CH3M
0
CH2M
CALM
CH1M
LTCM
CH0M
CVMM
LTIM
RXM
HTIM
TXM
UVIM
W
R
0x0D
ERRM
Interrupt mask register
W
Notes
104. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.4.5.3
Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.4.5.3.1
Interrupt source register (INT_SRC (hi))
Table 89. Interrupt source register (INT_SRC (hi))
Offset(105)
Access: User read
0x08
7
6
5
4
3
2
1
0
R
TOV
CH3
CH2
CH1
CH0
LTI
HTI
UVI
W
Notes
105. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 90. Interrupt Source Register (INT_SRC (hi)) - register field descriptions
Field
Description
TIM16B4C - Timer overflow interrupt status
0 - No timer overflow interrupt pending
1 - Timer overflow interrupt pending
7
TOV
TIM16B4C - TIM channel 3 interrupt status
0 - No channel 3 interrupt pending
1 - Channel 3 interrupt pending
6
CH3
TIM16B4C - TIM channel 2 interrupt status
0 - No channel 2 interrupt pending
1 - Channel 2 interrupt pending
5
CH2
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Table 90. Interrupt Source Register (INT_SRC (hi)) - register field descriptions (continued)
Field
Description
TIM16B4C - TIM channel 1 interrupt status
0 - No channel 1 interrupt pending
1 - Channel 1 interrupt pending
4
CH1
TIM16B4C - TIM channel 0 interrupt status
0 - No channel 0 interrupt pending
1 - Channel 0 interrupt pending
3
CH0
LIN Driver overtemperature interrupt status
0 - No LIN driver overtemperature interrupt
1 - LIN driver overtemperature interrupt
2
LTI
High temperature interrupt status
0 - No high temperature interrupt pending
1 - High temperature interrupt pending
1
HTI
Undervoltage interrupt pending or wake-up from Cranking mode status
0 - No undervoltage Interrupt pending or wake-up from Cranking mode
1 - Undervoltage interrupt pending or wake-up from Cranking mode
0
UVI
4.4.5.3.2
Interrupt source register (INT_SRC (lo))
Table 91. Interrupt source register (INT_SRC (lo))
Offset(106)
Access: User read
0x09
7
0
6
0
5
4
3
2
1
0
R
CAL
LTC
CVMI
RX
TX
ERR
W
Notes
106. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 92. Interrupt source register (INT_SRC (lo)) - register field descriptions
Field
Description
Calibration request interrupt status
0 - No calibration request interrupt pending
1 - Calibration request interrupt pending
5
CAL
Life time counter interrupt status
0 - No life time counter interrupt pending
1 - Life time counter interrupt pending
4
LTC
Current / Voltage measurement interrupt status
0 - No Current / Voltage measurement interrupt pending
1 - Current / Voltage measurement interrupt pending
3
CVMI
SCI receive interrupt status
0 - No SCI receive interrupt pending
1 - SCI receive interrupt pending
2
RX
SCI transmit interrupt status
0 - No SCI transmit interrupt pending
1 - SCI transmit interrupt pending
1
TX
SCI error interrupt status
0 - No SCI transmit interrupt pending
1 - SCI transmit interrupt pending
0
ERR
4.4.5.3.3
Interrupt vector register (INT_VECT)
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Table 93. Interrupt vector register (INT_VECT)
Offset(107)
Access: User read
0x0A
7
0
6
0
5
0
4
0
3
2
1
0
R
IRQ
W
Notes
107. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 94. Interrupt vector register (INT_VECT) - register field descriptions
Field
Description
4-0
IRQ
Represents the highest prioritized interrupt pending. See Table 95. If no interrupt is pending, the result will be 0.
Table 95. Interrupt vector/priority
IRQ
Description
IRQ
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Priority
-
No interrupt pending or wake-up from Stop mode
Undervoltage interrupt or wake-up from Cranking mode
High temperature interrupt
LIN driver overtemperature interrupt
TIM channel 0 interrupt
-
UVI
HTI
1 (highest)
2
LTI
3
CH0
CH1
CH2
CH3
TOV
ERR
TX
4
TIM channel 1 interrupt
5
TIM channel 2 interrupt
6
TIM channel 3 interrupt
7
TIM timer overflow interrupt
SCI error interrupt
8
9
SCI transmit interrupt
10
RX
SCI receive interrupt
11
12
CVMI
LTC
CAL
Acquisition interrupt
Life time counter interrupt
Calibration request interrupt
13
14 (lowest)
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4.4.5.3.4
Interrupt mask register (INT_MSK (hi))
Table 96. Interrupt mask register (INT_MSK (hi))
Offset(108)
Access: User read/write
0x0C
7
TOVM
0
6
CH3M
0
5
CH2M
0
4
CH1M
0
3
CH0M
0
2
LTIM
0
1
HTIM
0
0
UVIM
0
R
W
Reset
Notes
108. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 97. Interrupt mask register (INT_MSK (hi)) - register field descriptions
Field
Description
Timer overflow interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
7
TOVM
Timer channel 3 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
6
CH3M
Timer channel 2 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
5
CH2M
Timer channel 1 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
4
CH1M
Timer channel 1 interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
3
CH0M
LIN driver overtemperature interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
2
LTIM
High temperature interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
1
HTIM
Undervoltage interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
0
UVIM
4.4.5.3.5
Interrupt mask register (INT_MSK (lo))
Table 98. Interrupt mask register (INT_MSK (lo))
Offset(109)
Access: User read/write
1 0
0x0D
7
0
6
0
5
CALM
0
4
LTCM
0
3
CVMM
0
2
RXM
0
R
W
TXM
0
ERRM
0
Reset
0
0
Notes
109. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 99. Interrupt mask register (INT_MSK (lo)) - register field descriptions
Field
Description
Calibration request interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
5
CALM
Life time counter interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
4
LTCM
Current / Voltage measurement interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
3
CVMM
SCI receive interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
2
RXM
SCI transmit interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
1
TXM
SCI error interrupt mask
0 - Interrupt enabled
1 - Interrupt disabled
0
ERRM
4.5
Current measurement - ISENSE
Introduction
4.5.1
This chapter only gives a summary of the current sense module. Refer to Section 4.8, “Channel acquisition" for the complete description
of all acquisition channels, including the current measurement channel.
4.5.1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Dedicated 16 Bit Sigma Delta () ADC
Programmable Gain Amplifier (PGA) with 8 programmable gain factors
Gain Control Block (GCB) for automatic gain adjustment
Simultaneous Sampling with Voltage Channel
Programmable Gain and Offset Compensation
Optional Chopper Mode with moving average
SINC3 + IIR Stage
Calibration mode to compute compensation buffers
Programmable Low Pass Filter (LPF), configuration shared with the Voltage Measurement Channel
Optional Shunt resistor sensing feature
Triggered Sampling during Low Power Mode with programmable wake-up conditions
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4.5.1.2
Block diagram
PGA
Auto
Zero
Battery
Minus
Pole
Input
Swap
ESD
ESD
ISENSEL
ISENSEH
Decimation
with IIR
PGA
GCB
Compensation
LPF
24Bit
RSHUNT
Chassis
Ground
Vref
Digital Chopper
Figure 29. Current measurement channel
The battery current is measured by measuring the voltage drop V over an external shunt resistor, connected to ISENSEH and
DROP
ISENSEL. V
, and is defined as the differential voltage between the ISENSEL and ISENSEH inputs (V
=ISENSEL-ISENSEH). A
DROP
DROP
positive voltage drop means a positive current is flowing, and vice versa.
If the GND pin of the module is connected to ISENSEH, the measured current includes the supply current of the MM912_637 (current
flows back to negative battery pole). If the GND pin is connected to the ISENSEL input, the supply current of the MM912_637 is not
measured. However, the voltage at the ISENSEH input could go below GND (see max ratings). In this case, the current measurement still
functions as specified.
4.6
Voltage measurement - VSENSE
Introduction
4.6.1
This chapter only gives a summary of the voltage sense module. Refer to Section 4.8, “Channel acquisition" for the complete description
of all acquisition channels, including the voltage measurement channel.
4.6.1.1
Features
•
•
•
•
•
•
•
•
•
Dedicated 16 Bit Sigma Delta () ADC
Fixed High Precision Divider
Optional External Voltage Input “VOPT”
Simultaneous Sampling with Current Channel
Programmable Gain and Offset Compensation
Calibration mode to compute compensation buffers
Optional Chopper mode with moving average
SINC3 + IIR Stage
Programmable Low Pass Filter (LPF), Configuration shared with Current Measurement Channel
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4.6.1.2
Block diagram
Input
Swap
VOPT
ESD
DIV28
DIV28
Decimator
with IIR
MUX
Compensation
LPF
16Bit
VSENSE
ESD
Vref
Digital Chopper
Figure 30. Voltage Measurement Channel
The battery voltage is measured by default, via the VSENSE input. A high precision divider stage scales down the battery voltage by a
fixed factor K =1/28, to a voltage below the internal reference voltage of the Sigma Delta ADC (VSENSE*K < V ). If an optional external
REF
voltage is measured, the multiplexer (MUX) is selected to feed the V
input to the buffer.
OPT
4.7
Temperature measurement - TSENSE
4.7.1
Introduction
This chapter only gives a summary of the temperature sense module. Refer to Section 4.8, “Channel acquisition" for the complete
description of all acquisition channels, including the temperature measurement channel.
4.7.1.1
Features
•
•
•
•
•
•
Internal on chip Temperature Sensor
Optional External Temperature Sensor Input (VTEMP)
Dedicated 16-Bit Sigma Delta ADC
Programmable Gain and Offset Compensation
Optional External Sensor Supply (TSUP) with selectable capacitor
Optional Measurement during Low Power mode to trigger recalibration
4.7.1.2
Block diagram
TSUP
Input
Swap
TSUP
internal
R1
TempSense
MUX
Compensation
Decimation
16Bit
VTEMP
RVTEMP
ESD
CTSUP
Vref
R2
Digital Chopper
AGND
Figure 31. Temperature measurement channel
NOTE
To minimize ground shift effects while using the external sensor option, R2 must be placed as close
to the AGND pin as possible. C
the capacitor.
is optional. The supply output must be configured to operate with
TSUP
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4.8
Channel acquisition
4.8.1
Introduction
This chapter documents the current, voltage, and temperature acquisition flow. The chapter is structured in the following sections.
•
•
Section 4.8.2, “Channel structure overview"
Section 4.8.3, “Current and voltage measurement"
—
—
—
—
—
—
—
Section 4.8.3.1, “Shunt sense, PGA, and GCB (current channel only)"
Section 4.8.3.2, “Voltage sense multiplexer (voltage channel only)"
Section 4.8.3.3, “Sigma delta converter"
Section 4.8.3.4, “Compensation"
Section 4.8.3.5, “IIR/decimation/chopping stage"
Section 4.8.3.6, “Low pass filter"
Section 4.8.3.7, “Format and clamping"
•
Section 4.8.4, “Temperature measurement channel"
Section 4.8.4.1, “Compensation"
—
•
•
Section 4.8.5, “Calibration"
Section 4.8.6, “Memory map and registers"
4.8.2
Channel structure overview
The MM912_637 offers three parallel measurement channels. Current, Voltage, and Temperature. The Voltage Channel is shared
between the VSENSE and VOPT voltage source, the Temperature channel between ETEMP and ITEMP.
SINC3
+IIR
Format &
Clamp
1
24
16
16
I
PGA
SD
SD
SD
SINC1
LPF
10
8
Gain
(IGCx)
Offset
(COC)
SINC3
+IIR
Format &
Clamp
1
V
T
SINC1
LPF
10
8
Gain
(VSGC)
Offset
(VOC)
Format &
Clamp
1
SINC3
SINC1
8
8
Gain
(ITGC/
ETGC)
Offset
(ITOC/
ETOC)
Figure 32. Simplified measurement channel
Figure 33 shows an overview of the detailed dependencies between the control and status registers and the channels. Refer to the
following sections of this chapter for details.
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M ( ) E M V I C
R
R
R
R
R
R
R
R
W R /
W R /
R / W
W R / W R /
W R / W R /
R
R
R
R
R
R
R
W R /
W R / W R / W R / W R / W R / W R / W R / W R /
W
W R /
W R /
5
4
B
0 4 1
5
0 2 1 2
1 0 2 1
0 8 1 2
0 0 0 0
W R / W R / W R / W R / W R / W R / W R / W R /
3
0 E
4
0 A
0 0 B
W R /
R
)
M E I ( L C A
5
B
0 4 1
4
5
4
1 0 2
0 2 1 2
0 8 1 2
1
0 0 B
4
0 A
3
0 E
1 0 E
R
R
W R /
W R / W R / W R /
R
R
0 0 0 0 0 0 0 0
W R / W R /
)
M (
P
O M C C
)
P ( M M O V C
] 0 : 7 [
C V O
: 0 7 [ ] 2 . . 4 5 1 C O C
)
M ( P M O T C
] 0 : [ 7 C E T O
: 0 [ 7 C O T I
]
: 0 [ ] 9 2 . . 4 5 1 C I G
] 0 : 9 [ C G V S
] 0 : [ 7 C E T G
: 0 [ 7 C G T I
]
R
R
W R /
R
R
t r o S h
t r o S h
g a D i
W R / W R /
R / W R / W
W R / W R /
W R /
W R /
W R / W R /
W R /
R
0 0 0
R
g a D i
W R / W R / W R / W R /
R / W
W R /
R / W
W R /
W R / W R /
t r o S h
W R /
W R /
W R /
N E O P
P E O N E ( M
t
T e s
n e O p
)
Figure 33. Channel complete overview
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4.8.3
Current and voltage measurement
To guarantee synchronous voltage and current acquisition, both channels are implemented equal in terms of digital signal conditioning
and timing. The analog signal conditioning, before the Sigma Delta Converter, is different to match the different sources.
4.8.3.1
Shunt sense, PGA, and GCB (current channel only)
Current Channel specific analog signal conditioning.
4.8.3.1.1
Shunt sense
An optional current sense feature is implemented to sense the presence of the current shunt resistor. Setting the OPEN bit (ACQ_CTL
register), will activate the feature. The OPEN bit (ACQ_SR register) will indicate the shunt resistor open. The sense feature will detect an
open condition for a shunt resistance R
> ROPEN.
SHUNT
4.8.3.1.2
Programmable gain amplifier (PGA)
To allow a wide range of current levels to be measured, a programmable gain amplifier is implemented. Following the input chopper (see
Section 4.8.3.5, “IIR/decimation/chopping stage"), the differential voltage is amplified by one of the 8 gains controlled by the Gain Control
Block. The PGA has an internal offset compensation feature - see Section 4.8.4.1, “Compensation" and Section 4.8.5, “Calibration" for
details.
4.8.3.1.3
Gain control block (GCB)
To allow a transparent Gain adjustment with minimum MCU load, an automatic gain control has been implemented. The absolute output
of the PGA is constantly compared with a programmable up and down threshold (ACQ_GCB register). The threshold is a D/A output
according Table 100.
Table 100. Gain control block - register
ACQ_GCB D[7:0]
0000xxxx
0001xxxx
0010xxxx
0011xxxx
0100xxxx
0101xxxx
0110xxxx
0111xxxx
1000xxxx
1001xxxx
1010xxxx
1011xxxx
1100xxxx
1101xxxx
1110xxxx
1111xxxx
GCB high (up) threshold
ACQ_GCB D[7:0]
xxxx0000
xxxx0001
xxxx0010
xxxx0011
xxxx0100
xxxx0101
xxxx0110
xxxx0111
xxxx1000
xxxx1001
xxxx1010
xxxx1011
xxxx1100
xxxx1101
xxxx1110
xxxx1111
GCB low (down) threshold
1/16 V
2/16 V
3/16 V
4/16 V
5/16 V
6/16 V
7/16 V
8/16 V
9/16 V
0
REF
REF
REF
REF
REF
REF
REF
REF
REF
1/16 V
2/16 V
3/16 V
4/16 V
5/16 V
6/16 V
7/16 V
8/16 V
9/16 V
REF
REF
REF
REF
REF
REF
REF
REF
REF
10/16 V
11/16 V
12/16 V
13/16 V
14/16 V
15/16 V
16/16 V
REF
REF
REF
REF
REF
REF
REF
10/16 V
11/16 V
12/16 V
13/16 V
14/16 V
15/16 V
REF
REF
REF
REF
REF
REF
Once the programmed threshold is reached, the gain is adjusted to the next level. The currently active gain setting can be read in the
IGAIN[2:0] register. Once the gain has been adjusted by the GCB, the PGAG bit will be set.
The automatic Gain Control can be disabled by clearing the AGEN bit. In this case, writing the IGAIN[2:0] register will allow manual gain
control.
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NOTE
The IGAIN[2:0] register content does determine the offset compensation register access, as there are
8 individual offset register buffers implemented, accessed through the same COC[7:0] register.
4.8.3.2
Voltage sense multiplexer (voltage channel only)
A multiplexer has been implemented to select between the VSENSE or VOPT voltage input. The OPTE bit controls the multiplexer. Both
input signals are divided by a fixed DIV28 divider.
NOTE
There is no further state machine separation of the two voltage channels. The software has to assure
all compensation registers are configured properly after changing the multiplexer. Both voltage
source conversion results will be stored in the same result register.
The divided and multiplexed voltages will be routed through the optional chopper (see Section 4.8.3.5, “IIR/decimation/chopping stage")
before entering the Sigma Delta converter stage.
4.8.3.3
Sigma delta converter
Overview
4.8.3.3.1
A high resolution ADC is needed for current and battery voltage measurements of the MM912_637. A second order sigma delta modulator
based architecture is chosen.
4.8.3.4
Compensation
Following the optional chopper stage, the sigma delta bit stream is first gain and then offset compensated using the compensation
registers.
The compensation stages for both channels can be completely bypassed by clearing the CCOMP / VCOMP bits.
4.8.3.4.1
Gain compensation
Table 101 shows the gain compensation register for the current and voltage channel. At system startup, the factory trimmed values have
to be copied into the VSGC and IGCx registers (see Section 5.2, “IFR trimming content and location").
NOTE
There are 8 individual Gain compensation registers for the current measurement channels different
PGA gains with 8 individual gain trim values present in the IFR trimming flash.
Based on the voltage channel multiplexer configuration, a different trim gain compensation value has
to be used in the compensation register. The compensation register content has to be updated when
changing the multiplexer setting.
Table 101. Gain compensation - voltage and current channel
VSGC[9:0]
Voltage channel gain
Current channel gain
IGCx[9:0]
0x3FF
0x3FE
0x3FD
.
1.3174
1.3169
1.3164
.
1.7832
1.7822
1.7812
.
.
.
.
0x203
0x202
0x201
0x200 (default)
1.0694
1.0689
1.0684
1.0679
1.2872
1.2862
1.2852
1.2842
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Table 101. Gain compensation - voltage and current channel (continued)
VSGC[9:0]
Voltage channel gain
Current channel gain
IGCx[9:0]
0x1FF
0x1FE
0x1FD
.
1.0674
1.0669
1.0664
.
1.2832
1.2822
1.2812
.
.
.
.
0x002
0x001
0x000
0.8189
0.8184
0.8179
0.7862
0.7852
0.7842
4.8.3.4.2
Offset compensation
Table 102 shows the offset compensation register for the current and voltage channel. At system startup, the factory trimmed values have
to be copied into the VOC and COC registers (see Section 5.2, “IFR trimming content and location").
NOTE
Based on the voltage channel multiplexer and copper configuration, a different trim offset
compensation value has to be used in the compensation register. The compensation register content
has to be updated when changing the multiplexer setting.
While there is only one offset compensation register VOC[7:0] for the voltage channel, there are 8
individual offset compensation registers for the current channel. The access happens through the
COC[7:0] register mapped, based on the IGAIN[2:0] register content.
Table 102. Offset compensation - voltage and current channel
VOC[7:0]
(110)
(110)
Voltage channel offset
Current channel offset
COC[7:0]
0x7F
+9.073
+9.002
+8.93
.
+15.092
+14.974
+14.855
.
0x7E
0x7D
.
.
0x03
0x02
0x01
0x00 (default)
0xFF
0xFE
0xFD
.
.
.
0.214
0.143
0.071
0
+0.357
+0.238
+0.119
0
-0.071
-0.143
-0.214
.
-0.119
-0.238
-0.357
.
.
.
.
0x82
0x81
-9.002
-9.073
-14.974
-15.092
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Table 102. Offset compensation - voltage and current channel (continued)
VOC[7:0]
(110)
(110)
Voltage channel offset
Current channel offset
COC[7:0]
0x80
-9.145
-15.211
Notes
110. SD input related (mV)
4.8.3.5
IIR/decimation/chopping stage
Functional description
4.8.3.5.1
The chopper frequency is set to one eighth of the decimator frequency (512 kHz typ). On each phase, four decimation cycles are
necessary to get a steady signal. The equation of the IIR is y =.x +(1-).y .
n+1
n
n
The parameter can be configured by the IIRC[2:0] register. See Section 4.8.6.3.18, “I and V chopper control register (ACQ_CVCR (lo))".
The decimation process is then completed by a programmable (DEC[2:0]) sinc3 filter, which outputs a 0.5...8 kS/s signal. The modulated
noise is removed by an averaging filter (SINC1; L=4), which has an infinite rejection at the chopping frequency.
4.8.3.5.2
Latency and throughput
•
•
The throughput is 512 kHz/DF with DF configurable from 64 to 1024.
The latency is given by (4+3*IIR+3*Avger+N_LPF)*DF/512 kHz where:
—
—
—
IIR=1 if IIR is enabled (0 otherwise),
Avger=1 if the chopper mode is activated (0 otherwise),
N_LPF is the LPF coefficient number.
4.8.3.6
Low pass filter
To achieve the required attenuation of the measured voltage and current signals in the frequency domain, a programmable low-pass filter
following the SINC3+IIR filter, is implemented for both channels with shared configuration registers to deliver the equivalent filtering.
The following filter characteristic is implemented:
•
•
F
= 100 Hz (Att100 Hz)
PASS
F
= 500 Hz (Att500 Hz)
STOPP
The number of filter coefficients used can be programmed in the ACQ_LPFC[3:0] register. The filter can be bypassed completely clearing
the LPFEN bit.
The filter uses an algorithmic and logic unit (ALU) for calculating the filtered output data, depending on the incoming data stream at “DATA
IN” and the low-pass coefficients (A0...15) at the input “COEFF”, 16-bit width of each coefficient (See 4.8.6.3.22, “Low pass filter coefficient
Ax (LPF_Ax (hi))"). The filter structure calculates during one cycle (Tcyc=1/Fadc) the filtered data output.
Y(n)
……
+
+
+
+
+
+
……
a13
a14
a0
a15
a1
a2
-1
-1
-1
-1
-1
Z
Z
Z
Z
……
Z
X(n)
y(n) = a0.x(n)+a1.x(n-1)+a2.x(n-2)+a3.x(n-3)+a4.x(n-4)+a5.x(n-5)+a6.x(n-6)+a7.x(n-7)
+a8.x(n-8)+a9.x(n-9)+a10.x(n-10)+a11.x(n-11)+a12.x(n-12)+a13.x(n-13)+a14.x(n-14)+a15.x(n-15)
Figure 34. FIR structure
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-1
Z
Unit delay is done at a programmable frequency, depending on the decimation factor programmed in the DEC[2:0] register. See
Table 120.
NOTE
There is no decimation from SINC3 to the LPF output, LPF uses same output rate than decimator.
It's therefore possible to select an output update rate independent of the filter characteristic and
bandwidth.
The coefficient vector consists of 16*16-bit elements and is free programmable, the maximum response time for 16 coefficients structure
is 16*1/output rate. The following filter function can be realized.
M
H (z) a * zi
LP
i
i0
LP filter function
Eqn. 3
The coefficients aj are the elements of the coefficient vector and determine the filter function. M <= 16. It's possible to realize FIR filter
functions. A typical total frequency response of the decimator and the programmable LP filter is given in Figure 35.
0
0
20
40
Gtot( f)
60
80
100
100
3
4
10
100
1
10
1 10
10
f
10000
Figure 35. Typical total filter response Sinc3 (D=128), LP filter (FIR type with 15 coefficients used)
4.8.3.7
Format and clamping
The output data stream is formatted into its final size for both channels (16-Bit for Voltage and 24-Bit for Current). The current result will
contain the gain information as part of the result. See Section 4.8.6.3.12, “Current measurement result (ACQ_CURR1 / ACQ_CURR0)"
and Section 4.8.6.3.13, “Voltage measurement result (ACQ_VOLT)". Both results are written into the corresponding result registers and
will issue an IRQ if enabled.
The internal voltage measurement results (no compensation active) are clamped to maximum and minimum values of 0xFFFF and 0x0000
respectively. Terminal voltages outside this range will result in the respective max or min clamped values. The internal current
measurement results (no compensation active) are clamped to maximum and minimum values of 0x0FFFF and 0x10000 respectively.
Terminal voltages outside this range will result in the respective max or min clamped values.
NOTE
Both channels will perform synchronized conversions when enabled with a single write to the
ACQ_CTL register.
As the voltage channel is not active during low power mode, the synchronicity might not be given after
wake-up, and has to be re-established by restarting both channels.
Entering low power mode with the current / temperature channel enabled will have the channel(s)
remain active during low power mode.
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4.8.4
Temperature measurement channel
The MM912_637 can measure the temperature from an internal built-in temperature sensor, or from an external temperature sensor
connected to the VTEMP pin. The external temperature sensor is supplied via the TSUP pin. The measurement channel is the same for
the internal and external temperature sensor.
The temperature measurement channel uses the same Sigma Delta (SD) converter implementation as the current and voltage channel,
followed by a fixed decimation (L=128). A selectable chopper mode is implemented to compensate for offset errors. Once the chopper is
enabled, an average (sinc1, L=2) is active.
Once the measurement is enabled, the temperature result registers are updated with the channel update rate. When both measurements
are enabled, both temperature sensors are measured successively where the measurement is started with the internal sensor.
The internal temperature measurement result (no compensation active) of 0x0000 represents 0K, the maximum 0xFFFF = 523K (typ).
The result data is stored into the result registers ACQ_ITEMP and ACQ_ETEMP (both 16-bit). During an over range event, the ADC is
limited to the maximum value. The result of the internal temperature measurement is utilized to generate the calibration request. See
Section 4.8.5, “Calibration".
4.8.4.1
Compensation
The compensation for the temperature channels is implemented similar to the current and voltage channel.
Table 103. Gain compensation - temperature channel
ITGC[7:0]
Temperature channel gain compensation
ETGC[7:0]
0xFF
1.124
1.123
1.122
.
0xFE
0xFD
.
.
0x83
0x82
0x81
0x80 (default)
0x7F
0x7E
0x7D
.
.
1.003
1.002
1.001
1.000
0.999
0.998
0.997
.
.
.
0x02
0x01
0x00
0.877
0.876
0.875
Table 104. Offset compensation - temperature channel(111)
ITOC[7:0]
(112)
Temperature channel offset compensation
ETOC[7:0]
0x7F
+9.689
+9.613
+9.537
0x7E
0x7D
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Table 104. Offset compensation - temperature channel(111)
ITOC[7:0]
(112)
Temperature channel offset compensation
ETOC[7:0]
.
.
.
.
0x03
0x02
0x01
0x00 (default)
0xFF
0xFE
0xFD
.
+0.229
+0.153
+0.076
0
-0.076
-0.153
-0.229
.
.
.
0x82
0x81
0x80
-9.613
-9.689
-9.766
Notes
111. Typical values based on default gain setting
112. SD input related (mV)
NOTE
Factory trimmed compensation values are only available for the internal temperature channel.
4.8.5
Calibration
To ensure the maximum precision of the current and voltage sense module, several stages of calibration are implemented to compensate
temperature effects. The calibration concept combines the availability of FLASH and the temperature information to guarantee the
measurement accuracy under all functional conditions. The trimming and calibration procedures are split in three different categories:
Power On-, Calibration Request-, and Optional Verification Procedures.
4.8.5.1
System power on procedure
Several device parameters are guaranteed with full precision after system trimming only. During final test of the device, trim values are
computed, verified, and stored into the system FLASH memory. To ensure optimum system performance, the following power on
procedure has to be performed during power on. As the device is typically constantly powered during its operation, this operation has to
be performed typically one time only. During a system power loss or low power reset condition, the application software has to ensure the
procedure executes again.
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Power On
Procedure
(One time only)
Startup Trimming
Bandgap Trim (BG1,2,3)
LIN Slope Trim
LVT Trim
LPOSC Trim
Build Gain Compensation
Reference Table
Build Current Channel GC
Look Up table
Build VSENSE Channel GC
Look Up table
Build VOpt Channel GC
Look Up table
Startup Calibration
VSENSE / VOPT Channel
Offset Compensation1
ITEMP Channel Offset
Compensation
ITEMP Channel Gain
Compensation
PGA Auto Zero Sequence
Current / Voltage Channel
Gain Comp. based on
ITEMP and LookUp Table
Current Channel Offset
Compensation procedure2
Program Calibration IRQ
Temperature Thresholds
1: Based on first channel used
2: In case copper mode is not used
Figure 36. Power on procedure
4.8.5.1.1
Startup trimming
To ensure all analog die modules are being trimmed properly, the following FLASH information (located in the MCU IFR from 0x01_80D0
to 0x01_80D9) has to be copied to the analog die register 0xE0 to 0xE9. This trimming includes the Band Gap Reference adjustment for
the 3 system Band Gap circuits, The LIN slope adjustment (TRIM_LIN), the Low Voltage Threshold (TRIM_LVT), and the Low Power
Oscillator (TRIM_OSC). See Section 5, “MM912_637 - trimming".
NOTE
The LPOSC[12:0] trim will adjust the low power oscillator to its specified accuracy. This will result in
the dependent Watchdog timing to be accurate after writing the trimming information.
4.8.5.1.2
Gain compensation look up table
In order to prepare the system for the optional calibration interrupt service during operation, it is be beneficial to create a look up table for
the voltage and current channel gain compensation over temperature.
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For all current and voltage channel gain buffers, there are corresponding ROOM temperature optimum trim values stored in the IFR
FLASH. For HOT (125 °C) and COLD (-40 °C) temperature, the adjustment towards the ROOM value is stored.
Table 105. Gain compensation buffer optimum
OFFSET
HEX
Byte description
Global
address
Content
DEC
00
01
02
03
04
05
06
07
08
09
10
11
7
6
5
4
3
2
1
0
0x01_80C0
0x01_80C1
0x01_80C2
0x01_80C3
0x01_80C4
0x01_80C5
0x01_80C6
0x01_80C7
0x01_80C8
0x01_80C9
0x01_80CA
0x01_80CB
0x01_80CC
0x01_80CD
0x01_80CE
0x01_80CF
0x01_80DE
0x01_80DF
0x01_80E0
0x01_80E1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
1E
1F
20
21
IGC4[9:8]
Current Channel Gain (4) Compensation - Room Temp
Current Channel Gain (8) Compensation - Room Temp
IGC4[7:0]
IGC8[7:0]
IGC8[9:8]
IGC16[9:8]
IGC32[9:8]
IGC64[9:8]
IGC128[9:8]
IGC256[9:8]
IGC512[9:8]
VSGC[9:8]
VOGC[9:8]
Current Channel Gain (16) Compensation - Room
Temp
IGC16[7:0]
IGC32[7:0]
IGC64[7:0]
IGC128[7:0]
IGC256[7:0]
IGC512[7:0]
VSGC[7:0]
VOGC[7:0]
Current Channel Gain (32) Compensation - Room
Temp
Current Channel Gain (64) Compensation - Room
Temp
Current Channel Gain (128) Compensation - Room
Temp
12
13
14
15
30
31
32
33
Current Channel Gain (256) Compensation - Room
Temp
Current Channel Gain (512) Compensation - Room
Temp
VSENSE Channel Gain Compensation - Room Temp
VOPT Channel Gain Compensation - Room Temp
VSENSE Channel Gain Compensation - COLD
0x01_80EC
0x01_80ED
2C
2D
44
45
COMP_VSG_COLD[7:0]
COMP_VSG_HOT[7:0]
(113)
Temp
VSENSE Channel Gain Compensation - HOT
(113)
Temp
(113)
0x01_80EE
0x01_80EF
2E
2F
46
47
COMP_VOG_COLD[7:0]
COMP_VOG_HOT[7:0]
VOPT Channel Gain Compensation - COLD Temp
(113)
VOPT Channel Gain Compensation - HOT Temp
Current Channel Gain (4) Compensation - COLD
0x01_80F0
0x01_80F1
0x01_80F2
0x01_80F3
0x01_80F4
0x01_80F5
30
31
32
33
34
35
48
49
50
51
52
53
IGC4_COLD[7:0]
IGC4_HOT[7:0]
IGC8_COLD[7:0]
IGC8_HOT[7:0]
IGC16_COLD[7:0]
IGC16_HOT[7:0]
(113)
Temp
Current Channel Gain (4) Compensation - HOT
(113)
Temp
Current Channel Gain (8) Compensation - COLD
(113)
Temp
Current Channel Gain (8) Compensation - HOT
(113)
Temp
Current Channel Gain (16) Compensation - COLD
(113)
Temp
Current Channel Gain (16) Compensation - HOT
(113)
Temp
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Table 105. Gain compensation buffer optimum (continued)
OFFSET
Byte description
Global
address
Content
HEX
DEC
7
6
5
4
3
2
1
0
Current Channel Gain (32) Compensation - COLD
0x01_80F6
0x01_80F7
0x01_80F8
0x01_80F9
0x01_80FA
0x01_80FB
0x01_80FC
0x01_80FD
0x01_80FE
36
37
38
39
3A
3B
3C
3D
3E
3F
54
IGC32_COLD[7:0]
IGC32_HOT[7:0]
IGC64_COLD[7:0]
IGC64_HOT[7:0]
IGC128_COLD[7:0]
IGC128_HOT[7:0]
IGC256_COLD[7:0]
IGC256_HOT[7:0]
IGC512_COLD[7:0]
IGC512_HOT[7:0]
(113)
Temp
Current Channel Gain (32) Compensation - HOT
55
56
57
58
59
60
61
62
63
(113)
Temp
Current Channel Gain (64) Compensation - COLD
(113)
Temp
Current Channel Gain (64) Compensation - HOT
(113)
Temp
Current Channel Gain (128) Compensation - COLD
(113)
Temp
Current Channel Gain (128) Compensation - HOT
(113)
Temp
Current Channel Gain (256) Compensation - COLD
(113)
Temp
Current Channel Gain (256) Compensation - HOT
(113)
Temp
Current Channel Gain (512) Compensation - COLD
(113)
Temp
Current Channel Gain (512) Compensation - HOT
0x01_80FF
Notes
(113)
Temp
113. 7-Bit character with bit 7 (MSB) as sign (0 = “+”; 1 = “-”) with the difference to the corresponding room temperature value (e.g. 10000010 = “-2”).
To create the look up table, a linear interpolation of the gain adjustment has to be done between the three given temperatures, based on
the temperature step width specified (TCALSTEP).
HOT
+x
+2
+1
0
ROOM
-1
-2
-x
COLD
Figure 37. Look up table creation
4.8.5.1.3
Startup calibration
The power on trimming / calibration procedure is finalized by performing the start up calibration.
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4.8.5.1.3.1 VSENSE/VOPT channel offset compensation and ITEMP channel gain/offset
compensation
Copying the default compensation values, according to Table 106, will establish the optimum offset compensation for the VSENSE and
VOPT channels, as well as the optimum gain and offset compensation for the internal temperature sensor.
Table 106. Voltage/temp trim
OFFSET
Byte description
Target register
Name
Global
Address
HEX
DEC
26
7
6
5
4
3
2
1
0
Offset
(114)
0x01_80DA
0x01_80DB
0x01_80DC
0x01_80DD
0x01_80E2
0x01_80E3
1A
1B
1C
1D
22
23
VOC_S[7:0]
VOC_O[7:0]
COMP_VO
COMP_VO
COMP_VO
COMP_VO
COMP_ITO
COMP_ITG
0xAA
0xAA
0xAA
0xAA
(114)
(114)
(114)
27
28
VOC_S_CHOP[7:0] (Chopper Mode)
VOC_O_CHOP[7:0] (Chopper Mode)
ITO[7:0]
29
34
0xD0
0xD1
35
ITG[7:0]
Notes
114. Based on the selection of the voltage measurement source (VSENSE or VOPT) and the activation of chopper mode. VOC_S is for VSENSE with
Chopper mode OFF, VOC_O for VOPT with Chopper mode OFF, VOC_S_CHOP for VSENSE with Chopper mode ON, VOC_O_CHOP for VOPT
with Chopper mode ON.
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4.8.5.1.3.2 PGA auto zero sequence
The following procedure has to be performed for the PGA (Programmable Gain Amplifier) Auto Zero (AZ).
1. Write a “1” to the PGAO bit and its mask in the COMP_CTL register (0xA0)
2. Approximately 6.5 ms later, PGAOF will become set at to “1” (Flag needs to be polled)
3. Exit the PGAO mode by writing “0” in PGA0 and its mask being a “1”
4. Clear the PGAOF flag by writing “1”
NOTE
The new offset compensation data can be observed in the (PGAOC4...512[10:0]) registers.
The sequence will require 3352 clock cycles of the D2DFCLK (512kHz), typically 6.5 ms.
4.8.5.1.3.3 Current and voltage channel gain compensation based on ITEMP from look up
table
After the first reading of the temperature channel measurement, the current and voltage channel gain compensation buffers must be
written with the corresponding look up table value (see Section 4.8.5.1.2, “Gain compensation look up table").
4.8.5.1.3.4 Current channel offset compensation procedure (chopper off only)
If the chopper feature is not used for the current measurement channel, the offset should be compensated using the following procedure
with the highest decimation selected and the LPF active.
Short PGA inputs
PGAZ(M) = 1
Start regular SD Current Channel
Conversion with Compensation
disabled (CCOMP(M) = 0)
Wait for conversion complete IRQ
and adjust offset compensation
buffers with result.
Figure 38. Current channel offset compensation sequence
4.8.5.1.3.5 Program calibration IRQ temperature thresholds
To finalize the startup sequence, the new temperature limits must be programmed into the Calibration Temperature Limits (TCMAX[15:0]
and TCMIN[15:0]), and the Calibration Request interrupt must be enabled.
4.8.5.2
Calibration request procedure
During normal system operation (in Normal and Low Power mode), a calibration request interrupt / wake-up will indicate the device
temperature changed outside the range for the programmed Current and Voltage Channel Gain Compensation.
During a calibration request interrupt (wake-up), the Current and Voltage Channel Gain Compensation buffers have to be updated with
the corresponding values stored in the look up table created upon system start up (see Section 4.8.5.1.2, “Gain compensation look up
table"). The the new temperature limits must be programmed into the Calibration Temperature Limits (TCMAX[15:0] and TCMIN[15:0])
before leaving the interrupt service routine.
4.8.5.3
Verification procedures
As an optional feature, upon application requirement, the proper function of the current and voltage measurement channels can be verified
by connecting a special calibration reference to the input of the channels.
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Connect Calibration Reference to
Channel Inputs
(DIAGI(M) = DIAGV(M) = 1)
Start regular SD Conversion.
Wait for conversion complete IRQ.
Verify result based on the reference
measurements
Disconnect Calibration Reference to
Channel Inputs
(DIAGI(M) = DIAGV(M) = 0)
Table 107 shows the location of the diagnostic reference measurements.
Note: This table is unpopulated for Analog Option 1 devices.
Table 107. Diagnostic measurement flash location
OFFSET
Global
Byte description
Address
HEX
24
DEC
36
7
6
5
4
3
2
1
0
0x01_80E4
0x01_80E5
0x01_80E6
0x01_80E7
0x01_80E8
0x01_80E9
0x01_80EA
BG3 diag measurement from Vsense channel after cal at room
BG3 diag measurement from Vopt channel after cal at room
25
37
26
38
27
39
28
40
29
41
BG3 diag measurement from I channel (gain4) at room
2A
42
4.8.6
Memory map and registers
Overview
4.8.6.1
This section provides a detailed description of the memory map and registers.
4.8.6.2
Module memory map
The memory map for the Acquisition, Compensation, and LPF module is given in Table 63.
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Table 108. Module memory map
Offset
Name
7
6
5
4
3
2
1
0
(115)(116)
R
W
R
0
0
0
0
0
0
0
0
AHCRM
0
OPTEM
OPENEM CVMIEM ETMENM ITMENM
VMENM
CMENM
ACQ_CTL
0x58
Acquisition control register
OPTE
PGAG
OPENE
VMOW
CVMIE
ETMEN
ITMEN
ITM
VMEN
VM
CMEN
CM
W
R
AHCR
AVRF
ACQ_SR (hi)
0x5A
CMOW
ETM
Acquisition status register
W
R
Write 1 will clear the flags
ACQ_SR (lo)
0x5B
OPEN
0
0
0
0
0
VTH
ETCHOP
ITCHOP
VCHOP
CCHOP
Acquisition status register
W
R
0
0
0
0
0
ETCHOP
M
CVCHOP
M
W
TCOMPM VCOMPM CCOMPM LPFENM
ITCHOPM
AGENM
ACQ_ACC1
0x5C
Acquisition chain control 1
R
W
R
TCOMP
VCOMP
CCOMP
0
LPFEN
0
ETCHOP
ITCHOP
CVCHOP
AGEN
0
0
0
0
0
0
W
R
ZEROM
ECAPM
TADCGM VADCGM CADCGM
TDENM
VDENM
CDENM
ACQ_ACC0
0x5E
Acquisition chain control 0
ZERO
0
ECAP
0
TADCG
0
VADCG
0
CADCG
0
TDEN
VDEN
CDEN
W
R
ACQ_DEC
0x60
DEC[2:0]
BG2EN
Decimation Rate
W
R
ACQ_BGC
0x61
0
0
0
0
BG3EN
BG1EN
BGADC[1:0]
BGLDO
0
BandGap control
W
R
ACQ_GAIN
0
0
0x62
IGAIN[2:0]
PGA gain
W
R
ACQ_GCB
0x63
D[7:0]
GCB threshold
W
R
ACQ_ITEMP (hi)
0x64
ITEMP[15:8]
ITEMP[7:0]
EEMP[15:8]
Internal temp. measurement result
W
R
ACQ_ITEMP (lo)
0x65
Internal temp. measurement result
W
R
ACQ_ETEMP (hi)
0x66
0x67
External temp. measurement
result
W
R
ACQ_ETEMP (lo)
EEMP[7:0]
External temp. measurement
result
W
R
W
R
0
0
0
0
0
0
0
0
0x68
0x69
Reserved
ACQ_CURR1
CURR[23:16]
CURR[15:8]
CURR[7:0]
Current measurement result
W
R
W
R
ACQ_CURR0
Current measurement result
0x6A
W
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Table 108. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(115)(116)
R
VOLT[15:8]
W
R
ACQ_VOLT
Voltage measurement result
0x6C
VOLT[7:0]
W
R
ACQ_LPFC
0
0
0
0
0
0
0
0
0x6E
0x6F
LPFC[3:0]
Low pass filter coefficient number
W
R
0
0
0
0
Reserved
W
R
ACQ_TCMP
Low power trigger current
measurement period
W
R
0x70
0x72
TCMP[15:0]
THF[7:0]
W
R
ACQ_THF
Low power current threshold
filtering period
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
Reserved
ACQ_CVCR (hi)
I and V chopper control register
ACQ_CVCR (lo)
0
0
W
R
DBTM[1:0]
DBT[1:0]
IIRCM[2:0]
PGAFM
IIRC[2:0]
PGAF
I and V chopper control register
ACQ_CTH
W
R
CTH[7:0]
Low power current threshold
W
R
0
0
0
0
0
0
0
0
0
Reserved
W
R
ACQ_AHTH1 (hi)
Low power Ah counter threshold
ACQ_AHTH1 (lo)
W
R
AHTH[30:16]
AHTH[15:0]
Low power Ah counter threshold
ACQ_AHTH0 (hi)
W
R
Low power Ah counter threshold
ACQ_AHTH0 (lo)
W
R
Low power Ah counter threshold
ACQ_AHC1 (hi)
W
R
AHC[31:24]
AHC[23:16]
AHC[15:8]
AHC[7:0]
Low power Ah counter
ACQ_AHC1 (lo)
W
R
Low power Ah counter
ACQ_AHC0 (hi)
W
R
Low power Ah counter
ACQ_AHC0 (lo)
W
R
Low power Ah counter
LPF_A0 (hi)
W
R
A0 filter coeff
W
R
A0[15:0]
LPF_A0 (lo)
A0 filter coeff
W
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Table 108. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(115)(116)
LPF_A1 (hi)
A1 filter coeff
LPF_A1 (lo)
A1 filter coeff
LPF_A2 (hi)
A2 filter coeff
LPF_A2 (lo)
A2 filter coeff
LPF_A3 (hi)
A3 filter coeff
LPF_A3 (lo)
A3 filter coeff
LPF_A4 (hi)
A4 filter coeff
LPF_A4 (lo)
A4 filter coeff
LPF_A5 (hi)
A5 filter coeff
LPF_A5 (lo)
A5 filter coeff
LPF_A6 (hi)
A6 filter coeff
LPF_A6 (lo)
A6 filter coeff
LPF_A7 (hi)
A7 filter coeff
LPF_A7 (lo)
A7 filter coeff
LPF_A8 (hi)
A8 filter coeff
LPF_A8 (lo)
A8 filter coeff
LPF_A9 (hi)
A9 filter coeff
LPF_A9 (lo)
A9 filter coeff
LPF_A10 (hi)
A10 filter coeff
LPF_A10 (lo)
A10 filter coeff
LPF_A11 (hi)
A11 filter coeff
LPF_A11 (lo)
A11 filter coeff
R
W
R
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
A1[15:0]
A2[15:0]
A3[15:0]
A4[15:0]
A5[15:0]
A6[15:0]
A7[15:0]
A8[15:0]
A9[15:0]
A10[15:0]
A11[15:0]
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
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Table 108. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(115)(116)
LPF_A12 (hi)
A12 filter coeff
LPF_A12 (lo)
A12 filter coeff
LPF_A13 (hi)
A13 filter coeff
LPF_A13 (lo)
A13 filter coeff
LPF_A14 (hi)
A14 filter coeff
LPF_A14 (lo)
A14 filter coeff
LPF_A15 (hi)
A15 filter coeff
LPF_A15 (lo)
A15 filter coeff
R
W
R
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
A12[15:0]
A13[15:0]
A14[15:0]
A15[15:0]
W
R
W
R
W
R
W
R
W
R
W
R
W
R
0
0
0
0
0
0
0
W
R
BGCALM[1:0]
PGAZM
PGAOM
DIAGVM
DIAGIM
CALIEM
CALIE
COMP_CTL
Compensation control register
0xA0
BGCAL[1:0]
PGAZ
0
PGAO
DIAGV
0
DIAGI
0
W
R
COMP_SR
Compensation status register
COMP_TF
0
0
BGRF
PGAOF
0
CALF
0xA2
0xA3
W
R
Write 1 will clear the flags
0
0
0
0
TMF[2:0]
Temperature filtering period
W
R
W
R
COMP_TMAX
Max temp before recalibration
0xA4
0xA6
TCMAX[15:0]
TCMIN[15:0]
W
R
W
R
COMP_TMIN
Min temp before recalibration
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xA8
0xA9
0xAA
Reserved
Reserved
W
R
W
R
COMP_VO
Offset voltage compensation
COMP_IO
VOC[7:0]
COC[7:0]
W
R
0xAB
0xAC
Offset current compensation
window
W
R
W
R
0
0
0
0
0
0
VSGC[9:8]
COMP_VSG
Gain voltage comp. vsense
channel
VSGC[7:0]
W
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Table 108. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(115)(116)
R
0
0
0
0
0
0
0
0
0xAE
0xAF
Reserved
Reserved
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
IGC4[9:8]
IGC8[9:8]
IGC16[9:8]
IGC32[9:8]
IGC64[9:8]
W
R
COMP_IG4
Gain current compensation 4
0xB0
0xB2
0xB4
0xB6
0xB8
0xBA
0xBC
0xBE
0xC0
0xC2
IGC4[7:0]
IGC8[7:0]
IGC16[7:0]
IGC32[7:0]
IGC64[7:0]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
COMP_IG8
Gain current compensation 8
W
R
W
R
COMP_IG16
Gain current compensation 16
W
R
W
R
COMP_IG32
Gain current compensation 32
W
R
W
R
COMP_IG64
Gain current compensation 64
W
R
IGC128[9:8]
IGC256[9:8]
IGC512[9:8]
W
R
COMP_IG128
Gain current compensation 128
IGC128[7:0]
W
R
0
0
W
R
COMP_IG256
Gain current compensation 256
IGC256[7:0]
W
R
0
0
W
R
COMP_IG512
Gain current compensation 512
IGC512[7:0]
W
R
0
0
PGAOC4[10:8]
W
R
COMP_PGAO4
Offset PGA compensation 4
PGAOC4[7:0]
W
R
0
0
PGAOC8[10:8]
W
R
COMP_PGAO8
Offset PGA compensation 8
PGAOC8[7:0]
W
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Table 108. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(115)(116)
R
0
0
0
0
0
PGAOC16[10:8]
W
R
COMP_PGAO16
Offset PGA compensation 16
0xC4
0xC6
0xC8
0xCA
0xCC
0xCE
PGAOC16[7:0]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PGAOC32[10:8]
PGAOC64[10:8]
PGAOC128[10:8]
PGAOC256[10:8]
PGAOC512[10:8]
W
R
COMP_PGAO32
Offset PGA compensation 32
PGAOC32[7:0]
W
R
0
0
W
R
COMP_PGAO64
Offset PGA compensation 64
PGAOC64[7:0]
W
R
0
0
W
R
COMP_PGAO128
Offset PGA compensation 128
PGAOC128[7:0]
W
R
0
0
W
R
COMP_PGAO256
Offset PGA compensation 256
PGAOC256[7:0]
W
R
0
0
W
R
COMP_PGAO512
Offset PGA compensation 512
PGAOC512[7:0]
ITOC[7:0]
W
R
COMP_ITO
Internal temp. offset compensation
COMP_ITG
0xD0
0xD1
W
R
ITGC[7:0]
Internal temp. gain compensation
COMP_ETO
W
R
0xD2
ETOC[7:0]
ETGC[7:0]
External temp. offset
compensation
W
COMP_ETG
R
W
R
0xD3
0xD4
0xD5
0xD6
0xD7
External temp. gain compensation
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
W
R
W
R
W
R
W
Notes
115. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
116. Register Offset with the “lo” address value not shown have to be accessed in 16Bit mode. 8 Bit access will not function.
4.8.6.3
Register descriptions
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This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.8.6.3.1
Acquisition control register (ACQ_CTL)
Table 109. Acquisition control register (ACQ_CTL)
Offset
Access: User read/write
0x58
(117),(118)
15
0
14
13
12
11
10
9
0
8
0
R
W
0
0
0
0
0
AHCRM
OPTEM
OPENEM
CVMIEM
ETMENM
ITMENM
VMENM
CMENM
Reset
0
0
6
0
5
0
4
0
3
0
2
0
1
0
0
7
R
W
0
AHCR
0
OPTE
0
OPENE
0
CVMIE
0
ETMEN
0
ITMEN
0
VMEN
0
CMEN
0
Reset
Notes
117. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
118. This Register is 16-Bit access only.
Table 110. Acquisition control register (ACQ_CTL) - register field descriptions
Field
Description
Ampere Hour Counter Reset - Mask
0 - writing the AHCR Bit will have no effect
1 - writing the AHCR Bit will be effective
15
AHCRM
Optional Voltage Sense Enable - Mask
0 - writing the OPTE Bit will have no effect
1 - writing the OPTE Bit will be effective
14
OPTEM
Enable Shunt Resistor Open Detection - Mask
0 - writing the OPENE Bit will have no effect
1 - writing the OPENE Bit will be effective
13
OPENEM
Current / Voltage Measurement Interrupt Enable - Mask
0 - writing the CVMIE Bit will have no effect
1 - writing the CVMIE Bit will be effective
12
CVMIEM
External Temperature Measurement Enable - Mask
0 - writing the ETMEN Bit will have no effect
1 - writing the ETMEN Bit will be effective
11
ETMENM
Internal Temperature Measurement Enable - Mask
0 - writing the ITMEN Bit will have no effect
1 - writing the ITMEN Bit will be effective
10
ITMENM
Voltage Measurement Enable - Mask
0 - writing the VMEN Bit will have no effect
1 - writing the VMEN Bit will be effective
9
VMENM
Current Measurement Enable - Mask
0 - writing the CMEN Bit will have no effect
1 - writing the CMEN Bit will be effective
8
CMENM
Ampere Hour Counter Reset, this write only bit will reset the ACQ_AHC register.
0 - no effect
1 - ACQ_AHC reset to 0x00000000
7
AHCR
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Table 110. Acquisition control register (ACQ_CTL) - register field descriptions (continued)
Field
Description
Optional Voltage Sense Enable (Voltage Channel Multiplexer Control)
0 - VSENSE routed to ADC
1 - VOPT routed to ADC
6
OPTE
Enable Shunt Resistor Open Detection
0 - Shunt resistor open detection disabled, the OPEN bit must be ignored
1 - Shunt resistor open detection enabled, OPEN bit will indicate status
5
OPENE
Current / Voltage Measurement Interrupt Enable
0 - current and voltage measurement interrupt disabled
1 - current and voltage measurement interrupt enabled
4
CVMIE
External Temperature Measurement Enable
0 - external temperature measurement disabled
1 - external temperature measurement enabled
3
ETMEN
Internal Temperature Measurement Enable
0 - internal temperature measurement disabled
1 - internal temperature measurement enabled
2
ITMEN
Voltage Measurement Enable
0 - voltage measurement disabled
1 - voltage measurement enabled
1
VMEN
Current Measurement Enable
0 - current measurement disabled
1 - current measurement enabled
0
CMEN
4.8.6.3.2
Acquisition status register (ACQ_SR (hi))
Table 111. Acquisition status register (ACQ_SR (hi))
(119)
Offset
Access: User read/write
0x5A
7
6
5
4
3
2
1
0
R
AVRF
PGAG
VMOW
CMOW
ETM
ITM
VM
CM
W
Write 1 will clear the flags
Reset
0
0
0
0
0
0
0
0
Notes
119. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 112. Acquisition status register (ACQ_SR (hi)) - register field descriptions
Field
Description
VDDA Low Voltage Reset Flag. Writing this bit to logic 1 will clear the flag.
0 - n.a.
1 - Last reset was caused by a low voltage condition at the VDDA regulator.
7
AVRF
(120)
PGA Gain Change Flag
. Writing this bit to logic 1 will clear the flag.
6
0 - PGA gain has not changed since last flag clear
1 - PGA gain has changed since last flag clear
PGAG
(120)
Voltage Measurement Result Overwritten
. Writing this bit to logic 1 will clear the flag.
5
(121)
0 - Voltage measurement result register VOLT[15:0] not overwritten
1 - Voltage measurement result register VOLT[15:0] overwritten
since last VMOW flag clear
since last VMOW flag clear
VMOW
(121)
(120)
Current Measurement Result Overwritten
. Writing this bit to logic 1 will clear the flag.
4
(121)
0 - Current measurement result register CURR[15:0] not overwritten
1 - Current measurement result register CURR[15:0] overwritten
since last CMOW flag clear
since last CMOW flag clear
CMOW
(121)
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Table 112. Acquisition status register (ACQ_SR (hi)) - register field descriptions (continued)
Field
Description
(120)
End of Measurement - External Temperature
. Writing this bit to logic 1 will clear the flag.
3
ETM
0 - No external temperature measurement completed since last ETM clear
1 - External temperature measurement completed since last ETM clear
(120)
End of Measurement - Internal Temperature
. Writing this bit to logic 1 will clear the flag.
2
ITM
0 - No internal temperature measurement completed since last ITM clear
1 - Internal temperature measurement completed since last ITM clear
End of Measurement - Voltage. Writing this bit to logic 1 will clear the flag.
0 - No voltage measurement completed since last VM clear
1 - Voltage measurement completed since last VM clear
1
VM
End of Measurement - Current. Writing this bit to logic 1 will clear the flag.
0 - No current measurement completed since last CM clear
1 - Current measurement completed since last CM clear
0
CM
Notes
120. No Interrupts issued for those flags
121. Overwritten - new result latched before previous result was read
4.8.6.3.3
Acquisition status register (ACQ_SR (lo))
Table 113. Acquisition status register (ACQ_SR (lo))
(122)
Offset
Access: User read
0x5B
7
6
0
5
0
4
3
2
1
0
R
OPEN
VTH
ETCHOP
ITCHOP
VCHOP
CCHOP
W
Notes
122. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 114. Acquisition status register (ACQ_SR (lo)) - register field descriptions
Field
Description
Shunt Resistor Open Detection Status (Normal mode only, only functional if OPENE=1)
0 - Shunt resistor detected
1 - Shunt resistor disconnected
7
OPEN
Digital Voltage High Threshold Reached
0 - Voltage measurement result for VSENSE / VOPT below V (0xDAC0: equivalent to 28 V at 0.5 mV LSB weighing)
1 - Voltage measurement result for VSENSE / VOPT above or equal V (0xDAC0: equivalent to 28 V at 0.5 mV LSB weighing)
4
VTH
TH
TH
Chopping Active Status - External Temperature
0 - Chopper for external temperature measurement disabled
1 - Chopper for external temperature measurement enabled
3
ETCHOP
Chopping Active Status - Internal Temperature
0 - Chopper for internal temperature measurement disabled
1 - Chopper for internal temperature measurement enabled
2
ITCHOP
Chopping Active Status - Voltage
0 - Chopper for voltage measurement disabled
1 - Chopper for voltage measurement enabled
1
VCHOP
Chopping Active Status - Current
0 - Chopper for current measurement disabled
1 - Chopper for current measurement enabled
0
CCHOP
4.8.6.3.4
Acquisition chain control 1 (ACQ_ACC1)
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Table 115. Acquisition chain control 1 (ACQ_ACC1)
Offset
Access: User read/write
0x5C
(123)(124)
15
0
14
13
12
11
10
9
8
R
W
0
0
0
0
0
0
0
TCOMPM
VCOMPM
CCOMPM
LPFENM
ETCHOPM
ITCHOPM
CVCHOPM
AGENM
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
TCOMP
1
VCOMP
1
CCOMP
1
LPFEN
0
ETCHOP
0
ITCHOP
0
CVCHOP
0
AGEN
1
Reset
Notes
123. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
124. This Register is 16 Bit access only.
Table 116. Acquisition chain control 1 (ACQ_ACC1) - register field descriptions
Field
Description
Temperature Measurement Channel - Compensation Enable - Mask
0 - writing the TCOMP bit will have no effect
1 - writing the TCOMP bit will be effective
15
TCOMPM
Voltage Measurement Channel - Compensation Enable - Mask
0 - writing the VCOMP bit will have no effect
1 - writing the VCOMP bit will be effective
14
VCOMPM
Current Measurement Channel - Compensation Enable - Mask
0 - writing the CCOMP bit will have no effect
1 - writing the CCOMP bit will be effective
13
CCOMPM
LPF Enable - Mask
0 - writing the LPFEN bit will have no effect
1 - writing the LPFEN bit will be effective
12
LPFENM
Chopping Enable - External Temperature Measurement Channel - Mask
0 - writing the ETCHOP bit will have no effect
1 - writing the ETCHOP bit will be effective
11
ETCHOPM
Chopping Enable - Internal Temperature Measurement Channel - Mask
0 - writing the ITCHOP bit will have no effect
1 - writing the ITCHOP bit will be effective
10
ITCHOPM
Chopping Enable - Voltage Measurement Channel - Mask
0 - writing the CVCHOP bit will have no effect
1 - writing the CVCHOP bit will be effective
9
CVCHOPM
Automatic Gain Control Enable - Mask
0 - writing the AGEN bit will have no effect
1 - writing the AGEN bit will be effective
8
AGENM
Temperature Measurement Channel - Compensation Enable
0 - Temperature measurement channel offset and gain compensation disabled
1 - Temperature measurement channel offset and gain compensation enabled
7
TCOMP
Voltage Compensation Enable
0 - Voltage measurement channel offset and gain compensation disabled
1 - Voltage measurement channel offset and gain compensation enabled
6
VCOMP
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Table 116. Acquisition chain control 1 (ACQ_ACC1) - register field descriptions (continued)
Field
Description
Current Compensation Enable
0 - Current measurement channel offset and gain compensation disabled
1 - Current measurement channel offset and gain compensation enabled
5
CCOMP
LPF Enable
4
0 - Low pass filter for current and voltage channel disabled
1 - Low pass filter for current and voltage channel enabled
LPFEN
Chopping Enable - External Temperature
0 - Chopper mode for external temperature measurement disabled
1 - Chopper mode for external temperature measurement enabled
3
ETCHOP
Chopping Enable - Internal Temperature
0 - Chopper mode for internal temperature measurement disabled
1 - Chopper mode for internal temperature measurement enabled
2
ITCHOP
Chopping Enable - Voltage
0 - Chopper mode for voltage and current measurement disabled
1 - Chopper mode for voltage and current measurement enabled
1
CVCHOP
Automatic Gain Control Enable
0 - Automatic gain control disabled (manual gain control via IGAIN[2:0])
1 - Automatic gain control enabled
0
AGEN
4.8.6.3.5
Acquisition chain control 0 (ACQ_ACC0)
Table 117. Acquisition chain control 0 (ACQ_ACC0)
Offset
Access: User read/write
0x5E
(125),(126)
15
0
14
13
12
11
10
9
0
8
0
R
W
0
0
0
0
0
ZEROM
ECAPM
TADCGM
VADCGM
CADCGM
TDENM
VDENM
CDENM
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
ZERO
0
ECAP
0
TADCG
1
VADCG
1
CADCG
1
TDEN
0
VDEN
0
CDEN
0
Reset
Notes
125. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
126. This Register is 16 Bit access only.
Table 118. Acquisition chain control 0 (ACQ_ACC0) - register field descriptions
Field
Description
Current and Voltage Sigma Delta Input Short - Mask
0 - writing the ZERO bit will have no effect
1 - writing the ZERO bit will be effective
15
ZEROM
TSUP External Capacitor - Mask
0 - writing the ECAP bit will have no effect
1 - writing the ECAP bit will be effective
14
ECAPM
Temperature ADC Gain Select - Mask
0 - writing the TADCG bit will have no effect
1 - writing the TADCG bit will be effective
13
TADCGM
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Table 118. Acquisition chain control 0 (ACQ_ACC0) - register field descriptions
Field
Description
Voltage ADC Gain Select - Mask
0 - writing the VADCG bit will have no effect
1 - writing the VADCG bit will be effective
12
VADCGM
Current ADC Gain Select - Mask
0 - writing the CADCG bit will have no effect
1 - writing the CADCG bit will be effective
11
CADCGM
100ns Clock delay - Internal Temperature - Mask
0 - writing the TDEN bit will have no effect
1 - writing the TDEN bit will be effective
10
TDENM
100ns Clock delay - Voltage - Mask
0 - writing the VDEN bit will have no effect
1 - writing the VDEN bit will be effective
9
VDENM
100ns Clock delay - Current - Mask
0 - writing the CDEN bit will have no effect
1 - writing the CDEN bit will be effective
8
CDENM
Current and Voltage Sigma Delta Input Short (to perform Offset Compensation measurement)
0 - Sigma delta inputs not shorted
1 - Current and voltage sigma delta inputs shorted
7
ZERO
TSUP External Capacitor select
0 - TSUP frequency compensation disabled. No capacitor at pin.
0 - TSUP frequency compensation enabled. Capacitor C
6
ECAP
allowed at pin.
TSUP
Temperature ADC Gain Select; Test purpose only, Default value (1) must be used
0 - Temperature ADC - gain adjustment
1 - Temperature ADC - standard gain (default)
5
TADCG
Voltage ADC Gain Select; Test purpose only; Default value (1) must be used
0 - Voltage ADC - gain adjustment
1 - Voltage ADC - standard gain (default)
4
VADCG
Current ADC Gain Select; Test purpose only; Default value (1) must be used
0 - Current ADC - gain adjustment
1 - Current ADC - standard gain (default)
3
CADCG
Timing delay - Temperature
0 - standard timing for temperature measurement channel
1 - additional SD converter input delay (typ. 100 ns) for temperature measurement channel
2
TDEN
Timing delay - Voltage
1
0 - standard timing for Voltage measurement channel
1 - additional SD converter input delay (typ. 100 ns) for voltage measurement channel
VDEN
Timing delay - Current
0
0 - standard timing for current measurement channel
1 - additional SD converter input delay (typ. 100 ns) for current measurement channel
CDEN
4.8.6.3.6
Decimation rate (ACQ_DEC)
Table 119. Decimation rate (ACQ_DEC)
(127)
Offset
Access: User read/write
1 0
0x60
7
0
6
0
5
0
4
0
3
0
2
R
DEC[2:0]
W
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Table 119. Decimation rate (ACQ_DEC)
Reset
0
0
0
0
0
1
0
0
Notes
127. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 120. Decimation rate (ACQ_DEC) - register field descriptions
Field
Description
Decimation Rate Selection (Combined decimation rate of first and second sinc3 decimator; Fist decimator is fixed to D=8)
000 - D = 512 (Channel Output Rate = 1.0 kHz)
001 - D = 64 (Channel Output Rate = 8.0 kHz)
010 - D = 128 (Channel Output Rate = 4.0 kHz)
011 - D = 256 (Channel Output Rate = 2.0 kHz)
100 - D = 512 (Channel Output Rate = 1.0 kHz), (default)
101 - D = 1024 (Channel Output Rate = 500 Hz)
2-0
DEC[2:0]
110 - D = 512 (Channel Output Rate = 1.0 kHz)
111 - D = 512 (Channel Output Rate = 1.0 kHz)
4.8.6.3.7
BandGap control (ACQ_BGC)
Table 121. BandGap control (ACQ_BGC)
(128)
Offset
Access: User read/write
1 0
0x61
7
0
6
0
5
4
1
3
BGLDO
1
2
R
BG3EN
BG2EN
BG1EN
BGADC
W
Reset
0
0
0
0
0
0
Notes
128. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 122. BandGap control (ACQ_BGC) - register field descriptions
Field
Description
ADC Bandgap select
00 - n.a. (not allowed - VDDA Reset)
5-4
BGADC
01 - BG1 reference selected for the AD converters (default)
10 - BG2 reference selected for the AD converters
11 - BG3 reference selected for the AD converters
LDO (Low Dropout Regulator) Bandgap select
0 - BG2 selected as voltage regulator reference
1 - BG1 selected as voltage regulator reference (default)
3
BGLDO
Bandgap 3 Status
0 - Bandgap 3 disabled
1 - Bandgap 3 enabled
2
BG3EN
Bandgap 2 Status
0 - Bandgap 2 disabled
1 - Bandgap 2 enabled
1
BG2EN
Bandgap 1 Status
0 - Bandgap 1 disabled
1 - Bandgap 1 enabled
0
BG1EN
4.8.6.3.8
PGA gain (ACQ_GAIN)
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Table 123. PGA gain (ACQ_GAIN)
(129)
Offset
Access: User read/write
0x62
7
0
6
0
5
0
4
0
3
0
2
0
1
IGAIN[2:0]
0
0
R
W
Reset
0
0
0
0
0
0
Notes
129. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 124. PGA gain (ACQ_GAIN) - register field descriptions
Field
Description
PGA Gain Register - Writing will select (manually override) the PGA gain if the automatic gain control is disabled (AGEN=0). Reading
will return current gain setting (including the auto gain). The register content will also determine the current channel offset compensation
buffer accessed through the COC[7:0] register.
000 - PGA Gain = 4
001 - PGA Gain = 8
010 - PGA Gain = 16
011 - PGA Gain = 32
100 - PGA Gain = 64
101 - PGA Gain = 128
110 - PGA Gain = 256
111 - PGA Gain = 512
2-0
IGAIN[2:0]
4.8.6.3.9
GCB threshold (ACQ_GCB)
Table 125. GCB threshold (ACQ_GCB)
(130)
Offset
Access: User read/write
0
0x63
7
6
5
4
0
3
0
2
0
1
0
R
D (hi)
D (lo)
W
Reset
0
0
0
0
Notes
130. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 126. GCB threshold (ACQ_GCB) - register field descriptions
Field
Description
7-4
D[7:4]
Gain Control Block (GCB) - 4 Bit Gain “Up” Threshold. See Section 4.8.3.1.3, “Gain control block (GCB)".
3-0
D[3:0]
Gain Control Block (GCB) - 4 Bit Gain “Down” Threshold. See Section 4.8.3.1.3, “Gain control block (GCB)".
4.8.6.3.10
Internal temp. measurement result (ACQ_ITEMP (hi) / ACQ_ITEMP (lo))
Table 127. Internal temp. measurement result (ACQ_ITEMP (hi) / ACQ_ITEMP (lo))
(131)
Offset
Access: User read
0
0x64 / 0x65
7
6
5
4
3
2
1
R
ITEMP[15:8]
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Table 127. Internal temp. measurement result (ACQ_ITEMP (hi) / ACQ_ITEMP (lo))
W
R
ITEMP[7:0]
W
Notes
131. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 128. Internal Temp. Measurement Result (ACQ_ITEMP (hi) / ACQ_ITEMP (lo)) - Register Field Descriptions
Field
Description
15-0
ITEMP[15:0]
Internal Temperature Measurement - 16 Bit ADC Result Register (unsigned Integer)
4.8.6.3.11
External temp. measurement result (ACQ_ETEMP (hi) / ACQ_ETEMP (lo))
Table 129. External temp. measurement result (ACQ_ETEMP (hi) / ACQ_ETEMP (lo))
(132)
Offset
Access: User read
0
0x66 / 0x67
7
6
5
4
3
2
1
R
W
R
ETEMP[15:8]
ETEMP[7:0]
W
Notes
132. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 130. External temp. measurement result (ACQ_ETEMP (hi) / ACQ_ETEMP (lo)) - register field descriptions
Field
Description
15-0
ETEMP[15:0]
External Temperature Measurement - 16 Bit ADC Result Register (unsigned Integer)
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4.8.6.3.12
Current measurement result (ACQ_CURR1 / ACQ_CURR0)
Table 131. Current measurement result (ACQ_CURR1 / ACQ_CURR0)
(133)
(134)
(135)
Offset
Access: User read
0x69
/ 0x6A
7
6
5
4
3
2
1
0
R
CURR[23:16]
W
R
W
R
CURR[15:8]
CURR[7:0]
W
Notes
133. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
134. 0x69 for 8-Bit access. 0x68 for 16-Bit access.
135. This Register is 16-Bit access only.
Table 132. Current measurement result (ACQ_CURR1 / ACQ_CURR0) - register field descriptions
Field
Description
CURR[23:0]
Two's complement 24-Bit signed integer result register for the current measurement channel.
23-16
CURR[23:16]
Current Measurement - High Byte Result Register, 8 or 16-Bit read operation.
Current Measurement - Low Word Result Register, 16-Bit read operation only.
15-0
CURR[15:0]
4.8.6.3.13
Voltage measurement result (ACQ_VOLT)
Table 133. Voltage measurement result (ACQ_VOLT)
Offset
Access: User read
0
0x6C
(136)(137)
7
6
5
4
3
2
1
R
W
R
VOLT[15:8]
VOLT[7:0]
W
Notes
136. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
137. This Register is 16-Bit access only.
Table 134. Voltage measurement result (ACQ_VOLT) - register field descriptions
Field
Description
15-0
VOLT[15:0]
Unsigned 16-Bit integer result register for the voltage measurement channel.
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4.8.6.3.14
Low pass filter coefficient number (ACQ_LPFC)
Table 135. Low pass filter coefficient number (ACQ_LPFC)
(138)
Offset
Access: User read/write
0x6E
7
0
6
0
5
0
4
0
3
2
1
1
1
0
R
W
LPFC[3:0]
Reset
0
0
0
0
1
0
Notes
138. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 136. Low pass filter coefficient number (ACQ_LPFC) - register field descriptions
Field
Description
Low Pass Filter Coefficient Number. Defines the highest coefficient Number used.
0000 - LPF used with Coefficient A0
0001 - LPF used with Coefficient A0...A1
....
3-0
LPFC[3:0]
1111 - LPF used with Coefficient A0...A15
4.8.6.3.15
Low power trigger current measurement period (ACQ_TCMP)
Table 137. Low power trigger current measurement period (ACQ_TCMP)
Offset
Access: User read / write
0x70
(139)(140)
7
0
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
R
W
TCMP[15:8]
TCMP[7:0]
Reset
R
0
0
W
Reset
Notes
139. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
140. This Register is 16-Bit access only.
Table 138. Low power trigger current measurement period (ACQ_TCMP) - register field descriptions
Field
Description
15-0
TCMP[15:0]
Low power trigger current measurement period (Trigger counter based on ALFCLK). See Section 4.3.4.1.1, “Cyclic current
acquisition/calibration temperature check".
NOTE
The cyclic acquisition period must be greater than the acquisition time. See Section 4.8.3.5.2,
“Latency and throughput"” for estimation. A continuous acquisition is still possible by using TCMP=0.
The Low Power Trigger Current counter is an up counting counter starting at 0. It is increment according to the Low Power Clock. In Low
Power mode, when Low Power Trigger Current counter is equal to the Low Power Trigger Currrent Measurement Period, the device will
start a current and temperature acquisition according to the setting of the current and internal temperature acquisition channels.
4.8.6.3.16
Low power current threshold filtering period (ACQ_THF)
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Table 139. Low power current threshold filtering period (ACQ_THF)
(141)
Offset
Access: User read / write
0x72
7
6
5
4
3
0
2
0
1
0
R
W
THF[7:0]
Reset
0
0
0
0
0
0
Notes
141. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 140. Low power current threshold filtering period (ACQ_THF) - register field descriptions
Field
Description
7-0
THF[7:0]
Low power current threshold wake up filtering period. See Section 4.3.4.1.1, “Cyclic current acquisition/calibration temperature check".
4.8.6.3.17
I and V chopper control register (ACQ_CVCR (hi))
Table 141. I and V chopper control register (ACQ_CVCR (hi))
(142)
Offset
Access: User write
0x74
7
0
6
0
5
0
4
0
3
0
2
1
0
0
R
W
0
IIRCM
0
0
PGAFM
0
DBTM
Reset
0
0
0
0
0
0
Notes
142. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 142. I and V chopper control register (ACQ_CVCR (hi)) - register field descriptions
Field
Description
Hold Time After Chopper Swap - Mask
0 - writing the DBT bits will have no effect
1 - writing the DBT bits will be effective
5-4
DBTM[1:0]
IIR Low Pass Filter Configuration - Mask
0 - writing the IIRC bits will have no effect
1 - writing the IIRC bits will be effective
3-1
IIRCM[2:0]
PGA fast mode enable - Mask
0 - writing the PGAF bit will have no effect
1 - writing the PGAF bit will be effective
0
PGAFM
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4.8.6.3.18
I and V chopper control register (ACQ_CVCR (lo))
Table 143. I and V chopper control register (ACQ_CVCR (lo))
(143)
Offset
Access: User write
0x75
7
0
6
0
5
4
3
2
IIRC
1
1
1
0
PGAF
1
R
DBT
W
Reset
0
0
0
0
1
Notes
143. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 144. I and V chopper control register (ACQ_CVCR (lo)) - register field descriptions
Field
Description
Hold Time After Chopper Swap
00 - Hold after swap disabled
5-4
DBT[1:0]
01 - 3 x 64 kHz cycles hold time for the SINC3-L8
10 - 4 x 64 kHz cycles hold time for the SINC3-L8
11 - 5 x 64 kHz cycles hold time for the SINC3-L8
IIR Low Pass Filter Coefficient (
000 - 1/8
001 - 1/16
010 - 1/32
011 - 1/64
100 - 1/128
3-1
IIRC[2:0]
101 - IIR disabled
110 - IIR disabled
111 - IIR disabled
PGA fast mode enable
0 - PGA capacitor swap disabled (slow mode).
1 - PGA capacitors swapped during chopper
0
PGAF
NOTE
During Low Power mode: 0x15; (00010101b) is recommend for ACQ_CVCR (DBT =01, IIRC = 010,
PGAF = 1)
4.8.6.3.19
Low power current threshold (ACQ_CTH)
Table 145. Low power current threshold (ACQ_CTH
(144)
Offset
Access: User read / write
0x76
7
6
5
4
3
0
2
0
1
0
R
CTH[7:0]
W
Reset
0
0
0
0
0
0
Notes
144. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 146. Low power current threshold (ACQ_CTH - register field descriptions
Field
Description
7-0
Low power current threshold
CTH[7:0]
See Section 4.3.4.1.1.1, “Current threshold wake-up" for details.
4.8.6.3.20
Low power Ah counter threshold (ACQ_AHTH1 (hi) / ACQ_AHTH1 (lo) /
ACQ_AHTH0 (hi) / ACQ_AHTH0 (lo))
Table 147. Low power Ah counter threshold (ACQ_AHTH1 (hi) / ACQ_AHTH1 (lo) / ACQ_AHTH0 (hi) / ACQ_AHTH0 (lo))
(145)
Offset
Access: User read / write
1 0
0x78 / 0x79 / 0x7A / 0x7B
7
0
6
5
4
3
2
R
W
R
W
R
AHTH[30:0]
W
R
W
Reset
0
0
0
0
0
0
0
0
Notes
145. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 148. Low power Ah counter threshold (ACQ_AHTH1 (hi) / ACQ_AHTH1 (lo) / ACQ_AHTH0 (hi) / ACQ_AHTH0 (lo)) - register
field descriptions
Field
Description
30-0
AHTH[30:0]
Low power Ah counter threshold. Absolute (unsigned) 31-Bit integer. Reading one 16-Bit part of the register will buffer the second.
Reading the second will unlock the buffer. See Section 4.3.4.1.1.2, “Current ampere hour threshold wake-up". for details on the Register.
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4.8.6.3.21
Low power Ah counter (ACQ_AHC1 (hi) / ACQ_AHC1 (lo) / ACQ_AHC0 (hi) /
ACQ_AHC0 (lo))
Table 149. Low power Ah counter (ACQ_AHC1 (hi) / ACQ_AHC1 (lo) / ACQ_AHC0 (hi) / ACQ_AHC0 (lo))
(146)
Offset
Access: User read
0
0x7C / 0x7D / 0x7E / 0x7F
7
6
5
4
3
2
1
R
W
R
AHC[31:0]
AHC[23:16]
AHC[15:8]
AHC[7:0]
W
R
W
R
W
Notes
146. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 150. Low power Ah counter (ACQ_AHC1 (hi) / ACQ_AHC1 (lo) / ACQ_AHC0 (hi) / ACQ_AHC0 (lo)) - register field
descriptions
Field
Description
31-0
AHC[31:0]
Low power Ah counter (32-Bit signed integer, two’s complement). Reading one 16-Bit part of the register will buffer the second. Reading
the second will unlock the buffer. See Section 4.3.4.1.1.2, “Current ampere hour threshold wake-up".
4.8.6.3.22
Low pass filter coefficient Ax (LPF_Ax (hi))
Table 151. Low pass filter coefficient Ax (LPF_Ax (hi))
(147)
Offset
Access: User read/write
1 0
0x80...0x9E
7
6
5
4
3
2
R
W
Ax[15:8]
Reset
see Table 154
Notes
147. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.8.6.3.23
Low pass filter coefficient Ax (LPF_Ax (lo))
Table 152. Low pass filter coefficient Ax (LPF_Ax (lo))
(148)
Offset
Access: User read/write
0x81...0x9F
7
6
5
4
3
2
1
0
R
Ax[7:0]
W
Reset
see Table 154
Notes
148. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 153. Low pass filter coefficient Ax - register field descriptions
Field
Description
15-0
Ax[15:0]
Low Pass Filter Coefficient Value. x = 0...15. Data Format: MSB = Sign (“1” minus). [14:0] integer.
Table 154. Low pass filter coefficient Ax - reset values
Field
A0
Reset Value
0x00F5
0x0312
0x051F
0x0852
0x0B44
0x0E35
0x1021
0x10E5
Field
A8
Reset Value
0x1021
0x0E35
0x0B44
0x0852
0x051F
0x0312
0x00F5
0x0000
A1
A9
A2
A10
A11
A12
A13
A14
A15
A3
A4
A5
A6
A7
4.8.6.3.24
Compensation control register (COMP_CTL)
Table 155. Compensation control register (COMP_CTL)
Offset
Access: User read/write
0xA0
(149)(150)
15
0
14
0
13
12
11
10
9
0
8
R
W
0
0
0
0
0
BGCALM
BGCAL
PGAZM
PGAOM
DIAGVM
DIAGIM
CALIEM
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
PGAZ
0
PGAO
0
DIAGV
0
DIAGI
0
CALIE
0
Reset
1
0
0
Notes
149. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
150. This Register is 16-Bit access only.
Table 156. Compensation control register (COMP_CTL) - register field descriptions
Field
Description
Calibration Band Gap Select - Mask
0 - writing the corresponding BGCAL bits will have no effect
1 - writing the corresponding BGCAL bits will be effective
15-14
BGCALM
PGA Input Zero - Mask
0 - writing the PGAZ bit will have no effect
1 - writing the PGAZ bit will be effective
13
PGAZM
PGA Offset Calibration - Mask
0 - writing the PGAO bit will have no effect
1 - writing the PGAO bit will be effective
12
PGAOM
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Table 156. Compensation control register (COMP_CTL) - register field descriptions (continued)
Field
Description
Diagnostic Mode Voltage Channel - Mask
0 - writing the DIAGV bit will have no effect
1 - writing the DIAGV bit will be effective
11
DIAGVM
Diagnostic Mode Current Channel - Mask
0 - writing the DIAGI bit will have no effect
1 - writing the DIAGI bit will be effective
10
DIAGIM
Calibration IRQ Enable - Mask
0 - writing the CALIE bit will have no effect
1 - writing the CALIE bit will be effective
8
CALIEM
Calibration Band Gap Select
00 - Bandgap disconnected from calibration
01 - BG1 selected as calibration reference
10 - BG2 selected as calibration reference (default)
11 - BG3 selected as calibration reference
7-6
BGCAL
PGA Input Zero
0 - Programmable gain amplifier inputs in normal operation
1 - Programmable gain amplifier inputs shorted for Calibration
5
PGAZ
PGA Offset Calibration Start
0 - PGA normal operation
4
1 - PGA internal offset calibration start (PGAOF will indicate calibration complete). PGAZ has to be set to 1 during calibration. The bit
will remain set after the calibration is complete. It has to be cleared by writing 0 before it can be set to start the next calibration. The
current measurement channel has to be enabled (ACQ_CTL[CMEN]=1) in order to perform the PGA offset compensation.
PGAO
Diagnostic Mode Voltage Channel
0 - Calibration reference disconnected from the voltage channel input
1 - Calibration reference connected to the voltage channel input for calibration. Manual conversion needed to measure reference
3
DIAGV
Diagnostic Mode Current Channel
0 - Calibration reference disconnected from the current channel input
1 - Calibration reference connected to the current channel input for calibration. Manual conversion needed to measure reference
2
DIAGI
Calibration IRQ Enable
0 - Calibration request interrupt disabled
1 - Calibration request interrupt enabled. A temperature “out of calibration range” will cause a calibration interrupt request
0
CALIE
4.8.6.3.25
Compensation status register (COMP_SR)
Table 157. Compensation status register (COMP_SR)
(151)
Offset
Access: User read/write
0xA2
7
0
6
5
0
4
3
0
2
0
1
0
0
R
BGRF
PGAOF
CALF
W
Write 1 will clear the flags and will start next calibration steps
Reset
0
0
0
0
0
0
0
0
Notes
151. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 158. Compensation status register (COMP_SR) - register field descriptions
Field
Description
Band Gap Reference Status Flag
0 - Indicates the reference bandgap has not been set / applied
1 - Reference bandgap has been set. Writing 1 will clear the flag
6
BGRF
PGA Internal Offset Compensation Complete Flag
0 - PGA offset compensation ongoing or not started since last flag clear
1 - PGA offset compensation finished since last flag clear. Writing 1 will clear the flag
4
PGAOF
Calibration Request Status Flag
0 - No Temperature out of range condition detected
1 - Temperature out of range condition detected. Writing 1 will clear the flag
0
CALF
4.8.6.3.26
Temperature filtering period (COMP_TF)
Table 159. Temperature filtering period (COMP_TF)
(152)
Offset
Access: User read / write
0xA3
7
0
6
0
5
0
4
0
3
0
2
0
1
TMF[2:0]
0
0
R
W
Reset
0
0
0
0
0
0
Notes
152. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 160. Temperature filtering period (COMP_TF) - register field descriptions
Field
Description
2-0
TMF[2:0]
Recalibration Temperature Filtering period. Defines the number of measurements above / below the Max / Min thresholds that are
required before a calibration request is detected.
4.8.6.3.27
Max. temp. before recalibration (COMP_TMAX)
Table 161. Max. temp. before recalibration (COMP_TMAX)
Offset
Access: User read/write
8
0xA4
(153)(154)
15
14
13
12
11
10
9
R
W
TCMAX[15:8]
TCMAX[7:0]
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset
0
0
0
0
0
0
0
0
Notes
153. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
154. This Register is 16 Bit access only.
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Table 162. Max. temp. before recalibration (COMP_TMAX) - register field descriptions
Field
Description
15-0
TCMAX[15:0]
Maximum Temperature before recalibration. Once the internal temperature measurement result is above or equal to TCMAX, the TMF
filter counter is increased, if below, the counter is decreased.
4.8.6.3.28
Min.temp. before recalibration (COMP_TMIN)
Table 163. Min. temp. before recalibration (COMP_TMIN)
Offset
Access: User read/write
8
0xA6
(155)(156)
15
14
13
12
11
10
9
R
W
TCMIN[15:8]
TCMIN[7:0]
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset
0
0
0
0
0
0
0
0
Notes
155. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
156. This Register is 16-Bit access only.
Table 164. Min. Temp. before recalibration (COMP_TMIN) - register field descriptions
Field
Description
15-0
TCMIN[15:0]
Minimum Temperature before recalibration. Once the internal temperature measurement result is below TCMIN, the TMF filter counter
is increased, if above or equal, the counter is decreased.
4.8.6.3.29
Offset voltage compensation (COMP_VO)
Table 165. Offset voltage compensation (COMP_VO)
(157)
Offset
Access: User read/write
0
0xAA
7
0
6
0
5
0
4
0
3
0
2
0
1
0
R
VOC[7:0]
W
Reset
0
Notes
157. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 166. Offset voltage compensation (COMP_VO) - register field descriptions
Field
Description
7-0
VOC[7:0]
Voltage Offset Compensation Buffer. This register contains the voltage channel offset compensation as an 8-bit signed char (two
complement). 0x7F = max, 0x80 =min.
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4.8.6.3.30
Offset current compensation window (COMP_IO)
Table 167. Offset current compensation window (COMP_IO)
(158)
Offset
Access: User read/write
0xAB
7
6
5
4
3
2
0
1
0
0
R
COC[7:0]
W
Reset
0
0
0
0
0
0
Notes
158. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 168. Offset current compensation window (COMP_IO) - register field descriptions
Field
Description
Current Offset Compensation Buffer window for the 8 current compensation values stored. The content of the IGAIN[2:0] register will
determine the compensation buffer accessed through the COC[7:0] register. This register contains the current channel offset
compensation as 8-bit signed char (two complement). 0x7F = max, 0x80 =min.
7-0
COC[7:0]
4.8.6.3.31
Gain voltage comp. V
channel (COMP_VSG)
SENSE
Table 169. Gain voltage comp. VSENSE channel (COMP_VSG)
Offset
Access: User read/write
0xAC
(159)(160)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
R
W
VSGC[9:8]
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
VSGC[7:0]
Reset
0
0
0
0
0
0
0
0
Notes
159. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
160. This Register is 16 Bit access only.
Table 170. Gain voltage comp. VSENSE channel (COMP_VSG) - register field descriptions
Field
Description
9-0
VSGC[9:0]
Voltage Channel Gain Compensation Buffer. This register contains the voltage channel gain compensation as 10-bit special coded
value. Refer to Section 4.8.3.4, “Compensation" for details.
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4.8.6.3.32
8 x gain current compensation 4...512 (COMP_IG4... COMP_IG512)
Table 171. 8 x Gain current compensation 4...512 (COMP_IG4... COMP_IG512)
Offset
Access: User read/write
0xB0... 0xBE
(161)(162)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
R
W
IGC4...512 (hi) [9:8]
Reset
0
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
R
W
IGC4...512 (lo) [7:0]
Reset
0
0
0
0
0
0
0
0
Notes
161. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
162. This Register is 16 Bit access only.
Table 172. 8 x gain current compensation 4...512 (COMP_IG4 COMP_IG512) - register field descriptions
Field
Description
9-0
IGC4[9:0]
IGC8[9:0]
IGC16[9:0]
IGC32[9:0]
IGC64[9:0]
IGC128[9:0]
IGC256[9:0]
IGC512[9:0]
Individual Current Gain Compensation Buffers for the 8 Gain configurations. Those registers contain the current channel gain
compensation as 10-bit special coded value. Refer to Section 4.8.3.4, “Compensation" for details.
4.8.6.3.33
8 x offset PGA compensation (COMP_PGAO4COMP_PGAO512)
Table 173. 8 x offset PGA compensation (COMP_PGAO4... COMP_PGAO512)
Offset
Access: User read/write
9 8
0xC0... 0xCE
(163)(164)
15
0
14
0
13
0
12
0
11
0
10
R
W
PGAOC4...512 (hi) [10:8]
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
PGAOC4...512 (lo) [7:0]
Reset
0
0
0
0
0
0
0
0
Notes
163. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
164. This Register is 16 Bit access only.
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Table 174. 8 x offset PGA compensation (COMP_PGAO4...COMP_PGAO512) - register field descriptions
Field
Description
10-0
PGAOC4[10:0]
PGAOC8[10:0]
PGAOC16[10:0]
PGAOC32[10:0]
PGAOC64[10:0]
PGAOC128[10:0]
PGAOC256[10:0]
PGAOC512[10:0]
Individual PGA Offset Compensation Buffers for the 8 Gain configurations. Those registers contain the PGA Offset compensation
as 11-bit special coded value. Refer to Section 4.8.3.4, “Compensation" for details.
4.8.6.3.34
Internal temp. offset compensation (COMP_ITO)
Table 175. Internal temp. offset compensation (COMP_ITO)
(165)
Offset
Access: User read/write
0
0xD0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
R
ITOC[7:0]
W
Reset
0
Notes
165. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 176. Internal temp. offset compensation (COMP_ITO) - register field descriptions
Field
Description
7-0
ITOC[7:0]
Internal Temperature Offset Compensation Buffer. This register contains the Internal Temperature Offset compensation as 8-bit signed
char (two complement). Refer to Section 4.8.3.4, “Compensation" for details.
4.8.6.3.35
Internal temp. gain compensation (COMP_ITG)
Table 177. Internal temp. gain compensation (COMP_ITG)
(166)
Offset
Access: User read/write
0
0xD1
7
1
6
0
5
0
4
0
3
0
2
0
1
0
R
ITGC[7:0]
W
Reset
0
Notes
166. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 178. Internal temp. gain compensation (COMP_ITG) - register field descriptions
Field
Description
7-0
ITGC[7:0]
Internal Temperature Gain Compensation Buffer. This register contains the Internal Temperature Gain compensation as 8-bit
special coded value. Refer to Section 4.8.3.4, “Compensation" for details.
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4.8.6.3.36
External temp. offset compensation (COMP_ETO)
Table 179. External temp. offset compensation (COMP_ETO)
(167)
Offset
Access: User read/write
0xD2
7
6
5
4
3
2
0
1
0
0
R
ETOC[7:0]
W
Reset
0
0
0
0
0
0
Notes
167. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 180. External temp. offset compensation (COMP_ETO) - register field descriptions
Field
Description
7-0
ETOC[7:0]
External Temperature Offset Compensation Buffer. This register contains the External Temperature Offset compensation as 8-bit signed
char (two complement). Refer to Section 4.8.3.4, “Compensation" for details.
4.8.6.3.37
External temp. gain compensation (COMP_ETG)
Table 181. External temp. gain compensation (COMP_ETG)
(168)
Offset
Access: User read/write
0
0xD3
7
6
5
4
3
2
0
1
0
R
W
ETGC[7:0]
Reset
1
0
0
0
0
0
Notes
168. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 182. External temp. gain compensation (COMP_ETG) - register field descriptions
Field
Description
7-0
ETGC[7:0]
External Temperature Gain Compensation Buffer. This register contains the External Temperature Gain compensation as 8-bit special
coded value. Refer to Section 4.8.3.4, “Compensation" for details.
4.9
Window watchdog
The MM912_637 analog die includes a configurable window watchdog which is active in Normal mode. The watchdog module is based
on the Low Power Oscillator (LPCLK) to operate independently from the MCU based D2DCLK clock. The watchdog timeout (t
be configured between 4.0 ms and 2048 ms using the watchdog control register (WD_CTL).
) can
WDTO
NOTE
As the watchdog timing is based on the LPCLK, its accuracy is based on the trimming applied to the
TRIM_OSC register. The given timeout values are typical values only.
During Low Power mode, the watchdog feature is not active, a D2D read during Stop mode will have the WDOFF bit set. After wake-up
and transition to Normal mode, the watchdog is reset to the same state as when following a Power-On-Reset (POR).
To clear the watchdog counter, a alternating write has to be performed to the watchdog rearm register (WD_RR). The first write after the
wake-up or RESET_A has been released has to be 0xAA, the next one has to be 0x55.
After the wake-up or RESET_A has been released, there will be a standard (non window) watchdog active with a fixed timeout of t
IWDTO
(t
= b100 = 256 ms). The Watchdog Window Open (WDWO) bit is set during that time.
WDTO
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WD Register
WRITE = 0xAA
(to be continued)
Window WD timing (tWDTO
)
tWDTO / 2 tWDTO / 2
WD Register
WRITE = 0x55
Window Watch Dog
Window Closed
Window Watch Dog
Window Open
Initial WD Reg.
WRITE = 0xAA
Window Watch Dog
Window Closed
Window Watch Dog
Window Open
Standard Initial Watch Dog (no window)
t
tIWDTO
Figure 39. MM912_637 Analog die watchdog operation
To change from the standard initial watchdog to the window watchdog, the initial counter reset has to be performed by writing 0xAA to the
Watchdog rearm register (WD_RR) before t is reached.
IWDTO
NOTE
An immediate trimming of the low power oscillator after reset release assures t
being at the
IWDTO
maximum accuracy. See chapter 5.2.2.5, “Low power oscillator trimming (TRIM_OSC)".
If the t
timeout is reached with no counter reset or a value different from 0xAA written to the WD_RR, a watchdog reset will occur.
IWDTO
Once entering window watchdog mode, the first half of the time, t
is forbidden for a counter reset. To reset the watchdog counter, an
WDTO
alternating write of 0x55 and 0xAA has to be performed within the second half of the t
. A Window Open (WDWO) flag will indicate
WDTO
the current status of the window. A timeout or wrong value written to the WD_RR will force a watchdog reset.
If the first write to the WD_CTL register is 000 (WD OFF), the WD will be disabled(169). If a different cycle time is written or the WD is
refreshed with the default Window (100) unchanged, no further “000” write will be effective (a change of cycle time would still be possible).
Notes
169. The Watchdog can be enabled any time later.
4.9.1
Memory map and registers
Overview
4.9.1.1
This section provides a detailed description of the memory map and registers.
4.9.1.2
Module memory map
The memory map for the Watchdog module is given in Table 63
Table 183. Module memory map
Offset
Name
7
6
5
4
3
2
1
0
(170),(171)
R
W
R
0
0
0
0
0
0
0
0
Reserved
WDTOM[2:0]
WD_CTL
Watchdog control register
0x10
0
0
0
0
0
0
0
0
Reserved
0
WDTO[2:0]
WDOFF
W
R
WD_SR
0
WDWO
0x12
Watchdog status register
W
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Table 183. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(170),(171)
R
W
R
0
0
0
0
0
0
0
0
0x13
0x14
0x15
0x16
0x17
Reserved
WD_RR
WDR[7:0]
Watchdog rearm register
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
W
R
W
R
W
Notes
170. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
171. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
4.9.1.3
Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bits and field function follow the register diagrams, in bit order.
4.9.1.3.1
Watchdog control register (WD_CTL)
Table 184. Watchdog control register (WD_CTL)
Offset
Access: User write
0x10
(172),(173)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
0
R
W
0
Reserved
WDTOM
Reset
0
7
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
1
0
0
R
W
Reserved
1
WDTO
0
Reset
0
0
0
0
1
0
Notes
172. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
173. This Register is 16 Bit access only.
Table 185. Watchdog control register (WD_CTL) - register field descriptions
Field
Description
15
Reserved
This reserved bit is used for test purpose. Software has to write a 0 into this bit.
Watchdog Timeout - Mask
any setting other than 111 - writing the WDTO bits will have no effect
111 - writing the WDTO bits will be effective
10-8
WDTOM[2:0]
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Table 185. Watchdog control register (WD_CTL) - register field descriptions (continued)
Field
Description
7
This reserved bit is used for test purpose. Software has to write a 0 into this bit.
Reserved
Watchdog Timeout Configuration - configuring the watchdog timeout duration t
.
WDTO
000 - Watchdog OFF
001 - 4.0 ms
010 - 16.0 ms
011 - 64.0 ms
100 - 256 ms (default)
101 - 512 ms
2-0
WDTO[2:0]
110 - 1024 ms
111 - 2048 ms
4.9.1.3.2
Watchdog status register (WD_SR)
Table 186. Watchdog status register (WD_SR)
(174)
Offset
Access: User read
0x12
7
0
6
0
5
0
4
0
3
0
2
0
1
0
R
WDOFF
WDWO
W
Notes
174. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 187. Watchdog status register (WD_SR) - register field descriptions
Field
Description
Watchdog Status - Indicating the watchdog module being enabled/disabled
1 - Watchdog Off
0 - Watchdog Active
1
WDOFF
Watchdog Window Status
0
1 - Open - Indicating the watchdog window is currently open for counter reset.
WDWO
0 - Closed - Indicating the watchdog window is currently closed for counter reset. Resetting the watchdog with the window closed will
cause a watchdog - reset.
4.9.1.3.3
Watchdog rearm register (WD_RR)
Table 188. Watchdog rearm register (WD_RR)
(175)
Offset
Access: User read/write
0
0x14
7
6
5
4
3
0
2
0
1
0
R
WDR
W
Reset
0
0
0
0
0
Notes
175. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 189. Watchdog rearm register (WD_RR) - register field descriptions
Field
Description
7-0
WDR[7:0]
Watchdog rearm register- Writing this register with the correct value (0xAA alternating 0x55) while the window is open will reset the
watchdog counter. Writing the register while the watchdog is disabled will have no effect.
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4.10 Basic timer module - TIM (TIM16B4C)
4.10.1 Introduction
4.10.1.1 Overview
The basic timer consists of a 16-bit, software-programmable counter driven by a seven stage programmable prescaler. This timer can be
used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can
vary from microseconds to many seconds.
This timer contains four complete input capture/output compare channels [IOC 3:0]. The input capture function is used to detect a selected
transition edge and record the time. The output compare function is used for generating output signals or for timer software delays.
Full access for the counter registers or the input capture/output compare registers should take place in a16-bit word access. Accessing
high bytes and low bytes separately for all of these registers may not yield the same result as accessing them in one word.
4.10.1.2 Features
The TIM16B4C includes these distinctive features:
•
•
•
•
Four input capture/output compare channels.
Clock prescaler
16-bit counter
Timer counter reset on Output Compare 3
4.10.1.3 Modes of operation
The TIM16B4C is driven by the D2DCLK / 4 during Normal mode and the ALFCLK during Low Power mode.
4.10.1.4 Block diagram
Channel 0
Input capture
Output compare
Prescaler
D2DCLK / 4 or
ALFCLK
IOC0
IOC1
Timer overflow
interrupt
Channel 1
Input capture
Output compare
16-bit Counter
Channel 2
Input capture
Output compare
Timer channel 0
interrupt
IOC2
IOC3
Channel 3
Input capture
Output compare
Registers
Timer channel 3
interrupt
Figure 40. Timer block diagram
For more information on the respective functional descriptions see Section 4.10.4, “Functional description" of this chapter.
4.10.2 Signal description
4.10.2.1 Overview
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The TIM16B4C module can be used as regular time base, or can be internally routed to the PTB and LIN module. Refer to the
corresponding sections for further details, see Section 4.12, “LIN" and Section 4.11, “General purpose I/O - GPIO". In addition, the
TIM16B4C module is used during Low Power mode to determine the cyclic wake-up and current measurement timing (Section 4.3,
“Analog die - power, clock and resets - PCR")
4.10.2.2 Detailed signal descriptions
4.10.2.2.1
IOC3 – input capture and output compare channel 3
This pin serves as the input capture or output compare for channel 3.
4.10.2.2.2
IOC2 – input capture and output compare channel 2
This pin serves as the input capture or output compare for channel 2.
4.10.2.2.3
IOC1 – input capture and output compare channel 1
This pin serves as the input capture or output compare for channel 1.
4.10.2.2.4
IOC0 – input capture and output compare channel 0
This pin serves as the input capture or output compare for channel 0.
4.10.3 Memory map and registers
4.10.3.1 Overview
This section provides a detailed description of all memory and registers.
4.10.3.2 Module memory map
The memory map for the TIM16B4C module is given in Table 63.
Table 190. Module memory map
Offset
Name
7
6
5
4
3
2
1
0
(176)
TIOS
R
0
0
0
0
0x20
IOS3
IOS2
IOS1
IOS0
Timer Input Capture/Output
Compare Select
W
CFORC
Timer Compare Force Register
OC3M
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x21
(177)
FOC3
FOC2
FOC1
FOC0
0x22
0x23
OC3M3
OC3D3
OC3M2
OC3D2
OC3M1
OC3D1
OC3M0
OC3D0
Output Compare 3 Mask Register
OC3D
W
R
Output Compare 3 Data Register
TCNT (hi)
W
R
0x24
(178)
Timer Count Register
TCNT (lo)
W
R
TCNT
0x25
(178)
Timer Count Register
W
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Table 190. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(176)
TSCR1
Timer System Control Register 1
TTOV
R
W
R
0
0
0
0
0
0
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
TEN
0
TFFCA
0
0
0
TOV3
OM1
TOV2
OL1
TOV1
OM0
TOV0
OL0
Timer Toggle Overflow Register
TCTL1
W
R
OM3
OL3
OM2
OL2
Timer Control Register 1
TCTL2
W
R
EDG3B
0
EDG3A
0
EDG2B
0
EDG2A
0
EDG1B
C3I
EDG1A
C2I
EDG0B
C1I
EDG0A
C0I
Timer Control Register 2
TIE
W
R
Timer Interrupt Enable Register
TSCR2
W
R
0
0
0
0
0
0
0
0
0
TOI
0
TCRE
PR2
PR1
PR0
Timer System Control Register 2
TFLG1
W
R
C3F
0
C2F
0
C1F
0
C0F
0
Main Timer Interrupt Flag 1
TFLG2
W
R
TOF
Main Timer Interrupt Flag 2
TC0 (hi)
W
R
0x2E
(179)
Timer Input Capture/Output
Compare Register 0
W
R
TC0
TC1
TC2
TC3
TC0 (lo)
0x2F
(179)
Timer Input Capture/Output
Compare Register 0
W
R
TC1 (hi)
0x30
(179)
Timer Input Capture/Output
Compare Register 1
W
R
TC1 (lo)
0x31
(179)
Timer Input Capture/Output
Compare Register 1
W
R
TC2 (hi)
0x32
(179)
Timer Input Capture/Output
Compare Register 2
W
R
TC2 (lo)
0x33
(179)
Timer Input Capture/Output
Compare Register 2
W
R
TC3 (hi)
0x34
(179)
Timer Input Capture/Output
Compare Register 3
W
R
TC3 (lo)
0x35
(179)
Timer Input Capture/Output
Compare Register 3
W
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Table 190. Module memory map (continued)
Offset
Name
7
6
5
4
3
2
1
0
(176)
TIMTST
R
0
0
0
0
0
0
0
0x36
TCBYP
(178)
Timer Test Register
W
Notes
176. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
177. Always reads $00.
178. Only writable in special modes. (Refer to the SOC Guide for different modes).
179. A write to these registers has no meaning or effect during input capture.
4.10.3.3 Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.10.3.3.1
Timer input capture/output compare select (TIOS)
Table 191. Timer input capture/output compare select (TIOS)
(180)
Offset
Access: User read/write
1 0
0x20
7
0
6
0
5
0
4
0
3
IOS3
0
2
IOS2
0
R
IOS1
0
IOS0
0
W
Reset
0
0
0
0
Notes
180. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 192. TIOS - register field descriptions
Field
Description
Input Capture or Output Compare Channel Configuration
0 - The corresponding channel acts as an input capture.
1 - The corresponding channel acts as an output compare.
3-0
IOS[3-0]
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4.10.3.3.2
Timer compare force register (CFORC)
Table 193. Timer compare force register (CFORC)
(181)
Offset
Access: User write
0x21
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
FOC3
0
FOC2
0
FOC1
0
FOC0
0
Reset
0
0
0
0
Notes
181. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 194. CFORC - register field descriptions
Field
Description
Force Output Compare Action for Channel 3-0
0 - Force output compare action disabled. Input capture or output compare channel configuration
1 - Force output compare action enabled
3-0
FOC[3-0]
A write to this register with the corresponding (FOC 3:0) data bit(s) set causes the action programmed for output compare on channel “n”
to occur immediately.The action taken is the same as if a successful comparison had just taken place with the TCn register, except the
interrupt flag does not get set.
NOTE
A successful channel 3 output compare overrides any channel 2:0 compare. If a forced output
compare on any channel occurs at the same time as the successful output compare, then a forced
output compare action will take precedence and the interrupt flag will not get set.
4.10.3.3.3
Output compare 3 mask register (OC3M)
Table 195. Output compare 3 mask register (OC3M)
(182)
Offset
Access: User read/write
1 0
0x22
7
0
6
0
5
0
4
0
3
OC3M3
0
2
OC3M2
0
R
OC3M1
0
OC3M0
0
W
Reset
0
0
0
0
Notes
182. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 196. OC3M - register field descriptions
Field
Description
Output Compare 3 Mask “n” Channel bit
0 - Does not set the corresponding port to be an output port
1 - Sets the corresponding port to be an output port when this corresponding TIOS bit is set to be an output compare
3-0
OC3M[3-0]
Setting the OC3Mn (n ranges from 0 to 2) will set the corresponding port to be an output port when the corresponding TIOSn (n ranges
from 0 to 2) bit is set to be an output compare.
NOTE
Asuccessful channel 3 output compare overrides any channel 2:0 compares. For each OC3M bit that
is set, the output compare action reflects the corresponding OC3D bit.
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4.10.3.3.4
Output compare 3 data register (OC3D)
Table 197. Output compare 3 data register (OC3D)
(183)
Offset
Access: User read/write
0x23
7
0
6
0
5
0
4
0
3
OC3D3
0
2
OC3D2
0
1
OC3D1
0
0
OC3D0
0
R
W
Reset
0
0
0
0
Notes
183. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 198. OC3D - register field descriptions
Field
Description
3
Output Compare 3 Data for Channel 3
Output Compare 3 Data for Channel 2
Output Compare 3 Data for Channel 1
Output Compare 3 Data for Channel 0
OC3D3
2
OC3D2
1
OC3D1
0
OC3D0
NOTE
A channel 3 output compare will cause bits in the output compare 3 data register to transfer to the
timer port data register if the corresponding output compare 3 mask register bits are set.
4.10.3.3.5
Timer count register (TCNT)
Table 199. Timer count register (TCNT)
(184)
Offset
Access: User read (anytime)/write (special mode)
0x24, 0x25
15
14
13
12
11
10
9
8
R
tcnt15
tcnt14
tcnt13
tcnt12
tcnt11
tcnt10
tcnt9
tcnt8
W
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
tcnt7
0
tcnt6
0
tcnt5
0
tcnt4
0
tcnt3
0
tcnt2
0
tcnt1
0
tcnt0
0
Reset
Notes
184. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 200. TCNT - register field descriptions
Field
Description
15-0
tcnt[15-0]
16-Bit Timer Count Register
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NOTE
The 16-bit main timer is an up counter. Full access to the counter register should take place in one
clock cycle. A separate read/write for high bytes and low bytes will give a different result than
accessing them as a word. The period of the first count after a write to the TCNT registers may be a
different length, because the write is not synchronized with the prescaler clock.
4.10.3.3.6
Timer system control register 1 (TSCR1)
Table 201. Timer system control register 1 (TSCR1)
(185)
Offset
Access: User read/write
0x26
7
TEN
0
6
0
5
0
4
TFFCA
0
3
0
2
0
1
0
0
R
W
0
Reset
0
0
0
0
0
0
Notes
185. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 202. TSCR1 - register field descriptions
Field
Description
Timer Enable
1 = Enables the timer.
0 = Disables the timer. (Used for reducing power consumption).
7
TEN
Timer Fast Flag Clear All
1 = For TFLG1 register, a read from an input capture or a write to the output compare channel [TC 3:0] causes the corresponding
channel flag, CnF, to be cleared. For TFLG2 register, any access to the TCNT register clears the TOF flag. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended
accesses.
4
TFFCA
0 = Allows the timer flag clearing.
4.10.3.3.7
Timer toggle on overflow register 1 (TTOV)
Table 203. Timer toggle on overflow register 1 (TTOV)
(186)
Offset
Access: User read/write
1 0
0x27
7
0
6
0
5
0
4
0
3
TOV3
0
2
TOV2
0
R
TOV1
0
TOV0
0
W
Reset
0
0
0
0
Notes
186. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 204. TTOV - register field descriptions
Field
Description
Toggle On Overflow Bits
1 = Toggle output compare pin on overflow feature enabled.
0 = Toggle output compare pin on overflow feature disabled.
3-0
TOV[3-0]
NOTE
TOVn toggles the output compare pin on overflow. This feature only takes effect when the
corresponding channel is configured for an output compare mode. When set, an overflow toggle on
the output compare pin takes precedence over forced output compare events.
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4.10.3.3.8
Timer control register 1 (TCTL1)
Table 205. Timer control register 1 (TCTL1)
(187)
Offset
Access: User read/write
0x28
7
OM3
0
6
OL3
0
5
OM2
0
4
OL2
0
3
OM1
0
2
OL1
0
1
OM0
0
0
OL0
0
R
W
Reset
Notes
187. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 206. TCTL1 - register field descriptions
Field
Description
7,5,3,1
OMn
Output Mode bit
Output Level bit
6,4,2,0
OLn
NOTE
These four pairs of control bits are encoded to specify the output action to be taken as a result of a
successful Output Compare on “n” channel. When either OMn or OLn, the pin associated with the
corresponding channel becomes an output tied to its IOC. To enable output action by the OMn and
OLn bits on a timer port, the corresponding bit in OC3M should be cleared.
Table 207. Compare result output action
OMn
OLn
Action
0
0
1
1
0
1
0
1
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
4.10.3.3.9
Timer control register 2 (TCTL2)
Table 208. Timer control register 2 (TCTL2)
(188)
Offset
Access: User read/write
1 0
0x29
7
6
EDG3A
0
5
EDG2B
0
4
EDG2A
0
3
EDG1B
0
2
EDG1A
0
R
EDG3B
0
EDG0B
0
EDG0A
0
W
Reset
Notes
188. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 209. TCTL2 - register field descriptions
Field
Description
EDGnB,EDGn
A
Input Capture Edge Control
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These four pairs of control bits configure the input capture edge detector circuits.
Table 210. Edge detector circuit configuration
EDGnB
EDGnA
Configuration
Capture disabled
0
0
1
1
0
1
0
1
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
4.10.3.3.10 Timer interrupt enable register (TIE)
Table 211. Timer interrupt enable register (TIE)
(189)
Offset
Access: User read/write
0x2A
7
0
6
0
5
0
4
0
3
C3I
0
2
C2I
0
1
C1I
0
0
C0I
0
R
W
Reset
0
0
0
0
Notes
189. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 212. TIE - register field descriptions
Field
Description
Input Capture/Output Compare Interrupt Enable.
1 = Enables corresponding Interrupt flag (CnF of TFLG1 register) to cause a hardware interrupt
0 = Disables corresponding Interrupt flag (CnF of TFLG1 register) from causing a hardware interrupt
3-0
C[3-0]I
4.10.3.3.11 Timer system control register 2 (TSCR2)
Table 213. Timer system control register 2 (TSCR2)
(190)
Offset
Access: User read/write
1 0
0x2B
7
TOI
0
6
0
5
0
4
0
3
TCRE
0
2
PR2
0
R
PR1
0
PR0
0
W
Reset
0
0
0
Notes
190. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 214. TIE - register field descriptions
Field
Description
Timer Overflow Interrupt Enable
1 = Hardware interrupt requested when TOF flag set in TFLG2 register.
0 = Hardware Interrupt request inhibited.
7
TOI
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Table 214. TIE - register field descriptions
Field
Description
TCRE — Timer Counter Reset Enable
3
1 = Enables timer counter reset by a successful output compare on channel 3
0 = Inhibits timer counter reset and counter continues to run.
TCRE
3-0
Timer Prescaler Select
PR[2:0]
These three bits select the frequency of the timer prescaler clock derived from the bus clock as shown in Table 215.
NOTE
This mode of operation is similar to an up-counting modulus counter.
If register TC3 = $0000 and TCRE = 1, the timer counter register (TCNT) will stay at $0000
continuously. If register TC3 = $FFFF and TCRE = 1, TOF will not be set when the timer counter
register (TCNT) is reset from $FFFF to $0000.
The newly selected prescale factor will not take effect until the next synchronized edge, where all
prescale counter stages equal zero.
Table 215. Timer clock selection
(191)
PR2
0
PR1
0
PR0
0
Timer Clock
TimerClk / 1
TimerClk / 2
TimerClk / 4
TimerClk / 8
TimerClk / 16
TimerClk / 32
TimerClk / 64
TimerClk / 128
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Notes
191. TimerClk = D2DCLK/4 or ALFCLK
4.10.3.3.12 Main timer interrupt flag 1 (TFLG1)
Table 216. Main timer interrupt flag 1 (TFLG1)
(192)
Offset
Access: User read/write
1 0
0x2C
7
0
6
0
5
0
4
0
3
C3F
0
2
C2F
0
R
W
C1F
0
C0F
0
Reset
0
0
0
0
Notes
192. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 217. TFLG1 - register field descriptions
Field
Description
Input Capture/Output Compare Channel Flag.
1 = Input capture or output compare event occurred
0 = No event (input capture or output compare event) occurred.
3-0
C[3:0]F
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NOTE
These flags are set when an input capture or output compare event occurs. Flag set on a particular
channel is cleared by writing a one to that corresponding CnF bit. Writing a zero to CnF bit has no
effect on its status. When TFFCA bit in TSCR register is set, a read from an input capture or a write
into an output compare channel will cause the corresponding channel flag CnF to be cleared.
4.10.3.3.13 Main timer interrupt flag 2 (TFLG2)
Table 218. Main timer interrupt flag 2 (TFLG2)
(193)
Offset
Access: User read/write
0x2D
7
TOF
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
Notes
193. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 219. TFLG2 - register field descriptions
Field
Description
Timer Overflow Flag
7
1 = Indicates that an interrupt has occurred (Set when 16-bit free-running timer counter overflows from $FFFF to $0000)
0 = Flag indicates an interrupt has not occurred.
TOF
NOTE
The TFLG2 register indicates when an interrupt has occurred. Writing a one to the TOF bit will clear
it. Any access to TCNT will clear TOF bit of TFLG2 register if the TFFCA bit in TSCR register is set.
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4.10.3.3.14 Timer input capture/output compare registers (TC3 - TC0)
Table 220. Timer input capture/output compare register 0 (TC0)
(194)
Offset
Access: User read/write
9 8
0x2E, 0x2F
15
14
13
12
11
10
R
W
tc0_15
tc0_14
tc0_13
tc0_12
tc0_11
tc0_10
tc0_9
tc0_8
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
tc0_7
0
tc0_6
0
tc0_5
0
tc0_4
0
tc0_3
0
tc0_2
0
tc0_1
0
tc0_0
0
Reset
Notes
194. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 221. Timer input capture/output compare register 1(TC1)
(195)
Offset
Access: User read/write
9 8
0x30, 0x31
15
14
13
12
11
10
R
tc1_15
tc1_14
tc1_13
tc1_12
tc1_11
tc1_10
tc1_9
tc1_8
W
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
tc1_7
0
tc1_6
0
tc1_5
0
tc1_4
0
tc1_3
0
tc1_2
0
tc1_1
0
tc1_0
0
Reset
Notes
195. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 222. Timer input capture/output compare register 2(TC2)
(196)
Offset
Access: User read/write
9 8
0x32, 0x33
15
14
13
12
11
10
R
tc2_15
tc2_14
tc2_13
tc2_12
tc2_11
tc2_10
tc2_9
tc2_8
W
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
tc2_7
0
tc2_6
0
tc2_5
0
tc2_4
0
tc2_3
0
tc2_2
0
tc2_1
0
tc2_0
0
Reset
Notes
196. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 223. Timer input capture/output compare register 3(TC3)
(197)
Offset
Access: User read/write
0x34, 0x35
15
14
13
12
11
10
9
8
R
tc3_15
tc3_14
tc3_13
tc3_12
tc3_11
tc3_10
tc3_9
tc3_8
W
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
tc3_7
0
tc3_6
0
tc3_5
0
tc3_4
0
tc3_3
0
tc3_2
0
tc3_1
0
tc3_0
0
Reset
Notes
197. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 224. TCn - register field descriptions
Field
Description
15-0
tcn[15-0]
16 Timer Input Capture/Output Compare Registers
NOTE
TRead anytime. Write anytime for output compare function. Writes to these registers have no effect
during input capture.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value
of the free-running counter when a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give
a different result.
4.10.4 Functional description
4.10.4.1 general
This section provides a complete functional description of the timer TIM16B4C block. Refer to the detailed timer block diagram in Figure 41
as necessary.
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D2D Clock / 4 or ALFCLK
channel 3 output
compare
PR[2:1:0]
TCRE
PRESCALER
CxI
TCNT(hi):TCNT(lo)
16-BIT COUNTER
CxF
CLEAR COUNTER
TOF
TOI
INTERRUPT
TOF
LOGIC
TE
CHANNEL 0
16-BIT COMPARATOR
TC0
C0F
C0F
CH. 0 CAPTURE
CH. 0 COMPARE
OM:OL0
IOC0 PIN
LOGIC
IOC0 PIN
TOV0
EDGE
DETECT
EDG0A EDG0B
IOC0
CHANNEL3
16-BIT COMPARATOR
TC3
C3F
C3F
CH.3 CAPTURE
CH.3 COMPARE
IOC3 PIN
LOGIC
OM:OL3
TOV3
IOC3 PIN
EDG3A
EDG3B
EDGE
DETECT
IOC3
Figure 41. Detailed timer block diagram
4.10.4.2 Prescaler
The prescaler divides the bus clock by 1, 2, 4, 8,16, 32, 64, or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0]
are in the timer system control register 2 (TSCR2).
4.10.4.3 Input capture
Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The input capture function captures the
time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value
in the timer counter into the timer channel registers, TCn.
The minimum pulse width for the input capture input is greater than two bus clocks. An input capture on channel n sets the CnF flag. The
CnI bit enables the CnF flag to generate interrupt requests.
4.10.4.4 Output compare
Setting the I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an
output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets the CnF flag. The CnI
bit enables the CnF flag to generate interrupt requests.
The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both OMn and OLn disconnects the
pin from the output logic. Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output compare
does not set the channel flag.
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A successful output compare on channel 3 overrides output compares on all other output compare channels. The output compare 3 mask
register masks the bits in the output compare 3 data register. The timer counter reset enable bit, TCRE, enables channel 3 output
compares to reset the timer counter.Writing to the timer port bit of an output compare pin does not affect the pin state. The value written
is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
4.10.5 Resets
4.10.5.1 General
The reset state of each individual bit is listed within the Register Description Section 4.10.3, “Memory map and registers", which details
the registers and their bit-fields.
4.10.6 Interrupts
4.10.6.1 General
This section describes interrupts originated by the TIM16B4C block. Table 225 lists the interrupts generated by the TIM16B4C to
communicate with the MCU.
Table 225. TIM16B4C interrupts
Interrupt
C[3:0]F
TOF
Offset
Vector
Priority
Source
Description
-
-
-
-
-
-
Timer Channel 3-0
Timer Overflow
Active high timer channel interrupts 3-0
Timer Overflow interrupt
4.10.6.2 Description of interrupt operation
The TIM16B4C uses a total of 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. More information
on interrupt vector offsets and interrupt numbers can be found in Section 4.4, “Interrupt module - IRQ".
Channel [3:0] Interrupt
These active high outputs is asserted by the module to request a timer channel 3 – 0 interrupt following an input capture or output compare
event on these channels [3-0]. For the interrupt to be asserted on a specific channel, the enable, CnI bit of TIE register should be set.
These interrupts are serviced by the system controller.
4.10.6.2.1
Timer overflow interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt, following the timer counter overflow when the
overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is serviced by the system controller.
4.11 General purpose I/O - GPIO
4.11.1 Introduction
The 3 General Purpose I/Os (PTB0...2) are multipurpose ports, making internal signals available externally and providing digital inputs.
L0 (PTB3) offers an additional wake-up on rising edge during low power mode.
Additional routing options allow connections to the LIN, TIMER, and SCI module.
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4.11.2 Features
•
•
•
•
•
•
Internal Clamping Structure to operate as High Voltage Input (PTB3/L0 only).
5.0 V (VDDX) digital port Input/Output (PTB3/L0 only as Input)
Selectable internal pull-up (PTB3/L0 pull-down) resistor
Selectable Wake-up Input during Low Power mode (PTB3/L0 - rising edge only).
Selectable Timer Channel Input / Output
Selectable connection to LIN / SCI
4.11.3 Block diagram
0
1
Z
PD3
PTB3 / L0
PDE3
PTWU
Wake-up Detection
TCAP3..0
VDDX
=1
PTBXx
LINRX
TX
LIN
RX
SCITX
PUEx
IC
TCOMP3..0
WKUP
TIMER3..0
Z
OC
PTBx
PTB0..PTB2
(x = 2..0)
Internal Wake-up
DIRx (M)
PDx
TCAP3..0
SCIRX
LINTX
TX
SCI
RX
Figure 42. General purpose I/O - block diagram
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4.11.4 High voltage wake-up input - PTB3 / L0
To offer robust high voltage wake-up capabilities, the following structure is implemented for PTB3/L0.
47k
1k
2k
ESD
47n
1p
100k
6V clamp
ESD / clamp
External
Input
components
buffer
Figure 43. L0 / PTB3 input structure (typical values indicated)
NOTE
Due the different implementation of the L0/PTB3, the PTWU bit needs to be set in the GPIO_IN3
register, to read the port status PD3 during Normal mode.
4.11.4.1 Modes of operation
The full GPIO functionality is only available during Normal mode. The only features in available in both low power modes is the PTB3/L0
external wake-up and the wake-up routing of the timer output compare.
NOTE
TCOMP3...0 needs to be configured to allow timer output compare interrupts to generate a system
wake-up.
4.11.5 Memory map and registers
4.11.5.1 Overview
This section provides a detailed description of the memory map and registers.
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4.11.5.2 Module memory map
The memory map for the GPIO module is given in Table 63
Table 226. Module memory map
Offset
Name
7
6
5
4
3
2
1
0
(198), (199)
R
W
R
0
0
0
0
0
0
0
0
DIR2M
DIR1M
DIR0M
PE3M
PE2M
PE1M
PE0M
GPIO_CTL
GPIO control register
0x40
0
0
0
0
DIR2
0
DIR1
0
DIR0
0
PE3
PE2
PE1
PE0
W
R
GPIO_PUC
GPIO pull up configuration
GPIO_DATA
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
PDE3
PD3
PUE2
PD2
PUE1
PD1
PUE0
PD0
W
R
0
0
0
GPIO port data register
GPIO_IN0
W
R
0
TCAP3
TCAP2
TCAP1
TCAP0
SCIRX
SCITX
SCIRX
SCITX
SCIRX
SCITX
LINTX
LINRX
LINTX
LINRX
LINTX
Port 0 input configuration
GPIO_OUT0
W
R
0
PTBX0
0
WKUP
0
TCOMP3 TCOMP2 TCOMP1 TCOMP0
Port 0 output configuration
GPIO_IN1
W
R
TCAP3
TCAP2
TCAP1
TCAP0
Port 1 input configuration
GPIO_OUT1
W
R
0
PTBX1
0
WKUP
0
TCOMP3 TCOMP2 TCOMP1 TCOMP0
Port 1 output configuration
GPIO_IN2
W
R
TCAP3
TCAP2
TCAP1
TCAP0
Port 2 input configuration
GPIO_OUT2
W
R
0
PTBX2
0
WKUP
TCOMP3 TCOMP2 TCOMP1 TCOMP0
LINRX
0
Port 2 output configuration
GPIO_IN3
W
R
PTWU
0
PTWU
0
TCAP3
0
TCAP2
0
TCAP1
0
TCAP0
0
Port 3 input configuration
W
R
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
0x4F
W
Notes
198. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
199. Register Offset with the “lo” address value not shown have to be accessed in 16-Bit mode. 8-Bit access will not function.
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4.11.5.3 Register descriptions
4.11.5.3.1
GPIO control register (GPIO_CTL)
Table 227. GPIO control register (GPIO_CTL)
Offset
Access: User read/write
0x40
(200),(201)
15
0
14
13
12
11
10
9
8
R
W
0
0
0
0
0
0
0
DIR2M
DIR1M
DIR0M
PE3M
PE2M
PE1M
PE0M
Reset
0
7
0
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
DIR2
0
DIR1
0
DIR0
0
PE3
0
PE2
0
PE1
0
PE0
0
Reset
0
Notes
200. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
201. Those Registers are 16-Bit access only.
Table 228. GPIO control register (GPIO_CTL)
Field
Description
Data Direction PTB2 - Mask
0 - writing the DIR2 bit will have no effect
1 - writing the DIR2 bit will be effective
14
DIR2M
Data Direction PTB1 - Mask
0 - writing the DIR1 bit will have no effect
1 - writing the DIR1 bit will be effective
13
DIR1M
Data Direction PTB0 - Mask
0 - writing the DIR0 bit will have no effect
1 - writing the DIR0 bit will be effective
12
DIR0M
Port 3 Enable - Mask
0 - writing the PE3 bit will have no effect
1 - writing the PE3 bit will be effective
11
PE3M
Port 2 Enable - Mask
0 - writing the PE2 bit will have no effect
1 - writing the PE2 bit will be effective
10
PE2M
Port 1 Enable - Mask
0 - writing the PE1 bit will have no effect
1 - writing the PE1 bit will be effective
9
PE1M
Port 0 Enable - Mask
0 - writing the PE0 bit will have no effect
1 - writing the PE0 bit will be effective
8
PE0M
Data Direction PTB2
0 - PTB2 configured as Input
1 - PTB2 configured as Output
6
DIR2
Data Direction PTB1
0 - PTB1 configured as Input
1 - PTB1 configured as Output
5
DIR1
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Table 228. GPIO control register (GPIO_CTL) (continued)
Field
Description
Data Direction PTB0
4
0 - PTB0 configured as Input
DIR0
1 - PTB0 configured as Output
(202)
Port 3 Enable
3
PE3
0 - PTB3 Disabled (Z state)
1 - PTB3 Enabled (I)
(202)
Port 2 Enable
2
0 - PTB2 disabled (Z state)
PE2
1 - PTB2 enabled (I/O)
(202)
Port 1 Enable
1
0 - PTB1 disabled (Z state)
PE1
1 - PTB1 enabled (I/O)
(202)
Port 0 Enable
0
PE0
0 - PTB0 disabled (Z state)
1 - PTB0 enabled (I/O)
Notes
202. The port logic is always enabled. Setting PEx will connect the logic to the port I/O buffers.
4.11.5.3.2
GPIO pull-up configuration (GPIO_PUC)
Table 229. GPIO pull-up configuration (GPIO_PUC)
(203)
Offset
Access: User read/write
1 0
0x42
7
0
6
0
5
0
4
0
3
PDE3
0
2
PUE2
0
R
PUE1
0
PUE0
0
W
Reset
0
0
0
0
Notes
203. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 230. GPIO pull-up configuration (GPIO_PUC)
Field
Description
PTB3 Pull-down Enable
0 - PTB3 pull-down disabled
1 - PTB3 pull-down enabled
3
PDE3
PTB2 Pull-up Enable
0 - PTB2 pull-up disabled
1 - PTB2 pull-up enabled
2
PUE2
PTB1 Pull-up Enable
0 - PTB1 pull-up disabled
1 - PTB1 pull-up enabled
1
PUE1
PTB0 Pull-up Enable
0 - PTB0 pull-up disabled
1 - PTB0 pull-up enabled
0
PUE0
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4.11.5.3.3
GPIO port data register (GPIO_DATA)
Table 231. GPIO port data register (GPIO_DATA)
(204)
Offset
Access: User read
0x43
7
0
6
0
5
0
4
0
3
2
1
0
(205)
R
PD3
PD2
PD1
PD0
W
Notes
204. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
205. Due the different implementation of the L0/PTB3, PTWU needs to be set in the GPIO_IN3 to read the PD3 port status during normal mode.
Table 232. GPIO port data register (GPIO_DATA)
Field
Description
3
PTB3 Data Register
PD3
A read returns the value of the PTB3 buffer.
2
PTB2 Data Register
PD2
A read returns the value of the PTB2 buffer.
1
PTB1 Data Register
PD1
A read returns the value of the PTB1 buffer.
0
PTB0 Data Register
PD0
A read returns the value of the PTB0 buffer.
4.11.5.3.4
Port 0 input configuration (GPIO_IN0)
Table 233. Port 0 input configuration (GPIO_IN0)
(206)
Offset
Access: User read/write
0x44
7
0
6
TCAP3
0
5
TCAP2
0
4
TCAP1
0
3
TCAP0
0
2
SCIRX
0
1
0
0
R
LINTX
0
W
Reset
0
0
Notes
206. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 234. Port 0 input configuration (GPIO_IN0)
Field
Description
PTB0 - Timer Input Capture Channel 3
0 - PTB0 Input buffer disconnected from Timer Channel 3 - Input Capture
1 - PTB0 Input buffer routed to Timer Channel 3 - Input Capture
6
TCAP3
PTB0 - Timer Input Capture Channel 2
0 - PTB0 Input buffer disconnected from Timer Channel 2 - Input Capture
1 - PTB0 Input buffer routed to Timer Channel 2 - Input Capture
5
TCAP2
PTB0 - Timer Input Capture Channel 1
0 - PTB0 Input buffer disconnected from Timer Channel 1 - Input Capture
1 - PTB0 Input buffer routed to Timer Channel 1 - Input Capture
4
TCAP1
PTB0 - Timer Input Capture Channel 0
0 - PTB0 Input buffer disconnected from Timer Channel 0 - Input Capture
1 - PTB0 Input buffer routed to Timer Channel 0 - Input Capture
3
TCAP0
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Table 234. Port 0 input configuration (GPIO_IN0) (continued)
Field
Description
PTB0 - SCI Module Rx Input
2
0 - PTB0 Input buffer disconnected from SCI Module Rx Input
1 - PTB0 Input buffer routed to SCI Module Rx Input
SCIRX
PTB0 - LIN Module Tx Input
0 - PTB0 Input buffer disconnected from LIN Module Tx Input
1 - PTB0 Input buffer routed to LIN Module Tx Input
1
LINTX
4.11.5.3.5
Port 0 output configuration (GPIO_OUT0)
Table 235. Port 0 output configuration (GPIO_OUT0)
(207)
Offset
Access: User read/write
0x45
7
6
TCOMP3
0
5
TCOMP2
0
4
TCOMP1
0
3
TCOMP0
0
2
SCITX
0
1
LINRX
0
0
R
W
0
PTBX0
0
WKUP
0
Reset
Notes
207. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 236. Port 0 output configuration (GPIO_OUT0)
Field
Description
PTB0 - Wake-up output
0 - Internal wake-up signal disconnected from PTB0 output buffer OR gate
1 - Internal wake-up signal connected to PTB0 output buffer OR gate
7
WKUP
PTB0 - Timer Channel 3 - Output Compare output
0 - Timer Channel 3 - output compare disconnected from PTB0 output buffer OR gate
1 - Timer Channel 3 - output compare connected to PTB0 output buffer OR gate
6
TCOMP3
PTB0 - Timer Channel 2 - Output Compare output
0 - Timer Channel 2 - output compare disconnected from PTB0 output buffer OR gate
1 - Timer Channel 2 - output compare connected to PTB0 output buffer OR gate
5
TCOMP2
PTB0 - Timer Channel 1 - Output Compare output
0 - Timer Channel 1 - output compare disconnected from PTB0 output buffer OR gate
1 - Timer Channel 1 - output compare connected to PTB0 output buffer OR gate
4
TCOMP1
PTB0 - Timer Channel 0 - Output Compare output
0 - Timer Channel 0 - output compare disconnected from PTB0 output buffer OR gate
1 - Timer Channel 0 - output compare connected to PTB0 output buffer OR gate
3
TCOMP0
PTB0 - SCI TX Output
0 - SCI TX output disconnected from PTB0 output buffer OR gate
1 - SCI TX output connected to PTB0 output buffer OR gate
2
SCITX
PTB0 - LIN RX Output
0 - LIN RX output disconnected from PTB0 output buffer OR gate
1 - LIN RX output connected to PTB0 output buffer OR gate
1
LINRX
PTB0 - Output Buffer Control
0 - PTB0 output buffer OR gate input = 0
1 - PTB0 output buffer OR gate input = 1
0
PTBX0
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4.11.5.3.6
Port 1 input configuration (GPIO_IN1)
Table 237. Port 1 input configuration (GPIO_IN1)
(208)
Offset
Access: User read/write
0x46
7
0
6
TCAP3
0
5
TCAP2
0
4
TCAP1
0
3
TCAP0
0
2
SCIRX
0
1
LINTX
0
0
R
W
Reset
0
0
Notes
208. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 238. Port 1 input configuration (GPIO_IN1)
Field
Description
PTB1 - Timer Input Capture Channel 3
0 - PTB1 Input buffer disconnected from Timer Channel 3 - Input Capture
1 - PTB1 Input buffer routed to Timer Channel 3 - Input Capture
6
TCAP3
PTB1 - Timer Input Capture Channel 2
0 - PTB1 Input buffer disconnected from Timer Channel 2 - Input Capture
1 - PTB1 Input buffer routed to Timer Channel 2 - Input Capture
5
TCAP2
PTB1 - Timer Input Capture Channel 1
0 - PTB1 Input buffer disconnected from Timer Channel 1 - Input Capture
1 - PTB1 Input buffer routed to Timer Channel 1 - Input Capture
4
TCAP1
PTB1 - Timer Input Capture Channel 0
0 - PTB1 Input buffer disconnected from Timer Channel 0 - Input Capture
1 - PTB1 Input buffer routed to Timer Channel 0 - Input Capture
3
TCAP0
PTB1 - SCI Module Rx Input
0 - PTB1 Input buffer disconnected from SCI Module Rx Input
1 - PTB1 Input buffer routed to SCI Module Rx Input
2
SCIRX
PTB1 - LIN Module Tx Input
0 - PTB1 Input buffer disconnected from LIN Module Tx Input
1 - PTB1 Input buffer routed to LIN Module Tx Input
1
LINTX
4.11.5.3.7
Port 1 output configuration (GPIO_OUT1)
Table 239. Port 1 output configuration (GPIO_OUT1)
(209)
Offset
Access: User read/write
0x47
7
6
TCOMP3
0
5
TCOMP2
0
4
TCOMP1
0
3
TCOMP0
0
2
SCITX
0
1
0
0
R
WKUP
0
LINRX
0
W
PTBX1
0
Reset
Notes
209. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 240. Port 1 output configuration (GPIO_OUT1)
Field
Description
PTB1 - Wake-up output
7
0 - Internal wake-up signal disconnected from PTB1 output buffer OR gate
1 - Internal wake-up signal connected to PTB1 output buffer OR gate
WKUP
PTB1 - Timer Channel 3 - Output Compare output
0 - Timer Channel 3 - output compare disconnected from PTB1 output buffer OR gate
1 - Timer Channel 3 - output compare connected to PTB1 output buffer OR gate
6
TCOMP3
PTB1 - Timer Channel 2 - Output Compare output
0 - Timer Channel 2 - output compare disconnected from PTB1 output buffer OR gate
1 - Timer Channel 2 - output compare connected to PTB1 output buffer OR gate
5
TCOMP2
PTB1 - Timer Channel 1 - Output Compare output
0 - Timer Channel 1 - output compare disconnected from PTB1 output buffer OR gate
1 - Timer Channel 1 - output compare connected to PTB1 output buffer OR gate
4
TCOMP1
PTB1 - Timer Channel 0 - Output Compare output
0 - Timer Channel 0 - output compare disconnected from PTB1 output buffer OR gate
1 - Timer Channel 0 - output compare connected to PTB1 output buffer OR gate
3
TCOMP0
PTB1 - SCI TX Output
0 - SCI TX output disconnected from PTB1 output buffer OR gate
1 - SCI TX output connected to PTB1 output buffer OR gate
2
SCITX
PTB1 - LIN RX Output
0 - LIN RX output disconnected from PTB1 output buffer OR gate
1 - LIN RX output connected to PTB1 output buffer OR gate
1
LINRX
PTB1 - Output Buffer Control
0 - PTB1 output buffer OR gate input = 0
1 - PTB1 output buffer OR gate input = 1
0
PTBX1
4.11.5.3.8
Port 2 input configuration (GPIO_IN2)
Table 241. Port 2 input configuration (GPIO_IN2)
(210)
Offset
Access: User read/write
0x48
7
0
6
TCAP3
0
5
TCAP2
0
4
TCAP1
0
3
TCAP0
0
2
SCIRX
0
1
0
0
R
LINTX
0
W
Reset
0
0
Notes
210. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 242. Port 2 input configuration (GPIO_IN2)
Field
Description
PTB2 - Timer Input Capture Channel 3
0 - PTB2 Input buffer disconnected from Timer Channel 3 - Input Capture
1 - PTB2 Input buffer routed to Timer Channel 3 - Input Capture
6
TCAP3
PTB2 - Timer Input Capture Channel 2
0 - PTB2 Input buffer disconnected from Timer Channel 2 - Input Capture
1 - PTB2 Input buffer routed to Timer Channel 2 - Input Capture
5
TCAP2
PTB2 - Timer Input Capture Channel 1
0 - PTB2 Input buffer disconnected from Timer Channel 1 - Input Capture
1 - PTB2 Input buffer routed to Timer Channel 1 - Input Capture
4
TCAP1
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Table 242. Port 2 input configuration (GPIO_IN2) (continued)
Field
Description
PTB2 - Timer Input Capture Channel 0
3
0 - PTB2 Input buffer disconnected from Timer Channel 0 - Input Capture
1 - PTB2 Input buffer routed to Timer Channel 0 - Input Capture
TCAP0
PTB2 - SCI Module Rx Input
0 - PTB2 Input buffer disconnected from SCI Module Rx Input
1 - PTB2 Input buffer routed to SCI Module Rx Input
2
SCIRX
PTB2 - LIN Module Tx Input
0 - PTB2 Input buffer disconnected from LIN Module Tx Input
1 - PTB2 Input buffer routed to LIN Module Tx Input
1
LINTX
4.11.5.3.9
Port 2 output configuration (GPIO_OUT2)
Table 243. Port 2 output configuration (GPIO_OUT2)
(210)
Offset
Access: User read/write
0x49
7
6
TCOMP3
0
5
TCOMP2
0
4
TCOMP1
0
3
TCOMP0
0
2
SCITX
0
1
LINRX
0
0
R
0
PTBX2
0
WKUP
0
W
Reset
Notes
211. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 244. Port 2 output configuration (GPIO_OUT2)
Field
Description
PTB2 - Wake-up output
0 - Internal wake-up signal disconnected from PTB2 output buffer OR gate
1 - Internal wake-up signal connected to PTB2 output buffer OR gate
7
WKUP
PTB2 - Timer Channel 3 - Output Compare output
0 - Timer Channel 3 - output compare disconnected from PTB2 output buffer OR gate
1 - Timer Channel 3 - output compare connected to PTB2 output buffer OR gate
6
TCOMP3
PTB2 - Timer Channel 2 - Output Compare output
0 - Timer Channel 2 - output compare disconnected from PTB2 output buffer OR gate
1 - Timer Channel 2 - output compare connected to PTB2 output buffer OR gate
5
TCOMP2
PTB2 - Timer Channel 1 - Output Compare output
0 - Timer Channel 1 - output compare disconnected from PTB2 output buffer OR gate
1 - Timer Channel 1 - output compare connected to PTB2 output buffer OR gate
4
TCOMP1
PTB2 - Timer Channel 0 - Output Compare output
0 - Timer Channel 0 - output compare disconnected from PTB2 output buffer OR gate
1 - Timer Channel 0 - output compare connected to PTB2 output buffer OR gate
3
TCOMP0
PTB2 - SCI TX Output
0 - SCI TX output disconnected from PTB2 output buffer OR gate
1 - SCI TX output connected to PTB2 output buffer OR gate
2
SCITX
PTB2 - LIN RX Output
0 - LIN RX output disconnected from PTB2 output buffer OR gate
1 - LIN RX output connected to PTB2 output buffer OR gate
1
LINRX
PTB2 - Output Buffer Control
0 - PTB2 output buffer OR gate input = 0
1 - PTB2 output buffer OR gate input = 1
0
PTBX2
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4.11.5.3.10 Port 3 input configuration (GPIO_IN3)
Table 245. Port 3 input configuration (GPIO_IN3)
(212)
Offset
Access: User read/write
0x4A
7
6
TCAP3
0
5
TCAP2
0
4
TCAP1
0
3
TCAP0
0
2
0
1
0
0
0
R
PTWU
0
W
Reset
0
0
0
Notes
212. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 246. Port 3 input configuration (GPIO_IN3)
Field
Description
PTB3 Wake-up
7
0 - PTB3 Input buffer low power mode wake-up circuity disabled
1 - PTB3 Input buffer low power mode wake-up circuity enabled
PTWU
PTB3 - Timer Input Capture Channel 3
0 - PTB3 Input buffer disconnected from Timer Channel 3 - Input Capture
1 - PTB3 Input buffer routed to Timer Channel 3 - Input Capture
6
TCAP3
PTB3 - Timer Input Capture Channel 2
0 - PTB3 Input buffer disconnected from Timer Channel 2 - Input Capture
1 - PTB3 Input buffer routed to Timer Channel 2 - Input Capture
5
TCAP2
PTB3 - Timer Input Capture Channel 1
0 - PTB3 Input buffer disconnected from Timer Channel 1 - Input Capture
1 - PTB3 Input buffer routed to Timer Channel 1 - Input Capture
4
TCAP1
PTB3 - Timer Input Capture Channel 0
0 - PTB3 Input buffer disconnected from Timer Channel 0 - Input Capture
1 - PTB3 Input buffer routed to Timer Channel 0 - Input Capture
3
TCAP0
4.12 LIN
4.12.1 Introduction
The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to
meet the LIN physical layer version 2.0 / 2.1 and J2602 specification, and has the following features:
•
•
•
•
•
•
•
•
LIN physical layer 2.0 / 2.1 / J2602 compliant
Slew rate selection 20 kBit, 10 kBit, and fast Mode (100 kBit)
Overtemperature Shutdown - HTI
Permanent Pull-up in Normal mode 30 k, 1.0 M in low power
Current limitation
Special J2602 compliant configuration
Direct Rx / Tx access
Optional external Rx / Tx access and routing to the TIMER Input through PTBx
The LIN driver is a low side MOSFET with current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure
is integrated, so no external pull-up components are required for the application in a slave node. The fall time from dominant to recessive
and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed.
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4.12.2 Overview
4.12.2.1 Block diagram
Figure 44 shows the basic function of the LIN module.
VSUP
UV
Under-
voltage
Wake Up
LVSD (M)
Detection
DSER
Wake-up
Filter
RSLAVE
TOPTB
TOSCI
RX
LIN
Receiver
SCI
=1
TX
FROMSCI
PTB
0
1
FROMPTB
TXDM (M)
LGND
SRS (M)[1:0]
RDY
Transmitter
Control
Over-
temperature
Detection
OTIE (M)
OT
EN (M)
Interrupt
Figure 44. LIN module block diagram
4.12.2.2 LIN pin
The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbances.
See Section 3.8, “Electromagnetic compatibility (EMC)".
4.12.2.3 Slew rate selection
The slew rate can be selected for optimized operation at 10 kBit/s and 20 kBit/s as well as a fast baud rate (100 kBit) for test and
programming. The slew rate can be adapted with the bits SRS[1:0] in the LIN Control Register (LIN_CTL). The initial slew rate is 20 kBit/s.
4.12.2.4 Overtemperature shutdown (LIN interrupt)
The output low side FET (transmitter) is protected against overtemperature conditions. In an overtemperature condition, the transmitter
will be shut down, and the TO bit in the LIN Control Register (LIN_CTL) is set as long as the condition is present.
If the OTIEM bit is set in the LIN Status Register (LIN_SR), an Interrupt IRQ will be generated. Acknowledge the interrupt by writing a “1”
in the LIN Status Register (LIN_SR). To issue a new interrupt, the condition has to vanish and reoccur.
The transmitter is automatically re-enabled once the overtemperature condition is gone and TxD is High.
4.12.2.5 Low power mode and wake-up feature
During Low Power mode operation, the transmitter of the physical layer is disabled. The receiver is still active and able to detect wake-up
events on the LIN bus line.
A dominant level longer than t
Register (WSR).
, followed by a rising edge will generate a wake-up event and be reported in the Wake-up Source
PROPWL
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4.12.2.6 J2602 compliance
A Low Voltage Shutdown feature was implemented to allow controlled LIN driver behavior under low voltage conditions at VSUP. If LVSD
is set, once VSUP is below the threshold VJ2602H, the LIN transmitter is not turned dominant again. The condition is indicated by the UV
flag.
4.12.2.7 Transmit/receiving line definition
The LIN module can be connected to the SCI or PTB module, or can be directly controlled by the TXDM / RX bit
4.12.2.8 Transmitter enable/ready
The LIN transmitter must be enabled before transmission is possible (EN). The RDY bit is set to 1 about 50 µs after the LIN transmitter is
enabled. This is due to the initialization time for the LIN transmitter, under some low voltage conditions.
During this period (LIN enabled to RDY = 1), the LIN is forced to a recessive state.
4.12.3 Memory map and registers
4.12.3.1 Overview
This section provides a detailed description of the memory map and registers.
4.12.3.2 Module memory map
The memory map for the LIN module is given in Table 63
Table 247. Module memory map
Offset
Name
7
6
5
4
3
2
1
0
(213),(214)
R
W
R
0
0
0
0
0
0
0
0
OTIEM
TXDM
LVSDM
ENM
SRSM
SRS
LIN_CTL
LIN control register
0x50
0
0
0
0
0
0
0
0
HF
0
OTIE
OT
TXD
0
LVSD
UV
EN
0
W
R
LIN_SR (hi)
LIN status register
LIN_SR (lo)
0
0
0x52
0x53
0x54
0x55
0x56
W
R
Write 1 will clear the flags
RDY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RX
TX
LIN status register
LIN_TX
W
R
0
0
0
0
0
FROMPT
B
FROMSCI
LIN transmit line definition
LIN_RX
W
R
0
TOPTB
0
TOSCI
0
LIN receive line definition
W
R
0
Reserved
Reserved
W
R
0
0
0
0x57
W
Notes
213. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
214. This Register is 16-Bit access only.
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4.12.3.3 Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of the register bit and field function follow the register diagrams, in bit order.
4.12.3.3.1
LIN control register (LIN_CTL)
Table 248. LIN control register (LIN_CTL)
Offset
Access: User write
0x50
(215) ,(216)
15
0
14
0
13
0
12
11
10
0
9
0
8
R
W
0
0
0
OTIEM
TXDM
LVSDM
ENM
0
SRSM
Reset
0
7
0
6
0
0
5
0
0
4
0
3
0
1
0
0
2
R
W
OTIE
0
TXD
0
LVSD
0
EN
0
SRS
Reset
0
0
0
0
Notes
215. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
216. This Register is 16-Bit access only.
Table 249. LIN control register (LIN_CTL) - register field descriptions
Field
Description
LIN Overtemperature Interrupt Enable - Mask
0 - writing the OTIE Bit will have no effect
1 - writing the OTIE Bit will be effective
15
OTIEM
IN - Direct Transmitter Control - Mask
0 - writing the TXD Bit will have no effect
1 - writing the TXD Bit will be effective
12
TXDM
LIN - Low Voltage Shutdown Disable (J2602 Compliance Control) - Mask
0 - writing the LVSD Bit will have no effect
1 - writing the LVSD Bit will be effective
11
LVSDM
LIN Module Enable - Mask
0 - writing the EN Bit will have no effect
1 - writing the EN Bit will be effective
10
ENM
LIN - Slew Rate Select - Mask
00,01,10 - writing the SRS Bits will have no effect
11 - writing the SRS Bits will be effective
9-8
SRSM[1:0]
LIN Overtemperature Interrupt Enable
0 - LIN overtemperature interrupt disabled
1 - LIN overtemperature interrupt enabled
7
OTIE
IN - Direct Transmitter Control
0 - Transmitter not controlled
1 - Transmitter dominant
4
TXD
LIN - Low Voltage Shutdown Disable (J2602 Compliance Control)
3
0 - LIN will be remain in recessive state in case of V
undervoltage condition
SUP
LVSD
1 - LIN will stay functional even with a V
undervoltage condition
SUP
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Table 249. LIN control register (LIN_CTL) - register field descriptions (continued)
Field
Description
LIN Module Enable
0 - LIN module disabled
1 - LIN module enabled
2
EN
LIN - Slew Rate Select
00 - Normal slew rate (20 kBit)
01 - Slow slew rate (10.4 kBit)
10 - Fast slew rate (100 kbit)
11 - normal Slew Rate (20 kBit)
1-0
SRS[1:0]
4.12.3.3.2
LIN status register (LIN_SR (hi))
Table 250. LIN status register (LIN_SR (hi))
(217)
Offset
Access: User read/write
0x52
7
6
0
5
4
0
3
2
0
1
0
0
R
W
OT
HF
UV
0
Write 1 will clear the flags
Reset
0
0
0
0
0
0
0
0
Notes
217. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 251. LIN status register (LIN_SR (hi)) - register field descriptions
Field
Description
LIN Overtemperature Status. This bit is latched and has to be reset by writing 1 into OT bit.
0 - No LIN overtemperature condition detected
1 - LIN overtemperature condition detected
7
OT
LIN HF (High Frequency) Condition Status indicating HF (DPI) disturbance in the LIN module. This bit is latched and has to be reset by
writing 1 into HF bit.
5
0 - No LIN HF (DPI) condition detected
1 - LIN HF (DPI) condition detected
HF
LIN Undervoltage Status. This threshold is used for the J2602 feature as well. This bit is latched and has to be reset by writing 1 into
UV bit.
3
0 - No LIN undervoltage condition detected
1 - LIN undervoltage condition detected
UV
4.12.3.3.3
LIN status register (LIN_SR (lo))
Table 252. LIN status register (LIN_SR (lo))
(218)
Offset
Access: User read
0x53
7
6
0
5
0
4
0
3
0
2
0
1
0
R
RDY
RX
TX
W
Notes
218. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 253. LIN status register (LIN_SR (lo)) - register field descriptions
Field
Description
Transmitter Ready Status
0 - Transmitter not ready
1 - Transmitter ready
1
RDY
Current RX status
0 - Rx recessive
1 - Rx dominant
1
RX
Current TX status
0 - Tx recessive
1 - Tx dominant
0
TX
4.12.3.3.4
LIN transmit line definition (LIN_TX)
Table 254. LIN transmit line definition (LIN_TX)
(219)
Offset
Access: User read/write
0x54
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
FROMPTB
FROMSCI
W
Reset
0
0
0
0
0
0
0
0
Notes
219. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 255. LIN transmit line definition (LIN_TX) - register field descriptions
Field
Description
(220)
LIN_TX internally routed from PTB. See Section 4.11, “General purpose I/O - GPIO" for details.
0 - LIN transmitter disconnected from PTB module.
1
FROMPTB
1 - LIN transmitter connected to the PTB module.
(220)
LIN_TX internally routed from SCI
0
0 - LIN transmitter disconnected from SCI module.
1 - LIN transmitter connected to the SCI module.
FROMSCI
Notes
220. In case both, FROMPTB and FROMSCI are selected, the SCI has priority and the PTB signal is ignored. In any case, the signal is logically ORed
with the TXD direct transmitter control.
4.12.3.3.5
LIN receive line definition (LIN_RX)
Table 256. LIN receive line definition (LIN_RX)
(221)
Offset
Access: User read/write
1 0
0x55
7
0
6
0
5
0
4
0
3
0
2
0
R
W
TOPTB
0
TOSCI
0
Reset
0
0
0
0
0
0
Notes
221. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 257. LIN receive line definition (LIN_RX) - register field descriptions
Field
Description
LIN_RX internally routed to PTB
0 - LIN receiver disconnected from PTB module.
1 - LIN receiver connected to the PTB module.
1
TOPTB
LIN_RX internally routed to SCI
0 - LIN receiver disconnected from SCI module.
1 - LIN receiver connected to the SCI module.
0
TOSCI
NOTE
In order to route the RX signal to the Timer Input capture, one of the PTBx must be configured as a
pass through.
Figure 45. Definition of LIN bus timing parameters
4.13 Serial communication interface (S08SCIV4)
4.13.1 Introduction
4.13.1.1 Features
Features of SCI module include:
•
•
•
•
Full-duplex, standard non-return-to-zero (NRZ) format
Double-buffered transmitter and receiver with separate enables
Programmable baud rates (13-bit modulo divider)
Interrupt-driven or polled operation:
—
—
—
—
—
—
Transmit data register empty and transmission complete
Receive data register full
Receive overrun, parity error, framing error, and noise error
Idle receiver detect
Active edge on receive pin
Break detect supporting LIN
•
Hardware parity generation and checking
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•
•
•
•
Programmable 8-bit or 9-bit character length
Receiver wake-up by idle-line or address-mark
Optional 13-bit break character generation / 11-bit break character detection
Selectable transmitter output polarity
4.13.1.2 Modes of operation
See Section 4.13.3, “Functional description", for details concerning SCI operation in these modes:
•
•
•
8- and 9-bit data modes
Loop mode
Single-wire mode
4.13.1.3 Block diagram
Figure 46 shows the transmitter portion of the SCI.
INTERNAL BUS
(WRITE-ONLY)
SCID – Tx BUFFER
LOOPS
RSRC
LOOP
CONTROL
TO RECEIVE
DATA IN
11-BIT TRANSMIT SHIFT REGISTER
M
TO TxD
H
8
7
6
5
4
3
2
1
0
L
1 BAUD
RATE CLOCK
SHIFT DIRECTION
TXINV
T8
PE
PARITY
GENERATION
PT
SCI CONTROLS TxD
TxD DIRECTION
TE
SBK
TO TxD
LOGIC
TRANSMIT CONTROL
TXDIR
BRK13
TDRE
TIE
Tx INTERRUPT
REQUEST
TC
TCIE
Figure 46. SCI transmitter block diagram
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Figure 47 shows the receiver portion of the SCI.
INTERNAL BUS
(READ-ONLY)
SCID – Rx BUFFER
16 BAUD
RATE CLOCK
DIVIDE
BY 16
FROM
TRANSMITTER
11-BIT RECEIVE SHIFT REGISTER
LOOPS
SINGLE-WIRE
M
LOOP CONTROL
RSRC
LBKDE
H
8
7
6
5
4
3
2
1
0
L
FROM RxD
RXINV
DATA RECOVERY
SHIFT DIRECTION
WAKEUP
LOGIC
ILT
RWU
RWUID
ACTIVE EDGE
DETECT
RDRF
RIE
IDLE
ILIE
Rx INTERRUPT
REQUEST
LBKDIF
LBKDIE
RXEDGIF
RXEDGIE
OR
ORIE
FE
FEIE
ERROR INTERRUPT
REQUEST
NF
NEIE
PE
PT
PARITY
CHECKING
PF
PEIE
Figure 47. SCI receiver block diagram
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4.13.2 Memory map and registers
4.13.2.1 Overview
This section provides a detailed description of the memory map and registers.
4.13.2.2 Module memory map
The memory map for the S08SCIV4 module is given in Table 63.
Table 258. Module memory map
(
Offset
Name
7
6
5
4
3
2
1
0
222)
SCIBD (hi)
SCI Baud Rate Register
SCIBD (lo)
R
W
R
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
SBR7
SBR6
0
SBR5
RSRC
SBR4
M
SBR3
0
SBR2
ILT
SBR1
PE
SBR0
PT
SCI Baud Rate Register
SCIC1
W
R
LOOPS
SCI Control Register 1
SCIC2
W
R
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
SCI Control Register 2
SCIS1
W
R
TDRE
RDRF
IDLE
OR
SCI Status Register 1
SCIS2
W
R
0
RAF
LBKDIF
R8
RXEDGIF
T8
RXINV
TXINV
RWUID
ORIE
BRK13
NEIE
LBKDE
FEIE
SCI Status Register 2
SCIC3
W
R
TXDIR
PEIE
SCI Control Register 3
SCID
W
R
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
0x1F
SCI Data Register
W
Notes
222. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.13.2.3 Register definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data.
4.13.2.3.1
SCI baud rate registers (SCIBD (hi), SCIBD (lo))
This pair of registers control the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first
write to SCIBD (hi) to buffer the high half of the new value, and then write to SCIBD (lo). The working value in SCIBD (hi) does not change
until SCIBD (lo) is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter
is enabled (RE or TE bits in SCIC2 are written to 1).
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Table 259. SCI baud rate register (SCIBD (hi))
(223)
Offset
Access: User read/write
0x18
7
6
RXEDGIE
0
5
0
4
SBR12
0
3
SBR11
0
2
SBR10
0
1
SBR9
0
0
SBR8
0
R
W
LBKDIE
0
Reset
0
= Unimplemented or Reserved
Notes
223. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 260. SCIBD (hi) field descriptions
Field
Description
LIN Break Detect Interrupt Enable (for LBKDIF)
7
0
1
Hardware interrupts from LBKDIF disabled (use polling).
Hardware interrupt requested when LBKDIF flag is 1.
LBKDIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
6
0
1
Hardware interrupts from RXEDGIF disabled (use polling).
Hardware interrupt requested when RXEDGIF flag is 1.
RXEDGIE
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the
SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI
baud rate = BUSCLK/(64BR). See BR bits in Table 261.
4:0
SBR[12:8]
Table 261. SCI baud rate register (SCIBDL)
(224)
Offset
Access: User read/write
1 0
0x19
7
SBR7
0
6
SBR6
0
5
SBR5
0
4
SBR4
0
3
SBR3
0
2
SBR2
1
R
SBR1
0
SBR0
0
W
Reset
Notes
224. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 262. SCIBDL field descriptions
Field
Description
Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the
SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI
baud rate = BUSCLK/(64BR). See also BR bits in Table 259.
7:0
SBR[7:0]
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4.13.2.3.2
SCI control register 1 (SCIC1)
This read/write register is used to control various optional features of the SCI system.
Table 263. SCI control register 1 (SCIC1)
(225)
Offset
Access: User read/write
1 0
0x1A
7
6
0
5
RSRC
0
4
M
0
3
0
2
ILT
0
R
W
LOOPS
0
PE
0
PT
0
Reset
0
0
Notes
225. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 264. SCIC1 field descriptions
Field
Description
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the transmitter output
is internally connected to the receiver input.
7
0
1
Normal operation — RxD and TxD use separate pins.
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not
used by SCI.
LOOPS
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input is
internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output.
5
0
1
Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
RSRC
9-Bit or 8-Bit Mode Select
4
M
0
1
Normal — start + 8 data bits (LSB first) + stop.
Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the
10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section 4.13.3.3.2.1, “Idle-line wake-up" for more
information.
2
ILT
0
1
Idle character bit count starts after start bit.
Idle character bit count starts after stop bit.
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data
character (eighth or ninth data bit) is treated as the parity bit.
1
0
1
No hardware parity generation or checking.
Parity enabled.
PE
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the
data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is
even.
0
PT
0
1
Even parity.
Odd parity.
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4.13.2.3.3
SCI control register 2 (SCIC2)
This register can be read or written at any time.
Table 265. SCI control register 2 (SCIC2)
(226)
Offset
Access: User read/write
0x1B
7
TIE
0
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
0
SBK
0
R
W
Reset
Notes
226. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 266. SCIC2 field descriptions
Field
Description
Transmit Interrupt Enable (for TDRE)
7
TIE
0
1
Hardware interrupts from TDRE disabled (use polling).
Hardware interrupt requested when TDRE flag is 1.
Transmission Complete Interrupt Enable (for TC)
6
0
1
Hardware interrupts from TC disabled (use polling).
Hardware interrupt requested when TC flag is 1.
TCIE
Receiver Interrupt Enable (for RDRF)
5
RIE
0
1
Hardware interrupts from RDRF disabled (use polling).
Hardware interrupt requested when RDRF flag is 1.
Idle Line Interrupt Enable (for IDLE)
4
ILIE
0
1
Hardware interrupts from IDLE disabled (use polling).
Hardware interrupt requested when IDLE flag is 1.
Transmitter Enable
0
1
Transmitter off.
Transmitter on.
TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI
communication line (TxD pin).
3
TE
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress. Refer to
Section 4.13.3.2.1, “Send break and queued idle" for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes
transmitting before allowing the pin to revert to a general-purpose I/O pin.
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1 the RxD pin
reverts to being a general-purpose I/O pin even if RE = 1.
2
0
1
Receiver off.
Receiver on.
RE
Receiver Wake-up Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic
hardware detection of a selected wake-up condition. The wake-up condition is either an idle line between messages (WAKE = 0, idle-line
wake-up), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wake-up). Application software sets RWU
and (normally) a selected hardware condition automatically clears RWU. Refer to Section 4.13.3.3.2, “Receiver wake-up operation" for
more details.
1
RWU
0
1
Normal SCI receiver operation.
SCI receiver in standby waiting for wake-up condition.
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10
or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the set and clear of SBK
relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to
Section 4.13.3.2.1, “Send break and queued idle" for more details.
0
SBK
0
1
Normal transmitter operation.
Queue break character(s) to be sent.
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4.13.2.3.4
SCI status register 1 (SCIS1)
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this
register) are used to clear these status flags.
Table 267. SCI status register 1 (SCIS1)
(227)
Offset
Access: User read/write
1 0
0x1C
7
6
5
4
3
2
R
TDRE
1
TC
RDRF
IDLE
OR
NF
FE
PF
W
Reset
1
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
227. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 268. SCIS1 field descriptions
Field
Description
Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer
to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIS1 with TDRE = 1 and then write to the
SCI data register (SCID).
7
TDRE
0
1
Transmit data register (buffer) full.
Transmit data register (buffer) empty.
Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being
transmitted.
0
1
Transmitter active (sending data, a preamble, or a break).
Transmitter idle (transmission activity complete).
6
TC
TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things:
•
•
•
Write to the SCI data register (SCID) to transmit new data
Queue a preamble by changing TE from 0 to 1
Queue a break character by writing 1 to SBK in SCIC2
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register
(SCID). If the OR bit is set, further received characters are lost and RDRF bit does not set. To clear RDRF, read SCIS1 with RDRF = 1
and then read the SCI data register (SCID).
5
RDRF
0
1
Receive data register empty.
Receive data register full.
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When ILT = 0, the
receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count
toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle
line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at
the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line.
4
To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been cleared, it cannot become set
again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains
idle for an extended period.
IDLE
0
1
No idle line detected.
Idle line was detected.
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the
previously received character has not been read from SCID yet. In this case, the new character (and all associated error information) is
lost because there is no room to move it into SCID. To clear OR, read SCIS1 with OR = 1 and then read the SCI data register (SCID).
3
OR
0
1
No overrun.
Receive overrun (new SCI data lost).
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each
data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF will
be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and then read the SCI data register (SCID).
2
NF
0
1
No noise detected.
Noise detected in the received character in SCID.
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Table 268. SCIS1 field descriptions (continued)
Field
Description
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This
suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIS1 with FE = 1 and then read the SCI data
register (SCID).
1
FE
0
1
No framing error detected. This does not guarantee the framing is correct.
Framing error.
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character
does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID).
0
0
1
No parity error.
Parity error.
PF
4.13.2.3.5
SCI status register 2 (SCIS2)
This register has one read-only status flag.
Table 269. SCI status register 2 (SCIS2)
(228)
Offset
Access: User read/write
0x1D
7
6
RXEDGIF
0
5
0
4
RXINV
0
3
RWUID
0
2
BRK13
0
1
0
R
W
RAF
LBKDIF
0
LBKDE
0
Reset
0
0
= Unimplemented or Reserved
Notes
228. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 270. SCIS2 field descriptions
Field
Description
LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected.
LBKDIF is cleared by writing a “1” to it.
7
0
1
No LIN break character has been detected.
LIN break character has been detected.
LBKDIF
RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin
occurs. RXEDGIF is cleared by writing a “1” to it.
6
0
1
No active edge on the receive pin has occurred.
An active edge on the receive pin has occurred.
RXEDGIF
Receive Data Inversion — Setting this bit reverses the polarity of the received data input.
4
0
1
Receive data not inverted
Receive data inverted
(229)
RXINV
Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit.
3
0
1
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
RWUID
Break Character Generation Length — BRK13 is used to select a longer transmitted break character length. Detection of a framing
error is not affected by the state of this bit.
2
0
1
Break character is transmitted with length of 10 bit times (11 if M = 1)
Break character is transmitted with length of 13 bit times (14 if M = 1)
BRK13
LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error
(FE) and receive data register full (RDRF) flags are prevented from setting.
1
0
1
Break character detection enabled.
Break character detection disabled.
LBKDE
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Table 270. SCIS2 field descriptions (continued)
Field
Description
Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared automatically
when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing
the MCU to go to stop mode.
0
RAF
0
1
SCI receiver idle waiting for a start bit.
SCI receiver active (RxD input not idle).
Notes
229. Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by one bit time. Under the worst
case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave which is
running 14% faster than the master. This would trigger normal break detection circuitry, which is designed to detect a 10 bit break symbol.
When the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false
detection of a 0x00 data character as a LIN break symbol.
4.13.2.3.6
SCI control register 3 (SCIC3)
Table 271. SCI control register 3 (SCIC3)
(230)
Offset
Access: User read/write
1 0
0x1E
7
6
T8
0
5
TXDIR
0
4
TXINV
0
3
ORIE
0
2
NEIE
0
R
R8
FEIE
0
PEIE
0
W
Reset
0
= Unimplemented or Reserved
Notes
230. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 272. SCIC3 field descriptions
Field
Description
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the
left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8 before reading SCID, because reading SCID
completes automatic flag clearing sequences, which could allow R8 and SCID to be overwritten with new data.
7
R8
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit
to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire 9-bit value is transferred to the SCI shift register
after SCID is written, so T8 should be written (if it needs to change from its previous value) before SCID is written. If T8 does not need
to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCID is written.
6
T8
TxD Pin Direction in Single-wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this
bit determines the direction of data at the TxD pin.
5
0
1
TxD pin is an input in single-wire mode.
TxD pin is an output in single-wire mode.
TXDIR
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
4
0
1
Transmit data not inverted
Transmit data inverted
(231)
TXINV
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
3
0
1
OR interrupts disabled (use polling).
Hardware interrupt requested when OR = 1.
ORIE
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
2
0
1
NF interrupts disabled (use polling).
Hardware interrupt requested when NF = 1.
NEIE
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Table 272. SCIC3 field descriptions (continued)
Field
Description
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt requests.
1
FEIE
0
1
FE interrupts disabled (use polling).
Hardware interrupt requested when FE = 1.
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0
0
1
PF interrupts disabled (use polling).
Hardware interrupt requested when PF = 1.
PEIE
Notes
231. Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
4.13.2.3.7
SCI data register (SCID)
This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the
write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI
status flags.
Table 273. SCI data register (SCID)
(232)
Offset
Access: User read/write
1 0
0x1D
7
R7
T7
0
6
R6
T6
0
5
R5
T5
0
4
R4
T4
0
3
R3
T3
0
2
R2
T2
0
R
R1
T1
0
R0
T0
0
W
Reset
Notes
232. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.13.3 Functional description
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The
SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they
use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted,
and processes received data. The following describes each of the blocks of the SCI.
4.13.3.1 Baud rate generation
Figure 48 shows the clock source for the SCI baud rate generator is the D2D clock / 4.
MODULO DIVIDE BY
(1 THROUGH 8191)
DIVIDE BY
Tx BAUD RATE
16
D2D / 4
SBR12:SBR0
Rx SAMPLING CLOCK
(16 BAUD RATE)
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
D2DCLK / 4
BAUD RATE =
[SBR12:SBR0] 16
Figure 48. SCI baud rate generation
SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the
same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge
of the start bit and how bit sampling is performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full
10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a NXP Semiconductor
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SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and
about ±4.0 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match
standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications.
4.13.3.2 Transmitter functional description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle
characters. The transmitter block diagram is shown in Figure 46.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter output is inverted by setting TXINV
= 1. The transmitter is enabled by setting the TE bit in SCIC2. This queues a preamble character that is one full character frame of the
idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data
buffer by writing to the SCI data register (SCID).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M
control bit. For the remainder of this section, we will assume M = 0, selecting the normal 8-bit data mode. In 8-bit data mode, the shift
register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI character, the value
waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register
empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCID.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete
flag and enters an idle mode, with TxD high, waiting for more characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general purpose I/O pin. Any transmit activity that is in progress must first be
completed. This includes data characters in progress, queued idle characters, and queued break characters.
4.13.3.2.1
Send break and queued idle
The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the attention of old teletype receivers.
Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be
enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the
shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break
character is queued. If the receiving device is another NXP Semiconductor SCI, the break characters will be received as 0s in all eight
data bits and a framing error (FE = 1) occurs.
When idle-line wake-up is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter,
then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter is available. As long as
the character in the shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If there is a
possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin that is shared with TxD is an output driving
a logic 1. This ensures that the TxD line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and
then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown in Table 274.
Table 274. Break character length
BRK13
M
0
1
0
1
Break character length
10 bit times
0
0
1
1
11 bit times
13 bit times
14 bit times
4.13.3.3 Receiver functional description
In this section, the receiver block diagram (Figure 47) is used as a guide for the overall receiver functional description. The data sampling
technique used to reconstruct receiver data is then described in more detail. Finally, two variations of the receiver wake-up function are
explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIC2. Character frames consist of
a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to
Section 4.13.3.5.1, “8- and 9-bit data modes". For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data
mode.
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After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred
to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set indicating the receive data
register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered,
the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver
overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID.
The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles
receive data. Refer to Section 4.13.3.4, “Interrupts and status flags" for more details about flag clearing.
4.13.3.3.1
Data sampling technique
The SCI receiver uses a 16 baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to
search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1
samples. The 16 baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is
located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of
these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit.
The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed
to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s.
If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise
flag (NF) will be set when the received character is transferred to the receive data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit
times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case
analysis because some characters do not have any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling
edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. The receiver is inhibited from receiving
any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
4.13.3.3.2
Receiver wake-up operation
Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a
different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the
message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU bit is set,
the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting,
thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of
the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next
message.
4.13.3.3.2.1 Idle-line wake-up
When WAKE = 0, the receiver is configured for idle-line wake-up. In this mode, RWU is cleared automatically when the receiver detects
a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are
needed to constitute a full character time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE flag. The receiver wakes up
and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID
is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit
so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter
does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message.
4.13.3.3.2.2 Address-mark wake-up
When WAKE = 1, the receiver is configured for address-mark wake-up. In this mode, RWU is cleared automatically when the receiver
detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark
wake-up allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB
of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag. In this case, the character with the MSB
set is received even though the receiver was sleeping during most of this character time.
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4.13.3.4 Interrupts and status flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One
interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for
RDRF, IDLE, RXEDGIF, and LBKDIF events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt
sources can be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are
cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE)
indicates when there is room in the transmit data buffer to write another transmit character to SCID. If the transmit interrupt enable (TIE)
bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished
transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is often used in systems with
modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt
will be requested whenever TC = 1. Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags
if the corresponding TIE or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID.
The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then reading SCID.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIS1
must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence
is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended period of
time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading SCID. After IDLE has been cleared, it cannot become set again
until the receiver has received at least one new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags — noise flag (NF), framing error
(FE), and parity error flag (PF) — get set at the same time as RDRF. These flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun
(OR) flag gets set instead the data along with any associated NF, FE, or PF condition is lost.
At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF flag is cleared by writing a
“1” to it. This function does depend on the receiver being enabled (RE = 1).
4.13.3.5 Additional SCI functions
The following sections describe additional SCI functions.
4.13.3.5.1
8- and 9-bit data modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIC1. In 9-bit
mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIC3.
For the receiver, the ninth bit is held in R8 in SCIC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write
to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data
is transferred from SCID to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with
address-mark wake-up so the ninth data bit can serve as the wake-up bit. In custom protocols, the ninth bit can also serve as a
software-controlled marker.
4.13.3.5.2
Stop mode operation
During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized
upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode.
The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. An active edge on the receive input brings the
CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1).
Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should
ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module.
4.13.3.5.3
Loop mode
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When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop
mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this
mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general
purpose port I/O pin.
4.13.3.5.4
Single-wire operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1).
Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and
to the TxD pin. The RxD pin is not used and reverts to a general-purpose port I/O pin.
In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD pin. When TXDIR = 0, the TxD pin is an input
to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the
receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from
the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
4.14 Life time counter (LTC)
4.14.1 Introduction
The Life Time Counter is implemented as flexible counter running in both, low power (STOP and SLEEP) and normal modes.
It is based on the ALFCLK clock featuring IRQ and Wake Up capabilities on the Life Time Counter Overflow. The Wake Up on overflow
would be indicated in the PCR_SR register WULTCF bit. The Life Time Counter must be set in Normal mode. The Life Time Counter is
an up counter.
4.14.2 Memory map and registers
4.14.2.1 Overview
This section provides a detailed description of the memory map and registers.
4.14.2.2 Module memory map
The memory map for the LTC module is in Table 63
Table 275. Module memory map
(233)
Offset
Name
7
0
6
5
4
3
2
1
0
0
LTC_CTL (hi)
R
W
R
0
0
0
0
0
0
0x38
Life Time Counter control register
LTC_CTL (lo)
LTCIEM
LTCEM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x39
0x3A
0x3B
LTCIE
LTCE
0
Life Time Counter control register
LTC_SR
W
R
LTCOF
1 = clear
0
Life Time Counter status register
W
R
0
Reserved
W
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Table 275. Module memory map (continued)
(233)
Offset
Name
7
6
5
4
3
2
1
0
R
W
R
LTC_CNT1
Life Time Counter Register
0x3C
W
R
LTC[31:0]
W
R
LTC_CNT0
Life Time Counter Register
0x3E
W
Notes
233. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4.14.2.3 Register descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.14.2.3.1
Life time counter control register (LTC_CTL (hi))
Table 276. Life time counter control register (LTC_CTL (hi))
(234)
Offset
Access: User write
0x38
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
0
LTCEM
0
LTCIEM
0
Reset
0
0
0
0
0
0
Notes
234. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 277. Life time counter control register (LTC_CTL (hi)) - register field descriptions
Field
Description
Life Time Counter Enable Mask
0 - writing the LTCE Bit will have no effect
1 - writing the LTCE Bit will be effective
0
LTCEM
Life Time Counter Interrupt Enable Mask
0 - writing the LTCIE Bit will have no effect
1 - writing the LTCIE Bit will be effective
7
LTCIEM
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4.14.2.3.2
Life time counter control register (LTC_CTL (lo))
Table 278. Life time counter control register (LTC_CTL (lo))
(235)
Offset
Access: User read/write
0x39
7
LTCIE
0
6
0
5
0
4
0
3
0
2
0
1
0
0
LTCE
0
R
W
Reset
0
0
0
0
0
0
Notes
235. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 279. Life time counter control register (LTC_CTL (lo)) - register field descriptions
Field
Description
Life Time Counter Enable
0
1 - Life time counter module enabled. Counter will be incremented with based on the ALFCLK frequency.
0 - Life time counter module disabled. Counter content will remain.
LTCE
(236)
Life Time Counter Interrupt Enable
1 - Life time counter overflow will generate an interrupt request.
0 - Life time counter overflow will not generate an interrupt request.
7
LTCIE
Notes
236. The first period after enable might be shorted due to the asynchronous clocks.
4.14.2.3.3
Life time counter status register (LTC_SR)
Table 280. Life time counter status register (LTC_SR)
(237)
Offset
Access: User read/write
0x3A
7
6
5
4
3
2
1
0
R
LTCOF
0
0
0
0
0
0
0
0
W
Reset
Notes
0
0
0
0
0
0
0
237. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 281. Life time counter status register (LTC_SR) - register field descriptions
Field
Description
Life Time Counter Overflow Flag. Writing 1 will clear the flag.
1 - Life time counter overflow detected.
0 - No life time counter overflow since last clear
0
LTCOF
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4.14.2.3.4
Life time counter register (LTC_CNT1, LTC_CNT0)
Table 282. Life time counter register (LTC_CNT1, LTC_CNT0)
Offset
Access: User read/write
0x3C, 0x3E
7
(238),(239)
6
5
4
3
2
1
0
R
W
LTC[31:16]
LTC[15:0]
R
W
R
W
R
W
Reset
0
0
0
0
0
0
0
0
Notes
238. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
239. Those Registers are 16-Bit access only.
Table 283. Life time counter register (LTC_CNT1, LTC_CNT0) - register field descriptions
Field
Description
Life Time Counter Register
The two 16-Bit words of the 32-Bit Life Time Counter register represent the current counter status. Whenever the microcontroller
performs a reading operation on one of the 16Bit registers, the Life Time Counter is stopped until the remaining 16-Bit register is read,
to prevent loss of information. After the second part is read, the LTC continues automatically.
0-31
LTC[31:0]
Write operations should be performed with the Life Time Counter disabled to prevent a loss of data.
4.15 Die to die interface - target
The D2D Interface is the bus interface to the Microcontroller. Access to the MM912_637 analog die is controlled by the D2D Interface
module. This section describes the functionality of the die-to-die target block (D2D).
4.15.1 Overview
The D2D is the target for a data transfer from the target to the initiator (MCU). The initiator provides a set of configuration registers and
two memory mapped 256 Byte address windows. When writing to a window a transaction is initiated sending a write command, followed
by an 8-bit address and the data byte or word is received from the initiator. When reading from a window a transaction is received with
the read command, followed by an 8-bit address. The target then responds with the data. The basic idea is that a peripheral located on
the MM912_637 analog die, can be addressed like an on-chip peripheral.
MM912_637D1
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Internal Read Data Bus
Internal Write Data Bus
Internal Address Bus
D2DCLK
Command,
Address and
Data Buffer
Internal Interrupt signal (INT)
Internal
Interrupt
Sources
Figure 49. Die to die interface
Features:
•
•
•
•
•
•
•
software transparent register access to peripherals on the MM912_637 analog die
256 Byte address window
supports blocking read or write as well as non-blocking write transactions
8 bit physical bus width
automatic synchronization of the target when initiator starts driving the interface clock
generates transaction and error status as well as EOT acknowledge
providing single interrupt interface to D2D Initiator
4.15.2 Low power mode operation
The D2D module is disabled in SLEEP and STOP mode. In Stop mode, the D2DINT signal is used to wake-up a powered down MCU after
re-enabling the D2D interface. As the MCU could wake-up without the MM912_637 analog die, a special command will be recognized as
wake-up event during Stop mode. See Section 4.3, “Analog die - power, clock and resets - PCR".
4.15.2.1 Normal mode
While in Normal, D2DCLK acts as an input only with pull present. D2D[7:0] operates as input/output with pull-down always present.
D2DINT acts as an output only.
4.15.2.2 Sleep mode/stop mode
While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption.
4.16 Embedded microcontroller - overview
4.16.1 Introduction
The S12 Central Processing Unit (CPU) offers 128 kB of Flash memory and 6.0 kB of system SRAM, up to eight general purpose I/Os,
an on-chip oscillator and clock multiplier, one Serial Peripheral Interface (SPI), an interrupt module, and debug capabilities via the on-chip
debug module (DBG), in combination with the Background Debug mode (BDM) interface. Additionally, there is a die-to-die initiator (D2DI)
which represents the communication interface to the companion (analog) die.
4.16.2 Features
This section describes the key features of the MM912_637 micro controller die.
MM912_637D1
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4.16.2.1 Chip-level features
On-chip modules available within the family include the following features:
•
•
•
•
•
•
•
•
•
•
S12 CPU core (CPU12_V1)
128 kByte on-chip flash with ECC
4.0 kbyte on-chip data flash with ECC
6.0 kbyte on-chip SRAM
Phase locked loop (IPLL) frequency multiplier with internal filter
4.0–16 MHz amplitude controlled Pierce oscillator
1.024 MHz internal RC oscillator
One serial peripheral interface (SPI) module
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Die to Die Initiator (D2DI)
4.16.3 Module features
The following sections provide more details of the modules implemented on the MC9S12I128.
4.16.3.1 S12 16-bit central processor unit (CPU)
S12 CPU is a high-speed 16-bit processing unit:
•
•
•
Full 16-bit data paths supports efficient arithmetic operation and high speed math execution
Includes many single-byte instructions. This allows much more efficient use of ROM space
Extensive set of indexed addressing capabilities, including:
—
—
—
—
Using the stack pointer as an indexing register in all indexed operations
Using the program counter as an indexing register in all but auto increment/decrement mode
Accumulator offsets using A, B, or D accumulators
Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
4.16.3.2 On-chip flash with ECC
On-chip flash memory on the MM912_637 features the following:
•
128 kbyte of program flash memory
—
—
—
—
—
32 data bits plus 7 syndrome ECC (Error Correction Code) bits allow single bit error correction and double fault detection
Erase sector size 512 bytes
Automated program and erase algorithm
User margin level setting for reads
Protection scheme to prevent accidental program or erase
•
4.0 kbyte data flash memory
—
—
—
—
16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit error correction and double-bit error detection
Erase sector size 256 bytes
Automated program and erase algorithm
User margin level setting for reads
4.16.3.3 On-chip SRAM
•
6.0 kBytes of general purpose RAM
4.16.3.4 Main external oscillator (XOSC)
•
Loop controlled Pierce oscillator using a 4.0 MHz to 16 MHz crystal or resonator
—
—
—
—
—
Current gain control on amplitude output
Signal with low harmonic distortion
Low power
Good noise immunity
Eliminates need for external current limiting resistor
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—
Transconductance sized for optimum start-up margin for typical crystals
4.16.3.5 Internal RC oscillator (IRC)
•
Trimmable internal reference clock
Frequency: 1.024 MHz
—
4.16.3.6 Internal phase-locked-loop (IPLL)
•
Phase-locked-loop clock frequency multiplier
—
—
—
—
—
—
No external components required
Reference divider and multiplier allow large variety of clock rates
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
Reference clock sources:
–
–
External 4.0–16 MHz resonator/crystal (XOSC)
Internal 1.024 MHz RC oscillator (IRC)
4.16.3.7 System integrity support
•
•
•
•
•
•
Power-on reset (POR)
System reset generation
Illegal address detection with reset
Low voltage detection with interrupt or reset
Real time interrupt (RTI)
Computer operating properly (COP) watchdog
—
—
Configurable as window COP for enhanced failure detection
Initialized out of reset using option bits located in flash memory
•
Clock monitor supervising the correct function of the oscillator
4.16.3.8 Serial peripheral interface module (SPI)
•
•
•
•
•
•
Configurable 8- or 16-bit data size
Full duplex or single-wire bidirectional
Double buffered transmit and receive
Master or slave mode
MSB-first or LSB-first shifting
Serial clock phase and polarity options
4.16.3.9 On-chip voltage regulator (VREG)
•
•
•
•
Linear voltage regulator with bandgap reference
Low voltage detect (LVD) with low voltage interrupt (LVI)
Power-on reset (POR) circuit
Low voltage reset (LVR)
4.16.3.10 Background debug (BDM)
•
•
Non-intrusive memory access commands
Supports in-circuit programming of on-chip nonvolatile memory
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4.16.3.11 Debugger (DBG)
•
•
Trace buffer with depth of 64 entries
Three comparators (A, B and C)
—
—
Comparator A compares the full address bus and full 16-bit data bus
Exact address or address range comparisons
•
Two types of comparator matches
—
—
Tagged: This matches just before a specific instruction begins execution
Force: This is valid on the first instruction boundary after a match occurs
•
•
Four trace modes
Four stage state sequencer
4.16.3.12 Die to die initiator (D2DI)
•
•
Up to 2.0 Mbyte/s data rate
Configurable 4-bit or 8-bit wide data path
4.16.4 Block diagram
Figure 50 shows a block diagram of the MC9S12I128 device.
D2D0
D2D1
D2D2
D2D3
D2D4
D2D5
D2D6
D2D7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Die-to-Die Initiator
128 k bytes Flash with ECC
6.0 k bytes RAM
selectable 4 or 8 bit wide
4.0 k bytes Dataflash with ECC
Voltage Regulator
Input: 3.13 V … 5.5 V
Outputs: 1.8 V core and 2.7 Flash
D2DCLK
D2DINT
PC0
PC1
CPU12-V1
MISO
MOSI
SCK
SS
PA0
PA1
SPI
Debug Module
PA2
PA3
PA4
PA5
PA6
PA7
3 address breakpoints
1 data breakpoints
Single-wire Background
Debug Module
Synchronous Serial IF
BKGD
64 Byte Trace Buffer
Clock Monitor
COP Watchdog
Periodic Interrupt
.
Amplitude
Controlled
Low Power
PE0
PE1
EXTAL
XTAL
Power Supply:
PLL with Frequency
Modulation option
VDDRX, VSSRX: 3.13 V …5.5V
for Regulator Input, Port A, Port E, BKGD, TEST
RESET
TEST
and RESET
VDDD2D, VSSD2D: 2.5 V for Ports C and D
Reset Generation
and Test Entry
Interrupt Module
Figure 50. MC9S12I128 block diagram
4.16.5 Device memory map
Table 284 shows the device register memory map.
Table 284. Device register memory map
Address
Module
Size (Bytes)
0x0000–0x0009
0x000A–0x000B
0x000C–0x000D
0x000E–0x000F
0x0010–0x0015
PIM (port integration module)
MMC (memory map control)
PIM (port integration module)
Reserved
10
2
2
2
MMC (memory map control)
8
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Table 284. Device register memory map (continued)
Address
Module
Size (Bytes)
0x0016–0x0019
0x001A–0x001B
0x001C–0x001E
0x001F
Reserved
2
2
Device ID register
Reserved
4
INT (interrupt module)
DBG (debug module)
Reserved
1
0x0020–0x002F
0x0030–0x0033
0x0034–0x003F
0x0040–0x00D7
0x00D8–0x00DF
0x00E0–0x00E7
0x00E8–0x00EF
0x00F0–0x00FF
0x0100–0x0113
0x0114–0x011F
0x0120–0x017F
0x0180–0x01EF
0x01F0–0x01FC
0x01FD–0x01FF
0x0200-0x02FF
0x0300–0x03FF
16
4
CPMU (clock and power management)
Reserved
12
152
8
D2DI (die 2 die initiator)
Reserved
32
8
SPI (serial peripheral interface)
Reserved
32
20
12
96
112
13
3
FTMRC control registers
Reserved
PIM (port integration module)
Reserved
CPMU (clock and power management)
Reserved
D2DI (die 2 die initiator, blocking access window)
D2DI (die 2 die initiator, non-blocking write window)
256
256
NOTE
Reserved register space shown in Table 284 is not allocated to any module. This register space is
reserved for future use. Writing to these locations have no effect. Read access to these locations
returns zero.
Figure 51 shows MM912_637 CPU and BDM local address translation to the global memory map. It indicates also the location of the
internal resources in the memory map. The whole 256 k global memory space is visible through the P-Flash window located in the 64 k
local memory map located at 0x8000 - 0xBFFF using the PPAGE register.
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CPU and BDM
Global Memory Map
Local Memory Map
0x0000
0x0_0000
Registers
Registers
0x0400
Unimplemented
D-Flash 4K Bytes
0x0_2800
RAM 6K
0x1400
Unpaged P-Flash
Page 0x0C
0x0_4000
NVM Resources
0x2800
0x4000
0x0_4400
D-Flash
RAM 6K Bytes
0x0_5400
NVM Resources
0x0_8000
Unimplemented
Unpaged P-Flash
Page 0x0D
0x2_0000
P-Flash
4* 16K Pages
0x8000
0x3_0000
Unpaged P-Flash
0 0 0 0 P3P2P1P0
PPAGE
P-Flash window
0x3_4000
0xC000
Unpaged P-Flash
0x3_8000
Unpaged P-Flash
Page 0x0F
0x3_C000
0xFFFF
Unpaged P-Flash
0x3_FFFF
Figure 51. MC9S12I128 global memory map
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4.16.6 Part ID assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique
part ID for each revision of the chip. Table 285 shows the assigned part ID number and Mask Set number.
The Version ID in Table 285 is a word located in a flash information row. The version ID number indicates a specific version of internal
NVM controller.
Table 285. Assigned part ID numbers
(240)
Device
Mask set number
Part ID
Version ID
MM912_637
0M96X
0x3880
0x0000
Notes
240. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
4.16.7 System clock description
Refer to Section 4.23, “S12 clock, reset, and power management unit (9S12I128PIMV1)" for the system clock description.
4.16.8 Modes of operation
The MCU can operate in different modes. These are described in Section 4.16.8.1, “Chip configuration summary".
The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These are
described in Section 4.16.8.2, “Low power operation". Some modules feature a software programmable option to freeze the module status
while the background debug module is active to facilitate debugging.
4.16.8.1 Chip configuration summary
The different modes and the security state of the MCU affect the debug features (enabled or disabled). The operating mode out of reset
is determined by the state of the MODC signal during reset (see Table 286). The MODC bit in the MODE register shows the current
operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising
edge of RESET.
Table 286. Chip modes
Chip modes
Normal single chip
Special single chip
MODC
1
0
4.16.8.1.1
Normal single-chip mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset
vector to be programmed correctly). The processor program is executed from internal memory.
4.16.8.1.2
Special single-chip mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module
BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for additional serial
commands through the BKGD pin.
4.16.8.2 Low power operation
The MM912_637 has two static low-power modes Pseudo Stop and Stop mode. For a detailed description refer to the S12CPMU section.
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4.16.9 Security
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 4.21, “MCU - security
(S12XS9S12I128PIMV1V2)", Section 4.22.4.1, “Security", and Section 4.25.5, “Security".
4.16.10 Resets and interrupts
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
4.16.10.1 Resets
Table 287 lists all Reset sources and the vector locations. Resets are explained in detail in Section 4.23, “S12 clock, reset, and power
management unit (9S12I128PIMV1)".
Table 287. Reset sources and vector locations
Vector address
$FFFE
Reset source
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock monitor reset
CCR mask
None
Local enable
None
$FFFE
None
None
None
$FFFE
None
$FFFE
None
None
$FFFC
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
$FFFA
COP watchdog reset
None
4.16.10.2 Interrupt vectors
Table 288 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see Section 4.18, “MCU - interrupt
module (S12S9S12I128PIMV1V1)") provides an interrupt vector base register (IVBR) to relocate the vectors.
Table 288. Interrupt vector locations (Sheet 2 of 2)
CCR
Wake-up
Wake-up
from WAIT
(241)
Vector Address
Interrupt Source
Local Enable
Mask
from STOP
Vector base + $F8
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
Unimplemented instruction trap
SWI
None
None
X Bit
I bit
None
None
-
-
-
-
D2DI Error Interrupt
D2DI External Interrupt
RTI timeout interrupt
None
Yes
Yes
Yes
Yes
D2DCTL (D2DIE)
CPMUINT (RTIE)
I bit
3.22.6 Interrupts
Vector base + $EE
to
Reserved
Vector base + $DA
Vector base + $D8
SPI
I bit
SPICR1 (SPIE, SPTIE)
No
Yes
Vector base + $D6
to
Reserved
Vector base + $CA
Vector base + $C8
Vector base + $C6
Oscillator status interrupt
PLL lock interrupt
I bit
I bit
CPMUINT (OSCIE)
CPMUINT (LOCKIE)
No
No
No
No
Vector base + $C4
to
Reserved
Vector base + $BC
Vector base + $BA
FLASH error
I bit
FERCNFG (SFDIE, DFDIE)
No
No
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Table 288. Interrupt vector locations (Sheet 2 of 2)
CCR
Wake-up
Wake-up
from WAIT
(241)
Vector Address
Interrupt Source
Local Enable
Mask
from STOP
Vector base + $B8
FLASH command
I bit
I bit
—
FCNFG (CCIE)
No
No
-
Yes
Yes
-
Vector base + $B6
to
Vector base + $8C
Reserved
Vector base + $8A
Low-voltage interrupt (LVI)
Spurious interrupt
CPMUCTRL (LVIE)
Vector base + $88
to
Vector base + $82
Reserved
Vector base + $80
None
Notes
241. 16-bit vector address based
4.16.10.3 Effects of reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On
each reset, the Flash module executes a reset sequence to load Flash configuration registers.
4.16.10.3.1 Flash configuration reset sequence phase
The Flash module will hold CPU on each reset activity while loading Flash module registers from the Flash memory. If double faults are
detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the
Flash module, Section 4.25.6, “Initialization".
4.16.10.3.2 Reset while flash command active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being
programmed or the sector/block being erased is not guaranteed.
4.16.10.3.3 I/O pins
Refer to the PIM section for reset configurations of all peripheral module ports.
4.16.10.3.4 Memory
The RAM arrays are not initialized out of reset.
4.16.11 COP configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are loaded from the Flash register
FOPT. See Table 289 and Table 290 for coding. The FOPT register is loaded from the Flash configuration field byte at global address
0x3_FF0E during the reset sequence.
Table 289. Initial COP rate configuration
NV[2:0] in FOPT register
CR[2:0] in COPCTL register
000
001
010
011
100
111
110
101
100
011
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Table 289. Initial COP rate configuration (continued)
NV[2:0] in FOPT register
CR[2:0] in COPCTL register
101
110
111
010
001
000
Table 290. Initial WCOP configuration
NV[3] in FOPT register
WCOP in COPCTL register
1
0
0
1
4.17 MCU - port integration module (9S12I128PIMV1)
4.17.1 Introduction
The Port Integration Module (PIM) establishes the interface between the S12I128 peripheral modules SPI and Die-To-Die Interface
module (D2DI) to the I/O pins of the MCU. All port A and port E pins support general purpose I/O functionality, if not in use with other
functions. The PIM controls the signal prioritization and multiplexing on shared pins.
4.17.1.1 Overview
Figure 52 is a block diagram of the Port Integration Module.
D2DCLK
D2DINT
PC0
PC1
D2DI
D2DDAT0
D2DDAT1
D2DDAT2
D2DDAT3
D2DDAT4
D2DDAT5
D2DDAT6
D2DDAT7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Die-to-Die IF
CPMU OSC
EXTAL
XTAL
PE0
PE1
MISO
MOSI
SCK
PA0
PA1
PA2
PA3
PA4
PA5
SPI
Synchronous Serial IF
SS
PA6
PA7
Figure 52. Port integration module - block diagram
4.17.1.2 Features
•
•
•
•
•
•
8-pin port A associated with the SPI module
2-pin port C used as D2DI clock output and D2DI interrupt input
8-pin port D used as 8 or 4 bit data I/O for the D2DI module
2-pin port E associated with the CPMU OSC module
GPIO function shared on port A and E pins
Pull-down devices on PC1 and PD7-0 if used as D2DI inputs
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•
Reduced drive capability on PC0 and PD7-0 on per pin basis
The Port Integration Module includes these distinctive registers:
•
•
•
•
Data registers for ports A and E when used as general purpose I/O
Data direction registers for ports A and E when used as general purpose I/O
Port input register on ports A and E
Reduced drive register on port C and D
4.17.2 External signal description
This section lists and describes the signals that do connect off-chip. Table 291 shows all the pins and their functions that are controlled
by the Port Integration Module.
NOTE
If there is more than one function associated with a pin, the priority is indicated by the position in the
table from top (highest priority) to bottom (lowest priority).
Table 291. Pin functions and priorities
Pin function &
priority
Pin function
after reset
Port
Pin name
I/O
Description
PA7
PA6
PA5
PA4
GPIO
GPIO
GPIO
GPIO
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
Serial Peripheral Interface 0 slave select output in master mode, input in
slave or master mode
SS
I/O
PA3
GPIO
SCK
I/O General-purpose I/O
A
GPI
I/O Serial Peripheral Interface 0 serial clock pin
I/O General-purpose I/O
PA2
PA1
PA0
PE1
PE0
GPIO
MOSI
GPIO
MISO
GPIO
XTAL
GPIO
EXTAL
GPIO
I/O Serial Peripheral Interface 0 master out/slave in pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master in/slave out pin
I/O General-purpose I/O
-
CPMU OSC XTAL pin
I/O General-purpose I/O
CPMU OSC EXTAL pin
I/O General-purpose I/O
E
GPI
-
4.17.3 Memory map and register definition
This section provides a detailed description of all Port Integration Module registers.
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4.17.3.1 Memory map
Table 292. PIM register summary
Register
Bit 7
6
5
4
3
2
1
Bit 0
Name
R
0x0000
PORTA
PA7
PA6
0
PA5
0
PA4
0
PA3
0
PA2
0
PA1
PA0
W
R
W
R
0
0x0001
PORTE
PE1
PE0
0x0002
DDRA
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
DDRA0
W
R
0x0003
DDRE
DDRE1
0
DDRE0
0
W
R
0x0004-
0x0009
Reserved
0
0
0
0
0
0
0
0
W
R
W
R
0
0
0
0
0
0x000C
PUCR
BKPUE
0
PDPEE
0
0
0
0
0x000D
RDRIV
RDPD
PTIA3
RDPC
PTIA2
W
R
PTIA7
PTIA6
PTIA5
PTIA4
PTIA1
PTIE1
0
PTIA0
PTIE0
0
0x0120
PTIA
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0x0121
PTIE
W
R
0x0122-
0x017F
W
Reserved
= Unimplemented or Reserved
4.17.3.2 Port A data register (PORTA)
Table 293. Port A data register (PORTA)
Address
Access: User read/write
1 0
0x0000
7
6
5
4
3
2
R
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
W
SPI
Function
—
0
—
0
—
0
—
0
SS
0
SCK
0
MOSI
0
MISO
0
Reset
Read: Anytime.
Write: Anytime.
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Table 294. PORTA register field descriptions
Field
Description
Port A general purpose input/output data—Data Register In / output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and synchronized
pin input state is read.
7–4
PA
Port A general purpose input/output data—Data Register, SPI SS input/output
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state
is read. The SPI function takes precedence over the general purpose I/O function if enabled.
3
PA
Port A general purpose input/output data—Data Register, SPI SCK input/output
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state
is read. The SPI function takes precedence over the general purpose I/O function if enabled.
2
PA
Port A general purpose input/output data—Data Register, SPI MOSI input/output
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state
is read. The SPI function takes precedence over the general purpose I/O function if enabled.
1
PA
Port A general purpose input/output data—Data Register, SPI MISO input/output
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state
is read. The SPI function takes precedence over the general purpose I/O function if enabled.
0
PA
4.17.3.3 Port E data register (PORTE)
Table 295. Port E data register (PORTE)
Address
Access: User read/write
1 0
0x0001
7
6
0
5
0
4
0
3
0
2
0
R
0
PE1
PE0
W
CPMU
OSC
Function
—
0
—
0
—
0
—
0
—
0
—
0
XTAL
0
EXTAL
0
Reset
Read: Anytime.
Write: Anytime.
Table 296. PORTE register field descriptions
Field
Description
Port E general purpose input/output data—Data Register, CPMU OSC XTAL signal
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state
is read. The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
1
PE
Port E general purpose input/output data—Data Register, CPMU OSC EXTAL signal
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state
is read. The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
0
PE
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4.17.3.4 Port A data direction register (DDRA)
Table 297. Port A data direction register (DDRA)
Address
Access: User read/write
0x0002
7
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
0
DDRA0
0
R
W
DDRA7
0
Reset
Read: Anytime.
Write: Anytime.
Table 298. DDRA register field descriptions
Field
Description
Port A Data Direction—
7–4
DDRA
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
3–0
DDRA
Depending on the configuration of the enabled SPI the I/O state will be forced to input or output. In this case, the data direction bits will not
change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
4.17.3.5 Port E data direction register (DDRE)
Table 299. Port E data direction register (DDRE)
Address
Access: User read/write
0x0003
7
6
0
5
0
4
0
3
0
2
0
1
0
DDRE0
0
R
W
0
0
DDRE1
0
Reset
0
0
0
0
0
Read: Anytime.
Write: Anytime.
Table 300. DDRE register field descriptions
Field
Description
Port E Data Direction—
This bit determines whether the associated pin is an input or output.
1–0
DDRE
The enabled CPMU OSC function connects the associated pins directly to the oscillator module. In this case, the data direction bits will not
change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
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4.17.3.6 Pull-up control register (PUCR)
Table 301. Pull control register (PUCR)
Address
Access: User read/write
0x000C
7
6
BKPUE
1
5
0
4
0
3
0
2
0
1
PDPEE
1
0
0
R
W
0
0
Reset
0
0
0
0
0
Read: Anytime.
Write: Anytime.
Table 302. PUCR register field descriptions
Field
Description
BKGD pin pull-up Enable—Enable pull-up devices on BKGD pin
This bit configures whether a pull-up device is activated, if the pin is used as input. This bit has no effect if the pin is used as output.
Out of reset the pull-up device is enabled.
1 Pull-up device enabled.
0 Pull-up device disabled.
6
BKPUE
Pull-down Port E Enable—Enable pull-down devices on all Port E input pins
This bit configures whether pull-down devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as
outputs. Out of reset the pull-down devices are enabled. If the CPMU OSC function is active, the pull-down devices are disabled. In this
case, the register bit will not change.
1
PDPEE
1 Pull-down devices enabled.
0 Pull-down devices disabled.
4.17.3.7 Reduced drive register (RDRIV)
Table 303. Reduced drive register (RDRIV)
Address
Access: User read/write
0x000D
7
6
0
5
0
4
0
3
RDPD
0
2
RDPC
0
1
0
0
0
R
W
0
Reset
0
0
0
0
0
0
Read: Anytime.
Write: Anytime.
Table 304. RDRIV register field descriptions
Field
Description
Port D reduced drive—Select reduced drive for output pins
3
This bit configures the drive strength of output pins as either full or reduced. If a pin is used as input, this bit has no effect.
1 Reduced drive selected (1/5 of the full drive strength)
RDPD
0 Full drive strength enabled
Port C reduced drive—Select reduced drive for D2DCLK output pin
This bit configures the drive strength of D2DCLK output pin as either full or reduced.
1 Reduced drive selected (1/5 of the full drive strength)
0 Full drive strength enabled
2
RDPC
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4.17.3.8 Port A input register (PTIA)
Table 305. Port A input register (PTIA)
Address
Access: User read
0x0120
7
6
5
4
3
2
1
0
R
PTIA7
u
PTIA6
PTIA5
PTIA4
PTIA3
PTIA2
PTIA1
PTIA0
W
(242)
Reset
u
u
u
u
u
u
u
Notes
242. u = Unaffected by reset
Read: Anytime.
Write: Unimplemented. Writing to this register has no effect.
Table 306. PTIA register field descriptions
Field
Description
Port A input data—
7–0
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short-circuit conditions on output
pins.
PTIA
4.17.3.9 Port E input register (PTIE)
Table 307. Port E input register (PTIE)
Address
Access: User read
0x0121
7
6
0
5
0
4
0
3
0
2
0
1
0
R
0
u
PTIE1
PTIE0
W
Reset
u
u
u
u
u
u
u
(243)
Notes
243. u = Unaffected by reset
Read: Anytime.
Write: Unimplemented. Writing to this register has no effect.
Table 308. PTIE register field descriptions
Field
Description
Port E input data—
1–0
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short-circuit conditions on output
pins.
PTIE
4.17.4 Functional description
4.17.4.1 Registers
4.17.4.1.1
Data register (PORTx)
This register holds the value driven out to the pin, if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin, if the pin is used as general purpose output. When reading this address, the buffered
and synchronized state of the pin is returned, if the associated data direction register bit is set to “0”.
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If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This is independent of any other
configuration (Figure 53).
4.17.4.1.2
Data direction register (DDRx)
This register defines whether the pin is used as an input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 53).
4.17.4.1.3
Input register (PTIx)
This is a read-only register and always returns the buffered and synchronized state of the pin (Figure 53).
synch.
PTIx
0
1
PIN
0
PORTx
1
0
DDRx
1
data out
output enable
Periph.
port enable
Module
data in
Figure 53. Illustration of I/O pin functionality
4.17.4.1.4
Reduced drive register (RDRIV)
If the pin is used as an output, this register allows the configuration of the drive strength.
4.17.4.1.5
Pull device enable register (PUCR)
This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input.
4.17.4.2 Ports
4.17.4.2.1
Port A
This port is associated with the SPI. Port A pins PA7-0 can be used for general purpose I/O and PA3-0 also with the SPI subsystem.
4.17.4.2.2
Port E
This port is associated with the CPMU OSC. Port E pins PE1-0 can be used for general purpose or with the CPMU OSC module.
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4.17.5 Initialization information
4.17.5.1 Port data and data direction register writes
Writing PTx and DDRx in a word access is not recommended. When changing the register pins from inputs to outputs, the data may have
extra transitions during the write access. Initialize the port data register before enabling the outputs.
4.18 MCU - interrupt module (S12S9S12I128PIMV1V1)
4.18.1 Introduction
The 9S12I128PIMV1 module decodes the priority of all system exception requests and provides the applicable vector for processing the
exception to the CPU. The 9S12I128PIMV1 module supports:
•
•
•
•
•
I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.18.1.1 Glossary
Table 309 contains terms and abbreviations used in the document.
Table 309. Terminology
Term
CCR
ISR
Meaning
Condition Code Register (in the CPU)
Interrupt Service Routine
MCU
Micro-controller Unit
4.18.1.2 Features
•
•
•
•
•
•
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base(244) + 0x0080).
2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2)
I bit maskable interrupts can be nested
One X bit maskable interrupt vector request (at address vector base + 0x00F4)
One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base +
0x00F6)
•
•
•
•
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8)
Three system reset vectors (at addresses 0xFFFA–0xFFFE)
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU request
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs
Notes
244. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00
(used as lower byte).
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4.18.1.3 Modes of operation
•
Run mode
This is the basic mode of operation.
Wait mode
•
In Wait mode, the clock to the 9S12I128PIMV1 module is disabled. The 9S12I128PIMV1 module is however capable of waking
up the CPU from Wait mode, if an interrupt occurs. Refer to Section 4.18.5.3, “Wake-up from stop or wait mode"” for details
Stop mode
In Stop mode, the clock to the 9S12I128PIMV1 module is disabled. The 9S12I128PIMV1 module is however capable of waking
up the CPU from Stop mode, if an interrupt occurs. Refer to Section 4.18.5.3, “Wake-up from stop or wait mode"” for details
Freeze mode (BDM active)
•
•
In Freeze mode (BDM active), the interrupt vector base register is overridden internally. Refer to Section 4.18.3.1.1, “Interrupt
vector base register (IVBR)"” for details
4.18.1.4 Block diagram
Figure 54 shows a block diagram of the 9S12I128PIMV1 module.
Peripheral
Interrupt Requests
Wake-up
CPU
Vector
Address
Non I bit Maskable Channels
I bit Maskable Channels
IVBR
Interrupt
Requests
Figure 54. 9S12I128PIMV1 block diagram
4.18.2 External signal description
The 9S12I128PIMV1 module has no external signals.
4.18.3 Memory map and register definition
This section provides a detailed description of all registers accessible in the 9S12I128PIMV1 module.
4.18.3.1 Register descriptions
This section describes in address order all the 9S12I128PIMV1 registers and their individual bits.
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4.18.3.1.1
Interrupt vector base register (IVBR)
Table 310. Interrupt vector base register (IVBR)
Address: 0x001F
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R
W
IVB_ADDR[7:0]
Reset
Read: Anytime.
Write: Anytime.
Table 311. IVBR field descriptions
Field
Description
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of reset, these bits are set
to 0xFF (i.e., vectors are located at 0xFF80–0xFFFE) to ensure compatibility to HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset vector
address. Therefore, changing the IVBR has no effect on the location of the three reset vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are ignored and
the upper byte of the vector address is fixed as “0xFF”. This is done to enable handling of all non-maskable interrupts in the
BDM firmware.
7–0
IVB_ADDR[7:0]
4.18.4 Functional description
The 9S12I128PIMV1 module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt
vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the following
subsections.
4.18.4.1 S12S exception requests
The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the priority of pending interrupt
requests.
4.18.4.2 Interrupt prioritization
The 9S12I128PIMV1 module contains a priority decoder to determine the priority for all interrupt requests pending for the CPU. If more
than one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The I bit in the condition code register (CCR) of the CPU must be cleared.
3. There is no SWI, TRAP, or X bit maskable request pending.
NOTE
All non I bit maskable interrupt requests always have higher priority than the I bit maskable interrupt
requests. If the X bit in the CCR is cleared, it is possible to interrupt an I bit maskable interrupt by an
X bit maskable interrupt. It is possible to nest non maskable interrupt requests, e.g., by nesting SWI
or TRAP calls.
Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher priority interrupt request could
override the original interrupt request that caused the CPU to request the vector. In this case, the CPU will receive the highest priority
vector and the system will process this interrupt request first, before the original interrupt request is processed.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been
recognized, but prior to the CPU vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector.
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NOTE
Care must be taken to ensure that all interrupt requests remain active until the system begins
execution of the applicable service routine; otherwise, the exception request may not get processed
at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0080)).
4.18.4.3 Reset exception requests
The 9S12I128PIMV1 module supports three system reset exception request types (Refer to the Clock and Reset generator module for
details):
1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)
2. Clock monitor reset request
3. COP watchdog reset request
4.18.4.4 Exception priority
The priority (from highest to lowest) and address of all exception vectors issued by the 9S12I128PIMV1 module upon request by the CPU
is shown in Table 312.
Table 312. Exception vector map and priority
(245)
Vector address
0xFFFE
Source
Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)
Clock monitor reset
0xFFFC
0xFFFA
COP watchdog reset
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
(246)
X bit maskable interrupt request (XIRQ or D2D error interrupt)
(247)
IRQ or D2D interrupt request
Device specific I bit maskable interrupt sources (priority determined by the low byte of the vector address, in
descending order)
(Vector base + 0x00F0–0x0082)
(Vector base + 0x0080)
Spurious interrupt
Notes
245. 16-bit vector address based
246. D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt
247. D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt
4.18.5 Initialization/application information
4.18.5.1 Initialization
After a system reset, the software should:
1. Initialize the interrupt vector base register, if the interrupt vector table is not located at the default location (0xFF80–0xFFF9).
2. Enable I bit maskable interrupts by clearing the I bit in the CCR.
3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.
4.18.5.2 Interrupt nesting
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the CPU.
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default. In order to make an interrupt
service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, other I bit maskable
interrupt requests can interrupt the current ISR.
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An ISR of an interruptible I bit maskable interrupt request could basically look like this:
1. Service interrupt, e.g., clear interrupt flags, copy data, etc.
2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests)
3. Process data
4. Return from interrupt by executing the instruction RTI
4.18.5.3 Wake-up from stop or wait mode
4.18.5.3.1
CPU wake-up from stop or wait mode
Every I bit maskable interrupt request is capable of waking the MCU from Stop or Wait mode. To determine whether an I bit maskable
interrupts is qualified to wake-up the CPU, the same conditions as in normal run mode are applied during Stop or Wait mode:
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU. Since there are no clocks running in Stop
mode, only interrupts which can be asserted asynchronously can wake-up the MCU from Stop mode.
NOTE
The only asynchronously asserted, I bit maskable interrupt for the MM912_637 would be the “D2D
External Interrupt”.
The X bit maskable interrupt request can wake-up the MCU from Stop or Wait mode at anytime, even if the X bit in CCR is set. If the X bit
maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the associated ISR is not called. The CPU then
resumes program execution with the instruction following the WAI or STOP instruction. This features works the same rules as with any
interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at least until the system begins
execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur.
NOTE
The only X bit maskable interrupt for the MM912_637 would be the D2D Error Interrupt. As the D2D
Initiator module is not active during STOP and WAIT mode, no X bit maskable interrupt source is
existing for the MM912_637.
4.19 Memory map control (S12PMMCV1)
4.19.1 Introduction
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and S12SBDM module. It regulates
access priorities and determines the address mapping of the on-chip resources. Figure 55 shows a block diagram of the S12PMMC
module.
4.19.1.1 Glossary
Table 313. Glossary of terms
Term
Definition
Address within the CPU12’s Local Address Map (Figure 60)
Address within the Global Address Map (Figure 60)
Bus access to an even address.
Local Address
Global Address
Aligned Bus Access
Misaligned Bus Access
Bus access to an odd address.
NS
Normal Single-chip Mode
SS
Special Single-chip Mode
Unimplemented Address Ranges
Address ranges which are not mapped to any on-chip resource.
Program Flash
P-Flash
D-Plash
Data Flash
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Table 313. Glossary of terms (continued)
Term
Definition
NVM
IFR
Non-volatile Memory; P-Flash or D-Flash
NVM Information Row. Refer to FTMRC Block Guide
4.19.1.2 Overview
The S12PMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources (memories and peripherals).
It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12PMMC is responsible for constraining
memory accesses on secured devices and for selecting the MCU’s functional mode.
4.19.1.3 Features
The main features of this block are:
•
•
•
•
•
•
Paging capability to support a global 256 kByte memory address space
Bus arbitration between the masters CPU12, S12SBDM to different resources
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU12, S12SBDM
Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address which does not belong to any
of the on-chip modules) in single-chip modes
4.19.1.4 Modes of operation
The S12PMMC selects the MCU’s functional mode. It also determines the devices behavior in secured and unsecured state.
4.19.1.4.1
Functional modes
Two functional modes are implemented on devices of the S12I product family:
•
Normal Single Chip (NS)
The mode used for running applications.
•
Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals may also provide special debug
features in this mode
4.19.1.4.2
Security
S12I devices can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module determines the access
permissions to the on-chip memories in secured and unsecured state.
4.19.1.5 Block diagram
Figure 55 shows a block diagram of the S12PMMC.
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CPU
BDM
MMC
Address Decoder & Priority
Target Bus Controller
DBG
D-Flash
P-Flash
RAM
Peripherals
Figure 55. S12PMMC block diagram
4.19.2 External signal description
The S12PMMC uses two external pins to determine the devices operating mode: RESET and MODC (Table 314) See Device User Guide
(DUG) for the mapping of these signals to device pins.
Table 314. External system pins associated With S12PMMC
Pin Name
Pin Functions
Description
RESET (See DUG)
RESET
The RESET pin is used the select the MCU’s operating mode.
The MODC pin is captured at the rising edge of the RESET pin. The captured value
determines the MCU’s operating mode.
MODC (See DUG)
MODC
4.19.3 Memory map and registers
4.19.3.1 Module memory map
A summary of the registers associated with the S12PMMC block is shown in Table 315. Detailed descriptions of the registers and bits are
given in the subsections that follow.
Table 315. MMC register table
Address
Register name
Bit 7
6
5
4
3
2
1
Bit 0
0x000A
R
W
R
0
0
0
0
0
0
0
0
Reserved
0x000B
0
0
0
0
0
0
0
MODE
MODC
W
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Table 315. MMC register table (continued)
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
R
W
R
0
0
0
0
0
0
0
0
Reserved
DIRECT
Reserved
Reserved
Reserved
PPAGE
DP15
0
DP14
0
DP13
0
DP12
0
DP11
0
DP10
0
DP9
0
DP8
0
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
PIX3
PIX2
PIX1
PIX0
W
= Unimplemented or Reserved
4.19.3.2 Register descriptions
This section consists of the S12PMMC control register descriptions in address order.
4.19.3.2.1
Mode register (MODE)
Table 316. Mode register (MODE)
Address: 0x000B
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
MODC
(248)
Reset
MODC
0
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
248. External signal (see Table 314).
Read: Anytime.
Write: Only if a transition is allowed (see Figure 56).
The MODC bit of the MODE register is used to select the MCU’s operating mode.
Table 317. MODE field descriptions
Field
Description
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external mode MODC pin determines
the operating mode during RESET low (active). The state of the pin is registered into the respective register bit after the RESET signal
goes inactive (see Figure 56).
7
Write restrictions exist to disallow transitions between certain modes. Figure 56 illustrates all allowed mode changes. Attempting non
authorized transitions will not change the MODE bit, but it will block further writes to the register bit except in special modes.
MODC
Write accesses to the MODE register are blocked when the device is secured.
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RESET
1
0
Special
Single-Chip
(SS)
Normal
Single-Chip
(NS)
1
0
1
Figure 56. Mode transition diagram when MCU is unsecured
4.19.3.2.2
Direct page register (DIRECT)
Table 318. Direct register (DIRECT)
Address: 0x0011
7
DP15
0
6
DP14
0
5
DP13
0
4
DP12
0
3
DP11
0
2
DP10
0
1
DP9
0
0
DP8
0
R
W
Reset
Read: Anytime.
Write: anytime in special SS, write-one in NS.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping
scheme.
Table 319. DIRECT field descriptions
Field
Description
7–0
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. These
register bits form bits [15:8] of the local address (see Figure 57).
DP[15:8]
Bit0
Bit15
Bit8
Bit7
DP [15:8]
CPU Address [15:0]
Figure 57. DIRECT address mapping
Example 1. This example demonstrates usage of the Direct Addressing Mode
MOVB
LDY
#$80,DIRECT
;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
<$00
;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are “direct page aware” and can
;automatically select direct mode.
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4.19.3.2.3
Program page index register (PPAGE)
Table 320. Program page index register (PPAGE)
Address: 0x0030
7
0
6
0
5
0
4
0
3
PIX3
1
2
PIX2
1
1
PIX1
1
0
PIX0
0
R
W
Reset
0
0
0
0
Read: Anytime.
Write: Anytime.
These four index bits are used to map 16 kB blocks into the Flash page window located in the local (CPU or BDM) memory map, from
address 0x8000 to address 0xBFFF (see Figure 58). This supports accessing up to 256 kB of Flash (in the Global map) within the 64 kB
Local map. The PPAGE index register is effectively used to construct paged Flash addresses in the Local map format. The CPU has
special access to read and write this register directly during execution of CALL and RTC instructions.
Global Address [17:0]
Bit17
Bit0
Bit14 Bit13
PPAGE Register [3:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 58. PPAGE address mapping
NOTE
Writes to this register using the special access of the CALL and RTC instructions will be complete
before the end of the instruction execution.
Table 321. PPAGE field descriptions
Field
Description
3–0
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 P-Flash or ROM array pages is to be
accessed in the Program Page Window.
PIX[3:0]
The fixed 16 kB page from 0x0000 to 0x3FFF is the page number 0x0C. Parts of this page are covered by Registers, D-Flash and RAM
space. See the SoC Guide for details.
The fixed 16 kB page from 0x4000–0x7FFF is the page number 0x0D. The reset value of 0x0E ensures that there is linear Flash space
available between addresses 0x0000 and 0xFFFF out of reset. The fixed 16 kB page from 0xC000-0xFFFF is the page number 0x0F.
4.19.4 Functional description
The S12PMMC block performs several basic functions of the S12I sub-system operation: MCU operation modes, priority control, address
mapping, select signal generation, and access limitations for the system. Each aspect is described in the following subsections.
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4.19.4.1 MCU operating modes
•
Normal single chip mode
This is the operation mode for running application code. There is no external bus in this mode.
Special single chip mode
•
This mode is generally used for debugging operation, boot-strapping or security related operations. The active background
debug mode is in control of the CPU code execution and the BDM firmware is waiting for serial commands sent through the
BKGD pin.
4.19.4.2 Memory map scheme
4.19.4.2.1
CPU and BDM memory map scheme
The BDM firmware lookup tables and BDM register memory locations share addresses with other modules; however they are not visible
in the memory map during user’s code execution. The BDM memory resources are enabled only during the READ_BD and WRITE_BD
access cycles to distinguish between accesses to the BDM memory area and accesses to the other modules. (Refer to the BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware look-up tables and the BDM registers become visible in the local memory
map in the range 0xFF00-0xFFFF (global address 0x3_FF00 - 0x3_FFFF) and the CPU begins execution of firmware commands or the
BDM begins execution of hardware commands. The resources which share memory space with the BDM module will not be visible in the
memory map during active BDM mode.
Note that after the MCU enters active BDM mode the BDM firmware look-up tables and the BDM registers will also be visible between
addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0x0F.
4.19.4.2.1.1 Expansion of the local address map
4.19.4.2.1.1.1 Expansion of the CPU local address map
The program page index register in S12PMMC allows accessing up to 256 kB of P-Flash in the global memory map by using the four index
bits (PPAGE[3:0]) to page 16x16 kB blocks into the program page window, located from address 0x8000 to address 0xBFFF in the local
CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE register can be read or written by
normal memory accesses as well as by the CALL and RTC instructions (see Section 4.19.6.1, “CALL and RTC instructions").
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64 kB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the PPAGE register
will be set to the appropriate value when the service routine is called. However an interrupt service routine can call other routines that are
in paged memory. The upper 16 kB block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset
and interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU memory map.
4.19.4.2.1.1.2 Expansion of the BDM local address map
PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global address. These registers can be read
and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. The four BDMPPR Program Page
index bits allow access to the full 256 kB address map that can be accessed with 18 address bits.
The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing
a firmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for further details. (see
Figure 59).
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BDM HARDWARE COMMAND
Global Address [17:0]
Bit14 Bit13
Bit17
Bit0
BDMPPR Register [3:0]
BDM Local Address [13:0]
BDM FIRMWARE COMMAND
Global Address [17:0]
Bit17
Bit0
Bit14 Bit13
BDMPPR Register [3:0]
CPU Local Address [13:0]
Figure 59. BDMPPR address mapping
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CPU and BDM
Global Memory Map
Local Memory Map
0x0000
0x0_0000
REGISTERS
REGISTERS
0x0400
Unimplemented Area
D-Flash
0x1400
RAM_LOW
RAM
Unpaged P-Flash
0x0_4000
0x0_4400
NVM Resources
D-Flash
RAM
0x0_5400
NVM Resources
0x4000
0x0_8000
Unpaged P-Flash
P-Flash
10 *16K paged
0x8000
0x3_0000
Unpaged P-Flash
or
0 0 0 0
P3P2P1
P0
Unpaged P-Flash
Unpaged P-Flash
P-Flash window
PPAGE
0x3_4000
0x3_8000
0xC000
Unpaged P-Flash
Unpaged P-Flash
Unpaged P-Flash
0x3_C000
0x3_FFFF
0xFFFF
Figure 60. Local to global address mapping
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4.19.5 Implemented memory in the system memory architecture
Each memory can be implemented in its maximum allowed size. But some devices have been defined for smaller sizes, which means
less implemented pages. All non implemented pages are called unimplemented areas.
•
•
•
•
•
Registers has a fixed size of 1.0 kB, accessible via xbus0
SRAM has a maximum size of 11 kB, accessible via xbus0
D-Flash has a fixed size of 4.0 kB accessible via xbus0
P-Flash has a maximum size of 224 kB, accessible via xbus0
NVM resources (IFR) including D-Flash have maximum size of 16 kB (PPAGE 0x01)
4.19.5.0.1
Implemented memory map
The global memory spaces reserved for the internal resources (RAM, D-Flash, and P-Flash) are not determined by the MMC module. Size
of the individual internal resources are however fixed in the design of the device cannot be changed by the user. Refer to the SoC Guide
for further details. Figure 61 and Table 322 show the memory spaces occupied by the on-chip resources. Note that the memory spaces
have fixed top addresses.
Table 322. Global implemented memory space
Internal resource
Registers
Bottom address
0x0_0000
Top address
0x0_03FF
0x0_3FFF
0x0_53FF
0x3_FFFF
(249)
(250)
System RAM
D-Flash
RAM_LOW = 0x0_4000 minus RAMSIZE
0x0_4400
P-Flash
PF_LOW = 0x4_0000 minus FLASHSIZE
Notes
249. RAMSIZE is the hexadecimal value of RAM SIZE in bytes
250. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes
In single-chip modes accesses by the CPU12 (except for firmware commands) to any of the unimplemented areas (see Figure 61) will
result in an illegal access reset (system reset). BDM accesses to the unimplemented areas are allowed but the data will be undefined.
No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block Guide).
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CPU and BDM
Global Memory Map
Local Memory Map
0x0000
REGISTERS
0x0_0000
REGISTERS
0x0400
D-Flash
Unimplemented Area
0x1400
RAM_LOW
Unpaged P-Flash
RAM
0x0_4000
0x0_4400
NVM Resources
D-Flash
RAM
0x0_5400
NVM Resources
0x4000
0x0_8000
Unpaged P-Flash
Unimplemented area
0x8000
0 0 0 0
P3P2P1
P0
P-Flash window
PPAGE
PF_LOW
0xC000
P-Flash
Unpaged P-Flash
0xFFFF
0x3_FFFF
Figure 61. Implemented global address mapping
4.19.5.1 Chip bus control
The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12, S12SBDM) with the rest of the
system (master buses). In addition, the MMC handles all CPU read data bus swapping operations. All internal resources are connected
to specific target buses (see Figure 62).
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DBG
CPU
BDM
S12X1
S12X0
MMC “Crossbar Switch”
XBUS0
BDM
IPBI
Peripherals
P-Flash
SRAM
D-Flash
resources
Figure 62. S12I platform
4.19.5.1.1
Master bus prioritization regarding access conflicts on target buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing
accesses from different masters to the same target bus:
•
•
CPU12 always has priority over BDM.
BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case the CPU will be stalled after
finishing the current operation and the BDM will gain access to the bus.
4.19.5.2 Interrupts
The MMC does not generate any interrupts.
4.19.6 Initialization/application information
4.19.6.1 CALL and RTC instructions
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the program page window. The CALL
instruction is similar to the JSR instruction, but the subroutine that is called can be located anywhere in the local address space or in any
Flash or ROM page visible through the program page window. The CALL instruction calculates and stacks a return address, stacks the
current PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value controls which of the 256
possible pages is visible through the 16 kbyte program page window in the 64 kbyte local CPU memory map. Execution then begins at
the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
1. Writes the current PPAGE value into an internal temporary register and writes the new instruction supplied PPAGE value into the
PPAGE register
2. Calculates the address of the next instruction after the CALL instruction (the return address) and pushes this 16-bit value onto
the stack
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new address
This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction execution. A CALL instruction can be
performed from any address to any other address in the local CPU memory space.
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The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing mode variations (except
indexed-indirect modes), the new page value is provided by an immediate operand in the instruction. In indexed indirect variations of the
CALL instruction, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored.
Using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time,
rather than immediate values that must be known at the time of assembly.
The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks the PPAGE value and the return
address and refills the queue. Execution resumes with the next instruction after the CALL instruction.
During the execution of an RTC instruction the CPU performs the following steps:
1. Pulls the previously stored PPAGE value from the stack
2. Pulls the 16-bit return address from the stack and loads it into the PC
3. Writes the PPAGE value into the PPAGE register
4. Refills the queue and resumes execution at the return address
This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory space.
The CALL and RTC instructions behave like JSR and RTS instruction. However they require more execution cycles. Usage of JSR/RTS
instructions is therefore recommended when possible, and CALL/RTC instructions should only be used when needed. The JSR and RTS
instructions can be used to access subroutines that are already present in the local CPU memory map (i.e. in the same page in the
program memory page window for example). However calling a function located in a different page requires usage of the CALL instruction.
The function must be terminated by the RTC instruction. Because the RTC instruction restores contents of the PPAGE register from the
stack. Functions terminated with the RTC instruction must be called using the CALL instruction, even when the correct page is already
present in the memory map. This is to make sure that the correct PPAGE value will be present on the stack at the time of the RTC
instruction execution.
4.20 MCU - debug module (9S12I128PIMV1)
4.20.1 Introduction
The 9S12I128PIMV1 module provides an on-chip trace buffer with flexible triggering capability, to allow non-intrusive debug of application
software. The 9S12I128PIMV1 module is optimized for S12SCPUdebugging.
Typically, the 9S12I128PIMV1 module is used in conjunction with the S12SBDM module, whereby the user configures the
9S12I128PIMV1 module for a debugging session over the BDM interface. Once configured the 9S12I128PIMV1 module is armed, the
device leaves BDM returning control to the user program, which is then monitored by the 9S12I128PIMV1 module. Alternatively the
9S12I128PIMV1 module can be configured over a serial interface using SWI routines.
4.20.1.1 Glossary Of terms
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
BDM: Background Debug Mode
S12SBDM: Background Debug Module
DUG: Device User Guide, describing the features of the device into which the DBG is integrated.
WORD: 16-bit data entity
Data Line: 20-bit data entity
CPU: S12SCPU module
DBG: S12SDBG module
POR: Power On Reset
Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit
occurs.
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The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition to the Final
state, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final state with associated tracing and breakpoint can be triggered immediately by
writing to the TRIG control bit. The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
4.20.1.3 Features
•
•
Three comparators (A, B and C)
—
—
—
—
—
—
Comparators A compares the full address bus and full 16-bit data bus
Comparator A features a data bus mask register
Comparators B and C compare the full address bus only
Each comparator features selection of read or write access cycles
Comparator B allows selection of byte or word access cycles
Comparator matches can initiate state sequencer transitions
Three comparator modes
—
—
—
Simple address/data comparator match mode
Inside address range mode, Addmin Address Addmax
Outside address range match mode, Address Addminor Address Addmax
•
•
Two types of matches
—
—
Tagged — This matches just before a specific instruction begins execution
Force — This is valid on the first instruction boundary after a match occurs
Two types of breakpoints
—
—
CPU breakpoint entering BDM on breakpoint (BDM)
CPU breakpoint executing SWI on breakpoint (SWI)
•
•
Trigger mode independent of comparators
TRIG Immediate software trigger
Four trace modes
—
—
Normal: change of flow (COF) PC information is stored (see Section 4.20.4.5.2.1, “Normal mode") for change of flow
definition.
—
—
—
Loop1: same as Normal but inhibits consecutive duplicate source address entries
Detail: address and data for all cycles except free cycles and opcode fetches are stored
Compressed Pure PC: all program counter addresses are stored
•
4-stage state sequencer for trace buffer control
—
—
Tracing session trigger linked to Final State of state sequencer
Begin and End alignment of tracing to trigger
4.20.1.4 Modes of operation
The DBG module can be used in all MCU functional modes. During BDM hardware accesses and while the BDM module is active, CPU
monitoring is disabled. When the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already armed,
remains armed. The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated.
Table 323. Mode dependent restriction summary
BDM enable BDM active MCU secure
Comparator matches enabled
Breakpoints possible Tagging possible
Tracing possible
x
0
0
1
1
x
0
1
0
1
1
0
0
0
0
Yes
Yes
Yes
Yes
Yes
No
Only SWI
Yes
Active BDM not possible when not enabled
Yes
No
Yes
No
Yes
No
Yes
No
4.20.1.5 Block diagram
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TAGS
TAGHITS
BREAKPOINT REQUESTS
TO CPU
SECURE
CPU BUS
TRANSITION
TAG &
MATCH0
MATCH1
MATCH2
COMPARATOR A
COMPARATOR B
COMPARATOR C
MATCH
CONTROL
LOGIC
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
TRACE BUFFER
READ TRACE DATA (DBG READ DATA BUS)
Figure 63. Debug module block diagram
4.20.2 External signal description
There are no external signals associated with this module.
4.20.3 Memory map and registers
4.20.3.1 Module memory map
A summary of the registers associated with the DBG sub-block is shown in Table 324. Detailed descriptions of the registers and bits are
given in the subsections that follow.
Table 324. Quick reference to DBG registers
Address
Name
Bit 7
6
0
5
4
BDM
0
3
DBGBRK
0
2
1
Bit 0
R
W
R
0
0
0x0020
DBGC1
ARM
COMRV
TRIG
0
(251)
TBF
0
0
SSF2
SSF1
0
SSF0
0x0021
0x0022
0x0023
0x0024
0x0025
DBGSR
DBGTCR
DBGC2
W
R
0
0
0
0
TSOURCE
0
TRCMOD
TALIGN
W
R
0
0
0
ABCM
W
R
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
DBGTBH
DBGTBL
W
R
W
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Table 324. Quick reference to DBG registers (continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
TBF
0
CNT
0x0026
DBGCNT
0
0
0
0
0
0
0
0
0x0027
0x0027
DBGSCRX
DBGMFR
DBGACTL
DBGBCTL
DBGCCTL
DBGXAH
DBGXAM
DBGXAL
DBGADH
DBGADL
SC3
0
SC2
MC2
SC1
MC1
SC0
MC0
W
R
W
R
(252)
0x0028
0x0028
0x0028
SZE
SZ
TAG
TAG
BRK
BRK
RW
RW
RWE
RWE
NDB
0
COMPE
COMPE
COMPE
Bit 16
Bit 8
W
R
(253)
(254)
SZE
0
SZ
0
W
R
0
TAG
0
BRK
0
RW
0
RWE
0
W
R
0
0
0x0029
Bit 17
W
R
0x002A
0x002B
0x002C
0x002D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
W
R
Bit 0
W
R
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 8
W
R
Bit 0
W
R
0x002E
0x002F
DBGADHM
DBGADLM
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
W
R
W
Notes
251. This bit is visible at DBGCNT[7] and DBGSR[7]
252. This represents the contents if the Comparator A control register is blended into this address
253. This represents the contents if the Comparator B control register is blended into this address
254. This represents the contents if the Comparator C control register is blended into this address
4.20.3.2 Register descriptions
This section consists of the DBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers
that are visible through an 8-byte window between 0x0028 and 0x002F in the DBG module register address map. When ARM is set in
DBGC1, the only bits in the DBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
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4.20.3.2.1
Debug control register 1 (DBGC1)
Table 325. Debug control register (DBGC1)
Address: 0x0020
7
ARM
0
6
0
5
0
4
BDM
0
3
DBGBRK
0
2
0
1
0
0
0
R
W
COMRV
TRIG
0
Reset
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
NOTE
When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by
the write, since up until the write operation, ARM = 1 preventing these bits from being written. These
bits must be cleared using a second write if required.
Table 326. DBGC1 field descriptions
Field
Description
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically
cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer
enters State1.
7
ARM
0
1
Debugger disarmed
Debugger armed
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state sequencer status.
When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads
back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already
commenced using BEGIN trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has
no affect. In secure mode, tracing is disabled and writing to this bit cannot initiate a tracing session.
6
TRIG
The session is ended by setting TRIG and ARM simultaneously.
0
1
Do not trigger until the state sequencer enters the Final state.
Trigger immediately
Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background Debug mode (BDM)
or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints
default to SWI.
4
BDM
0
1
Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
9S12I128PIMV1 Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint on reaching the
state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not
enabled, the breakpoint is generated immediately.
3
DBGBRK
0
1
No Breakpoint generated
Breakpoint generated
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the
S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the
address 0x0027. See Table 327.
1–0
COMRV
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Table 327. COMRV encoding
COMRV
00
Visible comparator
Visible register at 0x0027
DBGSCR1
Comparator A
Comparator B
Comparator C
None
01
DBGSCR2
10
DBGSCR3
11
DBGMFR
4.20.3.2.2
Debug status register (DBGSR)
Table 328. Debug status register (DBGSR)
Address: 0x0021
7
6
0
5
0
4
0
3
0
2
1
0
R
TBF
SSF2
SSF1
SSF0
W
Reset
POR
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Never
Table 329. DBGSR field descriptions
Field
Description
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is
set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to
a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit
7
TBF
This bit is also visible at DBGCNT[7]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each
transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain
their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the
state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module
the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 330.
2–0
SSF[2:0]
Table 330. SSF[2:0] — State sequence flag bit encoding
SSF[2:0]
000
Current state
State0 (disarmed)
State1
001
010
State2
011
State3
100
Final State
Reserved
101,110,111
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4.20.3.2.3
Debug trace control register (DBGTCR)
Table 331. Debug trace control register (DBGTCR)
Address: 0x0022
7
0
6
5
0
4
0
3
0
2
0
1
0
0
TALIGN
0
R
W
TSOURCE
0
TRCMOD
Reset
0
0
0
0
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Table 332. DBGTCR field descriptions
Field
Description
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is secured, this
bit cannot be set and tracing is inhibited.
6
This bit must be set to read the trace buffer.
TSOURCE
0
1
Debug session without tracing requested
Debug session with tracing requested
Trace Mode Bits — See Section 4.20.4.5.2, “Trace modes" for detailed Trace mode descriptions. In Normal mode, change of flow
information is stored. In Loop1 mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail
mode, address and data for all memory and register accesses is stored. In Compressed Pure PC mode the program counter value for
each instruction executed is stored. See Table 333.
3–2
TRCMOD
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0
0
1
Trigger at end of stored data
Trigger before storing data
TALIGN
Table 333. TRCMOD trace mode bit encoding
TRCMOD
Description
Normal
Loop1
00
01
10
Detail
11
Compressed Pure PC
4.20.3.2.4
Debug control register2 (DBGC2)
Table 334. Debug control register2 (DBGC2)
Address: 0x0023
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
ABCM
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime the module is disarmed
This register configures the comparators for range matching.
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Table 335. DBGC2 field descriptions
Field
Description
1–0
ABCM[1:0]
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 336.
Table 336. ABCM encoding
ABCM
Description
00
01
10
11
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
Match 0 mapped to comparator A/B inside range: Match1 disabled.
Match 0 mapped to comparator A/B outside range: Match1 disabled.
(255)
Reserved
Notes
255. Currently defaults to Comparator A, Comparator B disabled
4.20.3.2.5
Debug trace buffer register (DBGTBH:DBGTBL)
Table 337. Debug trace buffer register (DBGTB)
Address:
0x0024, 0x0025
15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other
Resets
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents
Table 338. DBGTB field descriptions
Field
Description
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer may be
read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read.
When the ARM bit is set the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to
DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte
reads or misaligned access of these registers return a 0, and do not cause the trace buffer pointer to increment to the next trace buffer
address. Similarly reads while the debugger is armed or with the TSOURCE bit clear, return a 0, and do not affect the trace buffer pointer.
The POR state is undefined. Other resets do not affect the trace buffer contents.
15–0
Bit[15:0]
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4.20.3.2.6
Debug count register (DBGCNT)
Table 339. Debug count register (DBGCNT)
Address: 0x0026
7
6
0
5
4
3
2
1
0
R
TBF
CNT
W
Reset
POR
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
0
= Unimplemented or Reserved
Read: Anytime
Write: Never
Table 340. DBGCNT field descriptions
Field
Description
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is
set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written
to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit
7
TBF
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer. Table 341 shows the
correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in
DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is
written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should
a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored
before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer.
5–0
CNT[5:0]
Table 341. CNT decoding table
TBF
CNT[5:0]
Description
0
000000
No data valid
000001
000010
000100
000110
...
1 line valid
2 lines valid
4 lines valid
6 lines valid
...
0
111111
63 lines valid
64 lines valid; if using Begin trigger alignment, ARM bit will
be cleared and the tracing session ends.
1
1
000000
000001
...
64 lines valid, oldest data has been overwritten by most
recent data
...
111110
4.20.3.2.7
Debug state control registers
There is a dedicated control register for each of the state sequencer states 1 to 3, that determines if transitions from that state are allowed,
depending upon comparator matches or tag hits, and define the next state for the state sequencer following a match. The three debug
state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the
COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR).
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Table 342. State control register access encoding
COMRV
00
Visible state control register
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
01
10
11
4.20.3.2.7.1 Debug state control register 1 (DBGSCR1)
Table 343. Debug state control register 1 (DBGSCR1)
Address: 0x0027
7
0
6
0
5
0
4
0
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
R
W
Reset
0
0
0
0
= Unimplemented or Reserved
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state while in State1.
The matches refer to the match channels of the comparator match control logic, as depicted in Figure 63 and described in
Section 4.20.3.2.8.1, “Debug comparator control register (DBGXCTL)". Comparators must be enabled by setting the comparator enable
bit in the associated DBGXCTL control register.
Table 344. DBGSCR1 field descriptions
Field
Description
3–0
SC[3:0]
These bits select the targeted next state while in State1, based upon the match event.
Table 345. State1 sequencer next state selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Description (unspecified matches have no effect)
Any match to Final State
Match1 to State3
Match2 to State2
Match1 to State2
Match0 to State2....... Match1 to State3
Match1 to State3.........Match0 to Final State
Match0 to State2....... Match2 to State3
Either Match0 or Match1 to State2
Reserved
Match0 to State3
Reserved
Reserved
Reserved
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Table 345. State1 sequencer next state selection (continued)
SC[3:0]
1101
Description (unspecified matches have no effect)
Either Match0 or Match2 to Final State........Match1 to State2
1110
Reserved
Reserved
1111
The priorities described in Table 378 dictate that in the case of simultaneous matches, a match leading to final state has priority followed
by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101, a simultaneous match0/match1 transitions to Final state.
4.20.3.2.7.2 Debug state control register 2 (DBGSCR2)
Table 346. Debug state control register 2 (DBGSCR2)
Address: 0x0027
7
0
6
0
5
0
4
0
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
R
W
Reset
0
0
0
0
= Unimplemented or Reserved
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state while in State 2.
The matches refer to the match channels of the comparator match control logic, as depicted in Figure 63 and described in
Section 4.20.3.2.8.1, “Debug comparator control register (DBGXCTL)". Comparators must be enabled by setting the comparator enable
bit in the associated DBGXCTL control register.
Table 347. DBGSCR2 field descriptions
Field
Description
3–0
SC[3:0]
These bits select the targeted next state while in State 2, based upon the match event.
Table 348. State2 —sequencer next state selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Description (unspecified matches have no effect)
Match0 to State1....... Match2 to State3.
Match1 to State3
Match2 to State3
Match1 to State3....... Match0 Final State
Match1 to State1....... Match2 to State3.
Match2 to Final State
Match2 to State1..... Match0 to Final State
Either Match0 or Match1 to Final State
Reserved
1000
1001
1010
1011
Reserved
Reserved
Reserved
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Table 348. State2 —sequencer next state selection (continued)
SC[3:0]
1100
Description (unspecified matches have no effect)
Either Match0 or Match1 to Final State........Match2 to State3
Reserved
1101
1110
Reserved
1111
Either Match0 or Match1 to Final State........Match2 to State1
The priorities described in Table 378 dictate that in the case of simultaneous matches, a match leading to final state has priority followed
by the match on the lower channel number (0,1,2).
4.20.3.2.7.3 Debug state control register 3 (DBGSCR3)
Table 349. Debug state control register 3 (DBGSCR3)
Address: 0x0027
7
0
6
0
5
0
4
0
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
R
W
Reset
0
0
0
0
= Unimplemented or Reserved
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state while in State
3. The matches refer to the match channels of the comparator match control logic, as depicted in Figure 63 and described in
Section 4.20.3.2.8.1, “Debug comparator control register (DBGXCTL)". Comparators must be enabled by setting the comparator enable
bit in the associated DBGXCTL control register.
Table 350. DBGSCR3 field descriptions
Field
Description
3–0
SC[3:0]
These bits select the targeted next state while in State 3, based upon the match event.
Table 351. State3 — sequencer next state selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Description (Unspecified matches have no effect)
Match0 to State1
Match2 to State2........ Match1 to Final State
Match0 to Final State....... Match1 to State1
Match1 to Final State....... Match2 to State1
Match1 to State2
Match1 to Final State
Match2 to State2........ Match0 to Final State
Match0 to Final State
1000
1001
1010
Reserved
Reserved
Either Match1 or Match2 to State1....... Match0 to Final State
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Table 351. State3 — sequencer next state selection (continued)
SC[3:0]
1011
1100
1101
1110
Description (Unspecified matches have no effect)
Reserved
Reserved
Either Match1 or Match2 to Final State....... Match0 to State1
Match0 to State2....... Match2 to Final State
Reserved
1111
The priorities described in Table 378 dictate that in the case of simultaneous matches, a match leading to final state has priority, followed
by the match on the lower channel number (0,1,2).
4.20.3.2.7.4 Debug match flag register (DBGMFR)
Table 352. Debug match flag register (DBGMFR)
Address: 0x0027
7
0
6
0
5
0
4
0
3
0
2
1
0
R
W
MC2
MC1
MC0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits, each mapped directly to a channel. Should a match occur
on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed, by
writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by
software. They are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further
comparator matches on the same channel in the same session have no affect on that flag.
4.20.3.2.8
Comparator register descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map. Comparator
A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers, and a
control register). Comparator B consists of four register bytes (three address bus compare registers and a control register). Comparator
C consists of four register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g.
Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs from those
of comparators A and C.
Table 353. Comparator register layout
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
CONTROL
ADDRESS HIGH
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparator A only
ADDRESS MEDIUM
ADDRESS LOW
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
DATA HIGH MASK
Comparator A only
Comparator A only
DATA LOW MASK
Comparator A only
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4.20.3.2.8.1 Debug comparator control register (DBGXCTL)
The contents of register bits 7 and 6 differ, depending upon which comparator registers are visible in the 8-byte window of the DBG module
register address map.
Table 354. Debug comparator control register DBGACTL (comparator A)
Address: 0x0028
7
SZE
0
6
SZ
0
5
4
BRK
0
3
RW
0
2
RWE
0
1
NDB
0
0
COMPE
0
R
W
TAG
Reset
0
= Unimplemented or Reserved
Table 355. Debug comparator control register DBGBCTL (comparator B)
Address: 0x0028
7
SZE
0
6
SZ
0
5
4
BRK
0
3
RW
0
2
RWE
0
1
0
0
COMPE
0
R
W
TAG
Reset
0
0
= Unimplemented or Reserved
Table 356. Debug comparator control register DBGCCTL (comparator C)
Address: 0x0028
7
0
6
0
5
4
BRK
0
3
RW
0
2
RWE
0
1
0
0
COMPE
0
R
W
TAG
Reset
0
0
0
0
= Unimplemented or Reserved
Read: DBGACTL if COMRV[1:0] = 00
DBGBCTL if COMRV[1:0] = 01
DBGCCTL if COMRV[1:0] = 10
Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed
DBGBCTL if COMRV[1:0] = 01 and DBG not armed
DBGCCTL if COMRV[1:0] = 10 and DBG not armed
Table 357. DBGXCTL field descriptions
Field
Description
7
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator.
This bit is ignored if the TAG bit in the same register is set.
SZE
0
1
Word/Byte access size is not used in comparison
Word/Byte access size is used in comparison
(Comparators
A and B)
6
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This
bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
SZ
0
1
Word access size is compared
Byte access size is compared
(Comparators
A and B)
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Table 357. DBGXCTL field descriptions (continued)
Field
Description
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer transition
or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
5
0
1
Allow state sequencer transition immediately on match
On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
TAG
Break— This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer
state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit DBGBRK.
4
BRK
0
1
The debug session termination is dependent upon the state sequencer and trigger conditions.
A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is
terminated and the module disarmed.
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator.
The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set.
3
RW
0
Write cycle is matched1Read cycle is matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator.This bit
is ignored if the TAG bit in the same register is set
2
0
1
Read/Write is not used in comparison
Read/Write is used in comparison
RWE
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when
the data bus differs from the register value. This bit is ignored if the TAG bit in the same register is set. This bit is only available for
comparator A.
1
NDB
(Comparator A)
0
1
Match on data bus equivalence to comparator register contents
Match on data bus difference to comparator register contents
Determines if comparator is enabled
0
0
1
The comparator is not enabled
The comparator is enabled
COMPE
Table 358 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit is set,
since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue.
Table 358. Read or write comparison logic table
RWE bit
RW bit
RW signal
Comment
RW not used in comparison
RW not used in comparison
Write data bus
0
0
1
1
1
1
x
x
0
0
1
1
0
1
0
1
0
1
No match
No match
Read data bus
4.20.3.2.8.2 Debug comparator address high register (DBGXAH)
Table 359. Debug comparator address high register (DBGXAH)
Address: 0x0029
7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 17
0
0
Bit 16
0
R
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F, as
shown in Table 360
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Table 360. Comparator address register visibility
COMRV
00
Visible comparator
DBGAAH, DBGAAM, DBGAAL
DBGBAH, DBGBAM, DBGBAL
DBGCAH, DBGCAM, DBGCAL
None
01
10
11
Notes
256. Read: Anytime. See Table for visible register encoding.
Write: If DBG not armed. See Table for visible register encoding.
Table 361. DBGXAH field descriptions
Field
Description
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator
compares the address bus bits [17:16] to a logic one or logic zero.
1–0
0
1
Compare corresponding address bit to a logic zero
Compare corresponding address bit to a logic one
Bit[17:16]
4.20.3.2.8.3 Debug comparator address mid register (DBGXAM)
Table 362. Debug comparator address mid register (DBGXAM)
Address: 0x002A
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
R
W
Reset
Read: Anytime. See Table 360 for visible register encoding.
Write: If DBG not armed. See Table 360 for visible register encoding.
Table 363. DBGXAM field descriptions
Field
Description
Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator
compares the address bus bits [15:8] to a logic one or logic zero.
7–0
0
1
Compare corresponding address bit to a logic zero
Compare corresponding address bit to a logic one
Bit[15:8]
4.20.3.2.8.4 Debug comparator address low register (DBGXAL)
Table 364. Debug comparator address low register (DBGXAL)
Address: 0x002B
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
R
W
Reset
Read: Anytime. See Table for visible register encoding
Write: If DBG not armed. See Table for visible register encoding
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Table 365. DBGXAL field descriptions
Field
Description
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator
compares the address bus bits [7:0] to a logic one or logic zero.
7–0
0
1
Compare corresponding address bit to a logic zero
Compare corresponding address bit to a logic one
Bits[7:0]
4.20.3.2.8.5 Debug comparator data high register (DBGADH)
Table 366. Debug comparator data high register (DBGADH)
Address: 0x002C
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
R
W
Reset
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed
Table 367. DBGADH field descriptions
Field
Description
Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected comparator compares
the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding
data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in
DBGACTL is clear.
7–0
Bits[15:8]
0
1
Compare corresponding data bit to a logic zero
Compare corresponding data bit to a logic one
4.20.3.2.8.6 Debug comparator data low register (DBGADL)
Table 368. Debug comparator data low register (DBGADL)
Address: 0x002D
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
R
W
Reset
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed
Table 369. DBGADL field descriptions
Field
Description
Comparator Data Low Compare Bits — The Comparator data low compare bits control, whether the selected comparator compares
the data bus bits [7:0] to a logic one or a logic zero. The comparator data compare bits are only used in comparison if the corresponding
data mask bit is a logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in
DBGACTL is clear
7–0
Bits[7:0]
0
1
Compare corresponding data bit to a logic zero
Compare corresponding data bit to a logic one
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4.20.3.2.8.7 Debug comparator data high mask register (DBGADHM)
Table 370. Debug comparator data high mask register (DBGADHM)
Address: 0x002E
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
R
W
Reset
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed
Table 371. DBGADHM field descriptions
Field
Description
Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data
bus bits [15:8] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL
is clear
7–0
Bits[15:8]
0
1
Do not compare corresponding data bit Any value of corresponding data bit allows match.
Compare corresponding data bit
4.20.3.2.8.8 Debug comparator data low mask register (DBGADLM)
Table 372. Debug comparator data low mask register (DBGADLM)
Address: 0x002F
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
R
W
Reset
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed
Table 373. DBGADLM field descriptions
Field
Description
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data
bus bits [7:0] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL
is clear
7–0
Bits[7:0]
0
1
Do not compare corresponding data bit. Any value of corresponding data bit allows match
Compare corresponding data bit
4.20.4 Functional description
This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can generate
breakpoints, but tracing is not possible.
4.20.4.1 9S12I128PIMV1 operation
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer, and generation
of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the
trace buffer.
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The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity. Comparator A
can also be configured to monitor data bus activity and mask out individual data bus bits during a compare. Comparators can be configured
to use R/W and word/byte access qualification in the comparison. A match with a comparator register value can initiate a state sequencer
transition to another state (see Figure 65). Either forced or tagged matches are possible. Using a forced match, a state sequencer
transition can occur immediately on a successful match of system busses and comparator registers. While tagging at a comparator match,
the instruction opcode is tagged, and only if the instruction reaches the execution stage of the instruction queue, can a state sequencer
transition occur. In the case of a transition to Final state, bus tracing is triggered, and/or a breakpoint can be generated.
A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in the DBGC1
control register. The trace buffer is visible through a 2-byte window in the register address map and must be read out using standard 16-bit
word reads.
TAGS
TAGHITS
BREAKPOINT REQUESTS
TO CPU
SECURE
CPU BUS
TRANSITION
MATCH0
MATCH1
MATCH2
COMPARATOR A
COMPARATOR B
COMPARATOR C
TAG &
MATCH
CONTROL
LOGIC
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
TRACE BUFFER
READ TRACE DATA (DBG READ DATA BUS)
Figure 64. DBG overview
4.20.4.2 Comparator modes
The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with the address stored in
DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH, DBGADL
and allows masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 64) configures
comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified
range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by
the DBGC2 contents.
Amatch can initiate a transition to another state sequencer state (see Section 4.20.4.4, “State sequence control"”). The comparator control
register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit
controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access
for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte) to be considered in the compare. Only comparators
A and B feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator qualifies a match
with the output of opcode tracking logic, and a state sequencer transition occurs when the tagged instruction reaches the CPU execution
stage. While tagging, the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored; the comparator address register
must be loaded with the exact opcode address.
If the TAG bit is clear (forced type match), a comparator match is generated when the selected address appears on the system address
bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory, which precedes
the instruction execution by an indefinite number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd
address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address
(n), the comparator register must contain address (n–1).
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Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent
matches. If a particular data value is verified at a given address, this address may not still contain that data value when a subsequent
match occurs.
Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see Section 4.20.3.2.4, “Debug control register2
(DBGC2)"). Comparator channel priority rules are described in the priority section (Section 4.20.4.3.4, “Channel priorities").
4.20.4.2.1
Single address comparator match
With range comparisons disabled, the match condition is an exact equivalence of address bus, with the value stored in the comparator
address registers. Further qualification of the type of access (R/W, word/byte) and data bus contents is possible, depending on comparator
channel.
4.20.4.2.1.1 Comparator C
Comparator C offers only address and direction (R/W) comparison. The exact address is compared, with the comparator address register
loaded with address (n), a word access of address (n–1) also accesses (n) but does not cause a match.
Table 374. Comparator C access considerations
Condition for valid match
Comp C address
RWE
RW
Examples
LDAA ADDR[n]
STAA #$BYTE ADDR[n]
(257)
Read and write accesses of ADDR[n]
ADDR[n]
0
X
Write accesses of ADDR[n]
Read accesses of ADDR[n]
ADDR[n]
ADDR[n]
1
1
0
1
STAA #$BYTE ADDR[n]
LDAA #$BYTE ADDR[n]
Notes
257. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact
address from the code.
4.20.4.2.1.2 Comparator B
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is set, the access size (word or byte)
is compared with the SZ bit value such that only the specified size of access causes a match. If configured for a byte access of a particular
address, a word access covering the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are shown in Table 375.
Table 375. Comparator B access size considerations
Condition for valid match
Comp B address
RWE
SZE
SZ8
Examples
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
(258)
Word and byte accesses of ADDR[n]
ADDR[n]
0
0
X
MOVW #$WORD ADDR[n]
LDD ADDR[n]
Word accesses of ADDR[n] only
Byte accesses of ADDR[n] only
ADDR[n]
ADDR[n]
0
0
1
1
0
1
MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
Notes
258. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact
address from the code.
Access direction can also be used to qualify a match for Comparator B in the same way, as described for Comparator C in Table 374.
4.20.4.2.1.3 Comparator A
Comparator A offers address, direction (R/W), access size (word/byte), and data bus comparison. Table 376 lists access considerations
with data bus comparison. On word accesses, the data byte of the lower address is mapped to DBGADH. Access direction can also be
used to qualify a match for Comparator A in the same way as described for Comparator C in Table 374.
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Table 376. Comparator A matches when accessing ADDR[n]
DBGADHM,
SZE
SZ
Access DH=DBGADH, DL=DBGADL
Comment
No databus comparison
Match data(ADDR[n])
DBGADLM
Byte
Word
0
X
$0000
Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
0
X
$FF00
0
0
0
0
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
$00FF
$00FF
$FFFF
$FFFF
$0000
$00FF
$FF00
$FFFF
$0000
$FF00
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Word
Match data(ADDR[n+1])
Possible unintended match
Match data(ADDR[n], ADDR[n+1])
Possible unintended match
No databus comparison
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte
Match only data at ADDR[n+1]
Match only data at ADDR[n]
Match data at ADDR[n] & ADDR[n+1]
No databus comparison
Byte, data(ADDR[n])=DH
Match data at ADDR[n]
4.20.4.2.1.4 Comparator A data bus comparison NDB dependency
Comparator A features an NDB control bit, which allows data bus comparators to be configured to either trigger on equivalence or trigger
on difference. This allows monitoring of a difference in the contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask
bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits
set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. Amatch occurs when any data bus bit with corresponding
mask bit set is different. Clearing all mask bits causes all bits to be ignored and prevents a match because no difference can be detected.
In this case, address bus equivalence does not cause a match.
Table 377. NDB and MASK bit dependency
DBGADHM[n] /
NDB
Comment
DBGADLM[n]
0
0
1
1
0
1
0
1
Do not compare data bus bit.
Compare data bus bit. Match on equivalence.
Do not compare data bus bit.
Compare data bus bit. Match on difference.
4.20.4.2.2
Range comparisons
Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data
registers. Furthermore, the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access.
The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator ATAG bit is used
to tag range comparisons. The comparator B TAG bit is ignored in range modes. For a range comparison using comparators A and B,
both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for
the AB range, the comparator B BRK bit is ignored in range mode.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
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4.20.4.2.2.1 Inside range (CompA_Addr address CompB_Addr)
In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration depends
upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle.
A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary is valid only if the
aligned address is inside the range.
4.20.4.2.2.2 Outside range (address < CompA_Addr or address > CompB_Addr)
In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on
either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid, only if the aligned
address is outside the range.
Outside range mode in combination with tagging can be used to detect, if the opcode fetches are from an unexpected range. In forced
match mode, the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by
setting the upper range limit to $3FFFF or lower range limit to $00000 respectively.
4.20.4.3 Match modes (forced or tagged)
Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the match
mode. The modes are described in the following sections.
4.20.4.3.1
Forced match
When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state,
whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state. Forced
matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of comparator RWE/RW settings.
Furthermore, since opcode fetches occur several cycles before the opcode execution, a forced match of an opcode address typically
precedes a tagged match at the same address.
4.20.4.3.2
Tagged match
If a CPU taghit occurs, a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a
comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the tagged
instruction reaches the execution stage of the instruction queue, a taghit is generated by the CPU. This can initiate a state sequencer
transition.
4.20.4.3.3
Immediate trigger
Independent of comparator matches, it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. If
configured for begin aligned tracing, this triggers the state sequencer into the Final state, if configured for end alignment, setting the TRIG
bit disarms the module, ending the session and issues a forced breakpoint request to the CPU.
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM.
4.20.4.3.4
Channel priorities
In case of simultaneous matches, the priority is resolved according to Table 378. The lower priority is suppressed. It is possible to miss a
lower priority match, if it occurs simultaneously with a higher priority. The priorities described in Table 378 dictate that in the case of
simultaneous matches, the match pointing to Final state has highest priority, followed by the lower channel number (0,1,2).
Table 378. Channel priorities
Priority
Source
Action
Highest
TRIG
Enter Final State
Channel pointing to Final State
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Lowest
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4.20.4.4 State sequence control
ARM = 0
ARM = 1
State 0
(Disarmed)
ARM = 0
State1
State2
Session Complete
(Disarm)
State3
Final State
ARM = 0
Figure 65. State sequencer diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG
module has been armed by setting the ARM bit in the DBGC1 register, the state 1 of the state sequencer is entered. Further transitions
between the states are then controlled by the state control registers and channel matches. From Final state, the only permitted transition
is back to the disarmed state 0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in
DBGSR accordingly to indicate the current state. Alternatively, writing to the TRIG bit in DBGSC1, provides an immediate trigger
independent of comparator matches.
Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when
a match occurs, through the use of the BRK bits in the DBGxCTL registers. It is possible to generate an immediate breakpoint on selected
channels, while a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a match on a
channel, the state sequencer transitions through Final state for a clock cycle to state 0. This is independent of tracing and breakpoint
activity, and with tracing and breakpoints disabled, the state sequencer enters state 0 and the debug module is disarmed.
4.20.4.4.1
Final state
On entering Final state, a trigger may be issued to the trace buffer according to the trace alignment control, as defined by the TALIGN bit
(see Section 4.20.3.2.3, “Debug trace control register (DBGTCR)"”). If the TSOURCE bit in DBGTCR is clear, then the trace buffer is
disabled and the transition to Final state can only generate a breakpoint request. In this case or upon completion of a tracing session when
tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state 0. If tracing is enabled, a
breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled, when the final state is
reached, it returns automatically to state 0 and the debug module is disarmed.
4.20.4.5 Trace buffer operation
The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular
buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After
each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read receives fresh information.
Data is stored in the format shown in Table 379 and Table 375. After each store the counter register DBGCNT is incremented. Tracing of
CPU activity is disabled when the BDM is active. Reading the trace buffer while the DBG is armed, returns invalid data and the trace buffer
pointer is not incremented.
4.20.4.5.1
Trace trigger alignment
Using the TALIGN bit (see Section 4.20.3.2.3, “Debug trace control register (DBGTCR)"), it is possible to align the trigger with the end or
the beginning of a tracing session.
If End tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final state signals the
end of the tracing session. Tracing with Begin Trigger starts at the opcode of the trigger. Using End Trigger or when the tracing is initiated
by writing to the TRIG bit while configured for Begin Trigger, tracing starts in the second cycle after the DBGC1 write cycle.
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4.20.4.5.1.1 Storing with begin trigger
Storing with Begin Trigger, data is not stored in the Trace Buffer until the Final state is entered. Once the trigger condition is met, the DBG
module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction, the
change of flow associated with the trigger is stored in the Trace Buffer. Using Begin Trigger together with tagging, if the tagged instruction
is about to be executed, then the trace is started. Upon completion of the tracing session, the breakpoint is generated, thus the breakpoint
does not occur at the tagged instruction boundary.
4.20.4.5.1.2 Storing with end trigger
Storing with End Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes
disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction, the trigger event is not stored in the
Trace Buffer.
4.20.4.5.2
Trace modes
Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the
TSOURCE bit in the DBGTCR register. The modes are described in the following subsections.
4.20.4.5.2.1 Normal mode
In Normal mode, change of flow (COF) program counter (PC) addresses are stored.
COF addresses are defined as follows:
•
•
•
•
Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR, and CALL instruction
Destination address of RTI, RTS, and RTC instructions
Vector address of interrupts, except for BDM vectors
LBRA, BRA, BSR, BGND, as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored
in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the
stored address was a source address or destination address.
NOTE
When a COF instruction with destination address is executed, the destination address is stored to the
trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs
simultaneously, then the next instruction carried out is actually from the interrupt service routine. The
instruction at the destination address of the original program flow gets executed after the interrupt
service routine.
In the following example, an IRQ interrupt occurs during execution of the indexed JMP at address
MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine, but
the destination address is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX
JMP
NOP
#SUB_1
0,X
MARK1
MARK2
; IRQ interrupt occurs during execution of this
;
SUB_1
ADDR1
BRN
*
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
NOP
DBNE
A,PART5
; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB
#$F0
VAR_C1
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
STAB
RTI
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The execution flow taking into account the IRQ is as follows
#SUB_1
0,X
LDX
JMP
IRQ_ISR LDAB
MARK1
;
;
#$F0
STAB
RTI
VAR_C1
;
SUB_1
ADDR1
BRN
NOP
DBNE
*
;
;
A,PART5
4.20.4.5.2.2 Loop1 mode
Loop1 mode, similarly to Normal mode also stores only COF address information to the trace buffer, it however allows the filtering out of
redundant information.
The intent of Loop1 mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct, such
as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed
in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in
the Trace Buffer resulting from repeated branches.
Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It
does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate
a bug in the user’s code that the DBG module is designed to help find.
4.20.4.5.2.3 Detail mode
In Detail mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply
additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information
required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each
address byte storage. The information bits indicate the size of access (word or byte) and the type of access (read or write).
When tracing in Detail mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle.
4.20.4.5.2.4 Compressed pure PC mode
In Compressed Pure PC mode, the PC addresses of all executed opcodes, including where illegal opcodes are stored. A compressed
storage format is used to increase the effective depth of the trace buffer. This is achieved by storing the lower order bits each time and
using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored.
Each Trace Buffer row consists of 2 information bits and 18 PC address bits
NOTE:
When tracing is terminated using forced breakpoints, latency in breakpoint generation means that
opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number
of opcodes is dependent on program flow. This can be avoided by using tagged breakpoints.
4.20.4.5.3
Trace buffer organization (normal, loop1, detail modes)
ADRH, ADRM, ADRL denote address high, middle, and low byte respectively. The numerical suffix refers to the tracing count. The
information format for Loop1 and Normal modes are identical. In Detail mode, the address and data for each entry are stored on
consecutive lines, thus the maximum number of entries is 32. In this case, DBGCNT bits are incremented twice, once for the address line,
and once for the data line, on each trace buffer entry. In Detail mode, CINF comprises of R/W and size access information (CRW and CSZ
respectively).
Single byte data accesses in Detail mode are always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. When
tracing word accesses, the byte at the lower address is always stored to trace buffer byte1 and the byte at the higher address is stored to
byte0.
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Table 379. Trace buffer organization (normal, loop1, detail modes)
4-bits
Field 2
CINF1,ADRH1
0
8-bits
Field 1
ADRM1
DATAH1
ADRM2
DATAH2
PCM1
8-bits
Entry
Number
Mode
Field 0
ADRL1
DATAL1
ADRL2
DATAL2
PCL1
Entry 1
Entry 2
Detail Mode
CINF2,ADRH2
0
Entry 1
Entry 2
PCH1
Normal/Loop1
Modes
PCH2
PCM2
PCL2
4.20.4.5.3.1 Information bit organization
The format of the bits is dependent upon the active trace mode as described by the following.
4.20.4.5.3.1.1 Field2 bits in detail mode
Table 380. Field2 bits in detail mode
Bit 3
Bit 2
Bit 1
Bit 0
CSZ
CRW
ADDR[17]
ADDR[16]
In Detail Mode, the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 381. Field descriptions
Bit
Description
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail mode
3
CSZ
0
1
Word Access
Byte Access
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when tracing in
Detail mode.
2
0
1
Write Access
Read Access
CRW
1
Address Bus bit 17— Corresponds to system address bus bit 17.
Address Bus bit 16— Corresponds to system address bus bit 16.
ADDR[17]
0
ADDR[16]
4.20.4.5.3.1.2 Field2 bits in normal and loop1 modes
Table 382. Information bits PCH
Bit 3
Bit 2
Bit 1
Bit 0
CSD
CVA
PC17
PC16
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Table 383. PCH field descriptions
Bit
Description
Source Destination Indicator — In Normal and Loop1 mode, this bit indicates if the corresponding stored address is a source or
destination address. This bit has no meaning in Compressed Pure PC mode.
3
0
1
Source Address
Destination Address
CSD
Vector Indicator — In Normal and Loop1 mode, this bit indicates if the corresponding stored address is a vector address. Vector
addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in Compressed
Pure PC mode.
2
CVA
0
1
Non-Vector destination address
Vector destination address
1
Program Counter bit 17— In Normal and Loop1 mode, this bit corresponds to program counter bit 17.
Program Counter bit 16— In Normal and Loop1 mode, this bit corresponds to program counter bit 16.
PC17
0
PC16
4.20.4.5.4
Trace buffer organization (compressed pure PC mode)
Table 384. Trace buffer organization example (compressed pure PC mode)
2-bits
Field 3
00
6-bits
6-bits
6-bits
Line
Number
Mode
Field 2
Field 1
Field 0
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
PC1 (Initial 18-bit PC Base Address)
11
PC4
0
PC3
PC2
PC5
01
0
Compressed Pure
PC Mode
00
PC6 (New 18-bit PC Base Address)
PC8
10
0
PC7
00
PC9 (New 18-bit PC Base Address)
4.20.4.5.4.0.1 Field3 bits in compressed pure PC modes
Table 385. Compressed pure PC mode field 3 information bit encoding
INF1
INF0
TRACE BUFFER ROW CONTENT
0
0
1
1
0
1
0
1
Base PC address TB[17:0] contains a full PC[17:0] value
Trace Buffer[5:0] contain incremental PC relative to base address zero value
Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value
Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value
Each time PC[17:6] differs form the previous base PC[17:6], a new base address is stored. The base address zero value is the lowest
address in the 64 address range.
The first line of the trace buffer always gets a base PC address; this applies also on rollover.
4.20.4.5.5
Reading data from trace buffer
The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for tracing (TSOURCE bit is set),
and the system not secured. When the ARM bit is written to 1 the trace buffer, it is locked to prevent reading. The trace buffer can only be
unlocked for reading by a single aligned word write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads. Any byte or misaligned reads return 0 and does
not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By
reading CNT in DBGCNT, the number of valid lines can be determined. DBGCNT does not decrement as data is read.
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While reading, an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data
entry. If no overflow has occurred, the pointer points to line 0, otherwise it points to the line with the oldest entry. In compressed Pure PC
mode on rollover, the line with the oldest data entry may also contain newer data entries in fields 0 and 1. If rollover is indicated by the
TBF bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are clear, the line contains only entries
from before the last rollover.
If INF0=1, field 0 contains post rollover data but fields 1 and 2 contain pre rollover data.
If INF1=1, fields 0 and 1 contain post rollover data but field 2 contains pre rollover data.
The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read
sequence to be easily restarted from the oldest data entry.
The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 379. The next word read returns field 2
in the least significant bits [3:0] and “0” for bits [15:4].
Reading the Trace Buffer while the DBG module is armed, returns invalid data and no shifting of the RAM pointer occurs.
4.20.4.5.6
Trace buffer reset state
The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Should a system reset occur, immediately before the
reset occurred, the trace session information can be read out and the number of valid lines in the trace buffer is indicated by DBGCNT.
The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data, even
if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set, otherwise the trace buffer
reads as all zeroes. Generally, debugging occurrences of system resets are best handled using end trigger alignment, since the reset may
occur before the trace trigger, which in the begin trigger alignment case, means no information would be stored in the trace buffer.
The Trace Buffer contents and DBGCNT bits are undefined following a POR.
NOTE
An external pin RESET that occurs simultaneous to a trace buffer entry can, in very few cases, lead
to either that entry being corrupted, or the first entry of the session being corrupted. In such cases,
the other contents of the trace buffer still contain valid tracing information. The case occurs when the
reset assertion coincides with the trace buffer entry clock edge.
4.20.4.6
Tagging
Atag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue,
a tag hit occurs and can initiate a state sequencer transition.
Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition
immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the
comparator match address registers must be an opcode address.
Using Begin Trigger together with tagging, if the tagged instruction is about to be executed, the transition to the next state sequencer state
occurs. If the transition is to the Final state, tracing is started. Only upon completion of the tracing session can a breakpoint be generated.
Using End alignment, when the tagged instruction is about to be executed and the next transition is to Final state, a breakpoint is generated
immediately, before the tagged instruction is carried out.
R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected, since the tag is attached to the
opcode at the matched address and is not dependent on the data bus nor on ta type of access. These bits are ignored if tagging is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM
becomes active.
4.20.4.7 Breakpoints
It is possible to generate breakpoints from channel transitions to final state or use software to write to the TRIG bit in the DBGC1 register.
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4.20.4.7.1
Breakpoints from comparator channels
Breakpoints can be generated when the state sequencer transitions to the Final state. If configured for tagging, the breakpoint is generated
when the tagged opcode reaches the execution stage of the instruction queue.
If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed. If Begin aligned
triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 386). If no tracing session is
selected, breakpoints are requested immediately. If the BRK bit is set, the associated breakpoint is generated immediately independent
of tracing trigger alignment.
Table 386. Breakpoint setup for CPU breakpoints
BRK
TALIGN
DBGBRK
Breakpoint Alignment
0
0
0
0
0
1
0
1
0
Fill Trace Buffer until trigger then disarm (no breakpoints)
Fill Trace Buffer until trigger, then breakpoint request occurs
Start Trace Buffer at trigger (no breakpoints)
Start Trace Buffer at trigger
A breakpoint request occurs when Trace Buffer is full
0
1
1
1
1
x
x
1
0
Terminate tracing and generate breakpoint immediately on trigger
Terminate tracing immediately on trigger
4.20.4.7.2
Breakpoints generated via the TRIG bit
If a TRIG triggers occur, the Final state is entered, where the tracing trigger alignment is defined by the TALIGN bit. If a tracing session is
selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed. If Begin aligned triggering is selected,
the breakpoint is requested only on completion of the subsequent trace (see Table 386). If no tracing session is selected, breakpoints are
requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and TRIG simultaneously.
4.20.4.7.3
Breakpoint priorities
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the associated tracing
session is complete, the breakpoint occurs. Similarly, if a TRIG is followed by a subsequent comparator channel match, it has no effect,
since tracing has already started. If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is
activated by the BGND and the breakpoint to SWI is suppressed.
4.20.4.7.3.1 DBG breakpoint priorities and BDM interfacing
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM
firmware. Comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging
into BDM is disabled. If BDM is not active, the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to
coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed.
Table 387. Breakpoint mapping summary
DBGBRK
BDM bit (DBGC1[4])
BDM enabled
BDM active
Breakpoint mapping
No Breakpoint
0
1
X
1
1
X
0
X
1
1
X
X
1
0
1
X
0
1
X
0
Breakpoint to SWI
No Breakpoint
Breakpoint to SWI
Breakpoint to BDM
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted
and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE, and returns if
ENABLE is not set. If not serviced by the monitor, the breakpoint is re-asserted when the BDM returns to normal CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address, an SWI in user code could coincide with a DBG breakpoint.
The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine, care must
be taken to avoid a repeated breakpoint at the same address.
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Should a tagged or forced breakpoint coincide with a BGND in user code, the instruction that follows the BGND instruction is the first
instruction executed when normal program execution resumes.
NOTE
When program control returns from a tagged breakpoint using an RTI or BDM GO command without
program counter modification, it returns to the instruction whose tag generated the breakpoint. To
avoid a repeated breakpoint at the same location, reconfigure the DBG module in the SWI routine, if
configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before
the GO, to increment the program flow past the tagged instruction.
4.20.5 Application information
4.20.5.1 State machine scenarios
Defining the state control registers as SCR1,SCR2, SCR3, and M0,M1,M2 as matches on channels 0, 1, 2 respectively. SCR encoding
supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For backwards
compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not changed.
4.20.5.2 Scenario 1
A trigger is generated if a given sequence of 3 code events is executed.
SCR2=0010
SCR3=0111
SCR1=0011
M0
M2
M1
Final State
State3
State2
State1
Figure 66. Scenario 1
Scenario 1 is possible with S12SDBGV1 SCR encoding.
4.20.5.3 Scenario 2
A trigger is generated if a given sequence of 2 code events is executed.
SCR2=0101
SCR1=0011
M2
M1
Final State
State2
State1
Figure 67. Scenario 2a
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (COMPA, COMPB
configured for range mode). M1 is disabled in range modes.
SCR2=0101
SCR1=0111
M2
M01
Final State
State2
State1
Figure 68. Scenario 2b
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range (COMPA, COMPB
configured for range mode).
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SCR2=0011
SCR1=0010
M0
M2
Final State
State2
State1
Figure 69. Scenario 2c
All 3 scenarios 2a, 2b, 2c are possible with the S12SDBGV1 SCR encoding.
4.20.5.4 Scenario 3
A trigger is generated immediately when one of up to 3 given events occurs.
SCR1=0000
M012
Final State
State1
Figure 70. Scenario 3
Scenario 3 is possible with S12SDBGV1 SCR encoding.
4.20.5.5 Scenario 4
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B, and event B must be followed
by event A. 2 consecutive occurrences of event A without an intermediate event B causes a trigger. Similarly 2 consecutive occurrences
of event B without an intermediate event A causes a trigger. This is possible by using CompA and CompC to match on the same address
as shown.
M0
SCR2=0011
SCR1=0100
State2
M0
State1
M2
M1
M1
Final State
State 3
SCR3=0001
M1
Figure 71. Scenario 4a
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3 allows a M0
to return to state 2, while a M2 leads to Final state, as shown in Figure 72.
M0
SCR2=1100
SCR1=0110
State2
M01
State1
M0
M2
M2
M1 disabled in
range mode
Final State
State 3
SCR3=1110
M2
Figure 72. Scenario 4b (with 2 comparators)
The advantage of using only 2 channels is that range comparisons can now be included (channel0).
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This however violates the S12SDBGV1 specification, which states that a match leading to final state always has priority, in case of a
simultaneous match, while priority is also given to the lowest channel number. For the S12SDBG, the corresponding CPU priority decoder
is removed to support this, such that on simultaneous taghits, taghits pointing to Final state have highest priority. If no taghit points to Final
state, then the lowest channel number has priority. With the above encoding from State3, the CPU and DBG would break on a
simultaneous M0/M2.
4.20.5.6 Scenario 5
Trigger if following event A, event C precedes event B. i.e... the expected execution flow is A->B->C.
SCR2=0110
SCR1=0011
M0
M1
M2
Final State
State2
State1
Figure 73. Scenario 5
Scenario 5 is possible with the S12SDBGV1 SCR encoding.
4.20.5.7 Scenario 6
Trigger if event A occurs twice in succession before any of 2 other events (BC) occur. This scenario is not possible using the S12SDBGV1
SCR encoding. S12SDBGV2 includes additions shown in red. The change in SCR1 encoding also has the advantage that a
State1->State3 transition using M0 is now possible. This is advantageous because range and data bus comparisons use channel 0 only.
SCR3=1010
SCR1=1001
M0
M0
M12
Final State
State3
State1
Figure 74. Scenario 6
4.20.5.8 Scenario 7
Trigger when a series of 3 events are executed out of order. Specifying the event order as M1, M2, M0 to run in loops (120120120). Any
deviation from that order should trigger. This scenario is not possible using the S12SDBGV1 SCR encoding, because OR possibilities are
very limited in the channel encoding. By adding OR forks as shown in red, this scenario is possible.
M01
SCR2=1100
SCR3=1101
SCR1=1101
M12
M2
M1
Final State
State3
State2
State1
M0
M02
Figure 75. Scenario 7
On simultaneous matches the lowest channel number has priority, so with this configuration the forking from State1 has the peculiar effect
that a simultaneous match0/match1 transitions to Final state, but a simultaneous match2/match1transitions to state2.
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4.20.5.9 Scenario 8
Trigger when a routine/event at M2 follows either M1 or M0.
SCR2=0101
SCR1=0111
M2
M01
Final State
State2
State1
Figure 76. Scenario 8a
Trigger when an event M2 is followed by either an event M0 or event M1
SCR2=0111
SCR1=0010
M01
M2
Final State
State2
State1
Figure 77. Scenario 8b
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding.
4.20.5.10 Scenario 9
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed again. This cannot be realized
with the S12SDBGV1 SCR encoding, due to OR limitations. By changing the SCR2 encoding as shown in red this scenario becomes
possible.
SCR2=1111
SCR1=0111
M01
M01
M2
Final State
State2
State1
Figure 78. Scenario 9
4.20.5.11 Scenario 10
Trigger if an event M0 occurs following up to two successive M2 events, without the resetting event M1. As shown, up to 2 consecutive
M2 events are allowed, whereby a reset to State1 is possible, after either one or two M2 events. If an event M0 occurs following the second
M2, before M1 resets to State1, a trigger is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint
on the third consecutive occurrence of event M0 without a reset on M1.
M1
SCR2=0100
SCR3=0010
SCR1=0010
M0
M2
M2
Final State
State3
State2
State1
M1
Figure 79. Scenario 10a
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M0
SCR2=0011
SCR3=0000
State3
SCR1=0010
M1
M2
Final State
State2
State1
M0
Figure 80. Scenario 10b
Scenario 10b shows the case that after M2, an M1 must occur before M0. Starting from a particular point in code, event M2 must always
be followed by M1 before M0. If after any M2 event, M0 occurs before M1, then a trigger is generated.
4.21 MCU - security (S12XS9S12I128PIMV1V2)
4.21.1 Introduction
This specification describes the function of the security mechanism in the S12I chip family (9S12I128PIMV1).
NOTE
No security feature is absolutely secure. However, NXP’s strategy is to make reading or copying the
FLASH and/or EEPROM difficult for unauthorized users.
4.21.1.1 Features
The user must be reminded that part of the security must lie with the application code. An extreme example would be application code
that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to
put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access
to a programming routine that updates parameters stored in another section of the Flash memory.
The security features of the S12I chip family (in secure mode) are:
•
•
•
Protect the content of non-volatile memories (Flash, EEPROM)
Execution of NVM commands is restricted
Disable access to internal memory via background debug module (BDM)
4.21.1.2 Modes of operation
Table 388 gives an overview over availability of security relevant features in unsecure and secure modes.
Table 388. Feature availability in unsecure and secure modes on S12XS
Unsecure mode
NX ES
Secure mode
NX ES
NS
SS
EX
ST
NS
SS
EX
ST
Flash Array Access
EEPROM Array Access
NVM Commands
BDM
4
4
4
4
4
4
(259)
(259)
(259)
4
4
4
4
4
(260)
4
4
4
—
—
DBG Module Trace
4
—
Notes
259. Restricted NVM command set only. Refer to the NVM wrapper block guides for detailed information.
260. BDM hardware commands restricted to peripheral registers only.
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4.21.1.3 Securing the microcontroller
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the
options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down.
The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased
and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory
page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The
contents of this byte are copied into the Flash security register (FSEC) during a reset sequence.
Table 389. Flash options/security byte
7
6
5
4
3
2
1
0
0xFF0F
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
The meaning of the bits KEYEN[1:0] is shown in Table 390. Refer to Section 4.21.1.5.1, “Unsecuring the MCU using the backdoor key
access" for more information.
Table 390. Backdoor key access enable bits
KEYEN[1:0]
Backdoor key access enabled
0 (disabled)
00
01
10
11
0 (disabled)
1 (enabled)
0 (disabled)
The meaning of the security bits SEC[1:0] is shown in Table 391. For security reasons, the state of device security is controlled by two
bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a
secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
Table 391. Security bits
SEC[1:0]
Security state
1 (secured)
00
01
10
11
1 (secured)
0 (unsecured)
1 (secured)
NOTE
Refer to the Flash block guide for actual security configuration (in section “Flash Module Security”).
4.21.1.4 Operation of the secured microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be
understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For
example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application
containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents, even when
the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a
challenge/response authentication before any code can be downloaded.
Secured operation has the following effects on the microcontroller:
4.21.1.4.1
Normal single chip mode (NS)
•
•
•
Background debug module (BDM) operation is completely disabled.
Execution of Flash and EEPROM commands is restricted. Refer to the NVM block guide for details.
Tracing code execution using the DBG module is disabled.
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4.21.1.4.2
Special single chip mode (SS)
•
•
•
•
BDM firmware commands are disabled.
BDM hardware commands are restricted to the register space.
Execution of Flash and EEPROM commands is restricted. Refer to the NVM block guide for details.
Tracing code execution using the DBG module is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of
the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check
succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed.
If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space
is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving
access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank
check to succeed and the options/security byte can be programmed to “unsecured” state via BDM.
While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are
temporarily blocked.
4.21.1.5 Unsecuring the microcontroller
Unsecuring the microcontroller can be done by three different methods:
1. Backdoor key access
2. Reprogramming the security bits
3. Complete memory erase (special modes)
4.21.1.5.1
Unsecuring the MCU using the backdoor key access
In Normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method
requires that:
•
•
•
The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value.
The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.
In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to
write to the backdoor key locations.
The backdoor key values themselves would not normally be stored within the application data, which means the application program would
have to be designed to receive the backdoor key values from an external source (e.g. through a serial port).
The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly
useful for failure analysis.
NOTE
No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF.
4.21.1.6 Reprogramming the security bits
In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash
options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–
0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode.
The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash
options/security byte is not protected (see Flash protection). Flash protection is a useful means of preventing this method. The
microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value.
This method requires that:
•
The application software previously programmed into the microcontroller has been designed to have the capability to erase and
program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to
issue commands to erase and program the Flash options/security byte.
•
The Flash sector containing the Flash options/security byte is not protected.
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4.21.1.7 Complete memory erase (special modes)
The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents.
When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash
memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware
commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks.
When next resetting into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased.
This being the case, it will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value.
The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset.
4.22 Background debug module (9S12I128PIMV1)
4.22.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system, implemented in on-chip hardware for
minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock
rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete.
The system is backwards compatible to the BDM of the S12 family with the following exceptions:
•
•
•
•
TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modified
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
•
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
4.22.1.1 Features
The BDM includes these distinctive features:
•
•
•
•
•
•
•
•
•
•
•
Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
(267)
GO_UNTIL
command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Software control of BDM operation during Wait mode
When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash erase
tests fail
•
•
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
BDM hardware commands are operational until system Stop mode is entered
4.22.1.2 Modes of operation
BDM is available in all operating modes, but must be enabled before firmware commands are executed. Some systems may have a control
bit that allows suspending the function during background debug mode.
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4.22.1.2.1
Regular run modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during
run mode.
•
•
Normal modes - General operation of the BDM is available and operates the same in all normal modes
Special single chip mode - In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory
4.22.1.2.2
Secure mode operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation
prevents access to Flash other than allowing erasure. For more information, see Section 4.22.4.1, “Security".
4.22.1.2.3
Low-power modes
The BDM can be used until Stop mode is entered. When CPU is in Wait mode, all BDM firmware commands as well as the hardware
BACKGROUND command cannot be used and are ignored. In this case, the CPU can not enter BDM active mode, and only hardware
read and write commands are available. Also, the CPU can not enter a Low Power mode (stop or wait) during BDM active mode.
In Stop mode, the BDM clocks are stopped. When BDM clocks are disabled and Stop mode is exited, the BDM clocks will restart and BDM
will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready
to receive a new command.
4.22.1.3 Block diagram
A block diagram of the BDM is shown in Figure 81.
Host
System
Serial
Interface
Data
16-Bit Shift Register
BKGD
Control
Register Block
Address
Data
Bus Interface
and
Control Logic
TRACE
Instruction Code
and
Control
Clocks
BDMACT
Execution
ENBDM
SDV
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
UNSEC
BDMSTS
Register
Figure 81. BDM block diagram
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4.22.2 External signal description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset,
this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated
serial interface pin for the background debug mode. The communication rate of this pin is based on the settings for the VCO clock
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset, the BDM clock is based on the reset
values of the CPMUSYNR register (4.0 MHz). When modifying the VCO clock, make sure that the communication rate is adapted
accordingly, and a communication timeout (BDM soft reset) has occurred.
4.22.3 Memory map and register definition
4.22.3.1 Module memory map
Table 49 shows the BDM memory map when BDM is active.
Table 392. BDM memory map
Global Address
0x3_FF00–0x3_FF0B
0x3_FF0C–0x3_FF0E
0x3_FF0F
Module
BDM registers
Size (bytes)
12
3
BDM firmware ROM
Family ID (part of BDM firmware ROM)
BDM firmware ROM
1
0x3_FF10–0x3_FFFF
240
4.22.3.2 Register descriptions
A summary of the registers associated with the BDM is shown in Table 393. Registers are accessed by host-driven communications to
the BDM hardware using READ_BD and WRITE_BD commands.
Table 393. BDM register summary
Register
name
Global
address
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
X
X
X
X
X
X
0
0
0x3_FF00
0x3_FF01
0x3_FF02
0x3_FF03
0x3_FF04
0x3_FF05
0x3_FF06
Reserved
BDMSTS
Reserved
Reserved
Reserved
Reserved
BDMCCR
BDMACT
0
X
X
X
X
SDV
Z
TRACE
0
X
X
X
X
UNSEC
0
X
X
X
X
ENBDM
X
W
R
Z
X
X
X
X
X
X
X
X
X
X
W
R
X
X
X
X
X
X
X
X
X
W
R
W
R
W
R
CCR7
X
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
W
= Unimplemented, Reserved
= Indeterminate
Z
0
= Implemented (do not alter)
= Always read zero
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Table 393. BDM register summary (continued)
Register
name
Global
address
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
0
0
0
0
0
0
0
0
0x3_FF07
0x3_FF08
0x3_FF09
0x3_FF0A
0x3_FF0B
Reserved
BDMPPR
0
0
0
0
0
0
0
0
0
0
0
0
BPAE
0
BPP3
0
BPP2
0
BPP1
0
BPP0
0
W
R
Reserved
Reserved
Reserved
W
R
0
0
0
0
0
0
0
0
0
0
W
R
W
= Unimplemented, Reserved
= Indeterminate
Z
0
= Implemented (do not alter)
= Always read zero
X
4.22.3.2.1
BDM status register (BDMSTS)
Table 394. BDM status register (BDMSTS)
Register Global Address
7
6
5
0
4
3
2
0
1
0
0
0x3_FF01
R
BDMACT
SDV
TRACE
UNSEC
ENBDM
W
Reset
(261)
(262)
Special Single-Chip Mode
All Other Modes
0
1
0
0
0
0
0
0
0
Z
0
0
0
0
0
0
0
0
= Unimplemented, Reserved
= Always read zero
= Implemented (do not alter)
Notes
261. ENBDM is read as a 1 by a debugging environment in special single chip mode, when the device is either secured or not secured, but fully erased
(Flash). This is because the ENBDM bit is set by the standard BDM firmware before a BDM command can be fully transmitted and executed.
262. UNSEC is read as a 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can
only be read if not secure (see also bit description).
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
—
—
—
ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply
in special single chip mode)
BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware
lookup table upon exit from BDM active mode
All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the
BDM hardware or the standard firmware lookup table, as part of BDM command execution
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Table 395. BDMSTS field descriptions
Field
Description
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware
commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed.
7
0
1
BDM disabled
BDM enabled
ENBDM
Note: ENBDM is set out of reset in special single chip mode. In special single chip mode with the device secured, this bit will not be
set until after the Flash erase verify tests are complete.
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into
the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware, as part of the exit sequence
to return to user code and remove the BDM memory from the map.
6
BDMACT
0
1
BDM not active
BDM active
Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a BDM firmware
or hardware read command, or after data has been received as part of a BDM firmware or hardware write command. It is cleared when
the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow
execution.
4
SDV
0
1
Data phase of command not complete
Data phase of command is complete
TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware command is first
(267)
3
recognized. It will stay set until BDM firmware is exited by one of the following BDM commands: GO or GO_UNTIL
.
0
1
TRACE1 command is not being executed
TRACE1 command is being executed
TRACE
Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure firmware. It is in a zero
state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map, overlapping
the standard BDM firmware lookup table.
The secure BDM firmware lookup table verifies that the on-chip Flash is erased. This being the case, the UNSEC bit is set and the BDM
program jumps to the start of the standard BDM firmware lookup table, and the secure BDM firmware lookup table is turned off. If the
erase test fails, the UNSEC bit will not be asserted.
1
0
1
System is in a secured mode.
System is in a unsecured mode.
UNSEC
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. Note that
if the user does not change the state of the bits to “unsecured” mode, the system will be secured again when it is next taken out
of reset. After reset, this bit has no meaning or effect when the security byte in the Flash EEPROM is configured for unsecure
mode.
Table 396. BDM CCR holding register (BDMCCR)
Register Global Address
7
6
5
4
3
2
1
0
0x3_FF06
R
W
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
Reset
Special Single-Chip Mode
All Other Modes
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCR register in the BDMCCR register.
However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset
value of the CCR register in this CPU mode. Out of reset in all other modes the BDMCCR register is
read zero.
When entering background debug mode, the BDM CCR holding register is used to save the condition code register of the user’s program.
It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the
CCR value.
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4.22.3.2.2
BDM program page index register (BDMPPR)
Table 397. BDM program page register (BDMPPR)
Register Global
Address 0x3_FF08
7
6
0
5
0
4
0
3
2
1
0
R
BPAE
0
BPP3
0
BPP2
0
BPP1
0
BPP0
0
W
Reset
0
0
0
= Unimplemented, Reserved
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Table 398. BDMPPR field descriptions
Field
Description
BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and firmware read/write
instructions The BDM hardware commands used to access the BDM registers (READ_BD and WRITE_BD) can not be used for global
accesses even if the BGAE bit is set.
7
BPAE
0
1
BDM Program Paging disabled
BDM Program Paging enabled
3–0
BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed information regarding the
program page window scheme, refer to the S12S_MMC Block Guide.
BPP[3:0]
4.22.3.3 Family ID assignment
The family ID is an 8-bit value located in the BDM ROM in active BDM (at global address: 0x3_FF0F). The read-only value is a unique
family ID which is 0xC2 for devices with an HCS12S core.
4.22.4 Functional description
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands:
hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. See
Section 4.22.4.3, “BDM hardware commands". Target system memory includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug mode. See Section 4.22.4.4,
“Standard BDM firmware commands". The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y),
stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode, excluding a few exceptions as highlighted (see Section 4.22.4.3,
“BDM hardware commands") and in secure mode (see Section 4.22.4.1, “Security"). BDM firmware commands can only be executed
when the system is not secure and is in active background debug mode (BDM).
4.22.4.1 Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the
map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip Flash EEPROM
is erased. This being the case, the UNSEC and ENBDM bits will get set. The BDM program jumps to the start of the standard BDM
firmware, the secured mode BDM firmware is turned off, and all BDM commands are allowed. If the Flash does not verify as erased, the
BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands
to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the Flash.
BDM operation is not possible in any other mode than special single chip mode when the device is secured. The device can only be
unsecured via the BDM serial interface in special single chip mode. For more information regarding security, see the S12S_9SEC Block
Guide.
4.22.4.2 Enabling and activating BDM
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The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM
is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS)
register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE.
After being enabled, BDM is activated by one of the following (263)
:
•
•
•
Hardware BACKGROUND command
CPU BGND instruction
Breakpoint force or tag mechanism(264)
Notes
263. BDM is enabled and active immediately out of special single-chip reset.
264. This method is provided by the S12S_DBG module.
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM
firmware lookup table. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or
after execution of the next instruction.
NOTE
If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction
execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued
are ignored by the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0x3_FF00 to 0x3_FFFF. BDM
registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses these registers which are readable anytime by the BDM.
However, these registers are not readable by user programs.
When BDM is activated, while CPU executes code overlapping with the BDM firmware space, the saved program counter (PC) will be
auto incremented by one from the BDM firmware, regardless of what caused the entry into BDM active mode (BGND instruction,
BACKGROUND command or breakpoints). In such cases, the PC must be set to the next valid address via a WRITE_PC command,
before executing the GO command.
4.22.4.3 BDM hardware commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target
system memory includes all memory that is accessible by the CPU such as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention, and do not require the system to be in active BDM for execution,
although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free bus cycle,
so the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU
is momentarily frozen so the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU
operation, provided it can be completed in a single cycle. However, if an operation requires multiple cycles, the CPU is frozen until the
operation is complete, even though the BDM found a free cycle.
The BDM hardware commands are listed in Table 399. The READ_BD and WRITE_BD commands allow access to the BDM register
locations. These locations are not normally in the system memory map, but share addresses with the application in memory. To distinguish
between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and
WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application
memory map.
Table 399. Hardware commands
Command
Opcode (hex)
Data
Description
Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the part
enters active background mode.
BACKGROUND
90
None
ACK_ENABLE
D5
D6
None
None
Enable Handshake. Issues an ACK pulse after the command is executed.
Disable Handshake. This command does not issue an ACK pulse.
ACK_DISABLE
READ_BD_BYTE
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
E4
EC
E0
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
READ_BD_WORD
READ_BYTE
Must be aligned access.
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
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Table 399. Hardware commands (continued)
Command
Opcode (hex)
Data
Description
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map. Must be aligned
access.
READ_WORD
E8
WRITE_BD_BYTE
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
C4
CC
C0
C8
Odd address data on low byte; even address data on high byte.
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
WRITE_BD_WORD
WRITE_BYTE
Must be aligned access.
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Must be aligned access.
WRITE_WORD
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands, and will occur after the write is complete for
all BDM WRITE commands.
4.22.4.4 Standard BDM firmware commands
BDM firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard
BDM firmware commands. See Section 4.22.4.2, “Enabling and activating BDM". Normal instruction execution is suspended while the
CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual
way to activate BDM.
As the system enters active BDM, the standard BDM firmware lookup table, BDM registers become visible in the on-chip memory map at
0x3_FF00–0x3_FFFF, and the CPU begins executing the standard BDM firmware. The standard BDM firmware watches for serial
commands and executes them as they are received.
The firmware commands are shown in Table 400.
Table 400. Firmware commands
(265)
Command
Opcode (hex)
Data
Description
(266)
READ_NEXT
62
63
64
65
66
67
42
43
44
45
46
47
08
0C
16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.
16-bit data out Read program counter.
READ_PC
READ_D
16-bit data out Read D accumulator.
READ_X
16-bit data out Read X index register.
READ_Y
16-bit data out Read Y index register.
READ_SP
WRITE_NEXT
WRITE_PC
WRITE_D
WRITE_X
WRITE_Y
WRITE_SP
GO
16-bit data out Read stack pointer.
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
none
Increment X index register by 2 (X = X + 2), then write word to location pointed to by X.
Write program counter.
Write D accumulator.
Write X index register.
Write Y index register.
Write stack pointer.
Go to user program. If enabled, ACK will occur when leaving active background mode.
Go to user program. If enabled, ACK will occur upon returning to active background mode.
(267)
GO_UNTIL
none
Execute one user instruction then return to active BDM. If enabled, ACK will occur upon
returning to active background mode.
TRACE1
10
none
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Table 400. Firmware commands (continued)
(265)
Command
Opcode (hex)
Data
Description
(Previous enable tagging and go to user program.) This command will be deprecated and
should not be used anymore. Opcode will be executed as a GO command.
TAGGO -> GO
18
none
Notes
265. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands, and will occur after the write is complete for all BDM
WRITE commands.
266. When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space, the BDM resources are accessed, rather
than user code. Writing BDM firmware is not possible.
267. System stop disables the ACK function and ignored commands will have no ACK-pulse (e.g., CPU in stop or wait mode). The GO_UNTIL command
will not get an Acknowledge, if the CPU executes the wait or stop instruction before the “UNTIL” condition (BDM active again) is reached (see
Section 4.22.4.7, “Serial interface hardware handshake protocol" last note).
4.22.4.5 BDM command structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word, depending on
the command. All the read commands return 16 bits of data despite the byte or word implication in the command name.
8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even
address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear
in the LSB.
16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware
command, the BDM ignores the least significant bit of the address and assumes an even address
from the remaining bits.
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting
to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write
commands, the external host must wait 150 bus clock cycles after sending the data to be written, before attempting to send a new
command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay, in both
cases, includes the maximum 128 cycle delay that can be incurred, as the BDM waits for a free cycle before stealing a cycle.
The external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read
data for BDM firmware read commands. The 48 cycle wait allows enough time for the requested data to be made available in the BDM
shift register, ready to be shifted out.
The external host must wait 36 bus clock cycles after sending the data to be written, before attempting to send a new command for BDM
firmware write commands. This is to avoid disturbing the BDM shift register before the write has been completed.
The external host should wait for at least for 76 bus clock cycles, after a TRACE1 or GO command and before starting any new serial
command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code.
Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing, it is recommended that the
ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK,
the delay times are automated.
Figure 82 represents the BDM command structure. The command blocks illustrate a series of eight bit times, starting with a falling edge.
The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 16 target
clock cycles.(268)
Notes
268. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 4.22.4.6, “BDM serial interface" and Section 4.22.3.2.1,
“BDM status register (BDMSTS)" for information on how serial clock rate is selected.
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8-Bits
AT ~16 TC/Bit
16-Bits
AT ~16 TC/Bit
150-BC
Delay
16 Bits
AT ~16 TC/Bit
Hardware
Read
Next
Command
Command
Address
Data
150-BC
Delay
Hardware
Write
Next
Command
Command
Address
Data
48-BC
DELAY
Firmware
Read
Next
Command
Command
Command
Data
Command
36-BC
DELAY
Firmware
Write
Next
Command
Data
76-BC
Delay
GO,
TRACE
Next
Command
BC = Bus Clock Cycles
TC = Target Clock Cycles
Figure 82. BDM command structure
4.22.4.6 BDM serial interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects
between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM.
The BDM serial interface is timed, based on the VCO clock (refer to the CPMU Block Guide for more details), which gets divided by 8.
This clock will be referred to as the target clock in the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start
of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred, most significant bit (MSB)
first, at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is
an external pull-up and drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long,
the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the
host for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 83, and that of target-to-host in Figure 84 and Figure 85. All four cases begin when the
host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the
target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time, while
the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization
between the host and target is established in this manner at the start of every bit time.
Figure 83 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is
asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes
this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch
detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
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BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time
Target Senses Bit
Earliest
Start of
Next Bit
10 Cycles
Synchronization
Uncertainty
Figure 83. BDM host-to-target serial bit timing
The receive cases are more complicated. Figure 84 shows the host receiving a logic 1 from the target system. Since the host is
asynchronous to the target, there is up to one clock cycle delay from the host-generated falling edge on BKGD to the perceived start of
the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The
host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of
the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
BDM Clock
(Target MCU)
Host
Drive to
High-impedance
BKGD Pin
Target System
Speedup
Pulse
High-impedance
High-impedance
Perceived
Start of Bit Time
R-C Rise
BKGD Pin
10 Cycles
10 Cycles
Earliest
Start of
Next Bit
Host Samples
BKGD Pin
Figure 84. BDM target-to-host serial bit timing (logic 1)
Figure 85 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock cycle
delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time
but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then
briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
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BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
High-impedance
Speedup Pulse
Target System
Drive and
Speedup Pulse
Perceived
Start of Bit Time
BKGD Pin
10 Cycles
10 Cycles
Earliest
Start of
Next Bit
Host Samples
BKGD Pin
Figure 85. BDM target-to-host serial bit timing (logic 0)
4.22.4.7 Serial interface hardware handshake protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modified
when changing the settings for the VCO frequency (CPMUSYNR), it is very helpful to provide a handshake protocol in which the host
could determine when an issued command is executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8.
The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could
be running. This sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This
protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated
by the target MCU when a command, issued by the host, has been successfully executed (see Figure 86). This pulse is referred to as the
ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start
(267)
a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL
or TRACE1).
The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is
assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also
that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon
the CPU bus, which in some cases could be very slow due to long accesses taking place.This protocol allows a great flexibility for the
POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM Clock
(Target MCU)
16 Cycles
Target
Transmits
ACK Pulse
High-Impedance
32 Cycles
High-Impedance
Speedup Pulse
Minimum Delay
From the BDM Command
BKGD Pin
Earliest
Start of
Next Bit
16th Tick of the
Last Command Bit
Figure 86. Target acknowledge pulse (ACK)
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NOTE
If the ACK pulse was issued by the target, the host assumes the previous command was executed.
If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be
issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM
command is no longer pending.
Figure 87 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example.
First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes
the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data,
the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK
pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word, and the host needs to determine which is
the appropriate byte, based on whether the address was odd or even.
Target
Host
(2) Bytes are
Retrieved
New BDM
Command
BKGD Pin
READ_BYTE
Host
Byte Address
Target
Host
Target
BDM Issues the
ACK Pulse (out of scale)
BDM Executes the
READ_BYTE Command
BDM Decodes
the Command
Figure 87. Handshake protocol at command level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by
the target MCU by issuing a negative edge on the BKGD pin. The hardware handshake protocol in Figure 86 specifies the timing when
the BKGD pin is being driven, so the host should follow this timing constraint to avoid the risk of an electrical conflict on the BKGD pin.
NOTE
The only place the BKGD pin can have an electrical conflict is when one side is driving low and the
other side is issuing a speedup pulse (high). Other “highs” are pulled rather than driven. The time of
the speedup pulse can become lengthy at low rates, and so the potential conflict time becomes longer
as well.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host
needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters wait or stop while the
host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.
Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued. After a certain time the
host (not aware of stop or wait) should decide to abort any possible pending ACK pulse, to be sure a new command can be issued. The
protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted.
NOTE
(267)
The ACK pulse does not provide a timeout. This means for the GO_UNTIL
command, it cannot
be distinguished if a stop or wait has been executed (command discarded and ACK not issued), or if
the “UNTIL” condition (BDM active) is just not reached yet. Therefore, where the ACK pulse of a
command is not issued, the possible pending command should be aborted before issuing a new
command. See the handshake abort procedure described in Section 4.22.4.8, “Hardware handshake
abort procedure".
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4.22.4.8 Hardware handshake abort procedure
The abort procedure is based on the SYNC command. To abort a command which had not issued the corresponding ACK pulse, the host
controller should generate a low pulse on the BKGD pin by driving it low for at least 128 serial clock cycles, and then driving it high for one
serial clock cycle, providing a speedup pulse. By detecting this long low pulse on the BKGD pin, the target executes the SYNC protocol,
see Section 4.22.4.9, “SYNC — request timed reference pulse", and assumes that the pending command, and therefore the related ACK
pulse, are being aborted. Therefore, after the SYNC protocol has been completed, the host is free to issue new BDM commands. For
BDM firmware READ or WRITE commands, it can not be guaranteed that the pending command is aborted, when issuing a SYNC before
the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the
corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and on the
selected bus clock rate. When the SYNC command starts during this latency time, the READ or WRITE command will not be aborted, but
(267)
the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL
corresponding ACK pulse can be aborted by the SYNC command.
command can not be aborted. Only the
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse on the BKGD pin, shorter than 128
serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived
by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, to allow the negative
edge to be detected by the target. In this case, the target will not execute the SYNC protocol, but the pending command will be aborted
along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short
abort pulse, where the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,
READ_BYTE). If the abort pulse is not perceived by the target, the host will attempt to send a new command after the abort pulse was
issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism.
However, if the command to be aborted is not a read command, the short abort pulse could be used. After a command is aborted, the
target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference for the reader to better
understand the BDM internal behavior. It is not recommended that this procedure be used in a real
application.
Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the
lower possible target frequency. The host could issue a SYNC very close to the 128 serial clock cycles length, providing a small overhead
on the pulse length, to assure the SYNC pulse will not be misinterpreted by the target. See Section 4.22.4.9, “SYNC — request timed
reference pulse".
Figure 88 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the
command is aborted, a new command could be issued by the host computer.
READ_BYTE CMD is Aborted
by the SYNC Request
(Out of Scale)
SYNC Response
From the Target
(Out of Scale)
BKGD Pin READ_BYTE
Host
Memory Address
Target
READ_STATUS
New BDM Command
Host Target
Host
Target
BDM Decode
New BDM Command
and Starts to Execute
the READ_BYTE Command
Figure 88. ACK abort procedure at the command level
NOTE
Figure 88 does not represent the signals in a true timing scale.
Figure 89 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected
to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command
at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command.
In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the
protocol does not prevent this conflict from happening.
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At Least 128 Cycles
BDM Clock
(Target MCU)
ACK Pulse
Target MCU
Drives to
BKGD Pin
High-impedance
Electrical Conflict
Speedup Pulse
Host and
Host
Drives SYNC
To BKGD Pin
Target Drive
to BKGD Pin
Host SYNC Request Pulse
BKGD Pin
16 Cycles
Figure 89. ACK pulse and sync request conflict
NOTE
This information is being provided so that the MCU integrator will be aware that such a conflict could
occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides
backwards compatibility with the existing POD devices, which are not able to execute the hardware handshake protocol. It also allows for
new POD devices supporting the hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
•
ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is
executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response.
ACK_DISABLE — disables the ACK pulse protocol The host needs to use the worst case delay time at the appropriate places
in the protocol.
•
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the
BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin,
and when the data bus cycle is complete. See Section 4.22.4.3, “BDM hardware commands" and Section 4.22.4.4, “Standard BDM
firmware commands" for more information on the BDM commands.
The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if
the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the
target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not
issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command.
The BACKGROUND command issues an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related
to this command could be aborted using the SYNC command.
The GO command issues an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be
aborted using the SYNC command.
(267)
The GO_UNTIL
command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU
enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a
breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters
BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command
could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the
application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.
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4.22.4.9 SYNC — request timed reference pulse
The SYNC command is unlike other BDM commands, because the host does not necessarily know the correct communication speed to
use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should
perform the following steps:
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (The lowest serial
communication frequency is determined by the settings for the VCO clock (CPMUSYNR). The BDM clock frequency is always
VCO clock frequency divided by 8.)
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.)
3. Remove all drive to the BKGD pin so it reverts to high-impedance.
4. Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1. Discards any incomplete command received or bit retrieved.
2. Waits for BKGD to return to a logic one.
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6. Removes all drive to the BKGD pin so it reverts to high-impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed, and
the communication protocol can easily tolerate speed errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to
as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative
edge (issued by the host) as the start of a new BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC
command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization
problem. In this case, the command may not have been understood by the target, so an ACK response pulse will not be issued.
4.22.4.10 Instruction tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware, the BDM is active, and
ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates
stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed.
Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step, but peripherals are free running.
Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address pointing
to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is
traced:
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode. This is
the case because BDM active mode can not be entered after the CPU executed the stop instruction. However, all BDM hardware
commands except the BACKGROUND command are operational after tracing a stop or wait instruction, and still being in stop or
wait mode. If system stop mode is entered (all bus masters are in stop mode), no BDM command is operational.
As soon as stop or wait mode is exited, the CPU enters BDM active mode and the saved PC value points to the entry of the
corresponding interrupt service routine.
If the handshake feature is enabled, the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a
stop or wait instruction. Hence, there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command, after
CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from
stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode has been
reached. After a system stop mode, the handshake feature must be enabled again by sending the ACK_ENABLE command.
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4.22.4.11 Serial communication timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128
target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge
on BKGD, to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any timeout
limit.
Consider now the case where the host returns BKGD to a logic one before 128 cycles. This is interpreted as a valid bit transmission, and
not as a SYNC request. The target will keep waiting for another falling edge, marking the start of a new bit. If, a new falling edge is not
detected by the target within 512 clock cycles, since the last falling edge, a timeout occurs and the current command is discarded without
affecting memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued, but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to
be disregarded. The data is not available for retrieval after the timeout has occurred. This is expected behavior if the handshake protocol
is not enabled. To allow the data to be retrieved, even with a large clock frequency mismatch (between BDM and CPU) when the hardware
handshake protocol is enabled, the timeout between a read command and the data retrieval is disabled. Therefore, the host could wait
for more then 512 serial clock cycles, and still be able to retrieve the data from an issued read command. However, once the handshake
pulse (ACK pulse) is issued, the timeout feature is re-activated, meaning that the target will timeout after 512 clock cycles. The host needs
to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command
is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the timeout period is considered to
be a new command or a SYNC request.
Note that whenever a partially issued command, or partially retrieved data has occurred, the timeout in the serial communication is active.
This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command
being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to
be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new
BDM command, or the start of a SYNC request pulse.
4.23 S12 clock, reset, and power management unit (9S12I128PIMV1)
4.23.1 Introduction
This specification describes the function of the Clock, Reset, and Power Management Unit (9S12I128PIMV1).
•
•
The Pierce oscillator (OSCLCP) provides a robust, low noise and low power external clock source. It is designed for optimal
start-up margin with typical crystal oscillators
The voltage regulator (IVREG) operates from the range 3.13 to 5.5 V. It provides all the required chip internal voltages and
voltage monitors
•
•
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter
The Internal Reference Clock (IRC1M) provides a1.0 MHz clock
4.23.1.1 Features
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with
low harmonic distortion, low power, and good noise immunity.
•
•
•
•
•
•
•
Supports crystals or resonators from 4.0 to 16 MHz
High noise immunity due to input hysteresis and spike filtering
Low RF emissions with peak-to-peak swing limited dynamically
Transconductance (gm) sized for optimum start-up margin for typical crystals
Dynamic gain control eliminates the need for external current limiting resistor
Integrated resistor eliminates the need for external bias resistor
Low power consumption: Operates from an internal 1.8 V (nominal) supply, amplitude control limits power
The Voltage Regulator (IVREG) has the following features:
•
•
•
•
Input voltage range from 3.13 to 5.5 V
Low voltage detect (LVD) with low voltage interrupt (LVI)
Power-on reset (POR)
Low voltage reset (LVR)
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The Phase Locked Loop (PLL) has the following features:
•
•
•
•
•
•
•
Highly accurate and phase locked frequency multiplier
Configurable internal filter for best stability and lock time
Frequency modulation for defined jitter and reduced emission
Automatic frequency lock detector
Interrupt request on entry or exit from locked condition
Reference clock either external (crystal) or internal square wave (1.0 MHz IRC1M) based
PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock
The Internal Reference Clock (IRC1M) has the following features:
•
•
Trimmable in frequency
Factory trimmed value for 1.0 MHz in Flash memory, can be overwritten by application if required
Other features of the 9S12I128PIMV1 include
•
•
Clock monitor to detect loss of crystal
Bus Clock Generator
—
—
Clock switch to select either PLLCLK or external crystal/resonator based bus clock
PLLCLK divider to adjust system speed
•
System Reset generation from the following possible sources:
—
—
—
—
—
—
Power-on reset (POR)
Low voltage reset (LVR)
Illegal address access
COP timeout
Loss of oscillation (clock monitor fail)
External pin RESET
4.23.1.2 Modes of operation
This subsection lists and briefly describes all operating modes supported by the 9S12I128PIMV1.
4.23.1.2.1
Run mode
The voltage regulator is in Full Performance mode (FPM).
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
•
•
•
PLL Engaged Internal (PEI)
—
—
—
This is the default mode after system reset and power-on reset.
The bus clock is based on the PLLCLK.
After reset the PLL is configured for 64 MHz VCOCLK operation. Post divider is 0x03, so PLLCLK is VCOCLK divided by 4,
that is 16 MHz and bus clock is 8.0 MHz. The PLL can be re-configured for other bus frequencies.
The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
—
PLL Engaged External (PEE)
—
—
The bus clock is based on the PLLCLK.
This mode can be entered from default mode PEI by performing the following steps:
–
–
–
Configure the PLL for desired bus frequency.
Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary.
Enable the external oscillator (OSCE bit)
PLL Bypassed External (PBE)
—
—
The bus clock is based on the oscillator clock (OSCCLK).
This mode can be entered from default mode PEI by performing the following steps:
–
–
–
Enable the external oscillator (OSCE bit)
Wait for oscillator to start up (UPOSC=1)
Select the oscillator clock (OSCCLK) as bus clock (PLLSEL=0).
—
The PLLCLK is still on to filter possible spikes of the external oscillator clock.
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4.23.1.2.2
Wait mode
For 9S12I128PIMV1 Wait mode is the same as Run mode.
4.23.1.2.3
Stop mode
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Power mode (RPM).
The Phase Locked Loop (PLL) is off.
The internal reference clock (IRC1M) is off.
Core clock, bus clock and BDM clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop mode can be differentiated between Full Stop mode (PSTP = 0 or OSCE=0)
and Pseudo Stop mode (PSTP = 1 and OSCE=1).
•
Full Stop mode (PSTP = 0 or OSCE=0)
The external oscillator (OSCLCP) is disabled.
After wake-up from Full Stop mode the core clock and bus clock are running on PLLCLK (PLLSEL=1). After wake-up from Full
Stop mode the COP and RTI are running on IRCCLK (COPOSCSEL=0, RTIOSCSEL=0).
Pseudo Stop Mode (PSTP = 1 and OSCE=1)
•
The external oscillator (OSCLCP) continues to run. If the respective enable bits are set the COP and RTI will continue to run.
The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged.
NOTE
When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full
Stop mode with OSCE bit already 1), the software must wait for a minimum time equivalent to the
startup-time of the external oscillator t
before entering Pseudo Stop mode.
UPOSC
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4.23.1.3 9S12I128PIMV1 block diagram
Illegal Address Access
MMC
VDDRX
VSS
VDD, VDDF
(core supplies)
Low Voltage Interrupt VDDRX
ILAF
Low Voltage Interrupt
LVDS
LVIE
Low Voltage Reset VDDRX
Voltage
Regulator
3.13 to 5.5V
LVRF
COP timeout
S12CPMU
VSSRX
Power-On Detect
PORF
Power-On Reset
System Reset
RESET
Reset
monitor fail
UPOSC
Generator
Clock
Monitor
Oscillator status Interrupt
OSCIE
UPOSC=0 sets PLLSEL bit
Loop
CAN_OSCCLK
Controlled
Pierce
EXTAL
XTAL
OSCCLK
adaptive
spike
filter
&
(to MSCAN)
Oscillator
(OSCLCP)
4.0 MHz-
OSCFILT[4:0]
OSCBW
PLLSEL
REFDIV[3:0]
IRCTRIM[9:0]
16 MH
POSTDIV[4:0]
ECLK2X
Internal
Reference
Clock
Reference
Divider
Post
(Core Clock)
Divider
1,2,...,32
PLLCLK
PSTP
divide
by 2
ECLK
(Bus Clock)
(IRC1M)
divide
by 4
IRCCLK
(to LCD)
OSCE
VCOFRQ[1:0]
divide
by 8
VCOCLK
BDM Clock
Phase
locked
REFCLK
Lock
detect
Loop with
internal
Filter (PLL)
FBCLK
REFFRQ[1:0]
PLL Lock Interrupt
RTI Interrupt
LOCK
LOCKIE
Divide by
2*(SYNDIV+1)
UPOSC
UPOSC=0 clears
SYNDIV[5:0]
RTIE
IRCCLK
IRCCLK
Real Time
COP timeout
to Reset
Generator
COP
COPCLK
RTICLK
Interrupt (RTI)
CPMURTI
PRE
Watchdog
OSCCLK
OSCCLK
RTIOSCSEL
COPOSCSEL
CPMUCOP
PCE
Figure 90. Block diagram of 9S12I128PIMV1
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Figure 91 shows a block diagram of the OSCLCP.
OSCCLK
Peak
Detector
Gain Control
VDD = 1.8 V
VSS
Rf
XTAL
EXTAL
Figure 91. OSCLCP block diagram
4.23.2 Signal description
This section lists and describes the signals that connect off chip.
4.23.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input, it initializes the MCU asynchronously to a known start-up state. As an open-drain
output, it indicates that an MCU-internal reset has been triggered.
4.23.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the external clock input or the input
to the crystal oscillator amplifier. XTALis the output of the crystal oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL
input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k, and the XTAL pin is pulled
down by an internal resistor of approximately 700 k.
NOTE
NXP recommends an evaluation of the application board and chosen resonator or crystal by the
resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals.
4.23.2.3 VSS — ground pin
VSS must be grounded.
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4.23.2.4 VDDRX, VSSRX— regulator power input pin and pad supply pins
VDDRX is the power input of IVREG and the PAD positive supply pin. All currents sourced into the regulator loads flow through this pin.The
VDDRX/VSSX supply domain is monitored by the low voltage reset circuit. An off-chip decoupling capacitor (100 nF...220 nF, X7R
ceramic) between VDDRX and VSSX can further improve the quality of this supply.
4.23.2.5 VDD — internal regulator output supply (core logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic. This supply domain
is monitored by the low voltage reset circuit.
4.23.2.6 VDDF — internal regulator output supply (NVM logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply
domain is monitored by the low voltage reset circuit
4.23.3 Memory map and registers
This section provides a detailed description of all registers accessible in the 9S12I128PIMV1.
4.23.3.1 Module memory map
The 9S12I128PIMV1 registers are shown in Table 401.
Table 401. CPMU register summary
Address
Name
Bit 7
6
5
4
0
3
2
1
Bit 0
R
W
R
CPMU
SYNR
0x0034
VCOFRQ[1:0]
SYNDIV[5:0]
0
0
CPMU
REFDIV
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
REFFRQ[1:0]
REFDIV[3:0]
W
R
0
0
CPMU
POSTDIV
POSTDIV[4:0]
W
R
LOCK
0
UPOSC
0
CPMUFLG
CPMUINT
RTIF
RTIE
PORF
0
LVRF
0
LOCKIF
ILAF
0
OSCIF
OSCIE
W
R
LOCKIE
0
W
R
0
RTI
OSCSEL
COP
OSCSEL
CPMUCLKS
CPMUPLL
CPMURTI
PLLSEL
0
PSTP
0
PRE
0
PCE
0
W
R
0
0
FM1
FM0
W
R
RTDEC
RTR6
RTR5
RTR4
0
RTR3
0
RTR2
RTR1
RTR0
W
R
0
CPMUCOP
RESERVEDC
WCOP
0
RSBCK
0
CR2
0
CR1
0
CR0
0
W
R
WRTMASK
0
0
0
W
= Unimplemented or Reserved
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Table 401. CPMU register summary (continued)
Address
Name
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
R
W
R
0x003E
RESERVEDC
0
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
CPMU
ARMCOP
0x003F
0x02F0
0x02F1
0x02F2
0x02F3
0x02F4
0x02F5
0x02F6
0x02F7
0x02F8
0x02F9
W
R
RESERVED
W
R
0
0
0
0
0
0
0
LVDS
CPMU
LVCTL
LVIE
LVIF
W
R
RESERVED
RESERVED
RESERVED
RESERVED
W
R
0
0
W
R
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESERVEDC
RESERVED
W
R
W
R
CPMU
IRCTRIMH
TCTRIM[4:0]
IRCTRIM[9:8]
W
R
CPMU
IRCTRIML
IRCTRIM[7:0]
W
OSCPINS_E
N
R
0x02FA
CPMUOSC
OSCE
0
OSCBW
0
OSCFILT[4:0]
0
W
R
0
0
0
0
0
0
0
0
0x02FB
0x02FC
CPMUPROT
RESERVEDC
PROT
0
W
R
0
0
0
W
= Unimplemented or Reserved
4.23.3.2 Register descriptions
This section describes all the 9S12I128PIMV1 registers and their individual bits. Address order is as listed in Table 401.
4.23.3.2.1
9S12I128PIMV1 synthesizer register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range.
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Table 402. 9S12I128PIMV1 synthesizer register (CPMUSYNR)
0x0034
7
0
6
1
5
0
4
1
3
1
2
1
1
1
0
1
R
W
VCOFRQ[1:0]
SYNDIV[5:0]
Reset
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
f
= 2 f
SYNDIV + 1
If PLL has locked (LOCK=1)
VCO
REF
NOTE
must be within the specified VCO frequency lock range. Bus frequency f
f
must not exceed
BUS
VCO
the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation, the VCOFRQ[1:0]
bits have to be selected according to the actual target VCOCLK frequency, as shown in Table 403. Setting the VCOFRQ[1:0] bits
incorrectly can result in a non functional PLL (no locking and/or insufficient stability).
Table 403. VCO clock frequency selection
VCOCLK Frequency Ranges
32 MHz <= f <= 48 MHz
VCOFRQ[1:0]
00
01
10
11
VCO
48 MHz < f
<= 64 MHz
VCO
Reserved
Reserved
4.23.3.2.2
9S12I128PIMV1 reference divider register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the external oscillator as reference.
Table 404. 9S12I128PIMV1 reference divider register (CPMUREFDIV)
0x0035
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
R
W
REFFRQ[1:0]
REFDIV[3:0]
Reset
0
0
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
f
OSC
------------------------------------
f
=
If OSCLCP is enabled (OSCE=1)
If OSCLCP is disabled (OSCE=0)
REF
REFDIV + 1
f
= f
REF
IRC1M
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The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For correct PLL operation, the
REFFRQ[1:0] bits have to be selected according to the actual REFCLK frequency as shown in Table 405.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1.0 MHz <= f
be written but will have no effect on the PLL filter configuration.
<= 2.0 MHz range. The bits can still
REF
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability).
Table 405. Reference clock frequency selection if OSC_LCP Is enabled
REFCLK Frequency Ranges (OSCE=1)
REFFRQ[1:0]
1.0 MHz <= f
<= 2.0 MHz
<= 6.0 MHz
00
01
10
11
REF
2.0 MHz < f
6.0 MHz < f
REF
<= 12.0 MHz
REF
f
>12.0 MHz
REF
4.23.3.2.3
9S12I128PIMV1 post divider register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Table 406. 9S12I128PIMV1 post divider register (CPMUPOSTDIV)
0x0036
7
0
6
0
5
0
4
0
3
0
2
1
1
0
1
R
W
POSTDIV[4:0]
0
Reset
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
f
VCO
----------------------------------------
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
f
=
=
PLL
POSTDIV + 1
f
VCO
--------------
f
PLL
4
f
PLL
------------
f
=
bus
2
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4.23.3.2.4
9S12I128PIMV1 flags register (CPMUFLG)
This register provides 9S12I128PIMV1 status bits and flags.
Table 407. 9S12I128PIMV1 flags register (CPMUFLG)
0x0037
7
RTIF
0
6
5
4
LOCKIF
0
3
2
1
OSCIF
0
0
R
W
LOCK
UPOSC
PORF
LVRF
ILAF
(269)
(270)
(271)
Reset
0
0
= Unimplemented or Reserved
Notes
269. 1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
270. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
271. 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 408. CPMUFLG field descriptions
Field
Description
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has
no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
7
0
1
RTI timeout has not yet occurred.
RTI timeout has occurred.
RTIF
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has
no effect.
6
0
1
Power on reset has not occurred.
Power on reset has occurred.
PORF
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0
has no effect.
5
0
1
Low voltage reset has not occurred.
Low voltage reset has occurred.
LVRF
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0
has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
4
0
1
No change in LOCK bit.
LOCK bit has changed.
LOCKIF
Lock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is unlocked (LOCK=0) f
PLL
is f
/ 4 to protect the system from high core clock frequencies during the PLL stabilization time t
.
3
VCO
lock
0
1
VCOCLK is not within the desired tolerance of the target frequency. f
= f
/4.
LOCK
PLL
= f
VCO
VCOCLK is within the desired tolerance of the target frequency. f
/(POSTDIV+1).
PLL
VCO
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for details. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
2
0
1
Illegal address reset has not occurred.
Illegal address reset has occurred.
ILAF
Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared by writing a 1. Writing a
0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
1
0
1
No change in UPOSC bit.
UPOSC bit has changed.
OSCIF
Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. While UPOSC=0 the OSCCLK going to the
MSCAN module is off. Entering Full Stop Mode UPOSC is cleared.
0
0
1
The oscillator is off or oscillation is not qualified by the PLL.
The oscillator is qualified by the PLL.
UPOSC
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NOTE
The adaptive oscillator filter uses the VCO clock as a reference to continuously qualify the external
oscillator clock. As a result, the PLL is always active and a valid PLL configuration is required for the
system to work properly. Furthermore, the adaptive oscillator filter is used to determine the status of
the external oscillator (reflected in the UPOSC bit). Since this function also relies on the VCO clock,
loosing PLL lock status (LOCK=0, except for entering Pseudo Stop mode) means loosing the
oscillator status information as well (UPOSC=0).
4.23.3.2.5
9S12I128PIMV1 interrupt enable register (CPMUINT)
This register enables 9S12I128PIMV1 interrupt requests.
Table 409. 9S12I128PIMV1 interrupt enable register (CPMUINT)
0x0038
7
RTIE
0
6
0
5
0
4
LOCKIE
0
3
0
2
0
1
OSCIE
0
0
0
R
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime
Table 410. CRGINT field descriptions
Field
Description
Real Time Interrupt Enable Bit
7
0
1
Interrupt requests from RTI are disabled.
Interrupt will be requested whenever RTIF is set.
RTIE
PLL Lock Interrupt Enable Bit
4
0
1
PLL LOCK interrupt requests are disabled.
Interrupt will be requested whenever LOCKIF is set.
LOCKIE
Oscillator Corrupt Interrupt Enable Bit
1
0
1
Oscillator Corrupt interrupt requests are disabled.
Interrupt will be requested whenever OSCIF is set.
OSCIE
4.23.3.2.6
9S12I128PIMV1 clock select register (CPMUCLKS)
This register controls 9S12I128PIMV1 clock selection.
Table 411. 9S12I128PIMV1 clock select register (CPMUCLKS)
0x0039
7
PLLSEL
1
6
PSTP
0
5
0
4
0
3
PRE
0
2
PCE
0
1
0
R
W
RTI
OSCSEL
COP
OSCSEL
Reset
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write:
1. Only possible if PROT=0 (CPMUPROT register) in all MCU modes (Normal and Special mode).
2. All bits in Special mode (if PROT=0).
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal mode (if PROT=0).
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4. COPOSCSEL: In Normal mode (if PROT=0) until CPMUCOP write once is taken. If COPOSCSEL was cleared by UPOSC=0
(entering Full Stop mode with COPOSCSEL=1 or insufficient OSCCLK quality), then COPOSCSEL can be set again once.
NOTE
After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS register to
make sure that write of PLLSEL, RTIOSCSEL and COPOSCSEL was successful.
Table 412. CPMUCLKS descriptions
Field
Description
PLL Select Bit
This bit selects the PLLCLK as source of the system clocks (core clock and bus clock).
PLLSEL can only be set to 0, if UPOSC=1.
UPOSC= 0 sets the PLLSEL bit.
7
PLLSEL
Entering Full Stop mode sets the PLLSEL bit.
0
1
System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, f
= f
/ 2.
OSC
BUS
System clocks are derived from PLLCLK, f
= f
/ 2.
PLL
BUS
Pseudo Stop Bit
This bit controls the functionality of the oscillator during Stop mode.
0
1
Oscillator is disabled in Stop mode (Full Stop mode).
Oscillator continues to run in Stop mode (Pseudo Stop mode), option to run RTI and COP.
6
Note: Pseudo Stop mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of
frequent STOP conditions at the expense of a slightly increased power consumption.
PSTP
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop mode with OSCE bit is
already 1) the software must wait for a minimum time equivalent to the startup time of the external oscillator t
entering Pseudo Stop mode.
before
UPOSC
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop mode.
3
PRE
0
1
RTI stops running during Pseudo Stop mode.
RTI continues running during Pseudo Stop mode if RTIOSCSEL=1.
Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop mode is active. The RTI counter will not be reset.
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop mode.
2
PCE
0
1
COP stops running during Pseudo Stop mode
COP continues running during Pseudo Stop mode if COPOSCSEL=1
Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop mode is active. The COP counter will not be reset.
RTI Clock Select— RTIOSCSELselects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the RTIOSCSEL bit re-starts
the RTI timeout period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
1
RTIOSCSEL
0
1
RTI clock source is IRCCLK.
RTI clock source is OSCCLK.
COP Clock Select— COPOSCSEL selects the clock source to the COP. Either IRCCLK or OSCCLK. Changing the COPOSCSEL bit
re-starts the COP timeout period.
COPOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL bit.
0
COPOSCSEL
0
1
COP clock source is IRCCLK.
COP clock source is OSCCLK
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4.23.3.2.7
9S12I128PIMV1 PLL control register (CPMUPLL)
This register controls the PLL functionality.
Table 413. 9S12I128PIMV1 PLL control register (CPMUPLL)
0x003A
7
0
6
0
5
FM1
0
4
FM0
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the specified maximum when
frequency modulation is enabled.
NOTE
The frequency modulation (FM1 and FM0) can not be used if the Adaptive Oscillator Filter is enabled.
Table 414. CPMUPLL field descriptions
Field
Description
5, 4
FM1, FM0
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This is to reduce noise
emission. The modulation frequency is f divided by 16. See Table 415 for coding.
REF
Table 415. FM Amplitude selection
FM1
FM0
FM amplitude /f
variation
VCO
0
0
1
1
0
1
0
1
FM off
1%
2%
4%
4.23.3.2.8
9S12I128PIMV1 RTI control register (CPMURTI)
This register selects the timeout period for the Real Time Interrupt. The clock source for the RTI is either IRCCLK or OSCCLK depending
on the setting of the RTIOSCSEL bit. In Stop mode with PSTP=1 (Pseudo Stop mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop mode.
Table 416. 9S12I128PIMV1 RTI control register (CPMURTI)
0x003B
7
RTDEC
0
6
RTR6
0
5
RTR5
0
4
RTR4
0
3
RTR3
0
2
RTR2
0
1
RTR1
0
0
RTR0
0
R
W
Reset
Read: Anytime
Write: Anytime
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NOTE
A write to this register starts the RTI timeout period. A change of the RTIOSCSEL bit (writing a
different value or loosing UPOSC status) re-starts the RTI timeout period.
Table 417. CPMURTI field descriptions
Field
Description
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
7
0
1
Binary based divider value. See Table 418
Decimal based divider value. See Table 419
RTDEC
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 418 and Table 419.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional
granularity.Table 418 and Table 419 show all possible divide values selectable by the CPMURTI register.
Table 418. RTI frequency divide rates for RTDEC = 0
RTR[6:4] =
RTR[3:0]
000
001
010
011
100
101
110
111
10
11
12
13
14
15
16
(OFF)
(2
)
(2
)
(2
)
(2
)
(2
)
(2
)
(2 )
(272)
10
11
12
13
14
15
16
0000 (1)
0001 (2)
0010 (3)
0011 (4)
0100 (5)
0101 (6)
0110 (7)
0111 (8)
1000 (9)
1001 (10)
1010 (11)
1011 (12)
1100 (13)
1101 (14)
1110 (15)
1111 (16)
OFF
2
2
2
2
2
2
2
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
10
10
10
10
10
10
10
11
11
11
11
11
11
11
12
12
12
12
12
12
12
13
13
13
13
13
13
13
14
14
14
14
14
14
14
15
15
15
15
15
15
15
16
16
16
16
16
16
16
10x2
11x2
12x2
13x2
14x2
15x2
16x2
10x2
11x2
12x2
13x2
14x2
15x2
16x2
10x2
11x2
12x2
13x2
14x2
15x2
16x2
10x2
11x2
12x2
13x2
14x2
15x2
16x2
10x2
11x2
12x2
13x2
14x2
15x2
16x2
10x2
11x2
12x2
13x2
14x2
15x2
16x2
10x2
11x2
12x2
13x2
14x2
15x2
16x2
Notes
272. Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
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Table 419. RTI frequency divide rates for RTDEC=1
RTR[3:0]
RTR[6:4] =
100
000
001
010
011
101
110
111
3
3
3
3
3
3
3
3
(1x10 )
(2x10 )
(5x10 )
(10x10 )
(20x10 )
(50x10 )
(100x10 )
(200x10 )
3
3
3
3
3
3
3
3
0000 (1)
0001 (2)
0010 (3)
0011 (4)
0100 (5)
0101 (6)
0110 (7)
0111 (8)
1000 (9)
1001 (10)
1010 (11)
1011 (12)
1100 (13)
1101 (14)
1110 (15)
1111 (16)
1x10
2x10
5x10
10x10
20x10
50x10
100x10
200x10
3
3
3
3
3
3
3
3
2x10
4x10
10x10
20x10
40x10
100x10
200x10
400x10
3
3
3
3
3
3
3
3
3x10
6x10
15x10
30x10
60x10
150x10
300x10
600x10
3
3
3
3
3
3
3
3
4x10
8x10
20x10
40x10
80x10
200x10
400x10
800x10
3
3
3
3
3
3
3
6
5x10
10x10
25x10
50x10
100x10
250x10
500x10
1x10
3
3
3
3
3
3
3
6
6x10
12x10
30x10
60x10
120x10
300x10
600x10
1.2x10
3
3
3
3
3
3
3
6
7x10
14x10
35x10
70x10
140x10
350x10
700x10
1.4x10
3
3
3
3
3
3
3
6
8x10
16x10
40x10
80x10
160x10
400x10
800x10
1.6x10
3
3
3
3
3
3
3
6
9x10
18x10
45x10
90x10
180x10
450x10
900x10
1.8x10
3
3
3
3
3
3
6
6
10 x10
20x10
50x10
100x10
200x10
500x10
1x10
2x10
3
3
3
3
3
3
6
6
11 x10
22x10
55x10
110x10
220x10
550x10
1.1x10
2.2x10
3
3
3
3
3
3
6
6
12x10
24x10
60x10
120x10
240x10
600x10
1.2x10
2.4x10
3
3
3
3
3
3
6
6
13x10
26x10
65x10
130x10
260x10
650x10
1.3x10
2.6x10
3
3
3
3
3
3
6
6
14x10
28x10
70x10
140x10
280x10
700x10
1.4x10
2.8x10
3
3
3
3
3
3
6
6
15x10
30x10
75x10
150x10
300x10
750x10
1.5x10
3x10
3
3
3
3
3
3
6
6
16x10
32x10
80x10
160x10
320x10
800x10
1.6x10
3.2x10
4.23.3.2.9
9S12I128PIMV1 COP control register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog. The clock source for the COP is either IRCCLK or OSCCLK
depending on the setting of the COPOSCSEL bit. In Stop mode with PSTP=1(Pseudo Stop mode), COPOSCSEL=1 and PCE=1 the COP
continues to run, else the COP counter halts in Stop mode.
Table 420. 9S12I128PIMV1 COP control register (CPMUCOP)
0x003C
7
WCOP
F
6
RSBCK
0
5
4
0
3
0
2
CR2
F
1
CR1
F
0
CR0
F
R
W
0
WRTMASK
0
Reset
0
0
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for details.
= Unimplemented or Reserved
Read: Anytime
Write:
1. RSBCK: anytime in Special Mode; write to “1” but not to “0” in Normal mode
2. WCOP, CR2, CR1, CR0:
—
—
Anytime in Special mode, when WRTMASK is 0, otherwise it has no effect
Write once in Normal mode, when WRTMASK is 0, otherwise it has no effect.
–
–
Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
Writing WCOP to “0” has no effect, but counts for the “write once” condition.
When a non-zero value is loaded from Flash to CR[2:0] the COP timeout period is started.
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A change of the COPOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the COP timeout period.
In Normal mode the COP timeout period is restarted if either of these conditions is true:
1. Writing a non-zero value to CR[2:0] (anytime in Special mode, once in Normal mode) with WRTMASK = 0.
2. Writing WCOP bit (anytime in Special mode, once in Normal mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
In Special mode, any write access to CPMUCOP register restarts the COP timeout period.
Table 421. CPMUCOP field descriptions
Field
Description
Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the selected period. A write
during the first 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55 can be written as
often as desired. Once $AA is written after the $55, the timeout logic restarts and the user must wait until the next window before writing
to CPMUARMCOP. Table 422 shows the duration of this window for the seven available COP rates.
7
WCOP
0
1
Normal COP operation
Window COP operation
COP and RTI Stop in Active BDM Mode Bit
6
0
1
Allows the COP and RTI to keep running in Active BDM mode.
Stops the COP and RTI counters whenever the part is in Active BDM mode.
RSBCK
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the
CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of WCOP and CR[2:0].
5
0
1
Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP
Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP. (Does not count for “write once”.)
WRTMASK
COP Watchdog Timer Rate Select — These bits select the COP timeout rate (see Table 422). Writing a nonzero value to CR[2:0]
enables the COP counter and starts the timeout period. A COP counter timeout causes a System Reset. This can be avoided by
periodically (before timeout) initializing the COP counter via the CPMUARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest timeout period (2
cycles) in normal COP mode (Window COP mode disabled):
2–0
CR[2:0]
24
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in Special mode
Table 422. COP watchdog rates
COPCLK
CR2
CR1
CR0
Cycles to Time-out (COPCLK is either IRCCLK or
OSCCLK depending on the COPOSCSEL bit)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COP disabled
14
2
16
2
18
2
20
2
22
2
23
2
24
2
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4.23.3.2.10 Reserved register CPMUTEST0
NOTE
This reserved register is designed for factory test purposes only, and is not intended for general user
access. Writing to this register when in Special mode can alter the 9S12I128PIMV1’s functionality.
Table 423. Reserved register (CPMUTEST0)
0x003D
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special mode
4.23.3.2.11 Reserved register CPMUTEST1
NOTE
This reserved register is designed for factory test purposes only, and is not intended for general user
access. Writing to this register when in Special mode can alter the 9S12I128PIMV1’s functionality.
Table 424. Reserved register (CPMUTEST1)
0x003E
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special Mode
4.23.3.2.12 9S12I128PIMV1 COP Timer Arm/reset Register (CPMUARMCOP)
This register is used to restart the COP timeout period.
Table 425. 9S12I128PIMV1 CPMUARMCOP register
0x003F
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reset
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
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Writing any value other than $55 or $AA causes a COP reset. To restart the COP timeout period write $55 followed by a write of
$AA. These writes do not need to occur back-to-back, but the sequence ($55, $AA) must be completed prior to COP end of
timeout period to avoid a COP reset. Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must
be done in the last 25% of the selected timeout period; writing any value in the first 75% of the selected period will cause a COP
reset.
4.23.3.2.13 Low-voltage control register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Table 426. Low-voltage control register (CPMULVCTL)
0x02F1
7
0
6
0
5
0
4
0
3
0
2
1
LVIE
0
0
LVIF
U
R
W
LVDS
Reset
0
0
0
0
0
U
The Reset state of LVDS and LVIF depends on the external supplied VDDXR level
= Unimplemented or Reserved
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
Table 427. CPMULVCTL field descriptions
Field
Description
Low-voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDXR. Writes have no effect.
2
0
1
Input voltage VDDXR is above level V
Input voltage VDDRX is below level V
or RPM.
and FPM.
LVID
LVIA
LVDS
Low-voltage Interrupt Enable Bit
1
LVIE
0
1
Interrupt request is disabled.
Interrupt will be requested whenever LVIF is set.
Low-voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0
has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0
0
1
No change in LVDS bit.
LVDS bit has changed.
LVIF
4.23.3.2.14 Reserved register CPMUTEST3
NOTE
This reserved register is designed for factory test purposes only, and is not intended for general user
access. Writing to this register when in Special mode can alter the 9S12I128PIMV1’s functionality.
Table 428. Reserved register (CPMUTEST3)
0x02F6
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special mode
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4.23.3.2.15 9S12I128PIMV1 IRC1M trim registers (CPMUIRCTRIMH / CPMUIRCTRIML)
Table 430. 9S12I128PIMV1 IRC1M trim high register (CPMUIRCTRIMH)
0x02F8
15
F
14
F
13
TCTRIM[4:0]
F
12
F
11
10
0
9
8
F
R
W
IRCTRIM[9:8]
Reset
0
0
F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference
Frequency f
.
IRC1M_TRIM
Table 431. 9S12I128PIMV1 IRC1M trim low register (CPMUIRCTRIML)
0x02F9
7
6
5
4
3
F
2
F
1
F
0
F
R
W
IRCTRIM[7:0]
Reset
F
F
F
F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal
Reference Frequency f
.
IRC1M_TRIM
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect
NOTE
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC status bits.
Table 432. CPMUIRCTRIMH/L field descriptions
Field
Description
IRC1M temperature coefficient Trim Bits
15-11
Trim bits for the Temperature Coefficient (TC) of the IRC1M frequency.
TCTRIM
Figure 93 shows the influence of the bits TCTRIM4:0] on the relationship between frequency and temperature.
Figure 93 shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for TCTRIM[4:0]=0x00000 or 0x10000).
IRC1M Frequency Trim Bits — Trim bits for Internal Reference Clock
After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in an Internal Reference
Frequency f
. See device electrical characteristics for value of f
.
IRC1M_TRIM
IRC1M_TRIM
9-0
The frequency trimming consists of two different trimming methods:
IRCTRIM
A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average.
A fine trimming controlled by the bits IRCTRIM[5:0] can be done with frequency leaps of about 0.3% (this trimming determines the
precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 92 shows the relationship
between the trim bits and the resulting IRC1M frequency.
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IRC1M frequency (IRCCLK)
IRCTRIM[9:6]
1.5 MHz
IRCTRIM[5:0]
1.0 MHz
......
600 kHz
$000
IRCTRIM[9:0]
$3FF
$1FF
Figure 92. IRC1M frequency trimming diagram
frequency
0x11111
...
0x10101
0x10100
0x10011
0x10010
0x10001
TC increases
TC decreases
TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC)
0x00001
0x00010
0x00011
0x00100
0x00101
...
0x01111
$1FF
150 C
- 40 C
temperature
Figure 93. Influence of TCTRIM[4:0] on the temperature coefficient
NOTE
The frequency is not necessarily linear with the temperature (in most cases it will not be). The above
diagram is meant only to give the direction (positive or negative) of the variation of the TC, relative to
the nominal TC.
Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefficient will be
zero. These two combinations basically switch off the TC compensation module, which result in the
nominal TC of the IRC1M.
Table 433. TC Trimming of the Frequency of the IRC1M
IRC1M indicative frequency drift for
relative TC variation
TCTRIM[4:0]
IRC1M indicative relative TC variation
00000
00001
00010
00011
00100
0 (nominal TC of the IRC)
0%
-0.27%
-0.54%
-0.81%
-1.08%
-0.5%
-0.9%
-1.3%
-1.7%
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Table 433. TC Trimming of the Frequency of the IRC1M (continued)
IRC1M indicative frequency drift for
TCTRIM[4:0]
IRC1M indicative relative TC variation
relative TC variation
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
-1.35%
-1.63%
-2.0%
-2.2%
-1.9%
-2.5%
-2.20%
-3.0%
-2.47%
-3.4%
-2.77%
-3.9%
-3.04
-4.3%
-3.33%
-4.7%
-3.6%
-5.1%
-3.91%
-5.6%
-4.18%
-5.9%
0 (nominal TC of the IRC)
+0.27%
+0.54%
+0.81%
+1.07%
+1.34%
+1.59%
+1.86%
+2.11%
0%
+0.5%
+0.9%
+1.3%
+1.7%
+2.0%
+2.2%
+2.5%
+3.0%
+3.4%
+3.9%
+4.3%
+4.7%
+5.1%
+5.6%
+5.9%
+2.38%
+2.62%
+2.89%
+3.12%
+3.39%
+3.62%
+3.89%
NOTE
Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the
above relative variation is only an indication and should be considered with care.
Be aware that the output frequency varies with the TC trimming. A frequency trimming correction is
therefore necessary. The values provided in Table 433 are typical values at ambient temperature
which can vary from device to device.
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4.23.3.2.16 9S12I128PIMV1 oscillator register (CPMUOSC)
This register configures the external oscillator (OSCLCP).
Table 434. 9S12I128PIMV1 oscillator register (CPMUOSC)
0x02FA
7
OSCE
0
6
OSCBW
0
5
4
0
3
0
2
1
0
0
0
R
W
OSCPINS_EN
OSCFILT[4:0]
0
Reset
0
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
If the chosen VCOCLK-to-OSCCLK ratio divided by two ((f
/ f
)/2) is not an integer number,
VCO OSC
the filter can not be used and the OSCFILT[4:0] bits must be set to 0.
NOTE
The frequency modulation (FM1 and FM0) can not be used if the Adaptive Oscillator Filter is enabled.
Table 435. CPMUOSC field descriptions
Field
Description
Oscillator Enable Bit — This bit enables the external oscillator (OSCLCP). The UPOSC status bit in the CPMUFLG register indicates
when the oscillation is stable and OSCCLK can be selected as bus clock or source of the COP or RTI. A loss of oscillation will lead to a
clock monitor reset.
0
External oscillator is disabled.
REFCLK for PLL is IRCCLK.
7
1
External oscillator is enabled.Clock monitor is enabled.
REFCLK for PLL is external oscillator clock divided by REFDIV.
OSCE
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop mode with OSCE bit already
1) the software must wait for a minimum time equivalent to the startup time of the external oscillator t
Pseudo Stop mode.
before entering
UPOSC
Oscillator Filter Bandwidth Bit — If the VCOCLK frequency exceeds 25 MHz wide bandwidth must be selected. The Oscillator Filter
is described in more detail in Section 4.23.4.5.2, “The adaptive oscillator filter"
6
0
1
Oscillator filter bandwidth is narrow (window for expected OSCCLK edge is one VCOCLK cycle).
Oscillator filter bandwidth is wide (window for expected OSCCLK edge is three VCOCLK cycles).
OSCBW
Oscillator Pins EXTAL and XTAL Enable Bit
If OSCE=1 this read-only bit is set. It can only be cleared with the next reset.
Enabling the external oscillator reserves the EXTAL and XTAL pins exclusively for oscillator application.
5
OSCPINS_EN
0
1
EXTAL and XTAL pins are not reserved for oscillator.
EXTAL and XTAL pins exclusively reserved for oscillator.
Oscillator Filter Bits — When using the oscillator a noise filter can be enabled, which filters noise from the incoming external oscillator
clock and detects if the external oscillator clock is qualified or not (quality status shown by bit UPOSC).
4-0
OSCFILT
The VCOCLK-to-OSCCLK ratio divided by two ((f
bits to enable the Adaptive Oscillator Filter.
/ f
)/2) must be an integer value. This value must be written to the OSCFILT[4:0]
VCO OSC
0x0000 Adaptive Oscillator Filter disabled, else Adaptive Oscillator Filter enabled]
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4.23.3.2.17 9S12I128PIMV1 protection register (CPMUPROT)
This register protects the following clock configuration registers from accidental overwrite:
CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L, and CPMUOSC
Table 436. 9S12I128PIMV1 protection register (CPMUPROT)
0x02FB
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PROT
0
R
W
Reset
0
0
0
0
0
0
0
Read: Anytime
Write: Anytime
Table 437. CPMUPROT field description
Field
Description
Clock Configuration Registers Protection Bit — This bit protects the clock configuration registers from accidental overwrite (see list
of protected registers above).
Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit.
0
0
1
Protection of clock configuration registers is disabled.
Protection of clock configuration registers is enabled. (see list of protected registers above)
4.23.3.2.18 Reserved register CPMUTEST2
NOTE
This reserved register is designed for factory test purposes only, and is not intended for general user
access. Writing to this register when in Special mode can alter the 9S12I128PIMV1’s functionality.
Table 438. Reserved register CPMUTEST2
0x02FC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special mode
4.23.4 Functional description
4.23.4.1 Phase locked loop with internal filter (PLL)
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK. The REFCLK is by default the IRCCLK which is
trimmed to f =1.0 MHz.
IRC1M_TRIM
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to
16 to generate the reference frequency REFCLK using the REFDIV[3:0] bits. Based on the SYNDIV[5:0] bits, the PLL generates the
VCOCLK by multiplying the reference clock by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits, the VCOCLK can be divided in a
range of 1,2, 3, 4, 5, 6,... to 32 to generate the PLLCLK.
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.
f
OSC
------------------------------------
=
f
f
If Oscillator is enabled (OSCE=1)
REF
REF
REFDIV + 1
If Oscillator is disabled (OSCE=0)
= f
IRC1M
f
= 2 f
SYNDIV + 1
VCO
REF
f
VCO
----------------------------------------
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
f
=
PLL
POSTDIV + 1
f
VCO
--------------
f
=
PLL
4
f
PLL
------------
f
=
bus
2
NOTE
Although it is possible to set the dividers to command a very high clock frequency, do not exceed the
specified bus frequency limit for the MCU.
Several examples of PLL divider settings are shown in Table 439. The following rules help to achieve optimum stability and shortest lock
time:
•
•
Use lowest possible f
Use highest possible REFCLK frequency f
/ f
ratio (SYNDIV value).
VCO REF
.
REF
Table 439. Examples of PLL divider settings
f
REFDIV[3:0]
f
REFFRQ[1:0]
SYNDIV[5:0]
f
VCOFRQ[1:0]
POSTDIV[4:0]
f
f
bus
osc
REF
VCO
PLL
off
off
$00
$00
$00
$00
1.0 MHz
1.0 MHz
1.0 MHz
4.0 MHz
00
00
00
01
$1F
$1F
$0F
$03
64 MHz
64 MHz
32 MHz
32 MHz
01
01
00
01
$03
$00
$00
$00
16 MHz
64 MHz
32 MHz
32 MHz
8.0 MHz
32 MHz
16 MHz
16 MHz
off
4.0 MHz
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1) with the reference clock (REFCLK =
(IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated based on the phase difference between the two signals. The loop
filter alters the DC voltage on the internal filter capacitor, based on the width and direction of the correction pulse, which leads to a higher
or lower VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the VCOCLK frequency (VCOFRQ[1:0]
bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore, the speed of the lock detector is directly
proportional to the reference clock frequency. The circuit determines the lock condition based on this comparison.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance check the LOCK bit. If interrupt
requests are disabled, software can poll the LOCK bit continuously (during PLL start-up) or at periodic intervals. In either case, only when
the LOCK bit is set, the VCOCLK will have stabilized to the programmed frequency.
•
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within the tolerance,
, and is cleared when the VCO frequency is out of
LOCK
the tolerance,
.
UNl
•
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit.
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4.23.4.2 Startup from reset
An example of startup of clock system from Reset is given in Figure 94.
System
Reset
768 cycles
VCORST
f
=32 MHz
f
=16MHz
f
increasing
PLL
PLL
f
PLL
PLLCLK
LOCK
) (
t
lock
SYNDIV
$1F (default target f
$03 (default target f
reset state
=64MHz)
VCO
POSTDIV
=f
/4 = 16MHz)
$01
PLL VCO
example change
of POSTDIV
CPU
vector fetch, program execution
Figure 94. Startup of clock system after reset
4.23.4.3 Stop mode using PLLCLK as bus clock
An example of what happens going into Stop mode and exiting Stop mode after an interrupt is shown in Figure 95. Disable PLL Lock
interrupt (LOCKIE=0) before going into Stop mode.
wake-up
interrupt continue execution
execution
STOP instruction
CPU
t
STP_REC
PLLCLK
LOCK
t
lock
Figure 95. Stop mode using PLLCLK as bus clock
4.23.4.4 Full stop mode using oscillator clock as bus clock
An example of what happens going into Full Stop mode and exiting Full Stop mode after an interrupt is shown in Figure 96. Disable PLL
Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop mode.
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wake-up
interrupt continue execution
execution
STOP instruction
CPU
Core
Clock
t
STP_REC
t
lock
PLLCLK
OSCCLK
UPOSC
select OSCCLK as Core/Bus Clock by writing PLLSEL to “0”
PLLSEL
automatically set when going into Full Stop Mode
Figure 96. Full stop mode using oscillator clock as bus clock
4.23.4.5 External oscillator
4.23.4.5.1
Enabling the external oscillator
An example of how to use the oscillator as Bus Clock is shown in Figure 97.
enable external oscillator by writing OSCE bit to one.
OSCE
crystal/resonator starts oscillating
EXTAL
UPOSC flag is set upon successful start of oscillation
UPOSC
OSCCLK
PLLSEL
select OSCCLK as Core/Bus Clock by writing PLLSEL to zero
based on OSCCLK
based on PLLCLK
Core
Clock
Figure 97. Enabling the external oscillator
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4.23.4.5.2
The adaptive oscillator filter
A spike in the oscillator clock can disturb the function of the modules driven by this clock. The Adaptive Oscillator Filter includes two
features:
1. Filter noise (spikes) from the incoming external oscillator clock. The filter feature is illustrated in Figure 98.
enable external oscillator
OSCE
configure the Adaptive Oscillator Filter
OSC
0
> 0
FILT
crystal/resonator starts oscillating
EXTAL
LOCK
UPOSC
filtered
filtered
OSCCLK
(filtered)
Figure 98. Noise filtered by the adaptive oscillator filter
2. Detect severe noise disturbance on external oscillator clock which can not be filtered and indicate the critical situation to the
software by clearing the UPOSC and LOCK status bit and setting the OSCIF and LOCKIF flag. An example for the detection of
critical noise is illustrated in Figure 99.
enable external oscillator
OSCE
configure the Adaptive Oscillator Filter
OSC
0
> 0
FILT
crystal/resonator starts oscillating
phase shift can not be filtered but detected
EXTAL
LOCK
UPOSC
OSCCLK
(filtered)
Figure 99. Critical noise detected by the adaptive oscillator filter
NOTE
If the LOCK bit is clear due to severe noise disturbance on the external oscillator clock, the PLLCLK
is derived from the VCO clock (with its actual frequency) divided by four (see Section 4.23.3.2.3,
“9S12I128PIMV1 post divider register (CPMUPOSTDIV)").
The use of the filter function is only possible if the VCOCLK-to-OSCCLK ratio divided by two ((f
/ f
)/2) is an integer number. This
VCO OSC
integer value must be written to the OSCFILT[4:0] bits. If enabled, the Adaptive Oscillator Filter samples the incoming external oscillator
clock signal (EXTAL) with the VCOCLK frequency.
Using VCOCLK, a time window is defined of which an edge of the OSCCLK is expected. In case of OSCBW = 1, the width of this window
is three VCOCLK cycles, if the OSCBW = 0 it is one VCOCLK cycle. The noise detection is active for certain combinations of OSCFILT[4:0]
and OSCBW bit settings, as shown in Table 440.
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Table 440. Noise detection settings
OSCFILT[4:0]
OSCBW
Detection
disabled
disabled
active
Filter
0
1
x
x
0
1
x
disabled
active
active
active
active
2 or 3
>=4
disabled
active
NOTE
If the VCOCLK frequency is higher than 25 MHz the wide bandwidth must be selected (OSCBW = 1).
4.23.4.6 System clock configurations
4.23.4.6.1 PLL engaged internal mode (PEI)
This mode is the default mode after System Reset or Power-on Reset. The Bus Clock is based on the PLLCLK, the reference clock for
the PLL is internally generated (IRC1M). The PLL is configured to 64 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this
results in a PLLCLK of 16 MHz and a Bus Clock of 8.0 MHz. The PLL can be re-configured to other bus frequencies. The clock sources
for COP and RTI are based on the internal reference clock generator (IRC1M).
4.23.4.6.2
PLL engaged external mode (PEE)
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL is based on the external oscillator.
The adaptive spike filter and detection logic which uses the VCOCLK to filter and qualify the external oscillator clock can be enabled.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
1. Configure the PLL for desired bus frequency.
2. Optionally the adaptive spike filter and detection logic can be enabled by calculating the integer value for the OSCFIL[4:0] bits
and setting the bandwidth (OSCBW) accordingly.
3. Enable the external Oscillator (OSCE bit).
4. Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up and additionally being qualified if the Adaptive Oscillator
Filter is enabled (UPOSC =1).
5. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
6. Optionally status interrupts can be enabled (CPMUINT register).
Since the Adaptive Oscillator Filter (adaptive spike filter and detection logic) uses the VCOCLK to continuously filter and qualify the
external oscillator clock, losing PLL lock status (LOCK=0), means losing the oscillator status information as well (UPOSC=0).
The impact of losing the oscillator status in PEE mode is as follows:
•
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
Application software needs to be prepared to deal with the impact of losing the oscillator status at any time.
4.23.4.6.3
PLL bypassed external mode (PBE)
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is based on the external oscillator.
The adaptive spike filter and detection logic can be enabled which uses the VCOCLK to filter and qualify the external oscillator clock.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
1. Make sure the PLL configuration is valid.
2. Optionally, the adaptive spike filter and detection logic can be enabled by calculating the integer value for the OSCFIL[4:0] bits
and setting the bandwidth (OSCBW) accordingly.
3. Enable the external Oscillator (OSCE bit)
4. Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up, and additionally being qualified if the Adaptive Oscillator
Filter is enabled (UPOSC=1).
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5. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
6. Optionally status interrupts can be enabled (CPMUINT register).
7. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
Since the Adaptive Oscillator Filter (adaptive spike filter and detection logic) uses the VCOCLK to continuously filter and qualify the
external oscillator clock, losing PLL lock status (LOCK=0) means losing the oscillator status information as well (UPOSC=0).
The impact of losing the oscillator status in PBE mode is as follows:
•
•
PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.
In the PBE mode, not every noise disturbance can be indicated by bits LOCK and UPOSC (both bits are based on the Bus Clock domain).
There are clock disturbances possible, after which UPOSC and LOCK both stay asserted, while occasional pauses on the filtered
OSCCLK and resulting Bus Clock occur. The adaptive spike filter is still functional and protects the Bus Clock from frequency overshoot
due to spikes on the external oscillator clock. The filtered OSCCLK and resulting Bus Clock will pause until the PLL has stabilized again.
4.23.5 Resets
4.23.5.1 General
All reset sources are listed in Table 441. Refer to MCU specification for related vector addresses and priorities.
Table 441. Reset summary
Reset source
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock Monitor Reset
COP Reset
Local enable
None
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
4.23.5.2 Description of reset operation
Upon detection of any reset in Table 441, an internal circuit drives the RESET pin low for 512 PLLCLK cycles. After 512 PLLCLK cycles,
the RESET pin is released. The reset generator of the 9S12I128PIMV1 waits for additional 256 PLLCLK cycles and then samples the
RESET pin to determine the originating source. Table 442 shows which vector will be fetched.
Table 442. Reset vector selection
Sampled RESET Pin (256 cycles
after release)
Oscillator monitor fail
pending
COP timeout pending
Vector fetch
POR
LVR
1
0
0
Illegal Address Reset
External pin RESET
1
1
1
0
X
1
Clock Monitor Reset
COP Reset
POR
LVR
0
X
X
Illegal Address Reset
External pin RESET
NOTE
While System Reset is asserted, the PLLCLK runs with the frequency f
.
VCORST
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The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK cycles long reset sequence. In case
the RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal reset remains asserted
longer.
RESET
S12_CPMU drives
RESET pin low
S12_CPMU releases
RESET pin
fVCORST
fVCORST
)
)
)
PLLCLK
(
(
(
512 cycles
256 cycles
possibly RESET
driven low externally
Figure 100. RESET timing
4.23.5.2.1
Clock monitor reset
When the external oscillator is enabled (OSCE=1), in case of a loss of oscillation or the oscillator frequency is below the failure assert
frequency f (see device electrical characteristics for values), the 9S12I128PIMV1 generates a clock monitor reset. In Full Stop mode
CMFA
the external oscillator and the clock monitor are disabled.
4.23.5.2.2
Computer operating properly watchdog (COP) reset
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is
being used, software is responsible for keeping the COP from timing out. If the COP times out, it is an indication that the software is no
longer being executed in the intended sequence, and a COP reset is generated.
The clock source for the COP is either IRCCLK or OSCCLK, depending on the setting of the COPOSCSEL bit. In Stop mode with PSTP=1
(Pseudo Stop mode), COPOSCSEL=1 and PCE=1 the COP continues to run, else the COP counter halts in Stop mode. Three control bits
in the CPMUCOP register allow selection of seven COP timeout periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP register during the selected timeout
period. Once this is done, the COP timeout period is restarted. If the program fails to do this and the COP times out, a COP reset is
generated. Also, if any value other than $55 or $AA is written, a COP reset is generated.
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to the CPMUARMCOP register to
clear the COP timer must occur in the last 25% of the selected timeout period. A premature write will immediately reset the part.
4.23.5.3 Power-on Reset (POR)
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage level. The POR is deasserted if the
internal supply VDD exceeds an appropriate voltage level (voltage levels are not specified in this document, because this internal supply
is not visible on device pins).
4.23.5.4 Low-voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDF, or VDDX, drops below an appropriate voltage level. If LVR
is deasserted, the MCU is fully operational at the specified maximum speed. The LVR assert and deassert levels for the supply voltage
VDDX are V
and V
, and are specified in the device reference manual.
LVRXA
LVRXD
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4.23.6 Interrupts
The interrupt/reset vectors requested by the 9S12I128PIMV1 are listed in Table 443. Refer to MCU specification for related vector
addresses and priorities.
Table 443. 9S12I128PIMV1 Interrupt Vectors
Interrupt source
RTI timeout interrupt
PLL lock interrupt
CCR mask
I bit
Local enable
CPMUINT (RTIE)
CPMUINT (LOCKIE)
CPMUINT (OSCIE)
CPMULVCTL (LVIE)
I bit
Oscillator status interrupt
Low voltage interrupt
I bit
I bit
4.23.6.1 Description of interrupt operation
4.23.6.1.1 Real time interrupt (RTI)
The clock source for the RTI is either IRCCLK or OSCCLK, depending on the setting of the RTIOSCSEL bit. In Stop mode with PSTP=1
(Pseudo Stop mode), RTIOSCSEL=1 and PRE=1 the RTI continues to run, else the RTI counter halts in Stop mode.
The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the
rate selected by the CPMURTI register. At the end of the RTI timeout period, the RTIF flag is set to one and a new RTI timeout period
starts immediately.
A write to the CPMURTI register restarts the RTI timeout period.
4.23.6.1.2
PLL lock interrupt
The 9S12I128PIMV1 generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL changes, either from a locked
state to an unlocked state, or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt flag
(LOCKIF) is set to 1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
4.23.6.1.3
Oscillator status interrupt
The Adaptive Oscillator filter contains two different features:
1. Filters spikes of the external oscillator clock.
2. Qualify the external oscillator clock.
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 and OSCFILT = 0, then the filter is transparent and no spikes are filtered.
The UPOSC bit is then set after the LOCK bit is set.
Upon detection of a status change (UPOSC), where an unqualified oscillation becomes qualified or vice versa, the OSCIF flag is set. Going
into Full Stop mode or disabling the oscillator can also cause a status change of UPOSC.
Since the Adaptive Oscillator Filter is based on the PLLCLK, any change in PLL configuration or any other event which causes the PLL
lock status to be cleared, leads to a loss of the oscillator status information as well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
NOTE
Losing the oscillator status (UPOSC=0) affects the clock configuration of the system(273). This needs
to be addressed in application software.
Notes
273. For details refer to “Section 4.23.4.6, “System clock configurations”
4.23.6.1.4
Low-voltage interrupt (LVI)
In FPM, the input voltage VDDXR is monitored. Whenever VDDXR drops below level V
, the status bit LVDS is set to 1. When VDDXR
LVIA
rises above level V
, the status bit LVDS is cleared to 0. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status
LVID
bit LVDS if interrupt enable bit LVIE = 1.
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4.23.7 Initialization/application information
4.23.7.1 General initialization information
Usually applications run in MCU Normal mode. It is recommended to write the CPMUCOP register from the application program
initialization routine after reset, regardless if the COP is used in the application, even if a configuration is loaded via the flash memory after
reset. By doing a “controlled” write access in MCU Normal mode (with the right value for the application), the write once for the COP
configuration bits (WCOP,CR[2:0]) takes place, which protects these bits from further accidental change. If there is a program sequencing
issue (code runaway), the COP configuration cannot be accidentally modified.
4.24 MCU - serial peripheral interface (S129S12I128PIMV1V5)
4.24.1 Introduction
The SPI module allows a duplex, synchronous, serial communication, between the MCU and peripheral devices. Software can poll the
SPI status flags or the SPI operation can be interrupt driven.
4.24.1.1 Glossary of terms
Table 444. Term Definition
SPI
SS
Serial Peripheral Interface
Slave Select
SCK
MOSI
MISO
MOMI
SISO
Serial Clock
Master Output, Slave Input
Master Input, Slave Output
Master Output, Master Input
Slave Input, Slave Output
4.24.1.2 Features
The 9S12I128PIMV1 includes these distinctive features:
•
•
•
•
•
•
•
•
Master mode and slave mode
Selectable 8 or 16-bit transfer width
Bidirectional mode
Slave select output
Mode fault error flag with CPU interrupt capability
Double-buffered data register
Serial clock with programmable polarity and phase
Control of SPI operation during Wait mode
4.24.1.3 Modes of operation
The SPI functions in three modes: run, wait, and stop.
•
•
Run mode
This is the basic mode of operation.
Wait mode
SPI operation in Wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In
Wait mode, if the SPISWAI bit is clear, the SPI operates like in Run mode. If the SPISWAI bit is set, the SPI goes into a power
conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress
stops, but is resumed after CPU goes into Run mode. If the SPI is configured as a slave, reception and transmission of data
continues, so that the slave stays synchronized to the master.
•
Stop mode
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The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in
progress stops, but is resumed after CPU goes into Run mode. If the SPI is configured as a slave, reception and transmission
of data continues, so that the slave stays synchronized to the master.
For a detailed description of operating modes, refer to Section 4.24.4.7, “Low power mode options".
4.24.1.4 Block diagram
Figure 101 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud
rate generator, master/slave control logic, and port control logic.
SPI
2
SPI Control Register 1
BIDIROE
2
SPI Control Register 2
SPC0
SPI Status Register
SPIF
Slave
Control
CPOL
CPHA
MOSI
MODF SPTEF
Phase +
Polarity
Control
SCK In
Interrupt Control
Slave Baud Rate
SPI
Interrupt
Master Baud Rate
Phase +
Polarity
Control
SCK Out
Request
Port
Control
Logic
SCK
SS
Baud Rate Generator
Counter
Master
Control
Bus Clock
Baud Rate
Prescaler
Clock Select
Shift
Clock
Sample
Clock
SPPR
3
3
SPR
Shifter
LSBFE=0
LSBFE=1
SPI Baud Rate Register
Data In
LSBFE=1
MSB
SPI Data Register
LSB
LSBFE=0
Data Out
LSBFE=0
LSBFE=1
Figure 101. SPI block diagram
4.24.2 External signal description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The 9S12I128PIMV1
module has a total of four external pins.
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4.24.2.1 MOSI — master out/slave in pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave.
4.24.2.2 MISO — master in/slave out pin
This pin is used to transmit data out of the SPI module when configured as a slave and receive data when configured as master.
4.24.2.3 SS — slave select pin
This pin is used to output the select signal from the SPI module to another peripheral, with which a data transfer is to take place when it
is configured as a master, and is used as an input to receive the slave select signal when the SPI is configured as a slave.
4.24.2.4 SCK — serial clock pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
4.24.3 Memory map and register definition
This section provides a detailed description of address space and registers used by the SPI.
4.24.3.1 Module memory map
The memory map for the 9S12I128PIMV1 is given in Table 445. The address listed for each register is the sum of a base address and an
address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the
reserved bits return zeros and writes to the reserved bits have no effect.
Table 445. SPI register summary
Register
Bit 7
6
5
4
3
2
1
Bit 0
Name
R
W
R
0x00E8
SPICR1
SPIE
0
SPE
SPTIE
0
MSTR
CPOL
CPHA
0
SSOE
LSBFE
0x00E9
SPICR2
XFRW
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
R
0
0x00EA
SPIBR
SPPR2
0
SPPR1
SPTEF
SPPR0
MODF
SPR2
0
SPR1
0
SPR0
0
W
R
SPIF
0
0x00EB
SPISR
W
R
R15
T15
R7
R14
T14
R6
R13
T13
R5
R12
T12
R4
R11
T11
R3
R10
T10
R2
R9
T9
R1
T1
R8
T8
R0
T0
0x00EC
SPIDRH
W
R
0x00ED
SPIDRL
W
R
T7
T6
T5
T4
T3
T2
0x00EE
Reserved
W
R
0x00EF
Reserved
W
= Unimplemented or Reserved
4.24.3.2 Register descriptions
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This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.24.3.2.1
SPI control register 1 (SPICR1)
Table 446. SPI control register 1 (SPICR1)
0x00E8
7
SPIE
0
6
SPE
0
5
SPTIE
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SSOE
0
0
LSBFE
0
R
W
Reset
Read: Anytime
Write: Anytime
Table 447. SPICR1 field descriptions
Field
Description
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
7
0
1
SPI interrupts disabled.
SPI interrupts enabled.
SPIE
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared,
SPI is disabled and forced into idle state, status bits in SPISR register are reset.
6
0
1
SPI disabled (lower power consumption).
SPI enabled, port pins are dedicated to SPI functions.
SPE
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
5
0
1
SPTEF interrupt disabled.
SPTEF interrupt enabled.
SPTIE
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master
to slave or vice versa forces the SPI system into idle state.
4
0
1
SPI is in slave mode.
SPI is in master mode.
MSTR
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules
must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system
into idle state.
3
CPOL
0
1
Active-high clocks selected. In idle state SCK is low.
Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
2
0
1
Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
CPHA
1
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as
shown in Table 448. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
SSOE
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have the MSB in the highest bit position. In master mode, a change of this bit will abort a transmission in progress and force the
SPI system into idle state.
0
LSBFE
0
1
Data is transferred most significant bit first.
Data is transferred least significant bit first.
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Table 448. SS input/output selection
MODFEN
SSOE
Master mode
SS not used by SPI
Slave mode
0
0
1
1
0
1
0
1
SS input
SS input
SS input
SS input
SS not used by SPI
SS input with MODF feature
SS is slave select output
4.24.3.2.2
SPI control register 2 (SPICR2)
Table 449. SPI control register 2 (SPICR2)
0x00E9
7
0
6
XFRW
0
5
0
4
MODFEN
0
3
BIDIROE
0
2
0
1
SPISWAI
0
0
SPC0
0
R
W
Reset
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 450. SPICR2 field descriptions
Field
Description
Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated
data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Refer to
Section 4.24.3.2.4, “SPI status register (SPISR)" for information about transmit/receive data handling and the interrupt flag clearing
mechanism. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
6
XFRW
(274)
0 8-bit Transfer Width (n = 8)
(274)
1 16-bit Transfer Width (n = 16)
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then
the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an
overview on the impact of the MODFEN bit on the SS port pin configuration, refer to Table 448. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
4
MODFEN
0
1
SS port pin is not used by the SPI.
SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in
bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it
controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and
force the SPI into idle state.
3
BIDIROE
0
1
Output buffer disabled.
Output buffer enabled.
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
1
0
1
SPI clock operates normally in wait mode.
Stop SPI clock generation when in wait mode.
SPISWAI
0
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 451. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
SPC0
Notes
274. n is used later in this document as a placeholder for the selected transfer width.
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Table 451. Bidirectional pin configurations
Pin Mode
SPC0
BIDIROE
MISO
MOSI
Master Mode of Operation
Normal
0
1
X
0
1
Master In
Master Out
Master In
Bidirectional
MISO not used by SPI
Master I/O
Slave Mode of Operation
Slave Out
Normal
0
1
X
0
1
Slave In
Slave In
Bidirectional
MOSI not used by SPI
Slave I/O
4.24.3.2.3
SPI baud rate register (SPIBR)
Table 452. SPI baud rate register (SPIBR)
0x00EA
7
0
6
SPPR2
0
5
SPPR1
0
4
3
0
2
SPR2
0
1
SPR1
0
0
SPR0
0
R
W
SPPR0
0
Reset
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 453. SPIBR field descriptions
Field
Description
6–4
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 454. In master mode, a change of these
bits will abort a transmission in progress and force the SPI system into idle state.
SPPR[2:0]
2–0
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 454. In master mode, a change of these bits
will abort a transmission in progress and force the SPI system into idle state.
SPR[2:0]
The baud rate divisor equation is as follows:
(SPR + 1)
BaudRateDivisor = (SPPR + 1) 2
The baud rate can be calculated with the following equation:
Eqn. 4
Eqn. 5
Baud Rate = BusClock / BaudRateDivisor
NOTE
For maximum allowed baud rates, refer to Section 3.6.2.5, “SPI timing" of this data sheet.
Table 454. Example SPI baud rate selection (25 MHz bus clock)
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Baud rate divisor
Baud rate
12.5 Mbit/s
6.25 Mbit/s
3.125 Mbit/s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
2
4
8
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Table 454. Example SPI baud rate selection (25 MHz bus clock) (continued)
SPPR2
SPPR1
SPPR0
SPR2
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SPR1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SPR0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud rate divisor
Baud rate
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
6.25 Mbit/s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
16
32
64
128
256
4
8
3.125 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
48.83 kbit/s
4.16667 Mbit/s
2.08333 Mbit/s
1.04167 Mbit/s
520.83 kbit/s
260.42 kbit/s
130.21 kbit/s
65.10 kbit/s
32.55 kbit/s
3.125 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
2.5 Mbit/s
16
32
64
128
256
512
6
12
24
48
96
192
384
768
8
16
32
64
128
256
512
1024
10
20
1.25 Mbit/s
40
625 kbit/s
80
312.5 kbit/s
156.25 kbit/s
78.13 kbit/s
39.06 kbit/s
19.53 kbit/s
160
320
640
1280
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Table 454. Example SPI baud rate selection (25 MHz bus clock) (continued)
SPPR2
SPPR1
SPPR0
SPR2
0
SPR1
0
SPR0
0
Baud rate divisor
Baud rate
2.08333 Mbit/s
1.04167 Mbit/s
520.83 kbit/s
260.42 kbit/s
130.21 kbit/s
65.10 kbit/s
32.55 kbit/s
16.28 kbit/s
1.78571 Mbit/s
892.86 kbit/s
446.43 kbit/s
223.21 kbit/s
111.61 kbit/s
55.80 kbit/s
27.90 kbit/s
13.95 kbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
12.21 kbit/s
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
12
24
0
0
1
0
1
0
48
0
1
1
96
1
0
0
192
384
768
1536
14
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
28
0
1
0
56
0
1
1
112
224
448
896
1792
16
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
32
0
1
0
64
0
1
1
128
256
512
1024
2048
1
0
0
1
0
1
1
1
0
1
1
1
4.24.3.2.4
SPI status register (SPISR)
Table 455. SPI status register (SPISR)
0x00EB
7
6
0
5
4
3
0
2
1
0
0
0
R
W
SPIF
SPTEF
MODF
0
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: Has no effect
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Table 456. SPISR field descriptions
Field
Description
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For information about clearing
SPIF Flag, refer to Table 457.
7
0
1
Transfer not yet complete.
New data copied to SPIDR.
SPIF
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For information about clearing
this bit and placing data into the transmit data register, refer to Table 458.
5
0
1
SPI data register not empty.
SPI data register empty.
SPTEF
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is
enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 4.24.3.2.2, “SPI control register 2
(SPICR2)"”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control
register 1.
4
MODF
0
1
Mode fault has not occurred.
Mode fault has occurred.
Table 457. SPIF interrupt flag clearing sequence
XFRW bit
SPIF interrupt flag clearing sequence
0
Read SPISR with SPIF == 1
then
Read SPIDRL
(275)
Byte Read SPIDRL
or
(276)
1
Read SPISR with SPIF == 1
then
Byte Read SPIDRH
Byte Read SPIDRL
or
Word Read (SPIDRH:SPIDRL)
Notes
275. Data in SPIDRH is lost, in this case.
276. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF == 1.
Table 458. SPTEF interrupt flag clearing sequence
XFRW bit
SPTEF interrupt flag clearing sequence
(277)
0
Read SPISR with SPTEF == 1
then
Write to SPIDRL
(277) (278)
Byte Write to SPIDRL
or
(277) (279)
(277)
1
Read SPISR with SPTEF == 1
then
Byte Write to SPIDRH
Byte Write to SPIDRL
or
Word Write to (SPIDRH:SPIDRL)
(277)
Notes
277. Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
278. Data in SPIDRH is undefined in this case.
279. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF
== 1.
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4.24.3.2.5
SPI data register (SPIDR = SPIDRH:SPIDRL)
Table 459. SPI data register high (SPIDRH)
0x00EC
7
6
5
4
3
2
1
R9
T9
0
0
R8
T8
0
R
W
R15
T15
0
R14
T14
0
R13
T13
0
R12
T12
0
R11
T11
0
R10
T10
0
Reset
Table 460. SPI data register low (SPIDRL)
0x00ED
7
R7
T7
0
6
R6
T6
0
5
R5
T5
0
4
R4
T4
0
3
R3
T3
0
2
R2
T2
0
1
R1
T1
0
0
R0
T0
0
R
W
Reset
Read: Anytime; read data only valid when SPIF is set
Write: Anytime
The SPI data register is both the input and output register for SPI data. A write to this register allows data to be queued and
transmitted. For an SPI configured as a master, queued data is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept
new data. Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and data has been received, the received data is transferred from the receive shift register to the SPIDR and
SPIF is set.
If SPIF is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the
receive shift register until the start of another transmission. The data in the SPIDR does not change.
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of a third transmission, the data
in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 102).
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in
the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 103).
Data A Received
Data B Received
Data C Received
SPIF Serviced
Receive Shift Register
SPIF
Data B
Data A
Data C
Data C
SPI Data Register
Data B
Data A
= Unspecified
= Reception in progress
Figure 102. Reception with SPIF serviced in time
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Data A Received
Data B Received
Data C Received
Data B Lost
SPIF Serviced
Receive Shift Register
SPIF
Data B
Data C
Data C
Data A
SPI Data Register
Data A
= Unspecified
= Reception in progress
Figure 103. Reception with SPIF serviced too late
4.24.4 Functional description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port
pins are dedicated to the SPI function as:
•
•
•
•
Slave select (SS)
Serial clock (SCK)
Master out/slave in (MOSI)
Master in/slave out (MISO)
The main element of the SPI system is the SPI data register. The n-bit(280) data register in the master and the n-bit(280) data register in the
slave are linked by the MOSI and MISO pins to form a distributed 2n-bit(280) register. When a data transfer operation is performed, this
2n-bit(280) register is serially shifted n(280) bit positions by the S-clock from the master, so data is exchanged between the master and the
slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register
after a transfer operation is the input data from the slave.
Notes
280. n depends on the selected transfer width, refer to Section 4.24.3.2.2, “SPI control register 2 (SPICR2)"
A read of SPISR with SPTEF = 1 followed by a write to SPIDR, puts data into the transmit data register. When a transfer is complete and
SPIF is cleared, received data is moved into the receive data register. This data register acts as the SPI receive data register for reads
and as the SPI transmit data register for writes. A common SPI data register address is shared for reading data from the read data buffer
and for writing data to the transmit data register.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible
clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to
accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges
(see Section 4.24.4.3, “Transmission formats").
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is
selected, when the MSTR bit is clear, slave mode is selected.
NOTE
A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will
destroy the received byte and must be avoided.
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4.24.4.1 Master mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins
by writing to the master SPI data register. If the shift register is empty, data immediately transfers to the shift register. Data begins shifting
out on the MOSI pin under the control of the serial clock.
•
Serial clock
The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection
bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is
the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0
and BIDIROE control bits.
•
•
SS pin
If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each
transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes
low, this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI
immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in
bidirectional mode). The result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in
progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE)
is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within
the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit,
CPHA, in SPI control register 1 (see Section 4.24.4.3, “Transmission formats").
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN, SPC0, or BIDIROE with SPC0
set, SPPR2-SPPR0, and SPR2-SPR0 in master mode, will abort a transmission in progress and force
the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that
the remote slave is returned to idle state.
4.24.4.2 Slave mode
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.
•
•
Serial clock
In slave mode, SCK is the SPI clock input from the master.
MISO, MOSI pins
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit
and BIDIROE bit in SPI control register 2.
•
SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain
low until the transmission is complete. If SS goes high, the SPI is forced into idle state.
The SS input also controls the serial data output pin. If SS is high (not selected), the serial data output pin is high impedance,
and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected
(SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode.
For these simpler devices, there is no serial data out pin.
NOTE
When peripherals with duplex capability are used, take care not to simultaneously enable two
receivers whose serial outputs drive the same system slave’s serial data output line.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the
same transmission from a master, although the master would not receive return information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be
latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI
shift register, depending on the LSBFE bit.
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If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered
edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on
the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is
low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the nth(281) shift, the transfer is considered
complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status
register is set.
Notes
281. n depends on the selected transfer width, refer to Section 4.24.3.2.2, “SPI control register 2 (SPICR2)"
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in
slave mode, will corrupt a transmission in progress and must be avoided.
4.24.4.3 Transmission formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock
(SCK) synchronizes shifting and sampling of the information on the two serial data lines. Aslave select line allows selection of an individual
slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave
select line can be used to indicate multiple-master bus contention.
MASTER SPI
SLAVE SPI
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SCK
SS
SCK
SS
BAUD RATE
GENERATOR
V
DD
Figure 104. Master/slave transfer block diagram
4.24.4.3.1
Clock phase and polarity controls
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock
polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase
control bit selects one of two fundamentally different transmission formats.
Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase
and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different
requirements.
4.24.4.3.2
CPHA = 0 transfer format
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the
slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this
format, the first SCK edge is issued a half cycle after SS has become low.
A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the
serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit.
After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input
pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and
shifted on even numbered edges.
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI
data register after the last bit is shifted in.
After 2n(282) (last) SCK edges:
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•
Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the
slave data register should be in the master.
•
The SPIF flag in the SPI status register is set, indicating that the transfer is complete.
Notes
282. n depends on the selected transfer width, refer to Section 4.24.3.2.2, “SPI control register 2 (SPICR2)"
Figure 105 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram
may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the
master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the
master must be either high or reconfigured as a general purpose output not affecting the SPI.
End of Idle State
Begin of Idle State
Begin
3
End
Transfer
1
2
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL
t
t
t
L
T
I
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
for t , t , t
MSB
T
l
L
t = Minimum leading time before the first SCK edge
L
t = Minimum trailing time after the last SCK edge
T
t = Minimum idling time between transfers (minimum SS high time)
I
t , t , and t are guaranteed for the master mode and required for the slave mode.
L
T
I
Figure 105. SPI Clock format 0 (CPHA = 0), with 8-bit transfer width selected (XFRW = 0)
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End of Idle State
Begin of Idle State
Begin
End
Transfer
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
SCK Edge Number
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL
MSB Bit 14Bit 13Bit 12Bit 11Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14 MSB for t , t , t
L
t
t t
I L
T
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
Minimum 1/2 SCK
T
l
t = Minimum leading time before the first SCK edge
L
t = Minimum trailing time after the last SCK edge
T
t = Minimum idling time between transfers (minimum SS high time)
I
t , t , and t are guaranteed for the master mode and required for the slave mode.
L
T
I
Figure 106. SPI clock format 0 (CPHA = 0), with 16-Bit transfer width selected (XFRW = 1)
In slave mode, if the SS line is not deasserted between the successive transmissions, then the content of the SPI data register is not
transmitted; instead the last received data is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle)
between successive transmissions, then the content of the SPI data register is transmitted.
In master mode, with slave select output enabled, the SS line is always deasserted and reasserted between successive transfers for at
least minimum idle time.
4.24.4.3.3
CPHA = 1 transfer format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data
into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the n(283)-cycle transfer operation.
Notes
283. n depends on the selected transfer width, refer to Section 4.24.3.2.2, “SPI control register 2 (SPICR2)"
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to
transfer its first data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave.
When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift
register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master
to the serial input pin on the slave.
4
This process continues for a total of n edges on the SCK line with data being latched on even numbered edges and shifting taking place
on odd numbered edges.
Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI
data register after the last bit is shifted in.
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4
After 2n SCK edges:
•
Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the
data register of the slave is in the master.
•
The SPIF flag bit in SPISR is set indicating that the transfer is complete.
Figure 107 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram, because
the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be
either high or reconfigured as a general purpose output not affecting the SPI.
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
Begin
4
End
Begin of Idle State
Transfer
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL
t
t
t
L
T
I
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
for t , t , t
MSB
T
l
L
t = Minimum leading time before the first SCK edge, not required for back-to-back transfers
L
t = Minimum trailing time after the last SCK edge
T
t = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
I
Figure 107. SPI clock format 1 (CPHA = 1), with 8-Bit transfer width selected (XFRW = 0)
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End of Idle State
Begin of Idle State
Begin
End
Transfer
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
SCK Edge Number
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
t
t t
I L
tL
T
Minimum 1/2 SCK
for t , t , t
MSB Bit 14Bit 13Bit 12Bit 11Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14 MSB
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
T
l
L
t = Minimum leading time before the first SCK edge, not required for back-to-back transfers
L
t = Minimum trailing time after the last SCK edge
T
t = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
I
Figure 108. SPI clock format 1 (CPHA = 1), with 16-Bit transfer width selected (XFRW = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in
systems having a single fixed master and a single slave that drive the MISO data line.
•
Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register, this data is sent out
immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK
edge.
4.24.4.4 SPI baud rate generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1,
and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud
rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 6.
(SPR + 1)
BaudRateDivisor = (SPPR + 1) 2
Eqn. 6
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and
the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock
divisor becomes 8, etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the
divisor is multiplied by 3, etc. See Table 454 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets
of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the
divider is disabled to decrease I current.
DD
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NOTE
For maximum allowed baud rates, refer to Section 3.6.2.5, “SPI timing" of this data sheet.
4.24.4.5 Special features
4.24.4.5.1 SS output
The SS output feature automatically drives the SS pin low during transmission, to select external devices and drives it high during idle to
deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 448.
The mode fault feature is disabled while SS output is enabled.
NOTE
Care must be taken when using the SS output feature in a multimaster system because the mode
fault feature is not available for detecting system errors between masters.
4.24.4.5.2
Bidirectional mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 461). In this mode, the SPI uses only one
serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O
(MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode
and MOSI pin in slave mode are not used by the SPI.
Table 461. Normal mode and bidirectional mode
When SPE = 1
Master mode MSTR = 1
Slave mode MSTR = 0
MOSI
MISO
Serial Out
Serial In
MOSI
MISO
Normal mode
SPC0 = 0
SPI
SPI
Serial Out
Serial In
Serial In
Serial Out
MOMI
Bidirectional mode
SPC0 = 1
BIDIROE
SPI
SPI
BIDIROE
Serial In
Serial Out
SISO
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is
driven out on the pin. The same pin is also the serial input to the shift register.
•
•
•
The SCK is output for the master mode and input for the slave mode.
The SS is the input or output for the master mode, and it is always the input for the slave mode.
The bidirectional mode does not affect SCK and SS functions.
NOTE
In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be
occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO
is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this
case, MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the
MISO pin is used for another purpose.
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4.24.4.6 Error conditions
The SPI has one error condition: Mode fault error
4.24.4.6.1
Mode fault error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying
to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register
is set automatically, provided the MODFEN bit is set.
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case,
the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a
dedicated input pin. Mode fault error doesn’t occur in slave mode.
If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO,
and MOSI pins are forced to be high-impedance inputs to avoid any possibility of conflict with another output driver. A transmission in
progress is aborted and the SPI is forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in
bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register
1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
NOTE
If a mode fault error occurs and a received data byte is pending in the receive shift register, this data
byte will be lost.
4.24.4.7 Low power mode options
4.24.4.7.1
SPI in run mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI
registers remain accessible, but clocks to the core of this module are disabled.
4.24.4.7.2
SPI in wait mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.
•
•
If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait
mode.
—
If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry.
The transmission and reception resumes when the SPI exits wait mode.
—
If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK
continues to be driven from the master. This keeps the slave synchronized to the master and the SCK.
If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with
the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to
send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each
previous master byte).
NOTE
Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even
though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt
will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be
copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode,
a received byte pending in the receive shift register will be lost when entering wait or stop mode. An
SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a transmission.
If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a
SPIDR copy will occur.
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4.24.4.7.3
SPI in stop mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in
master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop,
data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master.
The stop mode is not dependent on the SPISWAI bit.
4.24.4.7.4
Reset
The reset values of registers and signals are described in Section 4.18.3, “Memory map and register definition", which details the registers
and their bit fields.
•
If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the data last received
from the master before the reset.
•
Reading from the SPIDR after reset will always read zeros.
4.24.4.7.5
Interrupts
The 9S12I128PIMV1 only originates interrupt requests when the SPI is enabled (SPE bit in SPICR1 set). The following is a description of
how the 9S12I128PIMV1 makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt
priority are chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
4.24.4.7.5.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 448).
After MODF is set, the current transfer is aborted and the following bit is changed: MSTR = 0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active
while the MODF flag is set. MODF has an automatic clearing process which is described in Section 4.24.3.2.4, “SPI status register
(SPISR)".
4.24.4.7.5.2 SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced.
SPIF has an automatic clearing process, which is described in Section 4.24.3.2.4, “SPI status register (SPISR)".
4.24.4.7.5.3 SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has
an automatic clearing process, which is described in Section 4.24.3.2.4, “SPI status register (SPISR)".
4.25 128 kByte flash module (S12FTMRC128K1V1)
4.25.1 Introduction
The FTMRC128K1 module implements the following:
•
•
128 kbytes of P-Flash (Program Flash) memory
4.0 kbytes of D-Flash (Data Flash) memory
The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources
for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory
contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which
is written to with the command, global address, data, and any required command parameters. The memory controller must complete the
execution of a command before the FCCOB register can be written to with a new command.
CAUTION
A Flash word or phrase must be in the erased state before being programmed. Cumulative
programming of bits within a Flash word or phrase is not allowed.
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The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned
words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
It is possible to read from P-Flash memory while some commands are executing on D-Flash memory. It is not possible to read from
D-Flash memory while a command is executing on P-Flash memory. Simultaneous P-Flash and D-Flash operations are discussed in
Section 4.25.4.4, “Allowed simultaneous P-flash and D-flash operations".
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect
double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8-byte basis (a Flash
phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4-byte half-phrase containing the byte
or word accessed will be corrected.
4.25.1.1 Glossary
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash
memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased. The D-Flash sector consists of
four 64-byte rows for a total of 256-bytes.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command
execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with
each set, including 7 ECC bits for single bit fault correction and double bit fault detection within each double word.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains
512-bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device ID, Version ID, and the Program
Once field.
4.25.1.2 Features
4.25.1.2.1
P-flash features
•
•
•
•
•
•
128 kbytes of P-Flash memory composed of one 128 kbyte Flash block divided into 256 sectors of 512-bytes
Single bit fault correction and double bit fault detection within a 32-bit double word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to read the P-Flash memory while programming a word in the D-Flash memory
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
4.25.1.2.2
D-flash features
•
•
•
•
•
•
4.0 kbytes of D-Flash memory composed of one 4.0 kbyte Flash block divided into 16 sectors of 256-bytes
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Protection scheme to prevent accidental program or erase of D-Flash memory
Ability to program up to four words in a burst sequence
4.25.1.2.3
Other flash module features
•
•
•
No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory
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4.25.1.3 Block diagram
The block diagram of the Flash module is shown in Figure 109.
Command
Interrupt
Request
Flash
Interface
Registers
Protection
Security
16-bit
Error
internal
bus
Interrupt
P-Flash
32Kx39
sector 0
sector 1
Request
Bus
Clock
sector 255
Clock
Divider
FCLK
Memory
Controller
D-Flash
2Kx22
CPU
sector 0
sector 1
Scratch RAM
384x16
sector 15
Figure 109. FTMRC128K1 block diagram
4.25.2 External signal description
The Flash module contains no signals that connect off-chip.
4.25.3 Memory map and registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash
module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module.
4.25.3.1 Module memory map
The S12 architecture places the P-Flash memory between global addresses 0x2_0000 and 0x3_FFFF, as shown in Table 462.The
P-Flash memory map is shown in Figure 110.
Table 462. P-flash memory addressing
Global address
Size (bytes)
Description
P-Flash Block Contains Flash Configuration Field
(see Table 463)
0x2_0000 – 0x3_FFFF
128 k
The FPROT register, described in Section 4.25.3.2.9, “P-flash protection register (FPROT)", can be set to protect regions in the Flash
memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the
Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher
region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by
these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to
the Flash module are stored in the Flash configuration field as described in Table 463.
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Table 463. Flash configuration field
Global address
Size (bytes)
Description
Backdoor Comparison Key
0x3_FF00-0x3_FF07
8
Refer to Section 4.25.4.5.11, “Verify backdoor access key command", and Section 4.25.5.1,
“Unsecuring the MCU using backdoor key access".
(284)
0x3_FF08-0x3_FF0B
4
1
Reserved
P-Flash Protection byte
Refer to Section 4.25.3.2.9, “P-flash protection register (FPROT)".
(284)
0x3_FF0C
D-Flash Protection byte
Refer to Section 4.25.3.2.10, “D-flash protection register (DFPROT)".
(284)
0x3_FF0D
1
1
1
Flash Nonvolatile byte
Refer to Section 4.25.3.2.16, “Flash option register (FOPT)".
(284)
0x3_FF0E
Flash Security byte
Refer to Section 4.25.3.2.2, “Flash security register (FSEC)".
(284)
0x3_FF0F
Notes
284. 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B
reserved field should be programmed to 0xFF.
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P-Flash START = 0x2_0000
Flash Protected/Unprotected Region
96 kbytes
0x3_8000
0x3_8400
0x3_8800
Flash Protected/Unprotected Lower Region
1.0, 2.0, 4.0, 8.0 kbytes
0x3_9000
Protection
Fixed End
0x3_A000
0x3_C000
0x3_E000
Flash Protected/Unprotected Region
8.0 kbytes (up to 29 kbytes)
Protection
Movable End
Protection
Fixed End
Flash Protected/Unprotected Higher Region
2.0, 4.0, 8.0, 16 kbytes
0x3_F000
0x3_F800
Flash Configuration Field
16 bytes (0x3_FF00 - 0x3_FF0F)
P-Flash END = 0x3_FFFF
Figure 110. P-flash memory map
Table 464. Program IFR fields
Global Address
Size (Bytes)
Field description
0x01_8000 - 0x01_8007
0x01_8008 - 0x01_80B5
0x01_80B6 - 0x01_80B7
0x01_80B8 - 0x01_80BF
0x01_80C0 - 0x01_80FF
8
174
2
Reserved
Reserved
Version ID
Reserved
(285)
8
64
Program Once Field. Refer to Section 4.25.4.5.6, “Program once command".
Notes
285. Used to track firmware patch versions, see Section 4.25.4.2, “IFR version ID word".
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4.25.3.2 Register descriptions
The Flash module contains a set of 20 control and status registers located between 0x0100 and 0x0113. A summary of the Flash module
registers is given in Table 465 with detailed descriptions in the following subsections.
CAUTION
Writes to any Flash register must be avoided while a Flash command is active (CCIF=0) to prevent
corruption of Flash register contents and adversely affect Memory Controller behavior.
Table 465. FTMRC128K1 register summary
Address & Name
7
6
5
4
3
2
1
0
R
W
R
FDIVLD
0x0100
FCLKDIV
FDIVLCK
KEYEN0
FDIV5
RNV5
FDIV4
RNV4
FDIV3
RNV3
FDIV2
RNV2
FDIV1
SEC1
FDIV0
SEC0
KEYEN1
0x0101
FSEC
W
R
0
0
0
0
0
0
0
0
0
0
0x0102
FCCOBIX
CCOBIX2
0
CCOBIX1
0
CCOBIX0
0
W
R
0
0
0x0103
FRSV0
W
R
0
0
0
0x0104
FCNFG
CCIE
0
IGNSF
0
FDFD
FSFD
W
R
0
0
MGBUSY
0
0
RSVD
0
0x0105
FERCNFG
DFDIE
SFDIE
W
R
0
0
MGSTAT1
MGSTAT0
0x0106
FSTAT
CCIF
0
ACCERR
0
FPVIOL
0
W
R
0x0107
DFDIF
FPLS1
DPS1
SFDIF
FPLS0
DPS0
FERSTAT
W
R
RNV6
0
0x0108
FPROT
FPOPEN
DPOPEN
CCOB15
FPHDIS
0
FPHS1
0
FPHS0
DPS3
FPLDIS
DPS2
W
R
0x0109
DFPROT
W
R
0x010A
FCCOBHI
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
W
R
0x010B
FCCOBLO
CCOB7
0
CCOB6
0
CCOB5
0
CCOB4
0
CCOB3
0
CCOB2
0
CCOB1
0
CCOB0
0
W
R
0x010C
FRSV1
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x010D
FRSV2
W
R
0x010E
FRSV3
W
R
0x010F
FRSV4
W
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Table 465. FTMRC128K1 register summary (continued)
Address & Name
7
6
5
4
3
2
1
0
R
W
R
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0x0110
FOPT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0111
FRSV5
W
R
0x0112
FRSV6
W
R
0x01103
FRSV7
W
= Unimplemented or Reserved
4.25.3.2.1
Flash clock divider register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Table 466. Flash clock divider register (FCLKDIV)
Address: 0x0100
7
6
FDIVLCK
0
5
4
0
3
0
2
0
1
0
0
0
R
W
FDIVLD
FDIV[5:0]
Reset
0
0
= Unimplemented or Reserved
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field.
CAUTION
The FCLKDIV register must never be written to while a Flash command is executing (CCIF=0). The
FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear.
Table 467. FCLKDIV field descriptions
Field
Description
Clock Divider Loaded
7
0
1
FCLKDIV register has not been written since the last reset
FCLKDIV register has been written since the last reset
FDIVLD
Clock Divider Locked
6
0
1
FDIV field is open for writing
FDIVLCK
FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the
FDIV field.
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1.0 MHz to control timed events during Flash program
and erase algorithms. Table 468 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Refer to Section 4.25.4.3,
“Flash command operations", for more information.
5–0
FDIV[5:0]
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Table 468. FDIV values for various BUSCLK frequencies
BUSCLK frequency (MHz)
BUSCLK frequency (MHz)
FDIV[5:0]
FDIV[5:0]
(286)
(287)
(286)
(287)
MIN.
MAX.
MIN.
MAX.
1.0
1.6
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
16.6
17.6
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
1.6
2.6
2.6
3.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
26.6
27.6
28.6
29.6
30.6
31.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
26.6
27.6
28.6
29.6
30.6
31.6
32.6
3.6
4.6
4.6
5.6
5.6
6.6
6.6
7.6
7.6
8.6
8.6
9.6
9.6
10.6
11.6
12.6
13.6
14.6
15.6
16.6
10.6
11.6
12.6
13.6
14.6
15.6
Notes
286. BUSCLK is Greater Than this value.
287. BUSCLK is Less Than or Equal to this value.
4.25.3.2.2
Flash security register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Table 469. Flash security register (FSEC)
Address: 0x0101
7
F
6
F
5
4
F
3
F
2
F
1
F
0
F
R
W
KEYEN[1:0]
RNV[5:2]
SEC[1:0]
Reset
F
= Unimplemented or Reserved
All bits in the FSEC register are readable, but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global
address 0x3_FF0F located in P-Flash memory (see Table 463), as indicated by reset condition F in Figure 469. If a double bit fault is
detected, while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will
be set to leave the Flash module in a secured state with backdoor key access disabled.
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Table 470. FSEC field descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the Flash module as shown
in Table 471.
KEYEN[1:0]
5–2
RNV[5:2}
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
1–0
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 472. If the Flash module is unsecured
using backdoor key access, the SEC bits are forced to 10.
SEC[1:0]
Table 471. Flash KEYEN states
KEYEN[1:0]
Status of backdoor key access
00
01
10
11
DISABLED
(288)
DISABLED
ENABLED
DISABLED
Notes
288. Preferred KEYEN state to disable backdoor key access.
Table 472. Flash Security States
SEC[1:0]
Status of security
00
01
10
11
SECURED
(289)
SECURED
UNSECURED
SECURED
Notes
289. Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 4.25.5, “Security".
4.25.3.2.3
Flash CCOB index register (FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
Table 473. FCCOB index register (FCCOBIX)
Address: 0x0102
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
CCOBIX[2:0]
0
Reset
0
0
0
0
0
= Unimplemented or Reserved
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Table 474. FCCOBIX field descriptions
Field
Description
2–0
Common Command Register Index— The CCOBIX bits are used to select to which word of the FCCOB register array is being read
or written. See Section 4.25.3.2.11, “Flash common command object register (FCCOB)" for more details.
CCOBIX[1:0]
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4.25.3.2.4
Flash reserved0 register (FRSV0)
This Flash register is reserved for factory testing.
Table 475. Flash reserved0 register (FRSV0)
Address: 0x0103
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV0 register read 0 and are not writable.
4.25.3.2.5
Flash configuration register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU.
Table 476. Flash configuration register (FCNFG)
Address: 0x0104
7
CCIE
0
6
0
5
0
4
IGNSF
0
3
0
2
0
1
FDFD
0
0
FSFD
0
R
W
Reset
0
0
0
0
= Unimplemented or Reserved
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable.
Table 477. FCNFG field descriptions
Field
Description
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed.
7
0
1
Command complete interrupt disabled
An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 4.25.3.2.7, “Flash status register
(FSTAT)")
CCIE
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 4.25.3.2.8, “Flash error
status register (FERSTAT)").
4
0
1
All single bit faults detected during array reads are reported
Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated
IGNSF
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations, and
check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during
the Flash array read operation with FDFD set unless an actual double bit fault is detected.
1
0
1
Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 4.25.3.2.7, “Flash status
register (FSTAT)") and an interrupt will be generated, as long as the DFDIE interrupt enable in the FERCNFG register is set (see
Section 4.25.3.2.6, “Flash error configuration register (FERCNFG)")
FDFD
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations, and
check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The FECCR registers will not be updated during
the Flash array read operation with FSFD set unless an actual single bit fault is detected.
0
0
1
Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 4.25.3.2.7, “Flash status register
(FSTAT)"), and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 4.25.3.2.6, “Flash error configuration register (FERCNFG)")
FSFD
4.25.3.2.6
Flash error configuration register (FERCNFG)
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The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Table 478. Flash error configuration register (FERCNFG)
Address: 0x0105
7
0
6
0
5
0
4
0
3
0
2
0
1
DFDIE
0
0
SFDIE
0
R
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
All assigned bits in the FERCNFG register are readable and writable.
Table 479. FERCNFG field descriptions
Field
Description
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a
Flash block read operation.
1
0
1
DFDIF interrupt disabled
DFDIE
An interrupt will be requested whenever the DFDIF flag is set (see Section 4.25.3.2.8, “Flash error status register (FERSTAT)")
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash
block read operation.
0
0
1
SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 4.25.3.2.8, “Flash error status register (FERSTAT)")
An interrupt will be requested whenever the SFDIF flag is set (see Section 4.25.3.2.8, “Flash error status register (FERSTAT)")
SFDIE
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4.25.3.2.7
Flash status register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Table 480. Flash status register (FSTAT)
Address: 0x0106
7
CCIF
1
6
0
5
ACCERR
0
4
FPVIOL
0
3
2
1
0
R
W
MGBUSY
RSVD
MGSTAT[1:0]
(290)
(290)
Reset
0
0
0
0
0
= Unimplemented or Reserved
Notes
290. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 4.25.6, “Initialization").
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining
bits read 0 and are not writable.
Table 481. FSTAT field descriptions
Field
Description
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by
writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
7
0
1
Flash command in progress
Flash command has completed
CCIF
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a
violation of the command write sequence (see Section 4.25.4.3.2, “Command write sequence") or issuing an illegal Flash command.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR.
Writing a 0 to the ACCERR bit has no effect on ACCERR.
5
ACCERR
0
1
No access error detected
Access error detected
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected
area of P-Flash or D-Flash memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a
0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write
sequence.
4
FPVIOL
0
1
No protection violation detected
Protection violation detected
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
3
0
1
Memory Controller is idle
MGBUSY
Memory Controller is busy executing a Flash command (CCIF = 0)
2
Reserved Bit — This bit is reserved and always reads 0.
RSVD
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error is detected during
execution of a Flash command or during the Flash reset sequence. See Section 4.25.4.5, “Flash command description", and
Section 4.25.6, “Initialization", for details.
1–0
MGSTAT[1:0]
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4.25.3.2.8
Flash error status register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
Table 482. Flash error status register (FERSTAT)
Address: 0x0107
7
0
6
0
5
0
4
0
3
0
2
0
1
DFDIF
0
0
SFDIF
0
R
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
All flags in the FERSTAT register are readable and only writable to clear the flag.
Table 483. FERSTAT field descriptions
Field
Description
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity
and data bits during a Flash array read operation, or that a Flash array read operation was attempted on a Flash block that was under a
1
(291)
Flash command operation.
The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
DFDIF
0
1
No double bit fault detected
Double bit fault detected or an invalid Flash array read operation attempted
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault
was detected in the stored parity and data bits during a Flash array read operation, or that a Flash array read operation was attempted
(291)
on a Flash block that was under a Flash command operation.
has no effect on SFDIF.
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF
0
SFDIF
0
1
No single bit fault detected
Single bit fault detected and corrected or an invalid Flash array read operation attempted
Notes
291. The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double
fault but never both). A simultaneous access collision (read attempted while command running) is indicated when both SFDIF and DFDIF flags are
high.
4.25.3.2.9
P-flash protection register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
Table 484. Flash protection register (FPROT)
Address: 0x0108
7
FPOPEN
F
6
5
FPHDIS
F
4
F
3
F
2
FPLDIS
F
1
F
0
F
R
W
RNV6
FPHS[1:0]
FPLS[1:0]
Reset
F
= Unimplemented or Reserved
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased
(see Section 4.25.3.2.9.1, “P-flash protection restrictions", and Table 489).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field
at global address 0x3_FF0C located in P-Flash memory (see Table 463), as indicated by reset condition ‘F’ in Figure 484. To change the
P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the
P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash
protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave
the P-Flash memory fully protected.
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Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in
the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block
are protected.
Table 485. FPROT field descriptions
Field
Description
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown
in Table 486, for the P-Flash block.
7
0
1
When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS
and FPLS bits
When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS
and FPLS bits
FPOPEN
6
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
RNV[6]
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a
specific region of the P-Flash memory ending with global address 0x3_FFFF.
5
0
1
Protection/Unprotection enabled
Protection/Unprotection disabled
FPHDIS
4–3
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as
shown inTable 487. The FPHS bits can only be written to while the FPHDIS bit is set.
FPHS[1:0]
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a
specific region of the P-Flash memory beginning with global address 0x3_8000.
2
0
1
Protection/Unprotection enabled
Protection/Unprotection disabled
FPLDIS
1–0
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as
shown in Table 488. The FPLS bits can only be written to while the FPLDIS bit is set.
FPLS[1:0]
Table 486. P-flash protection function
(292)
FPOPEN
FPHDIS
FPLDIS
Function
No P-Flash Protection
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Protected Low Range
Protected High Range
Protected High and Low Ranges
Full P-Flash Memory Protected
Unprotected Low Range
Unprotected High Range
Unprotected High and Low Ranges
Notes
292. For range sizes, refer to Table 487 and Table 488.
Table 487. P-flash protection higher address range
FPHS[1:0]
Global address range
0x3_F800–0x3_FFFF
0x3_F000–0x3_FFFF
0x3_E000–0x3_FFFF
0x3_C000–0x3_FFFF
Protected size
2.0 kbytes
4.0 kbytes
8.0 kbytes
16 kbytes
00
01
10
11
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Table 488. P-Flash protection lower address range
FPLS[1:0]
Global address range
0x3_8000–0x3_83FF
0x3_8000–0x3_87FF
0x3_8000–0x3_8FFF
0x3_8000–0x3_9FFF
Protected size
00
01
10
11
1.0 kbyte
2.0 kbytes
4.0 kbytes
8.0 kbytes
All possible P-Flash protection scenarios are shown in Figure 111. Although the protection scheme is loaded from the Flash memory at
global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by
applications requiring reprogramming in single chip mode while providing as much protection as possible, if reprogramming is not
required.
FPHDIS = 1
FPLDIS = 1
FPHDIS = 1
FPLDIS = 0
FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
Scenario
7
6
5
4
FLASH START
0x3_8000
0x3_FFFF
Scenario
FLASH START
3
2
1
0
0x3_8000
0x3_FFFF
Protected region with size
defined by FPLS
Unprotected region
Protected region
not defined by FPLS, FPHS
Protected region with size
defined by FPHS
Figure 111. P-flash protection scenarios
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4.25.3.2.9.1 P-flash protection restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 489 specifies all valid transitions between
P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT
register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions.
Table 489. P-flash protection scenario transitions
(293)
From
To Protection Scenario
protection
scenario
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes
293. Allowed transitions marked with X, see Figure 111 for a definition of the scenarios.
4.25.3.2.10 D-flash protection register (DFPROT)
The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
Table 490. D-flash protection register (DFPROT)
Address: 0x0109
7
DPOPEN
F
6
0
5
0
4
0
3
F
2
F
1
F
0
F
R
W
DPS[3:0]
Reset
0
0
0
= Unimplemented or Reserved
The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added but not removed. Writes must
increase the DPS value and the DPOPEN bit can only be written from a 1 (protection disabled) to a 0 (protection enabled). If the DPOPEN
bit is set, the state of the DPS bits is irrelevant.
During the reset sequence, the DFPROT register is loaded with the contents of the D-Flash protection byte in the Flash configuration field
at global address 0x3_FF0D located in P-Flash memory (see Table 463) as indicated by reset condition F in Figure 490. To change the
D-Flash protection that will be loaded during the reset sequence, the P-Flash sector containing the D-Flash protection byte must be
unprotected, then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the
D-Flash memory fully protected.
Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error, and the FPVIOL bit will be set in
the FSTAT register. Block erase of the D-Flash memory is not possible if any of the D-Flash sectors are protected.
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Table 491. DFPROT field descriptions
Field
Description
D-Flash Protection Control
7
0
1
Enables D-Flash memory protection from program and erase with protected address range defined by DPS bits
Disables D-Flash memory protection from program and erase
DPOPEN
3–0
DPS[3:0]
D-Flash Protection Size — The DPS[3:0] bits determine the size of the protected area in the D-Flash memory as shown in Table 492.
Table 492. D-flash protection address range
DPS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Global address range
0x0_4400 – 0x0_44FF
0x0_4400 – 0x0_45FF
0x0_4400 – 0x0_46FF
0x0_4400 – 0x0_47FF
0x0_4400 – 0x0_48FF
0x0_4400 – 0x0_49FF
0x0_4400 – 0x0_4AFF
0x0_4400 – 0x0_4BFF
0x0_4400 – 0x0_4CFF
0x0_4400 – 0x0_4DFF
0x0_4400 – 0x0_4EFF
0x0_4400 – 0x0_4FFF
0x0_4400 – 0x0_50FF
0x0_4400 – 0x0_51FF
0x0_4400 – 0x0_52FF
0x0_4400 – 0x0_53FF
Protected size
256 bytes
512 bytes
768 bytes
1024 bytes
1280 bytes
1536 bytes
1792 bytes
2048 bytes
2304 bytes
2560 bytes
2816 bytes
3072 bytes
3328 bytes
3584 bytes
3840 bytes
4096 bytes
1000
1001
1010
1011
1100
1101
1110
1111
4.25.3.2.11 Flash common command object register (FCCOB)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are
allowed to the FCCOB register.
Table 493. Flash common command object high register (FCCOBHI)
Address: 0x010A
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
CCOB[15:8]
Reset
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Table 494. Flash common command object low register (FCCOBLO)
Address: 0x010B
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
CCOB[7:0]
Reset
4.25.3.2.11.1 FCCOB - NVM command mode
NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory
Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in
the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT
register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the
Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array.
The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 495. The return values are available for
reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter
fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000.
Table 495 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code,
followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash
command descriptions in Section 4.25.4.5, “Flash command description".
Table 495. FCCOB - NVM command mode (typical usage)
CCOBIX[2:0]
Byte
HI
FCCOB parameter fields (NVM command mode)
FCMD[7:0] defining Flash command
6’h0, Global address [17:16]
Global address [15:8]
Global address [7:0]
Data 0 [15:8]
000
LO
HI
001
010
011
100
101
LO
HI
LO
HI
Data 0 [7:0]
Data 1 [15:8]
LO
HI
Data 1 [7:0]
Data 2 [15:8]
LO
HI
Data 2 [7:0]
Data 3 [15:8]
LO
Data 3 [7:0]
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4.25.3.2.12 Flash reserved1 register (FRSV1)
This Flash register is reserved for factory testing.
Table 496. Flash reserved1 register (FRSV1)
Address: 0x010C
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV1 register read 0 and are not writable.
4.25.3.2.13 Flash reserved2 register (FRSV2)
This Flash register is reserved for factory testing.
Table 497. Flash reserved2 register (FRSV2)
Address: 0x010D
7
0
6
0
5
0
4
0
3
2
1
0
R
W
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV2 register read 0 and are not writable.
4.25.3.2.14 Flash reserved3 register (FRSV3)
This Flash register is reserved for factory testing.
Table 498. Flash reserved3 register (FRSV3)
Address: 0x010E
7
0
6
0
5
0
4
0
3
0
2
0
1
0
R
W
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV3 register read 0 and are not writable.
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4.25.3.2.15 Flash reserved4 register (FRSV4)
This Flash register is reserved for factory testing.
Table 499. Flash reserved4 register (FRSV4)
Address: 0x010F
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV4 register read 0 and are not writable.
4.25.3.2.16 Flash option register (FOPT)
The FOPT register is the Flash option register.
Table 500. Flash option register (FOPT)
Address: 0x0110
7
F
6
F
5
4
F
3
F
2
F
1
F
0
F
R
W
NV[7:0]
Reset
F
= Unimplemented or Reserved
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field, at global address
0x3_FF0E located in P-Flash memory (see Table 463), as indicated by reset condition F in Figure 500. If a double bit fault is detected
while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Table 501. FOPT field descriptions
Field
Description
7–0
NV[7:0]
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits.
4.25.3.2.17 Flash reserved5 register (FRSV5)
This Flash register is reserved for factory testing.
Table 502. Flash reserved5 register (FRSV5)
Address: 0x0111
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV5 register read 0 and are not writable.
4.25.3.2.18 Flash reserved6 register (FRSV6)
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This Flash register is reserved for factory testing.
Table 503. Flash reserved6 register (FRSV6)
Address: 0x0112
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV6 register read 0 and are not writable.
4.25.3.2.19 Flash reserved7 register (FRSV7)
This Flash register is reserved for factory testing.
Table 504. Flash reserved7 register (FRSV7)
Address: 0x0113
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
All bits in the FRSV7 register read 0 and are not writable.
4.25.4 Functional description
4.25.4.1 Modes of operation
The FTMRC128K1 module provides the modes of operation, as shown in Table 505. The operating mode is determined by module-level
inputs and affects the FCLKDIV, FCNFG, and DFPROT registers, Scratch RAM writes, and the command set availability (see Table 507).
Table 505. Modes and mode control inputs
FTMRC input
Operating mode
mmc_mode_ss_t2
Normal:
Special:
0
1
4.25.4.2 IFR version ID word
The version ID word is stored in the IFR at address 0x01_80B6. The contents of the word are defined in Table 506.
Table 506. IFR version ID fields
[15:4]
[3:0]
Reserved
VERNUM
VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’.
4.25.4.3 Flash command operations
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Flash command operations are used to modify Flash memory contents.
The next sections describe:
•
How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and
erase command operations
•
•
The command write sequence used to set Flash command parameters and launch execution
Valid Flash commands available for execution
4.25.4.3.1
Writing the FCLKDIV register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK
down to a target FCLK of 1.0 MHz. Table 468 shows recommended values for the FDIV field based on BUSCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than
0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too
low can result in incomplete programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written
since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write
sequence will not execute and the ACCERR bit in the FSTAT register will set.
4.25.4.3.2
Command write sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 4.25.3.2.7, “Flash status
register (FSTAT)") and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the
previous command write sequence is still active and a new command write sequence cannot be started, and all writes to the FCCOB
register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is active (CCIF=0) to prevent
corruption of Flash register contents and Memory Controller behavior.
4.25.4.3.2.1 Define FCCOB contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB
parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 4.25.3.2.3, “Flash CCOB index register
(FCCOBIX)").
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command
completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has
completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any
results. The flow for a generic command write sequence is shown in Figure 112.
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START
Read: FCLKDIV register
no
Clock Divider
Value Check
FDIV
Correct?
no
CCIF
Set?
Read: FSTAT register
yes
yes
Note: FCLKDIV must be
set after each reset
FCCOB
Availability Check
Read: FSTAT register
no
Write: FCLKDIV register
CCIF
Set?
yes
Results from previous Command
ACCERR/
FPVIOL
Set?
yes
Access Error and
Protection Violation
Check
Write: FSTAT register
Clear ACCERR/FPVIOL 0x30
no
Write to FCCOBIX register
to identify specific command
parameter to load.
Write to FCCOB register
to load required command parameter.
More
Parameters?
yes
no
Write: FSTAT register (to launch command)
Clear CCIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
no
CCIF Set?
yes
EXIT
Figure 112. Generic flash command write sequence flowchart
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4.25.4.3.3
Valid flash module commands
Table 507. Flash commands by mode
Unsecured
Secured
FCMD
Command
(294)
(295)
(296)
(297)
NS
SS
NS
SS
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x10
0x11
0x12
Erase Verify All Blocks
Erase Verify Block
Erase Verify P-Flash Section
Read Once
Program P-Flash
Program Once
Erase All Blocks
Erase Flash Block
Erase P-Flash Sector
Unsecure Flash
Verify Backdoor Access Key
Set User Margin Level
Set Field Margin Level
Erase Verify D-Flash Section
Program D-Flash
Erase D-Flash Sector
Notes
294. Unsecured Normal Single Chip mode.
295. Unsecured Special Single Chip mode.
296. Secured Normal Single Chip mode.
297. Secured Special Single Chip mode.
4.25.4.3.4
P-flash commands
Table 508 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources
within the Flash module.
Table 508. P-flash commands
FCMD
0x01
0x02
0x03
Command
Function on P-flash memory
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Erase Verify All Blocks
Erase Verify Block
Erase Verify P-Flash Section Verify that a given number of words starting at the address provided are erased.
Read a dedicated 64-byte field in the nonvolatile information register in P-Flash block that was previously
programmed using the Program Once command.
0x04
0x06
0x07
Read Once
Program P-Flash
Program Once
Program a phrase in a P-Flash block.
Program a dedicated 64-byte field in the nonvolatile information register in P-Flash block that is allowed to be
programmed only once.
Erase all P-Flash (and D-Flash) blocks.
0x08
Erase All Blocks
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT
register and the DPOPEN bit in the DFPROT register are set prior to launching the command.
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Table 508. P-flash commands (continued)
FCMD
Command
Function on P-flash memory
Erase a P-Flash (or D-Flash) block.
0x09
Erase Flash Block
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT
register are set prior to launching the command.
0x0A
0x0B
Erase P-Flash Sector
Unsecure Flash
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks and verifying that all
P-Flash (and D-Flash) blocks are erased.
0x0C
0x0D
0x0E
Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys.
Set User Margin Level
Set Field Margin Level
Specifies a user margin read level for all P-Flash blocks.
Specifies a field margin read level for all P-Flash blocks (special modes only).
4.25.4.3.5
D-flash commands
Table 509 summarizes the valid D-Flash commands along with the effects of the commands on the D-Flash block.
Table 509. D-flash commands
FCMD
0x01
Command
Function on D-flash memory
Verify that all D-Flash (and P-Flash) blocks are erased.
Erase Verify All Blocks
Erase Verify Block
0x02
Verify that the D-Flash block is erased.
Erase all D-Flash (and P-Flash) blocks.
0x08
Erase All Blocks
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register
and the DPOPEN bit in the DFPROT register are set prior to launching the command.
Erase a D-Flash (or P-Flash) block.
0x09
0x0B
Erase Flash Block
Unsecure Flash
An erase of the full D-Flash block is only possible when DPOPEN bit in the DFPROT register is set prior to
launching the command.
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks and verifying that all
D-Flash (and P-Flash) blocks are erased.
0x0D
0x0E
Set User Margin Level
Set Field Margin Level
Specifies a user margin read level for the D-Flash block.
Specifies a field margin read level for the D-Flash block (special modes only).
Erase Verify D-Flash
Section
0x10
Verify that a given number of words starting at the address provided are erased.
0x11
0x12
Program D-Flash
Program up to four words in the D-Flash block.
Erase all bytes in a sector of the D-Flash block.
Erase D-Flash Sector
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4.25.4.4 Allowed simultaneous P-flash and D-flash operations
Only the operations marked ‘OK’ in Table 510 are permitted to be run simultaneously on the Program Flash and Data Flash blocks. Some
operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has
been placed on permitting Program Flash reads while program and erase operations execute on the Data Flash, providing read (P-Flash)
while write (D-Flash) functionality.
Table 510. Allowed P-flash and D-flash simultaneous operations
Data flash
Margin read
Mass erase
Program flash
Read
Read
Program
Sector erase
(298)
(300)
OK
OK
OK
(298)
(299)
Margin read
OK
Program
Sector erase
OK
(300)
Mass erase
OK
Notes
298. A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin
Level’, or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified.
299. See the Note on margin settings in Section 4.25.4.5.12, “Set user margin level command" and
Section 4.25.4.5.13, “Set field margin level command".
300. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’.
4.25.4.5 Flash command description
This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT
register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be
processed by the Memory Controller:
•
•
•
Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register
Writing an invalid command as part of the command write sequence
For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data. If the
SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence
(see Section 4.25.3.2.7, “Flash status register (FSTAT)").
CAUTION
A Flash word or phrase must be in the erased state before being programmed. Cumulative
programming of bits within a Flash word or phrase is not allowed.
4.25.4.5.1
Erase verify all blocks command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 511. Erase verify all blocks command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
0x01
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space
is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed.
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Table 512. Erase verify all blocks command error handling
Register
Error bit
ACCERR
FPVIOL
Error condition
Set if CCOBIX[2:0]!= 000 at command launch
None
FSTAT
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
4.25.4.5.2
Erase verify block command
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been erased. The FCCOB upper
global address bits determine which block must be verified.
Table 513. Erase verify block command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
0x02
Global address [17:16] of the Flash block to be verified.
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or D-Flash
block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.
Table 514. Erase verify block command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 000 at command launch
ACCERR
Set if an invalid global address [17:16] is supplied
None
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
4.25.4.5.3
Erase verify P-flash section command
The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash
Section command defines the starting point of the code to be verified and the number of phrases.
Table 515. Erase verify P-flash section command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
000
001
010
0x03
Global address [17:16] of a P-Flash block
Global address [15:0] of the first phrase to be verified
Number of phrases to be verified
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash
memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed.
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Table 516. Erase verify P-flash section command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 010 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid global address [17:0] is supplied
ACCERR
Set if a misaligned phrase address is supplied (global address [2:0]!= 000)
Set if the requested section crosses a 128 kbyte boundary
None
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
4.25.4.5.4
Read once command
The Read Once command provides read access to a reserved 64-byte field (8 phrases) located in the nonvolatile information register of
P-Flash. The Read Once field is programmed using the Program Once command described in Section 4.25.4.5.6, “Program once
command". The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid
code runaway.
Table 517. Read once command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
001
010
011
100
101
0x04
Not Required
Read Once phrase index (0x0000 - 0x0007)
Read Once word 0 value
Read Once word 1 value
Read Once word 2 value
Read Once word 3 value
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The
CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from
0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid
data.
Table 518. Read once command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 001 at command launch
ACCERR
Set if command not available in current mode (see Table 507)
Set if an invalid phrase index is supplied
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
None
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
4.25.4.5.5
Program P-flash command
The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm.
CAUTION
A P-Flash phrase must be in the erased state before being programmed. Cumulative programming
of bits within a Flash phrase is not allowed.
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Table 519. Program P-flash command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
000
001
010
011
100
101
0x06
Global address [17:16] to identify P-Flash block
(301)
Global address [15:0] of phrase location to be programmed
Word 0 program value
Word 1 program value
Word 2 program value
Word 3 program value
Notes
301. Global address [2:0] must be 000
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global
address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation
has completed.
Table 520. Program P-flash command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 101 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid global address [17:0] is supplied
ACCERR
FSTAT
Set if a misaligned phrase address is supplied (global address [2:0]!= 000)
Set if the global address [17:0] points to a protected area
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
4.25.4.5.6
Program once command
The Program Once command restricts programming to a reserved 64-byte field (8 phrases) in the nonvolatile information register located
in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 4.25.4.5.4, “Read once
command". The Program Once command must only be issued once, since the nonvolatile information register in P-Flash cannot be
erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid
code runaway.
Table 521. Program once command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
001
010
011
100
101
0x07
Not Required
Program Once phrase index (0x0000 - 0x0007)
Program Once word 0 value
Program Once word 1 value
Program Once word 2 value
Program Once word 3 value
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If
erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after
the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program
one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to
0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data.
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Table 522. Program once command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 101 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid phrase index is supplied
ACCERR
(302)
FSTAT
Set if the requested phrase has already been programmed
None
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
Notes
302. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on
that same phrase.
4.25.4.5.7
Erase all blocks command
The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space.
Table 523. Erase all blocks command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x08
Not required
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify
that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During
the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
Table 524. Erase all blocks command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 000 at command launch
ACCERR
Set if command not available in current mode (see Table 507)
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
Set if any area of the P-Flash or D-Flash memory is protected
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
4.25.4.5.8
Erase flash block command
The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block.
Table 525. Erase flash block command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
Global address [17:16] to identify Flash block
Global address [15:0] in Flash block to be erased
000
001
0x09
Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that
it is erased. The CCIF flag will set after the Erase Flash Block operation has completed.
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Table 526. Erase flash block command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 001 at command launch
Set if command not available in current mode (see Table 507)
ACCERR
Set if an invalid global address [17:16] is supplied
FSTAT
Set if the supplied P-Flash address is not phrase-aligned or if the D-Flash address is not word-aligned
Set if an area of the selected Flash block is protected
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
4.25.4.5.9
Erase P-flash sector command
The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.
Table 527. Erase P-flash sector command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
Global address [17:16] to identify P-Flash
block to be erased
000
0x0A
Global address [15:0] anywhere within the sector to be erased.
Refer to Section 4.25.1.2.1, “P-flash features" for the P-Flash sector size.
001
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then
verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed.
Table 528. Erase P-flash sector command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 001 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid global address [17:16] is supplied
ACCERR
Set if a misaligned phrase address is supplied (global address [2:0]!= 000)
Set if the selected P-Flash sector is protected
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
4.25.4.5.10 Unsecure flash command
The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is successful, will release
security.
Table 529. Unsecure flash command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
0x0B
Not required
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and D-Flash memory
space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will
be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the
security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set
after the Unsecure Flash operation has completed.
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Table 530. Unsecure flash command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 000 at command launch
ACCERR
Set if command not available in current mode (see Table 507)
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
Set if any area of the P-Flash or D-Flash memory is protected
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
4.25.4.5.11 Verify backdoor access key command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 471). The
Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash
configuration field (see Table 463). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 531. Verify backdoor access key command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
001
010
011
100
0x0C
Not required
Key 0
Key 1
Key 2
Key 3
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify
that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the
command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do
not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set
ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed.
Table 532. Verify backdoor access key command Error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 100 at command launch
Set if an incorrect backdoor key is supplied
ACCERR
Set if backdoor key access has not been enabled (KEYEN[1:0]!= 10, see Section 4.25.3.2.2)
FSTAT
Set if the backdoor key has mismatched since the last reset
FPVIOL
MGSTAT1
MGSTAT0
None
None
None
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4.25.4.5.12 Set user margin level command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or
D-Flash block.
Table 533. Set user margin level command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
000
001
0x0D
Global address [17:16] to identify the Flash block
Margin level setting
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted
block and then set the CCIF flag.
NOTE
When the D-Flash block is targeted, the D-Flash user margin levels are applied only to the D-Flash
reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to
both P-Flash and D-Flash reads. It is not possible to apply user margin levels to the P-Flash block
only.
Valid margin level settings for the Set User Margin Level command are defined in Table 534.
Table 534. Valid set user margin level settings
CCOB
Level description
(CCOBIX=001)
0x0000
0x0001
0x0002
Return to Normal Level
(303)
User Margin-1 Level
(304)
User Margin-0 Level
Notes
303. Read margin to the erased state
304. Read margin to the programmed state
Table 535. Set user margin level command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 001 at command launch
Set if command not available in current mode (see Table 507)
ACCERR
Set if an invalid global address [17:16] is supplied
FSTAT
Set if an invalid margin level setting is supplied
FPVIOL
MGSTAT1
MGSTAT0
None
None
None
NOTE
User margin levels can be used to check that Flash memory contents have adequate margin for
normal level read operations. If unexpected results are encountered when checking Flash memory
contents at user margin levels, a potential loss of information has been detected.
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4.25.4.5.13 Set field margin level command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for
future read operations of the P-Flash or D-Flash block.
Table 536. Set field margin level command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
000
001
0x0E
Global address [17:16] to identify the Flash block
Margin level setting
Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted
block and then set the CCIF flag.
NOTE
When the D-Flash block is targeted, the D-Flash field margin levels are applied only to the D-Flash
reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to
both P-Flash and D-Flash reads. It is not possible to apply field margin levels to the P-Flash block
only.
Valid margin level settings for the Set Field Margin Level command are defined in Table 537.
Table 537. Valid set field margin level settings
CCOB
Level description
(CCOBIX=001)
0x0000
0x0001
0x0002
0x0003
0x0004
Return to Normal Level
(305)
User Margin-1 Level
(306)
User Margin-0 Level
(305)
Field Margin-1 Level
(306)
Field Margin-0 Level
Notes
305. Read margin to the erased state
306. Read margin to the programmed state
Table 538. Set field margin level command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 001 at command launch
Set if command not available in current mode (see Table 507)
ACCERR
Set if an invalid global address [17:16] is supplied
FSTAT
Set if an invalid margin level setting is supplied
FPVIOL
MGSTAT1
MGSTAT0
None
None
None
CAUTION
Field margin levels must only be used during verify of the initial factory programming.
NOTE
Field margin levels can be used to check that Flash memory contents have adequate margin for data
retention at the normal level setting. If unexpected results are encountered when checking Flash
memory contents at field margin levels, the Flash memory contents should be erased and
reprogrammed.
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4.25.4.5.14 Erase verify D-flash section command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased. The Erase Verify D-Flash Section
command defines the starting point of the data to be verified and the number of words.
Table 539. Erase verify D-flash section command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
001
010
0x10
Global address [17:16] to identify the D-Flash block
Global address [15:0] of the first word to be verified
Number of words to be verified
Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash
memory is erased. The CCIF flag will set after the Erase Verify D-Flash Section operation has completed.
Table 540. Erase verify D-flash section command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 010 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid global address [17:0] is supplied
ACCERR
Set if a misaligned word address is supplied (global address [0]!= 0)
Set if the requested section breaches the end of the D-Flash block
None
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
4.25.4.5.15 Program D-flash command
The Program D-Flash operation programs one to four previously erased words in the D-Flash block. The Program D-Flash operation will
confirm that the targeted location(s) were successfully programmed upon completion.
CAUTION
A Flash word must be in the erased state before being programmed. Cumulative programming of bits
within a Flash word is not allowed.
Table 541. Program D-flash command FCCOB requirements
CCOBIX[2:0]
FCCOB parameters
000
001
010
011
100
101
0x11
Global address [17:16] to identify the D-Flash block
Global address [15:0] of word to be programmed
Word 0 program value
Word 1 program value, if desired
Word 2 program value, if desired
Word 3 program value, if desired
Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred to the Memory Controller and
be programmed if the area is unprotected. The CCOBIX index value at Program D-Flash command launch determines how many words
will be programmed in the D-Flash block. The CCIF flag is set when the operation has completed.
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Table 542. Program D-flash command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0] < 010 at command launch
Set if CCOBIX[2:0] > 101 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid global address [17:0] is supplied
ACCERR
FSTAT
Set if a misaligned word address is supplied (global address [0]!= 0)
Set if the requested group of words breaches the end of the D-Flash block
Set if the selected area of the D-Flash memory is protected
FPVIOL
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
4.25.4.5.16 Erase D-flash sector command
The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash block.
Table 543. Erase D-flash sector command FCCOB requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x12
Global address [17:16] to identify D-Flash block
Global address [15:0] anywhere within the sector to be erased.
See Section 4.25.1.2.2, “D-flash features" for D-Flash sector size.
001
Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify
that it is erased. The CCIF flag will set after the Erase D-Flash Sector operation has completed.
Table 544. Erase D-flash sector command error handling
Register
Error bit
Error condition
Set if CCOBIX[2:0]!= 001 at command launch
Set if command not available in current mode (see Table 507)
Set if an invalid global address [17:0] is supplied
ACCERR
FSTAT
Set if a misaligned word address is supplied (global address [0]!= 0)
Set if the selected area of the D-Flash memory is protected
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify operation
FPVIOL
MGSTAT1
MGSTAT0
4.25.4.6 Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed, or when a Flash command operation has
detected an ECC fault.
Table 545. Flash interrupt sources
Interrupt source
Interrupt flag
Local enable
Global (CCR) Mask
Flash Command Complete
CCIF (FSTAT register)
DFDIF (FERSTAT register)
SFDIF (FERSTAT register)
CCIE (FCNFG register)
DFDIE (FERCNFG register)
SFDIE (FERCNFG register)
I Bit
I Bit
I Bit
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
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NOTE
Vector addresses and their relative interrupt priority are determined at the MCU level.
4.25.4.6.1
Description of flash interrupt operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request.
The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash
error interrupt request. For a detailed description of the register bits involved, refer to Section 4.25.3.2.5, “Flash configuration register
(FCNFG)", Section 4.25.3.2.6, “Flash error configuration register (FERCNFG)", Section 4.25.3.2.7, “Flash status register (FSTAT)", and
Section 4.25.3.2.8, “Flash error status register (FERSTAT)".
The logic used for generating the Flash module interrupts is shown in Figure 113.
Flash Command Interrupt Request
Flash Error Interrupt Request
CCIE
CCIF
DFDIE
DFDIF
SFDIE
SFDIF
Figure 113. Flash module interrupts implementation
4.25.4.7 Wait mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt
(see Section 4.25.4.6, “Interrupts").
4.25.4.8 Stop mode
If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the
CPU is allowed to enter stop mode.
4.25.5 Security
The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see
Table 472). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration
field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte, assuming
that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available, and that the upper region
of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
•
•
•
Unsecuring the MCU using backdoor key access
Unsecuring the MCU in special single chip mode using BDM
Mode and security effects on flash command availability
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4.25.5.1 Unsecuring the MCU using backdoor key access
The MCU may be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the backdoor keys
(four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see
Section 4.25.3.2.2, “Flash security register (FSEC)"), the Verify Backdoor Access Key command (see Section 4.25.4.5.11, “Verify
backdoor access key command") allows the user to present four prospective keys for comparison to the keys stored in the Flash memory
via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash
memory, the SEC bits in the FSEC register (see Table 472) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are
not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory, and D-Flash memory will
not be available for read access and will return invalid data.
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external
stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 4.25.3.2.2, “Flash security register (FSEC)"), the MCU can be unsecured by
the backdoor key access sequence described below:
1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 4.25.4.5.11, “Verify
backdoor access key command"
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are
forced to the unsecure state of 10
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify
Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The
security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence.
The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence.
The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection
register, FPROT.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the
Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure
state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash
configuration field.
4.25.5.2 Unsecuring the MCU in special single chip mode using BDM
A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and D-Flash memory:
1. Reset the MCU into special single chip mode
2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and D-Flash
memories are erased
3. Send BDM commands to disable protection in the P-Flash and D-Flash memory
4. Execute the Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory
5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip
mode
6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and D-Flash
memory are erased
If the P-Flash and D-Flash memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the
Flash security byte may be programmed to the unsecure state by continuing with the following steps:
7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the
unsecured state
8. Reset the MCU
4.25.5.3 Mode and security effects on flash command availability
The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 507.
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4.25.6 Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the Flash Block Configuration
Parameters, the FPROT and DFPROT protection registers, and the FOPT and FSEC registers. The Flash module reverts to using built-in
default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset
sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the initial portion of the reset sequence.
While Flash memory reads and access to most Flash registers are possible when the hold is removed, writes to the FCCOBIX, FCCOBHI,
and FCCOBLO registers are ignored. Completion of the reset sequence is marked by setting CCIF high which enables writes to the
FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being
programmed or the sector/block being erased is not guaranteed.
4.26 MCU - die-to-die initiator (9S12I128PIMV1)
4.26.0.1 Acronyms and abbreviations
Table 546 contains sample acronyms and abbreviations used in this document.
Table 546. Acronyms and abbreviated terms
Term
Meaning
D2D
Die-to-Die
4.26.0.1.1
Glossary
Table 313 shows a glossary of the major terms used in this document.
Table 547. Glossary
Term
Definition
Active low
Active high
Asserted
Customer
EOT
The signal is asserted when it changes to logic-level zero.
The signal is asserted when it changes to logic-level one.
Discrete signal is in active logic state.
The end user of an SoC design or device.
End of Transaction
Negated
Pin
A discrete signal is in inactive logic state.
External physical connection.
Revision
Signal
Revised or new version of a document. Revisions produce versions; there can be no ‘Rev 0.0.’
Electronic construct whose state or change in state conveys information.
Transfer
Transaction
Version
A read or write on the CPU bus following the IP-Bus protocol.
Command, address and if required data sent on the D2D interface. A transaction is finished by the EOT acknowledge cycle.
Particular form or variation of an earlier or original document.
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4.26.1 Introduction
This section describes the functionality of the die-to-die (9S12I128PIMV1) initiator block especially designed for low cost connections
between a microcontroller die (Interface Initiator) and an analog die (Interface Target) located in the same package.
The D2DI block
•
•
•
realizes the initiator part of the D2D interface, including supervision and error interrupt generation
generates the clock for this interface
disables/enables the interrupt from the D2D interface
4.26.1.1 Overview
The D2DI is the initiator for a data transfer to and from a target, typically located on another die in the same package. It provides a set of
configuration registers and two memory mapped 256 Byte address windows. When writing to a window a transaction is initiated, sending
a write command followed, by an 8-bit address and the data byte or word to the target. When reading from a window, a transaction is
initiated, sending a read command, followed by an 8-bit address to the target. The target then responds with the data. The basic idea is
that a peripheral located on another die, can be addressed like an on-chip peripheral, except for a small transaction delay.
D2DCW
Address Bus
Write Data Bus
Read Data Bus
D2DDAT[7:0]
D2DINT
D2DIF
D2DINTI
D2DERR_INT
D2DIE
xfr_wait
D2DCLKDIV
/n
Bus Clock
D2DCLK
n=1 … 8
Figure 114. Die-to-die initiator (D2DI) block diagram
4.26.1.2 Features
The main features of this block are
•
Software transparent, memory mapped access to peripherals on target die
—
—
256 Byte address window
Supports blocking read or write as well as non-blocking write transactions
•
•
•
•
•
•
•
Scalable interface clock divide by 1, 2, 3 and 4 of bus clock
Clock halt on system STOP
Configurable for 4- or 8-bit wide transfers
Configurable timeout period
Non-maskable interrupt on transaction errors
Transaction Status and Error Flags
Interrupt enable for receiving interrupt (from D2D target)
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4.26.1.3 Modes of operation
4.26.1.3.1
D2DI in STOP/WAIT mode
The D2DI stops working in STOP/WAIT mode. The D2DCLK signal as well as the data signals used are driven low (only after the end of
the current high phase, as defined by D2DCLKDIV).
Waking from STOP/WAIT mode, the D2DCLK line starts clocking again and the data lines will be driven low until the first transaction starts.
STOP and WAIT mode are entered by different CPU instructions. In the WAIT mode the behavior of the D2DI can be configured
(D2DSWAI). Every (enabled) interrupt can be used to leave the STOP and WAIT mode.
4.26.1.3.2
D2DI in special modes
The MCU can enter a special mode (used for test and debugging purposes as well as programming the FLASH). In the D2DI, the
“write-once” feature is disabled. See the MCU description for details.
4.26.2 External signal description
The D2DI optionally uses 6 or 10 port pins. The functions of those pins depends on the settings in the D2DCTL0 register, when the D2DI
module is enabled.
4.26.2.1 D2DCLK
When the D2DI is enabled, this pin is the clock output. This signal is low if the initiator is disabled, in STOP mode or in WAIT mode (with
D2DSWAI asserted), otherwise it is a continuos clock. This pin may be shared with general purpose functionality if the D2DI is disabled.
4.26.2.2 D2DDAT[7:4]
When the D2DI is enabled and the interface connection width D2DCW is set to be 8-bit wide, those lines carry the data bits 7:4 acting as
outputs or inputs. When they act as inputs pull-down elements are enabled. If the D2DI is disabled or if the interface connection width is
set as 4-bit wide, the pins may be shared with general purpose pin functionality.
4.26.2.3 D2DDAT[3:0]
When the D2DI is enabled those lines carry the data bits 3:0 acting as outputs or inputs. When they act as inputs pull-down elements are
enabled. If the D2DI is disabled the pins and may be shared with general purpose pin functionality.
4.26.2.4 D2DINT
The D2DINT is an active input interrupt input driven by the target device. The pin has an active pull-down device. If the D2DI is disabled,
the pin may be shared with general purpose pin functionality.
Table 548. Signal properties
Secondary
Name
Primary (D2DEN=1)
I/O
Reset
Comment
Pull down
(D2DEN=0)
(307)
D2DDAT[7:0]
D2DCLK
Bidirectional Data Lines
Interface Clock Signal
Active High Interrupt
I/O GPIO
0
0
driven low if in STOP mode
low if in STOP mode
—
Active
O
I
GPIO
GPIO
—
(308)
D2DINT
—
Active
Notes
307. Active if in input state, only if D2DEN=1
308. only if D2DEN=1
See the port interface module (PIM) guide for details of the GPIO function.
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4.26.3 Memory map and register definition
4.26.3.1 Memory map
The D2DI memory map is split into three sections.
1. An eight byte set of control registers
2. A 256 byte window for blocking transactions
3. A 256 byte window for non-blocking transactions
See the chapter “Device Memory Map” for the register layout (distribution of these sections).
D2DREGS
8 Byte Control
Registers
D2DBLK
256 Byte Window
Blocking Access
D2DNBLK
256 Byte Window
Non-blocking Write
Figure 115. D2DI top level memory map
A summary of the registers associated with the D2DI block is shown in Table 549. Detailed descriptions of the registers and bits are given
in the subsections that follow.
Table 549. D2DI register summary
Offset
Register name
Bit 7
6
D2DCW
0
5
D2DSWAI
0
4
3
2
1
Bit 0
0x0
R
0
0
0
D2DCTL0
D2DEN
D2DCLKDIV[1:0]
W
0x1
0x2
0x3
0x4
0x5
0x6
0x7
D2DCTL1
0
D2DIE
ERRIF
TIMEOUT[3:0]
R
ACKERF
D2DBSY
SZ8
CNCLF
TIMEF
0
TERRF
PARF
PAR1
PAR0
D2DSTAT0
D2DSTAT1
W
0
0
0
0
0
0
0
0
D2DIF
RWB
R
W
R
NBLK
0
0
D2DADRHI
D2DADRLO
D2DDATAHI
D2DDATALO
ADR[7:0]
W
R
DATA[15:8]
DATA[7:0]
W
R
W
= Unimplemented or Reserved
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4.26.3.2 Register definition
4.26.3.3 D2DI control register 0 (D2DCTL0)
This register is used to enable and configure the interface width, the wait behavior and the frequency of the interface clock.
Table 550. D2DI control register 0 (D2DCTL0)
Offset
Access: User read/write
1 0
0x0
7
D2DEN
0
6
D2DCW
0
5
D2DSWAI
0
4
0
3
0
2
0
R
D2DCLKDIV[1:0]
W
Reset
0
0
0
0
0
Table 551. D2DCTL0 register field descriptions
Field
Description
D2DI Enable — Enables the D2DI module. This bit is write-once in normal mode and can always be written in special modes.
7
0
1
D2DI initiator is disabled. No lines are not used, the pins have their GPIO (secondary) function.
D2DI initiator is enabled. After setting D2DEN=1 the D2DDAT[7:0] (or [3:0], see D2DCW) lines are driven low with the IDLE command;
the D2DCLK is driven by the divided bus clock.
D2DEN
D2D Connection Width — Sets the number of data lines used by the interface. This bit is write-once in normal modes and can always
be written in special modes.
6
0
1
Lines D2DDAT[3:0] are used for four line data transfer. D2DDAT[7:4] are unused.
All eight interface lines D2DDAT[7:0] are used for data transfer.
D2DCW
D2D Stop In Wait — Controls the WAIT behavior. This bit can be written at any time.
5
0
1
Interface clock continues to run if the CPU enters WAIT mode
Interface clock stops if the CPU enters WAIT mode.
D2DSWAI
4:2
Reserved, should be written to 0 to ensure compatibility with future versions of this interface.
Interface Clock Divider — Determines the frequency of the interface clock. These bits are write-once in normal modes and can be
always written in special modes. See Figure 116 for details on the clock waveforms
00 Encoding 0. Bus clock divide by 1.
01 Encoding 1. Bus clock divide by 2.
10 Encoding 2. Bus clock divide by 3.
11 Encoding 3. Bus clock divide by 4.
1:0
D2DCLKDIV
The Clock Divider will provide the waveforms as shown in Figure 116. The duty cycle of the clock is not always 50%, the high cycle is
shorter than 50% or equal but never longer, since this is beneficial for the transaction speed.
bus clock
00
01
10
11
Figure 116. Interface clock waveforms for various D2DCLKDIV encoding
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4.26.3.4 D2DI control register 1 (D2DCTL1)
This register is used to enable the D2DI interrupt and set number of D2DCLK cycles before a timeout error is asserted.
Table 552. D2DI control register 1 (D2DCTL1)
Offset
Access: User read/write
0
0x1
7
D2DIE
0
6
0
5
0
4
0
3
0
2
0
1
0
R
TIMOUT[3:0]
W
Reset
0
0
0
0
Table 553. D2DCTL1 register field descriptions
Field
Description
D2D Interrupt Enable — Enables the external interrupt
7
0
1
External Interrupt is disabled
External Interrupt is enabled
D2DIE
6:4
Reserved, should be written to 0 to ensure compatibility with future versions of this interface.
Time-out Setting — Defines the number of D2DCLK cycles to wait after the last transaction cycle until a timeout is asserted. In case of a
timeout the TIMEF flag in the D2DSTAT0 register will be set.
These bits are write-once in normal modes and can always be written in special modes.
0000 The acknowledge is expected directly after the last transfer, i.e. the target must not insert a wait cycle.
0001 - 1111: The target may insert up to TIMOUT wait states before acknowledging a transaction until a timeout is asserted
3:0
TIMOUT
NOTE
“Write-once” means that after writing D2DCNTL0.D2DEN=1 the write accesses to these bits have no
effect.
4.26.3.5 D2DI status register 0 (D2DSTAT0)
This register reflects the status of the D2DI transactions.
Table 554. D2DI status register 0 (D2DSTAT0)
Offset
Access: User read/write
1 0
0x2
7
ERRIF
0
6
5
4
3
2
R
ACKERF
CNCLF
TIMEF
TERRF
PARF
PAR1
PAR0
W
Reset
0
0
0
0
0
0
0
Table 555. D2DI status register 0 field descriptions
Field
Description
D2DI error interrupt flag — This status bit indicates that the D2D initiator has detected an error condition (summary of the following five
flags).This interrupt is not locally maskable. Write a 1 to clear the flag. Writing a 0 has no effect.
7
0
1
D2DI has not detected an error during a transaction.
D2DI has detected an error during a transaction.
ERRIF
6
Acknowledge Error Flag— This read-only flag indicates that in the acknowledge cycle not all data inputs are sampled high, indicating a
potential broken wire. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
ACKERF
5
CNCLF — This read-only flag indicates the initiator has canceled a transaction and replaced it by an IDLE command due to a pending error
flag (ERRIF). This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
CNCLF
4
Time Out Error Flag — This read-only flag indicates the initiator has detected a time-out error. This flag is cleared when the ERRIF bit is
cleared by writing a 1 to the ERRIF bit.
TIMEF
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Table 555. D2DI status register 0 field descriptions (continued)
Field
Description
3
Transaction Error Flag — This read-only flag indicates the initiator has detected the error signal during the acknowledge cycle of the
transaction. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
TERRF
2
Parity Error Flag — This read-only flag indicates the initiator has detected a parity error. Parity bits[1:0] contain further information. This flag
is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
PARF
1
Parity Bit — P[1] as received by the D2DI
Parity Bit — P[0] as received by the D2DI
PAR1
0
PAR0
4.26.3.6 D2DI status register 1 (D2DSTAT1)
This register holds the status of the external interrupt pin and an indicator about the D2DI transaction status.
Table 556. D2DI status register 1 (D2DSTAT1)
Offset
Access: User read
0x3
7
D2DIF
0
6
5
0
4
0
3
0
2
0
1
0
0
0
R
D2DBSY
W
Reset
0
0
0
0
0
0
0
Table 557. D2DSTAT1 register field descriptions
Field
Description
D2D Interrupt Flag — This read-only flag reflects the status of the D2DINT Pin. The D2D interrupt flag can only be cleared by a target specific
interrupt acknowledge sequence.
7
0
1
External Interrupt is negated
External Interrupt is asserted
D2DIF
D2D Initiator Busy — This read-only status bit indicates that a D2D transaction is ongoing.
6
0
1
D2D initiator idle.
D2D initiator transaction ongoing.
D2DBSY
5:0
Reserved, should be masked to ensure compatibility with future versions of this interface.
4.26.3.7 D2DI address buffer register (D2DADR)
This read-only register contains information about the ongoing D2D interface transaction. The register content will be updated when a new
transaction starts. In error cases the user can track back, which transaction failed.
Table 558. D2DI address buffer register (D2DADR)
Offset
Access: User read
0x4/0x5
15
14
13
0
12
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
0
1
0
0
0
R
RWB
SZ8
NBLK
ADR[7:0]
W
0
0
0
0
0
0
0
0
0
0
Reset
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Table 559. D2DI address buffer register bit descriptions
Field
Description
Transaction Read-Write Direction — This read-only bit reflects the direction of the transaction
15
RWB
0
1
Write Transaction
Read Transaction
Transaction Size — This read-only bit reflects the data size of the transaction
14
SZ8
0
1
16-bit transaction.
8-bit transaction.
13
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Mode — This read-only bit reflects the mode of the transaction
12
NBLK
0
1
Blocking transaction.
Non-blocking transaction.
11:8
Reserved, should be masked to ensure compatibility with future versions of this interface.
7:0
ADR[7:0]
Transaction Address — Those read-only bits contain the address of the transaction
4.26.3.8 D2DI data buffer register (D2DDATA)
This read-only register contains information about the ongoing D2D interface transaction. For a write transaction, the data becomes valid
at the begin of the transaction. For a read transaction, the data will be updated during the transaction and is finalized when the transaction
is acknowledged by the target. In error cases, the user can track back what has happened.
Table 560. D2DI data buffer register (D2DDATA)
Offset
Access: User read
0x6/0x7
15
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
DATA15:0
W
0
0
0
Reset
Table 561. D2DI data buffer register bit descriptions
Field
Description
15:0
DATA
Transaction Data — Those read-only bits contain the data of the transaction
Both D2DDATA and D2DADR can be read with byte accesses.
4.26.4 Functional description
4.26.4.1 Initialization
Out of reset the interface is disabled. The interface must be initialized by setting the interface clock speed, the timeout value, the transfer
width and finally enabling the interface. This should be done using a 16-bit write or if using 8-bit write D2DCTL1 must be written before
D2D2CTL0.D2DEN=1 is written. Once it is enabled in normal modes, only a reset can disable it again (write-once feature).
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4.26.4.2 Transactions
A transaction on the D2D Interface is triggered by writing to either the 256 byte address window or reading from the address window (see
STAA/LDAA 0/1 in the next figure). Depending on which address window is used, a blocking or a non-blocking transaction is performed.
The address for the transaction is the 8-bit wide window relative address. The data width of the CPU read or write instructions determines
if 8-bit or 16-bit wide data are transferred. There is always only one transaction active. Figure 117 shows the various types of transactions
explained in more detail below.
For all 16-bit read/write accesses of the CPU the addresses are assigned according the big-endian model:
word [15:8]: addr
word[7:0]: addr+1
addr: byte-address (8 bit wide) inside the blocking or non-blocking window, as provided by the CPU and transferred to the D2D target
word: CPU data, to be transferred from/to the D2D target
The application must care for the stretched CPU cycles (limited by the TIMOUT value, caused by blocking or consecutive accesses), which
could affect time limits, including COP (computer operates properly) supervision. The stretched CPU cycles cause the “CPU halted”
phases (see Figure 117).
CPU activity
D2D activity
STAA 0
CPU Halted
LDAA # STAA 1
CPU Halted
NOP
Blocking
Write
Write Transaction 0
Write Transaction 1
CPU activity
CPU
STAA 0 LDAA # STAA 1
NOP
Write Transaction 1
Halted
Non-Blocking
Write
Write Transaction 0
D2D activity
CPU activity
D2D activity
STAA
MEM
LDAA 0
CPU Halted
Transaction 0
LDAA 1
CPU Halted
NOP
Blocking
Read
Transaction 1
Figure 117. Blocking and non-blocking transfers.
4.26.4.2.1
Blocking writes
When writing to the address window associated with blocking transactions, the CPU is held until the transaction is completed, before
completing the instruction. Figure 117 shows the behavior of the CPU for a blocking write transaction shown in the following example.
STAA
LDAA
STAA
NOP
BLK_WINDOW+OFFS0; WRITE0 8-bit as a blocking transaction
#BYTE1
BLK_WINDOW+OFFS1 ; WRITE1 is executed after WRITE0 transaction is completed
Blocking writes should be used when clearing interrupt flags, located in the target or other writes which require that the operation at the
target, is completed before proceeding with the CPU instruction stream.
4.26.4.3 Non-blocking writes
When writing to the address window associated with non-blocking transactions, the CPU can continue before the transaction is completed.
However, if there was an ongoing transaction when doing the 2nd write, the CPU is held until the first one is completed, and before
executing the 2nd one. Figure 117 shows the behavior of the CPU for a blocking write transaction shown in the following example.
STAA
LDAA
STAA
NOP
NONBLK_WINDOW+OFFS0; write 8-bit as a blocking transaction
#BYTE1 ; load next byte
NONBLK_WINDOW+OFFS1; executed right after the first
As the figure illustrates, non-blocking writes have a performance advantage, but care must be taken that the following instructions are not
affected by the change in the target caused by the previous transaction.
4.26.4.4 Blocking read
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When reading from the address window associated with blocking transactions, the CPU is held until the data is returned from the target,
before completing the instruction. Figure 117 shows the behavior of the CPU for a blocking read transaction shown in the following
example.
LDAA
STAA
LDAA
BLK_WINDOW+OFFS0; Read 8-bit as a blocking transaction
MEM ; Store result to local Memory
BLK_WINDOW+OFFS1; Read 8-bit as a blocking transaction
4.26.4.5 Non-blocking read
Read access to the non-blocking window is reserved for future use. When reading from the address window associated with non-blocking
writes, the read returns an all 0s data byte or word. This behavior can change in future revisions.
4.26.4.6 Transfer width
8-bit wide writes or reads are translated into 8-bit wide interface transactions. 16-bit wide, aligned writes or reads are translated into a16-bit
wide interface transactions. 16-bit wide, misaligned writes or reads are split up into two consecutive 8-bit transactions with the transaction
on the odd address first followed by the transaction on the next higher even address. Due to the much more complex error handling (by
the MCU), misaligned 16-bit transfers should be avoided.
4.26.4.7 Error conditions and handling faults
Since the S12 CPU (as well as the S08) does not provide a method to abort a transfer once started, the D2DI asserts a D2DERRINT. The
ERRIF Flag is set in the D2DSTAT0 register. Depending on the error condition, further error flags will be set, as described below. The
content of the address and data buffers are frozen and all transactions will be replaced by an IDLE command, until the error flag is cleared.
If an error is detected during the read transaction of a read-modify-write instruction, or a non-blocking write transaction was followed by
another write or read transaction, the second transaction is cancelled. The CNCLF is set in the D2DSTAT0 register to indicate that a
transaction has been cancelled. The D2DERRINT handler can read the address and data buffer register to assess the error situation. Any
further transaction will be replaced by IDLE until the ERRIF is cleared.
4.26.4.7.1
Missing acknowledge
If the target detects a wrong command, it will not send back an acknowledge. The same situation occurs if the acknowledge is corrupted.
The D2DI detects this missing acknowledge after the timeout period configured in the TIMOUT parameter of the D2DCTL1 register. In
case of a timeout, the ERRIF and the TIMEF flags in the D2DSTAT0 register will be set.
4.26.4.7.2
Parity error
In the final acknowledge cycle of a transaction, the target sends two parity bits. If this parity does not match the parity calculated by the
initiator, the ERRIF and the PARF flags in the D2DSTAT0 register will be set. The PAR[1:0] bits contain the parity value received by the
D2DI.
4.26.4.7.3
Error signal
During the acknowledge cycle the target can signal a target specific error condition. If the D2DI finds the error signal asserted during a
transaction, the ERRIF and the TERRF flags in the D2DSTAT0 register will be set.
4.26.4.8 Low power mode options
4.26.4.8.1
D2DI in run mode
In run mode, with the D2D Interface enable (D2DEN) bit in the D2D control register 0 clear, the D2DI system is in a low-power, disabled
state. D2D registers remain accessible, but clocks to the core of this module are disabled. On D2D lines the GPIO function is activated.
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4.26.4.8.2
D2DI in wait mode
D2DI operation in wait mode depends upon the state of the D2DSWAI bit in D2D control register 0.
•
•
If D2DSWAI is clear, the D2DI operates normally when the CPU is in the wait mode
If D2DSWAI is set and the CPU enters the wait mode, any pending transmission is completed. When the D2DCLK output is
driven low then the clock generation is stopped, all internal clocks to the D2DI module are stopped as well and the module enters
a power saving state.
4.26.4.8.3
D2DI in stop mode
If the CPU enters the STOP mode, the D2DI shows the same behavior as for the wait mode with an activated D2DSWAI bit.
4.26.4.8.4
Reset
In case of reset any transaction is immediately stopped and the D2DI module is disabled.
4.26.4.8.5
Interrupts
The D2DI only originates interrupt requests when D2DI is enabled (D2DIE bit in D2DCTL0 set). There are two different interrupt requests
from the D2D module. The interrupt vector offset and interrupt priority are chip dependent.
4.26.4.8.5.1 D2D external interrupt
This is a level sensitive active high external interrupt driven by the D2DINT input. This interrupt is enabled if the D2DIE bit in the D2DCTL1
register is set. The interrupt must be cleared using an target specific clearing sequence. The status of the D2D input pin can be observed
by reading the D2DIF bit in the D2DSTAT1 register.
The D2DINIT signal is also asserted in the wait and stop mode; it can be used to leave these modes.
To read data bus (D2DSTAT1.D2DIF)
D2DINTI
D2DINT
D2DIE
Figure 118. D2D external interrupt scheme
4.26.4.8.5.2 D2D error interrupt
Those D2D interface specific interrupts are level sensitive and are all cleared by writing a 1 to the ERRIF flag in the D2DSTAT0 register.
This interrupt is not locally maskable and should be tied to the highest possible interrupt level in the system, on an S12 architecture to the
XIRQ. See the chapter “Vectors” of the MCU description for details.
ACKERF
CNCLF
ERRIF
1
TIMEF
TERRF
PARF
D2DERRINT
D2DEN
Figure 119. D2D internal interrupts
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4.26.5 Initialization information
During initialization, the transfer width, clock divider, and timeout value must be set according to the capabilities of the target device before
starting any transaction. See the D2D Target specification for details.
4.26.6 Application information
4.26.6.1 Entering low-power mode
The D2DI module is typically used on a microcontroller along with an analog companion device containing the D2D target interface and
supplying the power. Interface specification does not provide special wires for signalling low power modes to the target device. The CPU
should determine when it is time to enter one of the above power modes.The basic flow is as follows:
1. CPU determines there is no more work pending.
2. CPU writes a byte to a register on the analog die using blocking write configuring which mode to enter.
3. Analog die acknowledges that write sending back an acknowledge symbol on the interface.
4. CPU executes WAIT or STOP command.
5. Analog die can enter low power mode - (S12 needs some more cycles to stack data!)
; Example shows S12 code
SEI
; disable interrupts during test
; check is there is work pending?
; if yes, branch off and re-enable interrupt
; else
LDAA
STAA
CLI
#STOP_ENTRY
MODE_REG
; re-enable right before the STOP instruction
; stack and turn off all clocks inc. interface clock
; store to the analog die mode reg (use blocking write here)
STOP
For wake-up from STOP the basic flow is as follows:
1. Analog die detects a wake-up condition e.g. on a switch input or start bit of a LIN message.
2. Analog die exits Voltage Regulator low power mode.
3. Analog die asserts the interrupt signal D2DINT.
4. CPU starts clock generation.
5. CPU enters interrupt handler routine.
6. CPU services interrupt and acknowledges the source on the analog die.
NOTE
Entering STOP mode or WAIT mode with D2DSWAI asserted, the clock will complete the high duty
cycle portion and settle at a low level.
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5
MM912_637 - trimming
5.1
Introduction
To ensure the high precision requirements over a wide temperature and lifetime range, the MM912_637 uses several trimming and
calibration techniques. Due to the advantage of the FLASH technology available in the microcontroller die, several factory trimmed values
can be used to increase the overall device accuracy.
Trimming will use factory measured and calculated values stored in the microcontroller IFR (Information Register) to be loaded into
specific registers in the MCU and analog die at system power up.
Calibration would be done during operation of the system using internal references or specific measurement procedures. As calibration
is an essential part of the signal acquisition, see Section 4.8.5, “Calibration" as part of Section 4.8, “Channel acquisition".
NOTE
The MM912_637 trimming is primarily used to achieve the specified analog die parameters. The only
valid trimming of the MCU die, the Internal Oscillator Trimming (ICG) will be automatically stored into
the MCU trimming register during power up. See Section 4.23.3.2.15, “9S12I128PIMV1 IRC1M trim
registers (CPMUIRCTRIMH / CPMUIRCTRIML)".
5.2
IFR trimming content and location
All device trimming information are stored in the MCU Information Register (IFR) located at the following address. See also Section 4.25,
“128 kByte flash module (S12FTMRC128K1V1)".
Table 562. IFR location
Global address
Size (bytes)
Field description
0x01_8000 - 0x01_8007
0x01_8008 - 0x01_80B5
0x01_80B6 - 0x01_80B7
0x01_80B8 - 0x01_80BF
0x01_80C0 - 0x01_80FF
8
174
2
Unique Device ID
Reserved
(309)
Version ID
8
Reserved
64
Analog Die Trimming Information (Program Once Field)
Notes
309. Used to track firmware patch versions, see Section 4.25.4.2, “IFR version ID word".
NOTE
The Program Once reserved field can be read using the Read Once command as described in
Section 4.25.4.5.4, “Read once command".
5.2.1
IFR - trimming content for analog die functionality
The following table shows the details of the 64 byte (0x01_80C0 - 0x01_80FF) Program Once Field Content used to store the Analog Die
Trimming Information. Refer to Section 4.25.4.5.4, “Read once command", for access instructions.
Table 563. Analog die trimming information
OFFSET
Byte description
Target register
Name
Global
address
HEX
DEC
00
7
6
5
4
3
2
1
0
Offset
0x01_80C0
0x01_80C1
0x01_80C2
0x01_80C3
00
01
02
03
IGC4[9:8]
COMP_IG4 (hi)
0xB0
01
IGC4[7:0]
IGC8[7:0]
COMP_IG4 (lo)
COMP_IG8 (hi)
COMP_IG8 (lo)
02
IGC8[9:8]
0xB2
03
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Table 563. Analog die trimming information (continued)
OFFSET
HEX
Byte description
Target register
Global
address
DEC
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
7
6
5
4
3
2
1
0
Name
COMP_IG16 (hi)
COMP_IG16 (lo)
COMP_IG32 (hi)
COMP_IG32 (lo)
COMP_IG64 (hi)
COMP_IG64 (lo)
COMP_IG128 (hi)
COMP_IG128 (lo)
COMP_IG256 (hi)
COMP_IG256 (lo)
COMP_IG512 (hi)
COMP_IG512 (lo)
TRIM_BG0 (hi)
Offset
0x01_80C4
0x01_80C5
0x01_80C6
0x01_80C7
0x01_80C8
0x01_80C9
0x01_80CA
0x01_80CB
0x01_80CC
0x01_80CD
0x01_80CE
0x01_80CF
0x01_80D0
0x01_80D1
0x01_80D2
0x01_80D3
0x01_80D4
0x01_80D5
0x01_80D6
0x01_80D7
0x01_80D8
0x01_80D9
0x01_80DA
0x01_80DB
0x01_80DC
0x01_80DD
0x01_80DE
0x01_80DF
0x01_80E0
0x01_80E1
0x01_80E2
0x01_80E3
0x01_80E4
0x01_80E5
0x01_80E6
0x01_80E7
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
IGC16[9:8]
IGC32[9:8]
IGC64[9:8]
IGC128[9:8]
IGC256[9:8]
IGC512[9:8]
0xB4
IGC16[7:0]
IGC32[7:0]
IGC64[7:0]
IGC128[7:0]
IGC256[7:0]
IGC512[7:0]
0xB6
0xB8
0xBA
0xBC
0xBE
TCIBG2[2:0]
SLPBG[2:0]
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
IBG2[2:0]
IBG1[2:0]
TCBG1[2:0]
SLPBG[2:0]
TRIM_BG0 (lo)
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
UBG3 DBG3
TCBG2[2:0]
TRIM_BG1 (hi)
TRIM_BG1 (lo)
V1P2BG2[3:0]
V2P5BG2[3:0]
V1P2BG1[3:0]
V2P5BG1[3:0]
TRIM_BG2 (hi)
TRIM_BG2 (lo)
LIN
TRIM_LIN
LVT
TRIM_LVT
LPOSC[12:8]
LPOSC[7:0]
TRIM_OSC (hi)
TRIM_OSC (lo)
(310)
VOC_S[7:0]
VOC_O[7:0]
COMP_VO
0xAA
0xAA
0xAA
0xAA
(310)
(310)
(310)
COMP_VO
VOC_S_CHOP[7:0] (Chopper Mode)
VOC_O_CHOP[7:0] (Chopper Mode)
COMP_VO
COMP_VO
VSGC[9:8]
COMP_VSG (hi)
COMP_VSG (lo)
COMP_VOG (hi)
COMP_VOG (lo)
COMP_ITO
(310)
0xAC
0xAC
VSGC[7:0]
VOGC[9:8]
(310)
VOGC[7:0]
ITO[7:0]
0xD0
ITG[7:0]
COMP_ITG
0xD1
n.a.
n.a.
n.a.
n.a.
GAIN_CAL_VSENSE_ROOM (hi)
GAIN_CAL_VSENSE_ROOM (lo)
GAIN_CAL_VOPT_ROOM (hi)
GAIN_CAL_VOPT_ROOM (lo)
BG3 diag measurement from Vsense channel after cal at room
BG3 diag measurement from Vopt channel after cal at room
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Table 563. Analog die trimming information (continued)
OFFSET
Byte description
Target register
Global
address
HEX
DEC
40
7
6
5
4
3
2
1
0
Name
Offset
n.a.
0x01_80E8
0x01_80E9
0x01_80EA
0x01_80EB
28
29
2A
2B
GAIN_CAL_IG4_ROOM (hi)
GAIN_CAL_IG4_ROOM (med)
GAIN_CAL_IG4_ROOM (lo)
41
BG3 diag measurement from I channel (gain4) at room
n.a.
42
n.a.
43
Reserved
VSENSE Channel Gain Compensation
0x01_80EC
0x01_80ED
0x01_80EE
0x01_80EF
0x01_80F0
0x01_80F1
0x01_80F2
0x01_80F3
0x01_80F4
0x01_80F5
0x01_80F6
0x01_80F7
0x01_80F8
0x01_80F9
0x01_80FA
0x01_80FB
0x01_80FC
0x01_80FD
0x01_80FE
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
COMP_VSG_COLD[7:0]
COMP_VSG_HOT[7:0]
COMP_VOG_COLD[7:0]
COMP_VOG_HOT[7:0]
IGC4_COLD[7:0]
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
(311)
- COLD Temp
VSENSE Channel Gain Compensation
(311)
- HOT Temp
VOPT Channel Gain Compensation -
(311)
COLD Temp
VOPT Channel Gain Compensation -
(311)
HOT Temp
Current Channel Gain (4)
(311)
Compensation - COLD Temp
Current Channel Gain (4)
IGC4_HOT[7:0]
(311)
Compensation - HOT Temp
Current Channel Gain (8)
IGC8_COLD[7:0]
(311)
Compensation - COLD Temp
Current Channel Gain (8)
IGC8_HOT[7:0]
(311)
Compensation - HOT Temp
Current Channel Gain (16)
IGC16_COLD[7:0]
IGC16_HOT[7:0]
(311)
Compensation - COLD Temp
Current Channel Gain (16)
(311)
Compensation - HOT Temp
Current Channel Gain (32)
IGC32_COLD[7:0]
IGC32_HOT[7:0]
(311)
Compensation - COLD Temp
Current Channel Gain (32)
(311)
Compensation - HOT Temp
Current Channel Gain (64)
IGC64_COLD[7:0]
IGC64_HOT[7:0]
(311)
Compensation - COLD Temp
Current Channel Gain (64)
(311)
Compensation - HOT Temp
Current Channel Gain (128)
IGC128_COLD[7:0]
IGC128_HOT[7:0]
IGC256_COLD[7:0]
IGC256_HOT[7:0]
IGC512_COLD[7:0]
(311)
Compensation - COLD Temp
Current Channel Gain (128)
(311)
Compensation - HOT Temp
Current Channel Gain (256)
(311)
Compensation - COLD Temp
Current Channel Gain (256)
(311)
Compensation - HOT Temp
Current Channel Gain (512)
(311)
Compensation - COLD Temp
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Table 563. Analog die trimming information (continued)
OFFSET
Byte description
Target register
Global
address
HEX
3F
DEC
7
6
5
4
3
2
1
0
Name
Offset
Current Channel Gain (512)
Compensation - HOT Temp
0x01_80FF
Notes
63
IGC512_HOT[7:0]
n.a.
(311)
310. Based on the selection of the voltage measurement source (VSENSE or VOPT) and the activation of chopper mode.
311. 7 Bit character with bit 7 (MSB) as sign (0 = “+”; 1 = “-”) with the difference to the corresponding room temperature value
(e.g. 10000010 = “-2”).
5.2.2
Analog die trimming overview
5.2.2.1
Current channel gain compensation trim (COMP_IG4-COMP_IG512)
To achieve the specified accuracy of the current acquisition, the optimum trim value is calculated during final test and stored into the MCU
FLASH memory. On device every power up, the corresponding trim value needs to be copied into the corresponding analog register via
D2D interface. See Section 4.8, “Channel acquisition" for additional details.
5.2.2.2
Bandgap reference trimming (TRIM_BG0-TRIM_BG2)
To achieve the specified accuracy of the integrated voltage regulators on the analog die, the optimum trim value is calculated during final
test and stored into the MCU FLASH memory. On device every power up, the corresponding trim value needs to be copied into the desired
analog register via D2D interface.
5.2.2.3
LIN slope control trimming (TRIM_LIN)
To achieve the specified slope of the LIN output signal, the optimum trim information is determined during final test and stored into the IFR
register block of the MCU FLASH memory. On device every power up, the corresponding trim value needs to be copied into the desired
analog register via D2D interface.
5.2.2.4
Low voltage threshold trim (TRIM_LVT)
To achieve the specified low voltage behavior, on device every power up, the corresponding trim value (LVR) needs to be copied into the
corresponding analog trim register via D2D interface.
5.2.2.5
Low power oscillator trimming (TRIM_OSC)
To achieve the specified accuracy of the analog low power reference frequency (f
), the optimum trim value is calculated during final
TOL_A
test and stored into the IFR register block of the MCU FLASH memory. On device every power up, the corresponding trim value needs to
be copied into the desired analog register via D2D interface.
5.2.2.6
Voltage channel compensation (COMP_VOx, COMP_VSG, COMP_VOG)
To achieve the specified accuracy of the voltage channels, gain and offset compensation are trimmed during final test and stored into the
IFR register block of the MCU FLASH memory. The information is used during the calibration procedure described in Section 4.8.5,
“Calibration".
5.2.2.7
Temperature sense module trimming (COMP_ITO, COMP_ITG)
To achieve the specified accuracy of the internal temperature sense module, the optimum trim information is determined during final test
at hot / cold temperature and stored into the IFR register block of the MCU FLASH memory. On device every power up, the corresponding
trim value needs to be copied into the desired analog register via D2D interface.
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5.2.2.8
Band gap reference - diagnostic measurements (GAIN_CAL_X_X)
To achieve the specified accuracy of the voltage and current channels, reference measurements are performed during final test and stored
for different temperatures into the IFR register block of the MCU FLASH memory. The information is used during the calibration procedure
described in Section 4.8.5, “Calibration".
5.2.2.9
Hot/cold gain compensation data (0x01_80EC - 0x01_80FF)
To achieve the specified accuracy of the voltage and current channels, reference measurements are performed during final test and stored
for different temperatures into the IFR register block of the MCU FLASH memory. The information is used during the calibration procedure
described in Section 4.8.5, “Calibration".
5.3
Memory map and registers
Overview
5.3.1
This section provides a detailed description of the memory map and registers for the analog die trimming excluding registers used for
calibration located from offset 0xE0 to 0xEF. Refer to Section 4.8.5, “Calibration" for details on Current channel gain compensation trim
(COMP_IG4-COMP_IG512), Voltage channel compensation (COMP_VOx, COMP_VSG, COMP_VOG), Temperature sense module
trimming (COMP_ITO, COMP_ITG), Band gap reference - diagnostic measurements (GAIN_CAL_X_X) and Hot/cold gain compensation
data (0x01_80EC - 0x01_80FF).
5.3.2
Module memory map
The memory map for the Compensation module is given below in Table 63.
Table 564. Module memory map
(312
Offset
Name
7
6
5
4
3
2
1
0
)
TRIM_BG0 (hi)
Trim bandgap 0
TRIM_BG0 (lo)
Trim bandgap 0
TRIM_BG1 (hi)
Trim bandgap 1
TRIM_BG1 (lo)
Trim bandgap 1
TRIM_BG2 (hi)
Trim bandgap 2
TRIM_BG2 (lo)
Trim bandgap 2
TRIM_LIN
R
W
R
0
0
0xE0
TCIBG2[2:0]
TCIBG1[2:0]
0
0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
IBG2[2:0]
IBG1[2:0]
TCBG1[2:0]
SLPBG[2:0]
W
R
UBG3
0
DBG3
0
TCBG2[2:0]
0
W
R
0
0
W
R
V1P2BG2[3:0]
V2P5BG2[3:0]
V1P2BG1[3:0]
V2P5BG1[3:0]
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LIN
Trim LIN
W
R
TRIM_LVT
LVT
Trim low voltage threshold
W
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Table 564. Module memory map (continued)
(312
Offset
Name
7
6
5
4
3
2
1
0
)
TRIM_OSC (hi)
Trim LP oscillator
TRIM_OSC (lo)
Trim LP oscillator
R
W
R
0xE8
0xE9
LPOSC[12:0]
W
R
0
0
0
0
0
0
0
0
0xEA-
0xEF
Reserved
W
Notes
312. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
5.3.2.1
Trim bandgap 0 (TRIM_BG0 (hi))
Table 565. Trim bandgap 0 (TRIM_BG0 (hi))
(313)
Offset
Access: User read/write
1 0
0xE0
7
0
6
0
5
4
3
0
2
0
R
TCIBG2[2:0]
0
TCIBG1[2:0]
0
W
Reset
0
0
0
0
Notes
313. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 566. Trim bandgap 0 (TRIM_BG0 (hi)) - register field descriptions
Field
Description
5-3
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
TCIBG2[2:0]
2-0
TCIBG1[2:0]
5.3.2.2
Trim bandgap 0 (TRIM_BG0 (lo))
Table 567. Trim bandgap 0 (TRIM_BG0 (lo))
(314)
Offset
Access: User read/write
1 0
0xE1
7
0
6
0
5
4
IBG2[2:0]
0
3
0
2
0
R
IBG1[2:0]
0
W
Reset
0
0
0
0
Notes
314. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
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Table 568. Trim bandgap 0 (TRIM_BG0 (lo)) - register field descriptions
Field
Description
5-3
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
IBG2[2:0]
2-0
IBG1[2:0]
5.3.2.3
Trim bandgap 1 (TRIM_BG1 (hi))
Table 569. Trim bandgap 1 (TRIM_BG1 (hi))
(315)
Offset
Access: User read/write
1 0
0xE2
7
6
DBG3
0
5
4
3
0
2
0
R
UBG3
0
TCBG2[2:0]
0
TCBG1[2:0]
0
W
Reset
0
0
Notes
315. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 570. Trim bandgap 1 (TRIM_BG1 (hi)) - register field descriptions
Field
Description
7
UBG3
6
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
DBG3
5-3
TCBG2[2:0]
2-1
TCBG1[2:0]
5.3.2.4
Trim bandgap 1 (TRIM_BG1 (lo))
Table 571. Trim bandgap 1 (TRIM_BG1 (lo))
(316)
Offset
Access: User read/write
1 0
0xE3
7
0
6
0
5
0
4
0
3
0
2
0
R
SLPBG[2:0]
0
W
Reset
0
0
0
0
0
0
Notes
316. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 572. Trim bandgap 1 (TRIM_BG1 (lo)) - register field descriptions
Field
Description
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
2-0
SLPBG[2:0]
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5.3.2.5
Trim bandgap 2 (TRIM_BG2 (hi))
Table 573. Trim bandgap 2 (TRIM_BG2 (hi))
(317)
Offset
Access: User read/write
0xE4
7
6
5
4
3
0
2
0
1
0
0
R
V1P2BG2[3:0]
V1P2BG1[3:0]
W
Reset
0
0
0
0
0
Notes
317. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 574. Trim bandgap 2 (TRIM_BG2 (hi)) - register field descriptions
Field
Description
7-4
V1P2BG2[3:0
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality"
for location information.
3-0
V1P2BG1[3:0
5.3.2.6
Trim Bandgap 2 (TRIM_BG2 (lo))
Table 575. Trim bandgap 2 (TRIM_BG2 (hi))
(318)
Offset
Access: User read/write
0
0xE5
7
6
5
4
3
0
2
0
1
0
R
V2P5BG2[3:0]
V2P5BG1[3:0]
W
Reset
0
0
0
0
0
Notes
318. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 576. Trim bandgap 2 (TRIM_BG2 (hi)) - register field descriptions
Field
Description
7-4
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
V2P5BG2[3:0
3-0
V2P5BG1[3:0
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5.3.2.7
trim LIN (TRIM_LIN)
Table 577. Trim LIN (TRIM_LIN)
(319)
Offset
Access: User read/write
0xE6
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
LIN
0
R
W
Reset
0
0
0
0
0
0
0
Notes
319. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 578. Trim LIN (TRIM_LIN) - register field descriptions
Field
Description
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
0
LIN
5.3.2.8
Trim low voltage threshold (TRIM_LVT)
Table 579. Trim low-voltage threshold (TRIM_LVT)
(320)
Offset
Access: User read/write
0
0xE7
7
0
6
0
5
0
4
0
3
0
2
0
1
0
R
W
LVT
0
Reset
0
0
0
0
0
0
0
Notes
320. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 580. Trim low-voltage threshold (TRIM_LVT) - register field descriptions
Field
Description
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation of the
MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die functionality" for
location information.
0
LVT
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5.3.2.9
Trim LP oscillator (TRIM_OSC (hi), TRIM_OSC (lo))
Table 581. Trim LP oscillator (TRIM_OSC (hi), TRIM_OSC (lo))
(321)
Offset
Access: User read/write
0xE8
7
0
0
6
0
0
5
0
1
4
0
1
3
0
1
2
1
0
1
0
0
1
R
LPOSC[12:8]
0
W
Reset
R
W
LPOSC[7:0]
Reset
1
Notes
321. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 582. Trim LP Oscillator (TRIM_OSC (hi), TRIM_OSC (lo)) - Register Field Descriptions
Field
Description
The optimal content of this register is determined during final test and stored in the microcontroller IFR. For proper operation
of the MM912_637, the content has to be copied to this location. See Section 5.2.1, “IFR - trimming content for analog die
functionality" for location information.
12-0
LPOSC[12:0]
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6
Packaging
For the most current package revision, visit www.nxp.com and perform a keyword search using the “98A” listed below.
6.1
Package dimensions SOT619-25(D)
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6.2
Package dimensions SOT619-16
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Revision history
Revision
Date
Description of Changes
1.0
2.0
4/2011
8/2011
•
Initial release
Minor changes throughout the document
•
•
Minor description changes and logo to align this data sheet to the Xtrinsic product platform. No content
was altered.
3.0
1/2012
• Added targeted applications
• Normal mode current max = 25 mA
• MM912_637 stop/sleep/pseudo stop consumption combined for the product
• Max operating conditions on Isense set to +/-0.3 V
• Low voltage resetH lower limit = 1.9 V
• Undervoltage interrupt assert lower limit = 4.55 V
• Undervoltage interrupt deassert lower limit = 4.7 V
• Description updated to fit current implementation on current ampere hour counter: The accumulator
could be reset by writing 1 into AHCR register. The Ampere Hour Counter is counting after wake-up. In
Normal mode, the accumulator register ACQ_AHC can be read out any time.
10/2013
4.0
• Added RESET to RESETA connection to Figure 4. Required / Recommended External Components.
• Added connection information to VDDX/VDDRX, VDDH/VDDD2D and RESET/RESETA pins into pin
description.
• Repeated description of the Life Time Counter
• Clarified to wait for PLL Lock after wake-up
• Repeated description of Low Power Current trigger threshold
• Removed Xtrinsic logo. No other change to the document
• Changed document status to Technical Data.
3/2014
1/2015
• Remove option detailing reduced accuracy for voltage and current measurement if the temperature
based compensation is not used (single temperature calibration). All known customers are using
temperature based compensation for best accuracy.
5.0
6.0
• Updated tables 62 and 182, and updated description corresponding descriiption tables 27 and 184.
• Updated per PB #16604.
8/2016
6/2021
• Updated to NXP document form and style
• Added four part numbers to Table 1., “Ordering information" and Table 2., “Ordering options":
MM912I637TM2EP, MM912J637TM2EP, MM912I637TV1EP and MM912J637TV1EP, and the
corresponding package information
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Information in this document is provided solely to enable system and software implementers to use NXP products. There
are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on
the information in this document.
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Document Number: MM912_637D1
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