MPC5554MZP132 [NXP]
32-BIT, FLASH, 132MHz, MICROCONTROLLER, PBGA416, 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, TEBGA-416;型号: | MPC5554MZP132 |
厂家: | NXP |
描述: | 32-BIT, FLASH, 132MHz, MICROCONTROLLER, PBGA416, 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, TEBGA-416 时钟 外围集成电路 |
文件: | 总58页 (文件大小:2155K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: MPC5554
Rev. 4, May 2012
Freescale Semiconductor
Data Sheet: Technical Data
MPC5554
Microcontroller Data Sheet
by: Microcontroller Division
Contents
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5554
microcontroller device. For functional characteristics,
refer to the MPC5553/MPC5554 Microcontroller
Reference Manual.
1
2
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI (Electromagnetic Interference) Characteristics 8
3.5 ESD (Electromagnetic Static Discharge) Characteris-
tics9
1
Overview
3.6 Voltage Regulator Controller (VRC) and
The MPC5554 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power-On Reset (POR) Electrical Specifications9
3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 10
3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 14
3.9 Oscillator and FMPLL Electrical Characteristics . . 20
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fa Flash Memory Electrical Characteristics . . . 23
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Architecture embedded technology. This family
of parts has many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
4
5
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 MPC5553546667 416 PBGA Pinout . . . . . . . . . . . 45
4.2 MPC5554 416-Pin Package Dimensions . . . . . . . 52
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (including floating point library)
with the original PowerPC instruction set. The embedded
architecture enhancements improve the performance in
embedded applications. The core also has additional
instructions, including digital signal processing (DSP)
instructions, beyond the original PowerPC instruction
set.
Revision History for the MPC5554 Data Sheet . . . . . . 54
5.1 Changes between Revision 3 and Revision 4. . . . 54
5.2 Changes between Revision 2 and Revision 3. . . . 54
© Freescale Semiconductor, Inc., 2008,2012. All rights reserved.
Overview
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The MPC5554 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and
two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5554 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware
channels, variable number of parameters per channel, angle clock hardware, and additional control and
arithmetic instructions. The eTPU is programmed using a high-level programming language.
The less complex timer functions of the MPC5554 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). 324 s40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of
eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
MPC5554 Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Ordering Information
2
Ordering Information
5554
R2
ZP
80
M PC
M
Qualification status
Core code
Device number
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Tape and Reel Status
R2 = Tape and reel
(blank) = Trays
Operating Frequency
80 = 80 MHz
112 = 112 MHz
132 = 132 MHz
Package Identifier
ZP = 416PBGA SnPb
VR = 416PBGA Pb-free
Temperature Range
M = –40° C to 125° C
A = –55° C to 125° C
Qualification Status
P = Pre qualification
M = Fully spec. qualified
Note: Not all options are available on all devices. Refer to Table 1.
Figure 1. MPC5500 Family Part Number Example
Unless noted in this data sheet, all specifications apply from T to T .
L
H
Table 1. Orderable Part Numbers
Operating Temperature 2
Speed (MHz)
Freescale Part Number1
Package Description
Nominal
Max. 3 (fMAX
)
Min. (TL)
Max. (TH)
MPC5554MVR132
MPC5554MVR112
MPC5554MVR80
MPC5554AVR132
MPC5554MZP132
MPC5554MZP112
MPC5554MZP80
MPC5554AZP132
132
112
80
132
114
82
–40° C
–55° C
–40° C
–55° C
125° C
125° C
125° C
125° C
MPC5554 416 package
Lead-free (PbFree)
132
132
112
80
132
132
114
82
MPC5554 416 package
Leaded (SnPb)
132
132
1
All devices are PPC5554, rather than MPC5554, until product qualifications are complete. Not all configurations are available in
the PPC parts.
2
3
The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and132 MHz
parts allow for 128 MHz system clock + 2% FM.
MPC5554 Microcontroller Data Sheet, Rev. 4
3
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1
Maximum Ratings
1
Table 2. Absolute Maximum Ratings
Spec
Characteristic
1.5 V core supply voltage 2
Symbol
Min.
Max.
Unit
1
2
4
5
6
7
8
9
VDD
VPP
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.7
6.5
4.6
1.7
4.6
4.6
4.6
5.5
4.6
6.5
V
V
V
V
V
V
V
V
V
V
Flash program/erase voltage
Flash read voltage
VFLASH
VSTBY
VDDSYN
VDD33
VRC33
VDDA
SRAM standby voltage
Clock synthesizer voltage
3.3 V I/O buffer voltage
Voltage regulator control input voltage
Analog supply voltage (reference to VSSA
)
10 I/O supply voltage (fast I/O pads) 3
11 I/O supply voltage (slow and medium I/O pads) 3
12 DC input voltage 4
VDDEH powered I/O pads
VDDE powered I/O pads
VDDE
VDDEH
VIN
–1.0 5
–1.0 5
6.5 6
4.6 7
V
13 Analog reference high voltage (reference to VRL
)
VRH
–0.3
–0.1
5.5
0.1
V
V
V
V
V
V
V
V
14
15
V
SS to VSSA differential voltage
DD to VDDA differential voltage
VSS – VSSA
VDD – VDDA
VRH – VRL
V
–VDDA
–0.3
VDD
5.5
16 VREF differential voltage
17
18
V
RH to VDDA differential voltage
RL to VSSA differential voltage
VRH – VDDA
VRL – VSSA
VDDEH – VDDA
VDDF – VDD
–5.5
5.5
V
–0.3
0.3
19 VDDEH to VDDA differential voltage
–VDDA
–0.3
VDDEH
0.3
20
21
VDDF to VDD differential voltage
VRC33 to VDDSYN differential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a.
22 VSSSYN to VSS differential voltage
23 RCVSS to VSS differential voltage
24 Maximum DC digital input current 8
VSSSYN – VSS
VRCVSS – VSS
IMAXD
–0.1
–0.1
–2
0.1
0.1
2
V
V
V
mA
4
(per pin, applies to all digital pins)
25 Maximum DC analog input current 9
(per pin, applies to all analog pins)
26 Maximum operating temperature range 10
Die junction temperature
IMAXA
TJ
–3
TL
3
mA
oC
oC
150.0
150.0
27 Storage temperature range
TSTG
–55.0
MPC5554 Microcontroller Data Sheet, Rev. 4
4
Freescale Semiconductor
Electrical Characteristics
1
Table 2. Absolute Maximum Ratings (continued)
Spec
Characteristic
Symbol
Min.
Max.
Unit
28 Maximum solder temperature 11
Lead free (Pb-free)
Leaded (SnPb)
29 Moisture sensitivity level 12
TSDR
MSL
—
—
260.0
245.0
oC
—
3
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability
or cause permanent damage to the device.
2
3
4
1.5 V 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC.
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH
.
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
5
6
7
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC
voltage greater than –0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
Total injection current for all analog input pins must not exceed 15 mA.
8
9
10 Lifetime operation at these specification limits is not guaranteed.
11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D.
12 Moisture sensitivity per JEDEC test method A112.
3.2
Thermal Characteristics
The shaded rows in the following table indicate information specific to a four-layer board.
Table 3. MPC5554 Thermal Characteristics
Spec
MPC5554 Thermal Characteristic
Symbol
416 PBGA
Unit
1
2
3
4
5
6
7
Junction to ambient 1, 2, natural convection (one-layer board)
Junction to ambient 1, 3, natural convection (four-layer board 2s2p)
Junction to ambient 1, 3 (@200 ft./min., one-layer board)
Junction to ambient 1, 3 (@200 ft./min., four-layer board 2s2p)
Junction to board 4 (four-layer board 2s2p)
RJA
RJA
RJMA
RJMA
RJB
RJC
JT
24
18
19
15
9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction to case 5
Junction to package top 6, natural convection
5
2
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
MPC5554 Microcontroller Data Sheet, Rev. 4
5
Freescale Semiconductor
Electrical Characteristics
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, T , can be obtained from the equation:
J
T = T + (R
P )
D
J
A
JA
where:
o
T = ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
JA
P = power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
2
Overall power dissipation on the board is less than 0.02 W/cm
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
MPC5554 Microcontroller Data Sheet, Rev. 4
6
Freescale Semiconductor
Electrical Characteristics
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
P )
D
J
B
JB
where:
o
T = junction temperature ( C)
J
o
T = board temperature at the package perimeter ( C/W)
B
o
R
= junction-to-board thermal resistance ( C/W) per JESD51-8
JB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
R
= R
+ R
JA
JC CA
where:
o
R
R
R
= junction-to-ambient thermal resistance ( C/W)
JA
JC
CA
o
= junction-to-case thermal resistance ( C/W)
o
= case-to-ambient thermal resistance ( C/W)
R
is device related and is not affected by other factors. The thermal environment can be controlled to
JC
change the case-to-ambient thermal resistance, R
. For example, change the air flow around the device,
CA
add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter ( ) to determine the junction temperature by measuring the
JT
temperature at the top center of the package case using the following equation:
T = T + ( P )
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
MPC5554 Microcontroller Data Sheet, Rev. 4
7
Freescale Semiconductor
Electrical Characteristics
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple
junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat
against the package case to avoid measurement errors caused by the cooling effects of the thermocouple
wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Rd.
San Jose, CA., 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applica-
tions,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and
Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.3
Package
The MPC5554 is available in packaged form. Read the package options in Section 2, “Ordering
Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
3.4
EMI (Electromagnetic Interference) Characteristics
1
Table 4. EMI Testing Specifications
Spec
Characteristic
Minimum
Typical
Maximum
Unit
1
2
3
4
5
6
Scan range
0.15
—
—
—
1000
fMAX
—
MHz
MHz
V
Operating frequency
VDD operating voltages
DDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages
—
1.5
3.3
5.0
—
V
—
—
V
VPP, VDDEH, VDDA operating voltages
Maximum amplitude
—
—
14 2
32 3
V
—
dBuV
7
Operating temperature
—
—
25
oC
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554
and applied to the MPC5500 family as generic EMI performance data.
2
3
Measured with the single-chip EMI program.
Measured with the expanded EMI program.
MPC5554 Microcontroller Data Sheet, Rev. 4
8
Freescale Semiconductor
Electrical Characteristics
3.5
ESD (Electromagnetic Static Discharge) Characteristics
1, 2
Table 5. ESD Ratings
Characteristic
Symbol
Value
Unit
ESD for human body model (HBM)
HBM circuit description
2000
1500
V
R1
C
100
pF
500 (all pins)
750 (corner pins)
ESD for field induced charge model (FDCM)
V
Number of pulses per pin:
Positive pulses (HBM)
Negative pulses (HBM)
—
—
1
1
—
—
Interval of pulses
—
1
second
1
All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2
Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements,
which includes the complete DC parametric and functional testing at room temperature and hot temperature.
3.6
Voltage Regulator Controller (V ) and
Power-On Reset (POR) Electrical Specifications
RC
The following table lists the V and POR electrical specifications:
RC
Table 6. V and POR Electrical Specifications
RC
Spec
Characteristic
Negated (ramp up)
Symbol
VPOR15
Min.
Max. Units
1.1
1.1
1.35
V
1
1.5 V (VDD) POR 1
Asserted (ramp down)
1.35
Asserted (ramp up)
Negated (ramp up)
Asserted (ramp down)
Negated (ramp down)
0.0
2.0
2.0
0.0
0.30
2.85
2.85
0.30
2
3.3 V (VDDSYN) POR 1
VPOR33
V
Negated (ramp up)
2.0
2.0
2.85
2.85
RESET pin supply
(VDDEH6) POR 1, 2
3
4
5
VPOR5
V
Asserted (ramp down)
Before VRC allows the pass
transistor to start turning on
VTRANS_START
VTRANS_ON
1.0
2.0
2.0
V
V
When VRC allows the pass
2.85
VRC33 voltage
transistor to completely turn on 3, 4
When the voltage is greater than
the voltage at which the VRC keeps
the 1.5 V supply in regulation 5, 6
6
VVRC33REG
3.0
—
V
– 55o C7
–40o C
25o C
11.0
11.0
9.0
—
—
—
—
mA
mA
mA
mA
Current can be sourced
by VRCCTL at Tj:
8
7
IVRCCTL
150o C
7.5
MPC5554 Microcontroller Data Sheet, Rev. 4
9
Freescale Semiconductor
Electrical Characteristics
Spec
Table 6. V and POR Electrical Specifications (continued)
RC
Characteristic
Symbol
Min.
Max. Units
Voltage differential during power up such that:
8
9
VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach the
VDD33_LAG
—
—
1.0
V
VPOR33 and VPOR5 minimums respectively.
Absolute value of slew rate on power supply pins
—
70
50
—
V/ms
—
Required gain at Tj:
IDD IVRCCTL (@ fsys = fMAX
– 55o C7
– 40o C
25o C
6, 8, 9, 10
)
70
—
—
10
BETA11
8511
10511
—
—
150o C
500
—
1
The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates.
RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
2
3
4
5
6
VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5
.
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
At peak current for device.
Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1 ). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal)
bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals.
7
8
9
Only available on devices that support -55o C.
IVRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
Refer to Table 1 for the maximum operating frequency.
10 Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.
11 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (IDD IVRCCTL).
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and V
or the RESET power supplies is required
DDSYN
if using an external 1.5 V power supply with V
tied to ground (GND). To avoid power-sequencing,
RC33
V
must be powered up within the specified operating range, even if the on-chip voltage regulator
RC33
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that V
must reach a certain voltage where the values are read as ones
DD33
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
VDD33.”
Although power sequencing is not required between V
and V
during power up, V
must
RC33
RC33
DDSYN
not lead V
by more than 600 mV or lag by more than 100 mV for the V stage turn-on to operate
DDSYN
RC
within specification. Higher spikes in the emitter current of the pass transistor occur if V
leads or lags
RC33
V
by more than these amounts. The value of that higher spike in current depends on the board power
DDSYN
supply circuitry and the amount of board level capacitance.
MPC5554 Microcontroller Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical Characteristics
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by V
. If V
lags V
by more than 100 mV, the increase in current
RC33
RC33
DDSYN
consumed can drop V low enough to assert the 1.5 V POR again. Oscillations are possible when the
DD
1.5 V POR asserts and stops the system clock, causing the voltage on V to rise until the 1.5 V POR
DD
negates again. All oscillations stop when V
is powered sufficiently.
RC33
When powering down, V
and V
have no delta requirement to each other, because the bypass
RC33
DDSYN
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between V and V is required for the V to operate within specification.
RC33
DDSYN
RC
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 7. Pin Status for Fast Pads During the Power Sequence
Pin Status for Fast Pad Output Driver
VDDE
VDD33
VDD
POR
pad_fc (fast)
Low
—
—
Asserted
Asserted
Asserted
Asserted
Asserted
Negated
Low
VDDE
VDDE
VDDE
VDDE
VDDE
Low
Low
VDD
Low
VDD
VDD
High
High
Low
VDD33
VDD33
VDD33
High impedance (Hi-Z)
Hi-Z
Functional
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
Pin Status for Medium and Slow Pad Output Driver
VDDEH
VDD
POR
pad_mh (medium) pad_sh (slow)
Low
—
Asserted
Asserted
Asserted
Negated
Low
High impedance (Hi-Z)
Hi-Z
VDDEH
VDDEH
VDDEH
Low
VDD
VDD
Functional
The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the voltage on the pins go to a high-impedance state until POR
negates. When the internal POR negates, the functional state of the signal during reset applies and the
weak-pull devices
(up or down) are enabled as defined in the device reference manual. If V is too low to correctly
DD
propagate the logic signals, the weak-pull devices can pull the signals to V
and V
.
DDE
DDEH
MPC5554 Microcontroller Data Sheet, Rev. 4
11
Freescale Semiconductor
Electrical Characteristics
To avoid this condition, minimize the ramp time of the V supply to a time period less than the time
DD
required to enable the external circuitry connected to the device outputs.
During initial power ramp-up, when Vstby is 0.6v or above. a typical current of 1-3mA and maximum of
4mA may be seen until V is applied. This current will not reoccur until V
is lowered below V
DD
stby
stby
min. specification.
Figure 2 shows an approximate interpolation of the I
worst-case specification to estimate values at
STBY
different voltages and temperatures. The vertical lines shown at 25 C, 60 C, and 150 C in Figure 2 are
the actual I
specifications (27d) listed in Table 9.
DD_STBY
Figure 2. fISTBY Worst-case Specifications
MPC5554 Microcontroller Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical Characteristics
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, V
must not lag the latest V
or RESET power pin (V
) by
DD33
DDSYN
DDEH6
more than the V
lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
DD33
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V can lag V or the RESET power
DD33
DDSYN
pin (V
), but cannot lag both by more than the V
lag specification. This V
lag specification
DDEH6
DD33
DD33
applies during power up only. V
has no lead or lag requirements when powering down.
DD33
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V V power supply must rise to 1.35 V before the 3.3 V V
power supply and the RESET
DDSYN
DD
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, V must be within specification before the 3.3 V POR and the RESET
DD
POR negate.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
Figure 3. Power-Up Sequence (V
Grounded)
RC33
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with V
grounded is if V decreases to less than
DD
RC33
its operating range, V
or the RESET power must decrease to less than 2.0 V before the V power
DDSYN
DD
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
MPC5554 Microcontroller Data Sheet, Rev. 4
13
Freescale Semiconductor
Electrical Characteristics
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications (T = T to T )
A
L
H
Spec
Characteristic
Symbol
Min
Max.
Unit
1
2
3
4
5
6
8
9
Core supply voltage (average DC RMS voltage)
Input/output supply voltage (fast input/output) 1
Input/output supply voltage (slow and medium input/output)
3.3 V input/output buffer voltage
VDD
VDDE
1.35
1.62
3.0
3.0
3.0
4.5
4.5
3.0
0.8
3.0
1.65
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDEH
VDD33
VRC33
VDDA
5.25
3.6
Voltage regulator control input voltage
Analog supply voltage 2
3.6
5.25
Flash programming voltage 3
VPP
5.25
Flash read voltage
VFLASH
VSTBY
VDDSYN
VIH_F
3.6
10 SRAM standby voltage 4
1.2
11 Clock synthesizer operating voltage
12 Fast I/O input high voltage
3.6
0.65 VDDE
VSS – 0.3
VDDE + 0.3
0.35 VDDE
VDDEH + 0.3
0.35 VDDEH
13 Fast I/O input low voltage
VIL_F
14 Medium and slow I/O input high voltage
15 Medium and slow I/O input low voltage
16 Fast input hysteresis
VIH_S
VIL_S
0.65 VDDEH
VSS – 0.3
VHYS_F
VHYS_S
VINDC
VOH_F
0.1 VDDE
0.1 VDDEH
17 Medium and slow I/O input hysteresis
18 Analog input voltage
VSSA – 0.3
VDDA + 0.3
—
19 Fast output high voltage (IOH_F = –2.0 mA)
0.8 VDDE
20 Slow and medium output high voltage
IOH_S = –2.0 mA
VOH_S
VOL_F
VOL_S
0.80 VDDEH
0.85 VDDEH
—
V
IOH_S = –1.0 mA
21 Fast output low voltage (IOL_F = 2.0 mA)
—
—
0.2 VDDE
V
V
22 Slow and medium output low voltage
IOL_S = 2.0 mA
0.20 VDDEH
0.15 VDDEH
IOL_S = 1.0 mA
23 Load capacitance (fast I/O) 5
DSC (SIU_PCR[8:9]) = 0b00
—
—
—
—
10
20
30
50
pF
pF
pF
pF
= 0b01
= 0b10
= 0b11
CL
24 Input capacitance (digital pins)
25 Input capacitance (analog pins)
CIN
—
—
7
pF
pF
CIN_A
10
26 Input capacitance:
(Shared digital and analog pins AN[12]_MA[0]_SDS,
AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)
CIN_M
—
12
pF
MPC5554 Microcontroller Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (T = T to T ) (continued)
A
L
H
Spec
Characteristic
Symbol
Min
Max.
Unit
27a Operating Current 1.5 V Supplies @ 132 MHz: 6
VDD (including VDDF max current) @1.65 V typical use 7, 8
VDD (including VDDF max current) @1.4 V typical use 7, 8
VDD (including VDDF max current) @1.65 V high use 8, 9
VDD (including VDDF max current) @1.4 V high use 8, 9
IDD
IDD
IDD
IDD
—
—
—
—
700
600
875
740
mA
mA
mA
mA
27b Operating Current 1.5 V Supplies @ 114 MHz: 6
VDD (including VDDF max current) @1.65 V typical use 7, 8
VDD (including VDDF max current) @1.4 V typical use 7, 8
VDD (including VDDF max current) @1.65 V high use 8, 9
VDD (including VDDF max current) @1.4 V high use 8, 9
IDD
IDD
IDD
IDD
—
—
—
—
609
522
760
643
mA
mA
mA
mA
27c Operating Current 1.5 V Supplies @ 82 MHz: 6
VDD (including VDDF max current) @1.65 V typical use 7, 8
VDD (including VDDF max current) @1.40 V typical use 7, 8
VDD (including VDDF max current) @1.65 V high use 8, 9
VDD (including VDDF max current) @1.40 V high use 8, 9
IDD
IDD
IDD
IDD
—
—
—
—
446
384
555
471
mA
mA
mA
mA
27d RAM standby current.10
IDD_STBY @ 25o C
VSTBY @ 0.8 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
20
30
50
A
A
A
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY @ 60o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
70
100
200
A
A
A
IDD_STBY @ 150o C (Tj)
VSTBY @ 0.8 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
1200
1500
2000
A
A
A
VSTBY @ 1.0 V
VSTBY @ 1.2 V
28 Operating current 3.3 V supplies @ fMAX MHz
11
VDD33
IDD_33
—
2 + (values
derived from
procedure of
mA
footnote 11
)
VFLASH
IVFLASH
IDDSYN
—
—
10
15
mA
mA
VDDSYN
29 Operating current 5.0 V supplies (12 MHz ADCLK):
VDDA (VDDA0 + VDDA1
Analog reference supply current (VRH, VRL
VPP
)
IDD_A
IREF
IPP
—
—
—
20.0
1.0
25.0
mA
mA
mA
)
MPC5554 Microcontroller Data Sheet, Rev. 4
15
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (T = T to T ) (continued)
A
L
H
Spec
Characteristic
Symbol
Min
Max.
Unit
30 Operating current VDDE supplies: 12
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
VDDEH8
VDDEH9
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
Refer to
mA
mA
mA
mA
mA
mA
mA
mA
mA
footnote 12
31 Fast I/O weak pullup current 13
1.62–1.98 V
10
20
20
110
130
170
A
A
A
2.25–2.75 V
3.00–3.60 V
IACT_F
Fast I/O weak pulldown current 13
1.62–1.98 V
10
20
20
100
130
170
A
A
A
2.25–2.75 V
3.00–3.60 V
32 Slow and medium I/O weak pullup/down current 13
3.0–3.6 V
4.5–5.5 V
IACT_S
10
20
150
170
A
A
33 I/O input leakage current 14
34 DC injection current (per pin)
35 Analog input current, channel off 15
IINACT_D
IIC
–2.5
–2.0
–150
2.5
2.0
A
mA
nA
IINACT_A
150
35a Analog input current, shared analog / digital pins
(AN[12], AN[13], AN[14], AN[15])
IINACT_AD
–2.5
2.5
A
36
V
SS to VSSA differential voltage 16
VSS – VSSA
VRL
VRL – VSSA
VRH
–100
VSSA – 0.1
–100
VDDA – 0.1
4.5
100
VSSA + 0.1
100
mV
V
37 Analog reference low voltage
38 VRL differential voltage
mV
V
39 Analog reference high voltage
VDDA + 0.1
5.25
40 VREF differential voltage
VRH – VRL
V
41 VSSSYN to VSS differential voltage
42 VRCVSS to VSS differential voltage
43 VDDF to VDD differential voltage
VSSSYN – VSS
VRCVSS – VSS
VDDF – VDD
VRC33 – VDDSYN
VIDIFF
–50
50
mV
mV
mV
V
–50
50
–100
–0.1
100
43a VRC33 to VDDSYN differential voltage
44 Analog input differential signal range (with common mode 2.5 V)
45 Operating temperature range, ambient (packaged)
46 Slew rate on power-supply pins
0.1 17
2.5
–2.5
V
TA = (TL to TH)
—
TL
TH
C
V/ms
—
50
1
VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and VDDE3 have a range of 1.6–3.6 V if
SIU_ECCR[EBTS] = 1.
MPC5554 Microcontroller Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
2
3
4
5
6
7
8
9
| VDDA0 – VDDA1 | must be < 0.1 V.
VPP can drop to 3.0 V during read operations.
If standby operation is not required, connect VSTBY to ground.
Applies to CLKOUT, external bus pins, and Nexus pins.
Maximum average RMS DC current.
Average current measured on automotive benchmark.
Peak currents can be higher on specialized code.
High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache
(0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents are possible if an “idle” loop that crosses cache lines is run from cache. Write code that avoids this
condition.
10 The current specification relates to average standby operation after SRAM has been loaded with data. For power up current see
Section 3.7, “Power-Up/Down Sequencing”, Figure 2.
11 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation.
12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
13 Absolute value of current, measured at VIL and VIH.
14 Weak pullup/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC
to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae.
16
V
refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V.
SSA
17 Up to 0.6 V during power up and power down.
MPC5554 Microcontroller Data Sheet, Rev. 4
17
Freescale Semiconductor
Electrical Characteristics
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a segment. The output pin current can be
calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
1
Table 10. I/O Pad Average DC Current (T = T to T )
A
L
H
Drive Select /
Slew Rate
Control Setting
Frequency
(MHz)
Spec
Pad Type
Symbol
Load2 (pF)
Voltage (V)
Current (mA)
1
25
10
2
50
50
50
200
50
50
50
200
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
5.25
5.25
5.25
5.25
5.25
5.25
5.25
5.25
3.6
11
01
00
00
11
01
00
00
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
8.0
3.2
0.7
2.4
17.3
6.5
1.1
3.9
2.8
5.2
8.5
11.0
1.6
2.9
4.2
6.7
2.4
4.4
7.2
9.3
1.3
2.5
3.5
5.7
1.7
3.1
5.1
6.6
1.0
1.8
2.5
4.0
2
Slow
IDRV_SH
3
4
2
5
50
20
3.33
3.33
66
66
66
66
66
66
66
66
56
56
56
56
56
56
56
56
40
40
40
40
40
40
40
40
6
Medium
IDRV_MH
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3.6
3.6
3.6
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
Fast
IDRV_FC
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
1
2
These values are estimates from simulation and are not tested. Currents apply to output pins only.
All loads are lumped.
MPC5554 Microcontroller Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the V
supply dependents on the usage of the pins on all I/O segments. The
DD33
power consumption is the sum of all input and output pin V
currents for all I/O segments. The output
DD33
pin V
current can be calculated from Table 11 based on the voltage, frequency, and load on all fast
DD33
(pad_fc) pins. The input pin V
current can be calculated from Table 11 based on the voltage,
DD33
frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
1
Table 11. V
Pad Average DC Current (T = T to T )
DD33
A
L
H
Frequency
(MHz)
Load 2
(pF)
VDD33
(V)
VDDE
(V)
Drive
Select
Current
(mA)
Spec
Pad Type
Symbol
Inputs
1
2
Slow
I33_SH
I33_MH
66
66
0.5
0.5
3.6
3.6
5.5
5.5
NA
NA
0.003
0.003
Medium
Outputs
3
66
66
66
66
66
66
66
66
56
56
56
56
56
56
56
56
40
40
40
40
40
40
40
40
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0.35
0.53
0.62
0.79
0.35
0.44
0.53
0.70
0.30
0.45
0.52
0.67
0.30
0.37
0.45
0.60
0.21
0.31
0.37
0.48
0.21
0.27
0.32
0.42
4
5
3.6
6
3.6
7
1.98
1.98
1.98
1.98
3.6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3.6
3.6
3.6
Fast
I33_FC
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
1
2
These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input
pins for the slow and medium pads only.
All loads are lumped.
MPC5554 Microcontroller Data Sheet, Rev. 4
19
Freescale Semiconductor
Electrical Characteristics
3.9
Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
PLL reference frequency range: 1
Crystal reference
fref_crystal
fref_ext
8
8
20
20
1
MHz
External reference
Dual controller (1:1 mode)
fref_1:1
24
fsys 2
3
2
3
4
5
System frequency 2
fsys
tCYC
f
ICO(MIN) 2RFD
fMAX
MHz
ns
System clock period
—
100
7.4
1 fsys
1000
17.5
—
Loss of reference frequency 4
Self-clocked mode (SCM) frequency 5
EXTAL input high voltage crystal mode 6
fLOR
kHz
MHz
V
fSCM
VIHEXT
VXTAL + 0.4 V
6
7
All other modes
[dual controller (1:1), bypass, external reference]
VIHEXT
VILEXT
(VDDE5 2) + 0.4 V
—
V
V
EXTAL input low voltage crystal mode 7
—
V
XTAL – 0.4 V
All other modes
[dual controller (1:1), bypass, external reference]
VILEXT
IXTAL
—
0.8
—
(VDDE5 2) – 0.4 V
V
8
9
XTAL current 8
3
mA
pF
pF
pF
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
CS_XTAL
CS_EXTAL
CL
1.5
1.5
10
—
Crystal manufacturer’s recommended capacitive
load
Refer to crystal
specification
Refer to crystal
specification
11
12
Discrete load capacitance to connect to EXTAL
Discrete load capacitance to connect to XTAL
PLL lock time 10
CL_EXTAL
(2 CL)– CS_EXTAL
– CPCB_EXTAL
pF
pF
—
—
9
CL_XTAL
(2 CL) – CS_XTAL
13
14
15
9
– CPCB_XTAL
tlpll
—
750
2
s
Dual controller (1:1) clock skew
tskew
–2
ns
(between CLKOUT and EXTAL) 11, 12
16
17
18
Duty cycle of reference
Frequency unLOCK range
Frequency LOCK range
tDC
fUL
40
60
4.0
2.0
%
–4.0
–2.0
% fSYS
% fSYS
fLCK
MPC5554 Microcontroller Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
CLKOUT period jitter, measured at fSYS max: 13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
%
fCLKOUT
19
—
—
5.0
0.01
Frequency modulation range limit 15
(do not exceed fsys maximum)
%fSYS
20
CMOD
0.8
2.4
ICO frequency
21
22
fico = [fref_crystal (MFD + 4)] (PREDIV + 1) 16
fico = [fref_ext (MFD + 4) ] (PREDIV + 1)
fico
48
4
fMAX
MHz
MHz
Predivider output frequency (to PLL)
fPREDIV
20 17
1
Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2
3
4
All internal registers retain data at 0 Hz.
Up to the maximum frequency rating of the device (refer to Table 1).
Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5
The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below fLOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6
7
Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be 400 mV for the oscillator’s comparator to produce the output clock.
Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal – Vextal) must be 400 mV for the oscillator’s comparator to produce the output clock.
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8
9
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11 PLL is operating in 1:1 PLL mode.
12
V
= 3.0–3.6 V.
DDE
13 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
14 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
15 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value.
16 f = f (2RFD).
sys
ico
17 Maximum value for dual controller (1:1) mode is (fMAX 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
MPC5554 Microcontroller Data Sheet, Rev. 4
21
Freescale Semiconductor
Electrical Characteristics
3.10 eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (TA = TL to TH)
Spec
Characteristic
ADC clock (ADCLK) frequency 1
Symbol
Minimum
Maximum
Unit
1
FADCLK
CC
1
12
MHz
Conversion cycles
Differential
ADCLK
cycles
2
13 + 2 (15)
14 + 2 (16)
13 + 128 (141)
14 + 128 (142)
Single ended
3
4
5
6
7
8
9
Stop mode recovery time 2
Resolution 3
TSR
—
10
1.25
–4
—
—
4
s
mV
INL: 6 MHz ADC clock
INL: 12 MHz ADC clock
DNL: 6 MHz ADC clock
DNL: 12 MHz ADC clock
Offset error with calibration
INL6
Counts 3
Counts
Counts
Counts
Counts
Counts
mA
INL12
DNL6
DNL12
OFFWC
GAINWC
IINJ
–8
8
–3 4
–6 4
–4 5
–8 6
–1
3 4
6 4
4 5
8 6
1
10 Full-scale gain error with calibration
11 Disruptive input injection current 7, 8, 9, 10
Incremental error due to injection current. All channels are
10 k < Rs <100 k
12
EINJ
–4
4
Counts
Channel under test has Rs = 10 k,
IINJ = IINJMAX, IINJMIN
Total unadjusted error (TUE) for single ended conversions
13
TUE
–4
4
Counts
with calibration 11, 12, 13, 14, 15
1
2
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a
maximum 16 factor.
Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform
conversions.
3
4
5
6
7
At VRH – VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.
Guaranteed 10-bit mono tonicity.
The absolute value of the offset error without calibration 100 counts.
The absolute value of the full scale gain error without calibration 120 counts.
Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than
VRH, and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8
9
Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not
affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
10 This condition applies to two adjacent pads on the internal pad.
11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12 TUE does not apply to differential conversions.
13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).
15 Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can
affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].
MPC5554 Microcontroller Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
3.11 H7Fa Flash Memory Electrical Characteristics
Table 14. Flash Program and Erase Specifications (T = T to T )
A
L
H
Initial
Spec
Flash Program Characteristic
Symbol
Min.
Typical 1
Max. 3 Unit
Max. 2
3
4
Doubleword (64 bits) program time 4
Page program time 4
Tdwprogram
Tpprogram
—
—
—
—
—
—
10
—
500
500
s
s
22
44 5
400
400
500
1250
7
16 KB block pre-program and erase time
48 KB block pre-program and erase time
64 KB block pre-program and erase time
128 KB block pre-program and erase time
T16kpperase
T48kpperase
T64kpperase
T128kpperase
265
345
415
500
5000
5000
5000
7500
ms
ms
ms
ms
9
10
8
Minimum operating frequency for program and erase
operations 6
11
—
25
—
—
—
MHz
Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values.
Initial factory condition: 100program/erase cycles, 25 oC, using a typical supply voltage measured at a minimum system
1
2
frequency of 80 MHz.
3
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
4
5
6
Actual hardware programming times. This does not include software overhead.
Page size is 256 bits (8 words).
The read frequency of the flash can range up to the maximum operating frequency. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (T = T to T )
A
L
H
Spec
Characteristic
Symbol
Min.
Typical 1 Unit
cycles
100,000 cycles
Number of program/erase cycles per block for 16 KB, 48 KB, and
64 KB blocks over the operating temperature range (TJ)
1a
P/E
100,000
—
Number of program/erase cycles per block for 128 KB blocks over the
operating temperature range (TJ)
1b
2
P/E
1000
Data retention
Retention
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–100,000 P/E cycles
20
5
—
—
years
Typical endurance is evaluated at 25o C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for
Nonvolatile Memory.
1
MPC5554 Microcontroller Data Sheet, Rev. 4
23
Freescale Semiconductor
Electrical Characteristics
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference
manual for definitions of these bit fields.
1
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz)
APC
RWSC
WWSC DPFEN 2 IPFEN 2
PFLIM 3
BFEN 4
Up to and including 82 MHz 5
0b001
0b001
0b01
0b01
0b01
0b11
0b00
0b01
0b11
0b00
0b01
0b11
0b000
to
0b110
0b0
0b1
Up to and including 102 MHz 6
Up to and including 132 MHz 7
Default setting after reset
0b001
0b010
0b111
0b010
0b011
0b111
0b00
0b01
0b11
0b00
0b01
0b11
0b000
to
0b110
0b0
0b1
0b00
0b01
0b11
0b00
0b01
0b11
0b000
to
0b110
0b0
0b1
0b00
0b00
0b000
0b0
1
Illegal combinations exist. Use entries from the same row in this table.
For maximum flash performance, set to 0b11.
2
3
4
5
6
7
For maximum flash performance, set to 0b110.
For maximum flash performance, set to 0b1.
82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).
102 MHz parts allow for 100 MHz system clock + 2% FM.
132 MHz parts allow for 128 MHz system clock + 2% FM.
3.12 AC Specifications
3.12.1 Pad AC Specifications
1
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)
2, 3, 4
SRC / DSC
(binary)
Out Delay
(ns)
Rise / Fall 4, 5
(ns)
Load Drive
(pF)
Spec
Pad
26
82
15
60
50
200
50
11
01
00
11
01
00
75
40
1
Slow high voltage (SH)
137
377
476
16
80
200
50
200
260
8
200
50
43
30
200
50
34
15
2
Medium high voltage (MH)
61
35
200
50
192
239
100
125
200
MPC5554 Microcontroller Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
1
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V) (continued)
2, 3, 4
SRC / DSC
(binary)
Out Delay
(ns)
Rise / Fall 4, 5
(ns)
Load Drive
(pF)
Spec
Pad
00
01
10
11
—
—
2.7
2.5
10
20
30
50
50
50
3
Fast
3.1
2.4
2.3
4
5
Pullup/down (3.6 V max)
Pullup/down (5.5 V max)
—
—
7500
9000
1
These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
DD = 1.35–1.65 V; VDDE = 1.62–1.98 V; VDDEH = 4.5–5.25 V; VDD33 and VDDSYN = 3.0–3.6 V; and TA = TL to TH.
V
2
3
This parameter is supplied for reference and is guaranteed by design (not tested).
The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock,
add a maximum of one system clock to the output delay.
4
5
The output delay and rise and fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization rather than 100% tested.
1
Table 18. Derated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)
2, 3, 4
SRC/DSC
(binary)
Out Delay
(ns)
Rise / Fall 3, 5
(ns)
Load Drive
(pF)
Spec
Pad
39
120
101
188
507
597
23
23
87
50
200
50
11
01
00
11
01
00
52
1
Slow high voltage (SH)
111
248
312
12
200
50
200
50
64
44
200
50
50
22
2
3
Medium high voltage (MH)
90
50
200
50
261
305
123
156
2.4
2.2
2.1
2.1
7500
9500
200
10
00
01
10
11
—
—
20
Fast
3.2
30
50
4
5
Pullup/down (3.6 V max)
Pullup/down (5.5 V max)
—
—
50
50
1
2
These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
VDD = 1.35–1.65 V; VDDE = 3.0–3.6 V; VDDEH = 3.0–3.6 V; VDD33 and VDDSYN = 3.0–3.6 V; and TA = TL to TH.
This parameter is supplied for reference and guaranteed by design (not tested).
MPC5554 Microcontroller Data Sheet, Rev. 4
25
Freescale Semiconductor
Electrical Characteristics
3
The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal.
4
The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one
system clock to the output delay.
5
This parameter is guaranteed by characterization rather than 100% tested.
VDD 2
Pad
internal data
input signal
Rising-edge
out
Falling-edge
out
delay
delay
VOH
Pad
output
VOL
Figure 4. Pad Output Delay
3.13 AC Timing
3.13.1 Reset and Configuration Pin Timing
1
Table 19. Reset and Configuration Pin Timing
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
4
RESET pulse width
tRPW
tGPW
tRCSU
tRCH
10
2
—
—
—
—
tCYC
tCYC
tCYC
tCYC
RESET glitch detect pulse width
PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid
PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid
10
0
1
Reset timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
MPC5554 Microcontroller Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 5. Reset and Configuration Pin Timing
3.13.2 IEEE 1149.1 Interface Timing
1
Table 20. JTAG Pin AC Electrical Characteristics
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
4
5
6
7
8
9
TCK cycle time
tJCYC
tJDC
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width (measured at VDDE 2)
TCK rise and fall times (40% to 70%)
TMS, TDI data setup time
tTCKRISE
tTMSS, TDIS
tTMSH, TDIH
tTDOV
tTDOI
t
—
—
20
—
20
—
—
50
50
50
—
—
TMS, TDI data hold time
t
25
—
0
TCK low to TDO data valid
TCK low to TDO data invalid
TCK low to TDO high impedance
JCOMP assertion time
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
—
50
50
10 JCOMP setup time to TCK low
11 TCK falling-edge to output valid
12 TCK falling-edge to output valid out of high impedance
13 TCK falling-edge to output high impedance (Hi-Z)
14 Boundary scan input valid to TCK rising-edge
15 TCK rising-edge to boundary scan input invalid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at: VDDE = 3.0–3.6 V and TA = TL to TH.
Refer to Table 21 for Nexus specifications.
MPC5554 Microcontroller Data Sheet, Rev. 4
27
Freescale Semiconductor
Electrical Characteristics
TCK
2
3
3
2
1
Figure 6. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 7. JTAG Test Access Port Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
TCK
10
JCOMP
9
Figure 8. JTAG JCOMP Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
29
Freescale Semiconductor
Electrical Characteristics
TCK
11
13
Output
signals
12
Output
signals
14
15
Input
signals
Figure 9. JTAG Boundary Scan Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
3.13.3 Nexus Timing
1
Table 21. Nexus Debug Port Timing
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
4
5
6
7
8
9
MCKO cycle time
tMCYC
tMDC
22
40
8
tCYC
%
MCKO duty cycle
60
3.0
3.0
3.0
—
MCKO low to MDO data valid 3
MCKO low to MSEO data valid 3
MCKO low to EVTO data valid 3
EVTI pulse width
tMDOV
–1.5
–1.5
–1.5
4.0
1
ns
tMSEOV
tEVTOV
ns
ns
tEVTIPW
tEVTOPW
tTCYC
tTCYC
tMCYC
tCYC
%
EVTO pulse width
—
TCK cycle time
4 4
—
TCK duty cycle
tTDC
40
60
—
10 TDI, TMS data setup time
11 TDI, TMS data hold time
TCK low to TDO data valid
t
NTDIS, tNTMSS
8
ns
t
NTDIH, tNTMSH
tJOV
5
—
ns
12
VDDE = 2.25–3.0 V
DDE = 3.0–3.6 V
13 RDY valid to MCKO 5
0
0
12
10
—
ns
ns
—
V
—
—
1
JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of
MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35–1.65 V, VDDE = 2.25–3.6 V,
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2
3
4
The Nexus AUX port runs up to 82 MHz.
MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs.
Limit the maximum frequency to approximately 16 MHz (VDDE = 2.25–3.0 V) or 20 MHz (VDDE = 3.0–3.6 V) to meet the timing
specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification.
5
The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly.
1
2
MCKO
4
5
3
MDO
MSEO
EVTO
Output Data Valid
Figure 10. Nexus Output Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
31
Freescale Semiconductor
Electrical Characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 11. Nexus TDI, TMS, TDO Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
3.13.4 External Bus Interface (EBI) Timing
Table 22 lists the timing information for the external bus interface (EBI).
1
Table 22. Bus Operation Timing
External Bus Frequency 2, 3
Characteristic
Spec
and
Description
Symbol
Unit
Notes
40 MHz
56 MHz
66 MHz
Min.
Max.
—
Min.
Max.
—
Min.
15.2
Max.
Signals are measured
1
CLKOUT period
TC
24.4
17.5
—
ns
at 50% VDDE
.
2
3
4
CLKOUT duty cycle
CLKOUT rise time
CLKOUT fall time
tCDC
tCRT
tCFT
tCOH
45%
—
55%
45%
—
55%
45% 55% TC
4
4
4
—
—
—
—
—
ns
ns
4
4
4
—
1.010
—
—
1.010
—
—
CLKOUT positive edge to output
1.010
EBTS = 0
EBTS = 1
signal invalid or Hi-Z (hold time)
—
—
—
ns
1.5
1.5
1.5
External bus interface
BG 5
Hold time selectable
via SIU_ECCR
[EBTS] bit.
BR 6
BB
CS[0:3]
ADDR[8:31]
DATA[0:31] 7
BDIP
5
OE
RD_WR
TA
TEA 8
TS
TSIZ[0:1]
WE/BE[0:3] 9
CLKOUT positive edge to output
signal valid (output delay)
tCOV
10.010
7.510
8.5
6.010
7.0
EBTS = 0
EBTS = 1
—
—
—
ns
11.0
External bus interface
BG 5
Output valid time
selectable via
SIU_ECCR
BR 6
BB
CS[0:3]
ADDR[8:31]
DATA[0:31] 7
BDIP
[EBTS] bit.
6
OE
RD_WR
TA
TEA 8
TS
TSIZ[0:1]
WE/BE[0:3] 9
MPC5554 Microcontroller Data Sheet, Rev. 4
33
Freescale Semiconductor
Electrical Characteristics
Characteristic
1
Table 22. Bus Operation Timing (continued)
External Bus Frequency 2, 3
Spec
and
Description
Symbol
Unit
Notes
40 MHz
56 MHz
66 MHz
Min.
Max.
Min.
Max.
Min.
Max.
Input signal valid to CLKOUT
positive edge (setup time)
External bus interface
ADDR[8:31]
DATA[0:31] 7
BG 6
7
tCIS
10.0
—
7.0
—
5.0
—
ns
BR 5
BB
RD_WR
TA
TEA 8
TS
CLKOUT positive edge to input
signal invalid (hold time)
External bus interface
ADDR[8:31]
DATA[0:31] 7
BG 6
8
tCIH
1.0
—
1.0
—
1.0
—
ns
BR 5
BB
RD_WR
TA
TEA 8
TS
1
2
EBI timing specified at: VDDE = 1.6–3.6 V (unless stated otherwise); TA = TL to TH; and CL = 30 pF with DSC = 0b10.
Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
132 MHz parts allow for 128 MHz system clock + 2% FM.
3
4
5
6
7
8
9
The external bus is limited to half the speed of the internal bus.
Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).
Internal arbitration.
External arbitration.
Due to pin limitations, the DATA[16:31] signals are not available on the 324 package.
Due to pin limitations, the TEA signal is not available on the 324 package.
Due to pin limitations, the WE/BE[2:3] signals are not available on the 324 package.
10 SIU_ECCR[EBTS] = 0 timings are tested and valid at VDDE = 2.25–3.6 V only; SIU_ECCR[EBTS] = 1 timings are tested and
valid at VDDE = 1.6–3.6 V.
MPC5554 Microcontroller Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
Voh_f
VDDE 2
Vol_f
CLKOUT
2
3
2
4
1
Figure 12. CLKOUT Timing
VDDE 2
CLKOUT
6
5
VDDE 2
5
Output
bus
VDDE 2
6
5
5
Output
signal
VDDE 2
6
Output
signal
VDDE 2
Figure 13. Synchronous Output Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
35
Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDDE 2
7
8
Input
bus
VDDE 2
7
8
Input
signal
VDDE 2
Figure 14. Synchronous Input Timing
3.13.5 External Interrupt Timing (IRQ Signals)
1
Table 23. External Interrupt Timing
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
IRQ pulse-width low
IRQ pulse-width high
IRQ edge-to-edge time 2
tIPWL
TIPWH
tICYC
3
3
6
—
—
—
tCYC
tCYC
tCYC
1
2
IRQ timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.
MPC5554 Microcontroller Data Sheet, Rev. 4
36
Freescale Semiconductor
Electrical Characteristics
IRQ
2
1
3
Figure 15. External Interrupt Timing
3.13.6 eTPU Timing
1
Table 24. eTPU Timing
Spec
Characteristic
eTPU input channel pulse width
eTPU output channel pulse width
Symbol
Min.
Max
Unit
1
2
tICPW
4
2 2
—
—
tCYC
tCYC
tOCPW
1
2
eTPU timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
2
eTPU
output
eTPU input
and TCRCLK
1
Figure 16. eTPU Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
37
Freescale Semiconductor
Electrical Characteristics
3.13.7 eMIOS Timing
1
Table 25. eMIOS Timing
Characteristic
Spec
Symbol
Min.
Max.
Unit
1
2
eMIOS input pulse width
eMIOS output pulse width
tMIPW
4
1 2
—
—
tCYC
tCYC
tMOPW
1
2
eMIOS timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
2
eMIOS
output
eMIOS input
1
Figure 17. eMIOS Timing
3.13.8 DSPI Timing
1
2
Table 26. DSPI Timing ’
80 MHz
Symbol
112 MHz
132 MHz
Spec
Characteristic
SCK cycle time3, 4
PCS to SCK delay5
After SCK delay6
SCK duty cycle
Unit
Min.
Max.
Min.
Max.
Min.
Max.
1
2
3
tSCK
tCSC
tASC
24.4 ns
23
2.9 ms
—
17.5 ns
15
2.1 ms 15.2 ns 1.7 ms
—
ns
ns
—
—
13
12
—
—
22
—
14
(tSCK 2) (tSCK 2) (tSCK 2) (tSCK 2) (tSCK 2) (tSCK 2)
4
5
6
tSDC
tA
ns
ns
ns
– 2 ns
+ 2 ns
– 2 ns
+ 2 ns
– 2 ns
+ 2 ns
Slave access time
(SS active to SOUT driven)
—
25
—
25
—
25
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
tDIS
—
25
—
25
—
25
7
8
PCSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
4
5
—
—
4
5
—
—
4
5
—
—
ns
ns
MPC5554 Microcontroller Data Sheet, Rev. 4
38
Freescale Semiconductor
Electrical Characteristics
1 2
Table 26. DSPI Timing ’ (continued)
80 MHz
112 MHz
132 MHz
Unit
Spec
Characteristic
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Data setup time for inputs
Master (MTFE = 0)
tSUI
20
2
–4
20
—
—
—
—
20
2
3
—
—
—
—
20
2
6
—
—
—
—
ns
ns
ns
ns
9
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
20
20
Data hold time for inputs
Master (MTFE = 0)
tHI
tSUO
tHO
–4
7
21
–4
—
—
—
—
–4
7
14
–4
—
—
—
—
–4
7
12
–4
—
—
—
—
ns
ns
ns
ns
10
11
12
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
—
—
—
—
5
25
18
5
—
—
—
—
5
25
14
5
—
—
—
—
5
25
13
5
ns
ns
ns
ns
Data hold time for outputs
Master (MTFE = 0)
–5
5.5
8
—
—
—
—
–5
5.5
4
—
—
—
—
–5
5.5
3
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–5
–5
–5
1
2
3
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types
of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: VDDEH = 3.0–5.25 V;TA = TL to TH;
and CL = 50 pF with SRC = 0b11.
Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
132 MHz parts allow for 128 MHz system clock + 2% FM.
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
4
5
6
7
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
MPC5554 Microcontroller Data Sheet, Rev. 4
39
Freescale Semiconductor
Electrical Characteristics
2
3
PCSx
1
4
SCK output
(CPOL=0)
4
SCK output
(CPOL=1)
10
9
Last data
SIN
First data
Data
Data
12
11
First data
Last data
SOUT
Figure 18. DSPI Classic SPI Timing—Master, CPHA = 0
PCSx
SCK output
(CPOL=0)
10
SCK output
(CPOL=1)
9
Data
Data
First data
Last data
SIN
12
11
SOUT
Last data
First data
Figure 19. DSPI Classic SPI Timing—Master, CPHA = 1
MPC5554 Microcontroller Data Sheet, Rev. 4
40
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
4
SCK input
(CPOL=0)
4
SCK input
(CPOL=1)
5
11
12
Data
6
First data
Last data
SOUT
9
10
First data
Data
Last data
SIN
Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 0
SS
SCK input
(CPOL=0)
SCK input
(CPOL=1)
11
5
6
12
Last data
Data
Data
SOUT
SIN
First data
10
9
Last data
First data
Figure 21. DSPI Classic SPI Timing—Slave, CPHA = 1
MPC5554 Microcontroller Data Sheet, Rev. 4
41
Freescale Semiconductor
Electrical Characteristics
3
PCSx
4
1
2
SCK output
(CPOL=0)
4
SCK output
(CPOL=1)
9
10
SIN
First data
Last data
Last data
Data
12
11
SOUT
First data
Data
Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 0
PCSx
SCK output
(CPOL=0)
SCK output
(CPOL=1)
10
9
SIN
Last data
First data
Data
12
Data
11
First data
Last data
SOUT
Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = 1
MPC5554 Microcontroller Data Sheet, Rev. 4
42
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
SCK input
(CPOL=0)
4
4
SCK input
(CPOL=1)
12
11
6
5
First data
9
Data
Data
Last data
10
SOUT
Last data
First data
SIN
Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 0
SS
SCK input
(CPOL=0)
SCK input
(CPOL=1)
11
5
6
12
Last data
First data
10
Data
Data
SOUT
SIN
9
First data
Last data
Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1
8
7
PCSS
PCSx
Figure 26. DSPI PCS Strobe (PCSS) Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
43
Freescale Semiconductor
Electrical Characteristics
3.13.9 eQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics
Spec
Rating
Symbol
Minimum
Typical
Maximum
Unit
1, 2
2
3
4
5
6
7
8
FCK period (tFCK = 1 fFCK
Clock (FCK) high time
Clock (FCK) low time
SDS lead / lag time
)
tFCK
2
—
—
—
—
—
—
—
17
tSYS_CLK
ns
tFCKHT
tFCKLT
tSDS_LL
tSDO_LL
tEQ_SU
tEQ_HO
tSYS_CLK 6.5
9 (tSYS_CLK 6.5)
tSYS_CLK 6.5
8 (tSYS_CLK 6.5)
ns
–7.5
–7.5
22
+7.5
+7.5
—
ns
SDO lead / lag time
ns
EQADC data setup time (inputs)
EQADC data hold time (inputs)
ns
1
—
ns
1
2
SS timing specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
varies depending on track delays, master pad delays, and slave pad delays.
FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
FCK
SDS
5
6
4
5
25th
1st (MSB)
2nd
26th
SDO
External device data sample at
FCK falling-edge
8
7
1st (MSB) 2nd
25th
26th
SDI
EQADC data sample at
FCK rising-edge
Figure 27. EQADC SSI Timing
MPC5554 Microcontroller Data Sheet, Rev. 4
44
Freescale Semiconductor
Mechanicals
4
Mechanicals
4.1
MPC5553546667 416 PBGA Pinout
Figure 28, Figure 29, and Figure 30 show the pinout for the MPC5553546667 416 PBGA package. The
alternate Fast Ethernet Controller (FEC) signals are multiplexed with the data calibration bus signals.
NOTE
The MPC5500 devices are pin compatible for software portability and use
the primary function names to label the pins in the BGA diagram. Although
some devices do not support all the primary functions shown in the BGA
diagram, the muxed and GPIO signals on those pins remain available. See
the signals chapter in the device reference manual for the signal muxing.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ETRIG ETPUB ETPUB ETPUB ETPUB GPIO
AN1
AN5
VRH
AN23 AN27 AN28 AN35 VSSA0 AN15
AN22 AN26 AN31 AN32 VSSA0 AN14
MDO11 MDO8 VDD VDD33 VSS
A
B
VSS VSTBY AN37 AN11 VDDA1 AN16
VDD VSS AN36 AN39 AN19 AN20
A
1
18 20 24 27 205
REF
BYPC
ETRIG ETPUB ETPUB ETPUB ETPUB
MDO10 MDO7 MDO4 MDO0 VSS VDDE7
AN0
AN4
AN3
B
0
21
25
28
31
ETPUB ETPUB ETPUB ETPUB
AN21
AN7
AN2
VRL
AN6
AN25 AN30 AN33 VDDA0 AN13
VDDEH
MDO9 MDO6 MDO3 MDO1 VSS VDDE7 VDD
C
D
E
VDD33 VDD
ETPUA ETPUA
VSS
VDD
AN8
VSS
VDD
AN17 VSSA1
AN38 AN9
C
19
22
26
30
ETPUB ETPUB ETPUB ETPUB
VDDEH
8
AN10 AN18
AN24 AN29 AN34
AN12
MDO5 MDO2
VSS VDDE7 TCK
TDI
D
30
31
9
16
17
23
29
ETPUA ETPUA VDDEH
28 29
VDDE7 TMS
TDO
TEST
E
1
ETPUA ETPUA ETPUA VDDEH
MSEO0 JCOMP EVTI EVTO
F
F
24
27
26
1
ETPUA ETPUA ETPUA ETPUA
GPIO ETPUB
MSEO1 MCKO
G
H
J
G
H
23
22
25
21
204
15
ETPUA ETPUA ETPUA ETPUA
20 19 18 17
GPIO ETPUB ETPUB
203 14 13
RDY
ETPUA ETPUA ETPUA ETPUA
16 15 14 13
VDDEH ETPUB ETPUB ETPUB
J
6
12
11
9
ETPUA ETPUA ETPUA ETPUA
ETPUB ETPUB ETPUB ETPUB
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7 VDDE7 VDDE7 VDDE7
K
K
12
11
10
9
10
8
7
5
ETPUA ETPUA ETPUA ETPUA
ETPUB ETPUB ETPUB ETPUB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7
VSS VDDE7
VSS VDDE7
L
L
8
7
6
5
6
4
3
2
ETPUA ETPUA ETPUA ETPUA
TCRCLK ETPUB ETPUB
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
SINB
M
N
P
M
N
4
3
2
1
B
1
0
ETPUA TCRCLK
SOUTB PCSB3 PCSB0 PCSB1
PCSA3 PCSB4 SCKB PCSB2
PCSB5 SOUTA SINA SCKA
PCSA1 PCSA0 PCSA2 VPP
PCSA4 TXDA PCSA5 VFLASH
BDIP
TEA
0
A
VSS
VSS
VSS
VSS
VSS
VSS
CS3
CS2
CS1
CS0
P
R
T
WE3
WE2
WE1
WE0
R
VDDE2 VSS VDDE2 VDDE2 VDDE2 VDDE2 VSS
VSS VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS
VDDE2 TSIZ0 RD_WR VDDE2
ADDR
T
U
V
TSIZ1
TA
VDD33
U
16
ADDR ADDR
18 17
ADDR
8
RST
CNTXC RXDA RSTOUT
CFG
TS
V
ADDR ADDR ADDR ADDR
RXDB CNRXC TXDB RESET
W
Y
W
Y
20
19
9
10
ADDR ADDR ADDR
WKP BOOT VRC
VSS
SYN
NC
VDDE2
Note:
No connect. AC22 & AD23 reserved
22
21
11
CFG
CFG1
VSS
ADDR ADDR ADDR ADDR
VDDEH PLL
BOOT
EXTAL
XTAL
AA
AA
AB
AC
AD
AE
AF
24
23
13
12
6
CFG1 CFG0
ADDR ADDR ADDR
VRC
CTL
PLL
CFG0
VDD
AB VDDE2
25
15
14
ADDR ADDR ADDR
DATA DATA
26 28
DATA DATA DATA DATA
DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH
VDD
SYN
VDDE2
VDDE2
VDDE5
NC
VSS
NC
VDD VRC33
VSS
AC
AD
AE
VSS
VDD
26
27
31
30
31
8
10
12
14
2
8
12
21
4
ADDR ADDR
DATA DATA DATA DATA
24 25 27 29
GPIO DATA DATA DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
VDD33
CNTXA VDDE5
VDD VDD33
VSS
VDD
28
30
207
9
11
13
15
3
6
10
15
13
17
16
22
19
ADDR
29
DATA DATA DATA DATA DATA DATA DATA DATA
17
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
1
OE
BR
BG
CNRXA VDDE5 CLKOUT VSS
VDD
VSS
VDD
19
VDDE2
5
21
23
0
2
4
6
VDDE2
11
5
9
23
DATA DATA
DATA DATA GPIO DATA DATA
DATA DATA
5
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
ENG
CNTXB CNRXB VDDE5
CLK
BB
14
VSS
26
AF VSS
1
VDD
2
16
18
20
22
206
1
3
7
0
4
7
11
14
18
20
3
4
6
7
8
9
10
12
13
15
16
17
18
19
20
21
22
23
24
25
Figure 28. MPC5553546667 416 Package
MPC5554 Microcontroller Data Sheet, Rev. 4
45
Freescale Semiconductor
Mechanicals
1
2
3
4
5
6
7
8
9
10
11
12
13
AN1
AN5
VRH
AN23 AN27 AN28 AN35
AN22 AN26 AN31 AN32
A
B
C
D
E
F
VSS VSTBY AN37
VDD VSS AN36 AN39 AN19 AN20
AN11 VDDA1 AN16
REF
BYPC
AN0
AN4
AN3
AN21
AN7
AN2
VRL
AN6
AN25 AN30 AN33
AN24 AN29 AN34
VDD33 VDD
ETPUA ETPUA
VSS
VDD
AN8
VSS
VDD
AN17 VSSA1
AN38 AN9
AN10 AN18
30
31
ETPUA ETPUA VDDEH
28 29
1
ETPUA ETPUA ETPUA VDDEH
24 27 26
1
ETPUA ETPUA ETPUA ETPUA
G
H
J
23
22
25
21
ETPUA ETPUA ETPUA ETPUA
20 19 18 17
ETPUA ETPUA ETPUA ETPUA
16 15 14 13
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
12
11
10
9
ETPUA ETPUA ETPUA ETPUA
L
8
7
6
5
ETPUA ETPUA ETPUA ETPUA
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
M
N
P
4
3
2
1
ETPUA TCRCLK
BDIP
TEA
0
A
CS3
CS2
CS1
CS0
R
T
WE3
WE2
WE1
WE0
VDDE2 VSS VDDE2 VDDE2
VSS VDDE2 VDDE2 VDDE2
VDDE2 TSIZ0 RD_WR VDDE2
ADDR
U
V
TSIZ1
TA
VDD33
16
ADDR ADDR
18 17
ADDR
8
TS
ADDR ADDR ADDR ADDR
W
Y
20
19
9
10
ADDR ADDR ADDR
VDDE2
22
21
11
ADDR ADDR ADDR ADDR
AA
24
23
13
12
ADDR ADDR ADDR
AB VDDE2
25
15
14
ADDR ADDR ADDR
DATA DATA
26 28
DATA DATA DATA DATA
VDDE2
VDDE2
AC
AD
AE
VSS
VDD
26
27
31
30
31
8
10
ADDR ADDR
DATA DATA DATA DATA
24 25 27 29
GPIO DATA DATA DATA
VDD33
VSS
VDD
28
30
207
9
11
13
ADDR
29
DATA DATA DATA DATA DATA DATA DATA DATA
OE
BR
VSS
VDD
17
19
VDDE2
5
21
23
0
2
4
6
VDDE2
11
DATA DATA
DATA DATA GPIO DATA DATA
DATA DATA
5
AF VSS
1
VDD
2
16
18
20
22
206
1
3
7
3
4
6
7
8
9
10
12
13
Figure 29. MPC5553546667 416 Package Left Side (view 1 of 2)
MPC5554 Microcontroller Data Sheet, Rev. 4
46
Freescale Semiconductor
Mechanicals
14
15
16
17
18
19
20
21
22
MDO11 MDO8 VDD VDD33 VSS
VSS VDDE7
23
24
25
26
ETRIG ETPUB ETPUB ETPUB ETPUB GPIO
1
VSSA0 AN15
VSSA0 AN14
VDDA0 AN13
A
18 20 24 27 205
ETRIG ETPUB ETPUB ETPUB ETPUB
0
MDO10 MDO7 MDO4 MDO0
B
21
25
28
31
ETPUB ETPUB ETPUB ETPUB
19
MDO9 MDO6 MDO3 MDO1
VSS VDDE7 VDD
VSS VDDE7 TCK TDI
C
22
26
30
VDDEH
AN12
9
ETPUB ETPUB ETPUB ETPUB
16
VDDEH
MDO5 MDO2
D
17
23
29
8
VDDE7 TMS
TDO
TEST
EVTO
E
MSEO0 JCOMP EVTI
F
GPIO ETPUB
MSEO1 MCKO
G
H
204
15
GPIO ETPUB ETPUB
203 14 13
RDY
VDDEH ETPUB ETPUB ETPUB
J
6
12
11
9
ETPUB ETPUB ETPUB ETPUB
VDDE7 VDDE7 VDDE7 VDDE7
K
10
8
7
5
ETPUB ETPUB ETPUB ETPUB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7
VSS VDDE7
VSS VDDE7
L
6
4
3
2
TCRCLK ETPUB ETPUB
SINB
M
N
B
1
0
SOUTB PCSB3 PCSB0 PCSB1
PCSA3 PCSB4 SCKB PCSB2
PCSB5 SOUTA SINA SCKA
PCSA1 PCSA0 PCSA2 VPP
PCSA4 TXDA PCSA5 VFLASH
VSS
VSS
VSS
VSS
VSS
VSS
P
R
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
T
U
RST
CNTXC RXDA RSTOUT
CFG
V
RXDB CNRXC TXDB RESET
W
Y
WKP BOOT
CFG CFG1
VRC
VSS
VSS
SYN
NC
Note:
No connect. AC22 & AD23 reserved
VDDEH PLL
BOOT
EXTAL
XTAL
AA
AB
AC
AD
AE
AF
6
CFG1 CFG0
VRC
CTL
PLL
CFG0
VDD
DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH
VDD
SYN
VDDE5
NC
VSS
NC
VDD VRC33
VSS
12
14
2
8
12
21
4
DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
CNTXA VDDE5
VDD VDD33
15
3
6
10
15
17
16
22
19
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
1
BG
CNRXA VDDE5 CLKOUT VSS
VDD
5
9
13
23
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
ENG
CNTXB CNRXB VDDE5
CLK
BB
14
VSS
26
0
4
7
11
14
18
20
15
16
17
18
19
20
21
22
23
24
25
Figure 30. MPC5553546667 416 Package Right Side (view 2 of 2)
Figure 31. MPC5567 416 Package
MPC5554 Microcontroller Data Sheet, Rev. 4
47
Freescale Semiconductor
Mechanicals
The package drawings of the MPC55 208-pin MAP BGA are shown below.
Figure 32. 208-Pin Package
MPC5554 Microcontroller Data Sheet, Rev. 4
48
Freescale Semiconductor
Mechanicals
Figure 32. MPC55 208 MAP BGA Package (continued)
MPC5554 Microcontroller Data Sheet, Rev. 4
49
Freescale Semiconductor
Mechanicals
The package drawings of the 324-pin TEPBGA package are shown in Figure 33.
Figure 33. 324 TEPBGA Package
MPC5554 Microcontroller Data Sheet, Rev. 4
50
Freescale Semiconductor
Mechanicals
Figure 33. 324 TEPBGA Package (continued)
MPC5554 Microcontroller Data Sheet, Rev. 4
51
Freescale Semiconductor
Mechanicals
4.2
MPC5554 416-Pin Package Dimensions
The package drawings of the MPC5554 416 pin TEPBGA package are shown in Figure 34.
Figure 34. MPC5554 416 TEPBGA Package
MPC5554 Microcontroller Data Sheet, Rev. 4
52
Freescale Semiconductor
Mechanicals
Figure 34. MPC5554 416 TEPBGA Package (continued)
MPC5554 Microcontroller Data Sheet, Rev. 4
53
Freescale Semiconductor
Revision History for the MPC5554 Data Sheet
5
Revision History for the MPC5554 Data Sheet
The history of revisions made to this data sheet are described in this section.
5.1
Changes between Revision 3 and Revision 4
Location
Description of Changes
Added the following paragraph in Section 3.7, “Power-Up/Down Sequencing”:
“During initial power ramp-up, when Vstby is 0.6v or above. a typical current of 1-3mA and
maximum of 4mA may be seen until VDD is applied. This current will not reoccur until Vstby is
lowered below Vstby min. specification”.
Section 3.7, “Power-Up/Down
Sequencing”
Moved Figure 2 (fISTBY Worst-case Specifications) “ISTBY Worst-case Specifications” to
Section 3.7, “Power-Up/Down Sequencing”.
Removed the footnote “Figure 3 shows an illustration of the IDD_STBY values interpolated for
these temperature values”.
Changed the footnote attached to IDD_STBY” to “The current specification relates to average
standby operation after SRAM has been loaded with data. For power up current see
Section 3.7, “Power-Up/Down Sequencing”,Figure 2 (fISTBY Worst-case Specifications).”
Section 3.8, “DC Electrical
Specifications”
In Table 9 (DC Electrical Specifications (TA = TL to TH)) the Characteristic “Refer to Figure 3 for
an interpolation of this data” changed to “RAM standby current”.
5.2
Changes between Revision 2 and Revision 3
The substantive changes incorporated in MPC5554 Data Sheet Rev. 2.0 to produce Rev. 3.0 are listed in
Table 28. The changes are listed in sequential page number order.
Table 28. Changes Between Rev. 2.0 and 3.0
Location
Description of Changes
Throughout:
Changed ‘TA = TL – TH’ to ‘TA = TL to TH.’
Title page:
Changed the Revision number from 2 to 3. Changed the date. Made the same change in the lower left corner of the
back page.
Section 1, “Overview”
• Fourth paragraph, First sentence: Deleted ‘of the MPC5500 family’; Second to last sentence: Deleted ‘can’.
• Fifth paragraph, First sentence: Replaced ‘MPC5500 family’ with ‘MPC5554’; Last sentence: Replaced ‘can be’
with ‘is’.
• Sixth paragraph, First sentence: Replaced ‘MPC5500 family’ with ‘MPC5554’;
• Second to last paragraph: Rewrote to read: The MCU has an on-chip enhanced queued dual analog-to-digital
converter (eQADC). The 416 package has 40-channels.
Section 3.2.1, “General Notes for Specifications at Maximum Junction Temperature
Updated the address of Semiconductor Equipment and Materials International
3081 Zanker Rd.
San Jose, CA., 95134
(408) 943-6900
MPC5554 Microcontroller Data Sheet, Rev. 4
54
Freescale Semiconductor
Revision History for the MPC5554 Data Sheet
Table 28. Changes Between Rev. 2.0 and 3.0 (continued)
Description of Changes
Location
Section 3.7, “Power-Up/Down Sequencing
Last paragraph: Changed the first sentence FROM , , , the voltage on the pins goes to high-impedance until . . .
TO. . .the pins go to a high-impedance state until . . .
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)”
Last sentence: Changed from: ‘This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and
can cause the 1.5 V supply to decrease below its specification, is reset properly.’
To: ‘This ensures that the digital 1.5 V logic, which is reset only by an ORed POR and can cause the 1.5 V supply
to decrease less than its specification, resets correctly.’
Section 4.1, “MPC5553546667 416 PBGA Pinout”
Added the following NOTE before the 416 BGA Map:
NOTE
The MPC5500 devices are pin compatible for software portability and use the primary
function names to label the pins in the BGA diagram. Although some devices do not support
all the primary functions shown in the BGA diagram, the muxed and GPIO signals on those
pins remain available. See the signals chapter in the device reference manual for the signal
muxing.
Table 5 (ESD Ratings ,) ESD Ratings:
Changed footnote 2 from:
• ‘Device failure is defined as: ‘If after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete DC parametric and functional testing will be performed per applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.’
to:
• Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.
Table 6 (VRC and POR Electrical Specifications) VCR/POR Electrical Specifications:
• Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are VPOR15, VPOR33, and VPOR5
.
On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power
supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down,
assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.
• Reformatted columns.
Table 9 (DC Electrical Specifications (TA = TL to TH)) DC Electrical Specifications:
• Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and
VDDE3 have a range of 1.6–3.6 V if SIU_ECCR[EBTS] =1.
• Added (TA = TL to TH) to the table title.
Table 14 (Flash Program and Erase Specifications (TA = TL to TH)) Flash Program and Erase Specifications (TA = TL to TH)
• Footnote 1, Changed ‘Typical program and erase times assume nominal supply values and operation at 25 oC’
to ‘Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values..’
Table 17 (Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)) Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)
• Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Table 19 (Reset and Configuration Pin Timing) Reset and Configuration Pin Timing:
• Footnote 1: Removed VDD = 1.35–1.65 V.
MPC5554 Microcontroller Data Sheet, Rev. 4
55
Freescale Semiconductor
Revision History for the MPC5554 Data Sheet
Table 28. Changes Between Rev. 2.0 and 3.0 (continued)
Description of Changes
Location
Table 20 (JTAG Pin AC Electrical Characteristics) JTAG Pin AC Electrical Characteristics
• Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Table 22 (Bus Operation Timing) Bus Operation Timing:
• External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts
allow for 128 MHz system clock + 2% FM.
• Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.
• Specifications 7 and 8: Removed EBI signals BDIP, OE, TSIZ[0:1], WE/BE[0:3].
• Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
• Footnote 8: Changed EBTS to SIU_ECCR[EBTS].
Table 23 (External Interrupt Timing) External Interrupt Timing (IRQ Signals)
• Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 24 (eTPU Timing) eTPU Timing
• Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 25 (eMIOS Timing) eMIOS Timing
• Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 26 (DSPI Timing’) DSPI Timing:
• Footnote 1, changed ‘VDDEH = 3.0–5.5 V;’ to ‘VDDEH = 3.0–5.25 V;’
• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts allow for
128 MHz system clock + 2% FM.
• Spec 1: SCK cycle time; Changed to 80 MHz minimum column from 25 to 24.4; 112 MHz minimum column from
17.9 to 17.5; 112 MHz maximum column from 2.0 to 2.1.
Table 27 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics
• Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
MPC5554 Microcontroller Data Sheet, Rev. 4
56
Freescale Semiconductor
THIS PAGE IS INTENTIONALLY BLANK
MPC5554 Microcontroller Data Sheet, Rev. 4
57
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Document Number: MPC5554
Rev. 4
5/2012
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