MPC5602BEVLL [NXP]
32-BIT, FLASH, 64MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100;型号: | MPC5602BEVLL |
厂家: | NXP |
描述: | 32-BIT, FLASH, 64MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100 时钟 微控制器 外围集成电路 |
文件: | 总72页 (文件大小:971K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604BC
Rev. 4, 08/2009
MPC5604B/C
208 MAPBGA
(17 x 17 x 1.7 mm)
MPC5604B/C
Microcontroller Data Sheet
144 LQFP
(20 x 20 x 1.4 mm)
100 LQFP
(14 x 14 x 1.4 mm)
32-bit MCU family built on the Power Architecture™ for
automotive body electronics applications
•
Up to 6 enhanced full CAN (FlexCAN) modules
with configurable buffers
•
•
1 inter IC communication interface (I2C) module
Features:
Up to 123 configurable general purpose pins
supporting input and output operations (package
dependent)
•
Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture™
embedded category
•
Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
•
Up to 6 periodic interrupt timers (PIT) with 32-bit
counter resolution
instructions, it is possible to achieve significant
code size footprint reduction.
•
•
1 System Module Timer (STM)
•
Up to 512 Kbytes on-chip flash supported with the
flash controller
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
•
•
Up to 48 Kbytes on-chip SRAM
•
•
Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity
•
Interrupt controller (INTC) with 148 interrupt
vectors, including 16 external interrupt sources and
18 external interrupt/wakeup sources
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
•
•
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus
masters
•
•
Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
•
•
•
10-bit analog-to-digital converter (ADC)
3 serial peripheral interface (DSPI) modules
Up to 4 serial communication interface (LINFlex)
modules
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1
2
General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 29
4.11.2 Flash power supply DC characteristics . . . . . . 31
4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 31
4.12 Electromagnetic compatibility (EMC) characteristics. . 32
4.12.1 Designing hardened software to avoid noise
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Device blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Device block summary . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .11
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description
12
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .12
4.5 Recommended operating conditions . . . . . . . . . . . . . .13
4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .15
4.6.1 Package thermal characteristics . . . . . . . . . . . .15
4.6.2 Power considerations. . . . . . . . . . . . . . . . . . . . .15
4.7 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .16
4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.7.2 I/O input DC characteristics. . . . . . . . . . . . . . . .17
4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .17
4.7.4 Output pin transition times. . . . . . . . . . . . . . . . .20
4.7.5 I/O pad current specification . . . . . . . . . . . . . . .21
4.8 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .23
4.9 Power management electrical characteristics. . . . . . . .25
4.9.1 Voltage regulator electrical characteristics . . . .25
4.9.2 Voltage monitor electrical characteristics. . . . . .27
4.10 Low voltage domain power consumption . . . . . . . . . . .28
4.11 Flash memory electrical characteristics . . . . . . . . . . . .29
3
4
problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 32
4.12.3 Absolute maximum ratings (electrical sensitivity)33
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.14 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.15 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 39
4.16 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.17 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 42
4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 44
4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 50
4.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 51
4.18.5 ADC electrical characteristics . . . . . . . . . . . . . 52
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 60
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5
6
7
Appendix A
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MPC5604B/C Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
General description
1
General description
1.1
Introduction
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture™ embedded category. This
document describes the features of the family and options available within the family members, and highlights important
1
electrical and physical characteristics of the device .
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers.
It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5604B/C automotive controller
family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding)
APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized
for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices
and is supported with software drivers, operating systems and configuration code to assist with users implementations.
1
Table 1. MPC5604B/C device comparison
Device
Feature
MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560
2BxLL 2BxLQ 2CxLL 3BxLL 3BxLQ 3CxLL 4BxLL 4BxLQ 4BxMG 4CxLL
CPU
e200z0h
Execution
speed2
Static - 64 MHz
Code Flash
Data Flash
RAM
256 KB
384 KB
512 KB
64 KB (4 × 16 KB)
24 KB
32 KB
28 KB
40 KB
8-entry
32 KB
48 KB
MPU
ADC
28 ch,
10-bit
36 ch,
10-bit
28 ch, 10-bit
36 ch,
10-bit
28 ch,
10-bit
28 ch,
10-bit
36 ch,
10-bit
36 ch,
10-bit
28 ch,
10-bit
CTU
Yes
Total timer
I/O3
28 ch,
16-bit
56 ch,
16-bit
28 ch, 16-bit
56ch,
16-bit
28 ch, 16-bit
56 ch, 16-bit
28 ch,
16-bit
eMIOS
• PWM + MC
+ IC/OC4
5 ch
20 ch
3 ch
10 ch
40 ch
6 ch
5 ch
5 ch
20 ch
3 ch
10 ch
40 ch
6 ch
5 ch
5 ch
20 ch
3 ch
10 ch
40 ch
10 ch
40 ch
6 ch
5 ch
• PWM +
IC/OC4
20 ch
20 ch
20 ch
• IC/OC4
3 ch
4
3 ch
4
6 ch
4
3 ch
4
SCI (LINFlex)
SPI (DSPI)
3
2
4
3
3
CAN
6
6
3
3
6
6
(FlexCAN)
1.For a correct use of the datasheet, it’s recommended of referring to the errata sheet.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
3
General description
1
Table 1. MPC5604B/C device comparison (continued)
Device
Feature
MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560
2BxLL 2BxLQ 2CxLL 3BxLL 3BxLQ 3CxLL 4BxLL 4BxLQ 4BxMG 4CxLL
I2C
1
32 kHz
Yes
oscillator
GPIO5
79
123
79
79
123
79
79
123
123
79
Debug
JTAG
Nexus2+ JTAG
Package
100
LQFP
144
LQFP
100
LQFP
100
LQFP
144
LQFP
100
LQFP
100
LQFP
144
LQFP
208 MA
PBGA6
100
LQFP
1
Feature set dependent on selected peripheral multiplexing—table shows example implementation
Based on 105 °C ambient operating temperature
2
3
4
5
6
Refer to eMIOS section of device reference manual for information on the channel configuration and functions
IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter
I/O count based on multiplexing with peripherals
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
4
Freescale Semiconductor
Device blocks
2
Device blocks
2.1
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
Figure 1. MPC5604B/C series block diagram
RAM
48 KB
Code Flash DataFlash
512 KB 64 KB
TCU
JTAG
JTAG Port
Nexus Port
Instructions
(Master)
SRAM
Flash
Controller
e200z0h
Nexus 2+
Nexus
Controller
Data
NMI
(Slave)
(Master)
SIUL
Voltage
Regulator
(Slave)
Interrupt requests
from peripheral
blocks
(Slave)
NMI
MPU
Registers
INTC
Clocks
CMU
FMPLL
RTC
RGM
CGM
MEM
PCU
SSCM
STM
PIT
BAM
SWT
ECSM
Peripheral Bridge
2 x
SIUL
36 Ch.
ADC
4 x
LINFlex
3 x
DSPI
6 x
FlexCAN
2
CTU
I C
eMIOS
Reset Control
Interrupt
Request
External
Interrupt
Request
IMUX
GPIO &
Pad Control
. . .
. . .
. . .
. . .
. . .
I/O
Legend:
ADC
BAM
CAN
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network (FlexCAN)
Clock Generation Module
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
MEM
MPU
Nexus
NMI
PCU
PIT
Mode Entry Module
Memory Protection Unit
NexuS Development Interface (NDI) Level
Non-Maskable Interrupt
Power Control Unit
Periodic Interrupt Timer
Reset Generation Module
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Test Control Unit
CGM
CMU
CTU
DSPI
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
LINFlex
RGM
RTC
SIUL
SRAM
SSCM
STM
SWT
TCU
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
5
Device blocks
2.2
Device block summary
Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the
presence and number of blocks varies by device and package.
Table 2. MPC5604B/C series block summary
Block
Function
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter
Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module (CGM) Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Cross triggering unit (CTU)
Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINflex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Mode entry module (MC_ME)
Provides hardware access control for all memory references generated in a
device
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Nexus development interface
(NDI)
Provides real-time development support capabilities in compliance with the
IEEE-ISTO 5001-2003 standard
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
6
Freescale Semiconductor
Device blocks
Table 2. MPC5604B/C series block summary (continued)
Function
Block
Periodic interrupt timer (PIT)
Power control unit (PCU)
Produces periodic interrupts and triggers
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Real-time counter (RTC)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
Reset generation module (RGM) Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit (SIU)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR and operating
system tasks
System watchdog timer (SWT)
Test control unit (TCU)
Provides protection from runaway code
An extension of the JTAG controller module, the TCU provides the means to test
chip functionality and connectivity while remaining transparent to system logic
when not in test mode.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
7
Package pinouts
3
Package pinouts
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,
please refer to the device reference manual.
Figure 2. LQFP 144-pin configuration (top view)
WKUP[11] / SCL / LIN0RX / GPIO[19] / PB[3]
WKUP[13] / LIN2RX / GPIO[41] / PC[9]
EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14]
CS0_2 / E0UC[15] / GPIO[47] / PC[15]
WKUP[18] / E1UC[14] / GPIO[101] / PG[5]
E1UC[13] / GPIO[100] / PG[4]
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
PA[11] / GPIO[11] / E0UC[11] / SCL
PA[10] / GPIO[10] / E0UC[10] / SDA
PA[9] / GPIO[9] / E0UC[9] / FAB
PA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0]
PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ[2]
PE[13] / GPIO[77] / SOUT2 / E1UC[20]
PF[14] / GPIO[94] / CAN1TX / CAN4TX / E1UC[27]
PF[15] / GPIO[95] / CAN1RX / CAN4RX / EIRQ[13]
VDD_HV
WKUP[17] / E1UC[12] / GPIO[99] / PG[3]
E1UC[11] / GPIO[98] / PG[2]
WKUP[3] / E0UC[2] / GPIO[2] / PA[2]
WKUP[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0]
WKUP[2] / NMI / E0UC[1] / GPIO[1] / PA[1]
CAN5TX / E0UC[17] / GPIO[65] / PE[1]
CAN3TX / E0UC[22] / CAN2TX / GPIO[72] / PE[8]
WKUP[7] / E0UC[23] / CAN3RX / CAN2RX / GPIO[73] / PE[9]
EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10]
WKUP[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0]
WKUP[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11]
VSS_HV
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS_HV
PG[0] / GPIO[96] / CAN5TX / E1UC[23]
PG[1] / GPIO[97] / CAN5RX / E1UC[24] / EIRQ[14]
PH[3] / GPIO[115] / E1UC[5] / CS0_1
PH[2] / GPIO[114] / E1UC[4] / SCK1
PH[1] / GPIO[113] / E1UC[3] / SOUT1
PH[0] / GPIO[112] / E1UC[2] / SIN1
PG[12] / GPIO[108] / E0UC[26]
PG[13] / GPIO[109] / E0UC[27]
144 LQFP
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PA[3] / GPIO[3] / E0UC[3] / EIRQ[0]
PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ANX[3]
PD[15] / GPIO[63] / CS2_1 / ANS[7] / E0UC[27]
PB[14] / GPIO[30] / CS3_0 / E0UC[6] / ANX[2]
PD[14] / GPIO[62] / CS1_1 / ANS[6] / E0UC[26]
PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1]
PD[13] / GPIO[61] / CS0_1 / ANS[5] / E0UC[25]
PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0]
PD[12] / GPIO[60] / CS5_0 / ANS[4] / E0UC[24]
PB[11] / GPIO[27] / E0UC[3] / ANS[3] / CS0_0
PD[11] / GPIO[59] / ANP[15]
PD[10] / GPIO[58] / ANP[14]
PD[9] / GPIO[57] / ANP[13]
PB[7] / GPIO[23] / ANP[3]
PB[6] / GPIO[22] / ANP[2]
PB[5] / GPIO[21] / ANP[1]
VDD_HV_ADC
VSS_HV_ADC
SCK_2 / E1UC[18] / GPIO[105] / PG[9]
EIRQ[15] / CS0_2 / E1UC[17] / GPIO[104] / PG[8]
WKUP[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11]
MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10]
E1UC[16] / GPIO[103] / PG[7]
E1UC[15] / GPIO[102] / PG[6]
CAN0TX / GPIO[16] / PB[0]
WKUP[4] / CAN0RX / GPIO[17] / PB[1]
CS5_0 / CAN3RX / CAN2RX / GPIO[89] / PF[9]
CS4_0 / CAN3TX / CAN2TX / GPIO[88] / PF[8]
E1UC[25] / GPIO[92] / PF[12]
74
73
LIN1TX / GPIO[38] / PC[6]
Note:
Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
8
Freescale Semiconductor
Package pinouts
Figure 3. LQFP 100-pin configuration (top view)
WKUP[11] / SCL / LIN0RX / GPIO[19] / PB[3]
WKUP[13] / LIN2RX / GPIO[41] / PC[9]
EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14]
CS0_2 / E0UC[15] / GPIO[47] / PC[15]
WKUP[3] / E0UC[2] / GPIO[2] / PA[2]
WKUP[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0]
WKUP[2] / NMI / E0UC[1] / GPIO[1] / PA[1]
CAN5TX / E0UC[17] / GPIO[65] / PE[1]
CAN3TX / E0UC[22] /CAN2TX / GPIO[72] / PE[8]
WKUP[7] / CAN3RX / E0UC[23] /CAN2RX / GPIO[73] / PE[9]
EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10]
WKUP[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0]
WKUP[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11]
VSS_HV
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11] / GPIO[11] / E0UC[11] / SCL
PA[10] / GPIO[10] / E0UC[10] / SDA
PA[9] / GPIO[9] / E0UC[9] / FAB
PA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0]
PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ [2]
VDD_HV
VSS_HV
PA[3] / GPIO[3] / E0UC[3] / EIRQ[0]
PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ANX[3]
PD[15] / GPIO[63] / CS2_1 / ANS[7] / E0UC[27]
PB[14] / GPIO[30] / CS3_ 0 / E0UC[6] / ANX[2]
PD[14] / GPIO[62] / CS1_1 / ANS[6] / E0UC[26]
PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1]
PD[13] / GPIO[61] / CS0_1 / ANS[5] / E0UC[25]
PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0]
PD[12] / GPIO[60] / CS5_0 / ANS[4] / E0UC[24]
PB[11] / GPIO[27] / E0UC[3] / ANS[3] / CS0_0
PD[11] / GPIO[59] / ANP[15]
PD[10] / GPIO[58] / ANP[14]
PD[9] / GPIO[57] / ANP[13]
PB[7] / GPIO[23] / ANP[3]
PB[6] / GPIO[22] / ANP[2]
PB[5] / GPIO[21] / ANP[1]
VDD_HV_ADC
VSS_HV_ADC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
WKUP[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11]
MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10]
CAN0TX / GPIO[16] / PB[0]
WKUP[4] / CAN0RX / GPIO[17] / PB[1]
LIN1TX / GPIO[38] / PC[6]
Note:
Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
9
Electrical characteristics
1
2
3
4
NC
5
6
7
8
9
10
NC
NC
NC
NC
11
12
NC
13
PE[15]
PG[15]
PE[14]
PG[10]
PG[1]
PH[0]
VDD_HV
MDO3
NC
14
15
NC
16
NC
PC[8]
PC[9]
PC[13]
PB[2]
NC
PH[8]
PE[6]
PH[7]
PH[6]
PH[4]
PH[5]
PE[5]
PE[4]
PC[5]
PC[4]
PE[3]
PE[2]
PC[0]
PH[9]
VSS_LV
NC
PC[2]
PC[3]
PA[5]
PA[6]
NC
A
B
C
D
E
F
A
B
C
D
E
F
NC
PC[12]
PE[7]
NC
PH[10]
PC[1]
PG[11]
NC
PG[14]
PE[12]
PF[14]
PG[0]
PH[1]
NC
PA[11]
PA[9]
PE[13]
PA[10]
PA[8]
PA[7]
PC[14] VDD_HV
PB[3]
PC[15]
PG[3]
PA[1]
PE[10]
NC
NC
VDD_LV VDD_HV
NC
PG[4]
PE[0]
PE[9]
PG[5]
PA[2]
PE[8]
PG[2]
PE[1]
PA[0]
NC
PF[15] VDD_HV
PH[3]
NC
PH[2]
MSEO
MDO1
NC
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
G
H
J
G
H
J
VSS_HV PE[11] VDD_HV
MDO2
NC
MDO0
NC
RESET VSS_LV
NC
NC
EVTI
PG[9]
PG[7]
PB[1]
PF[8]
PF[12]
NC
NC
PG[8]
PG[6]
PF[9]
NC
VDD_BV VDD_LV
NC
PG[12]
PD[15]
PD[13]
PD[10]
PA[3]
PD[14]
PD[12]
PD[9]
PB[6]
PG[13]
PB[14]
PB[12]
PD[11]
PB[7]
PB[5]
PB[4]
16
K
L
K
L
NC
PC[10]
PB[0]
PC[7]
PF[10]
NC
EVTO
PC[11]
NC
PB[15]
PB[13]
PB[11]
PD[3]
PD[4]
PD[5]
13
M
N
P
R
T
M
N
P
R
T
NC
NC
PA[4]
VSS_LV
VDD_LV
PA[13]
PA[12]
7
EXTAL VDD_HV
PF[0]
PF[1]
PF[3]
PF[2]
10
PF[4]
PF[5]
PF[7]
PF[6]
11
NC
VDD_HV
_ADC
NC
PA[14]
XTAL
NC
NC
8
PB[10]
PD[0]
PD[2]
PD[1]
12
OSC32K
_XTAL
VSS_HV
_ADC
PC[6]
NC
PF[11] VDD_HV PA[15]
PD[7]
PD[6]
OSC32K
_EXTAL
MCKO
NC
PF[13]
PD[8]
1
2
3
4
5
6
9
14
15
NC
Note: 208 MAPBGA available only as development package for Nexus 2+.
= Not connected
Figure 4. 208 MAPBGA configuration
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by
DD
SS
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical characteristics
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or
silicon reliability trial.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 3. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.3
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
4.3.1
NVUSRO[PAD3V5V] field description
Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration.
1
Table 4. PAD3V5V field description
Value2
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1
2
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
11
Electrical characteristics
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
1
Table 5. OSCILLATOR_MARGIN field description
Value2
Description
0
1
Low consumption configuration (4 MHz/8 MHz)
High margin configuration (4 MHz/16 MHz)
1
2
See the device reference manual for more information on the NVUSRO register.
'1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
4.4
Absolute maximum ratings
Table 6. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
VDD
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
SR Voltage on VDD_HV pins with respect to
−0.3
6.0
ground (VSS
)
VSS_LV SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
—
—
VSS−0.1 VSS+0.1
V
(VSS
)
VDD_BV SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS
−0.3
−0.3
5.5
V
V
)
Relative to VDD
VDD+0.3
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
—
VSS−0.1 VSS+0.1
reference) pin with respect to ground
(VSS
)
VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS
—
—
−0.3
VDD−0.3 VDD+0.3
−0.3 5.5
VDD−0.3 VDD+0.3
5.5
V
V
)
Relative to VDD
Relative to VDD
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS
)
IINJPAD SR Injected input current on any pin during
overload condition
—
—
−10
10
mA
IINJSUM SR Absolute sum of all injected input
currents during overload condition
−50
50
IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
—
70
64
mA
supply segment
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
ICORELV SR Low voltage static current sink through
VDD_BV
—
150
mA
°C
TSTORAGE SR Storage temperature
—
−55
150
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical characteristics
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
4.5
Recommended operating conditions
Table 7. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect
3.0
3.6
to ground (VSS
)
2
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
—
—
VSS−0.1 VSS+0.1
V
(VSS
)
3
VDD_BV
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS
3.0
3.6
V
V
)
Relative to VDD
VDD−0.1 VDD+0.1
VSS−0.1 VSS+0.1
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground
(VSS
—
—
)
4
VDD_ADC
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground
3.05
VDD−0.1 VDD+0.1
3.6
V
Relative to VDD
(VSS
)
VIN
SR Voltage on any GPIO pin with respect
—
VSS−0.1
—
—
VDD+0.1
5
V
to ground (VSS
)
Relative to VDD
IINJPAD
IINJSUM
TVDD
SR Injected input current on any pin
during overload condition
—
−5
mA
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
—
—
3
0.25 V/µs
—
V/s
°C
TA
TJ
SR Ambient temperature under bias
SR Junction temperature under bias
fCPU < 64 MHz
−40
−40
125
150
—
1
2
3
100 nF capacitance needs to be provided between each VDD/VSS pair
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical characteristics
5
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL
device is reset.
,
6
Guaranteed by device validation
Table 8. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect to
4.5
3.0
5.5
5.5
ground (VSS
)
Voltage drop2
3
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
—
VSS−0.1 VSS+0.1
V
V
(VSS
)
4
VDD_BV
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS
—
4.5
3.0
5.5
5.5
)
Voltage drop(2)
Relative to VDD
VDD−0.1 VDD+0.1
VSS−0.1 VSS+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC
—
V
V
reference) pin with respect to ground
(VSS
5
VDD_ADC
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS
—
4.5
3.0
5.5
5.5
)
Voltage drop(2)
Relative to VDD
VDD−0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS
—
VSS−0.1
—
—
VDD+0.1
5
V
)
Relative to VDD
IINJPAD
IINJSUM
TVDD
SR Injected input current on any pin during
overload condition
—
−5
mA
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
—
—
0.25 V/µs
3
—
V/s
°C
TA C-Grade Part SR Ambient temperature under bias
TJ C-Grade Part SR Junction temperature under bias
TA V-Grade Part SR Ambient temperature under bias
TJ V-Grade Part SR Junction temperature under bias
TA M-Grade Part SR Ambient temperature under bias
TJ M-Grade Part SR Junction temperature under bias
100 nF capacitance needs to be provided between each VDD/VSS pair.
fCPU < 64 MHz
−40
−40
−40
−40
−40
−40
85
—
110
105
130
125
150
fCPU < 64 MHz
—
fCPU < 60 MHz
—
1
2
Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits.
3
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical characteristics
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
4
depending on external regulator characteristics).
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Guaranteed by device validation
5
6
NOTE
RAM data retention is guaranteed with V
not below 1.08 V.
DD_LV
4.6
Thermal characteristics
4.6.1
Package thermal characteristics
1
Table 9. LQFP thermal characteristics
Value3
Typ
Pin
count
Symbol
C
Parameter
Conditions2
Unit
Min
Max
RθJA CC
D
Thermal resistance,
junction-to-ambient natural
convection4
Single-layer board—1s
100
144
100
144
—
—
—
—
—
—
—
—
64
64
°C/W
Four-layer board—2s2p
50.8
49.4
1
2
3
4
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C.
All values need to be confirmed during device validation.
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA
.
1
Table 10. 208 MAPBGA thermal characteristics
Symbol
C
Parameter
Conditions
Value Unit
TBD °C/W
RθJA CC
—
Thermal resistance, junction-to-ambient natural Single-layer board—1s
convection2
Four-layer board—2s2p
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA
.
4.6.2
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:
J
T = T + (P x R )
θJA
Eqn. 1
J
A
D
Where:
T is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
θJA
P is the sum of P
and P (P = P
+ P ).
D
INT
I/O
D
INT I/O
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical characteristics
P
P
is the product of I and V , expressed in watts. This is the chip internal power.
DD DD
INT
represents the power dissipation on input and output pins; user determined.
I/O
Most of the time for the applications, P < P
and may be neglected. On the other hand, P may be significant, if the device
I/O
INT
I/O
is configured to continuously drive external modules and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273 °C)
Eqn. 2
Eqn. 3
D
J
Therefore, solving equations 1 and 2:
Where:
2
K = P x (T + 273 °C) + R
x P
D
D
A
θJA
K is a constant for the particular part, which may be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T Using this value of K, the values of P and T may be obtained by solving equations 1 and 2
A.
D
J
iteratively for any value of T .
A
4.7
I/O pad electrical characteristics
I/O pad types
4.7.1
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads—These pads provide transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
•
•
Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging capability.
Input only pads—These pads are associated to ADC channels and 32 kHz slow external crystal oscillator providing
low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical characteristics
4.7.2
I/O input DC characteristics
Table 11 provides input DC electrical characteristics as described in Figure 5.
Figure 5. I/O input DC electrical characteristics definition
V
IN
V
DD
V
IH
V
HYS
V
IL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Table 11. I/O input DC electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input high level CMOS (Schmitt
Trigger)
—
—
—
0.65VDD
—
VDD+0.4
V
VIL SR P Input low level CMOS (Schmitt
Trigger)
−0.4
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
0.1VDD
ILKG CC P Digital input leakage
No injection
on adjacent
pin
TA = −40 °C
TA = 25 °C
TA = 105 °C
TA = 125 °C
—
—
2
—
—
nA
P
2
D
—
12
70
—
—
500
1000
40
P
—
WFI SR P Digital input filtered pulse
WNFI SR P Digital input not filtered pulse
—
—
—
ns
ns
1000
—
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
4.7.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 13 provides output driver characteristics for I/O pads when in SLOW configuration.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical characteristics
•
•
Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 15 provides output driver characteristics for I/O pads when in FAST configuration.
Table 12. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
|IWPU| CC P Weak pull-up current
VIN = VIL, VDD = 5.0 V 10ꢀ PAD3V5V = 0
PAD3V5V = 12
10
10
10
10
10
10
—
—
—
—
—
—
150 µA
250
absolute value
C
P
VIN = VIL, VDD = 3.3 V 10ꢀ PAD3V5V = 1
VIN = VIH, VDD = 5.0 V 10ꢀ PAD3V5V = 0
PAD3V5V = 1
150
|IWPD| CC P Weak pull-down current
150 µA
250
absolute value
C
P
VIN = VIH, VDD = 3.3 V 10ꢀ PAD3V5V = 1
150
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 13. SLOW configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
SLOW configuration
Push Pull IOH = −2 mA,
0.8VDD
—
—
V
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
C
C
I
OH = −2 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 12
I
OH = −1 mA,
VDD−0.8
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
VOL CC P Output low level
SLOW configuration
Push Pull IOL = 2 mA,
—
—
—
—
—
—
0.1VDD
0.1VDD
0.5
V
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
C
C
IOL = 2 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V =
1(2)
I
V
OL = 1 mA,
DD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
2
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical characteristics
Table 14. MEDIUM configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC C Output high level
MEDIUM configuration
Push Pull IOH = −3.8 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
0.8VDD
—
—
V
P
I
OH = −2 mA,
0.8VDD
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
C
C
I
OH = −1 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 12
I
OH = −1 mA,
DD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
VDD−0.8
V
C
I
OH = −100 µA,
0.8VDD
—
—
—
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
0.2VDD
0.1VDD
V
MEDIUM configuration
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
P
IOL = 2 mA,
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
C
C
I
OL = 1 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10ꢀ, PAD3V5V = 1(2)
I
OL = 1 mA,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
C
I
OH = 100 µA,
—
—
0.1VDD
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical characteristics
Table 15. FAST configuration output buffer electrical characteristics
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
FAST configuration
Push
Pull
IOH = −14mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
0.8VDD
—
—
V
(recommended)
C
C
I
OH = −7mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 12
IOH = −11mA,
VDD−0.8
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
VOL CC P Output low level
FAST configuration
Push
Pull
IOL = 14mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
C
C
I
OL = 7mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10ꢀ, PAD3V5V = 1(2)
IOL = 11mA,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
2
4.7.4
Output pin transition times
Table 16. Output pin transition times
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
Ttr CC D Output transition time output pin3 CL = 25 pF VDD = 5.0 V 10ꢀ,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
100
125
50
ns
SLOW configuration
PAD3V5V = 0
T
D
D
T
CL = 50 pF
CL = 100 pF
CL = 25 pF VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
CL = 50 pF
100
125
10
D
CL = 100 pF
Ttr CC D Output transition time output pin(3) CL = 25 pF VDD = 5.0 V 10ꢀ,
ns
MEDIUM configuration
PAD3V5V = 0
SIUL.PCRx.SRC=1
T
D
D
T
CL = 50 pF
20
CL = 100 pF
40
CL = 25 pF VDD = 3.3 V 10ꢀ,
12
PAD3V5V = 1
SIUL.PCRx.SRC=1
CL = 50 pF
25
D
CL = 100 pF
40
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical characteristics
Table 16. Output pin transition times (continued)
Conditions1
Ttr CC D Output transition time output pin(3) CL = 25 pF VDD = 5.0 V 10ꢀ,
Value2
Symbol
C
Parameter
Unit
Min
Typ
Max
—
—
—
—
—
—
—
—
—
—
—
—
4
6
ns
FAST configuration
PAD3V5V = 0
CL = 50 pF
CL = 100 pF
12
4
CL = 25 pF VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
CL = 50 pF
7
CL = 100 pF
12
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
CL includes device and package capacitances (CPKG < 5 pF).
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as
DD SS
described in Table 17.
Table 18 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I
maximum value.
AVGSEG
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the I
maximum value.
DYNSEG
Table 17. I/O supply segment
Supply segment
Package
1
2
3
4
5
6
208 MAPBGA1
144 LQFP
Equivalent to 144 LQFP segment pad distribution
pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19
pin16–pin35 pin37–pin69 pin70–pin83 pin 84–pin15
MCKO
—
MDOn/MSEO
—
—
100 LQFP
—
1
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical characteristics
Table 18. I/O consumption
Value2
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
IDYNSEG
SR D Sum of all the
dynamic and static
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
—
—
110 mA
65
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
I/O current within a
supply segment
,3
ISWTSLW
CC D Dynamic I/O current CL = 25 pF
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
20
16
29
17
mA
for SLOW
configuration
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
(3)
ISWTMED
CC D Dynamic I/O current CL = 25 pF
for MEDIUM
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
mA
configuration
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
(3)
ISWTFST
CC D Dynamic I/O current CL = 25 pF
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
110 mA
50
for FAST
configuration
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
IRMSSLW
CC D Root medium square CL = 25 pF, 2 MHz
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.3 mA
3.2
I/O current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
6.6
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
1.6
2.3
4.7
IRMSMED CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V 10ꢀ,
6.6 mA
13.4
18.3
5
I/O current for
MEDIUM
configuration
PAD3V5V = 0
CL = 25 pF, 40 MHz
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
CL = 25 pF, 40 MHz
8.5
CL = 100 pF, 13 MHz
11
IRMSFST
CC D Root medium square CL = 25 pF, 40 MHz VDD = 5.0 V 10ꢀ,
22
33
56
14
20
35
70
65
mA
I/O current for FAST
configuration
PAD3V5V = 0
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
IAVGSEG
SR D Sum of all the static VDD = 5.0 V 10ꢀ, PAD3V5V = 0
I/O current within a
mA
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
supply segment
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical characteristics
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
4.8
nRSTIN electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 6. Start-up reset requirements
V
DD
V
DDMIN
nRSTIN
V
IH
V
IL
device reset forced by nRSTIN
device start-up phase
Figure 7. Noise filtering on reset signal
VRSTIN
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical characteristics
Table 19. Reset electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input High Level CMOS
(Schmitt Trigger)
—
—
—
0.65VDD
—
VDD+0.4
V
V
V
V
VIL SR P Input low Level CMOS
(Schmitt Trigger)
−0.4
0.1VDD
—
—
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
VOL CC P Output low level
Push Pull, IOL = 2mA,
0.1VDD
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
Push Pull, IOL = 1mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10ꢀ, PAD3V5V = 13
Push Pull, IOL = 1mA,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
Ttr
CC D Output transition time
output pin4
CL = 25pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
40
—
ns
MEDIUM configuration
CL = 50pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
CL = 100pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
CL = 25pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
—
CL = 50pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
—
CL = 100pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
—
WFRST SR P nRSTIN input filtered
pulse
—
—
ns
ns
µA
WNFRST SR P nRSTIN input not filtered
pulse
—
1000
|IWPU
|
CC P Weak pull-up current
absolute value
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
VDD = 5.0 V 10ꢀ, PAD3V5V = 15
10
10
10
—
—
—
150
150
250
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
4
5
CL includes device and package capacitance (CPKG < 5 pF).
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical characteristics
4.9
Power management electrical characteristics
Voltage regulator electrical characteristics
4.9.1
The device implements an internal voltage regulator to generate the low voltage core supply V
from the high voltage
DD_LV
ballast supply V
. The regulator itself is supplied by the common I/O supply V . The following supplies are involved:
DD_BV
DD
•
•
•
HV—High voltage external power supply for voltage regulator module. This must be provided externally through V
power pin.
DD
BV—High voltage external power supply for internal ballast module. This must be provided externally through
V
power pin. Voltage values should be aligned with V
.
DD_BV
DD
LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
Figure 8. Voltage regulator capacitance connection
C
(LV_COR/LV_CFLA)
REG2
GND
V
DD
V
V
DD_LV
SS_LV
V
DD_BV
DD_LVn
SS_LVn
V
REF
V
DD_BV
V
DD_LV
DEVICE
V
Voltage Regulator
I
V
SS_LV
GND
V
V
V
V
V
DD
SS_LV
DD_LV
SS
DEVICE
GND
GND
C
(supply/IO decoupling)
C
(LV_COR/LV_PLL)
DEC2
REG3
The internal voltage regulator requires external capacitance (C
) to be connected to the device in order to provide a stable
REGn
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical characteristics
Each decoupling capacitor must be placed between each of the three V
/V
supply pairs to ensure stable voltage (see
DD_LV SS_LV
Section 4.5, “Recommended operating conditions).
Table 20. Voltage regulator electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
CREGn
RREG
SR — Internal voltage regulator external
capacitance
—
—
200
—
330
nF
SR — Stability capacitor equivalent serial
resistance
—
—
0.2
Ω
CDEC1
CDEC2
SR — Decoupling capacitance3 ballast
VDD_BV/VSS_LV pair
VDD/VSS pair
400
10
4704
100
—
—
nF
nF
SR — Decoupling capacitance regulator
supply
VMREG
CC P Main regulator output voltage
Before trimming
After trimming
—
—
—
—
1.32
1.28
—
—
—
V
IMREG
SR — Main regulator current provided to
VDD_LV domain
150
mA
mA
IMREGINT CC D Main regulator module current
consumption
IMREG = 200 mA
IMREG = 0 mA
—
—
—
—
—
—
2
1
VLPREG
ILPREG
CC P Low power regulator output voltage After trimming
1.23
—
—
15
V
SR — Low power regulator current provided
to VDD_LV domain
mA
—
ILPREGINT CC D Low power regulator module current ILPREG = 15 mA;
—
—
—
—
—
—
—
—
5
600
TBD
—
µA
consumption
TA = 55 °C
—
ILPREG = 0 mA;
TA = 55 °C
VULPREG CC P Ultra low power regulator output
voltage
Post trimming
1.23
—
—
2
V
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
—
5
mA
µA
IULPREGINT CC D Ultra low power regulator module
current consumption
IULPREG = 5 mA;
TA = 55 °C
100
TBD
—
IULPREG = 0 mA;
TA = 55 °C
IVREGREF CC D Main LVDs and reference current
consumption (low power and main
regulator switched off)
TA = 55 °C
17
µA
IVREDLVD12 CC D Main LVD current consumption
(switch-off during standby)
TA = 55 °C
—
—
—
2
TBD µA
4005 mA
IDD_BV
CC D In-rush current on VDD_BV during
power-up
—
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical characteristics
3
4
5
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
In-rush current is seen only for short time during power-up and on standby exit (max 20µs, depending on external
capacitances to be load)
4.9.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage
detectors (LVDs) to monitor the V and the V voltage while device is supplied:
DD
DD_LV
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply
DD
LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range
DD
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVD_DIGBKP.
Figure 9. Low voltage monitor vs reset
V
DD
V
V
LVDHVxH
LVDHVxL
RESET
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical characteristics
Table 21. Low voltage monitor electrical characteristics
Value2
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
VPORUP
VPORH
SR P Supply for functional POR module
CC P Power-on reset threshold
TA = 25 °C,
after trimming
1.0
1.5
—
—
—
—
—
—
—
—
—
5.5
2.6
V
VLVDHV3H CC T LVDHV3 low voltage detector high threshold
VLVDHV3L CC P LVDHV3 low voltage detector low threshold
VLVDHV5H CC T LVDHV5 low voltage detector high threshold
VLVDHV5L CC P LVDHV5 low voltage detector low threshold
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
2.95
2.9
2.7
—
4.5
3.8
1.07
1.07
4.4
1.11
1.11
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
4.10 Low voltage domain power consumption
Table 22 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 22. Low voltage power domain electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
115 1403 mA
Min Typ Max
2
IDDMAX
CC D RUN mode maximum
average current
—
—
4
IDDRUN
CC T RUN modetypical average
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60
TBD TBD
TBD mA
180 7008 µA
80
mA
current5
P
—
IDDHALT
CC P HALT mode current6
—
8
IDDSTOP CC P STOP mode current7
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
D
D
D
P
TA = 55 °C
500
1
—
—
—
TA = 85 °C
TA = 105 °C
TA = 125 °C
mA
µA
2
4.5 TBD(8)
IDDSTDBY2 CC P STANDBY2modecurrent9 Slow internal RC oscillator TA = 25 °C
(128 kHz) running
30
100
—
D
D
D
P
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
TBD
—
—
TBD
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical characteristics
Table 22. Low voltage power domain electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
IDDSTDBY1 CC T STANDBY1 mode
Slow internal RC oscillator TA = 25 °C
—
—
—
—
—
20
60
—
—
—
µA
current10
D
(128 kHz) running
TA = 55 °C
TBD
D
D
D
TA = 85 °C
TA = 105 °C
TA = 125 °C
280 TBD
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with
all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be
noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce
peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when
possible.
3
4
5
Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 20.
RUN current measured with typical application with accesses on both flash and RAM.
Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master,
PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic
SW/WDG timer reset enabled.
6
Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON
(16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20KHz, instance: 1 clock gated. DSPI: instance: 0
(clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue
watchdog
7
8
Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All
possible peripherals off and clock gated. Flash in power down mode.
When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances , it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum
consumption, all possible modules switched-off.
10 ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules
switched-off.
4.11 Flash memory electrical characteristics
4.11.1 Program/Erase characteristics
Table 23 shows the program and erase characteristics.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical characteristics
Table 23. Program and erase specifications
Parameter
Value
Symbol
C
Unit
Initial
max2
Min
Typ1
Max3
Tdwprogram CC C Double word (64 bits) program time4
—
—
—
—
22
TBD
500
500
µs
ms
ms
ms
T16Kpperase
T32Kpperase
T128Kpperase
16 KB block pre-program and erase time
32 KB block pre-program and erase time
128 KB block pre-program and erase time
300
400
800
5000
5000
7500
600
1300
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
Table 24. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
P/E
CC C Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
100,000
—
cycles
P/E
P/E
CC C Number of program/erase cycles per
block for 32 Kbyte blocks over the
operating temperature range (TJ)
—
—
10,000
1,000
100,0001 cycles
100,000(1) cycles
CC C Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
Retention CC C Minimum data retention at 85 °C
average ambient temperature2
Blocks with 0–1,000 P/E
cycles
20
10
—
—
—
years
years
years
Blocks with 10,000 P/E
cycles
Blocks with 100,000 P/E
cycles
1–5
1
To be confirmed
2
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results.
Some units will experience single bit corrections throughout the life of the product with no impact to product
reliability.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical characteristics
Max Unit
Table 25. Flash read access timing
Parameter
Symbol
C
Conditions1
fREAD CC P Maximum frequency for Flash reading
2 wait states
1 wait state
0 wait states
64
40
20
MHz
C
C
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
4.11.2 Flash power supply DC characteristics
Table 26 shows the power supply DC characteristics on external supply.
Table 26. Flash power supply DC electrical characteristics
Conditions1
Value2
Min Typ Max
Symbol
C
Parameter
Unit
IFREAD CC D Sum of the current consumption on VDDHV Flash module read
and VDDBV on read access
fCPU = 64 MHz3
—
—
33 mA
IFMOD CC D Sum of the current consumption on VDDHV Program/Erase on-going
—
—
33 mA
and VDDBV on matrix modification
(program/erase)
while reading Flash registers
fCPU = 64 MHz(3)
IFLPW CC D Sum of the current consumption on VDDHV
and VDDBV during Flash low-power mode
—
—
—
—
900 µA
150 µA
IFPWD CC D Sum of the current consumption on VDDHV
and VDDBV during Flash powe-down mode
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
fCPU 64 MHz can be achieved only at up to 105 °C
4.11.3 Start-up/Switch-off timings
Table 27. Start-up time/Switch-off time
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
125
TFLARSTEXIT CC T Delay for Flash module to exit reset mode
—
—
—
—
—
—
µs
TFLALPEXIT
CC T Delay for Flash module to exit low-power
mode
0.5
TFLAPDEXIT
CC T Delay for Flash module to exit power-down
mode
—
—
—
—
—
—
—
—
—
30
TFLALPENTRY CC T Delay for Flash module to enter low-power
mode
0.5
1.5
TFLAPDENTRY CC T
Delay for Flash module to enter power-down
mode
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical characteristics
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
4.12 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for his application.
•
Software recommendations − The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
•
Prequalification trials − Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
4.12.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1
standard, which specifies the general conditions for EMI measurements.
1,2
Table 28. EMI radiated emission measurement
Value
Symbol
C
Parameter
Conditions
Unit
Min Typ Max
—
S — Scan range
R
—
—
—
0.15
0
1000 MHz
fCPU S — Operating frequency
R
—
—
—
—
64
1.28
—
—
—
MHz
V
VDD_L S — LV operating
R
voltages
V
SEMI C T Peak level
C
VDD = 5 V, TA = 25 °C,
LQFP144 package
No PLL frequency
modulation
18 dBµ
V
Test conforming to IEC 61967-2,
fOSC = 8 MHz/fCPU = 64 MHz
2ꢀ PLL
frequency
modulation
—
143 dBµ
V
1
2
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3
All values need to be confirmed during device validation
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical characteristics
4.12.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
4.12.3.1 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
1 2
Table 29. ESD absolute maximum ratings
Symbol
C
Ratings
Conditions
TA = 25 °C
Class Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
H1C
2000
V
conforming to AEC-Q100-002
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
4.12.3.2 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 30. Latch-up results
Symbol
LU CC
C
Parameter
Conditions
Class
T Static latch-up class
TA = 125 °C
II level A
conforming to JESD 78
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical characteristics
Table 31 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
Figure 10. Crystal oscillator and resonator connection scheme
EXTAL
C1
EXTAL
XTAL
C2
DEVICE
V
DD
I
R
EXTAL
XTAL
DEVICE
XTAL
DEVICE
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical characteristics
Shunt
Table 31. Crystal description
Crystal
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
capacitance
between
xtalout
Nominal
frequency
(MHz)
equivalent
series
NDK crystal
reference
xtalin/xtalout
C1 = C2
(pF)1
resistance
ESR Ω
and xtalin
C02 (pF)
4
NX8045GB
NX5032GA
300
300
150
120
120
2.68
2.46
2.93
3.11
3.90
591.0
160.7
86.6
21
17
15
15
10
2.93
3.01
2.91
2.93
3.00
8
10
12
16
56.5
25.3
1
2
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
Figure 11. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
S_MTRANS bit (ME_GS register)
‘1’
‘0’
V
XTAL
1/f
FXOSC
V
FXOSC
90ꢀ
10ꢀ
V
FXOSCOP
T
valid internal clock
FXOSCSU
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
35
Electrical characteristics
Table 32. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC CC C Fast external crystal
oscillator
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
OSCILLATOR_MARGIN =0
2.2
2.0
2.7
2.5
—
—
—
—
8.2
7.4
9.7
9.2
mA/V
transconductance
CC P
CC C
CC C
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
OSCILLATOR_MARGIN =0
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
OSCILLATOR_MARGIN =1
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
OSCILLATOR_MARGIN =1
VFXOSC
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
1.3
—
—
—
—
V
f
OSC = 16 MHz,
OSCILLATOR_MARGIN = 1
VFXOSCOP CC P Oscillation operating point
—
—
—
—
0.95
2
V
,3
IFXOSC
CC T Fast external crystal
oscillator consumption
3
6
mA
TFXOSCSU CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
—
—
—
—
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.8
VIH
VIL
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
Oscillator bypass mode
0.65VDD
−0.4
VDD+0.4
0.35VDD
V
V
SR P Input low level CMOS
(Schmitt Trigger)
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
36
Freescale Semiconductor
Electrical characteristics
4.14 Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
Figure 12. Crystal oscillator and resonator connection scheme
OSC32K_EXTAL
OSC32K_EXTAL
C1
C2
OSC32K_XTAL
OSC32K_XTAL
DEVICE
DEVICE
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 13. Equivalent circuit of a quartz crystal
C0
Crystal
Rm
Lm
Cm
C1
C2
C1
C2
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
37
Electrical characteristics
Symbol
1
Table 33. Crystal motional characteristics
Value
Typ
Parameter
Conditions
Unit
Min
Max
Lm
Motional inductance
Motional capacitance
—
—
—
—
—
18
11.796
—
—
28
KH
fF
Cm
2
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
—
pF
AC coupled @ C0 = 2.85 pF4
AC coupled @ C0 = 4.9 pF(4)
AC coupled @ C0 = 7.0 pF(4)
AC coupled @ C0 = 9.0 pF(4)
—
—
—
—
—
—
—
—
65
50
35
30
kW
3
Rm
Motional resistance
1
2
The crystal used is Epson Toyocom MC306.
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3
4
Maximum ESR (Rm) of the crystal is 50 kΩ
C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
OSCON bit (OSC_CTL register)
1
0
V
OSC32K_XTAL
1/f
SXOSC
V
SXOSC
90ꢀ
10ꢀ
T
valid internal clock
SXOSCSU
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
38
Freescale Semiconductor
Electrical characteristics
Table 34. Slow external crystal oscillator (32 kHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fSXOSC
SR — Slow external crystal oscillator
frequency
—
32
32.768
40
kHz
gmSXOSC CC — Slow external crystal oscillator
transconductance
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
TBD
TBD
TBD
TBD
mA/V
VDD = 5.0 V 10ꢀ
PAD3V5V = 0
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
VSXOSC
CC T Oscillation amplitude
—
—
—
—
2.1
TBD
—
—
V
ISXOSCBIAS CC T Oscillation bias current
µA
µA
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
8
TSXOSCSU CC T Slow external crystal oscillator
start-up time
—
—
23
s
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
4.15 FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Table 35. FMPLL electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fPLLIN SR — FMPLL reference clock3
—
—
4
—
—
64
60
MHz
ꢀ
ΔPLLIN SR — FMPLL reference clock duty
40
cycle(3)
fPLLOUT CC P FMPLL output clock frequency
fCPU SR — System clock frequency
fFREE CC P Free-running frequency
tLOCK CC P FMPLL lock time
—
16
—
20
—
—
—
40
—
64
MHz
—
644 MHz
—
150 MHz
Stable oscillator (fPLLIN = 16 MHz)
100
10
µs
ns
ΔtLTJIT CC — FMPLL long term jitter
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
—
—
IPLL
CC C FMPLL consumption
TA = 25 °C
—
4
mA
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
39
Electrical characteristics
2
All values need to be confirmed during device validation.
3
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN
fCPU 64 MHz can be achieved only at up to 105 °C
.
4
4.16 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 36. Fast internal RC oscillator (16 MHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFIRC
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
—
16
—
MHz
SR —
—
12
20
3,
IFIRCRUN
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
—
—
200
µA
µA
frequency current in running
mode
IFIRCPWD CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
—
TBD
10
—
TA = 55 °C
TBD TBD
down mode
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C sysclk = off
frequency and system clock
—
—
—
—
—
—
—
500
600
700
900
1250
1.1
—
—
µA
sysclk = 2 MHz
current in stop mode
sysclk = 4 MHz
sysclk = 8 MHz
—
—
sysclk = 16 MHz
—
TFIRCSU CC C Fast internal RC oscillator
TA = 55 °C VDD = 5.0 V 10ꢀ
VDD = 3.3 V 10ꢀ
2.0
TBD
µs
start-up time
—
1.2
—
—
TA = 125 °C VDD = 5.0 V 10ꢀ
—
—
−1
—
—
—
2.0
TBD
+1
VDD = 3.3 V 10ꢀ
ΔFIRCPRE CC C Fast internal RC oscillator
precision after software
TA = 25 °C
TA = 25 °C
ꢀ
trimming of fFIRC
ΔFIRCTRIM CC C Fast internal RC oscillator
—
1.6
—
ꢀ
ꢀ
trimming step
ΔFIRCVAR CC C Fast internal RC oscillator
variation in temperature and
supply with respect to fFIRC at
TA = 55 °C in high-frequency
configuration
—
−5
+5
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
40
Freescale Semiconductor
Electrical characteristics
2
3
All values need to be confirmed during device validation.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
4.17 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 37. Slow internal RC oscillator (128 kHz) electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fSIRC
CC P Slow internal RC oscillator low
TA = 25 °C, trimmed
—
—
100
—
128
—
—
150
5
kHz
frequency
SR —
3,
ISIRC
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
µA
µs
ꢀ
TSIRCSU CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V 10ꢀ
time
—
−2
8
12
+2
ΔSIRCPRE CC C Slow internal RC oscillator precision TA = 25 °C
—
2.7
—
after software trimming of fSIRC
ΔSIRCTRIM CC C Slow internal RC oscillator trimming
—
—
—
step
ΔSIRCVAR CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
−10
+10
ꢀ
respect to fSIRC at TA = 55 °C in high
frequency configuration
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
All values need to be confirmed during device validation.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
41
Electrical characteristics
4.18 On-chip peripherals
4.18.1 Current consumption
1
Table 38. On-chip peripherals current consumption
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
IDD_BV(CAN)
CC T CAN (FlexCAN) supply 500 Kbps Total (static + dynamic)
7.652 * fperiph + 84.73
8.0743 * fperiph + 26.757
µA
current on VDD_BV
consumption:
125 Kbps
• FlexCAN in loop-back
mode
• XTAL@8MHz used as
CAN engine clock
source
• Messagesendingperiod
is 580 µs
IDD_BV(eMIOS) CC T eMIOS supply current Static consumption:
28.7 * fperiph
on VDD_BV
• eMIOS channel OFF
• Global prescaler enabled
Dynamic consumption:
3
• It does not change varying the
frequency (0.003 mA)
IDD_BV(SCI)
CC T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynamic) consumption:
• LIN mode
4.7804 * fperiph + 30.946
• Baudrate: 20 Kbps
IDD_BV(SPI)
CC T SPI (DSPI) supply
current on VDD_BV
Ballast static consumption (only
clocked)
1
Ballast dynamic consumption
(continuus communication):
• Baudrate: 2 Mbit
16.3 * fperiph
• Trasmission every 8 µs
• Frame: 16 bits
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
42
Freescale Semiconductor
Electrical characteristics
Table 38. On-chip peripherals current consumption (continued)
1
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
IDD_BV(ADC)
CC T ADC supply current on VDD =5.5V Ballast static consumption
0.0409 * fperiph
mA
VDD_BV
(no conversion)
VDD =5.5V
Ballast dynamic
consumption (continuus
conversion)
0.0049 * fperiph
IDD_HV_ADC(ADC) CC T ADC supply current on VDD =5.5V Analog static consumption
0.0017 * fperiph
VDD_HV_ADC
(no conversion)
VDD =5.5V
Analog dynamic
consumption (continuus
conversion)
0.075 * fperiph + 0.032
IDD_HV(FLASH) CC T CFlash + DFlash
supply current on
VDD =5.5V
-
8.21 (4.14 + 4.07)
0.0031 * fperiph
VDD_HV_ADC
IDD_HV(PLL)
CC T PLL supply current on VDD =5.5V
VDD_HV
-
1
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
43
Electrical characteristics
4.18.2 DSPI characteristics
Table 39. DSPI characteristics
Value
Typ
No. Symbol
C
Parameter
Unit
Min
Max
1
tSCK SR D SCK cycle time
64
—
—
—
—
—
—
ns
—
—
fDSPI SR D DSPI digital controller frequency
fCPU MHz
ΔtCSC CC D Internal delay between pad associated to SCK and
1201
ns
pad associated to CSn in master mode
2
2
3
4
tCSCext CC D CS to SCK delay
SR D
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
—
t
CSCext = tCSC + ΔtCSC
ns
32
—
—
3
tASCext CC D After SCK delay
tASCext = tASC + ΔtCSC
ns
ns
ns
SR D
1/fDSPI + 5 ns
—
tSCK/2
—
—
—
—
—
—
—
—
—
—
—
—
32
34
32
—
—
—
tSDC CC D SCK duty cycle
SR D
—
tSCK/2
27
0
5
6
7
tA
SR D Slave access time
—
ns
ns
ns
tDI
SR D Slave SOUT disable time
—
—
tSUI SR D Data setup time for inputs
Master (MTFE = 0)
Slave
35
5
—
—
Master(MTFE = 1)
Master (MTFE = 0)
Slave
35
0
—
8
9
tHI
SR D Data hold time for inputs
—
ns
ns
ns
24
—
Master(MTFE = 1)
Master (MTFE = 0)
Slave
0
—
5
tSUO CC D Data valid after SCK edge
—
—
—
2
—
—
Master (MTFE = 1)
Master (MTFE = 0)
Slave
—
(5)
10 tHO
CC D Data hold time for outputs
—
5.5
2
—
Master (MTFE = 1)
—
1
2
Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields
in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtCSC to ensure
positive tCSCext
.
3
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than ΔtASC to ensure positive
tASCext
.
4
5
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
SCK and SOUT configured as MEDIUM pad
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
44
Freescale Semiconductor
Electrical characteristics
Figure 15. DSPI classic SPI timing – master, CPHA = 0
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Note: Numbers shown reference Table 39.
Figure 16. DSPI classic SPI timing – master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
45
Electrical characteristics
Figure 17. DSPI classic SPI timing – slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Numbers shown reference Table 39.
Figure 18. DSPI classic SPI timing – slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
46
Freescale Semiconductor
Electrical characteristics
Figure 19. DSPI modified transfer format timing – master, CPHA = 0
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Note: Numbers shown reference Table 39.
Figure 20. DSPI modified transfer format timing – master, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
47
Electrical characteristics
Figure 21. DSPI modified transfer format timing – slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Numbers shown reference Table 39.
Figure 22. DSPI modified transfer format timing – slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
48
Freescale Semiconductor
Electrical characteristics
Figure 23. DSPI PCS strobe (PCSS) timing
8
7
PCSS
PCSx
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
49
Electrical characteristics
4.18.3 Nexus characteristics
Table 40. Nexus characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
tTCYC
tMCYC
tMDOV
tMSEOV CC D MCKO low to MSEO_b data valid
CC D TCK cycle time
64
32
—
—
—
15
15
5
—
—
—
—
—
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC D MCKO cycle time
3
CC D MCKO low to MDO data valid
4
8
5
tEVTOV
tNTDIS
CC D MCKO low to EVTO data valid
CC D TDI data setup time
8
10
—
—
—
—
—
—
tNTMSS CC D TMS data setup time
tNTDIH CC D TDI data hold time
tNTMSH CC D TMS data hold time
11
5
12
13
tTDOV
tTDOI
CC D TCK low to TDO data valid
CC D TCK low to TDO data invalid
35
6
Figure 24. Nexus TDI, TMS, TDO timing
TCK
10
11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 40.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
50
Freescale Semiconductor
Electrical characteristics
4.18.4 JTAG characteristics
Table 41. JTAG characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Max
Min
1
2
3
4
5
6
7
tJCYC
tTDIS
CC D TCK cycle time
CC D TDI setup time
CC D TDI hold time
64
15
5
—
—
—
—
—
—
—
—
—
—
—
—
33
—
ns
ns
ns
ns
ns
ns
ns
tTDIH
tTMSS
tTMSH
tTDOV
tTDOI
CC D TMS setup time
CC D TMS hold time
CC D TCK low to TDO valid
CC D TCK low to TDO invalid
15
5
6
Figure 25. Timing diagram – JTAG boundary scan
TCK
2/4
3/5
INPUT DATA VALID
DATA INPUTS
6
DATA OUTPUTS
DATA OUTPUTS
OUTPUT DATA VALID
7
Note: Numbers shown reference Table 41.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
51
Electrical characteristics
4.18.5 ADC electrical characteristics
4.18.5.1 Introduction
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.
Figure 26. ADC characteristic and error definitions
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
4.18.5.2 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
52
Freescale Semiconductor
Electrical characteristics
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 kΩ is obtained (R
S
EQ
= 1 / (f *C ), where f represents the conversion rate at the considered channel). To minimize the error induced by the voltage
c
S
c
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 4:
Eqn. 4
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V •
< -- LSB
A
R
EQ
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
53
Electrical characteristics
Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
Figure 27. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
Pin Capacitance (two contributions, C and C
P1
Sampling Capacitance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
)
P2
S
Figure 28. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Filter
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions R
Sampling Switch Impedance
Pin Capacitance (three contributions, C , C and C )
P3
Sampling Capacitance
S
F
F
L
and R
)
SW2
SW
AD
P
SW1
P1
P2
S
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
54
Freescale Semiconductor
Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit in Figure 27): A charge sharing phenomenon is installed
A
when the sampling phase is started (A/D switch close).
Figure 29. Transient behavior during sampling phase
Voltage transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ2 = RL (CS + CP1 + CP2)
T
t
S
In particular two different transient periods can be distinguished:
1. A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
Eqn. 5
C • C
P
S
--------------------
) •
τ
= (R
+ R
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
Eqn. 6
τ < (R
+ R
) • C « T
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
Eqn. 7
V
• (C + C + C ) = V • (C + C
)
A1
S
P1
P2
A
P1
P2
2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
55
Electrical characteristics
Eqn. 8
τ < R • (C + C + C
P1 P2
)
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
Eqn. 9
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 10
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
Figure 30. Spectral representation of input signal
Analog source bandwidth (VA)
TC < 2 RFCF (conversion rate vs. filter pole)
Noise
fF = f0 (anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
Sampled signal spectrum (fC = conversion rate)
fF
f0
fC
f
f
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
56
Freescale Semiconductor
Electrical characteristics
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 12
C
> 2048 • C
F
S
4.18.5.3 ADC electrical characteristics
Table 42. ADC input leakage current
Value
Typ
Symbol C
Parameter
Conditions
Unit
Min
Max
ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin
—
—
—
—
1
1
—
—
nA
C
C
P
TA = 25 °C
TA = 105 °C
TA = 125 °C
8
200
400
45
Table 43. ADC conversion characteristics
Value
Uni
t
Symbol
C
Parameter
Conditions1
Min
Typ
Max
VSS_ADC
S
R
— Voltage on
—
−0.1
—
0.1
V
V
V
VSS_HV_ADC (ADC
reference) pin with
respect to ground
2
(VSS
)
VDD_ADC
S
R
— Voltage on
VDD_HV_ADC pin
—
VDD−0.1
—
VDD+0.1
(ADC reference) with
respect to ground
(VSS
)
VAINx
fADC
S
R
— Analog input voltage3
—
—
VSS_ADC−0.1
—
—
—
—
VDD_ADC+0.
1
S
R
— ADC analog
frequency
6
32 + 4ꢀ
MH
z
ΔADC_SY
S
R
— ADC digital clock duty ADCLKSEL = 14
cycle (ipg_clk)
45
—
55
ꢀ
S
tADC_PU
S
R
— ADC power up delay
—
1.5
µs
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
57
Electrical characteristics
Table 43. ADC conversion characteristics (continued)
Value
Uni
t
Symbol
C
Parameter
Sample time5
Conditions1
Min
Typ
Max
tADC_S
C
C
T
fADC = 32 MHz,
ADC_conf_sample_input = 17
0.5
—
µs
f
ADC = 6 MHz,
—
—
—
—
—
—
—
—
—
—
—
42
INPSAMP = 255
tADC_C
CS
C
C
P
D
D
D
D
D
D
D
Conversion time6
fADC = 32 MHz,
ADC_conf_comp = 2
0.625
—
µs
pF
pF
pF
pF
kΩ
kΩ
kΩ
mA
C
C
ADC input sampling
capacitance
—
—
—
—
—
—
—
3
3
CP1
C
C
ADC input pin
capacitance 1
—
CP2
C
C
ADC input pin
capacitance 2
—
1
CP3
C
C
ADC input pin
capacitance 3
—
1
RSW1
RSW2
RAD
IINJ
C
C
Internal resistance of
analog source
—
3
C
C
Internal resistance of
analog source
—
2
C
C
Internal resistance of
analog source
—
0.1
5
S
R
— Input current Injection Current
injection on
VDD
3.3 V 10ꢀ
=
−5
−5
one ADC input,
different from
the converted
one
VDD
5.0 V 10ꢀ
=
5
| INL |
| DNL |
| OFS |
| GNE |
TUEp
C
C
T
T
T
T
Absolute value for
integral non-linearity
No overload
—
—
—
—
0.5
0.5
0.5
0.6
0.6
1.5
1.0
—
LSB
LSB
LSB
LSB
LSB
C
C
Absolute differential
non-linearity
No overload
C
C
Absolute offset error
—
C
C
Absolute gain error
—
—
C
C
P
T
Total unadjusted
error7 for precise
channels, input only
pins
Without current injection
With current injection
−2
−3
2
3
TUEx
C
C
T
T
Total unadjusted
error(7) for extended
channel
Without current injection
With current injection
−3
−4
1
3
4
LSB
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
58
Freescale Semiconductor
Electrical characteristics
2
3
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4
5
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
6
7
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
59
Package characteristics
5
Package characteristics
5.1
Package mechanical data
Figure 31. 144 LQFP package mechanical drawing
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
60
Freescale Semiconductor
Package characteristics
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
61
Package characteristics
Figure 32. 100 LQFP package mechanical drawing
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
62
Freescale Semiconductor
Package characteristics
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
63
Package characteristics
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
64
Freescale Semiconductor
Package characteristics
Figure 33. 208 MAPBGA package mechanical drawing
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
65
Package characteristics
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
66
Freescale Semiconductor
Ordering information
6
Ordering information
Table 44. Orderable Part Number Summary
Code Flash /
SRAM
(Kbytes)
Operating
temp.
Orderable Part
Number
Speed
(MHz)
Data
Flash
CPU
Package
Voltage Packing
(°C)
MPC5602BEMLL
MPC5602BEMLLR
MPC5602BEMLQ
MPC5602BEMLQR
MPC5602CEMLL
MPC5602CEMLLR
MPC5603BEMLL
MPC5603BEMLLR
MPC5603BEMLQ
MPC5603BEMLQR
MPC5603CEMLL
MPC5603CEMLLR
MPC5602BEVLL
MPC5602BEVLLR
MPC5602BEVLQ
MPC5602BEVLQR
MPC5602CEVLL
MPC5602CEVLLR
MPC5603BEVLL
MPC5603BEVLLR
MPC5603BEVLQ
MPC5603BEVLQR
MPC5603CEVLL
MPC5603CEVLLR
MPC5604BEMLL
MPC5604BEMLLR
MPC5604BEMLQ
MPC5604BEMLQR
MPC5604BEVLL
MPC5604BEVLLR
e200z0h
256 / 24
256 / 24
256 / 32
384 / 28
384 / 28
384 / 40
256 / 24
256 / 24
256 / 32
384 / 28
384 / 28
384 / 40
512 / 32
512 / 32
512 / 32
100 LQFP −40 to 125
144 LQFP −40 to 125
100 LQFP −40 to 125
100 LQFP −40 to 125
144 LQFP −40 to 125
100 LQFP −40 to 125
100 LQFP −40 to 105
144 LQFP −40 to 105
100 LQFP −40 to 105
100 LQFP −40 to 105
144 LQFP −40 to 105
100 LQFP −40 to 105
100 LQFP −40 to 125
144 LQFP −40 to 125
100 LQFP −40 to 105
60
60
60
60
60
60
64
64
64
64
64
64
60
60
64
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
Tray
Tape & Reel
Tray
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
e200z0h
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
67
Document revision history
Table 44. Orderable Part Number Summary (continued)
Code Flash /
SRAM
(Kbytes)
Operating
temp.
Orderable Part
Number
Speed
(MHz)
Data
Flash
CPU
Package
Voltage Packing
(°C)
MPC5604BEVLQ
MPC5604BEVLQR
MPC5604CEMLL
MPC5604CEMLLR
MPC5604BEMMG
e200z0h
512 / 32
512 / 48
512 / 48
144 LQFP −40 to 105
100 LQFP −40 to 125
64
60
64
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
4 x 16 KB 3.3/5 V
Tray
Tape & Reel
Tray
e200z0h
e200z0h
Tape & Reel
Tray
208 MAP −40 to 125
BGA1
1
208 MAPBGA available only as development package for Nexus2+
Figure 34. Commercial product code structure
Example code:
M
PC
56
0
4
B
E
M
LL
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
R = Tape & Reel (blank if Tray)
Qualification Status
M = MC status
Flash Size (z0 core)
2 = 256 KB
Temperature spec.
C = -40 to 85 °C
S = Auto qualified
P = PC status
3 = 384 KB
V = -40 to 105 °C
M = -40 to 125 °C
4 = 512 KB
Automotive Platform
56 = PPC in 90nm
Product
B = Body
Package Code
LL = 100 LQFP
LQ = 144 LQFP
57 = PPC in 65nm
C = Gateway
1
MG = 208 MAPBGA
1
208 MAPBGA available only as development package for Nexus2+
7
Document revision history
Table 45 summarizes revisions to this document.
Table 45. Revision history
Revision
Date
Description of Changes
1
04-Apr-2008 Initial release.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
68
Freescale Semiconductor
Document revision history
Table 45. Revision history (continued)
Description of Changes
Revision
Date
2
06-Mar-2009 Made minor editing and formatting changes to improve readability
Harmonized oscillator naming throughout document
Features:
—Replaced 32 KB with 48 KB as max SRAM size
—Updated descripiton of INTC
—Changed max number of GPIO pins from 121 to 123
Updated Section 1.1, “Introduction
Updated Table 2
Added Section 2, “Device blocks
Section 3, “Package pinouts: Removed signal descriptions (these are found in the device
reference manual)
Updated Figure 2:
—Replaced VPP with VSS_HV on pin 18
—Added MA[1] as AF3 for PC[10] (pin 28)
—Added MA[0] as AF2 for PC[3] (pin 116)
—Changed description for pin 120 to PH[10] / GPIO[122] / TMS
—Changed description for pin 127 to PH[9] / GPIO[121] / TCK
—Replaced NMI[0] with NMI on pin 11
Updated Figure 3:
—Replaced VPP with VSS_HV on pin 14
—Added MA[1] as AF3 for PC[10] (pin 22)
—Added MA[0] as AF2 for PC[3] (pin 77)
—Changed description for pin 81 to PH[10] / GPIO[122] / TMS
—Changed description for pin 88 to PH[9] / GPIO[121] / TCK
—Removed E1UC[19] from pin 76
—Replaced [11] with WKUP[11] for PB[3] (pin 1)
—Replaced NMI[0] with NMI on pin 7
Updated Figure 4:
—Changed description for ball B8 from TCK to PH[9]
—Changed description for ball B9 from TMS to PH[10]
—Updated descriptions for balls R9 and T9
Added Section 3.2, “Parameter classification and tagged parameters in tables where
appropriate
Added Section 3.3, “NVUSRO register
Updated Table 7
Section 3.5, “Recommended operating conditions: Added note on RAM data retention to
end of section
Updated Table 8 and Table 9
Added Section 3.6.1, “Package thermal characteristics
Updated Section 3.6.2, “Power considerations
Updated Figure 6
Updated Table 12, Table 13, Table 14, Table 15 and Table 16
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
69
Document revision history
Table 45. Revision history (continued)
Description of Changes
Revision
Date
2
06-Mar-2009 Added Section 3.7.4, “Output pin transition times
Updated Table 19
Updated Figure 7
Updated Table 20
Section 3.9.1, “Voltage regulator electrical characteristics: Amended description of
LV_PLL
Figure 9: Exchanged position of symbols CDEC1 and CDEC2
Updated Table 21
Added Figure 10
Updated Table 22 and Table 23
Updated Section 3.11, “Flash memory electrical characteristics
Added Section 3.12, “Electromagnetic compatibility (EMC) characteristics
Updated Section 3.13, “Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
Updated Section 3.14, “Slow external crystal oscillator (32 kHz) electrical characteristics
Updated Table 37, Table 38 and Table 39
Added Section 3.18, “On-chip peripherals
Added Table 44
Updated Table 45
Updated Table 49
Added Section Appendix A, “Abbreviations
4
06-Aug-2009 Updated Figure 4
Table 7
• VDD_ADC: changed min value for “relative to VDD“ condition
• VIN: changed min value for “relative to VDD“ condition
• ICORELV: added new row
Table 9
• TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part
:
added new rows
• Changed capacitance value in footnote
Table 17
• MEDIUM configuration: added condition for PAD3V5V = 0
Updated Figure 9
Table 21
• CDEC1: changed min value
• IMREG: changed max value
• IDD_BV: added max value footnote
Table 22
• VLVDHV3H: changed max value
• VLVDHV3L: added max value
• VLVDHV5H: changed max value
• VLVDHV5L: added max value
Updated Table 23
Table 26
• Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“
Table 34
• IFXOSC: added typ value
Table 36
• VSXOSC: changed typ value
• TSXOSCSU: added max value footnote
Table 37
• ΔtLTJIT: added max value
Updated Figure 33
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
70
Freescale Semiconductor
Abbreviations
Appendix A
Abbreviations
Table 46 lists abbreviations used but not defined elsewhere in this document.
Table 46. Abbreviations
Abbreviation
Meaning
CMOS
CPHA
CPOL
CS
Complementary metal–oxide–semiconductor
Clock phase
Clock polarity
Peripheral chip select
Event out
EVTO
LED
Light emitting diode
Message clock out
Message data out
Message start/end out
Modified timing format enable
Serial communications clock
Serial data out
MCKO
MDO
MSEO
MTFE
SCK
SOUT
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
71
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Japan:
Freescale Semiconductor Japan Ltd. Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
Freescale Semiconductor Literature Distribution Center
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. The described product contains a PowerPC processor
core. The PowerPC name is a trademark of IBM Corp. and used under license.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2009. All rights reserved.
MPC5604BC
Rev. 4
08/2009
相关型号:
MPC5602BEVLLR
32-BIT, FLASH, 64MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100
NXP
MPC5602BEVLQ
32-BIT, FLASH, 64MHz, MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144
NXP
MPC5602BEVLQR
32-BIT, FLASH, 64MHz, MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144
NXP
MPC5602BF1CLH6
MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64
NXP
MPC5602BF1CLH6R
MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64
NXP
©2020 ICPDF网 联系我们和版权申明