MPC5602CF1MLH4 [NXP]
MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64;
| 型号： | MPC5602CF1MLH4 |
| 厂家： | 
NXP |
| 描述： | MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64 CD 外围集成电路 |
| 文件： | 总104页 (文件大小：926K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604BC
Rev. 9, 06/2011
MPC5604B/C
144 LQFP
208 MAPBGA
(20 x 20 x 1.4 mm)
(17 x 17 x 1.7 mm)
MPC5604B/C
Microcontroller Data Sheet
100 LQFP
64 LQFP
(14 x 14 x 1.4 mm)
(10 x 10 x 1.4 mm)
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 7
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Pad configuration during reset phases. . . . . . . . . . . . . 11
3.3 Voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Nexus 2+ pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 32
4.5 Recommended operating conditions . . . . . . . . . . . . . . 33
4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 36
4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . 46
4.9 Power management electrical characteristics . . . . . . . 48
4.10 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.11 Flash memory electrical characteristics . . . . . . . . . . . . 55
4.12 Electromagnetic compatibility (EMC) characteristics . . 58
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.14 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.15 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 64
4.16 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.17 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.18 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 68
4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 85
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Features
•
Single issue, 32-bit CPU core complex (e200z0)
2
3
®
— Compliant with the Power Architecture
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
4
•
Up to 512 KB on-chip code flash supported with the
flash controller
•
•
•
64 (4 × 16) KB on-chip data flash memory with ECC
Up to 48 KB on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity
•
Interrupt controller (INTC) with 148 interrupt
vectors, including 16 external interrupt sources and
18 external interrupt/wakeup sources
•
•
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash memory, or RAM from multiple
bus masters
•
•
Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
5
•
•
•
10-bit analog-to-digital converter (ADC)
3 serial peripheral interface (DSPI) modules
6
7
Up to 4 serial communication interface (LINFlex)
modules
Appendix AAbbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2011. All rights reserved.
Introduction
•
•
•
•
Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers
2
1 inter IC communication interface (I C) module
Up to 123 configurable general purpose pins supporting input and output operations (package dependent)
Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous
wakeup with 1 ms resolution with max timeout of 2 seconds
•
•
•
•
•
Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution
1 System Module Timer (STM)
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator (VREG) for regulation of input supply for all internal levels
1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also
to the device reference manual and errata sheet.
1.2
Description
®
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture embedded category.
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers.
It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU,
providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and
is supported with software drivers, operating systems and configuration code to assist with users implementations.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
2
Freescale Semiconductor
1
Table 1. MPC5604B/C device comparison
Device
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC5604
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL BxMG
CPU
e200z0h
Execution
speed2
Static – up to 64 MHz
Code Flash
Data Flash
RAM
256 KB
36 ch
384 KB
512 KB
64 KB (4 × 16 KB)
24 KB
28 ch
32 KB
28 KB
28 ch
40 KB
32 KB
28 ch
48 KB
28 ch
MPU
8-entry
36 ch 8 ch
Yes
ADC (10-bit)
CTU
12 ch
8 ch
28 ch
12 ch
28 ch
12 ch
36 ch
8 ch
36 ch
Total timer
12 ch, 28 ch, 56 ch, 12 ch, 28 ch, 12 ch, 28 ch, 56 ch, 12 ch, 28 ch, 12 ch, 28 ch, 56 ch, 12 ch, 28 ch,
16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit
56 ch,
16-bit
I/O3 eMIOS
• PWM+MC 2 ch
+ IC/OC4
5 ch
10 ch
40 ch
6 ch
2 ch
10 ch
—
5 ch
20 ch
3 ch
2 ch
10 ch
—
5 ch
20 ch
3 ch
10 ch
40 ch
6 ch
2 ch
10 ch
—
5 ch
2 ch
10 ch
—
5 ch
20 ch
3 ch
10 ch
40 ch
6 ch
2 ch
10 ch
—
5 ch
20 ch
3 ch
10 ch
40 ch
6 ch
• PWM +
IC/OC4
10 ch
20 ch
20 ch
• IC/OC4
—
3 ch
35
3 ch
4
SCI (LINFlex)
SPI (DSPI)
2
3
2
5
3
6
2
3
2
5
3
2
3
2
5
3
6
CAN
26
37
6
37
(FlexCAN)
I2C
1
32 kHz
Yes
oscillator
GPIO8
45
64
79
123
144
45
64
79
45
64
79
123
JTAG
144
45
64
79
45
64
79
123
144
45
64
79
123
Debug
Nexus2+
208
Package
100
100
100
100
100
100
LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP MAPBGA9
1
2
3
4
5
6
7
8
9
Feature set dependent on selected peripheral multiplexing—table shows example implementation
Based on 125 °C ambient operating temperature
See the eMIOS section of the device reference manual for information on the channel configuration and functions.
IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter
SCI0, SCI1 and SCI2 are available. SCI3 is not available.
CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.
I/O count based on multiplexing with peripherals
208 MAPBGA available only as development package for Nexus2+
Block diagram
2
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
SRAM
48 KB
Code Flash Data Flash
512 KB 64 KB
JTAG
JTAG port
Instructions
Nexus port
SRAM
Flash
controller
e200z0h
Nexus 2+
(Master)
Nexus
controller
Data
NMI
(Slave)
(Master)
SIUL
Voltage
regulator
(Slave)
Interrupt requests
from peripheral
blocks
(Slave)
NMI
MPU
registers
INTC
Clocks
CMU
FMPLL
RTC
MC_RGM MC_CGM MC_ME MC_PCU
SSCM
STM
PIT
BAM
SWT
ECSM
Peripheral bridge
SIUL
36 Ch.
ADC
2 x
eMIOS
4 x
LINFlex
3 x
DSPI
6 x
FlexCAN
2
CTU
I C
Reset control
Interrupt
request
External
interrupt
request
IMUX
WKPU
GPIO and
pad control
Interrupt
request with
wakeup
. . .
. . .
. . .
. . .
. . .
I/O
functionality
Legend:
ADC
BAM
Analog-to-Digital Converter
Boot Assist Module
MC_ME
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
Mode Entry Module
FlexCAN Controller Area Network
CMU
CTU
DSPI
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
MPU
Nexus
NMI
Memory Protection Unit
Nexus Development Interface (NDI) Level
Non-Maskable Interrupt
eMIOS
FMPLL
I C
IMUX
INTC
JTAG
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
PIT
RTC
SIUL
SRAM
SSCM
STM
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
2
JTAG controller
LINFlex
ECSM
Serial Communication Interface (LIN support)
Error Correction Status Module
SWT
WKPU
Software Watchdog Timer
Wakeup Unit
MC_CGM Clock Generation Module
Figure 1. MPC5604B/C block diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
5
Block diagram
Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the
presence and number of blocks vary by device and package.
Table 2. MPC5604B/C series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock monitor unit (CMU)
Cross triggering unit (CTU)
Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Error Correction Status Module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor
(eDMA)
via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
Generates high-speed system clocks and supports programmable frequency
phase-locked loop (FMPLL)
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
MPC5604B/C Microcontroller Data Sheet, Rev. 9
6
Freescale Semiconductor
Package pinouts and signal descriptions
Table 2. MPC5604B/C series block summary (continued)
Block
Function
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Nexus development interface
(NDI)
Provides real-time development support capabilities in compliance with the
IEEE-ISTO 5001-2003 standard
Periodic interrupt timer (PIT)
Real-time counter (RTC)
Produces periodic interrupts and triggers
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
System integration unit (SIU)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System status configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR and operating
system tasks
System watchdog timer (SWT)
Wakeup unit (WKPU)
Provides protection from runaway code
The wakeup unit supports up to 18 external sources that can generate interrupts
or wakeup events, of which 1 can cause non-maskable interrupt requests or
wakeup events.
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
3
Package pinouts and signal descriptions
3.1
Package pinouts
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,
please refer to the device reference manual.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
7
Package pinouts and signal descriptions
48 PA[11]
47 PA[10]
46 PA[9]
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
1
2
3
45 PA[8]
4
44 PA[7]
43 PA[3]
5
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
6
42 PB[15]
41 PB[14]
40 PB[13]
39 PB[12]
38 PB[11]
37 PB[7]
7
8
64 LQFP
Top view
9
10
11
12
13
14
15
16
36 PB[6]
35 PB[5]
34 VDD_HV_ADC
33 VSS_HV_ADC
PB[0]
PB[1]
PC[6]
Figure 2. MPC560xB LQFP 64-pin configuration
48 PA[11]
47 PA[10]
46 PA[9]
PB[3]
PC[9]
1
2
PA[2]
3
45 PA[8]
PA[1]
PA[0]
4
44 PA[7]
5
43 PF[14]
42 PF[15]
41 PG[0]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
6
7
8
64 LQFP
Top view
40 PG[1]
39 PA[3]
38 PB[15]
37 PB[14]
36 PB[11]
35 PB[7]
9
10
11
12
13
14
15
16
PB[1]
PC[6]
34 VDD_HV_ADC
33 VSS_HV_ADC
Figure 3. MPC560xC LQFP 64-pin configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 9
8
Freescale Semiconductor
Package pinouts and signal descriptions
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
9
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PE[9]
PE[10]
PA[0]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
100 LQFP
Top view
PB[1]
PC[6]
Note:
Availability of port pin alternate functions depends on product selection.
Figure 4. LQFP 100-pin configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
9
Package pinouts and signal descriptions
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
144 LQFP
Top view
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
74
73
Note:
Availability of port pin alternate functions depends on product selection.
Figure 5. LQFP 144-pin configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 9
10
Freescale Semiconductor
Package pinouts and signal descriptions
1
2
3
4
NC
5
6
7
8
9
10
NC
NC
NC
NC
11
12
NC
13
PE[15]
PG[15]
PE[14]
PG[10]
PG[1]
PH[0]
VDD_HV
MDO3
NC
14
15
NC
16
NC
PC[8]
PC[9]
PC[13]
PB[2]
NC
PH[8]
PE[6]
PH[7]
PH[6]
PH[4]
PH[5]
PE[5]
PE[4]
PC[5]
PC[4]
PE[3]
PE[2]
PC[0]
PH[9]
VSS_LV
NC
PC[2]
PC[3]
PA[5]
PA[6]
NC
A
B
C
D
E
F
A
B
C
D
E
F
NC
PC[12]
PE[7]
NC
PH[10]
PC[1]
PG[11]
NC
PG[14]
PE[12]
PF[14]
PG[0]
PH[1]
NC
PA[11]
PA[9]
PE[13]
PA[10]
PA[8]
PA[7]
PC[14] VDD_HV
PB[3]
PC[15]
PG[3]
PA[1]
PE[10]
NC
NC
VDD_LV VDD_HV
NC
PG[4]
PE[0]
PE[9]
PG[5]
PA[2]
PE[8]
PG[2]
PE[1]
PA[0]
NC
PF[15] VDD_HV
PH[3]
NC
PH[2]
MSEO
MDO1
NC
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
G
H
J
G
H
J
VSS_HV PE[11] VDD_HV
MDO2
NC
MDO0
NC
RESET VSS_LV
NC
NC
EVTI
PG[9]
PG[7]
PB[1]
PF[8]
PF[12]
NC
NC
PG[8]
PG[6]
PF[9]
NC
VDD_BV VDD_LV
NC
PG[12]
PD[15]
PD[13]
PD[10]
PA[3]
PD[14]
PD[12]
PD[9]
PB[6]
PG[13]
PB[14]
PB[12]
PD[11]
PB[7]
PB[5]
PB[4]
16
K
L
K
L
NC
PC[10]
PB[0]
PC[7]
PF[10]
NC
EVTO
PC[11]
NC
PB[15]
PB[13]
PB[11]
PD[3]
PD[4]
PD[5]
13
M
N
P
R
T
M
N
P
R
T
NC
NC
PA[4]
VSS_LV
VDD_LV
PA[13]
PA[12]
7
EXTAL VDD_HV
PF[0]
PF[1]
PF[3]
PF[2]
10
PF[4]
PF[5]
PF[7]
PF[6]
11
NC
VDD_HV
_ADC
NC
PA[14]
XTAL
NC
NC
8
PB[10]
PD[0]
PD[2]
PD[1]
12
OSC32K
_XTAL
VSS_HV
_ADC
PC[6]
NC
PF[11] VDD_HV PA[15]
PD[7]
PD[6]
OSC32K
_EXTAL
MCKO
NC
PF[13]
PD[8]
1
2
3
4
5
6
9
14
15
NC
Note: 208 MAPBGA available only as development package for Nexus 2+.
= Not connected
Figure 6. 208 MAPBGA configuration
3.2
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
•
•
•
•
•
•
•
PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
PA[8] (ABS[0]) is pull-up.
RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.
Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
Main oscillator pads (EXTAL, XTAL) are tristate.
Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
11
Package pinouts and signal descriptions
3.3
Voltage supply pins
Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply pairs are used for 1.2
V regulator stabilization.
Table 3. Voltage supply pin descriptions
Pin number
Port pin
Function
208
64 LQFP1
100 LQFP
144 LQFP
MAPBGA2
VDD_HV
Digital supply voltage
7, 28, 56 15, 37, 70, 84 19, 51, 100, C2, D9, E16,
123
G13, H3, N9,
R5
VSS_HV
Digital ground
6, 8, 26, 55
14, 16, 35,
69, 83
18, 20, 49, G7, G8, G9,
99, 122
G10, H1, H7,
H8, H9, H10,
J7, J8, J9,
J10, K7, K8,
K9, K10
VDD_LV
VSS_LV
VDD_BV
1.2V decoupling pins. Decoupling
11, 23, 57
10, 24, 58
19, 32, 85
18, 33, 86
23, 46, 124 D8, K4, P7
capacitor must be connected between
these pins and the nearest VSS_LV pin.3
1.2V decoupling pins. Decoupling
22, 47, 125
C8, J2, N7
capacitor must be connected between
these pins and the nearest VDD_LV pin.3
Internal regulator supply voltage
12
33
20
51
24
73
K3
VSS_HV_ADC Reference ground and analog ground for
the ADC
R15
VDD_HV_ADC Reference voltage and analog supply for
the ADC
34
52
74
P14
1
2
3
Pin numbers apply to both the MPC560xB and MPC560xC packages.
208 MAPBGA available only as development package for Nexus2+
A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable
voltage (see the recommended operating conditions in the device datasheet for details).
3.4
Pad types
In the device the following types of pads are available for system pins and functional port pins:
1
S = Slow
1 2
M = Medium
1 2
F = Fast
1
I = Input only with analog feature
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
1. See the I/O pad electrical characteristics in the device datasheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC
in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).
MPC5604B/C Microcontroller Data Sheet, Rev. 9
12
Freescale Semiconductor
Package pinouts and signal descriptions
3.5
System pins
The system pins are listed in Table 4.
Table 4. System pin descriptions
Pin number
Function
RESET Bidirectional reset with Schmitt-Trigger characteristics
and noise filter.
I/O
M
X
Input, weak
pull-up only
after PHASE2
9
17 21 J1
EXTAL Analog output of the oscillator amplifier circuit, when the I/O
oscillator is not in bypass mode.
Tristate
27 36 50 N8
Analog input for the clock generator when the oscillator is
in bypass mode.3
XTAL Analog input of the oscillator amplifier circuit. Needs to be
grounded if oscillator is used in bypass mode.3
I
X
Tristate
25 34 48 P8
1
2
3
Pin numbers apply to both the MPC560xB and MPC560xC packages.
208 MAPBGA available only as development package for Nexus2+
See the relevant section of the datasheet
3.6
Functional ports
The functional port pins are listed in Table 5.
Table 5. Functional port pin descriptions
Pin number
PA[0]
PA[1]
PCR[0] AF0
GPIO[0]
E0UC[0]
CLKOUT
—
SIUL
eMIOS_0 I/O
CGL
—
WKPU
I/O
M
S
Tristate
Tristate
5
4
5
4
12 16 G4
AF1
AF2
AF3
—
O
—
I
WKPU[19]4
PCR[1] AF0
GPIO[1]
E0UC[1]
—
SIUL
eMIOS_0 I/O
—
—
WKPU
WKPU
I/O
7
11 F3
AF1
AF2
AF3
—
—
—
I
—
NMI5
—
WKPU[2]4
I
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
13
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PA[2]
PA[3]
PA[4]
PCR[2] AF0
GPIO[2]
E0UC[2]
—
SIUL
eMIOS_0 I/O
—
—
WKPU
I/O
S
S
S
Tristate
Tristate
Tristate
3
3
5
9
F2
AF1
AF2
AF3
—
—
—
I
—
WKPU[3]4
PCR[3] AF0
GPIO[3]
E0UC[3]
—
—
EIRQ[0]
SIUL
eMIOS_0 I/O
—
—
SIUL
I/O
43 39 68 90 K15
AF1
AF2
AF3
—
—
—
I
PCR[4] AF0
GPIO[4]
E0UC[4]
—
SIUL
eMIOS_0 I/O
—
—
WKPU
I/O
20 20 29 43 N6
AF1
AF2
AF3
—
—
—
I
—
WKPU[9]4
PA[5]
PA[6]
PCR[5] AF0
GPIO[5]
E0UC[5]
—
SIUL
eMIOS_0 I/O
I/O
M
S
Tristate
Tristate
51 51 79 118 C11
52 52 80 119 D11
AF1
AF2
AF3
—
—
—
—
—
PCR[6] AF0
GPIO[6]
E0UC[6]
—
—
EIRQ[1]
SIUL
eMIOS_0 I/O
—
—
SIUL
I/O
AF1
AF2
AF3
—
—
—
I
PA[7]
PA[8]
PCR[7] AF0
GPIO[7]
E0UC[7]
LIN3TX
—
SIUL
eMIOS_0 I/O
LINFlex_3
—
I/O
S
S
Tristate
44 44 71 104 D16
AF1
AF2
AF3
—
O
—
I
EIRQ[2]
SIUL
PCR[8] AF0
GPIO[8]
E0UC[8]
—
SIUL
eMIOS_0 I/O
—
—
SIUL
I/O
Input, weak 45 45 72 105 C16
pull-up
AF1
AF2
AF3
—
—
—
I
I
I
—
EIRQ[3]
ABS[0]
LIN3RX
N/A6
—
BAM
LINFlex_3
PA[9]
PCR[9] AF0
AF1
GPIO[9]
E0UC[9]
—
—
FAB
SIUL
eMIOS_0 I/O
—
—
BAM
I/O
S
Pull-down
46 46 73 106 C15
AF2
—
—
I
AF3
N/A6
MPC5604B/C Microcontroller Data Sheet, Rev. 9
14
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PA[10] PCR[10] AF0
GPIO[10]
E0UC[10]
SDA
SIUL
eMIOS_0 I/O
I2C_0
—
I/O
S
S
S
Tristate
Tristate
Tristate
47 47 74 107 B16
48 48 75 108 B15
22 22 31 45 T7
AF1
AF2
AF3
I/O
—
—
PA[11] PCR[11] AF0
GPIO[11]
E0UC[11]
SCL
SIUL
eMIOS_0 I/O
I2C_0
—
I/O
AF1
AF2
AF3
I/O
—
—
PA[12] PCR[12] AF0
GPIO[12]
—
—
—
SIN_0
SIUL
—
—
—
DSPI0
I/O
—
—
—
I
AF1
AF2
AF3
—
PA[13] PCR[13] AF0
GPIO[13]
SOUT_0
—
SIUL
DSPI_0
—
I/O
O
—
—
M
M
Tristate
Tristate
21 21 30 44 R7
AF1
AF2
AF3
—
—
PA[14] PCR[14] AF0
GPIO[14]
SCK_0
CS0_0
—
SIUL
DSPI_0
DSPI_0
—
I/O
I/O
I/O
—
I
19 19 28 42 P6
AF1
AF2
AF3
—
EIRQ[4]
SIUL
PA[15] PCR[15] AF0
GPIO[15]
CS0_0
SIUL
DSPI_0
DSPI_0
—
I/O
I/O
I/O
—
I
M
Tristate
18 18 27 40 R6
AF1
AF2
AF3
—
SCK_0
—
WKPU[10]4
WKPU
PB[0]
PB[1]
PCR[16] AF0
GPIO[16]
CAN0TX
—
SIUL
FlexCAN_0
I/O
O
—
—
M
S
Tristate
Tristate
14 14 23 31 N3
AF1
AF2
AF3
—
—
—
PCR[17] AF0
GPIO[17]
—
SIUL
—
—
I/O
—
—
—
I
15 15 24 32 N1
AF1
AF2
AF3
—
—
—
—
WKPU[4]4
CAN0RX
WKPU
FlexCAN_0
—
I
PB[2]
PCR[18] AF0
GPIO[18]
LIN0TX
SDA
SIUL
LINFlex_0
I2C_0
—
I/O
O
I/O
—
M
Tristate
64 64 100 144 B2
AF1
AF2
AF3
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
15
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PB[3]
PCR[19] AF0
GPIO[19]
—
SIUL
—
I2C_0
—
WKPU
LINFlex_0
I/O
—
I/O
—
I
S
Tristate
1
1
1
1
C3
AF1
AF2
AF3
—
SCL
—
WKPU[11]4
LIN0RX
—
I
PB[4]
PB[5]
PB[6]
PB[7]
PB[8]
PCR[20] AF0
GPIO[20]
—
—
—
GPI[0]
SIUL
—
—
—
ADC
I
I
I
I
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
32 32 50 72 T16
AF1
AF2
AF3
—
—
—
—
I
PCR[21] AF0
GPIO[21]
—
—
—
GPI[1]
SIUL
—
—
—
ADC
I
35
36
—
—
53 75 R16
AF1
AF2
AF3
—
—
—
—
I
PCR[22] AF0
GPIO[22]
—
—
—
GPI[2]
SIUL
—
—
—
ADC
I
54 76 P15
AF1
AF2
AF3
—
—
—
—
I
PCR[23] AF0
GPIO[23]
—
—
—
GPI[3]
SIUL
—
—
—
ADC
I
37 35 55 77 P16
AF1
AF2
AF3
—
—
—
—
I
PCR[24] AF0
GPIO[24]
SIUL
—
—
—
ADC
SXOSC
I
30 30 39 53 R9
AF1
AF2
AF3
—
—
—
—
—
—
—
I
ANS[0]
—
OSC32K_XTAL7
I/O
PB[9]
PCR[25] AF0
GPIO[25]
SIUL
—
—
—
ADC
SXOSC
I
I
Tristate
29 29 38 52 T9
AF1
AF2
AF3
—
—
—
—
—
—
—
I
ANS[1]
—
OSC32K_EXTAL7
I/O
MPC5604B/C Microcontroller Data Sheet, Rev. 9
16
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PB[10] PCR[26] AF0
GPIO[26]
—
SIUL
—
—
—
ADC
WKPU
I/O
—
—
—
I
J
Tristate
31 31 40 54 P9
AF1
AF2
AF3
—
—
—
ANS[2]
—
WKPU[8]4
I
PB[11]8 PCR[27] AF0
GPIO[27]
E0UC[3]
—
CS0_0
ANS[3]
SIUL
eMIOS_0 I/O
—
DSPI_0
ADC
I/O
J
J
J
J
J
Tristate
Tristate
Tristate
Tristate
Tristate
38 36 59 81 N13
AF1
AF2
AF3
—
—
I/O
I
PB[12] PCR[28] AF0
GPIO[28]
E0UC[4]
—
CS1_0
ANX[0]
SIUL
eMIOS_0 I/O
—
DSPI_0
ADC
I/O
39
40
—
—
61 83 M16
AF1
AF2
AF3
—
—
O
I
PB[13] PCR[29] AF0
GPIO[29]
E0UC[5]
—
CS2_0
ANX[1]
SIUL
eMIOS_0 I/O
—
DSPI_0
ADC
I/O
63 85 M13
AF1
AF2
AF3
—
—
O
I
PB[14] PCR[30] AF0
GPIO[30]
E0UC[6]
—
CS3_0
ANX[2]
SIUL
eMIOS_0 I/O
—
DSPI_0
ADC
I/O
41 37 65 87 L16
AF1
AF2
AF3
—
—
O
I
PB[15] PCR[31] AF0
GPIO[31]
E0UC[7]
—
CS4_0
ANX[3]
SIUL
eMIOS_0 I/O
—
DSPI_0
ADC
I/O
42 38 67 89 L13
AF1
AF2
AF3
—
—
O
I
PC[0]9 PCR[32] AF0
GPIO[32]
SIUL
—
JTAGC
—
I/O
—
I
M
M
Input, weak 59 59 87 126 A8
pull-up
AF1
AF2
AF3
—
TDI
—
—
PC[1]9 PCR[33] AF0
GPIO[33]
—
SIUL
—
JTAGC
—
I/O
—
O
Tristate
54 54 82 121 C9
AF1
AF2
AF3
TDO10
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
17
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PC[2]
PC[3]
PCR[34] AF0
GPIO[34]
SCK_1
CAN4TX11
—
SIUL
DSPI_1
FlexCAN_4
—
I/O
I/O
O
—
I
M
S
Tristate
Tristate
50 50 78 117 A11
AF1
AF2
AF3
—
EIRQ[5]
SIUL
PCR[35] AF0
GPIO[35]
CS0_1
MA[0]
SIUL
DSPI_1
ADC
I/O
I/O
O
—
I
49 49 77 116 B11
AF1
AF2
AF3
—
—
—
—
—
CAN1RX
CAN4RX11
EIRQ[6]
FlexCAN_1
FlexCAN_4
SIUL
I
I
PC[4]
PC[5]
PCR[36] AF0
GPIO[36]
SIUL
—
—
I/O
—
—
—
I
M
M
Tristate
Tristate
62 62 92 131 B7
AF1
AF2
AF3
—
—
—
—
—
SIN_1
DSPI_1
FlexCAN_3
—
CAN3RX11
I
PCR[37] AF0
GPIO[37]
SOUT_1
CAN3TX11
—
SIUL
DSPI1
FlexCAN_3
—
I/O
O
O
—
I
61 61 91 130 A7
AF1
AF2
AF3
—
EIRQ[7]
SIUL
PC[6]
PC[7]
PCR[38] AF0
GPIO[38]
LIN1TX
—
SIUL
LINFlex_1
—
I/O
O
—
—
S
S
Tristate
Tristate
16 16 25 36 R2
AF1
AF2
AF3
—
—
PCR[39] AF0
GPIO[39]
SIUL
—
—
I/O
—
—
—
I
17 17 26 37 P3
AF1
AF2
AF3
—
—
—
—
—
LIN1RX
LINFlex_1
WKPU
—
WKPU[12]4
I
PC[8]
PCR[40] AF0
GPIO[40]
LIN2TX
—
SIUL
LINFlex_2
—
I/O
O
—
—
S
Tristate
63 63 99 143 A1
AF1
AF2
AF3
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
18
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PC[9]
PCR[41] AF0
GPIO[41]
SIUL
—
—
I/O
—
—
—
I
S
Tristate
2
2
2
2
B1
AF1
AF2
AF3
—
—
—
—
—
LIN2RX
LINFlex_2
WKPU
—
WKPU[13]4
I
PC[10] PCR[42] AF0
GPIO[42]
CAN1TX
CAN4TX11
MA[1]
SIUL
FlexCAN_1
FlexCAN_4
ADC
I/O
O
O
M
S
Tristate
Tristate
13 13 22 28 M3
AF1
AF2
AF3
O
PC[11] PCR[43] AF0
GPIO[43]
—
SIUL
—
—
I/O
—
—
—
I
—
—
—
—
21 27 M4
AF1
AF2
AF3
—
—
—
—
—
—
CAN1RX
CAN4RX11
WKPU[5]4
FlexCAN_1
FlexCAN_4
WKPU
I
I
PC[12] PCR[44] AF0
GPIO[44]
E0UC[12]
—
—
SIN_2
SIUL
eMIOS_0 I/O
—
—
DSPI_2
I/O
M
Tristate
97 141 B4
AF1
AF2
AF3
—
—
—
I
PC[13] PCR[45] AF0
GPIO[45]
E0UC[13]
SOUT_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
I/O
S
S
Tristate
Tristate
—
—
—
—
98 142 A2
AF1
AF2
AF3
O
—
PC[14] PCR[46] AF0
GPIO[46]
E0UC[14]
SCK_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
SIUL
I/O
3
4
3
4
C1
D3
AF1
AF2
AF3
—
I/O
—
I
EIRQ[8]
PC[15] PCR[47] AF0
GPIO[47]
E0UC[15]
CS0_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
I/O
M
I
Tristate
Tristate
—
—
—
—
AF1
AF2
AF3
I/O
—
PD[0]
PCR[48] AF0
GPIO[48]
—
—
—
GPI[4]
SIUL
—
—
—
ADC
I
41 63 P12
AF1
AF2
AF3
—
—
—
—
I
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
19
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PCR[49] AF0
GPIO[49]
—
—
—
GPI[5]
SIUL
—
—
—
ADC
I
I
I
I
I
I
I
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
42 64 T12
43 65 R12
44 66 P13
45 67 R13
46 68 T13
47 69 T14
48 70 R14
49 71 T15
AF1
AF2
AF3
—
—
—
—
I
PCR[50] AF0
GPIO[50]
—
—
—
GPI[6]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
—
AF1
AF2
AF3
—
—
—
—
I
PCR[51] AF0
GPIO[51]
—
—
—
GPI[7]
SIUL
—
—
—
ADC
I
AF1
AF2
AF3
—
—
—
—
I
PCR[52] AF0
GPIO[52]
—
—
—
GPI[8]
SIUL
—
—
—
ADC
I
AF1
AF2
AF3
—
—
—
—
I
PCR[53] AF0
GPIO[53]
—
—
—
GPI[9]
SIUL
—
—
—
ADC
I
AF1
AF2
AF3
—
—
—
—
I
PCR[54] AF0
GPIO[54]
SIUL
—
—
—
ADC
I
AF1
AF2
AF3
—
—
—
—
—
—
—
I
GPI[10]
PCR[55] AF0
GPIO[55]
SIUL
—
—
—
ADC
I
AF1
AF2
AF3
—
—
—
—
—
—
—
I
GPI[11]
PCR[56] AF0
GPIO[56]
SIUL
—
—
—
ADC
I
AF1
AF2
AF3
—
—
—
—
—
—
—
I
GPI[12]
MPC5604B/C Microcontroller Data Sheet, Rev. 9
20
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PD[9]
PCR[57] AF0
GPIO[57]
SIUL
—
—
—
ADC
I
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
56 78 N15
57 79 N14
58 80 N16
60 82 M15
62 84 M14
64 86 L15
66 88 L14
AF1
AF2
AF3
—
—
—
—
—
—
—
I
GPI[13]
PD[10] PCR[58] AF0
GPIO[58]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
—
AF1
AF2
AF3
—
—
—
—
—
—
—
I
GPI[14]
PD[11] PCR[59] AF0
GPIO[59]
SIUL
—
—
—
ADC
I
I
AF1
AF2
AF3
—
—
—
—
—
—
—
I
GPI[15]
PD[12]8 PCR[60] AF0
GPIO[60]
CS5_0
E0UC[24]
—
SIUL
DSPI_0
eMIOS_0 I/O
—
ADC
I/O
O
J
J
J
J
S
AF1
AF2
AF3
—
—
I
ANS[4]
PD[13] PCR[61] AF0
GPIO[61]
CS0_1
E0UC[25]
—
SIUL
DSPI_1
eMIOS_0 I/O
—
ADC
I/O
I/O
AF1
AF2
AF3
—
—
I
ANS[5]
PD[14] PCR[62] AF0
GPIO[62]
CS1_1
E0UC[26]
—
SIUL
DSPI_1
eMIOS_0 I/O
—
ADC
I/O
O
AF1
AF2
AF3
—
—
I
ANS[6]
PD[15] PCR[63] AF0
GPIO[63]
CS2_1
E0UC[27]
—
SIUL
DSPI_1
eMIOS_0 I/O
—
ADC
I/O
O
AF1
AF2
AF3
—
—
I
ANS[7]
PE[0]
PCR[64] AF0
GPIO[64]
E0UC[16]
—
SIUL
eMIOS_0 I/O
I/O
6
10 F1
AF1
AF2
AF3
—
—
—
—
—
I
—
CAN5RX11
WKPU[6]4
FlexCAN_5
WKPU
—
I
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
21
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PE[1]
PE[2]
PCR[65] AF0
GPIO[65]
E0UC[17]
CAN5TX11
—
SIUL
eMIOS_0 I/O
FlexCAN_5
—
I/O
M
M
Tristate
Tristate
—
—
—
8
12 F4
AF1
AF2
AF3
O
—
PCR[66] AF0
GPIO[66]
E0UC[18]
—
—
SIN_1
SIUL
eMIOS_0 I/O
—
—
DSPI_1
I/O
—
89 128 D7
AF1
AF2
AF3
—
—
—
I
PE[3]
PE[4]
PCR[67] AF0
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0 I/O
DSPI_1
—
I/O
M
M
Tristate
Tristate
—
—
—
—
90 129 C7
93 132 D6
AF1
AF2
AF3
O
—
PCR[68] AF0
GPIO[68]
E0UC[20]
SCK_1
—
SIUL
eMIOS_0 I/O
DSPI_1
—
SIUL
I/O
AF1
AF2
AF3
—
I/O
—
I
EIRQ[9]
PE[5]
PE[6]
PE[7]
PE[8]
PE[9]
PCR[69] AF0
GPIO[69]
E0UC[21]
CS0_1
SIUL
eMIOS_0 I/O
DSPI_1
ADC
I/O
M
M
M
M
S
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
—
94 133 C6
95 139 B5
96 140 C4
AF1
AF2
AF3
I/O
O
MA[2]
PCR[70] AF0
GPIO[70]
E0UC[22]
CS3_0
SIUL
eMIOS_0 I/O
DSPI_0
ADC
I/O
AF1
AF2
AF3
O
O
MA[1]
PCR[71] AF0
GPIO[71]
E0UC[23]
CS2_0
SIUL
eMIOS_0 I/O
DSPI_0
ADC
I/O
AF1
AF2
AF3
O
O
MA[0]
PCR[72] AF0
GPIO[72]
CAN2TX12
E0UC[22]
CAN3TX11
SIUL
FlexCAN_2
eMIOS_0 I/O
FlexCAN_3
I/O
O
9
13 G2
AF1
AF2
AF3
O
PCR[73] AF0
GPIO[73]
—
SIUL
—
eMIOS_0 I/O
—
WKPU
I/O
—
10 14 G1
AF1
AF2
AF3
—
—
—
E0UC[23]
—
—
WKPU[7]4
CAN2RX12
CAN3RX11
I
I
I
FlexCAN_2
FlexCAN_3
MPC5604B/C Microcontroller Data Sheet, Rev. 9
22
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PE[10] PCR[74] AF0
GPIO[74]
LIN3TX
CS3_1
—
SIUL
LINFlex_3
DSPI_1
—
I/O
O
O
—
I
S
S
Tristate
Tristate
—
—
—
11 15 G3
AF1
AF2
AF3
—
EIRQ[10]
SIUL
PE[11] PCR[75] AF0
GPIO[75]
—
CS4_1
—
SIUL
—
DSPI_1
—
LINFlex_3
WKPU
I/O
—
O
—
I
—
—
13 17 H2
AF1
AF2
AF3
—
LIN3RX
—
WKPU[14]4
I
PE[12] PCR[76] AF0
GPIO[76]
—
SIUL
—
eMIOS_1 I/O
—
DSPI_2
SIUL
I/O
—
S
Tristate
—
76 109 C14
AF1
AF2
AF3
—
E1UC[19]13
—
—
I
I
SIN_2
EIRQ[11]
—
PE[13] PCR[77] AF0
GPIO[77]
SOUT2
E1UC[20]
—
SIUL
DSPI_2
eMIOS_1 I/O
I/O
O
S
S
Tristate
Tristate
—
—
—
—
—
—
103 D15
112 C13
AF1
AF2
AF3
—
—
PE[14] PCR[78] AF0
GPIO[78]
SCK_2
E1UC[21]
—
SIUL
DSPI_2
eMIOS_1 I/O
—
SIUL
I/O
I/O
AF1
AF2
AF3
—
—
I
EIRQ[12]
PE[15] PCR[79] AF0
GPIO[79]
CS0_2
E1UC[22]
—
SIUL
DSPI_2
eMIOS_1 I/O
I/O
I/O
M
J
Tristate
Tristate
—
—
—
—
—
—
113 A13
55 N10
AF1
AF2
AF3
—
—
PF[0]
PF[1]
PCR[80] AF0
GPIO[80]
E0UC[10]
CS3_1
—
SIUL
eMIOS_0 I/O
DSPI_1
—
ADC
I/O
AF1
AF2
AF3
—
O
—
I
ANS[8]
PCR[81] AF0
GPIO[81]
E0UC[11]
CS4_1
—
SIUL
eMIOS_0 I/O
DSPI_1
I/O
J
Tristate
—
—
—
56 P10
AF1
AF2
AF3
—
O
—
I
—
I
ANS[9]
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
23
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PCR[82] AF0
GPIO[82]
E0UC[12]
CS0_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
ADC
I/O
J
J
J
J
J
J
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
—
—
—
—
57 T10
AF1
AF2
AF3
—
I/O
—
I
ANS[10]
PCR[83] AF0
GPIO[83]
E0UC[13]
CS1_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
ADC
I/O
—
—
—
—
—
58 R10
59 N11
60 P11
61 T11
62 R11
AF1
AF2
AF3
—
O
—
I
ANS[11]
PCR[84] AF0
GPIO[84]
E0UC[14]
CS2_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
ADC
I/O
AF1
AF2
AF3
—
O
—
I
ANS[12]
PCR[85] AF0
GPIO[85]
E0UC[22]
CS3_2
—
SIUL
eMIOS_0 I/O
DSPI_2
—
ADC
I/O
AF1
AF2
AF3
—
O
—
I
ANS[13]
PCR[86] AF0
GPIO[86]
E0UC[23]
—
—
ANS[14]
SIUL
eMIOS_0 I/O
—
—
ADC
I/O
AF1
AF2
AF3
—
—
—
I
PCR[87] AF0
GPIO[87]
SIUL
—
—
—
ADC
I/O
—
—
—
I
AF1
AF2
AF3
—
—
—
—
ANS[15]
PF[8]
PF[9]
PCR[88] AF0
GPIO[88]
CAN3TX14
CS4_0
SIUL
FlexCAN_3
DSPI_0
I/O
O
O
M
S
Tristate
Tristate
—
—
—
—
—
—
34 P1
33 N2
AF1
AF2
AF3
CAN2TX15
FlexCAN_2
O
PCR[89] AF0
GPIO[89]
—
SIUL
—
DSPI_0
—
FlexCAN_2
FlexCAN_3
I/O
—
O
—
I
AF1
AF2
AF3
—
CS5_0
—
CAN2RX15
CAN3RX14
—
I
MPC5604B/C Microcontroller Data Sheet, Rev. 9
24
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PF[10] PCR[90] AF0
GPIO[90]
SIUL
—
—
I/O
—
—
—
M
S
Tristate
Tristate
—
—
—
—
—
38 R3
AF1
AF2
AF3
—
—
—
—
PF[11] PCR[91] AF0
GPIO[91]
SIUL
—
—
—
WKPU
I/O
—
—
—
I
—
39 R4
AF1
AF2
AF3
—
—
—
—
WKPU[15]4
PF[12] PCR[92] AF0
GPIO[92]
E1UC[25]
—
SIUL
eMIOS_1 I/O
I/O
M
S
Tristate
Tristate
—
—
—
—
—
—
35 R1
41 T6
AF1
AF2
AF3
—
—
—
—
—
PF[13] PCR[93] AF0
GPIO[93]
E1UC[26]
—
SIUL
eMIOS_1 I/O
—
—
WKPU
I/O
AF1
AF2
AF3
—
—
—
I
—
WKPU[16]4
PF[14] PCR[94] AF0
GPIO[94]
CAN4TX11
E1UC[27]
CAN1TX
SIUL
FlexCAN_4
eMIOS_1 I/O
FlexCAN_4
I/O
O
M
S
Tristate
Tristate
—
—
43
42
—
—
102 D14
101 E15
AF1
AF2
AF3
O
PF[15] PCR[95] AF0
GPIO[95]
—
SIUL
—
—
I/O
—
—
—
I
AF1
AF2
AF3
—
—
—
—
—
—
CAN1RX
CAN4RX11
EIRQ[13]
FlexCAN_1
FlexCAN_4
SIUL
I
I
PG[0]
PG[1]
PCR[96] AF0
GPIO[96]
CAN5TX11
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1 I/O
I/O
O
M
S
Tristate
Tristate
—
—
41
40
—
—
98 E14
97 E13
AF1
AF2
AF3
—
—
PCR[97] AF0
GPIO[97]
—
SIUL
—
eMIOS_1 I/O
I/O
—
AF1
AF2
AF3
—
E1UC[24]
—
—
—
I
I
CAN5RX11
EIRQ[14]
FlexCAN_5
SIUL
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
25
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PG[2]
PG[3]
PCR[98] AF0
GPIO[98]
E1UC[11]
—
SIUL
eMIOS_1 I/O
I/O
M
S
Tristate
Tristate
—
—
—
—
—
—
8
7
E4
E3
AF1
AF2
AF3
—
—
—
—
—
PCR[99] AF0
GPIO[99]
E1UC[12]
—
SIUL
eMIOS_1 I/O
—
—
WKPU
I/O
AF1
AF2
AF3
—
—
—
I
—
WKPU[17]4
PG[4] PCR[100] AF0
GPIO[100]
E1UC[13]
—
SIUL
eMIOS_1 I/O
I/O
M
S
Tristate
Tristate
—
—
—
—
—
—
6
5
E1
E2
AF1
AF2
AF3
—
—
—
—
—
PG[5] PCR[101] AF0
GPIO[101]
E1UC[14]
—
SIUL
eMIOS_1 I/O
—
—
WKPU
I/O
AF1
AF2
AF3
—
—
—
I
—
WKPU[18]4
PG[6] PCR[102] AF0
GPIO[102]
E1UC[15]
—
SIUL
eMIOS_1 I/O
I/O
M
M
S
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
30 M2
29 M1
26 L2
AF1
AF2
AF3
—
—
—
—
—
PG[7] PCR[103] AF0
GPIO[103]
E1UC[16]
—
SIUL
eMIOS_1 I/O
I/O
AF1
AF2
AF3
—
—
—
—
—
PG[8] PCR[104] AF0
GPIO[104]
E1UC[17]
—
CS0_2
EIRQ[15]
SIUL
eMIOS_1 I/O
—
DSPI_2
SIUL
I/O
AF1
AF2
AF3
—
—
I/O
I
PG[9] PCR[105] AF0
GPIO[105]
E1UC[18]
—
SIUL
eMIOS_1 I/O
—
DSPI_2
I/O
S
S
Tristate
Tristate
—
—
—
—
—
—
25 L1
AF1
AF2
AF3
—
I/O
SCK_2
PG[10] PCR[106] AF0
GPIO[106]
E0UC[24]
—
SIUL
eMIOS_0 I/O
I/O
114 D13
AF1
AF2
AF3
—
—
—
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
26
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PG[11] PCR[107] AF0
GPIO[107]
E0UC[25]
—
SIUL
eMIOS_0 I/O
I/O
M
M
M
S
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
—
—
—
—
115 B12
AF1
AF2
AF3
—
—
—
—
—
PG[12] PCR[108] AF0
GPIO[108]
E0UC[26]
—
SIUL
eMIOS_0 I/O
I/O
—
—
—
—
—
92 K14
91 K16
110 B14
111 B13
93 F13
AF1
AF2
AF3
—
—
—
—
—
PG[13] PCR[109] AF0
GPIO[109]
E0UC[27]
—
SIUL
eMIOS_0 I/O
I/O
AF1
AF2
AF3
—
—
—
—
—
PG[14] PCR[110] AF0
GPIO[110]
E1UC[0]
—
SIUL
eMIOS_1 I/O
I/O
AF1
AF2
AF3
—
—
—
—
—
PG[15] PCR[111] AF0
GPIO[111]
E1UC[1]
—
SIUL
eMIOS_1 I/O
I/O
M
M
AF1
AF2
AF3
—
—
—
—
—
PH[0] PCR[112] AF0
GPIO[112]
E1UC[2]
—
SIUL
eMIOS_1 I/O
—
—
DSPI_1
I/O
AF1
AF2
AF3
—
—
—
I
—
SIN1
PH[1] PCR[113] AF0
GPIO[113]
E1UC[3]
SOUT1
—
SIUL
eMIOS_1 I/O
DSPI_1
—
I/O
M
M
M
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
94 F14
95 F16
96 F15
AF1
AF2
AF3
O
—
PH[2] PCR[114] AF0
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1 I/O
DSPI_1
—
I/O
AF1
AF2
AF3
I/O
—
PH[3] PCR[115] AF0
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1 I/O
DSPI_1
—
I/O
AF1
AF2
AF3
I/O
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
27
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
PH[4] PCR[116] AF0
GPIO[116]
E1UC[6]
—
SIUL
eMIOS_1 I/O
I/O
M
S
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
—
—
134 A6
AF1
AF2
AF3
—
—
—
—
—
PH[5] PCR[117] AF0
GPIO[117]
E1UC[7]
—
SIUL
eMIOS_1 I/O
I/O
—
—
—
—
135 B6
136 D5
137 C5
138 A5
AF1
AF2
AF3
—
—
—
—
—
PH[6] PCR[118] AF0
GPIO[118]
E1UC[8]
—
SIUL
eMIOS_1 I/O
—
ADC
I/O
M
M
M
S
AF1
AF2
AF3
—
O
MA[2]
PH[7] PCR[119] AF0
GPIO[119]
E1UC[9]
CS3_2
SIUL
eMIOS_1 I/O
DSPI_2
ADC
I/O
AF1
AF2
AF3
O
O
MA[1]
PH[8] PCR[120] AF0
GPIO[120]
E1UC[10]
CS2_2
SIUL
eMIOS_1 I/O
DSPI_2
ADC
I/O
AF1
AF2
AF3
O
O
MA[0]
PH[9]9 PCR[121] AF0
GPIO[121]
SIUL
—
JTAGC
—
I/O
—
I
Input, weak 60 53 88 127 B8
pull-up
AF1
AF2
AF3
—
TCK
—
—
PH[10]9 PCR[122] AF0
GPIO[122]
SIUL
—
JTAGC
—
I/O
—
I
S
Input, weak 60 53 81 120 B9
pull-up
AF1
AF2
AF3
—
TMS
—
—
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF3. This is intended to select
the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the
values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
2
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
3
4
5
6
208 MAPBGA available only as development package for Nexus2+
All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details.
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
“Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the
reference manual for details.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
28
Freescale Semiconductor
Package pinouts and signal descriptions
7
8
Value of PCR.IBE bit must be 0
Be aware that this pad is used on the MPC5607B 100-pin and 144-pin to provide VDD_HV_ADC and
VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between MPC5604B/C and
MPC5607B.
9
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.
10 The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in
STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad
is configured as an input. When no debugger is connected the TDO pad is floating causing additional current
consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of
47–100 k should be added between the TDO pin and VDD. Only in case the TDO pin is used as application pin
and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and
GND instead.
11 Available only on MPC560xC versions and MPC5604B 208 MAPBGA devices
12 Not available on MPC5602B devices
13 Not available in 100 LQFP package
14 Available only on MPC5604B 208 MAPBGA devices
15 Not available on MPC5603B 144-pin devices
3.7
Nexus 2+ pins
In the 208 MAPBGA package, eight additional debug pins are available (see Table 6).
Table 6. Nexus 2+ pin descriptions
Pin number
I/O
direction
Function
after reset
Debug pin
Function
Pad type
100
144
208 MAP
BGA1
LQFP
LQFP
MCKO
MDO0
MDO1
MDO2
MDO3
EVTI
Message clock out
Message data out 0
Message data out 1
Message data out 2
Message data out 3
Event in
O
O
O
O
O
I
F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T4
H15
H16
H14
H13
K1
M
M
M
M
M
M
M
—
—
—
Pull-up
—
EVTO
MSEO
Event out
O
O
L4
Message start/end out
—
G16
1
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
29
Electrical characteristics
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid applying any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by
DD
SS
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 7 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 7. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.3
NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical
parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after
reset).
For a detailed description of the NVUSRO register, please refer to the device reference manual.
4.3.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 8 shows how NVUSRO[PAD3V5V] controls
the device configuration.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
30
Freescale Semiconductor
Electrical characteristics
Table 8. PAD3V5V field description
Description
Value1
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 9 shows how
NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 9. OSCILLATOR_MARGIN field description
Value1
Description
0
1
Low consumption configuration (4 MHz/8 MHz)
High margin configuration (4 MHz/16 MHz)
1
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.3.3
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 10 shows how
NVUSRO[WATCHDOG_EN] controls the device configuration.
Table 10. WATCHDOG_EN field description
Value1
Description
0
1
Disable after reset
Enable after reset
1
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
31
Electrical characteristics
4.4
Absolute maximum ratings
Table 11. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
VDD
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
SR Voltage on VDD_HV pins with respect to
0.3
6.0
ground (VSS
)
VSS_LV SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
—
—
VSS0.1 VSS+0.1
V
(VSS
)
VDD_BV SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS
0.3
0.3
6.0
V
V
)
Relative to VDD
VDD+0.3
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
—
VSS0.1 VSS+0.1
reference) pin with respect to ground
(VSS
)
VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS
—
—
0.3
6.0
V
V
)
Relative to VDD
Relative to VDD
VDD 0.3 VDD+0.3
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS
0.3
—
6.0
VDD+0.3
10
)
IINJPAD SR Injected input current on any pin during
overload condition
—
—
10
mA
IINJSUM SR Absolute sum of all injected input
currents during overload condition
50
50
IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V 10%, PAD3V5V = 0
—
—
—
70
64
mA
supply segment
VDD = 3.3 V 10%, PAD3V5V = 1
ICORELV SR Low voltage static current sink through
VDD_BV
—
150
mA
°C
TSTORAGE SR Storage temperature
—
55
150
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
32
Freescale Semiconductor
Electrical characteristics
4.5
Recommended operating conditions
Table 12. Recommended operating conditions (3.3 V)
Value
Unit
Symbol
Parameter
Conditions
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect to ground
3.0
3.6
(VSS
)
2
VSS_LV
SR Voltage on VSS_LV (low voltage digital supply)
—
—
VSS0.1 VSS+0.1
3.0 3.6
V
V
pins with respect to ground (VSS
)
3
VDD_BV
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS
)
Relative to VDD VDD0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS
—
VSS0.1 VSS+0.1
V
V
)
VDD_ADC
SR Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS
—
3.05
3.6
4
)
Relative to VDD VDD0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to ground
(VSS
—
Relative to VDD
—
VSS0.1
—
—
VDD+0.1
5
V
)
IINJPAD
IINJSUM
TVDD
SR Injected input current on any pin during overload
condition
5
mA
SR Absolute sum of all injected input currents during
overload condition
—
50
50
SR VDD slope to ensure correct power up6
—
—
0.25
85
V/µs
°C
TA C-Grade Part SR Ambient temperature under bias
TJ C-Grade Part SR Junction temperature under bias
TA V-Grade Part SR Ambient temperature under bias
TJ V-Grade Part SR Junction temperature under bias
TA M-Grade Part SR Ambient temperature under bias
TJ M-Grade Part SR Junction temperature under bias
100 nF capacitance needs to be provided between each VDD/VSS pair
fCPU 64 MHz
40
40
40
40
40
40
110
105
130
125
150
1
2
3
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4
5
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL
device is reset.
,
6
Guaranteed by device validation
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
33
Electrical characteristics
Symbol
Table 13. Recommended operating conditions (5.0 V)
Value
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect to
—
Voltage drop2
—
4.5
3.0
5.5
5.5
ground (VSS
)
3
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS
VSS0.1 VSS+0.1
V
V
)
4
VDD_BV
SR Voltage on VDD_BV pin (regulator supply)
with respect to ground (VSS
—
4.5
3.0
5.5
5.5
)
Voltage drop2
Relative to VDD VDD0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference)
pin with respect to ground (VSS
—
VSS0.1 VSS+0.1
V
V
5
VDD_ADC
SR Voltage on VDD_HV_ADC pin (ADC
—
4.5
3.0
5.5
5.5
reference) with respect to ground (VSS
)
Voltage drop2
Relative to VDD VDD0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS
—
Relative to VDD
—
VSS0.1
—
—
VDD+0.1
5
V
)
IINJPAD
IINJSUM
SR Injected input current on any pin during
overload condition
5
mA
SR Absolute sum of all injected input currents
during overload condition
—
50
50
TVDD
SR VDD slope to ensure correct power up6
SR Ambient temperature under bias
SR Junction temperature under bias
SR Ambient temperature under bias
SR Junction temperature under bias
SR Ambient temperature under bias
SR Junction temperature under bias
—
—
0.25
85
V/µs
°C
TA C-Grade Part
TJ C-Grade Part
TA V-Grade Part
TJ V-Grade Part
TA M-Grade Part
TJ M-Grade Part
fCPU 64 MHz
40
40
40
40
40
40
110
105
130
125
150
1
2
100 nF capacitance needs to be provided between each VDD/VSS pair.
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3
4
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5
6
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Guaranteed by device validation
NOTE
RAM data retention is guaranteed with V
not below 1.08 V.
DD_LV
MPC5604B/C Microcontroller Data Sheet, Rev. 9
34
Freescale Semiconductor
Electrical characteristics
4.6
Thermal characteristics
4.6.1
Package thermal characteristics
1
Table 14. LQFP thermal characteristics
Conditions2
Symbol
C
Parameter
Thermal resistance,
Pin count Value Unit
RJA CC
D
Single-layer board - 1s
Four-layer board - 2s2p
Single-layer board - 1s
Four-layer board - 2s2p
Single-layer board - 1s
Four-layer board - 2s2p
Single-layer board - 1s
Four-layer board - 2s2p
Single-layer board - 1s
Four-layer board - 2s2p
64
100
144
64
60
64
64
42
51
49
24
36
37
24
34
35
11
22
22
11
22
22
°C/W
°C/W
°C/W
junction-to-ambient natural
convection3
100
144
64
RJB CC
RJC CC
JB CC
JC CC
D
D
D
D
Thermal resistance,
junction-to-board4
100
144
64
100
144
64
Thermal resistance,
junction-to-case5
100
144
64
100
144
64
Junction-to-board thermal
characterization parameter,
natural convection
TBD °C/W
100
144
64
33
34
TBD
100
144
64
34
35
Junction-to-case thermal
characterization parameter,
natural convection
TBD °C/W
100
144
64
9
10
TBD
9
100
144
10
1
Thermal characteristics are based on simulation.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
35
Electrical characteristics
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C
3
4
5
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test
board meets JEDEC specification for this package.
Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer.
4.6.2
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:
J
T = T + (P x R )
JA
Eqn. 1
J
A
D
Where:
T is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
JA
P is the sum of P
and P (P = P
+ P ).
D
INT
I/O
D
INT I/O
P
P
is the product of I and V , expressed in watts. This is the chip internal power.
DD DD
INT
I/O
represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, P < P
and may be neglected. On the other hand, P may be significant, if the device
I/O
INT
I/O
is configured to continuously drive external modules and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273 °C)
Eqn. 2
Eqn. 3
D
J
Therefore, solving equations 1 and 2:
Where:
2
K = P x (T + 273 °C) + R
x P
D
D
A
JA
K is a constant for the particular part, which may be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T Using this value of K, the values of P and T may be obtained by solving equations 1 and 2
A.
D
J
iteratively for any value of T .
A
4.7
I/O pad electrical characteristics
I/O pad types
4.7.1
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads—These pads provide transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
•
•
Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging capability.
Input only pads—These pads are associated to ADC channels and the external 32 kHz crystal oscillator (SXOSC)
providing low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
36
Freescale Semiconductor
Electrical characteristics
4.7.2
I/O input DC characteristics
Table 15 provides input DC electrical characteristics as described in Figure 7.
V
IN
V
DD
V
IH
V
HYS
V
IL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 7. I/O input DC electrical characteristics definition
Table 15. I/O input DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input high level CMOS (Schmitt
Trigger)
—
—
—
0.65VDD
—
VDD+0.4
V
VIL SR P Input low level CMOS (Schmitt
Trigger)
0.4
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
0.1VDD
ILKG CC D Digital input leakage
No injection
on adjacent
pin
TA = 40 °C
TA = 25 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
—
—
2
2
200
200
300
500
1000
40
nA
D
D
D
P
—
5
—
12
70
—
—
—
2
WFI SR P Wakeup input filtered pulse
—
—
—
ns
ns
2
WNFI SR P Wakeup input not filtered pulse
1000
—
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
2
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
37
Electrical characteristics
4.7.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
Table 16 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 17 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 18 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 19 provides output driver characteristics for I/O pads when in FAST configuration.
Table 16. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
|IWPU| CC P Weak pull-up current
VIN = VIL, VDD = 5.0 V 10% PAD3V5V = 0
10
—
—
—
—
—
—
150 µA
250
absolute value
C
PAD3V5V = 12 10
P
VIN = VIL, VDD = 3.3 V 10% PAD3V5V = 1
10
10
10
10
150
|IWPD| CC P Weak pull-down current VIN = VIH, VDD = 5.0 V 10% PAD3V5V = 0
absolute value
150 µA
250
C
P
PAD3V5V = 1
VIN = VIH, VDD = 3.3 V 10% PAD3V5V = 1
150
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 17. SLOW configuration output buffer electrical characteristics
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
SLOW configuration
Push Pull IOH = 2 mA,
0.8VDD
—
—
V
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
I
OH = 2 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10%, PAD3V5V = 12
IOH = 1 mA,
VDD0.8
VDD = 3.3 V 10%, PAD3V5V = 1
(recommended)
VOL CC P Output low level
SLOW configuration
Push Pull IOL = 2 mA,
—
—
0.1VDD
V
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
I
OL = 2 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10%, PAD3V5V = 12
IOL = 1 mA,
VDD = 3.3 V 10%, PAD3V5V = 1
(recommended)
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
2
MPC5604B/C Microcontroller Data Sheet, Rev. 9
38
Freescale Semiconductor
Electrical characteristics
Table 18. MEDIUM configuration output buffer electrical characteristics
Value
Typ Max
Symbol C
Parameter
Conditions1
Unit
Min
VOH CC C Output high level
MEDIUM configuration
Push Pull IOH = 3.8 mA,
VDD = 5.0 V 10%, PAD3V5V = 0
0.8VDD
—
—
V
P
I
OH = 2 mA,
0.8VDD
—
—
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
I
OH = 1 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10%, PAD3V5V = 12
I
OH = 1 mA,
DD = 3.3 V 10%, PAD3V5V = 1
(recommended)
VDD0.8
V
C
I
OH = 100 µA,
0.8VDD
—
—
—
—
—
VDD = 5.0 V 10%, PAD3V5V = 0
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
0.2VDD
0.1VDD
V
MEDIUM configuration
VDD = 5.0 V 10%, PAD3V5V = 0
P
IOL = 2 mA,
—
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
IOL = 1 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10%, PAD3V5V = 12
IOL = 1 mA,
VDD = 3.3 V 10%, PAD3V5V = 1
(recommended)
C
I
OL = 100 µA,
—
—
0.1VDD
VDD = 5.0 V 10%, PAD3V5V = 0
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 19. FAST configuration output buffer electrical characteristics
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
FAST configuration
Push Pull IOH = 14mA,
0.8VDD
—
—
V
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
I
OH = 7mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10%, PAD3V5V = 12
IOH = 11mA,
VDD0.8
VDD = 3.3 V 10%, PAD3V5V = 1
(recommended)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
39
Electrical characteristics
Table 19. FAST configuration output buffer electrical characteristics (continued)
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ
Max
VOL CC P Output low level
FAST configuration
Push Pull IOL = 14mA,
—
—
0.1VDD
V
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
I
OL = 7mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10%, PAD3V5V = 12
IOL = 11mA,
VDD = 3.3 V 10%, PAD3V5V = 1
(recommended)
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
2
4.7.4
Output pin transition times
Table 20. Output pin transition times
Value
Symbol C
Parameter
Conditions1
Unit
Min Typ Max
ttr CC D Output transition time output CL = 25 pF VDD = 5.0 V 10%, PAD3V5V = 0
pin2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50 ns
100
125
50
T
D
D
T
CL = 50 pF
SLOW configuration
CL = 100 pF
CL = 25 pF VDD = 3.3 V 10%, PAD3V5V = 1
CL = 50 pF
100
125
10 ns
20
D
CL = 100 pF
ttr CC D Output transition time output CL = 25 pF VDD = 5.0 V 10%, PAD3V5V = 0
pin2
SIUL.PCRx.SRC = 1
T
D
D
T
CL = 50 pF
MEDIUM configuration
CL = 100 pF
40
CL = 25 pF VDD = 3.3 V 10%, PAD3V5V = 1
12
SIUL.PCRx.SRC = 1
CL = 50 pF
25
D
CL = 100 pF
40
ttr CC D Output transition time output CL = 25 pF VDD = 5.0 V 10%, PAD3V5V = 0
4
6
ns
pin2
CL = 50 pF
FAST configuration
CL = 100 pF
CL = 25 pF VDD = 3.3 V 10%, PAD3V5V = 1
CL = 50 pF
12
4
7
CL = 100 pF
12
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
MPC5604B/C Microcontroller Data Sheet, Rev. 9
40
Freescale Semiconductor
Electrical characteristics
2
CL includes device and package capacitances (CPKG < 5 pF).
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as
DD SS
described in Table 21.
Table 21. I/O supply segment
Supply segment
Package
1
2
3
4
5
6
208 MAPBGA1
144 LQFP
100 LQFP
64 LQFP
Equivalent to 144 LQFP segment pad distribution
pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19
MCKO
—
MDOn/MSEO
—
—
—
pin16–pin35
pin8–pin26
pin37–pin69
pin28–pin55
pin70–pin83
pin56–pin7
pin 84–pin15
—
—
—
1
208 MAPBGA available only as development package for Nexus2+
Table 22 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I
maximum value.
AVGSEG
Table 22. I/O consumption
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ Max
,2
ISWTSLW CC D Dynamic I/O current for CL = 25 pF
SLOW configuration
VDD = 5.0 V 10%,
PAD3V5V = 0
—
—
—
—
—
—
—
20
16
29
17
mA
VDD = 3.3 V 10%,
PAD3V5V = 1
—
—
—
—
—
2
ISWTMED CC D Dynamic I/O current for CL = 25 pF
VDD = 5.0 V 10%,
PAD3V5V = 0
mA
MEDIUM configuration
VDD = 3.3 V 10%,
PAD3V5V = 1
2
ISWTFST CC D Dynamic I/O current for CL = 25 pF
VDD = 5.0 V 10%,
PAD3V5V = 0
110 mA
50
FAST configuration
VDD = 3.3 V 10%,
PAD3V5V = 1
IRMSSLW CC D Root mean square I/O CL = 25 pF, 2 MHz
VDD = 5.0 V 10%,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
2.3 mA
3.2
current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
6.6
VDD = 3.3 V 10%,
PAD3V5V = 1
1.6
2.3
4.7
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
41
Electrical characteristics
Table 22. I/O consumption (continued)
Conditions1
Value
Symbol
C
Parameter
Unit
Min
Typ Max
IRMSMED CC D Root mean square I/O CL = 25 pF, 13 MHz VDD = 5.0 V 10%,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6.6 mA
current for MEDIUM
configuration
PAD3V5V = 0
CL = 25 pF, 40 MHz
CL = 100 pF, 13 MHz
13.4
18.3
5
CL = 25 pF, 13 MHz VDD = 3.3 V 10%,
PAD3V5V = 1
CL = 25 pF, 40 MHz
8.5
11
CL = 100 pF, 13 MHz
IRMSFST CC D Root mean square I/O CL = 25 pF, 40 MHz VDD = 5.0 V 10%,
22
33
56
14
20
35
70
65
mA
current for FAST
configuration
PAD3V5V = 0
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz VDD = 3.3 V 10%,
PAD3V5V = 1
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
IAVGSEG SR D Sum of all the static I/O VDD = 5.0 V 10%, PAD3V5V = 0
current within a supply
mA
VDD = 3.3 V 10%, PAD3V5V = 1
segment
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
1
2
Table 23 provides the weight of concurrent switching I/Os.
Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on a single segment must not exceed
100% to ensure device functionality.
1
Table 23. I/O weight
144/100 LQFP
Weight 5 V Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
64 LQFP
Supply segment
Weight 5 V
Weight 3.3 V
Pad
144
100
64
LQFP LQFP LQFP2
4
4
3
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
10%
10%
9%
—
—
12%
12%
11%
11%
11%
10%
10%
—
—
10%
10%
—
—
—
—
—
—
—
—
12%
12%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9%
13%
—
12%
—
—
—
—
—
—
9%
—
—
9%
12%
—
11%
—
—
—
9%
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
42
Freescale Semiconductor
Electrical characteristics
1
Table 23. I/O weight (continued)
144/100 LQFP
64 LQFP
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
Supply segment
Weight 5 V
Weight 3.3 V
Weight 5 V
Pad
144
100
64
LQFP LQFP LQFP2
4
—
4
—
3
PG[2]
PA[2]
8%
8%
12%
—
10%
9%
10%
—
—
8%
—
—
—
—
9%
—
—
—
—
3
PE[0]
PA[1]
8%
—
9%
—
—
—
7%
—
9%
—
7%
—
—
9%
—
—
—
—
—
—
3
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
7%
10%
9%
—
8%
9%
8%
—
—
—
7%
8%
—
—
—
—
6%
7%
—
—
—
—
6%
—
7%
—
—
—
—
—
5%
8%
—
6%
7%
—
5%
—
8%
—
6%
—
7%
—
—
—
—
—
1
PE[11]
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
5%
6%
1
—
—
1
9%
—
10%
11%
11%
11%
11%
12%
12%
12%
12%
12%
12%
12%
12%
12%
11%
10%
10%
9%
—
—
—
—
—
9%
—
—
—
—
—
—
9%
—
—
—
—
—
—
9%
13%
14%
14%
14%
—
12%
12%
12%
12%
—
9%
—
13%
—
11%
—
12%
—
—
—
1
—
—
1
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
9%
—
—
—
—
10%
10%
—
14%
—
12%
12%
—
12%
—
—
—
—
1
—
—
—
1
—
—
—
—
PF[8]
15%
15%
—
13%
13%
—
—
—
—
—
PF[12]
PC[6]
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
—
—
—
—
10%
10%
—
—
12%
12%
—
—
—
—
—
—
—
—
1
—
—
1
14%
—
12%
—
—
—
—
—
—
—
12%
—
11%
—
9%
—
12%
—
10%
—
11%
—
—
1
—
1
8%
8%
11%
—
10%
—
8%
8%
7%
7%
11%
—
9%
9%
9%
8%
10%
—
8%
9%
PA[13]
PA[12]
7%
10%
—
9%
9%
—
10%
—
9%
—
7%
8%
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
43
Electrical characteristics
Supply segment
1
Table 23. I/O weight (continued)
144/100 LQFP
64 LQFP
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
Weight 5 V
Weight 3.3 V
Weight 5 V
Pad
144
100
64
LQFP LQFP LQFP2
2
2
2
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
PB[5]
PB[6]
PB[7]
PD[9]
PD[10]
PD[11]
PB[11]
PD[12]
PB[12]
PD[13]
1%
1%
6%
6%
7%
7%
7%
8%
8%
8%
9%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
11%
11%
11%
10%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1%
1%
7%
7%
8%
8%
9%
9%
10%
10%
10%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
13%
13%
13%
12%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1%
1%
6%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1%
1%
7%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1%
1%
1%
1%
—
1%
2%
2%
2%
—
—
—
—
2
—
—
—
—
17%
—
21%
—
—
2
18%
—
21%
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 9
44
Freescale Semiconductor
Electrical characteristics
1
Table 23. I/O weight (continued)
144/100 LQFP
64 LQFP
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
Supply segment
Weight 5 V
Weight 3.3 V
Weight 5 V
Pad
144
100
64
LQFP LQFP LQFP2
2
2
2
—
2
PB[13]
PD[14]
PB[14]
PD[15]
PB[15]
PA[3]
10%
10%
10%
10%
9%
9%
9%
9%
5%
5%
5%
4%
4%
3%
3%
4%
4%
5%
5%
5%
6%
6%
7%
7%
7%
7%
7%
6%
6%
6%
6%
—
—
12%
12%
12%
11%
11%
11%
10%
10%
6%
6%
5%
5%
4%
4%
4%
5%
5%
6%
6%
6%
7%
8%
8%
8%
8%
8%
8%
8%
7%
7%
7%
—
—
18%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9%
21%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8%
—
—
18%
—
21%
—
—
2
—
—
—
—
18%
18%
—
21%
21%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
—
—
—
—
—
—
—
—
—
—
—
2
PG[13]
PG[12]
PH[0]
13%
12%
8%
7%
6%
6%
—
11%
11%
7%
6%
6%
5%
—
—
—
—
—
PH[1]
—
—
PH[2]
—
—
PH[3]
—
—
PG[1]
PG[0]
PF[15]
PF[14]
PE[13]
PA[7]
—
—
4%
—
4%
—
—
—
3
—
—
5%
—
5%
—
—
—
—
—
—
—
16%
16%
15%
15%
14%
—
19%
19%
18%
18%
17%
—
PA[8]
—
—
PA[9]
—
—
PA[10]
PA[11]
PE[12]
PG[14]
PG[15]
PE[14]
PE[15]
PG[10]
PG[11]
PC[3]
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
—
—
—
—
3
—
—
—
—
10%
—
9%
—
—
—
—
—
9%
—
8%
—
—
—
—
—
9%
—
8%
—
—
—
7%
6%
9%
8%
PC[2]
8%
7%
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
45
Electrical characteristics
Supply segment
1
Table 23. I/O weight (continued)
144/100 LQFP
64 LQFP
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
Weight 5 V
Weight 3.3 V
Weight 5 V
Pad
144
100
64
LQFP LQFP LQFP2
3
4
3
4
2
PA[5]
PA[6]
5%
5%
4%
5%
6%
7%
—
6%
6%
6%
—
6%
5%
5%
5%
6%
7
8%
—
7%
6%
6%
5%
7%
8
7%
—
PH[10]
PC[1]
PC[0]
PH[9]
PE[2]
PE[3]
PC[5]
PC[4]
PE[4]
PE[5]
PH[4]
PH[5]
PH[6]
PH[7]
PH[8]
PE[6]
PE[7]
PC[12]
PC[13]
PC[8]
PB[2]
6%
5%
5%
7%
—
6%
—
—
5%
—
3
9%
7%
8%
9%
7
8%
8
7
7
8
8
—
—
3
7%
10%
11%
11%
12%
12%
12%
13%
—
9%
9%
—
—
—
—
8%
9%
9%
—
—
—
—
8%
9%
10%
10%
11%
11%
11%
—
8%
8%
—
11%
12%
—
9%
10%
—
10%
10%
—
8%
8%
10%
10%
10%
11%
11%
11%
11%
11%
12%
12%
12%
12%
12%
12%
—
—
—
—
—
—
—
—
—
—
—
3
9%
—
—
—
—
—
—
—
—
—
4
9%
—
—
—
—
9%
—
—
—
—
9%
13%
13%
14%
14%
14%
14%
—
12%
12%
12%
12%
12%
13%
—
—
—
—
—
9%
—
—
—
—
10%
10%
10%
10%
10%
10%
10%
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10%
10%
—
12%
12%
—
15%
13%
15%
13%
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to125 °C, unless otherwise specified
Segments shown apply to MPC560xB devices only
SRC: “Slew Rate Control” bit in SIU_PCR
4.8
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
46
Freescale Semiconductor
Electrical characteristics
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 8. Start-up reset requirements
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 9. Noise filtering on reset signal
Table 24. Reset electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
47
Electrical characteristics
Table 24. Reset electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIL SR P Input low Level CMOS
(Schmitt Trigger)
—
—
0.4
—
0.35VDD
V
V
V
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
0.1VDD
—
—
—
—
VOL CC P Output low level
Push Pull, IOL = 2mA,
0.1VDD
VDD = 5.0 V 10%, PAD3V5V = 0
(recommended)
C
C
Push Pull, IOL = 1mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10%, PAD3V5V = 12
Push Pull, IOL = 1mA,
VDD = 3.3 V 10%, PAD3V5V = 1
(recommended)
ttr
CC D Output transition time
output pin3
CL = 25pF,
VDD = 5.0 V 10%, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
40
—
ns
CL = 50pF,
VDD = 5.0 V 10%, PAD3V5V = 0
CL = 100pF,
VDD = 5.0 V 10%, PAD3V5V = 0
—
CL = 25pF,
VDD = 3.3 V 10%, PAD3V5V = 1
—
CL = 50pF,
VDD = 3.3 V 10%, PAD3V5V = 1
—
CL = 100pF,
VDD = 3.3 V 10%, PAD3V5V = 1
—
WFRST SR P RESET input filtered
pulse
—
—
ns
ns
µA
WNFRST SR P RESET input not filtered
pulse
—
1000
|IWPU
|
CC P Weak pull-up current
VDD = 3.3 V 10%, PAD3V5V = 1
VDD = 5.0 V 10%, PAD3V5V = 0
VDD = 5.0 V 10%, PAD3V5V = 12
10
10
10
—
—
—
150
150
250
absolute value
D
P
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
This transient configuration does not occurs when device is used in the VDD = 3.3 V 10% range.
CL includes device and package capacitance (CPKG < 5 pF).
4.9 Power management electrical characteristics
4.9.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply V
from the high voltage
DD_LV
ballast supply V
. The regulator itself is supplied by the common I/O supply V . The following supplies are involved:
DD_BV
DD
MPC5604B/C Microcontroller Data Sheet, Rev. 9
48
Freescale Semiconductor
Electrical characteristics
•
•
•
HV—High voltage external power supply for voltage regulator module. This must be provided externally through V
power pin.
DD
BV—High voltage external power supply for internal ballast module. This must be provided externally through
V
power pin. Voltage values should be aligned with V
.
DD_BV
DD
LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
C
(LV_COR/LV_CFLA)
REG2
V
DD
V
V
DD_LV
SS_LV
V
DD_BV
DD_LVn
SS_LVn
V
REF
V
DD_BV
V
DD_LV
DEVICE
V
Voltage Regulator
I
V
SS_LV
V
V
V
V
V
DD
SS_LV
DD_LV
SS
DEVICE
C
C
DEC2
REG3
(LV_COR/LV_PLL)
(supply/IO decoupling)
Figure 10. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (C ) to be connected to the device in order to provide a stable
REGn
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three V
/V
supply pairs to ensure stable voltage (see
DD_LV SS_LV
Section 4.5, “Recommended operating conditions).
The internal voltage regulator requires controlled slew rate of V /V
as described on Figure 11.
DD DD_BV
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
49
Electrical characteristics
V
DD_HV
V
(MAX)
DD_HV
d
dt
VDD
V
(MIN)
DD_HV
POWER UP
FUNCTIONAL RANGE
POWER DOWN
Figure 11. V and V
maximum slope
DD_BV
DD
When STANDBY mode is used, further constraints apply to the V /V
in order to guarantee correct regulator
DD DD_BV
functionality during STANDBY exit. This is described on Figure 12.
STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY capacitance on
application board (capacitance and ESR typical values), but would actually depend on exact characteristics of application
external regulator.
V
V
V
DD_HV
DD_HV
DD_HV
(MAX)
d
dt
VDDSTDBY
VDD(STDBY)
VDD(STDBY)
V
(MIN)
DD_LV
DD_HV
d
dt
VDDSTDBY
V
V
(NOMINAL)
DD_LV
0V
Figure 12. VDD and VDD_BV supply constraints during STANDBY mode exit
MPC5604B/C Microcontroller Data Sheet, Rev. 9
50
Freescale Semiconductor
Electrical characteristics
Table 25. Voltage regulator electrical characteristics
Value
Unit
Symbol
C
Parameter
Conditions1
Min Typ Max
CREGn
RREG
SR — Internal voltage regulator external
capacitance
—
200
—
500
0.2
—
nF
SR — Stability capacitor equivalent serial Range:
—
—
resistance
10 kHz to 20 MHz
CDEC1
SR — Decoupling capacitance2 ballast VDD_BV/VSS_LV pair:
1003 4704
400
nF
V
DD_BV = 4.5 V to 5.5 V
V
DD_BV/VSS_LV pair:
—
VDD_BV = 3 V to 3.6 V
SR — Decoupling capacitance regulator VDD/VSS pair
CDEC2
10
—
100
—
—
nF
supply
SR — Maximum slope on VDD
250 mV/µs
d
VDD
dt
VDD(STDBY)
|
SR — Maximum instant variation on VDD
during standby exit
—
—
—
—
30
mV
SR — Maximum slope on VDD during
standby exit
15 mV/µs
d
dt
VDDSTDBY
VMREG
CC T Main regulator output voltage
Before exiting from
reset
—
1.32
—
V
P
After trimming
—
1.16 1.28
—
IMREG
SR — Main regulator current provided to
VDD_LV domain
—
—
150
mA
mA
IMREGINT
CC D Main regulator module current
consumption
IMREG = 200 mA
IMREG = 0 mA
After trimming
—
—
—
—
2
1
VLPREG
ILPREG
CC P Low power regulator output
voltage
1.16 1.28
—
V
SR — Low power regulator current
provided to VDD_LV domain
—
—
—
—
—
5
15
600
—
mA
µA
—
ILPREGINT
CC D Low power regulator module
current consumption
ILPREG = 15 mA;
TA = 55 °C
—
ILPREG = 0 mA;
TA = 55 °C
VULPREG
IULPREG
CC P Ultra low power regulator output
voltage
After trimming
1.16 1.28
—
V
SR — Ultra low power regulator current
provided to VDD_LV domain
—
—
—
—
—
—
2
5
mA
µA
IULPREGINT
CC D Ultra low power regulator module IULPREG = 5 mA;
100
—
current consumption
TA = 55 °C
IULPREG = 0 mA;
TA = 55 °C
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
51
Electrical characteristics
Symbol
Table 25. Voltage regulator electrical characteristics (continued)
Value
C
Parameter
Conditions1
Unit
Min Typ Max
IDD_BV
CC D In-rush average current on VDD_BV
during power-up5
—
—
—
3006 mA
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
2
3
4
This value is acceptable to guarantee operation from 4.5 V to 5.5 V
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
5
6
In-rush average current is seen only for short time (maximum 20 µs) during power-up and on standby exit. It is
dependant on the sum of the CREGn capacitances.
The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
The
| and dVDD(STDBY)/dt system requirement can be used to define the component used for the V supply
VDD(STDBY)
DD
generation. The following two examples describe how to calculate capacitance size:
Example 1. No regulator (worst case)
The
capacitor when the I
| parameter can be seen as the V voltage drop through the ESR resistance of the regulator stability
DD
VDD(STDBY)
current required to load V
domain during the standby exit. It is thus possible to define the
DD_BV
DD_LV
maximum equivalent resistance ESR
(MAX) of the total capacitance on the V supply:
STDBY
DD
1
ESR
(MAX) =
|/I
= (30 mV)/(300 mA) = 0.1
STDBY
VDD(STDBY) DD_BV
The dVDD(STDBY)/dt parameter can be seen as the V voltage drop at the capacitance pin (excluding ESR drop) while
DD
providing the I
supply required to load V
domain during the standby exit. It is thus possible to define the minimum
DD_BV
DD_LV
equivalent capacitance C
(MIN) of the total capacitance on the V supply:
STDBY
DD
C
(MIN) = I
/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20 µF
DD_BV
STDBY
This configuration is a worst case, with the assumption no regulator is available.
Example 2. Simplified regulator
The regulator should be able to provide significant amount of the current during the standby exit process. For example, in case
of an ideal voltage regulator providing 200 mA current, it is possible to recalculate the equivalent ESR
(MAX) and
STDBY
C
(MIN) as follows:
STDBY
ESR
(MAX) =
|/(I
200 mA) = (30 mV)/(100 mA) = 0.3
STDBY
VDD(STDBY) DD_BV
C
(MIN) = (I
200 mA)/dVDD(STDBY)/dt = (300 mA 200 mA)/(15 mV/µs) = 6.7 µF
DD_BV
STDBY
In case optimization is required, C
(MIN) and ESR
(MAX) should be calculated based on the regulator
STDBY
STDBY
characteristics as well as the board V plane characteristics.
DD
4.9.2
Low voltage detector electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage
detectors (LVDs) to monitor the V and the V voltage while device is supplied:
DD
DD_LV
1. Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
52
Freescale Semiconductor
Electrical characteristics
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM
Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply (refer to RGM Destructive Event
DD
Status (RGM_DES) Register flag F_LVD27 in device reference manual)
LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status
DD
(RGM_FES) Register flag F_LVD45 in device reference manual)
LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD1 in device reference manual
LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD0 in device reference manual)
NOTE
When enabled, power domain No. 2 is monitored through LVDLVBKP.
V
DD
V
V
LVDHVxH
LVDHVxL
RESET
Figure 13. Low voltage detector vs reset
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
53
Electrical characteristics
Table 26. Low voltage detector electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
VPORUP
VPORH
SR P Supply for functional POR module
CC P Power-on reset threshold
—
1.0
1.5
—
—
5.5
2.6
V
TA = 25 °C,
after trimming
T
—
—
1.5
—
—
—
—
—
—
—
—
2.6
2.95
2.9
VLVDHV3H CC T LVDHV3 low voltage detector high threshold
VLVDHV3L CC P LVDHV3 low voltage detector low threshold
VLVDHV5H CC T LVDHV5 low voltage detector high threshold
VLVDHV5L CC P LVDHV5 low voltage detector low threshold
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
2.6
—
4.5
3.8
1.08
1.08
4.4
1.16
1.16
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
4.10 Power consumption
Table 27 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 27. Power consumption on VDD_BV and VDD_HV
Value
Symbol
C
Parameter
Conditions1
Unit
115 1403 mA
Min Typ Max
2
IDDMAX
CC D RUN mode maximum
average current
—
—
4
IDDRUN
CC T RUNmodetypicalaverage fCPU = 8 MHz
current5
—
—
—
—
—
—
—
—
—
—
—
—
7
—
—
mA
T
fCPU = 16 MHz
18
29
40
51
8
T
fCPU = 32 MHz
—
P
fCPU = 48 MHz
100
125
15
P
fCPU = 64 MHz
IDDHALT
CC C HALT mode current6
Slow internal RC oscillator TA = 25 °C
mA
(128 kHz) running
P
TA = 125 °C
14
25
IDDSTOP CC P STOP mode current7
Slow internal RC oscillator TA = 25 °C
180 7008 µA
(128 kHz) running
D
D
D
P
TA = 55 °C
500
1
—
68
TA = 85 °C
TA = 105 °C
TA = 125 °C
mA
2
98
4.5
128
MPC5604B/C Microcontroller Data Sheet, Rev. 9
54
Freescale Semiconductor
Electrical characteristics
Table 27. Power consumption on VDD_BV and VDD_HV (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
IDDSTDBY2 CC P STANDBY2 mode current9 Slow internal RC oscillator TA = 25 °C
(128 kHz) running
—
—
—
—
—
—
—
—
—
—
30
75
100
—
µA
D
TA = 55 °C
TA = 85 °C
D
180
700
D
TA = 105 °C
315 1000
560 1700
P
TA = 125 °C
IDDSTDBY1 CC T STANDBY1 mode
Slow internal RC oscillator TA = 25 °C
20
45
60
—
µA
current10
D
(128 kHz) running
TA = 55 °C
D
D
D
TA = 85 °C
TA = 105 °C
TA = 125 °C
100
165
280
350
500
900
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
--------Running consumption does not include I/Os toggling which is highly dependent on the application. The given
value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify
operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used
peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions,
use low power mode when possible.
3
4
5
Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 25.
RUN current measured with typical application with accesses on both flash and RAM.
Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and
LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and
running at max frequency, periodic SW/WDG timer reset enabled.
6
Data Flash Power Down. Code Flash in Low Power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16
channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked
but no communication). RTC/API ON. PIT ON. STM ON. ADC ON but not conversion except 2 analog watchdog.
7
8
Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPvreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched off.
10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
4.11 Flash memory electrical characteristics
4.11.1 Program/Erase characteristics
Table 28 shows the program and erase characteristics.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
55
Electrical characteristics
Table 28. Program and erase specifications
Parameter
Value
Symbol
C
Unit
Initial
max2
Min
Typ1
Max3
Tdwprogram CC C Double word (64 bits) program time4
—
—
—
—
—
22
300
400
800
—
50
500
600
1300
30
500
5000
5000
7500
30
µs
ms
ms
ms
µs
T16Kpperase
T32Kpperase
T128Kpperase
Tesus
16 KB block preprogram and erase time
32 KB block preprogram and erase time
128 KB block preprogram and erase time
CC D Erase suspend latency
1
2
3
Typical program and erase times assume nominal supply values and operation at 25 °C.
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
Table 29. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
P/E
CC C Number of program/erase cycles 16 KB blocks
100,000
—
—
—
—
—
cycles
per block over the operating
temperature range (TJ)
32 KB blocks
10,000 100,000
1,000 100,000
128 KB blocks
Retention CC C Minimum data retention at 85 °C Blocks with
average ambient temperature1
0–1,000 P/E cycles
20
10
5
—
—
—
years
Blocks with
1,001–10,000 P/E cycles
—
—
Blocks with
10,001–100,000 P/E cycles
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 30. Flash read access timing
Symbol
C
Parameter
Conditions1
Max Unit
fREAD CC P Maximum frequency for Flash reading
2 wait states
1 wait state
0 wait states
64
40
20
MHz
C
C
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
MPC5604B/C Microcontroller Data Sheet, Rev. 9
56
Freescale Semiconductor
Electrical characteristics
4.11.2 Flash power supply DC characteristics
Table 31 shows the power supply DC characteristics on external supply.
Table 31. Flash memory power supply DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
2
IFREAD CC D Sum of the current consumption on
VDD_HV and VDD_BV on read access
Code flash memory module read
fCPU = 64 MHz3
—
—
—
15
15
15
33 mA
Data flash memory module read
33
f
CPU = 64 MHz3
2
IFMOD CC D Sum of the current consumption on
Program/Erase ongoing while
reading code flash memory
registers fCPU = 64 MHz3
33 mA
VDD_HV and VDD_BV on matrix
modification (program/erase)
Program/Erase ongoing while
reading data flash memory
registers fCPU = 64 MHz3
—
15
33
IFLPW CC D Sum of the current consumption on
VDD_HV and VDD_BV
During code flash memory
low-power mode
—
—
—
—
—
—
—
—
900 µA
900
During data flash memory
low-power mode
IFPWD CC D Sum of the current consumption on
VDD_HV and VDD_BV
During code flash memory
power-down mode
150 µA
150
During data flash memory
power-down mode
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
This value is only relative to the actual duration of the read cycle
fCPU 64 MHz can be achieved only at up to 105 °C
2
3
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
57
Electrical characteristics
4.11.3 Start-up/Switch-off timings
Table 32. Start-up time/Switch-off time
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
TFLARSTEXIT CC T Delay for Flash module to exit reset mode
T
Code Flash
Data Flash
Code Flash
Data Flash
Code Flash
Data Flash
Code Flash
Data Flash
Code Flash
Data Flash
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
125
125
0.5
0.5
30
µs
TFLALPEXIT
CC T Delay for Flash module to exit low-power
mode
T
TFLAPDEXIT
CC T Delay for Flash module to exit power-down
mode
T
30
TFLALPENTRY CC T Delay for Flash module to enter low-power
0.5
0.5
1.5
1.5
mode
T
TFLAPDENTRY CC T
Delay for Flash module to enter power-down
mode
T
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
4.12 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for his application.
•
Software recommendations:The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
•
Prequalification trials:Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
4.12.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1
standard, which specifies the general conditions for EMI measurements.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
58
Freescale Semiconductor
Electrical characteristics
1,2
Table 33. EMI radiated emission measurement
Value
Unit
Symbol
C
Parameter
Conditions
Min Typ Max
—
SR — Scan range
—
—
—
0.150
—
—
64
1000 MHz
fCPU SR — Operating frequency
VDD_LV SR — LV operating voltages
SEMI CC T Peak level
—
—
MHz
V
—
1.28
—
VDD = 5 V, TA = 25 °C,
LQFP144 package
No PLL frequency
modulation
—
18 dBµV
Test conforming to IEC 61967-2,
fOSC = 8 MHz/fCPU = 64 MHz
2% PLL frequency
modulation
—
—
14 dBµV
1
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
2
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
4.12.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
4.12.3.1 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
1 2
Table 34. ESD absolute maximum ratings
Symbol
C
Ratings
Conditions
TA = 25 °C
Class Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
H1C
2000
V
conforming to AEC-Q100-002
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
4.12.3.2 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
59
Electrical characteristics
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 35. Latch-up results
Parameter Conditions
Symbol
LU CC
C
Class
T Static latch-up class
TA = 125 °C
II level A
conforming to JESD 78
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 14 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
Table 36 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
EXTAL
C1
EXTAL
XTAL
C2
DEVICE
V
DD
I
R
EXTAL
XTAL
DEVICE
XTAL
DEVICE
Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
Figure 14. Crystal oscillator and resonator connection scheme
MPC5604B/C Microcontroller Data Sheet, Rev. 9
60
Freescale Semiconductor
Electrical characteristics
Shunt
Table 36. Crystal description
Crystal
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
capacitance
between
xtalout
Nominal
frequency
(MHz)
equivalent
series
NDK crystal
reference
resistance
ESR
(pF)1
and xtalin
C02 (pF)
4
NX8045GB
NX5032GA
300
300
150
120
120
2.68
2.46
2.93
3.11
3.90
591.0
160.7
86.6
21
17
15
15
10
2.93
3.01
2.91
2.93
3.00
8
10
12
16
56.5
25.3
1
2
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
S_MTRANS bit (ME_GS register)
‘1’
‘0’
V
XTAL
1/f
FXOSC
V
FXOSC
90%
10%
V
FXOSCOP
t
valid internal clock
FXOSCSU
Figure 15. Fast external crystal oscillator (4 to 16 MHz) timing diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
61
Electrical characteristics
Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFXOSC SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC CC C Fast external crystal
VDD = 3.3 V 10%,
2.2
2.0
2.7
2.5
—
—
—
—
8.2
7.4
9.7
9.2
mA/V
oscillator transconductance PAD3V5V = 1
OSCILLATOR_MARGIN = 0
CC P
CC C
CC C
VDD = 5.0 V 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
V
DD = 3.3 V 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
V
DD = 5.0 V 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
VFXOSC CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
1.3
—
—
—
—
V
f
OSC = 16 MHz,
OSCILLATOR_MARGIN = 1
VFXOSCOP CC C Oscillation operating point
—
—
—
—
0.95
2
—
3
V
,2
IFXOSC
CC T Fast external crystal
oscillator consumption
mA
tFXOSCSU CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
—
—
—
—
6
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.8
VIH
VIL
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
Oscillator bypass mode
0.65VDD
0.4
VDD+0.4
0.35VDD
V
V
SR P Input low level CMOS
(Schmitt Trigger)
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
4.14 Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
62
Freescale Semiconductor
Electrical characteristics
OSC32K_EXTAL
OSC32K_EXTAL
C1
C2
OSC32K_XTAL
OSC32K_XTAL
DEVICE
DEVICE
Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 16. Crystal oscillator and resonator connection scheme
C0
Crystal
Rm
Lm
Cm
C1
C2
C1
C2
Figure 17. Equivalent circuit of a quartz crystal
1
Table 38. Crystal motional characteristics
Value
Typ
Symbol
Parameter
Conditions
Unit
Min
Max
Lm
Motional inductance
Motional capacitance
—
—
—
—
—
18
11.796
—
—
28
KH
fF
Cm
2
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
—
pF
AC coupled @ C0 = 2.85 pF4
AC coupled @ C0 = 4.9 pF4
AC coupled @ C0 = 7.0 pF4
AC coupled @ C0 = 9.0 pF4
—
—
—
—
—
—
—
—
65
50
35
30
k
3
Rm
Motional resistance
1
Crystal used: Epson Toyocom MC306
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
63
Electrical characteristics
2
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3
4
Maximum ESR (Rm) of the crystal is 50 k
C0 includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
OSCON bit (OSC_CTL register)
1
0
V
OSC32K_XTAL
1/f
SXOSC
V
SXOSC
90%
10%
T
valid internal clock
SXOSCSU
Figure 18. Slow external crystal oscillator (32 kHz) timing diagram
Table 39. Slow external crystal oscillator (32 kHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fSXOSC SR — Slow external crystal oscillator frequency
VSXOSC CC T Oscillation amplitude
—
—
—
—
—
32
—
—
—
—
32.768
2.1
40
—
—
8
kHz
V
ISXOSCBIAS CC T Oscillation bias current
2.5
µA
µA
s
ISXOSC CC T Slow external crystal oscillator consumption
TSXOSCSU CC T Slow external crystal oscillator start-up time
—
—
22
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified. Values are specified for no
neighbor GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins
should not toggle.
Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
4.15 FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
64
Freescale Semiconductor
Electrical characteristics
Table 40. FMPLL electrical characteristics
Value
Unit
Symbol
C
Parameter
Conditions1
Min
Typ
Max
fPLLIN SR — FMPLL reference clock2
—
—
4
—
—
64
60
MHz
%
PLLIN SR — FMPLL reference clock duty
40
cycle2
fPLLOUT CC D FMPLL output clock frequency
—
—
16
—
—
64
MHz
3
fVCO
CC P VCO frequency without
frequency modulation
256
512 MHz
C VCO frequency with frequency
modulation
—
245
—
533
fCPU SR — System clock frequency
fFREE CC P Free-running frequency
tLOCK CC P FMPLL lock time
—
—
20
—
–4
—
—
—
40
—
—
64
MHz
—
150 MHz
Stable oscillator (fPLLIN = 16 MHz)
fsys maximum
100
4
µs
%
tSTJIT CC — FMPLL short term jitter4
tLTJIT CC — FMPLL long term jitter
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
10
ns
IPLL
CC C FMPLL consumption
TA = 25 °C
—
—
4
mA
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN
Frequency modulation is considered 4%
.
3
4
Short term jitter is measured on the clock rising edge at cycle n and n+4.
4.16 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics
Value
Symbol
fFIRC
2,
C
Parameter
Conditions1
Unit
Min
Typ
Max
CC P Fast internal RC oscillator high
TA = 25 °C, trimmed
—
—
12
—
16
—
20
MHz
frequency
SR —
IFIRCRUN CC T Fast internal RC oscillator high
frequency current in running mode
TA = 25 °C, trimmed
—
—
200
µA
µA
IFIRCPWD CC D Fast internal RC oscillator high
frequency current in power down
mode
TA = 125 °C
—
10
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
65
Electrical characteristics
Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
IFIRCSTOP CC T Fast internal RC oscillator high
frequency and system clock current
in stop mode
TA = 25 °C sysclk = off
—
—
—
—
—
—
500
600
700
900
1250
1.1
—
—
—
—
—
2.0
µA
sysclk = 2 MHz
sysclk = 4 MHz
sysclk = 8 MHz
sysclk = 16 MHz
tFIRCSU CC C Fast internal RC oscillator start-up VDD = 5.0 V 10%
time
µs
%
%
%
FIRCPRE CC T Fast internal RC oscillator precision TA = 25 °C
1
—
5
—
1.6
—
+1
after software trimming of fFIRC
FIRCTRIM CC T Fast internal RC oscillator trimming TA = 25 °C
step
FIRCVAR CC P Fast internal RC oscillator variation
in overtemperature and supply with
respect to fFIRC at TA = 25 °C in
—
+5
high-frequency configuration
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
4.17 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fSIRC
CC P Slow internal RC oscillator low
TA = 25 °C, trimmed
—
—
100
—
128
—
—
150
5
kHz
frequency
SR —
2,
ISIRC
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
µA
µs
%
tSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V 10%
time
—
2
8
12
+2
SIRCPRE CC C Slow internal RC oscillator precision TA = 25 °C
—
2.7
—
after software trimming of fSIRC
SIRCTRIM CC C Slow internal RC oscillator trimming
—
—
—
step
SIRCVAR CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
10
+10
%
respect to fSIRC at TA = 55 °C in high
frequency configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 9
66
Freescale Semiconductor
Electrical characteristics
1
2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
67
Electrical characteristics
4.18 ADC electrical characteristics
4.18.1 Introduction
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.
Offset error (E )
Gain error (E )
G
O
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
4
3
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset error (E )
O
Figure 19. ADC characteristic and error definitions
4.18.2 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
MPC5604B/C Microcontroller Data Sheet, Rev. 9
68
Freescale Semiconductor
Electrical characteristics
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 k is obtained (R
S
EQ
= 1 / (f *C ), where f represents the conversion rate at the considered channel). To minimize the error induced by the voltage
c
S
c
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 4:
Eqn. 4
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V
-- LSB
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R : Source impedance
S
R : Filter resistance
F
C : Filter capacitance
F
R : Current limiter resistance
L
R
R
: Channel selection switch impedance
: Sampling switch impedance
SW1
AD
C : Pin capacitance (two contributions, C and C )
P2
P
P1
C : Sampling capacitance
S
Figure 20. Input equivalent circuit (precise channels)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
69
Electrical characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R : Source impedance
S
R : Filter resistance
F
C : Filter capacitance
F
R : Current limiter resistance
L
R
R
: Channel selection switch impedance (two contributions, R
: Sampling switch impedance
and R
)
SW1
SW1
SW2
AD
C : Pin capacitance (two contributions, C , C and C )
P3
P
P1
P2
C : Sampling capacitance
S
Figure 21. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit in Figure 20): A charge sharing phenomenon is installed
A
when the sampling phase is started (A/D switch close).
Voltage transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << ts
V
A1
2 = RL (CS + CP1 + CP2)
t
t
s
Figure 22. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
MPC5604B/C Microcontroller Data Sheet, Rev. 9
70
Freescale Semiconductor
Electrical characteristics
1. A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
P1
P2
S
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
Eqn. 5
C C
P
S
--------------------
= R
+ R
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time t
is always much longer than the internal time constant:
s
Eqn. 6
R
+ R
C « t
1
SW
AD
S
s
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
Eqn. 7
V
C + C + C = V C + C
A1
S
P1
P2
A
P1
P2
2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
Eqn. 8
R C + C + C
P1 P2
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time t , a constraints on R sizing is obtained:
s
L
Eqn. 9
10 = 10 R C + C + C t
P1 P2 s
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 10
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (t ). The filter is typically designed to act as anti-aliasing.
s
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
71
Electrical characteristics
Analog source bandwidth (VA)
tc < 2 RFCF (conversion rate vs. filter pole)
Noise
fF = f0 (anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
Sampled signal spectrum (fC = conversion rate)
fF
f0
fC
f
f
Figure 23. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (t ). Again the conversion period t is longer than the sampling time t ,
c
c
s
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time t , so the charge level on C cannot be modified by the analog signal source during the time in which the sampling
s
S
switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A2
P1
F
V
C
+ C + C + C
A
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 12
C
2048 C
F
S
MPC5604B/C Microcontroller Data Sheet, Rev. 9
72
Freescale Semiconductor
Electrical characteristics
4.18.3 ADC electrical characteristics
Table 43. ADC input leakage current
Value
Unit
Symbol C
Parameter
Conditions
Min
Typ
Max
ILKG CC D Input leakage current TA = 40 °C No current injection on adjacent pin
—
—
—
—
—
1
1
70
70
nA
D
D
D
P
TA = 25 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
3
100
200
400
8
45
Table 44. ADC conversion characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
0.1
VSS_ADC SR — Voltage on
VSS_HV_ADC (ADC
—
0.1
—
V
reference) pin with
respect to ground
2
(VSS
)
VDD_ADC SR — Voltage on
VDD_HV_ADC pin
—
VDD0.1
—
VDD+0.1
V
V
(ADC reference) with
respect to ground
(VSS
)
VAINx SR — Analog input voltage3
—
—
VSS_ADC0.1
—
—
—
VDD_ADC+0.1
fADC SR — ADC analog frequency
6
32 + 4% MHz
ADC_SYS SR — ADC digital clock duty ADCLKSEL = 14
45
55
50
4
%
µA
mA
cycle (ipg_clk)
IADCPWD SR — ADC0 consumption in
power down mode
—
—
—
—
—
—
IADCRUN SR — ADC0 consumption in
running mode
tADC_PU SR — ADC power up delay
—
—
0.5
—
—
—
—
—
—
1.5
µs
µs
ts
CC
T
Sampling time5
fADC = 32 MHz, INPSAMP = 17
fADC = 6 MHz, INPSAMP = 255
fADC = 32 MHz, INPCMP = 2
—
42
tc
CC
P
Conversion time6
0.625
—
µs
CS
CC D ADC input sampling
capacitance
3
3
1
pF
CP1
CP2
CC D ADC input pin
capacitance 1
—
—
—
—
—
—
pF
pF
CC D ADC input pin
capacitance 2
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
73
Electrical characteristics
Table 44. ADC conversion characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
CP3
CC D ADC input pin
capacitance 3
—
—
—
—
—
—
1
pF
k
k
k
mA
RSW1 CC D Internal resistance of
analog source
—
—
—
5
5
—
—
—
—
—
3
2
2
5
5
RSW2 CC D Internal resistance of
analog source
RAD CC D Internal resistance of
analog source
IINJ
SR — Input current Injection Current
VDD =
injection on one 3.3 V 10%
ADC input,
VDD
=
different from
the converted
one
5.0 V 10%
| INL | CC
| DNL | CC
T
T
Absolute value for
integral non-linearity
No overload
—
—
0.5
0.5
1.5
1.0
LSB
LSB
Absolute differential
non-linearity
No overload
| EO
| EG
|
|
CC
CC
T
T
P
T
Absolute offset error
—
—
—
2
3
0.5
0.6
0.6
—
—
2
LSB
LSB
LSB
Absolute gain error
—
TUEp CC
Total unadjusted error7 Without current injection
for precise channels,
With current injection
input only pins
3
TUEx CC
T
T
Total unadjusted error7 Without current injection
3
4
1
3
4
LSB
for extended channel
With current injection
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4
5
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of
the sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock ts depend on programming.
6
7
This parameter does not include the sampling time ts, but only the time for determining the digital result and the time
to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
74
Freescale Semiconductor
Electrical characteristics
4.19 On-chip peripherals
4.19.1 Current consumption
1
Table 45. On-chip peripherals current consumption
Symbol
C
Parameter
Conditions
Total (static + dynamic)
Typical value2 Unit
IDD_BV(CAN)
CC T CAN (FlexCAN) supply
current on VDD_BV
Bitrate:
500 Kbyte/s consumption:
8 * fperiph + 85 µA
• FlexCAN in loop-back
mode
• XTAL @ 8 MHz used as
CAN engine clock source
• Message sending period
is 580 µs
Bitrate:
125 Kbyte/s
8 * fperiph + 27
IDD_BV(eMIOS) CC T eMIOS supply current on Static consumption:
29 * fperiph
µA
VDD_BV
• eMIOS channel OFF
• Global prescaler enabled
Dynamic consumption:
3
• It does not change varying the
frequency (0.003 mA)
IDD_BV(SCI)
CC T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynamic) consumption:
• LIN mode
5 * fperiph + 31 µA
• Baudrate: 20 Kbyte/s
IDD_BV(SPI)
CC T SPI (DSPI) supply current Ballast static consumption (only clocked)
1
µA
on VDD_BV
Ballast dynamic consumption
16 * fperiph
(continuous communication):
• Baudrate: 2 Mbit/s
• Transmission every 8 µs
• Frame: 16 bits
IDD_BV(ADC)
CC T ADC supply current on
VDD_BV
VDD = 5.5 V Ballast static consumption
(no conversion)
41 * fperiph
5 * fperiph
µA
µA
Ballast dynamic
consumption
(continuous conversion)3
IDD_HV_ADC(ADC) CC T ADC supply current on
VDD_HV_ADC
VDD = 5.5 V Analog static consumption
(no conversion)
2 * fperiph
Analog dynamic
consumption
75 * fperiph + 32
(continuous conversion)
IDD_HV(FLASH) CC T Code Flash + Data Flash VDD = 5.5 V
supply current on VDD_HV
—
8.21
mA
µA
IDD_HV(PLL)
CC T PLL supply current on
VDD_HV
VDD = 5.5 V
—
30 * fperiph
1
2
3
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
fperiph is an absolute value.
During the conversion, the total current consumption is given from the sum of the static and dynamic consumption,
i.e., (41 + 5) * fperiph
.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
75
4.19.2 DSPI characteristics
1
Table 46. DSPI characteristics
DSPI0/DSPI1
DSPI2
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
Min
Typ
Max
1
tSCK
SR D SCK cycle time
Master mode
(MTFE = 0)
125
—
—
333
—
—
ns
D
D
D
Slave mode
(MTFE = 0)
125
83
—
—
—
—
—
—
333
125
125
—
—
—
—
—
—
Master mode
(MTFE = 1)
Slave mode
(MTFE = 1)
83
—
—
fDSPI
SR D DSPI digital controller frequency
—
—
—
—
fCPU
1302
—
—
—
—
fCPU
153
MHz
ns
tCSC CC D Internal delay between pad Master mode
associated to SCK and pad
associated to CSn in
master mode for CSn10
tASC CC D Internal delay between pad Master mode
associated to SCK and pad
associated to CSn in
master mode for CSn11
tCSCext SR D CS to SCK delay
—
—
—
—
1303
—
—
1303
ns
4
2
3
4
Slave mode
Slave mode
Master mode
Slave mode
Slave mode
32
—
32
—
—
—
ns
ns
ns
5
tASCext SR D After SCK delay
1/fDSPI + 5
—
tSCK/2
—
—
1/fDSPI + 5
—
tSDC
CC D SCK duty cycle
SR D
—
—
—
tSCK/2
—
tSCK/2
—
—
tSCK/2
—
1/fDSPI + 70
—
—
1/fDSPI + 130
—
5
6
7
8
9
tA
SR D Slave access time
—
7
—
—
ns
ns
ns
ns
ns
tDI
SR D Slave SOUT disable time Slave mode
PCSx to PCSS time
—
7
—
tPCSC
tPASC
tSUI
0
0
PCSS to PCSx time
0
0
SR D Data setup time for inputs Master mode
Slave mode
43
5
—
—
—
—
145
5
—
—
—
—
1
Table 46. DSPI characteristics (continued)
DSPI0/DSPI1
DSPI2
Typ
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
Min
Max
10
tHI
SR D Data hold time for inputs
Master mode
Slave mode
0
26
—
—
0
—
—
—
—
—
—
—
—
32
52
—
—
0
—
—
—
—
—
—
—
—
ns
26
—
—
0
7
11
12
tSUO
CC D Data valid after SCK edge Master mode
Slave mode
50
160
—
ns
ns
7
tHO
CC D Data hold time for outputs Master mode
Slave mode
8
13
—
1
2
Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
3
4
5
Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than tASC to ensure positive tASCext
.
.
6
7
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.
SCK and SOUT configured as MEDIUM pad
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 46
Figure 24. DSPI classic SPI timing – master, CPHA = 0
MPC5604B/C Microcontroller Data Sheet, Rev. 9
78
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: Numbers shown reference Table 46.
Figure 25. DSPI classic SPI timing – master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Numbers shown reference Table 46
Figure 26. DSPI classic SPI timing – slave, CPHA = 0
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
79
Electrical characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Numbers shown reference Table 46
Figure 27. DSPI classic SPI timing – slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Note: Numbers shown reference Table 46.
Figure 28. DSPI modified transfer format timing – master, CPHA = 0
MPC5604B/C Microcontroller Data Sheet, Rev. 9
80
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 46
Figure 29. DSPI modified transfer format timing – master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Numbers shown reference Table 46
Figure 30. DSPI modified transfer format timing – slave, CPHA = 0
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
81
Electrical characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Numbers shown reference Table 46
Figure 31. DSPI modified transfer format timing – slave, CPHA = 1
8
7
PCSS
PCSx
Note: Numbers shown reference Table 46.
Figure 32. DSPI PCS strobe (PCSS) timing
4.19.3 Nexus characteristics
Table 47. Nexus characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
tTCYC
tMCYC
tMDOV
CC D TCK cycle time
CC D MCKO cycle time
64
32
—
—
—
—
—
—
8
ns
ns
ns
CC D MCKO low to MDO data valid
MPC5604B/C Microcontroller Data Sheet, Rev. 9
82
Freescale Semiconductor
Electrical characteristics
Table 47. Nexus characteristics (continued)
Value
Typ
No.
Symbol
C
Parameter
Min
Unit
Max
4
5
tMSEOV CC D MCKO low to MSEO_b data valid
—
—
15
15
5
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
tEVTOV
tNTDIS
CC D MCKO low to EVTO data valid
CC D TDI data setup time
8
10
—
—
—
—
—
—
tNTMSS CC D TMS data setup time
tNTDIH CC D TDI data hold time
tNTMSH CC D TMS data hold time
11
5
12
13
tTDOV
tTDOI
CC D TCK low to TDO data valid
CC D TCK low to TDO data invalid
35
6
TCK
10
11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 47.
Figure 33. Nexus TDI, TMS, TDO timing
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
83
Electrical characteristics
4.19.4 JTAG characteristics
Table 48. JTAG characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
4
5
6
7
tJCYC
tTDIS
CC D TCK cycle time
CC D TDI setup time
CC D TDI hold time
64
15
5
—
—
—
—
—
—
—
—
—
—
—
—
33
—
ns
ns
ns
ns
ns
ns
ns
tTDIH
tTMSS
tTMSH
tTDOV
tTDOI
CC D TMS setup time
CC D TMS hold time
CC D TCK low to TDO valid
CC D TCK low to TDO invalid
15
5
—
6
TCK
2/4
3/5
INPUT DATA VALID
DATA INPUTS
6
DATA OUTPUTS
DATA OUTPUTS
OUTPUT DATA VALID
7
Note: Numbers shown reference Table 48
Figure 34. Timing diagram – JTAG boundary scan
MPC5604B/C Microcontroller Data Sheet, Rev. 9
84
Freescale Semiconductor
Package characteristics
5
Package characteristics
Package mechanical data
64 LQFP
5.1
5.1.1
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
85
Package characteristics
Figure 35. 64 LQFP package mechanical drawing (1 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
86
Freescale Semiconductor
Package characteristics
Figure 36. 64 LQFP package mechanical drawing (2 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
87
Package characteristics
Figure 37. 64 LQFP package mechanical drawing (3 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
88
Freescale Semiconductor
Package characteristics
5.1.2
100 LQFP
Figure 38. 100 LQFP package mechanical drawing (1 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
89
Package characteristics
Figure 39. 100 LQFP package mechanical drawing (2 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
90
Freescale Semiconductor
Package characteristics
Figure 40. 100 LQFP package mechanical drawing (3 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
91
Package characteristics
5.1.3
144 LQFP
Figure 41. 144 LQFP package mechanical drawing (1 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
92
Freescale Semiconductor
Package characteristics
Figure 42. 144 LQFP package mechanical drawing (2 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
93
Package characteristics
5.1.4
208 MAPBGA
Figure 43. 208 MAPBGA package mechanical drawing (1 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
94
Freescale Semiconductor
Package characteristics
Figure 44. 208 MAPBGA package mechanical drawing (2 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
95
Ordering information
6
Ordering information
Figure 45. Commercial product code structure
Example code:
M
PC
56
0
4
B
F1
M
LL
4
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Fab and Mask Indicator
Temperature spec.
Package Code
Frequency
R = Tape & Reel (blank if Tray)
Qualification Status
Flash Size (z0 core)
2 = 256 KB
3 = 384 KB
Temperature spec.
C = 40 to 85 °C
V = 40 to 105 °C
M = 40 to 125 °C
M = MC status
S = Auto qualified
P = PC status
4 = 512 KB
Automotive Platform
56 = PPC in 90nm
Product
B = Body
Package Code
LH = 64 LQFP
C = Gateway
LL = 100 LQFP
LQ = 144 LQFP
MG = 208 MAPBGA
Core Version
0 = e200z0
1
Fab and Mask Indicator
F = ATMC
1 = Maskset Revision
Frequency
4 = Up to 48 MHz
6 = Up to 64 MHz
1
208 MAPBGA available only as development package for Nexus2+
7
Document revision history
Table 49 summarizes revisions to this document.
Table 49. Revision history
Revision
Date
Description of Changes
1
04-Apr-2008 Initial release.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
96
Freescale Semiconductor
Document revision history
Table 49. Revision history (continued)
Description of Changes
Revision
Date
2
06-Mar-2009 Made minor editing and formatting changes to improve readability
Harmonized oscillator naming throughout document
Features:
—Replaced 32 KB with 48 KB as max SRAM size
—Updated description of INTC
—Changed max number of GPIO pins from 121 to 123
Updated Section 1.2, Descrioption
Updated Table 2
Added Section 2, “Block diagram
Section 3, “Package pinouts and signal descriptions: Removed signal descriptions (these
are found in the device reference manual)
Updated Figure 5:
—Replaced VPP with VSS_HV on pin 18
—Added MA[1] as AF3 for PC[10] (pin 28)
—Added MA[0] as AF2 for PC[3] (pin 116)
—Changed description for pin 120 to PH[10] / GPIO[122] / TMS
—Changed description for pin 127 to PH[9] / GPIO[121] / TCK
—Replaced NMI[0] with NMI on pin 11
Updated Figure 4:
—Replaced VPP with VSS_HV on pin 14
—Added MA[1] as AF3 for PC[10] (pin 22)
—Added MA[0] as AF2 for PC[3] (pin 77)
—Changed description for pin 81 to PH[10] / GPIO[122] / TMS
—Changed description for pin 88 to PH[9] / GPIO[121] / TCK
—Removed E1UC[19] from pin 76
—Replaced [11] with WKUP[11] for PB[3] (pin 1)
—Replaced NMI[0] with NMI on pin 7
Updated Figure 6:
—Changed description for ball B8 from TCK to PH[9]
—Changed description for ball B9 from TMS to PH[10]
—Updated descriptions for balls R9 and T9
Added Section 4.2, “Parameter classification and tagged parameters in tables where
appropriate
Added Section 4.3, “NVUSRO register
Updated Table 5
Section 4.5, “Recommended operating conditions: Added note on RAM data retention to
end of section
Updated Table 6 and Table 7
Added Section 4.6.1, “Package thermal characteristics
Updated Section 4.6.2, “Power considerations
Updated Figure 7
Updated Table 9, Table 10, Table 11, Table 12 and Table 13
Added Section 4.7.4, “Output pin transition times
Updated Table 16
Updated Figure 8
Updated Table 18
Section 4.9.1, “Voltage regulator electrical characteristics: Amended description of
LV_PLL
Figure 10: Exchanged position of symbols CDEC1 and CDEC2
Updated Table 19
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
97
Document revision history
Table 49. Revision history (continued)
Description of Changes
Revision
Date
2
06-Mar-2009 Added Figure 11
Updated Table 20 and Table 21
Updated Section 4.11, “Flash memory electrical characteristics
Added Section 4.12, “Electromagnetic compatibility (EMC) characteristics
Updated Section 4.13, “Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
Updated Section 4.14, “Slow external crystal oscillator (32 kHz) electrical characteristics
Updated Table 34, Table 35 and Table 36
Added Section 4.19, “On-chip peripherals
Added Table 37
Updated Table 38
Updated Table 47
Added Section Appendix A, “Abbreviations
4
06-Aug-2009 Updated Figure 6
Table 5
• VDD_ADC: changed min value for “relative to VDD” condition
• VIN: changed min value for “relative to VDD” condition
• ICORELV: added new row
Table 7
• TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part
:
added new rows
• Changed capacitance value in footnote
Table 14
• MEDIUM configuration: added condition for PAD3V5V = 0
Updated Figure 10
Table 19
• CDEC1: changed min value
• IMREG: changed max value
• IDD_BV: added max value footnote
Table 20
• VLVDHV3H: changed max value
• VLVDHV3L: added max value
• VLVDHV5H: changed max value
• VLVDHV5L: added max value
Updated Table 21
Table 23
• Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“
Table 31
• IFXOSC: added typ value
Table 33
• VSXOSC: changed typ value
• TSXOSCSU: added max value footnote
Table 34
• tLTJIT: added max value
Updated Figure 36
MPC5604B/C Microcontroller Data Sheet, Rev. 9
98
Freescale Semiconductor
Document revision history
Table 49. Revision history (continued)
Description of Changes
Revision
Date
5
02-Nov-2009 In the “MPC5604B/C series block summary” table, added a new row.
In the “Absolute maximum ratings” table, changed max value of VDD_BV, VDD_ADC, and
VIN.
In the “Recommended operating conditions (3.3 V)” table, deleted min value of TVDD
.
In the “Reset electrical characteristics” table, changed footnotes 3 and 5.
In the “Voltage regulator electrical characteristics” table:
• CREGn: changed max value.
• CDEC1: split into 2 rows.
• Updated voltage values in footnote 4
In the “Low voltage monitor electrical characteristics” table:
• Updated column Conditions.
• VLVDLVCORL, VLVDLVBKPL: changed min/max value.
In the “Program and erase specifications” table, added initial max value of Tdwprogram
In the “Flash module life” table, changed min value for blocks with 100K P/E cycles
In the “Flash power supply DC electrical characteristics” table:
• IFREAD, IFMOD: added typ value.
.
• Added footnote 1.
Added “NVUSRO[WATCHDOG_EN] field description” section.
Section 4.18: “ADC electrical characteristics” has been moved up in hierarchy (it was
Section 4.18.5).
In the “ADC conversion characteristics” table, changed initial max value of RAD
.
In the “On-chip peripherals current consumption” table:
• Removed min/max from the heading.
• Changed unit of measurement and consequently rounded the values.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
99
Document revision history
Table 49. Revision history (continued)
Description of Changes
Revision
Date
6
15-Mar-2010 In the “Introduction” section, relocated a note.
In the “MPC5604B/C device comparison” table, added footnote regarding SCI and CAN.
In the “Absolute maximum ratings” table, removed the min value of VIN relative to VDD
.
In the “Recommended operating conditions (3.3 V)” table:
• TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part
added new rows.
:
• TVDD: made single row.
In the “LQFP thermal characteristics” table, added more rows.
Removed “208 MAPBGA thermal characteristics” table.
In the “I/O consumption” table:
• Removed IDYNSEG row.
• Added “I/O weight” table.
In the “Voltage regulator electrical characteristics” table:
• Updated the values.
• Removed IVREGREF and IVREDLVD12
• Added a note about IDD_BC
.
.
In the “Low voltage monitor electrical characteristics” table:
• Updated VPORH values.
• Updated VLVDLVCORL value.
Entirely updated the “Low voltage power domain electrical characteristics” table.
In the “Program and erase specifications” table, inserted Teslat row.
Entirely updated the “Flash power supply DC electrical characteristics” table.
Entirely updated the “Start-up time/Switch-off time” table.
In the “Crystal oscillator and resonator connection scheme” figure, relocated a note.
In the “Slow external crystal oscillator (32 kHz) electrical characteristics” table:
• Removed gmSXOSC row.
• Inserted values of ISXOSCBIAS
.
Entirely updated the “Fast internal RC oscillator (16 MHz) electrical characteristics” table.
In the “ADC conversion characteristics” table: updated the description of the conditions of
tADC_PU and tADC_S.
Entirely updated the “DSPI characteristics” table.
In the “Orderable part number summary” table, modified some orderable part number.
Updated the “Commercial product code structure” figure.
Removed the note about the condition from “Flash read access timing” table
Removed the notes that assert the values need to be confirmed before validation
Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin configuration”
Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP 144-pin
package mechanical drawing”
MPC5604B/C Microcontroller Data Sheet, Rev. 9
100
Freescale Semiconductor
Document revision history
Table 49. Revision history (continued)
Description of Changes
Revision
Date
7
05-Jul-2010 Added 64 LQFP package information
Updated the “Features” section.
Figures “LQFP 100-pin configuration” and “LQFP 100-pin configuration”: removed
alternate function information
Added “Functional port pin descriptions” table
Added eDMA block in the “MPC5604B/C series block diagram” figure
Deleted the “NVUSRO[WATCHDOG_EN] field description” section
In the “Recommended operating conditions (3.3 V)” and “Recommended operating
conditions (5.0 V)” tables, deleted the conditions of TA C-Grade Part, TA V-Grade Part, TA M-Grade
Part
In the “LQFP thermal characteristics” table, rounded the values.
In the “RESET electrical characteristics” section, replaced “nRSTIN” with “RESET”.
In the “I/O input DC electrical characteristics” table:
• WFI: inserted a footnote
• WNFI: inserted a footnote
In the “Low voltage monitor electrical characteristics” table:
• changed min value VLVDHV3L, from 2.7 to 2.6
• Inserted max value of VLVDLVCORL
In the “FMPLL electrical characteristics” table, rounded the values of fVCO.
In the “DSPI characteristics” table:
• Added tASC row
• Update values of tA
In the “ADC conversion characteristics” table, added “IADCPWD” and “IADCRUN” rows
Removed “Orderable part number summary” table.
8
25-Nov-2010 Editorial changes and improvements.
In the “MPC5604B/C device comparison” table, changed the temperature value from 105
to 125 °C, in the footnote regarding “Execution speed”.
In the “Recommended operating conditions (3.3 V)” and “Recommended operating
conditions (5.0 V)” tables, restored the conditions of TA C-Grade Part, TA V-Grade Part, TA
M-Grade Part
In the “LQFP thermal characteristics” table, added values concerning 64 LQFP package.
In the “MEDIUM configuration output buffer electrical characteristics” table: fixed a typo in
last row of conditions column, there was IOH that now is IOL
.
In the “Reset electrical characteristics” table, changed the parameter classification tag for
VOL and |IWPU|.
In the “Low voltage monitor electrical characteristics” table, changed the max value of
VLVDLVCORL from 1.5V to 1.15V.
In the “Program and erase specifications” table, replaced “Teslat” with “Tesus”.
In the “FMPLL electrical characteristics” table, changed the parameter classification tag
for fVCO
.
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
101
Document revision history
Table 49. Revision history (continued)
Description of Changes
Revision
Date
9
16 June 2011 Formatting and minor editorial changes throughout
Harmonized oscillator nomenclature
Removed all instances of note “All 64 LQFP information is indicative and must be
confirmed during silicon validation.”
Device comparison table: changed temperature value in footnote 2 from 105 °C to 125 °C
MPC560xB LQFP 64-pin configuration and MPC560xC LQFP 64-pin configuration:
renamed pin 6 from VPP_TEST to VSS_HV
Removed “Pin Muxing” section; added sections “Pad configuration during reset phases”,
“Voltage supply pins”, “Pad types”, “System pins,” “Functional ports”, and “Nexus 2+
pins”
Section “NVUSRO register”: edited content to separate configuration into electrical
parameters and digital functionality; updated footnote describing default value of ‘1’ in
field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN]
Added section “NVUSRO[WATCHDOG_EN] field description”
Recommended operating conditions (3.3 V) and Recommended operating conditions
(5.0 V): updated conditions for ambient and junction temperature characteristics
I/O input DC electrical characteristics: updated ILKG characteristics
Section “I/O pad current specification”: removed content referencing the IDYNSEG
maximum value
I/O consumption: replaced instances of “Root medium square” with “Root mean square”
I/O weight: replaced instances of bit “SRE” with “SRC”; added pads PH[9] and PH[10];
added supply segments; removed weight values in 64-pin LQFP for pads that do not
exist in that package
Reset electrical characteristics: updated parameter classification for |IWPU
|
Updated Voltage regulator electrical characteristics
Section “Low voltage detector electrical characteristics”: changed title (was “Voltage
monitor electrical characteristics”); added event status flag names found in RGM
chapter of device reference manual to POR module and LVD descriptions; replaced
instances of “Low voltage monitor” with “Low voltage detector”; updated values for
VLVDLVBKPL and VLVDLVCORL; replaced “LVD_DIGBKP” with “LVDLVBKP” in note
Updated section “Power consumption”
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated parameter
classification for VFXOSCOP
Crystal oscillator and resonator connection scheme: added footnote about possibility of
adding a series resistor
Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1
FMPLL electrical characteristics: added short term jitter characteristics; inserted “—” in
empty min value cell of tlock row
Section “Input impedance and ADC accuracy”: changed “VA/VA2” to “VA2/VA” in
Equation 11
ADC input leakage current: updated ILKG characteristics
ADC conversion characteristics: updated symbols
On-chip peripherals current consumption: changed “supply current on “VDD_HV_ADC” to
“supply current on” VDD_HV” in IDD_HV(FLASH) row; updated IDD_HV(PLL) value—was
3 * fperiph, is 30 * fperiph; updated footnotes
DSPI characteristics: added rows tPCSC and tPASC
Added DSPI PCS strobe (PCSS) timing diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 9
102
Freescale Semiconductor
Abbreviations
Appendix A Abbreviations
Table A-1 lists abbreviations used but not defined elsewhere in this document.
Table A-1. Abbreviations
Abbreviation
Meaning
CMOS
CPHA
CPOL
CS
Complementary metal–oxide–semiconductor
Clock phase
Clock polarity
Peripheral chip select
Event out
EVTO
MCKO
MDO
MSEO
MTFE
SCK
Message clock out
Message data out
Message start/end out
Modified timing format enable
Serial communications clock
Serial data out
SOUT
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5604B/C Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
103
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MPC5604BC
Rev. 9
06/2011
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