MPC8260ZUGIAXXX [NXP]
32-BIT, 150MHz, RISC PROCESSOR, PBGA480, 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480;
| 型号： | MPC8260ZUGIAXXX |
| 厂家： | 
NXP |
| 描述： | 32-BIT, 150MHz, RISC PROCESSOR, PBGA480, 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480 |
| 文件： | 总40页 (文件大小：1069K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8260EC
Rev. 1.3, 10/2005
Freescale Semiconductor
Technical Data
MPC8260
PowerQUICC™ II Integrated
Communications Processor
Hardware Specifications
Contents
This document contains detailed information on power
1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical and Thermal Characteristics . . . . . . . . . . . . 5
3. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 19
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 36
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 37
7. Document Revision History . . . . . . . . . . . . . . . . . . . 38
considerations, DC/AC electrical characteristics, and AC
timing specifications for the .29 µm (HiP3) devices of the
PowerQUICC II™ family of communications processors:
the MPC8260 and the MPC8255. Throughout this
document, the MPC8260 and the MPC8255 are collectively
referred to as the MPC8260.
© Freescale Semiconductor, Inc., 2003, 2005. All rights reserved.
Features
NOTE: Document Revision History
Changes to this document are summarized in Table 17.
Figure 1 shows the block diagram for the MPC8260.
16 Kbytes
I-Cache
I-MMU
System Interface Unit
(SIU)
60x Bus
G2 Core
16 Kbytes
D-Cache
Bus Interface Unit
60x-to-Local
Bridge
Local Bus
32 bits, up to 66 MHz
D-MMU
Memory Controller
Clock Counter
Communication Processor Module (CPM)
Timers
Serial
DMAs
24 Kbytes
Interrupt
Controller
Dual-Port RAM
System Functions
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
2 Virtual
IDMAs
Baud Rate
Generators
1
1
2
MCC1 MCC2 FCC1 FCC2 FCC3
SCC1 SCC2 SCC3 SCC4 SMC1 SMC2
SPI
I C
Time Slot Assigner
Serial Interface
Non-Multiplexed
I/O
8 TDM Ports2
3 MII
2 UTOPIA
Ports
Ports3
Notes:
1 Not on MPC8255
2 4 on the MPC8255
3 2 on the MPC8255
Figure 1. MPC8260 Block Diagram
1 Features
The major features of the MPC8260 are as follows:
•
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the
MPC8255)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
2
Freescale Semiconductor
Features
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
•
•
Separate power supply for internal logic and for I/O
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
•
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
•
•
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
•
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
CPU core can be disabled and the device can be used in slave mode to an external core
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
3
Features
•
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications protocols
— Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers (two on the MPC8255) supporting the following
protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
2
2
— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
4
Freescale Semiconductor
Electrical and Thermal Characteristics
— Up to eight TDM interfaces (4 on the MPC8255)
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8260.
2.1
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8260. Table 1 shows the maximum
electrical ratings.
1
Table 1. Absolute Maximum Ratings
Rating
Core supply voltage 2
Symbol
Value
Unit
VDD
VCCSYN
VDDH
VIN
-0.3 – 2.75
-0.3 – 2.75
-0.3 – 4.0
V
V
PLL supply voltage2
I/O supply voltage 3
Input voltage 4
V
GND(-0.3) – 3.6
120
V
Junction temperature
Storage temperature range
Tj
°C
°C
TSTG
(-55) – (+150)
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
2
3
Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.
Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.0 V during normal operation.
4
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
5
Electrical and Thermal Characteristics
Table 2 lists recommended operational voltage conditions.
1
Table 2. Recommended Operating Conditions
Rating
Core supply voltage
Symbol
2.5-V Device 2
Unit
VDD
VCCSYN
VDDH
VIN
2.4–2.7
2.4–2.7
V
V
PLL supply voltage
I/O supply voltage
3.135 – 3.465
GND (-0.3) – 3.465
105
V
Input voltage
V
Junction temperature (maximum)
Tj
°C
1
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these
conditions is not guaranteed.
2
Parts labeled with an “-HVA” suffix are 2.6-V devices.
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in
the same direction—in the positive direction (+5% and +0.1 Vdc) or in the
negative direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or V ).
CC
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
4 V
GVDD + 5%
VIH
GVDD
GND
GND – 0.3 V
VIL
GND – 1.0 V
Not to exceed 10%
of tSDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
6
Electrical and Thermal Characteristics
Table 3 shows DC electrical characteristics.
1
Table 3. DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs except CLKIN
Input low voltage
VIH
VIL
VIHC
VILC
IIN
2.0
GND
2.4
GND
—
3.465
0.8
3.465
0.4
10
V
V
CLKIN input high voltage
V
CLKIN input low voltage
V
Input leakage current, VIN = VDDH 2
Hi-Z (off state) leakage current, VIN = VDDH2
Signal low input current, VIL = 0.8 V
Signal high input current, VIH = 2.0 V
µA
µA
µA
µA
V
IOZ
IL
—
10
—
1
IH
—
1
Output high voltage, IOH = –2 mA
VOH
2.4
—
except XFC, UTOPIA mode, and open drain pins
In UTOPIA mode: IOH = -8.0mA
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
In UTOPIA mode: IOL = 8.0mA
VOL
—
0.5
V
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
7
Electrical and Thermal Characteristics
1
Table 3. DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
IOL = 7.0mA
V
—
0.4
V
OL
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
8
Electrical and Thermal Characteristics
1
Table 3. DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
I
= 5.3mA
V
—
0.4
V
OL
OL
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0:3]/LBS[0–3]
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX 3/LGPL5
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
I
= 3.2mA
OL
L_A14
L_A15/SMI
L_A16
L_A17/CKSTP_OUT
L_A18
L_A19
L_A20
L_A21
L_A22
L_A23
L_A24
L_A25
L_A26
L_A27
L_A28/CORE_SRESET
L_A29
L_A30
L_A31
LCL_D(0-31)
LCL_DP(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
1
2
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
The leakage current is measured for nominal VDD, VCCSYN, and VDD.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
9
Electrical and Thermal Characteristics
3
Rev C.2 silicon only.
2.2
Thermal Characteristics
Table 4 describes thermal characteristics.
Table 4. Thermal Characteristics
Characteristics
Symbol
Value
Unit
Air Flow
Thermal resistance for TBGA
θJA
θJA
θJA
θJA
13.07 1
9.551
°C/W
°C/W
°C/W
°C/W
NC 2
1 m/s
NC
10.48 3
7.783
1 m/s
1
2
3
Assumes a single layer board with no thermal vias
Natural convection
Assumes a four layer board
2.3
Power Considerations
The average chip-junction temperature, T , in °C can be obtained from the following:
J
TJ = TA + (PD x θJA)
(1)
where
TA = ambient temperature °C
θJA = package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD x VDD Watts (chip internal power)
P
I/O = power dissipation on input and output pins (determined by user)
For most applications P < 0.3 x P . If P is neglected, an approximate relationship between P and
I/O
INT
I/O
D
T is the following:
J
PD = K/(TJ + 273° C)
(2)
(3)
Solving equations (1) and (2) for K gives:
2
K = PD x (TA + 273° C) + θJA x PD
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving equations (1) and (2) iteratively for any value of T .
A
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
10
Electrical and Thermal Characteristics
2.3.1
Layout Practices
Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground
CC
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V power supply should be bypassed to ground using at least four
CC
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip V and ground should be kept to less than half an
CC
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the MPC8260 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be
CC
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above P = 3W (when the ambient temperature is 70° C or
D
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that
the I/O power should be included when determining whether to use a heat sink.
1
Table 5. Estimated Power Dissipation for Various Configurations
P
INT (W) 2
Bus
(MHz)
CPM
CPU
CPM
(MHz)
CPU
(MHz)
Vddl
Multiplier Multiplier
2.4
2.5
2.6
2.7
2.8 3
33.3
4
4
133.3
133.3
2.04
2.21
2.47
2.57
2.81
2.88
2.83
2.14
2.30
2.62
2.69
2.95
3.05
3.00
2.26
2.45
2.74
2.83
3.12
3.22
3.14
2.38
2.59
2.88
2.98
3.29
3.38
3.31
2.50
2.69
3.02
3.12
3.43
3.55
3.48
50.0
66.7
66.7
66.7
66.7
50.0
2
3
100
150.0
166.7
166.7
200.0
200.0
200.0
2
2.5
2.5
3
133.3
166.7
133.3
166.7
150
2.5
2
2.5
3
3
4
1
2
3
Test temperature = room temperature (25° C)
PINT = IDD x VDD Watts
2.8 Vddl does not apply to HiP3 Rev C silicon.
2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8260 device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 6.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
11
Electrical and Thermal Characteristics
1
Table 6. Output Buffer Impedances
Output Buffers
Typical Impedance (Ω)
60x bus
40
40
40
46
Local bus
Memory controller
Parallel I/O
1
These are typical values at 65° C. The impedance may vary by
25% with process and temperature.
Table 7 lists CPM output characteristics.
1
Table 7. AC Characteristics for CPM Outputs
Spec Number
Max Min
Max Delay (ns) Min Delay (ns)
Characteristic
66 MHz
66 MHz
sp36a sp37a FCC outputs—internal clock (NMSI)
sp36b sp37b FCC outputs—external clock (NMSI)
6
1
2
5
1
2
1
14
25
19
19
14
sp40
sp41 TDM outputs/SI
sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
sp38b sp39b Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)
sp42
sp43 PIO/TIMER/IDMA outputs
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the
signal. Timings are measured at the pin.
Table 8 lists CPM input characteristics.
1
Table 8. AC Characteristics for CPM Inputs
Spec Number
Setup Hold
Setup (ns)
66 MHz
Hold (ns)
66 MHz
Characteristic
sp16a sp17a FCC inputs—internal clock (NMSI)
sp16b sp17b FCC inputs—external clock (NMSI)
10
3
0
3
sp20
sp21 TDM inputs/SI
15
20
5
12
0
sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI)
5
sp22
sp23 PIO/TIMER/IDMA inputs
10
3
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of
CLKIN. Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
12
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 3 shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 1
Figure 3. FCC External Clock Diagram
Figure 4 shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
FCC output signals
sp36a/sp37a
Note: When GFMR[TCI] = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.[TCI] = 1
Figure 4. FCC Internal Clock Diagram
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
13
Electrical and Thermal Characteristics
2
Figure 5 shows the SCC/SMC/SPI/I C external clock.
Serial CLKin
sp19b
sp18b
SCC/SMC/SPI/I2C input signals
(See note)
sp38b/sp39b
SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 5. SCC/SMC/SPI/I C External Clock Diagram
2
Figure 6 shows the SCC/SMC/SPI/I C internal clock.
BRG_OUT
sp19a
sp18a
SCC/SMC/SPI/I2C input signals
(See note)
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
14
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 7 shows PIO, timer, and DMA signals.
Sys clk
sp23
sp22
PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23
sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43
IDMA output signals
sp42/sp43
TIMER/PIO
output signals
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 7. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
1
Table 9. AC Characteristics for SIU Inputs
Spec Number
Setup (ns)
66 MHz
Hold (ns)
66 MHz
Characteristic
Setup
Hold
sp11
sp12
sp13
sp14
sp14
sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR
sp10 Data bus in normal mode
sp10 Data bus in ECC and PARITY modes
sp10 DP pins
6
5
8
8
5
1
1
1
1
1
sp10 All other pins
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of
CLKIN. Timings are measured at the pin.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
15
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
1
Table 10. AC Characteristics for SIU Outputs
Spec Number
Max Delay (ns) Min Delay (ns)
Characteristic
Max
Min
66 MHz
66 MHz
sp31
sp32
sp30 PSDVAL/TEA/TA
10
8
0.5
0.5
0.5
0.5
0.5
0.5
sp30 ADD/ADD_atr./BADDR/CI/GBL/WT
sp30 Data bus
sp33a
sp33b
sp34
8
sp30 DP
12
6
sp30 memc signals/ALE
sp30 all other signals
sp35
7.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 8 shows TDM input and output signals.
Serial CLKin
sp20
sp21
TDM input signals
TDM output signals
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 8. TDM Signal Diagram
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
CLKin
sp10
sp10
sp11
AACK/ARTRY/TA/TS/TEA/
DBG/BG/BR input signals
sp12
DATA bus normal mode
input signal
sp10
sp30
sp15
All other input signals
sp31
sp32
PSDVAL/TEA/TA output signals
sp30
sp30
sp30
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp33a
sp35
DATA bus output signals
All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
sp10
sp13
DATA bus, ECC, and PARITY mode input signals
sp10
sp14
DP mode input signal
sp33b/sp30
DP mode output signal
Figure 10. Parity Mode Diagram
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Figure 11 shows signal behavior in MEMC mode.
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8260 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Ratio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
1:3.5
3/10 CLKin
4/14 CLKin
1/2 CLKin
1/2 CLKin
8/10 CLKin
11/14 CLKin
Figure 12 is a graphical representation of Table 11.
CLKin
CLKin
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T1
T1
T2
T3
T3
T3
T4
for 1:2.5
T2
T4
for 1:3.5
T2
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
18
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
3 Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
NOTE
Clock configurations change only after POR is asserted.
3.1
Local Bus Mode
Table 12 describes default clock modes for the MPC8260.
Table 12. Clock Default Modes
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
MODCK[1–3]
Frequency
Factor
000
001
010
011
100
101
110
111
33 MHz
33 MHz
33 MHz
33 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
166 MHz
4
5
133 MHz
166 MHz
133 MHz
166 MHz
166 MHz
200 MHz
166 MHz
200 MHz
4
4
4
5
2
2.5
3
2
2.5
2.5
2.5
3
Table 13 describes all possible clock configurations when using the hard reset configuration sequence.
Note also that basic modes are shown in boldface type.
1
Table 13. Clock Configuration Modes
Input Clock
CPM Multiplication
Factor2, 5
CPM
Core Multiplication
Factor2, 6
Core
MODCK_H–MODCK[1–3]
Frequency2,3,4
Frequency2
Frequency2
0001_000
0001_001
0001_010
0001_011
0001_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
2
2
2
2
2
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
19
Clock Configuration Modes
MODCK_H–MODCK[1–3]
1
Table 13. Clock Configuration Modes (continued)
Input Clock
CPM Multiplication
Factor2, 5
CPM
Core Multiplication
Factor2, 6
Core
Frequency2,3,4
Frequency2
Frequency2
0001_101
0001_110
0001_111
0010_000
0010_001
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_010
0010_011
0010_100
0010_101
0010_110
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_111
0011_000
0011_001
0011_010
0011_011
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0011_100
0011_101
0011_110
0011_111
0100_000
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
6
6
6
6
6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0100_001
0100_010
0100_011
0100_100
0100_101
0100_110
Reserved
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
20
Clock Configuration Modes
1
Table 13. Clock Configuration Modes (continued)
Input Clock
CPM Multiplication
Factor2, 5
CPM
Core Multiplication
Core
MODCK_H–MODCK[1–3]
Frequency2,3,4
Frequency2
Factor2, 6
Frequency2
0100_111
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101
0101_110
0101_111
0110_000
0110_001
0110_010
Reserved
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0110_011
0110_100
0110_101
0110_110
0110_111
0111_000
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0111_001
0111_010
0111_011
0111_100
0111_101
0111_110
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
1
Because of speed dependencies, not all of the possible configurations in Table 13 are applicable.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
21
Pinout
2
The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU
ranges between 133–200 and the CPM ranges between 50–166 MHz.
3
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that the
resulting configuration does not exceed the frequency rating of the user’s part.
4
5
6
60x and local bus frequency. Identical to CLKIN.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
4 Pinout
This section provides the pin assignments and pinout list for the MPC8260.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
22
Freescale Semiconductor
Pinout
4.1
Pin Assignments
Figure 13 shows the pinout of the MPC8260 480 TBGA package as viewed from the top surface.
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
23
Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Pressure Sensitive
Copper Heat Spreader
(Oxidized for Insulation)
Adhesive
Etched
Cavity
Die
Attach
Polymide Tape
Die
Glob-Top Filled Area
Soldermask
Glob-Top Dam
Copper Traces
1.27 mm Pitch
Wire Bonds
Figure 14. Side View of the TBGA Package
Table 14 shows the pinout list of the MPC8260. Table 15 defines conventions and acronyms used in
Table 14.
Table 14. Pinout List
Pin Name
Ball
BR
W5
F4
E2
E3
G1
H5
H2
H1
J5
BG
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
K3
K2
K1
L5
L4
L3
L2
L1
A10
A11
A12
A13
A14
A15
A16
A17
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
24
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
A18
M5
N5
N4
N3
N2
N1
P4
P3
P2
P1
R1
R3
R5
R4
F1
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
TT0
TT1
G4
G3
G2
F2
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
D3
C1
E4
D2
F5
F3
E1
V1
V2
B20
A18
A16
A13
E12
D9
A6
D1
D2
D3
D4
D5
D6
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
25
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
D7
B5
D8
A20
E17
B15
B13
A11
E9
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
B7
B4
D19
D17
D15
C13
B11
A8
A5
C5
C19
C17
C15
D13
C11
B8
A4
E6
E18
B17
A15
A12
D11
C8
E7
A3
D18
A17
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
26
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
D42
A14
B12
A10
D8
D43
D44
D45
D46
B6
D47
C4
D48
C18
E16
B14
C12
B10
A7
D49
D50
D51
D52
D53
D54
C6
D55
D5
D56
B18
B16
E14
D12
C10
E8
D57
D58
D59
D60
D61
D62
D6
D63
C2
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
B22
A22
E21
D21
C21
B21
A21
E20
V3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
TA
C22
V5
TEA
GBL/IRQ1
W1
U2
CI/BADDR29/IRQ2
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
27
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
WT/BADDR30/IRQ3
U3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
Y4
U4
R2
CPU_BR
Y3
CS0
F25
C29
E27
E28
F26
F27
F28
G25
D29
E29
F29
G28
T5
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
U1
ALE
T2
BCTL0
A27
C25
E24
D24
C24
B26
A26
B25
A25
E23
B24
A24
B23
A23
D22
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
28
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
LWE0/LSDDQM0/LBS0
LWE1/LSDDQM1/LBS1
LWE2/LSDDQM2/LBS2
LWE3/LSDDQM3/LBS3
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX 1
LWR
H28
H27
H26
G29
D27
C28
E26
D25
C26
B27
D28
N27
T29
L_A14
L_A15/SMI
L_A16
R27
R26
R29
R28
W29
P28
N26
AA27
P29
AA26
N25
AA25
AB29
AB28
P25
AB27
H29
J29
L_A17/CKSTP_OUT
L_A18
L_A19
L_A20
L_A21
L_A22
L_A23
L_A24
L_A25
L_A26
L_A27
L_A28/CORE_SRESET
L_A29
L_A30
L_A31
LCL_D0
LCL_D1
LCL_D2
J28
LCL_D3
J27
LCL_D4
J26
LCL_D5
J25
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
29
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
LCL_D6
K25
L29
L27
L26
L25
M29
M28
M27
M26
N29
T25
U27
U26
U25
V29
V28
V27
V26
W27
W26
W25
Y29
Y28
Y25
AA29
AA28
L28
N28
T28
W28
T1
LCL_D7
LCL_D8
LCL_D9
LCL_D10
LCL_D11
LCL_D12
LCL_D13
LCL_D14
LCL_D15
LCL_D16
LCL_D17
LCL_D18
LCL_D19
LCL_D20
LCL_D21
LCL_D22
LCL_D23
LCL_D24
LCL_D25
LCL_D26
LCL_D27
LCL_D28
LCL_D29
LCL_D30
LCL_D31
LCL_DP0
LCL_DP1
LCL_DP2
LCL_DP3
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
TRST
D1
AH3
AG5
AJ3
TCK
TMS
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
30
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
TDI
AE6
TDO
AF5
TRIS
AB4
PORESET
AG6
HRESET
AH5
SRESET
AF6
QREQ
AA3
RSTCONF
AJ4
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
W2
W3
W4
AB2
CLKIN1
AH4
PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2
PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3
PA2/CLK20/FCC2_UTM_TXADDR0/DACK3
AC29 2
AC252
AE282
AG292
AG282
AG262
AE242
AH252
AF232
AH232
AE222
AH222
AJ212
AH202
AG192
AF182
AF172
AE162
AJ162
AG152
AJ132
AE132
PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2
PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4
PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2
PA6/L1RSYNCA1
PA7/SMSYN2/L1TSYNCA1/L1GNTA1
PA8/SMRXD2/L1RXD0A1/L1RXDA1
PA9/SMTXD2/L1TXD0A1
PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5
PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4
PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3
PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2
PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3
PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2
PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1
PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD
PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD
PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1
PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2
PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
31
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11
AF122
AG112
AH92
AJ82
PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10
PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1
PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0
PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER
PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV
AH72
AF72
AD52
AF12
PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN
PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER
PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS AD32
PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL
PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS
PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2
PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2
PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2
PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3_RXD/TXD3/L1RSYNCD1
PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1
PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1
AB52
AD282
AD262
AD252
AE262
AH272
AG242
AH242
AJ242
AG222
AH212
AG202
AF192
AJ182
AJ172
AE142
AF132
AG122
AH112
PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1
PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2
PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2
PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1
PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1
PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18
PB17/FCC3_MII_RX_DV/L1RQA1/CLK17
PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2
PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1
PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/
L1TXD2A1
PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2
PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2
PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2
PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1
PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2
AH162
AE152
AJ92
AE92
AJ72
PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2
AH62
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
32
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
AE32
AE22
PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/
FCC2_MII_TX_EN
PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2
PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
AC52
AC42
AB262
AD292
AE292
AE272
AF272
AF242
AJ262
PC1/DREQ2/BRGO6/L1RQA2
PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2
PC3/FCC3_CTS/FCC2_UT8_TXD2/DACK2/CTS4
PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD
PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1
AJ252
PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3
AF222
AE212
AF202
AE192
PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2
PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3
PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 AE182
PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1
PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0
PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0
PC16/CLK16/TIN4
AH182
AH172
AG162
AF152
AJ152
AH142
AG132
AH122
AJ112
AG102
AE102
AF92
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
PC19/CLK13/BRGO7/SPICLK
PC20/CLK12/TGATE1
PC21/CLK11/BRGO6
PC22/CLK10/DONE1
PC23/CLK9/BRGO5/DACK1
PC24/FCC2_UT8_TXD3/CLK8/TOUT4
PC25/FCC2_UT8_TXD2/CLK7/BRGO4
PC26/CLK6/TOUT3/TMCLK
AE82
AJ62
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
AG22
AF32
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
33
Pinout
Table 14. Pinout List (continued)
Pin Name
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
Ball
AF22
PC30/FCC2_UT8_TXD3/CLK2/TOUT1
PC31/CLK1/BRGO1
AE12
AD12
PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2
PD5/FCC1_UT16_TXD3/DONE1
AC282
AD272
AF292
AF282
PD6/FCC1_UT16_TXD4/DACK1
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/
FCC1_UTM_TXADDR4/FCC1_TXCLAV2
PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5
PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3
PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4
PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1
PD12/SI1_L1ST2/L1RXDB1
AG252
AH262
AJ272
AJ232
AG232
AJ222
AE202
AJ202
AG182
AG172
PD13/SI1_L1ST1/L1TXDB1
PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL
PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA
PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO
PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/ AF162
SPICLK/FCC2_UTM_RXADDR3/FCC2_UTS_RXADDR0
PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/FCC1_UTM_TXCLAV3/
SPISEL/BRGO1/FCC2_UTM_TXADDR3/FCC2_UTS_TXADDR0
AH152
PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1
AJ142
AH132
AJ122
AE122
AF102
AG92
AH82
AG72
AE42
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/FCC2_UTM_RXADDR4/FCC2_UTS_RXADDR1
AG12
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1
AD42
AD22
AB3
PD31/RXD1
VCCSYN
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
34
Pinout
Table 14. Pinout List (continued)
Pin Name
Ball
VCCSYN1
GNDSYN
B9
AB1
AE11
U5
SPARE1 3
SPARE43
SPARE5 4
SPARE63
AF25
V4
THERMAL0 5
THERMAL15
I/O power
AA1
AG4
AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29,
C7, C14, C16, C20, C23, E10, A28,
A29, B28, B29, C27, D26, E25, H3,
M4, T3, AA4, A1, A2, B1, B2, C3,
D4, E5
Core Power
Ground
U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25, Y26,
V25, T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
1
Only on Rev C.2 silicon.
2
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
3
4
Must be pulled down or left floating.
Must be pulled down or left floating. However, if compatibility with HiP4 silicon is required, this pin must be pulled up
or left floating.
5
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide available at
www.freescale.com.
Symbols used in Table 14 are described in Table 15.
Table 15. Symbol Legend
Symbol
Meaning
OVERBAR
UTM
Signals with overbars, such as TA, are active low.
Indicates that a signal is part of the UTOPIA master interface.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
35
Package Description
Table 15. Symbol Legend (continued)
Indicates that a signal is part of the UTOPIA slave interface.
UTS
UT8
UT16
MII
Indicates that a signal is part of the 8-bit UTOPIA interface.
Indicates that a signal is part of the 16-bit UTOPIA interface.
Indicates that a signal is part of the media independent interface.
5 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC8260.
5.1
Package Parameters
Package parameters are provided in Table 16. The package type is a 37.5 x 37.5 mm, 480-lead TBGA.
Table 16. Package Parameters
Parameter
Package Outline
Value
37.5 x 37.5 mm
Interconnects
Pitch
480 (29 x 29 ball array)
1.27 mm
Nominal unmounted package height 1.55 mm
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
36
Freescale Semiconductor
Ordering Information
5.2
Mechanical Dimensions
Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA
package.
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
Millimeters
Dim
Min
Max
A
A1
A2
A3
b
1.45
0.60
0.85
0.25
0.65
1.65
0.70
0.95
—
0.85
D
37.50 BSC
D1
e
35.56 REF
1.27 BSC
37.50 BSC
35.56 REF
E
E1
Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature
6 Ordering Information
Figure 16 provides an example of the Freescale part numbering nomenclature for the MPC8260. In
addition to the processor frequency, the part numbering scheme also consists of a part modifier that
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
37
Document Revision History
indicates any enhancement(s) in the part from the original production design. Each part number also
contains a revision code that refers to the die mask revision number and is specified in the part numbering
scheme for identification purposes only. For more information, contact your local Freescale sales office.
MPC 82XX C ZU XXX X XX
Die Revision Level
(Nn = Major.minor)
Product Code
Core Voltage
Device Number
Processor Frequency
(CPU/CPM/Bus)
Package
(ZU = 480 TBGA)
Temperature Range
Blank = 0 to 105 °C
C = -40 to 105 °C
Figure 16. Freescale Part Number Key
7 Document Revision History
Table 17 lists significant changes in each revision of this document.
Table 17. Document Revision History
Revision
Date
Substantive Changes
0
0.1
—
1/2000
—
Initial version
—
0.2–0.5
0.6
Temporary revisions
5/2001 Corrected the thermal values in Table 3, “Thermal Characteristics.”
0.7
11/2001 • Revision of Table 5, “Power Dissipation”
• Modifications to Figure 9, Table 2,Table 10, Table 11
• Additional revisions to text and figures throughout
0.8
2/2002
• Table 7, Table 8, Table 9, and Table 10: revision 0.7 of this document incorrectly included values for
83 MHz. 83 MHz is not supported on the MPC8260.
• Table 14: notes added to pins at AE11, AF25, U5, and V4.
0.9
1.0
2/2002
3/2002
• Table 14: additional note added to AE11
• Table 14: modified notes to pins AE11 and AF25.
• Table 14: added note to pins AA1 and AG4 (Therm0 and Therm1).
1.1
5/2002
• Section 1, “Features”: updated minimum supported core frequency to 133 MHz
• Addition of “Note” at bottom of page 5.
• Table 13: Note 3.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
38
Document Revision History
Table 17. Document Revision History (continued)
Substantive Changes
Revision
Date
1.2
8/2003
• Note: In revision 0.7, sp30 (Table 10) was changed. This change was not previously recorded in this
“Document Revision History” Table.
• Addition of MPC8255 description to Section 1, “Features”
• Addition of Figure 2
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
• Addition of note 1 to Table 3
• Addition of notes or modifications to Figure 3 through Figure 8
• Addition of reference notes 4, 5, and 6 to Table 13
• Addition of note 2 to Table 14
• Addition of SPICLK to PC19 in Table 14. It is documented correctly in the MPC8260 PowerQUICC
II™ Family Reference Manual but had previously been omitted from Table 14.
1.3
9/2005
• Document template update.
MPC8260 PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.3
Freescale Semiconductor
39
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Document Number: MPC8260EC
Rev. 1.3
10/2005
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