MPC8280CZUMX_技术文档

Document Number: MPC8280EC

Rev. 2, 09/2011

Freescale Semiconductor

Technical Data

MPC8280

PowerQUICC II Family

Hardware Specifications

Contents

This document contains detailed information about power

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7

3. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 12

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 16

7. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 26

8. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 75

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79

11. Document Revision History . . . . . . . . . . . . . . . . . . . 79

considerations, DC/AC electrical characteristics, and AC

timing specifications for .13µm (HiP7) members of the

PowerQUICC II family of integrated communications

processors—the MPC8280, the MPC8275, and the

MPC8270 (collectively called the MPC8280 throughout this

document).

Overview

1 Overview

This table shows the functionality supported by each SoC in the MPC8280 family.

Table 1. MPC8280 PowerQUICC II Family Functionality

SoCs

Functionality

MPC8270

MPC8275

516 PBGA

MPC8280

480 TBGA

1

Package

480 TBGA 516 PBGA

Serial communications controllers (SCCs)

QUICC multi-channel controller (QMC)

Fast communication controllers (FCCs)

I-Cache (Kbyte)

4

—

3

4

—

3

4

—

3

4

—

3

16

3

16

3

16

3

16

3

D-Cache (Kbyte)

Ethernet (10/100)

UTOPIA II Ports

0

2

Multi-channel controllers (MCCs)

PCI bridge

1

2

Yes

—

1

Yes

—

1

Yes

—

1

Yes

1

Transmission convergence (TC) layer

Inverse multiplexing for ATM (IMA)

Universal serial bus (USB) 2.0 full/low rate

Security engine (SEC)

—

1

See Table 2.

Devices in the MPC8280 family are available in four packages—the standard ZU and VV packages and

the alternate VR or ZQ packages—as shown in Table 2. Note that throughout this document, references to

the MPC8280 and the MPC8270 are inclusive of VR and ZQ package devices unless otherwise specified.

For more information on VR and ZQ packages, contact your Freescale sales office. For package ordering

information, see Section 10, “Ordering Information.”

Table 2. HiP7 PowerQUICC II Device Packages

Code

ZU

VV

VR

ZQ

(Package)

(480 TBGA—Leaded) (480 TBGA—Lead Free) (516 PBGA—Lead free) (516 PBGA—Lead spheres)

MPC8280

MPC8270

MPC8280

MPC8270

MPC8275VR

MPC8270VR

MPC8275ZQ

MPC8270ZQ

Device

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

2

Freescale Semiconductor

Overview

This figure shows the block diagram of the SoC. Shaded portions are SoC-specific; see the notes below

the figure.

16 KB

I-Cache

I-MMU

System Interface Unit

60x Bus

(SIU)

G2_LE Core

16 KB

Bus Interface Unit

D-Cache

PCI Bus

32 bits, up to 66 MHz

60x-to-PCI

Bridge

D-MMU

or

60x-to-Local

Bridge

Local Bus

32 bits, up to 100 MHz

Communication Processor Module (CPM)

Memory Controller

Clock Counter

32 KB

Instruction

RAM

32 KB

Data

RAM

Timers

Interrupt

Controller

Serial

DMAs

Parallel I/O

32-bit RISC Microcontroller

and Program ROM

4 Virtual

IDMAs

System Functions

Baud Rate

Generators

IMA

1

Microcode

I²C

MCC1

MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ SMC1 SMC2

SPI

1

USB

TC Layer Hardware1

Time Slot Assigner

Serial Interface2

Non-Multiplexed

I/O

3 MII or RMII

Ports

2 UTOPIA

Ports3

8 TDM Ports2

Notes:

1

MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)

MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have

only 1 SI block and 4 TDM ports (TDM2[A–D]).

2

3

MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)

Figure 1. SoC Block Diagram

1.1

Features

The major features of the SoC are as follows:

•

Dual-issue integer (G2_LE) core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 166–450 MHz

— Separate 16 KB data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— Power Architecture®-compliant memory management unit (MMU)

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

3

Overview

— Common on-chip processor (COP) test interface

— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)

— Supports bus snooping

— Support for data cache coherency

— Floating-point unit (FPU)

•

Separate power supply for internal logic and for I/O

Separate PLLs for G2_LE core and for the communications processor module (CPM)

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1,

7:1, 8:1

— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1

ratios

•

64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

32-bit data and 18-bit address local bus

•

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

•

PCI bridge

— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming

— PCI host bridge or peripheral capabilities

— Includes 4 DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

4

Freescale Semiconductor

Overview

— Includes all of the configuration registers (which are automatically loaded from the EPROM

and used to configure the MPC8280) required by the PCI standard as well as message and

doorbell registers

— Supports the I O standard

2

— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August

3, 1998)

— Support for 66.67/83.33/100 MHz, 3.3 V specification

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

— Uses the local bus signals, removing need for additional pins

System interface unit (SIU)

•

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

12-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other

user-definable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page mode

pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x) and byte selects for 32-bus width (local)

— Dedicated interface logic for SDRAM

•

CPU core can be disabled and the device can be used in slave mode to an external core

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support

for communications protocols

— Interfaces to G2_LE core through an on-chip 32 KB dual-port data RAM, an on-chip 32 KB

dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII) or reduced media independent interface (RMII)

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

5

Overview

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,

AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external

connections (no ATM support for the MPC8270)

– Transparent

– HDLC—Up to T3 rates (clear channel)

– FCC2 can also be connected to the TC layer (MPC8280 only)

— Two multichannel controllers (MCCs) (one MCC on the MPC8270)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split

into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM

interfaces up to four TDM interfaces per MCC

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting

the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

•

Universal serial bus (USB) controller

— Supports USB 2.0 full/low rate compatible

— USB host mode

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and

data rate configuration). Note that low-speed operation requires an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 Mbps only)

— Supports USB slave mode

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— Two serial management controllers (SMCs), identical to those of the MPC860

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

6

Freescale Semiconductor

Operating Conditions

– Provides management for BRI devices as general-circuit interface (GCI) controllers in

time-division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

2

— One I C controller (identical to the MPC860 I C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8270)

– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on

the MPC8270 and the MPC8275)

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN

primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and

user-defined TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,

SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

•

Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only). Supported by eight transfer

transmission convergence (TC) layers between the TDMs and FCC2.

Transmission convergence (TC) layer (MPC8280 only)

2 Operating Conditions

This table shows the maximum electrical ratings.

1

Table 3. Absolute Maximum Ratings

Rating Symbol

Value

Unit

2

Core supply voltage

VDD

VCCSYN

VDDH

VIN

–0.3 – 2.25

–0.3 – 4.0

V

2

PLL supply voltage

3

I/O supply voltage

V

4

Input voltage

GND(–0.3) – 3.6

120

V

Junction temperature

T

°C

j

Storage temperature range

T

(–55) – (+150)

STG

1

Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

7

Operating Conditions

2

Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that

VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may

exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.

Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should

not exceed VDD/VCCSYN by more than 2.5 V during normal operation.

3

4

Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

This table lists recommended operational voltage conditions.

1

Table 4. Recommended Operating Conditions

Rating

Symbol

Value

Unit

Core supply voltage

PLL supply voltage

VDD

1.45 – 1.60

V

VCCSYN

1.45 – 1.60

V

I/O supply voltage

Input voltage

VDDH

VIN

3.135 – 3.465

V

GND (–0.3) – 3.465

2

Junction temperature (maximum)

Ambient temperature

T

105

°C

j

2

T

0–70

A

1

2

Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions

is not guaranteed.

Note that for extended temperature parts the range is (-40) – 105 .

T

j

A

This SoC contains circuitry protecting against damage due to high static voltage or electrical fields;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (either GND or V ).

CC

This figure shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the

SoC. Note that in PCI mode the I/O interface is different.

4 V

GV + 5%

DD

V

GV

IH

DD

GND

GND – 0.3 V

IL

GND – 1.0 V

Not to exceed 10%

of t

SDRAM_CLK

Figure 2. Overshoot/Undershoot Voltage

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

8

Freescale Semiconductor

DC Electrical Characteristics

3 DC Electrical Characteristics

This table shows DC electrical characteristics.

1

Table 5. DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

2

Input high voltage—all inputs except TCK, TRST and PORESET

Input low voltage

V

2.0

GND

2.4

GND

—

3.465

0.8

3.465

0.4

10

V

IH

V

IL

CLKIN input high voltage

V

IHC

CLKIN input low voltage

V

I

V

ILC

3

Input leakage current, V = VDDH

µA

V

IN

3

Hi-Z (off state) leakage current, V = VDDH

I

—

10

IN

OZ

4

Signal low input current, V = 0.8 V

I

—

1

IL

L

Signal high input current, V = 2.0 V

I

—

1

IH

H

Output high voltage, I = –2 mA

V

2.4

—

OH

except UTOPIA mode, and open drain pins

5

In UTOPIA mode (UTOPIA pins only): I = -8.0mA

OH

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

5

In UTOPIA mode (UTOPIA pins only): I = 8.0mA

V

—

0.5

V

OL

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

9

DC Electrical Characteristics

1

Table 5. DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Max

Unit

I

= 6.0mA

V

—

0.4

V

OL

BR

BG

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG

DBB/IRQ3

D[0-63]

DP(0)/RSRV/EXT_BR2

DP(1)/IRQ1/EXT_BG2

DP(2)/TLBISYNC/IRQ2/EXT_DBG2

DP(3)/IRQ3/EXT_BR3/CKSTP_OUT

DP(4)/IRQ4/EXT_BG3/CORE_SREST

DP(5)/TBEN/EXT_DBG3/IRQ5/CINT

DP(6)/CSE(0)/IRQ6

DP(7)/CSE(1)/IRQ7

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

CPU_BR

IRQ0/NMI_OUT

IRQ7/PCI_RSTINT_OUT/APE

PORESET

HRESET

SRESET

RSTCONF

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

10

Freescale Semiconductor

DC Electrical Characteristics

1

Table 5. DC Electrical Characteristics (continued)

Characteristic Symbol

Min

Max

Unit

I

= 5.3mA

V

—

0.4

V

OL

CS[0-9]

CS(10)/BCTL1

CS(11)/AP(0)

BADDR[27–28]

ALE

BCTL0

PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LSDAMUX/LGPL5/PCI_MODCK

LWR

MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]

I

= 3.2mA

OL

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTAL_A30/REQ2

L_A31

LCL_D[0-31)]/AD[0-31]

LCL_DP[03]/C/BE[0-3]

PA[0–31]

PB[4–31]

PC[0–31]

PD[4–31]

TDO

QREQ

1

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC

current, either pull unused pins to GND or VDDH or configure them as outputs.

TCK, TRST and PORESET have min VIH = 2.5V.

2

3

The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

11

Thermal Characteristics

4

V

for IIC interface does not match IIC standard, but does meet IIC standard for V and should not cause any compatibility

OL

IL

issue.

5

MPC8280, MPC8275VR, MPC8275ZQ only.

4 Thermal Characteristics

This table describes thermal characteristics for both the packages. See Table 2 for information on a given

SoC’s package. Discussions of each characteristic are provided in Section 4.1, “Estimation with

Junction-to-Ambient Thermal Resistance,” and Section 4.5, “Experimental Determination.” For the these

discussions, P = (V × I ) + PI/O, where PI/O is the power dissipation of the I/O drivers.

D

DD

Table 6. Thermal Characteristics

Value

Characteristic

Symbol

Unit

Air Flow

480 TBGA

516 PBGA

Junction to ambient—

single-layer board

16

11

12

9

27

21

19

16

11

8

Natural convection

1

R

°C/W

θJA

1 m/s

Junction to ambient—

four-layer board

Natural convection

1 m/s

—

2

Junction to board

R

6

°C/W

θJB

3

Junction to case

2

—

θJC

4

Junction-to-package top

Ψ

2

—

JT

1

2

Assumes no thermal vias

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

3

4

4.1

Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, T_J, in C can be obtained from the following equation:

T = T + (R × P )

J

A

θJA

D

where:

T = ambient temperature (ºC)

A

R

= package junction-to-ambient thermal resistance (ºC/W)

θJA

P = power dissipation in package

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy

estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated

that errors of a factor of two (in the quantity T – T ) are possible.

J

A

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

12

Freescale Semiconductor

Thermal Characteristics

4.2

Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

R

= R

+ R

θJC θCA

θJA

where:

R

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resistance (ºC/W)

θJA

θJC

θCA

R

is device related and cannot be influenced by the user. The user adjusts the thermal environment to

θJC

affect the case-to-ambient thermal resistance, R

. For instance, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the

thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful

for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink

to the ambient environment. For most packages, a better model is required.

4.3

Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a

two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The

junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial

amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance

describes the thermal performance when most of the heat is conducted to the printed circuit board. It has

been observed that the thermal performance of most plastic packages, especially PBGA packages, is

strongly dependent on the board temperature.

If the board temperature is known, an estimate of the junction temperature in the environment can be made

using the following equation:

T = T + (R

× P )

D

J

B

θJB

where:

R

= junction-to-board thermal resistance (ºC/W)

θJB

T = board temperature (ºC)

B

P = power dissipation in package

D

If the board temperature is known and the heat loss from the package case to the air can be ignored,

acceptable predictions of junction temperature can be made. For this method to work, the board and board

mounting must be similar to the test board used to determine the junction-to-board thermal resistance,

namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground

plane.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

13

Thermal Characteristics

4.4

Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple

two-resistor model can be used with the thermal simulation of the application, or a more accurate and

complex model of the package can be used in the thermal simulation.

4.5

Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the

thermal characterization parameter (Ψ ) can be used to determine the junction temperature with a

JT

measurement of the temperature at the top center of the package case using the following equation:

T = T + (Ψ × P )

J

T

JT

D

where:

Ψ = thermal characterization parameter

JT

T = thermocouple temperature on top of package

T

P = power dissipation in package

D

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge

type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned

so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is

placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple

wire.

4.6

Layout Practices

Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies.

Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins

drive distinct groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground

using bypass capacitors located as close as possible to the four sides of the package. For filtering high

frequency noise, a capacitor of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium

frequency noise, a total of 2 capacitors of 47uF for VDD and 2 capacitors of 47uF for VDDH are also

recommended. The capacitor leads and associated printed circuit traces connecting to chip VDD, VDDH

and ground should be kept to less than half an inch per capacitor lead. Boards should employ separate inner

layers for power and GND planes.

All output pins on the SoC have fast rise and fall times. Printed circuit (PC) trace interconnection length

should be minimized to minimize overdamped conditions and reflections caused by these fast output

switching times. This recommendation particularly applies to the address and data buses. Maximum PC

trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as

well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient

currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

14

Freescale Semiconductor

Power Dissipation

5 Power Dissipation

This table provides preliminary, estimated power dissipation for various configurations. Note that suitable

thermal management is required to ensure the junction temperature does not exceed the maximum

specified value. Also note that the I/O power should be included when determining whether to use a heat

sink. For a complete list of possible clock configurations, see Section 7, “Clock Configuration Modes.”

1

Table 7. Estimated Power Dissipation for Various Configurations

2,3

P

(W)

INT

CPM

Multiplication

Factor

CPU

Multiplication

Factor

Bus

(MHz)

CPM

(MHz)

CPU

(MHz)

Vddl 1.5 Volts

Nominal

Maximum

66.67

83.33

100

2.5

3

166

200

233

250

292

300

3.5

4

233

266

300

333

375

417

400

450

0.95

1.0

1.05

1.1

4

1.05

1.25

1.3

3.5

3

4.5

4

1.15

1.35

1.4

3

4.5

5

3.5

3

1.45

1.5

1.55

1.6

4

100

3

4.5

1.55

1.65

1

2

3

Test temperature = 105° C

= I x V Watts

Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.45 W (nominal), 0.5 W (maximum)

P

INT

DD

83.3 MHz = 0.5W (nominal), 0.6 W (maximum)

100 MHz = 0.6 W (nominal), 0.7 W (maximum)

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

15

AC Electrical Characteristics

6 AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and

inputs for 66.67/83.33/100 MHz devices. Note that AC timings are based on a 50-pf load for MAX Delay

and 10-pf load for MIN delay. Typical output buffer impedances are shown in this table.

1

Table 8. Output Buffer Impedances

Output Buffers

Typical Impedance (Ω)

2

60x bus

45 or 27

Local bus

45

2

Memory controller

Parallel I/O

PCI

45 or 27

45

27

1

These are typical values at 65° C. Impedance may vary by 25% with process and

temperature.

On silicon revision 0.0 (mask #: 0K49M), selectable impedance is not available.

Impedance is set at 45 Ω.

2

On all other revisions, impedance value is selected through the SIUMCR[20,21]. See

the SoC reference manual.

6.1

CPM AC Characteristics

This table lists CPM output characteristics.

1

Table 9. AC Characteristics for CPM Outputs

Spec Number

Max Min

Characteristic Value (ns)

Maximum Delay

Minimum Delay

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp36a sp37a FCC outputs—internal clock (NMSI)

sp36b sp37b FCC outputs—external clock (NMSI)

6

8

5.5

8

5.5

8

0.5

2

0.5

2

0.5

2

sp38a sp39a SCC/SMC/SPI/I2C outputs—internal

clock (NMSI)

10

0

sp38b sp39b SCC/SMC/SPI/I2C outputs—external

clock (NMSI)

8

2

sp40

sp42

sp41 TDM outputs/SI

11

2.5

0.5

2.5

0.5

2.5

0.5

sp43 TIMER/IDMA outputs

sp42a sp43a PIO outputs

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

16

Freescale Semiconductor

AC Electrical Characteristics

This table lists CPM input characteristics.

NOTE: Rise/Fall Time on CPM Input Pins

It is recommended that the rise/fall time on CPM input pins should not

exceed 5 ns. This should be enforced especially on clock signals. Rise time

refers to signal transitions from 10% to 90% of VCC; fall time refers to

transitions from 90% to 10% of VCC.

1

Table 10. AC Characteristics for CPM Inputs

Spec Number

Setup Hold

Value (ns)

Characteristic

Setup

Hold

66 MHz

83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp16a sp17a FCC inputs—internal clock (NMSI)

sp16b sp17b FCC inputs—external clock (NMSI)

6

2.5

6

2.5

6

2.5

6

0

2

0

2

0

2

0

sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock

(NMSI)

sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock

(NMSI)

4

2

sp20

sp22

sp21 TDM inputs/SI

5

8

5

8

5

8

2.5

0.5

2.5

0.5

2.5

0.5

sp23 PIO/TIMER/IDMA inputs

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

NOTE

Although the specifications generally reference the rising edge of the clock,

the following AC timing diagrams also apply when the falling edge is the

active edge.

This figure shows the FCC internal clock.

BRG_OUT

sp17a

sp16a

FCC input signals

sp36a/sp37a

FCC output signals

Note: When GFMR[TCI] = 0

sp36a/sp37a

FCC output signals

Note: When GFMR.[TCI] = 1

Figure 3. FCC Internal Clock Diagram

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

17

AC Electrical Characteristics

This figure shows the FCC external clock.

Serial ClKin

sp17b

sp16b

FCC input signals

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 0

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 1

Figure 4. FCC External Clock Diagram

2

This figure shows the SCC/SMC/SPI/I C external clock.

Serial CLKin

sp19b

sp18b

SCC/SMC/SPI/I2C input signals

(See note)

sp38b/sp39b

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 5. SCC/SMC/SPI/I C External Clock Diagram

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

18

Freescale Semiconductor

AC Electrical Characteristics

2

This figure shows the SCC/SMC/SPI/I C internal clock.

BRG_OUT

sp19a

sp18a

SCC/SMC/SPI/I2C input signals

(See note)

sp38a/sp39a

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram

This figure shows TDM input and output signals.

Serial CLKin

sp20

sp21

TDM input signals

sp40/sp41

TDM output signals

Note: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 7. TDM Signal Diagram

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

19

AC Electrical Characteristics

This figure shows PIO and timer signals.

Sys clk

sp23

sp22

PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23

sp22

TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43

IDMA output signals

sp42/sp43

sp42a/sp43a

TIMER(sp42/43)/ PIO(sp42a/sp43a)

output signals

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure 8. PIO and Timer Signal Diagram

6.2

SIU AC Characteristics

This table lists SIU input characteristics.

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the SoC should not exceed +/– 150 psec of jitter

(peak-to-peak). This represents total input jitter—the combination of short

term (cycle-to-cycle) and long term (cumulative). The duty cycle of CLKIN

should not exceed the ratio of 40:60. The rise/file time of CLKIN should

adhere to the typical SDRAM device AC clock requirement of 1 V/ns to

meet SDRAM AC specs.

NOTE: Spread Spectrum Clocking

Spread spectrum clocking is allowed with 1% input frequency down-spread

at maximum 60 KHz modulation rate regardless of input frequency.

NOTE: PCI AC Timing

The SoC meets the timing requirements of PCI Specification Revision 2.2.

See Section 7, “Clock Configuration Modes,” and “Note: Tval (Output

Hold)” to determine if a specific clock configuration is compliant.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

20

Freescale Semiconductor

AC Electrical Characteristics

NOTE: Conditions

The following conditions must be met in order to operate the MPC8272

family devices with 133 MHz bus: single PowerQUICC II Bus mode must

be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline

mode (BRx[DR] = 1); internal arbiter and memory controller must be used.

For expected load of above 40 pF, it is recommended that data and address

buses be configured to low (25 Ω) impedance (SIUMCR[HLBE0] = 1,

SIUMCR[HLBE1] = 1).

1

Table 11. AC Characteristics for SIU Inputs

Spec Number

Setup Hold

Value (ns)

Setup

Hold

Characteristic

66

83

100

133

66

83

100

133

MHz MHz MHz MHz MHz MHz MHz MHz

sp11 sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/TEA

sp12 sp10 Data bus in normal mode

6

5

4

3.5

2.5

N/A

1.5

0.5

N/A

0.5

sp13 sp10 Data bus in pipeline mode (without ECC and

PARITY)

N/A

sp15 sp10 All other pins

5

4

3.5

N/A

0.5

N/A

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

This table lists SIU output characteristics.

1

Table 12. AC Characteristics for SIU Outputs

Spec Number

Value (ns)

Maximum Delay

Minimum Delay

Characteristic

Max

Min

66

83

100

133

66

83

100

133

MHz MHz MHz MHz MHz MHz MHz MHz

sp31 sp30 PSDVAL/TEA/TA

7

8

6

5.5

N/A

1

N/A

2

sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT

6.5

5.5

4.5

1

3

sp33 sp30 Data bus

6.5

6

4.5

N/A

0.8

1

0.8

1

0.8

1

sp34 sp30 Memory controller signals/ALE

sp35 sp30 All other signals

6

1

N/A

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

Value is for ADD only; other sp32/sp30 signals are not applicable.

2

3

To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

21

AC Electrical Characteristics

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing.

This table lists SIU input characteristics.

1

Table 13. AC Characteristics for SIU Inputs

Spec Number

Setup Hold

Value (ns)

Characteristic

Setup

Hold

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp11

sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/

6

5

3.5

0.5

TEA

sp12

sp13

sp10 Data bus in normal mode

sp10 Data bus in ECC and PARITY modes

5

7

4

5

3.5

0.5

sp13a sp10 Pipeline mode—Data bus (with or without

ECC/PARITY)

5

7

4

5

4

2.5

3.5

2.5

3.5

0.5

—

0.5

sp14

sp14a sp10 Pipeline mode—DP pins

sp15 sp10 All other pins

sp10 DP pins

—

5

0.5

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

This table lists SIU output characteristics.

1

Table 14. AC Characteristics for SIU Outputs

Spec Number

Value (ns)

Max

Min

Characteristic

Maximum Delay

Minimum Delay

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp31

sp32

sp30 PSDVAL/TEA/TA

7

8

6

5.5

7

1

sp30 ADD/ADD_atr./BADDR/CI/GBL/WT

6.5

5.5

7

2

sp33a sp30 Data bus

sp33b sp30 DP

6.5

6

0.7

1

0.7

1

0.7

1

sp34

sp35

sp30 Memory controller signals/ALE

sp30 All other signals

6

1

6

1

sp35a sp30 AP

7

1

2

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

To achieve 1 ns of hold time at 66, 83, or 100 MHz, a minimum loading of 20 pF is required.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

22

Freescale Semiconductor

AC Electrical Characteristics

This figure shows the interaction of several bus signals.

CLKin

sp10

sp11

AACK/TA/TS/

DBG/BG/BR input signals

sp11a

ARTRY/TEA input signals

sp12

sp10

DATA bus normal mode

input signal

sp15

All other input signals

sp30

sp31

sp32

PSDVAL/TEA/TA output signals

sp30

ADD/ADD_atr/BADDR/CI/

GBL/WT output signals

sp33a

sp35

DATA bus output signals

All other output signals

(except AP)

sp35a

sp30

AP signals

Figure 9. Bus Signals

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

23

AC Electrical Characteristics

This figure shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).

CLKin

sp10

sp13

DATA bus, ECC, and PARITY mode

input signals

sp10

sp13a

Pipeline mode—

DATA bus, ECC, and PARITY mode

input signals

sp10

sp14

DP mode input signal

sp14a

Pipeline mode—

DP mode input signal

sp33b

sp30

DP mode output signal

Figure 10. Parity Mode Diagram

This figure shows signal behavior in MEMC mode.

CLKin

V_CLK

sp34/sp30

Memory controller signals

Figure 11. MEMC Mode Diagram

NOTE

Generally, all SoC bus and system output signals are driven from the rising

edge of the input clock (CLKin). Memory controller signals, however,

trigger on four points within a CLKin cycle. Each cycle is divided by four

internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and

T3 at the falling edge, of CLKin. However, the spacing of T2 and T4

depends on the PLL clock ratio selected, as shown in Table 15.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

24

Freescale Semiconductor

AC Electrical Characteristics

Table 15. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

T2 T3 T4

1/4 CLKin 1/2 CLKin 3/4 CLKin

PLL Clock Ratio

1:2, 1:3, 1:4, 1:5, 1:6

1:2.5

1:3.5

3/10 CLKin

4/14 CLKin

1/2 CLKin

8/10 CLKin

11/14 CLKin

This table is a representation of the information in Table 15.

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

T1

T2

T3

T4

CLKin

for 1:2.5

T2

T4

for 1:3.5

T2

T4

Figure 12. Internal Tick Spacing for Memory Controller Signals

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC specifications are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

6.3

JTAG Timings

This table lists the JTAG timings.

1

Table 16. JTAG Timings

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

f

t

0

30

15

0

33.3

—

MHz

ns

—

JTG

JTAG external clock pulse width measured at 1.4V

JTAG external clock rise and fall times

t

—

ns

—

JTKHKL

6

t

and

5

ns

JTGR

t

JTGF

3

6

TRST assert time

Input setup times

t

25

—

ns

,

TRST

4

7

Boundary-scan data

TMS, TDI

t

4

—

ns

,

JTDVKH

JTIVKH

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

25

Clock Configuration Modes

1

Table 16. JTAG Timings (continued)

2

Parameter

Symbol

Min

Max

Unit

Notes

Input hold times

Output valid times

Output hold times

4

7

Boundary-scan data

TMS, TDI

t

10

—

ns

,

JTDXKH

JTIXKH

5

7

Boundary-scan data

TDO

t

—

10

ns

,

.

JTKLDV

JTKLOV

5

7

Boundary-scan data

TDO

t

1

—

ns

,

JTKLDX

JTKLOX

JTAG external clock to output high impedance

Boundary-scan data

TDO

5

6

t

1

10

ns

,

JTKLDZ

JTKLOZ

1

All outputs are measured from the midpoint voltage of the falling/rising edge of t

to the midpoint of the signal in question.

TCLK

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays

must be added for trace lengths, vias, and connectors in the system.

The symbols used for timing specifications herein follow the pattern of t

2

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(

for outputs. For example, t

symbolizes JTAG

(first two letters of functional block)(reference)(state)(signal)(state)

JTDVKH

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

clock reference

JTG

(K) going to the high (H) state or setup time. Also, t

symbolizes JTAG timing (JT) with respect to the time data input

JTDXKH

signals (D) went invalid (X) relative to the t

clock reference (K) going to the high (H) state. Note that, in general, the clock

JTG

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3

4

5

6

7

Non-JTAG signal input timing with respect to t

.

TCLK

Non-JTAG signal output timing with respect to t

Guaranteed by design.

.

TCLK

Guaranteed by design and device characterization.

7 Clock Configuration Modes

This SoC includes the following clocking modes:

•

Local

PCI host

PCI agent

The clocking mode is set according to the following input pins as shown in the following table:

•

PCI_MODE

PCI_CFG[0]

PCI_MODCK

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

26

Freescale Semiconductor

Clock Configuration Modes

Table 17. SoC Clocking Modes

Pins

PCI Clock

Clocking Mode

Frequency Range

(MHZ)

Reference

1

PCI_MODE PCI_CFG[0] PCI_MODCK

1

0

—

0

—

0

Local bus

PCI host

—

Table 18

Table 19

Table 20

Table 21

Table 22

50–66

25–50

50–66

25–50

0

1

0

PCI agent

1

Determines PCI clock frequency range. See Section 7.2, “PCI Host Mode,” and Section 7.3, “PCI Agent Mode.”

Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits

during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from

hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to

the selected clock operation mode as described in the following sections.

7.1

Local Bus Mode

This table lists clock configurations for the SoC in local bus mode. The frequencies listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting

configuration does not exceed the frequency rating of the user’s device.

NOTE

Clock configurations change only after PORESET is asserted.

1

Table 18. Clock Configurations for Local Bus Mode

3

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

2

CPM

Multiplication

CPU

Multiplication

Mode

4

5

Factor

MODCK_H-MODCK[1:3]

Low

High

Low

High

Low

High

Default Modes (MODCK_H= 0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

37.5

33.3

37.5

30.0

60.0

50.0

60.0

50.0

133.3

100.0

167.0

160.0

3

112.5

100.0

150.0

120.0

100.0

150.0

125.0

400.0

334.0

400.0

4

5

150.0

166.7

150.0

533.3

666.7

400.0

500.0

417.5

501.0

400.0

480.0

4

5

2

2.5

3

2

2.5

3

Full Configuration Modes

100.0

0001_000

50.0

167.0

2

334.0

4

200.0

668.0

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

27

Clock Configuration Modes

1

Table 18. Clock Configurations for Local Bus Mode (continued)

3

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

2

CPM

Multiplication

CPU

Multiplication

Mode

4

5

Factor

MODCK_H-MODCK[1:3]

Low

High

Low

High

Low

High

0001_001

0001_010

0001_011

0001_100

50.0

167.0

145.8

2

100.0

334.0

291.7

5

6

250.0

300.0

835.0

875.0

Reserved

0001_101

0001_110

1000_111

0001_111

0010_000

0010_001

37.5

33.3

133.3

3

112.5

400.0

4

5

150.0

166.7

183.3

200.0

533.3

666.7

733.3

800.0

100.0

5.5

6

Reserved

0010_010

0010_011

0010_100

0010_101

0010_110

37.5

30.0

25.0

100.0

4

150.0

400.0

4

5

6

7

8

150.0

175.0

200.0

400.0

500.0

600.0

700.0

800.0

120.0

100.0

0010_111

0011_000

0011_001

0011_010

0011_011

Reserved

30.0

25.0

80.0

5

150.0

125.0

400.0

5

6

7

8

150.0

175.0

200.0

400.0

480.0

560.0

640.0

0011_100

0011_101

0011_110

0011_111

0100_000

Reserved

25.0

66.7

6

150.0

400.0

6

7

8

150.0

175.0

200.0

400.0

466.7

533.3

150.0

0101_101

0101_110

0101_111

75.0

60.0

50.0

167.0

2

150.0

120.0

100.0

334.0

2

2.5

3

166.7

200.0

334.0

417.5

501.0

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

28

Freescale Semiconductor

Clock Configuration Modes

1

Table 18. Clock Configurations for Local Bus Mode (continued)

3

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

2

CPM

Multiplication

CPU

Multiplication

Mode

4

5

Factor

MODCK_H-MODCK[1:3]

Low

High

Low

High

Low

High

0110_000

0110_001

0110_010

50.0

167.0

2

100.0

334.0

3.5

4

250.0

584.5

668.0

751.5

4.5

0110_011

0110_100

0110_101

0110_110

0110_111

0111_000

Reserved

60.0

50.0

42.9

40.0

160.0

2.5

150.0

125.0

107.1

100.0

400.0

2.5

3

150.0

160.0

180.0

400.0

480.0

560.0

640.0

720.0

3.5

4

4.5

0111_001

0111_010

0111_011

0111_100

0111_101

0111_110

0111_111

Reserved

50.0

42.9

37.5

33.3

133.3

3

150.0

400.0

3

3.5

4

150.0

400.0

466.7

533.3

600.0

128.6

112.5

100.0

4.5

Reserved

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

42.9

37.5

33.3

30.0

28.6

114.3

3.5

150.0

400.0

3.5

4

150.0

400.0

457.1

514.3

571.4

628.6

131.3

116.7

105.0

100.0

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1101_000

Reserved

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

29

Clock Configuration Modes

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry

guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only.

Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of

the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For

modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices

and 175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev0.1 the minimum

CPU frequency is 250 MHz; for Rev A or later the minimum CPU frequency is 150 MHz for commercial temperature devices

and 175 MHz for extended temperature devices.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

60x and local bus frequency. Identical to CLKIN.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

2

3

4

5

7.2

PCI Host Mode

These tables show clock configurations for PCI host mode. The frequency values listed are for the purpose

of illustration only. Users must select a mode and input bus frequency so that the resulting configuration

does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the

following:

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum

Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock

configurations that fit this condition to achieve PCI-compliant AC timing.

1,2

Table 19. Clock Configurations for PCI Host Mode (PCI_MODCK=0)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 66.7

50.0 66.7

60.0 80.0

50.0 66.7

2

120.0 133.3

100.0 133.3

150.0 200.0

2.5

3

150.0 166.7

150.0 200.0

180.0 240.0

210.0 280.0

240.0 320.0

150.0 200.0

175.0 233.3

200.0 266.6

2

3

60.0 66.7

50.0 66.7

2.5

3

3.5

4

3

3.5

3

3.5

4

Full Configuration Modes

150.0 200.0

0001_000

50.0 66.7

3

5

250.0 333.3

3

50.0 66.7

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

30

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 19. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (continued)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

0001_001

0001_010

0001_011

50.0 66.7

3

150.0 200.0

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

3

50.0 66.7

0010_000

0010_001

0010_010

0010_011

50.0 66.7

4

200.0 266.6

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

4

50.0 66.7

0010_100

0010_101

0010_110

75.0 100.0

4

300.0 400.0

5

5.5

6

375.0 500.0

412.5 549.9

450.0 599.9

6

50.0 66.7

0011_000

0011_001

0011_010

0011_011

50.0 66.7

5

250.0 333.3

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

5

50.0 66.7

0100_000

0100_001

0100_010

0100_011

Reserved

50.0 66.7

6

300.0 400.0

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

6

50.0 66.7

0101_000

0101_001

0101_010

0101_011

0101_100

60.0 66.7

50.0 66.7

2

120.0 133.3

100.0 133.3

2.5

3

150.0 166.7

150.0 200.0

175.0 233.3

200.0 266.6

225.0 300.0

2

60.0 66.7

50.0 66.7

3.5

4

4.5

0110_000

0110_001

0110_010

60.0 80.0

2.5

150.0 200.0

2.5

3

150.0 200.0

180.0 240.0

210.0 280.0

3

50.0 66.7

3.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

31

Clock Configuration Modes

1,2

Table 19. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (continued)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

0110_011

0110_100

0110_101

0110_110

60.0 80.0

2.5

150.0 200.0

4

4.5

5

240.0 320.0

270.0 360.0

300.0 400.0

360.0 480.0

3

50.0 66.7

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

50.0 66.7

3

150.0 200.0

3

3.5

4

150.0 200.0

175.0 233.3

200.0 266.6

225.0 300.0

3

50.0 66.7

4.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

66.7 88.9

3

200.0 266.6

3

3.5

4

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

400.0 533.3

433.3 577.7

4

50.0 66.7

4.5

6

6.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

57.1 76.2

3.5

200.0 266.6

3.5

4

200.0 266.6

228.6 304.7

257.1 342.8

4

50.0 66.7

4.5

1001_101

1001_110

1001_111

85.7 114.3

3.5

300.0 400.0

5

5.5

6

428.6 571.4

471.4 628.5

514.3 685.6

6

50.0 66.7

1010_000

1010_001

1010_010

75.0 100.0

2

150.0 200.0

2

2.5

3

150.0 200.0

187.5 250.0

225.0 300.0

3

50.0 66.7

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

32

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 19. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (continued)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1010_011

1010_100

75.0 100.0

2

150.0 200.0

3.5

4

262.5 350.0

300.0 400.0

3

50.0 66.7

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

Reserved

80.0 106.7

2.5

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

360.0 480.0

4

50.0 66.7

3.5

4

4.5

1101_000

1101_001

1101_010

1101_011

1101_100

100.0 133.3

2.5

250.0 333.3

3

3.5

4

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

5

50.0 66.7

4.5

5

1101_101

1101_110

125.0 166.7

2

250.0 333.3

3

4

375.0 500.0

500.0 666.6

5

50.0 66.7

1110_000

1110_001

1110_010

1110_011

1110_100

100.0 133.3

3

300.0 400.0

3.5

4

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

6

50.0 66.7

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

33

Clock Configuration Modes

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry

guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only.

Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of

the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For

modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices

and 175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev0.1 the minimum

CPU frequency is 250 MHz; for Rev A or later the minimum CPU frequency is 150 MHz for commercial temperature devices

and 175 MHz for extended temperature devices.

As Table 17 shows, PCI_MODCK determines the PCI clock frequency range. See Table 20 for lower configurations.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

60x and local bus frequency. Identical to CLKIN.

CPM multiplication factor = CPM clock/bus clock

2

3

4

5

6

CPU multiplication factor = Core PLL multiplication factor

1,2

Table 20. Clock Configurations for PCI Host Mode (PCI_MODCK=1)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 100.0

50.0 100.0

60.0 120.0

50.0 100.0

2

120.0 200.0

100.0 200.0

150.0 300.0

2.5

3

150.0 250.0

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

150.0 300.0

175.0 350.0

200.0 400.0

4

6

30.0 50.0

25.0 50.0

2.5

3

3.5

4

3

3.5

4

3

Full Configuration Modes

0001_000

0001_001

0001_010

0001_011

50.0 100.0

3

150.0 300.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

6

25.0 50.0

0010_000

0010_001

0010_010

0010_011

50.0 100.0

4

200.0 400.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

8

25.0 50.0

0010_100

0010_101

37.5 75.0

4

150.0 300.0

5

187.5 375.0

206.3 412.5

6

25.0 50.0

5.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

34

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 20. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (continued)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

0010_110

37.5 75.0

4

150.0 300.0

6

225.0 450.0

6

25.0 50.0

0011_000

0011_001

0011_010

0011_011

30.0 50.0

25.0 50.0

5

150.0 250.0

125.0 250.0

5

6

7

8

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

5

30.0 50.0

25.0 50.0

0100_000

0100_001

0100_010

0100_011

Reserved

25.0 50.0

6

150.0 300.0

6

7

8

150.0 300.0

175.0 350.0

200.0 400.0

6

25.0 50.0

0101_000

0101_001

0101_010

0101_011

0101_100

60.0 100.0

50.0 100.0

2

120.0 200.0

100.0 200.0

2.5

3

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

4

30.0 50.0

25.0 50.0

3.5

4

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 120.0

2.5

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

300.0 600.0

360.0 720.0

6

25.0 50.0

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

50.0 100.0

3

150.0 300.0

3

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

6

25.0 50.0

3.5

4

4.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

35

Clock Configuration Modes

1,2

Table 20. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (continued)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

66.7 133.3

3

200.0 400.0

3

3.5

4

200.0 400.0

233.3 466.7

266.7 533.3

300.0 600.0

400.0 800.0

433.3 866.7

8

25.0 50.0

4.5

6

6.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

57.1 114.3

3.5

200.0 400.0

3.5

4

200.0 400.0

228.6 457.1

257.1 514.3

8

25.0 50.0

4.5

1001_101

1001_110

1001_111

42.9 85.7

3.5

150.0 300.0

5

5.5

6

214.3 428.6

235.7 471.4

257.1 514.3

6

25.0 50.0

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 150.0

2

150.0 300.0

2

2.5

3

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

300.0 600.0

6

25.0 50.0

3.5

4

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

Reserved

80.0 160.0

2.5

200.0 400.0

2.5

3

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

360.0 720.0

8

25.0 50.0

3.5

4

4.5

1101_000

50.0 100.0

2.5

125.0 250.0

3

150.0 300.0

5

25.0 50.0

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

36

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 20. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (continued)

4

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1101_001

1101_010

1101_011

1101_100

50.0 100.0

2.5

125.0 250.0

3.5

4

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

5

25.0 50.0

4.5

5

1101_101

1101_110

62.5 125.0

2

125.0 250.0

3

4

187.5 375.0

250.0 500.0

5

25.0 50.0

1110_000

1110_001

1110_010

1110_011

1110_100

50.0 100.0

3

150.0 300.0

3.5

4

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

275.0 550.0

6

25.0 50.0

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry

guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only.

Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of

the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For

modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices and

175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev0.1 the minimum CPU

frequency is 250 MHz; for Rev A or later the minimum CPU frequency is 150 MHz for commercial temperature devices and 175

MHz for extended temperature devices.

2

3

4

5

6

As Table 17 shows, PCI_MODCK determines the PCI clock frequency range. See Table 20 for higher configurations.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

60x and local bus frequency. Identical to CLKIN.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

7.3

PCI Agent Mode

These tables show configurations for PCI agent mode. The frequency values listed are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does

not exceed the frequency rating of the user’s device. Note that in PCI agent mode the following:

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

37

Clock Configuration Modes

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum

Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock

configurations that fit this condition to achieve PCI-compliant AC timing.

1,2

Table 21. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 66.7

50.0 66.7

2

3

4

120.0 133.3

100.0 133.3

150.0 200.0

200.0 266.6

2.5

3

150.0 166.7

150.0 200.0

200.0 266.6

180.0 240.0

210.0 280.0

233.3 311.1

240.0 320.0

2

60.0 66.7

50.0 66.7

60.0 80.0

66.7 88.9

80.0 106.7

3

4

3

2.5

3

3.5

3

2.5

Full Configuration Modes

0001_001

0001_010

0001_011

0001_100

60.0 66.7

50.0 66.7

2

120.0 133.3

100.0 133.3

5

6

7

8

150.0 166.7

150.0 200.0

175.0 233.3

200.0 266.6

4

30.0 33.3

25.0 33.3

0010_001

0010_010

0010_011

0010_100

50.0 66.7

3

150.0 200.0

3

3.5

4

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

2.5

60.0 80.0

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

38

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 21. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0100_000

0100_001

0100_010

0100_011

0100_100

Reserved

50.0 66.7

3

150.0 200.0

3

3.5

4

150.0 200.0

175.0 200.0

200.0 266.6

225.0 300.0

3

50.0 66.7

4.5

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

50.0 66.7

5

250.0 333.3

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

2.5

100.0 133.3

3.5

4

4.5

5

5.5

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

50.0 66.7

4

200.0 266.6

3

3.5

4

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

4.5

0111_000

0111_001

0111_010

0111_011

50.0 66.7

3

150.0 200.0

2

2.5

3

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

2

75.0 100.0

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

50.0 66.7

3

150.0 200.0

2.5

3

150.0 166.7

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

2.5

60.0 80.0

3.5

4

4.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

39

Clock Configuration Modes

1,2

Table 21. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

4

50.0 66.7

4

200.0 266.6

225.0 300.0

4

50.0 66.7

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

50.0 66.7

4

200.0 266.6

3

3.5

4

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

4.5

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

50.0 66.7

4

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

2.5

80.0 106.7

3.5

4

1100_101

1100_110

1100_111

1101_000

50.0 66.7

6

300.0 400.0

4

4.5

5

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

3

100.0 133.3

5.5

1101_001

1101_010

1101_011

1101_100

50.0 66.7

6

300.0 400.0

3.5

4

420.0 559.9

480.0 639.9

540.0 719.9

600.0 799.9

2.5

120.0 160.0

4.5

5

1110_000

1110_001

1110_010

50.0 66.7

5

250.0 333.3

2.5

3

312.5 416.6

375.0 500.0

437.5 583.3

2

125.0 166.7

3.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

40

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 21. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1110_011

50.0 66.7

5

250.0 333.3

4

500.0 666.6

2

125.0 166.7

1110_100

1110_101

1110_110

1110_111

50.0 66.7

5

250.0 333.3

4

4.5

5

333.3 444.4

375.0 500.0

416.7 555.5

458.3 611.1

3

83.3 111.1

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry

guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users

must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user’s

device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For modes with

a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz

for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev 0.1 the minimum CPU frequency

is 250 MHz; for Rev A or later the minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for

extended temperature devices.

2

3

4

5

As shown in Table 17, PCI_MODCK determines the PCI clock frequency range. See Table 20 for lower configurations.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

CPM multiplication factor = CPM clock/PCI clock

CPU multiplication factor = Core PLL multiplication factor

1,2

Table 22. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

30.0 50.0

25.0 50.0

4

6

8

120.0 200.0

100.0 200.0

150.0 300.0

200.0 400.0

2.5

3

150.0 250.0

150.0 300.0

200.0 400.0

180.0 360.0

210.0 420.0

233.3 466.7

2

60.0 100.0

50.0 100.0

60.0 120.0

66.7 133.3

3

4

3

2.5

3

3.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

41

Clock Configuration Modes

1,2

Table 22. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0000_111

25.0 50.0

8

200.0 400.0

3

240.0 480.0

2.5

80.0 160.0

Full Configuration Modes

0001_001

0001_010

0001_011

0001_100

30.0 50.0

25.0 50.0

4

120.0 200.0

100.0 200.0

5

6

7

8

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

4

30.0 50.0

25.0 50.0

0010_001

0010_010

0010_011

0010_100

25.0 50.0

6

150.0 300.0

3

3.5

4

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

2.5

60.0 120.0

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

37.5 50.0

32.1 50.0

28.1 50.0

25.0 50.0

4

150.0 200.0

128.6 200.0

112.5 200.0

100.0 200.0

3

3.5

4

150.0 200.0

150.0 233.3

150.0 266.7

150.0 300.0

3

50.0 66.7

42.9 66.7

37.5 66.7

33.3 66.7

4.5

0100_000

0100_001

0100_010

0100_011

0100_100

Reserved

25.0 50.0

6

150.0 300.0

3

3.5

4

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

3

50.0 100.0

4.5

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

30.0 50.0

25.0 50.0

5

150.0 250.0

125.0 250.0

2.5

3

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

275.0 550.0

2.5

60.0 100.0

50.0 100.0

3.5

4

4.5

5

5.5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

42

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 22. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

25.0 50.0

8

200.0 400.0

3

3.5

4

200.0 400.0

233.3 466.7

266.7 533.3

300.0 600.0

3

66.7 133.3

4.5

0111_000

0111_001

0111_010

0111_011

25.0 50.0

6

150.0 300.0

2

2.5

3

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

2

75.0 150.0

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

25.0 50.0

6

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

2.5

60.0 120.0

3.5

4

4.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

4

25.0 50.0

8

200.0 400.0

225.0 450.0

4

50.0 100.0

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

25.0 50.0

8

200.0 400.0

3

3.5

4

200.0 400.0

233.3 466.7

266.7 533.3

300.0 600.0

3

66.7 133.3

4.5

1011_000

1011_001

Reserved

2.5

25.0 50.0

8

200.0 400.0

2.5

80.0 160.0

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

43

Clock Configuration Modes

1,2

Table 22. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

Multiplication

CPU

Multiplication

Bus

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1011_010

1011_011

1011_100

25.0 50.0

8

200.0 400.0

3

3.5

4

240.0 480.0

280.0 560.0

320.0 640.0

2.5

80.0 160.0

1100_101

1100_110

1100_111

1101_000

25.0 50.0

6

150.0 300.0

4

4.5

5

200.0 400.0

225.0 450.0

250.0 500.0

275.0 550.0

3

50.0 100.0

5.5

1101_001

1101_010

1101_011

1101_100

25.0 50.0

6

150.0 300.0

3.5

4

210.0 420.0

240.0 480.0

270.0 540.0

300.0 600.0

2.5

60.0 120.0

4.5

5

1110_000

1110_001

1110_010

1110_011

25.0 50.0

5

125.0 250.0

2.5

3

156.3 312.5

187.5 375.0

218.8 437.5

250.0 500.0

2

62.5 125.0

3.5

4

1110_100

1110_101

1110_110

1110_111

25.0 50.0

5

125.0 250.0

4

4.5

5

166.7 333.3

187.5 375.0

208.3 416.7

229.2 458.3

3

41.7 83.3

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry

guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only.

Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of

the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For

modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices

and 175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev 0.1 the minimum

CPU frequency is 250 MHz; for Rev A or later the minimum CPU frequency is 150 MHz for commercial temperature devices

and 175 MHz for extended temperature devices.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

44

Freescale Semiconductor

Pinout

2

3

4

5

As shown in Table 17, PCI_MODCK determines the PCI clock range. See Table 20 for higher range configurations.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

CPM multiplication factor = CPM clock/PCI clock

CPU multiplication factor = Core PLL multiplication factor

8 Pinout

This section provides the pin assignments and pinout lists for both HiP7 PowerQUICC II packages.

8.1

ZU and VV Packages—MPC8280 and MPC8270

The following figures and table represent the standard 480 TBGA package. For information on the

alternate package, see Section 8.2, “VR and ZQ Packages—MPC8275 and MPC8270.”

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

45

Pinout

This figure shows the pinout of the ZU and VV packages as viewed from the top surface.

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

A

B

A

B

C

D

E

F

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AA

AB

AC

AD

AE

AF

AG

AH

AJ

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Not to Scale

Figure 13. Pinout of the 480 TBGA Package (View from Top)

This table lists the pins of the MPC8280 and MPC8270, and Table 24 defines conventions and acronyms

used in this table.

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

BR

BG

W5

F4

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

46

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

ABB/IRQ2

TS

E2

E3

G1

H5

H2

H1

J5

A0

A1

A2

A3

A4

A5

J4

A6

J3

A7

J2

A8

J1

A9

K4

K3

K2

K1

L5

L4

L3

L2

L1

M5

N5

N4

N3

N2

N1

P4

P3

P2

P1

R1

R3

R5

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

47

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

A31

TT0

TT1

TT2

TT3

TT4

TBST

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

ARTRY

DBG

DBB/IRQ3

D0

R4

F1

G4

G3

G2

F2

D3

C1

E4

D2

F5

F3

E1

V1

V2

B20

A18

A16

A13

E12

D9

D1

D2

D3

D4

D5

D6

A6

D7

B5

D8

A20

E17

B15

B13

A11

E9

D9

D10

D11

D12

D13

D14

D15

D16

D17

B7

B4

D19

D17

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

48

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D15

C13

B11

A8

A5

C5

C19

C17

C15

D13

C11

B8

A4

E6

E18

B17

A15

A12

D11

C8

E7

A3

D18

A17

A14

B12

A10

D8

B6

C4

C18

E16

B14

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

49

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

D51

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

C12

B10

A7

C6

D5

B18

B16

E14

D12

C10

E8

D6

C2

DP0/RSRV/EXT_BR2

IRQ1/DP1/EXT_BG2

IRQ2/DP2/TLBISYNC/EXT_DBG2

IRQ3/DP3/CKSTP_OUT/EXT_BR3

IRQ4/DP4/CORE_SRESET/EXT_BG3

IRQ5/CINT/DP5/TBEN/EXT_DBG3

IRQ6/DP6/CSE0

IRQ7/DP7/CSE1

PSDVAL

B22

A22

E21

D21

C21

B21

A21

E20

V3

TA

C22

V5

TEA

GBL/IRQ1

W1

U2

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

U3

Y4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

U4

R2

CPU_BR

Y3

CS0

F25

C29

CS1

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

50

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

E27

E28

F26

F27

F28

G25

D29

E29

F29

G28

T5

CS10/BCTL1

CS11/AP0

BADDR27

BADDR28

U1

ALE

T2

BCTL0

A27

C25

E24

D24

C24

B26

A26

B25

A25

E23

B24

A24

B23

A23

D22

H28

H27

H26

G29

D27

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

LWE0/LSDDQM0/LBS0/PCI_CFG0

LWE1/LSDDQM1/LBS1/PCI_CFG1

LWE2/LSDDQM2/LBS2/PCI_CFG2

LWE3/LSDDQM3/LBS3/PCI_CFG3

LSDA10/LGPL0/PCI_MODCKH0

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

51

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LGPL5/LSDAMUX/PCI_MODCK

LWR

C28

E26

D25

C26

B27

D28

N27

T29

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

R27

R26

R29

R28

W29

P28

N26

AA27

P29

AA26

N25

AA25

AB29

AB28

P25

AB27

H29

J29

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTA

L_A30/REQ2

L_A31/DLLOUT

LCL_D0/AD0

LCL_D1/AD1

LCL_D2/AD2

J28

LCL_D3/AD3

J27

LCL_D4/AD4

J26

LCL_D5/AD5

J25

LCL_D6/AD6

K25

L29

LCL_D7/AD7

LCL_D8/AD8

L27

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

52

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

LCL_D9/AD9

MPC8280 only

L26

L25

LCL_D10/AD10

LCL_D11/AD11

LCL_D12/AD12

LCL_D13/AD13

LCL_D14/AD14

LCL_D15/AD15

LCL_D16/AD16

LCL_D17/AD17

LCL_D18/AD18

LCL_D19/AD19

LCL_D20/AD20

LCL_D21/AD21

LCL_D22/AD22

LCL_D23/AD23

LCL_D24/AD24

LCL_D25/AD25

LCL_D26/AD26

LCL_D27/AD27

LCL_D28/AD28

LCL_D29/AD29

LCL_D30/AD30

LCL_D31/AD31

LCL_DP0/C0/BE0

LCL_DP1/C1/BE1

LCL_DP2/C2/BE2

LCL_DP3/C3/BE3

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

M29

M28

M27

M26

N29

T25

U27

U26

U25

V29

V28

V27

V26

W27

W26

W25

Y29

Y28

Y25

AA29

AA28

L28

N28

T28

W28

T1

D1

1

TRST

AH3

AG5

AJ3

AE6

TCK

TMS

TDI

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

53

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

TDO

AF5

AB4

AG6

AH5

AF6

AA3

AJ4

TRIS

1

PORESET

HRESET

SRESET

QREQ

RSTCONF

MODCK1/AP1/TC0/BNKSEL0

MODCK2/AP2/TC1/BNKSEL1

MODCK3/AP3/TC2/BNKSEL2

CLKIN1

W2

W3

W4

AH4

AC29

AC25

AE28

2

PA0/RESTART1/DREQ3

PA1/REJECT1/DONE3

PA2/CLK20/DACK3

FCC2_UTM_TXADDR2

FCC2_UTM_TXADDR1

FCC2_UTM_TXADDR0

FCC2_UTM_RXADDR0

FCC2_UTM_RXADDR1

PA3/CLK19/DACK4/L1RXD1A2

PA4/REJECT2/DONE4

PA5/RESTART2/DREQ4

AG29

AG28

AG26

2

FCC2_UTM_RXADDR2/FCC1_UT_RXPRT

Y

2

PA6/FCC2_RXADDR3

PA7/SMSYN2/FCC2_TXADDR3

PA8/SMRXD2/FCC2_TXADDR4

PA9/SMTXD2

L1RSYNCA1

AE24

AH25

L1TSYNCA1/L1GNTA1

L1RXD0A1/L1RXDA1

2

AF23

AH23

AE22

AH22

2

L1TXD0A1

PA10/MSNUM5

FCC1_UT8_RXD0/FCC1_UT16_RXD8

FCC1_UT8_RXD1/FCC1_UT16_RXD9

PA11/MSNUM4

2

PA12/MSNUM3

FCC1_UT8_RXD2/

FCC1_UT16_RXD10

AJ21

2

PA13/MSNUM2

FCC1_UT8_RXD3/

FCC1_UT16_RXD11

AH20

AG19

2

PA14/FCC1_MII_HDLC_RXD3

PA15/FCC1_MII_HDLC_RXD2

FCC1_UT8_RXD4/

FCC1_UT16_RXD12

2

FCC1_UT8_RXD5/

FCC1_UT16_RXD13

AF18

AF17

PA16/FCC1_MII_HDLC_RXD1/

FCCI_RMII_RXD1

FCC1_UT8_RXD6/

FCC1_UT16_RXD14

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

54

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

FCC1_UT8_RXD7/

2

PA17/FCC1_MII_HDLC_RXD0/

FCC1_MII_TRAN_RXD/

FCCI_RMII_RXD0

AE16

FCC1_UT16_RXD15

2

PA18/FCC1_MII_HDLC_TXD0/

FCC1_MII_TRAN_TXD/

FCC1_RMII_TXD0

FCC1_UT8_TXD7/FCC1_UT16_TXD15

AJ16

2

PA19/FCC1_MII_HDLC_TXD1/

FCC1_RMII_TXD1

FCC1_UT8_TXD6/FCC1_UT16_TXD14

AG15

2

PA20/FCC1_MII_HDLC_TXD2

PA21/FCC1_MII_HDLC_TXD3

PA22

FCC1_UT8_TXD5/FCC1_UT16_TXD13

FCC1_UT8_TXD4/FCC1_UT16_TXD12

FCC1_UT8_TXD3/FCC1_UT16_TXD11

FCC1_UT8_TXD2/FCC1_UT16_TXD10

FCC1_UT8_TXD1/FCC1_UT16_TXD9

FCC1_UT8_TXD0/FCC1_UT16_TXD8

AJ13

AE13

AF12

2

PA23

AG11

2

PA24/MSNUM1

AH9

2

PA25/MSNUM0

AJ8

2

PA26/FCC1_RMII_RX_ER

FCC1_UTM_RXCLAV/

FCC1_UTS_RXCLAV

AH7

2

PA27/FCC1_MII_RX_DV/

FCC1_RMII_CRS_DV

FCC1_UT_RXSOC

AF7

PA28/FCC1_MII_TX_EN/

FCC1_RMII_TX_EN

FCC1_UTM_RXENB/

FCC1_UTS_RXENB

AD5

2

PA29/FCC1_MII_TX_ER

FCC1_UT_TXSOC

AF1

AD3

2

PA30/FCC1_MII_CRS/FCC1_RTS

FCC1_UTM_TXCLAV/

FCC1_UTS_TXCLAV

PA31/FCC1_MII_COL

FCC1_UTM_TXENB/

FCC1_UTS_TXENB

AB5

2

PB4/FCC3_MII_HDLC_TXD3/

L1RSYNCA2/FCC3_RTS

FCC2_UT8_RXD0

FCC2_UT8_RXD1

FCC2_UT8_RXD2

AD28

AD26

AD25

PB5/FCC3_MII_HDLC_TXD2/

L1TSYNCA2/L1GNTA2

PB6/FCC3_MII_HDLC_TXD1/

FCC3_RMII_TXD1/

L1RXDA2/L1RXD0A2

2

PB7/FCC3_MII_HDLC_TXD0/

FCC3_RMII_TXD0/

FCC3_TXD/L1TXDA2/L1TXD0A2

FCC2_UT8_RXD3

AE26

PB8/FCC3_MII_HDLC_RXD0/

FCC3_RMII_RXD0/

FCC3_RXD/TXD3

FCC2_UT8_TXD3/L1RSYNCD1

AH27

PB9/FCC3_MII_HDLC_RXD1/

FCC3_RMII_RXD1/L1TXD2A2

FCC2_UT8_TXD2/L1TSYNCD1/

L1GNTD1

AG24

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

55

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

2

PB10/FCC3_MII_HDLC_RXD2

PB11/FCC3_MII_HDLC_RXD3

PB12/FCC3_MII_CRS/TXD2

FCC2_UT8_TXD1/L1RXDD1

FCC2_UT8_TXD0/L1TXDD1

L1CLKOB1/L1RSYNCC1

L1RQB1/L1TSYNCC1/L1GNTC1

L1RXDC1

AH24

2

AJ24

2

AG22

AH21

AG20

PB13/FCC3_MII_COL/L1TXD1A2

PB14/FCC3_MII_RMII_TX_EN//RXD3

PB15/FCC3_MII_TX_ER/RXD2

PB16/FCC3_MII_RMII_RX_ER/CLK18

2

L1TXDC1

AF19

2

L1CLKOA1

AJ18

AJ17

2

PB17/FCC3_MII_RX_DV/CLK17/

FCC3_RMII_CRS_DV

L1RQA1

2

PB18/FCC2_MII_HDLC_RXD3/

L1CLKOD2/L1RXD2A2

FCC2_UT8_RXD4

AE14

AF13

2

PB19FCC2_MII_HDLC_RXD2/

L1RQD2/L1RXD3A2

FCC2_UT8_RXD5

PB20/FCC2_MII_HDLC_RMII_RXD1/

L1RSYNCD2

FCC2_UT8_RXD6/L1TXD1A1

FCC2_UT8_RXD7/L1TXD2A1

AG12

2

PB21//FCC2_MII_HDLC_RMII_RXD0/

FCC2_TRAN_RXD/L1TSYNCD2/

L1GNTD2

AH11

PB22/FCC2_MII_HDLC_TXD0/

FCC2_TXD/FCC2_RMII_TXD0/

L1RXDD2

FCC2_UT8_TXD7/L1RXD1A1

FCC2_UT8_TXD6/L1RXD2A1

AH16

2

PB23/FCC2_MII_HDLC_TXD1/

L1RXD2A1/L1TXDD2/

FCC2_RMII_TXD1

AE15

2

PB24/FCC2_MII_HDLC_TXD2/

L1RSYNCC2

FCC2_UT8_TXD5/L1RXD3A1

FCC2_UT8_TXD4/L1TXD3A1

AJ9

PB25/FCC2_MII_HDLC_TXD3/

L1TSYNCC2/L1GNTC2

AE9

2

PB26/FCC2_MII_CRS/L1RXDC2

PB27/FCC2_MII_COL/L1TXDC2

FCC2_UT8_TXD1

FCC2_UT8_TXD0

AJ7

AH6

AE3

2

PB28/FCC2_MII_RX_ER/

FCC2_RMII_RX_ER/FCC2_RTS/

L1TSYNCB2/L1GNTB2/TXD1

2

PB29/L1RSYNCB2/FCC2_MII_TX_EN/

FCC2_RMII_TX_EN

FCC2_UTM_RXCLAV/

FCC2_UTS_RXCLAV

AE2

AC5

AC4

PB30/FCC2_MII_RX_DV/

FCC2_RMII_CRS_DV/L1RXDB2

FCC2_UT_TXSOC

PB31/FCC2_MII_TX_ER/L1TXDB2

FCC2_UT_RXSOC

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

56

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

2

PC0/DREQ1/BRGO7/SMSYN2/

L1CLKOA2

AB26

2

PC1/DREQ2/BRGO6/L1RQA2/ SPISEL

PC2/FCC3_CD/DONE2

AD29

AE29

AE27

FCC2_UT8_TXD3

PC3/FCC3_CTS/DACK2/CTS4/

USB_RP

FCC2_UT8_TXD2

2

PC4/SI2_L1ST4/FCC2_CD

PC5/SI2_L1ST3/FCC2_CTS

PC6/FCC1_CD

FCC2_UTM_RXENB/

FCC2_UTS_RXENB

AF27

AF24

FCC2_UTM_TXCLAV/

FCC2_UTS_TXCLAV

2

L1CLKOC1/FCC1_UTM_RXADDR2/

FCC1_UTS_RXADDR2/

FCC1_UTM_RXCLAV1

AJ26

AJ25

PC7/FCC1_CTS

L1RQC1/FCC1_UTM_TXADDR2/

FCC1_UTS_TXADDR2/

FCC1_UTM_TXCLAV1

PC8/CD4/RENA4/SI2_L1ST2/CTS3/

USBRN

FCC1_UT16_TXD0

AF22

AE21

AF20

2

PC9/CTS4/CLSN4/SI2_L1ST1/

L1TSYNCA2/L1GNTA2/USB_RP

FCC1_UT16_TXD1

PC10/CD3/RENA3

FCC1_UT16_TXD2/SI1_L1ST4/

FCC2_UT8_RXD3

2

PC11/CTS3/CLSN3/L1TXD3A2

PC12/CD2/RENA2

L1CLKOD1/FCC2_UT8_RXD2

AE19

AE18

SI1_L1ST3/FCC1_UTM_RXADDR1/

FCC1_UTS_RXADDR1

2

PC13/CTS2/CLSN2

L1RQD1/FCC1_UTM_TXADDR1/

FCC1_UTS_TXADDR1

AH18

AH17

AG16

2

PC14/CD1/RENA1

FCC1_UTM_RXADDR0/

FCC1_UTS_RXADDR0

PC15/CTS1/CLSN1/SMTXD2

FCC1_UTM_TXADDR0/

FCC1_UTS_TXADDR0

2

PC16/CLK16/TIN4

AF15

2

PC17/CLK15/TIN3/BRGO8

PC18/CLK14/TGATE2

AJ15

2

AH14

AG13

AH12

2

PC19/CLK13/BRGO7/SPICLK

PC20/CLK12/TGATE1/USB_OE

PC21/CLK11/BRGO6

2

AJ11

2

PC22/CLK10/DONE1/FCC1_UT_TXPRTY

PC23/CLK9/BRGO5/DACK1

AG10

2

AE10

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

57

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

FCC2_UT8_TXD3

FCC2_UT8_TXD2

2

PC24/CLK8/TOUT4

AF9

AE8

PC25/CLK7/BRGO4

2

PC26/CLK6/TOUT3/TMCLK

AJ6

2

PC27/FCC3_TXD/FCC3_MII_TXD0/

FCC3_RMII_TXD0/CLK5/BRGO3

AG2

2

PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2/

FCC2_RXADDR4

AF3

2

PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1

PC30/CLK2/TOUT1

AF2

AE1

FCC2_UT8_TXD3

PC31/CLK1/BRGO1

AD1

AC28

AD27

2

PD4/BRGO8/FCC3_RTS/SMRXD2

PD5/DONE1

L1TSYNCD1/L1GNTD1

FCC1_UT16_TXD3

FCC1_UT16_TXD4

2

PD6/DACK1

AF29

AF28

2

PD7/SMSYN1/FCC1_TXCLAV2

FCC1_UTM_TXADDR3/

FCC1_UTS_TXADDR3/

FCC2_UTM_TXADDR4

FCC2_UTS_TXADDR1

2

PD8/SMRXD1/BRGO5

PD9/SMTXD1/BRGO3

PD10/L1CLKOB2/BRGO4

PD11/L1RQB2

FCC2_UT_TXPRTY

AG25

AH26

2

FCC2_UT_RXPRTY

2

FCC2_UT8_RXD1/L1RSYNCB1

AJ27

AJ23

FCC2_UT8_RXD0/L1TSYNCB1/

L1GNTB1

2

PD12

SI1_L1ST2/L1RXDB1

SI1_L1ST1/L1TXDB1

FCC1_UT16_RXD0

FCC1_UT16_RXD1

AG23

2

PD13

AJ22

AE20

PD14/L1CLKOC2/I2CSCL

PD15/L1RQC2/I2CSDA

PD16/SPIMISO

2

AJ20

2

FCC1_UT_TXPRTY/L1TSYNCC1/

L1GNTC1

AG18

2

PD17/BRGO2/SPIMOSI

PD18/SPICLK

FCC1_UT_RXPRTY

AG17

2

FCC1_UTM_RXADDR4/

FCC1_UTS_RXADDR4/

FCC1_UTM_RXCLAV3/

FCC2_UTM_RXADDR3/

FCC2_UTS_RXADDR0

AF16

PD19/SPISEL/BRGO1

FCC1_UTM_TXADDR4/

FCC1_UTS_TXADDR4/

FCC1_UTM_TXCLAV3/

FCC2_UTM_TXADDR3/

FCC2_UTS_TXADDR0

AH15

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

58

Freescale Semiconductor

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

FCC1_UT16_RXD2

2

PD20/RTS4/TENA4/L1RSYNCA2/

USB_TP

AJ14

2

PD21/TXD4/L1RXD0A2/L1RXDA2/

USB_TN

FCC1_UT16_RXD3

FCC1_UT16_TXD5

AH13

2

PD22/RXD4L1TXD0A2/L1TXDA2/

USB_RXD

AJ12

2

PD23/RTS3/TENA3

PD24/TXD3

FCC1_UT16_RXD4/L1RSYNCD1

FCC1_UT16_RXD5/L1RXDD1

FCC1_UT16_TXD6/L1TXDD1

FCC1_UT16_RXD6/L1RSYNCC1

FCC1_UT16_RXD7/L1RXDC1

FCC1_UT16_TXD7/L1TXDC1

AE12

AF10

2

PD25/RXD3

AG9

AH8

AG7

AE4

AG1

2

PD26/RTS2/TENA2

PD27/TXD2

2

PD28/RXD2

PD29/RTS1/TENA1

FCC1_UTM_RXADDR3/

FCC1_UTS_RXADDR3/

FCC1_UTM_RXCLAV2/

FCC2_UTM_RXADDR4/

FCC2_UTS_RXADDR1

2

PD30/TXD1

FCC2_UTM_TXENB/

FCC2_UTS_TXENB

AD4

AD2

PD31/RXD1

VCCSYN

VCCSYN1

CLKIN2

AB3

B9

AE11

U5

3

SPARE4

4

PCI_MODE

AF25

V4

3

SPARE6

5

No connect

AA1, AG4

I/O power

AG21, AG14, AG8, AJ1, AJ2, AH1,

AH2, AG3, AF4, AE5, AC27, Y27,

T27, P27, K26, G27, AE25, AF26,

AG27, AH28, AH29, AJ28, AJ29, C7,

C14, C16, C20, C23, E10, A28, A29,

B28, B29, C27, D26, E25, H3, M4,

T3, AA4, A1, A2, B1, B2, C3, D4, E5

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

59

Pinout

Table 23. MPC8280 and MPC8270 (ZU and VV Packages) Pinout List (continued)

Pin Name

Ball

MPC8280/MPC8270

MPC8280 only

Core power

U28, U29, K28, K29, A9, A19, B19,

M1, M2, Y1, Y2, AC1, AC2, AH19,

AJ19, AH10, AJ10, AJ5

6

7

Ground

AA5, AB1 , AB2 , AF21, AF14, AF8,

AE7, AF11, AE17, AE23, AC26,

AB25, Y26, V25, T26, R25, P26,

M25, K27, H25, G26, D7, D10, D14,

D16, D20, D23, C9, E11, E13, E15,

E19, E22, B3, G5, H4, K5, M3, P5,

T4, Y5, AA2, AC3

1

Should be tied to VDDH via a 2K Ω external pull-up resistor.

2

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC current,

it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

Must be pulled down or left floating.

If PCI is not desired, must be pulled up or left floating.

Sphere is not connected to die.

GNDSYN (AB1): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a separate ground

signal on the SoC. New designs must connect AB1 to GND and follow the suggestions in Section 4.6, “Layout Practices.” Old

designs in which the MPC8280 is used as a drop-in replacement can leave the pin connected to GND with the noise filtering

capacitors.

XFC (AB2) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8280 because there is no need for external

capacitor to operate the PLL. New designs should connect AB2 (XFC) pin to GND. Old designs in which the SoC is used as a

drop-in replacement can leave the pin connected to the current capacitor.

3

4

5

6

7

This table describes symbols used in Table 23.

Table 24. Symbol Legend

Symbol

OVERBAR

Meaning

Signals with overbars, such as TA, are active low.

UTM

UTS

UT8

UT16

MII

Indicates that a signal is part of the UTOPIA master interface.

Indicates that a signal is part of the UTOPIA slave interface.

Indicates that a signal is part of the 8-bit UTOPIA interface.

Indicates that a signal is part of the 16-bit UTOPIA interface.

Indicates that a signal is part of the media independent interface.

Indicates that a signal is part of the reduced media independent interface.

RMII

8.2

VR and ZQ Packages—MPC8275 and MPC8270

The following figures and table represent the alternate 516 PBGA package. For information on the

standard package for the MPC8280 and the MPC8270, see Section 8.1, “ZU and VV

Packages—MPC8280 and MPC8270.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

60

Freescale Semiconductor

Pinout

This figure shows the pinout of the VR and ZQ packages as viewed from the top surface.

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A

B

A

B

C

D

E

F

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Not to Scale

Figure 14. Pinout of the 516 PBGA Package (View from Top)

This table shows the pinout list of the MPC8275 and MPC8270. Table 24 defines conventions and

acronyms used in Table 25.

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

BR

C16

D2

BG

ABB/IRQ2

TS

C1

D1

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

61

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

A0

D5

E8

A1

A2

C4

A3

B4

A4

A5

D7

A6

D8

A7

C6

A8

B5

A9

B6

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

TT0

C7

C8

A6

D9

F11

B7

B8

C9

A7

B9

E11

A8

D11

B10

C11

A9

B11

C12

D12

A10

B12

B13

E7

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

62

Freescale Semiconductor

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

TT1

TT2

TT3

TT4

TBST

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

ARTRY

DBG

DBB/IRQ3

D0

B3

F8

A3

C3

F5

E3

E2

E1

E4

D3

C2

A14

C15

W4

Y1

V1

P4

N3

K5

J4

D1

D2

D3

D4

D5

D6

D7

G1

AB1

U4

U2

N6

N1

L1

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

J5

G3

AA2

W1

T3

T1

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

63

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D51

D52

M2

K2

J1

G4

U5

T5

P5

P3

M3

K3

H2

G5

AA1

V2

U1

P2

M4

K4

H3

F2

Y2

U3

T2

N2

M5

K1

H4

F1

W2

T4

R3

N4

M1

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

64

Freescale Semiconductor

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

J2

H5

F3

V3

R5

R2

N5

L2

J3

H1

F4

DP0/RSRV/EXT_BR2

AB3

W5

AC2

AA3

AD1

AC1

AB2

Y3

IRQ1/DP1/EXT_BG2

IRQ2/DP2/TLBISYNC/EXT_DBG2

IRQ3/DP3/CKSTP_OUT/EXT_BR3

IRQ4/DP4/CORE_SRESET/EXT_BG3

IRQ5/CINT/DP5/TBEN/EXT_DBG3

IRQ6/DP6/CSE0

IRQ7/DP7/CSE1

PSDVAL

D15

Y4

TA

TEA

D16

E15

D14

E14

A17

B14

F13

B17

AC6

AD6

AE6

AB7

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

CPU_BR

CS0

CS1

CS2

CS3

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

65

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

CS4

CS5

CS6

CS7

CS8

CS9

AF7

AC7

AD7

AF8

AE8

AD8

AC8

AB8

C13

A12

D13

AF4

AA5

AE4

AD4

AF3

AB4

AE3

AF2

AD3

AE2

AD2

AE1

AC3

W6

CS10/BCTL1

CS11/AP0

BADDR27

BADDR28

ALE

BCTL0

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

AA4

AC9

AD9

AE9

AF9

AB6

AF5

AE5

LWE0/LSDDQM0/LBS0/PCI_CFG0

LWE1/LSDDQM1/LBS1/PCI_CFG1

LWE2/LSDDQM2/LBS2/PCI_CFG2

LWE3/LSDDQM3/LBS3/PCI_CFG3

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

66

Freescale Semiconductor

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LGPL5/LSDAMUX/PCI_MODCK

LWR

AD5

AC5

AB5

AF6

L_A14/PAR

AE13

AD15

AF16

AF15

AE15

AE14

AC17

AD14

AF13

AE20

AC14

AC19

AD13

AF21

AF22

AE21

AB14

AD20

AB9

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTA

L_A30/REQ2

L_A31/DLLOUT

LCL_D0/AD0

LCL_D1/AD1

AB10

AC10

AD10

AE10

AF10

AF11

AB12

AB11

AF12

AE11

LCL_D2/AD2

LCL_D3/AD3

LCL_D4/AD4

LCL_D5/AD5

LCL_D6/AD6

LCL_D7/AD7

LCL_D8/AD8

LCL_D9/AD9

LCL_D10/AD10

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

67

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

LCL_D11/AD11

LCL_D12/AD12

LCL_D13/AD13

LCL_D14/AD14

LCL_D15/AD15

LCL_D16/AD16

LCL_D17/AD17

LCL_D18/AD18

LCL_D19/AD19

LCL_D20/AD20

LCL_D21/AD21

LCL_D22/AD22

LCL_D23/AD23

LCL_D24/AD24

LCL_D25/AD25

LCL_D26/AD26

LCL_D27/AD27

LCL_D28/AD28

LCL_D29/AD29

LCL_D30/AD30

LCL_D31/AD31

LCL_DP0/C0/BE0

LCL_DP1/C1/BE1

LCL_DP2/C2/BE2

LCL_DP3/C3/BE3

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

AC13

AC12

AB13

AD12

AF14

AF17

AE16

AD16

AC16

AB16

AF18

AE17

AD17

AB17

AE18

AD18

AC18

AE19

AF20

AD19

AB18

AE12

AA13

AC15

AF19

A11

E5

1

TRST

F22

TCK

TMS

TDI

A24

C24

A25

TDO

TRIS

B24

C19

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

68

Freescale Semiconductor

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

2

PORESET

HRESET

SRESET

QREQ

B25

D24

E23

D18

E24

RSTCONF

MODCK1/AP1/TC0/BNKSEL0

MODCK2/AP2/TC1/BNKSEL1

MODCK3/AP3/TC2/BNKSEL2

CLKIN1

B16

F16

A15

G22

AC20

AC21

2

PA0/RESTART1/DREQ3

PA1/REJECT1/DONE3

PA2/CLK20/DACK3

PA3/CLK19/DACK4/L1RXD1A2

PA4/REJECT2/DONE4

PA5/RESTART2/DREQ4

PA6

FCC2_UTM_TXADDR2

FCC2_UTM_TXADDR1

FCC2_UTM_TXADDR0

FCC2_UTM_RXADDR0

FCC2_UTM_RXADDR1

FCC2_UTM_RXADDR2

FCC2_UT_RXADDR3

FCC2_UT_TXADDR3

FCC2_UT_TXADDR4

2

AF25

AE24

AA21

AD25

AC24

2

PA7/SMSYN2

AA22

AA23

2

PA8/SMRXD2

2

PA9/SMTXD2

Y26

W22

W23

2

PA10/MSNUM5

FCC1_UT8_RXD0/FCC1_UT16_RXD8

FCC1_UT8_RXD1/FCC1_UT16_RXD9

2

PA11/MSNUM4

2

PA12/MSNUM3

FCC1_UT8_RXD2/

FCC1_UT16_RXD10

V26

V25

T22

T25

2

PA13/MSNUM2

FCC1_UT8_RXD3/

FCC1_UT16_RXD11

2

PA14/FCC1_MII_HDLC_RXD3

PA15/FCC1_MII_HDLC_RXD2

FCC1_UT8_RXD4/

FCC1_UT16_RXD12

/FCC1_UT8_RXD5/

FCC1_UT16_RXD13

PA16/FCC1_MII_HDLC_RXD1/

FCC1_RMII_RXD1

FCC1_UT8_RXD6/

FCC1_UT16_RXD14

R24

2

PA17/FCC_MII_HDLC_RXD0/

FCC1_MII_TRAN_RXD/

FCCI_RMII_RXD0

FCC1_UT8_RXD7/

FCC1_UT16_RXD15

P22

2

PA18/FCC1_MII_HDLC_TXD0/

FCC1_MII_TRAN_TXD/

FCC1_RMII_TXD0

FCC1_UT8_TXD7/FCC1_UT16_TXD15

N26

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

69

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

2

PA19/FCC1_MII_HDLC_TXD1/

FCC1_RMII_TXD1

FCC1_UT8_TXD6/FCC1_UT16_TXD14

N23

K26

2

PA20/FCC1_MII_HDLC_TXD2

PA21/FCC1_MII_HDLC_TXD3

PA22

FCC1_UT8_TXD5/FCC1_UT16_TXD13

FCC1_UT8_TXD4/FCC1_UT16_TXD12

FCC1_UT8_TXD3/FCC1_UT16_TXD11

FCC1_UT8_TXD2/FCC1_UT16_TXD10

FCC1_UT8_TXD1/FCC1_UT16_TXD9

FCC1_UT8_TXD0/FCC1_UT16_TXD8

2

L23

2

K23

H26

2

PA23

2

PA24/MSNUM1

F25

2

PA25/MSNUM0

D26

D25

2

PA26/FCC1_MII_RMII_RX_ER/

FCC1_UTM_RXCLAV/

FCC1_UTS_RXCLAV

PA27/FCC1_MII_RX_DV/

FCC1_RMII_CRS_DV

FCC1_UT_RXSOC

C25

C22

PA28/FCC1_MII_TX_EN/

FCC1_RMII_TX_EN

FCC1_UTM_RXENB/

FCC1_UTS_RXENB

2

PA29/FCC1_MII_TX_ER

FCC1_UT_TXSOC

B21

A20

PA30/FCC1_MII_CRS/FCC1_RTS

FCC1_UTM_TXCLAV/

FCC1_UTS_TXCLAV

2

PA31/FCC1_MII_COL

FCC1_UTM_TXENB/

FCC1_UTS_TXENB

A19

2

PB4/FCC3_MII_HDLC_TXD3/

L1RSYNCA2/FCC3_RTS

FCC2_UT8_RXD0

FCC2_UT8_RXD1

FCC2_UT8_RXD2

AD21

AD22

AC22

PB5/FCC3_MII_HDLC_TXD2/

L1TSYNCA2/L1GNTA2

PB6/FCC3_MII_HDLC_TXD1/

FCC3_RMII_TXD1/

L1RXDA2/L1RXD0A2

2

PB7/FCC3_MII_HDLC_TXD0/

FCC3_RMII_TXD0/

FCC3_TXD/L1TXDA2/L1TXD0A2

FCC2_UT8_RXD3

FCC2_UT8_TXD3

FCC2_UT8_TXD2

AE26

AB23

AC26

PB8/FCC3_MII_HDLC_RXD0/

FCC3_RMII_RXD0/

FCC3_RXD/TXD3

PB9/FCC3_MII_HDLC_RXD1/

FCC3_RMII_RXD1/L1TXD2A2

2

PB10/FCC3_MII_HDLC_RXD2

PB11/FCC3_MII_HDLC_RXD3

PB12/FCC3_MII_CRS/TXD2

FCC2_UT8_TXD1

FCC2_UT8_TXD0

AB26

AA25

2

W26

W25

2

PB13/FCC3_MII_COL/L1TXD1A2

PB14/FCC3_MII_RMII_TX_EN/RXD3

2

V24

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

70

Freescale Semiconductor

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

2

PB15/FCC3_MII_TX_ER/RXD2

U24

R22

R23

PB16/FCC3_MII_RMII_RX_ER/CLK18

PB17/FCC3_MII_RX_DV/CLK17/

FCC3_RMII_CRS_DV

2

PB18/FCC2_MII_HDLC_RXD3/

L1CLKOD2/L1RXD2A2

FCC2_UT8_RXD4

M23

2

PB19FCC2_MII_HDLC_RXD2/

L1RQD2/L1RXD3A2

FCC2_UT8_RXD5

FCC2_UT8_RXD6

FCC2_UT8_RXD7

L24

2

PB20/FCC2_MII_HDLC_RMII_RXD1/

L1RSYNCD2

K24

2

PB21//FCC2_MII_HDLC_RMII_RXD0/

FCC2_TRAN_RXD/L1TSYNCD2/

L1GNTD2

L21

PB22/FCC2_MII_HDLC_RMII_TXD0/

FCC2_TXD/FCC2_RMII_TXD0/

L1RXDD2

FCC2_UT8_TXD7

FCC2_UT8_TXD6

P25

2

PB23/FCC2_MII_HDLC_TXD1/

L1RXD2A1/L1TXDD2/

FCC2_RMII_TXD1

N25

2

PB24/FCC2_MII_HDLC_TXD2/

L1RSYNCC2

FCC2_UT8_TXD5

FCC2_UT8_TXD4

E26

PB25/FCC2_MII_HDLC_TXD3/

L1TSYNCC2/L1GNTC2

H23

2

PB26/FCC2_MII_CRS/L1RXDC2

PB27/FCC2_MII_COL/L1TXDC2

FCC2_UT8_TXD1

FCC2_UT8_TXD0

C26

B26

A22

PB28/FCC2_MII_RX_ER/FCC2_RMII_RX_ER/

FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1

2

PB29/L1RSYNCB2/

FCC2_MII_TX_EN/FCC2_RMII_TX_EN

FCC2_UTM_RXCLAV/

FCC2_UTS_RXCLAV

A21

E20

C20

PB30/FCC2_MII_RX_DV/L1RXDB2/

FCC2_RMII_CRS_DV

FCC2_UT_TXSOC

PB31/FCC2_MII_TX_ER/L1TXDB2

FCC2_UT_RXSOC

2

PC0/DREQ1/BRGO7/SMSYN2/

L1CLKOA2

AE22

2

PC1/DREQ2/SPISEL/BRGO6/L1RQA2

PC2/FCC3_CD/DONE2

AA19

AF24

AE25

FCC2_UT8_TXD3

FCC2_UT8_TXD2

PC3/FCC3_CTS/DACK2/CTS4/

USB_RP

2

PC4/SI2_L1ST4/FCC2_CD

FCC2_UTM_RXENB/

FCC2_UTS_RXENB

AB22

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

71

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

FCC2_UTM_TXCLAV/

2

PC5/SI2_L1ST3/FCC2_CTS

AC25

FCC2_UTS_TXCLAV

PC6/FCC1_CD

FCC1_UTM_RXADDR2/

FCC1_UTS_RXADDR2/

FCC1_UTM_RXCLAV1

AB25

2

PC7/FCC1_CTS

FCC1_UTM_TXADDR2/

FCC1_UTS_TXADDR2/

FCC1_UTM_TXCLAV1

AA24

2

PC8/CD4/RENA4/SI2_L1ST2/CTS3/

USB_RN

FCC1_UT16_TXD0

Y24

PC9/CTS4/CLSN4/SI2_L1ST1/

L1TSYNCA2/L1GNTA2/USB_RP

FCC1_UT16_TXD1

U22

2

PC10/CD3/RENA3

FCC1_UT16_TXD2/FCC2_UT8_RXD3

FCC2_UT8_RXD2

V23

U23

PC11/CTS3/CLSN3/L1TXD3A2

PC12/CD2/RENA2

2

FCC1_UTM_RXADDR1/

FCC1_UTS_RXADDR1

T26

2

PC13/CTS2/CLSN2

FCC1_UTM_TXADDR1/

FCC1_UTS_TXADDR1

R26

P26

P24

2

PC14/CD1/RENA1

FCC1_UTM_RXADDR0/

FCC1_UTS_RXADDR0

PC15/CTS1/CLSN1/SMTXD2

FCC1_UTM_TXADDR0/

FCC1_UTS_TXADDR0

PC16/CLK16/TIN4

M26

2

PC17/CLK15/TIN3/BRGO8

PC18/CLK14/TGATE2

L26

2

M24

2

PC19/CLK13/BRGO7/SPICLK

PC20/CLK12/TGATE1/USB_OE

PC21/CLK11/BRGO6

L22

K25

2

J25

2

PC22/CLK10/DONE1

FCC1_UT_TXPRTY

G26

2

PC23/CLK9/BRGO5/DACK1

PC24/CLK8/TOUT4

F26

FCC2_UT8_TXD3

FCC2_UT8_TXD2

G24

2

PC25/CLK7/BRGO4

E25

G23

2

PC26/CLK6/TOUT3/TMCLK

2

PC27/FCC3_TXD/FCC3_MII_TXD0/

FCC3_RMII_TXD0/CLK5/BRGO3

B23

2

PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2

PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1

PC30/CLK2/TOUT1

FCC2_UT_RXADDR4

FCC2_UT8_TXD3

E22

E21

D21

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

72

Freescale Semiconductor

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

PC31/CLK1/BRGO1

MPC8275 only

2

B20

2

PD4/BRGO8/FCC3_RTS/SMRXD2

PD5/DONE1

AF23

AE23

AB21

FCC1_UT16_TXD3

PD6/DACK1

FCC1_UT16_TXD4

PD7/SMSYN1/FCC1_TXCLAV2

FCC1_UTM_TXADDR3/

FCC1_UTS_TXADDR3/

FCC2_UTM_TXADDR4

FCC2_UTS_TXADDR1

AD23

2

PD8/SMRXD1/BRGO5

PD9/SMTXD1/BRGO3

PD10/L1CLKOB2/BRGO4

PD11/L1RQB2

FCC2_UT_TXPRTY

FCC2_UT_RXPRTY

FCC2_UT8_RXD1

AD26

2

Y22

2

AB24

2

FCC2_UT8_RXD0

L1GNTB1

Y23

2

PD12

AA26

2

PD13

W24

2

PD14/L1CLKOC2/I2CSCL

PD15/L1RQC2/I2CSDA

PD16/SPIMISO

PD17/BRGO2/SPIMOSI

PD18/SPICLK

FCC1_UT16_RXD0

FCC1_UT16_RXD1

FCC1_UT_TXPRTY

FCC1_UT_RXPRTY

V22

U26

2

T23

2

R25

P23

2

FCC1_UTM_RXADDR4/

FCC1_UTS_RXADDR4/

FCC1_UTM_RXCLAV3/

FCC2_UTM_RXADDR3/

FCC2_UTS_RXADDR0

PD19/SPISEL/BRGO1

FCC1_UTM_TXADDR4/

FCC1_UTS_TXADDR4/

FCC1_UTM_TXCLAV3/

FCC2_UTM_TXADDR3/

FCC2_UTS_TXADDR0

N22

PD20/RTS4/TENA4/L1RSYNCA2/

USB_TP

FCC1_UT16_RXD2

FCC1_UT16_RXD3

FCC1_UT16_TXD5

M25

2

PD21/TXD4/L1RXD0A2/L1RXDA2/

USB_TN

L25

J26

2

PD22/RXD4L1TXD0A2/L1TXDA2/

USB_RXD

2

PD23/RTS3/TENA3

PD24/TXD3

FCC1_UT16_RXD4

FCC1_UT16_RXD5

FCC1_UT16_TXD6

FCC1_UT16_RXD6

K22

G25

H24

2

PD25/RXD3

2

PD26/RTS2/TENA2

F24

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

73

Pinout

Table 25. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (continued)

Pin Name

Ball

MPC8275/MPC8270

MPC8275 only

FCC1_UT16_RXD7

2

PD27/TXD2

H22

B22

D22

PD28/RXD2

FCC1_UT16_TXD7

PD29/RTS1/TENA1

FCC1_UTM_RXADDR3/

FCC1_UTS_RXADDR3/

FCC1_UTM_RXCLAV2/

FCC2_UTM_RXADDR4/

FCC2_UTS_RXADDR1

2

PD30/TXD1

FCC2_UTM_TXENB/

FCC2_UTS_TXENB

C21

PD31/RXD1

VCCSYN

VCCSYN1

CLKIN2

E19

D19

K6

K21

3

SPARE4

C14

4

PCI_MODE

AD24

B15

3

SPARE6

5

No connect

E17, C23

I/O power

E6, F6, H6, L5, L6, P6, T6, U6, V5,

Y5, AA6, AA8, AA10, AA11, AA14,

AA16, AA17, AB19, AB20, W21,

U21, T21, P21, N21, M22, J22, H21,

F21, F19, F17, E16, F14, E13, E12,

F10, E10, E9

Core Power

Ground

L3, V4, W3, AC11, AD11, AB15,

U25, T24, J24, H25, F23, B19, D17,

C17, D10, C10

6

7

B18 , A18 , A2, B1, B2, A5, C5,

C18, D4, D6, G2, L4, P1, R1, R4,

AC4, AE7, AC23, Y25, N24, J23,

A23, D23, D20, E18, A13, A16, K10,

K11, K12, K13, K14, K15, K16, K17,

L10, L11, L12, L13, L14, L15, L16,

L17, M10, M11, M12, M13, M14,

M15, M16, M17, N10, N11, N12,

N13, N14, N15, N16, N17, P10, P11,

P12, P13, P14, P15, P16, P17, R10,

R11,R12, R13, R14, R15, R16, R17,

T10, T11, T12, T13, T14, T15, T16,

T17, U10, U11, U12, U13, U14, U15,

U16, U17

1

Should be tied to VDDH via a 2K Ω external pull-up resistor.

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC

current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

2

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

74

Freescale Semiconductor

Package Description

3

4

5

6

Must be pulled down or left floating.

If PCI is not desired, must be pulled up or left floating.

Sphere is not connected to die.

GNDSYN (B18): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a separate ground

signal on the MPC8275/MPC8270. New designs must connect B18 to GND and follow the suggestions in Section 4.6, “Layout

Practices.” Old designs in which the MPC8275/MPC8270 is used as a drop-in replacement can leave the pin connected to

GND with the noise filtering capacitors.

XFC (A18) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8275/MPC8270 because there is no need for

external capacitor to operate the PLL. New designs should connect A18 (XFC) pin to GND. Old designs in which the

MPC8275/MPC8270 is used as a drop-in replacement can leave the pin connected to the current capacitor.

7

9 Package Description

This figure shows the side profile of the TBGA package to indicate the direction of the top surface view.

View

Pressure Sensitive

Copper Heat Spreader

Adhesive

Etched

Cavity

(Oxidized for Insulation)

Die

Attach

Polymide Tape

Die

Glob-Top Filled Area

Soldermask

Glob-Top Dam

Copper Traces

1.27 mm Pitch

Wire Bonds

Figure 15. Side View of the TBGA Package

This figure shows the side profile of the PBGA package to indicate the direction of the top surface view.

Wire bonds

Ball bond

Die

attach

Transfer molding compound

Plated substrate via

Screen-printed

solder mask

Cu substrate traces

Resin glass epoxy

DIE

1 mm pitch

Figure 16. Side View of the PBGA Package Remove

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

75

Package Description

9.1

Package Parameters

This table provides package parameters.

NOTE: Temperature Reflow for the VR Package

In the VR package, sphere composition is lead-free (see Table 2). This

requires higher temperature reflow than what is required for other

PowerQUICC II packages. Consult “Freescale PowerQUICC II Pb-Free

Packaging Information” (MPC8250PBFREEPKG) available on

www.freescale.com.

Table 26. Package Parameters

Outline

(mm)

Pitch

(mm)

Nominal Unmounted

Height (mm)

Package

SoCs

MPC8280

Type

Interconnects

ZU

37.5 × 37.5

27 × 27

TBGA

480

1.27

1

1.55

2.25

MPC8270

VV

VR

ZQ

MPC8280

MPC8270

TBGA

PBGA

480

516

MPC8275VR

MPC8270VR

MPC8275ZQ

MPC8270ZQ

27 × 27

1

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

76

Freescale Semiconductor

Package Description

9.2

Mechanical Dimensions

This figure provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA

(ZU/VV) package. See Table 2, “HiP7 PowerQUICC II Device Packages.”

Millimeters

Dim

Min

Max

A

1.45

0.60

0.85

0.25

0.65

1.65

A1

A2

A3

b

0.70

0.95

—

0.85

D

37.50 BSC

35.56 REF

1.27 BSC

37.50 BSC

35.56 REF

D1

e

E

E1

Notes:

1. Dimensions and Tolerancing per ASME Y14.5M-1994.

2. Dimensions in millimeters.

3. Dimension b is measured at the maximum solder ball diameter, parallel to primary data A.

4. Primary data A and the seating plane are defined by the spherical crowns of the solder balls.

Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

77

Package Description

This figure provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA

(VR/ZQ) packages.

Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

78

Freescale Semiconductor

Ordering Information

10 Ordering Information

This figure provides an example of the Freescale part numbering nomenclature for the SoC. In addition to

the processor frequency, the part numbering scheme also consists of a part modifier that indicates any

enhancement(s) in the part from the original production design. Each part number also contains a revision

code that refers to the die mask revision number and is specified in the part numbering scheme for

identification purposes only. For more information, contact your local Freescale sales office.

MPC 82XX C ZU XXX X

Die revision level

Product code

Device number

Processor frequency

(CPU/CPM/Bus in MHz)

B = 66

E = 100

F = 133

I = 200

M = 266

P = 300

T = 400

Temperature range

Blank = 0 to 105

T

j

A

C = (–40) – 105

T

j

A

Package

ZU = 480 TBGA lead spheres

VV = 480 TBGA lead-free spheres

VR = 516 PBGA lead-free spheres

ZQ = 516 PBGA lead sphere

Figure 19. Freescale Part Number Key

11 Document Revision History

This table summarizes changes to this document.

Table 27. Document Revision History

Substantive Changes

Date

Revision

2

09/2011 In Figure 19, “Freescale Part Number Key,” added speed decoding information below processor

frequency information.

1.8

1.7

07/2007 • Updated the entire document, adding information on the VV package.

12/2006 • Section 6, “AC Electrical Characteristics,” removed deratings statement and clarified AC

timing descriptions.

1.6

05/2006 • Table 11: Added text to clarify that Data Bus Parity is not supported at 66 Mhz.

• Table 11: Added text to clarify that Data Bus ECC is supported at 66 Mhz

• Table 11: Added note to DP pins to show it is not supported at 66 MHz

• Table 12: Added note to support 1 ns hold time

1.5

03/2006 • Added Section 6.3, “JTAG Timings”

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

79

Document Revision History

Table 27. Document Revision History (continued)

Substantive Changes

Date

Revision

1.4

11/2005 • In Section 6.2, “SIU AC Characteristics”, modified the note on CLKIN Jitter and Duty Cycle.

• Modified Figure 17 to display all text.

1.3

1.2

01/2005 • Modification for correct display of assertion level (“overbar”) for some signals

12/2004 • Section 2: removed voltage tracking note

• Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset

• Table 5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external

pullup removed.

• Table 5: Note 4 added regarding IIC compatibility

• Section 4.2: New information about jumper-to-case thermal resistance

• Section 4.3: New information about jumper-to-board thermal resistance

• Section 4.4: New information about estimation with simulation

• Section 4.6: Updated description of layout practices

• Section 6: Added sentence providing derating factor

• Section 6.1, “CPM AC Characteristics”: added Note: Rise/Fall Time on CPM Input Pins

• Table 9: updated values for following specs: sp42, sp43, sp42a

• Table 20: updated values for following specs: sp16b, sp18b, sp20, sp22

• Section 6.2: added spread sprectrum clocking note

• Table 11: combined specs sp11 and sp11a

• Sections 7.2, 7.3: unit of ns added to Tval notes

• Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin

of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

80

Freescale Semiconductor

Document Revision History

Table 27. Document Revision History (continued)

Substantive Changes

Date

Revision

1.0

2/2004

• Removal of “Advance Information” and “Preliminary.” The MPC8280 is fully qualified.

• Table 2: New

• Figure 1: Modification to note 2

• Section 1.1: Core frequency range is 166–450 MHz

• Addition of ZQ (516 PBGA with Lead spheres) package references

• Table 4: VDD and VCCSYN modified to 1.45–1.60 V

• Note following Table 4: Modified

• Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5)

• Table 5: Changed I for 60x signals to 6.0 mA

OL

• Table 5: Moved QREQ to V : I = 3.2 mA

OL OL

• Table 5: Addition of critical interrupt (CINT) to IRQ5 for V (I = 6.0mA)

OL OL

• Table 10: Addition of Ψ and note 4

JT

• Sections 4.1–4.5: New

• Table 12: Modified power values (+ 150mW to each)

• Table 14: Addition of note 2. Changed PCI impedance to 27 Ω.

• Table 9: Changes to sp36b, SP38a, sp38b, sp37a, sp39a, sp40 and sp41

• Table 20: Changes to sp16a, sp18a, sp20 and sp21

• Section 6.2: Addition of Note: CLKIN Jitter and Duty Cycle

• Table 11: Changes to sp13 @ 66 and 83 MHz, sp14 @ 83 MHz

• Table 12: Change to sp30 (data bus signals). Changes to sp33b. Removal of note 2.

• Table 18 through Table 37: Modification of note 1 regarding CPU and CPM Fmin. Modification

to corresponding values in tables.

• Table 23: Addition of note 1 to TRST (AH3) and PORESET (AG6)

• Table 23: Addition of RXD3 to CPM port pin PB14. Previously omitted.

• Table 23: Addition of critical interrupt (CINT) to B21 and U4. Previously omitted.

• Table 23: Addition of note 5 to ‘No connect’ (AA1, AG4)

• Addition of “Note: Temperature Reflow for the VR Package" on page 76

• Table 25: Addition of note 1 to TRST (F22) and PORESET (B25)

• Table 25: Addition of previously omitted signals that are multiplexed with CPM port pins:

PA6—FCC2_UT_RXADDR3

PA7—FCC2_UT_TXADDR3

PA8—FCC2_UT_TXADDR4

PB14—RXD3

PC19—SPICLK

PC22—FCC1_UT_TXPRTY

PC28—FCC2_UT_RXADDR4

• Table 25: Removal of serial interface 1 (SI1) signals from port pins (see note 2 in Figure 1):

PA[6–9], PB[8–17, 20–25], PC[6–7, 10–13], PD[4, 10–13, 16, 23–28]

• Table 25: Addition of critical interrupt (CINT) to AC1 and B14. Previously omitted.

• Table 25: Addition of note 5 to ‘No connect’ (E17, C23)

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

81

Document Revision History

Table 27. Document Revision History (continued)

Substantive Changes

Date

Revision

0.3

6/2003

• Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the

MPC8275VR have local bus support.

• References to “G2 core” changed to “G2_LE core.” See the G2 Core Reference Manual

(G2CORERM/D).

• Addition of VCCSYN to “Note” below Table 4, and to note 3 of Table 5

• Figure 2: New

• Table 5: Addition of note 1

• Table 10: Addition of θ and θ . Modifications to ZU package values.

JB

JC

• Table 12: Addition of various configurations, Modification of values. Addition of note 3.

• Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.

• Table 20: Addition of 66 MHZ and 100 MHz values

• Table 12: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of

current note 2.

• Figure 5, Figure 6, Figure 7, and Figure 8: Addition of notes

• Section 6.2: Addition of note on PCI timing

• Table 18, Table 32, Table 33, Table 36, Table 37: Addition of note 1 concerning minimum

operating frequencies

• Addition of statement before clock tables about selection of clock configuration and input

frequency

• Table 23 and Table 25: Addition of note 1 to CPM pins

0.2

0.1

11/2002 Table 25, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)

—

Initial public release

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

82

Freescale Semiconductor

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

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Freescale Semiconductor reserves the right to make changes without further notice to

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Document Number: MPC8280EC

Rev. 2

09/2011


型号：	MPC8280CZUMX
厂家：	NXP
描述：	32-BIT, 266MHz, RISC PROCESSOR, PBGA480, 37.5 X 37.5 MM, 1.55 MM, 1.27 MM PITCH, TBGA-480 外围集成电路
文件：	总83页 (文件大小：618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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