MPC8313CVRAFFC_技术文档

Document Number: MPC8313EEC

Rev. 4, 11/2011

Freescale Semiconductor

Datasheet: Technical Data

MPC8313E

PowerQUICC II Pro Processor

Hardware Specifications

Contents

This document provides an overview of the MPC8313E

PowerQUICC™ II Pro processor features, including a block

diagram showing the major functional components. The

MPC8313E is a cost-effective, low-power, highly integrated

host processor that addresses the requirements of several

printing and imaging, consumer, and industrial applications,

including main CPUs and I/O processors in printing systems,

networking switches and line cards, wireless LANs

(WLANs), network access servers (NAS), VPN routers,

intelligent NIC, and industrial controllers. The MPC8313E

extends the PowerQUICC™ family, adding higher CPU

performance, additional functionality, and faster interfaces

while addressing the requirements related to time-to-market,

price, power consumption, and package size.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 14

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8. Ethernet: Three-Speed Ethernet, MII Management . 21

9. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 36

10. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 47

12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

16. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

17. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

18. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

19. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 63

20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

22. System Design Information . . . . . . . . . . . . . . . . . . . 87

23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 93

24. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

NOTE

The information in this document is accurate for

revisions 1.0, 2.x, and later. See Section 23.1, “Part

Numbers Fully Addressed by this Document.”

1 Overview

The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches

and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced

three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an

enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role

2

controller and an on-chip high-speed PHY, a programmable interrupt controller, dual I C controllers, a

4-channel DMA controller, and a general-purpose I/O port. This figure shows a block diagram of the

MPC8313E.

DUART

Dual I²C

Timers

GPIO

e300c3 Core w/FPU and

Power Management

Interrupt

16-KB

D-Cache

Local Bus,

SPI

DDR1/DDR2

Controller

I-Cache

Controller

USB 2.0

Host/Device/OTG

Gb Ethernet

MAC

Gb Ethernet

MAC

Security Engine 2.2

I/O Sequencer

(IOS)

On-Chip

ULPI

FS PHY

PCI

DMA

Note: The MPC8313 does not include a security engine.

Figure 1. MPC8313E Block Diagram

The MPC8313E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded

from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,

3DES, AES, SHA-1, and MD-5 algorithms.

1.1

MPC8313E Features

The following features are supported in the MPC8313E:

•

Embedded PowerPC™ e300 processor core built on Power Architecture™ technology; operates at

up to 333 MHz.

•

High-performance, low-power, and cost-effective host processor

DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both

DDR1 and DDR2

•

16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units

Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced

local bus interface with up to 66-MHz operation, and USB 2.0 (high speed) with an on-chip PHY.

•

Security engine provides acceleration for control and data plane security protocols

Power management controller for low-power consumption

High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

1.2

Serial Interfaces

2

The following interfaces are supported in the MPC8313E: dual UART, dual I C, and an SPI interface.

1.3

Security Engine

The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i®,

and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution

units (EUs). The execution units are as follows:

•

Data encryption standard execution unit (DEU), supporting DES and 3DES

Advanced encryption standard unit (AESU), supporting AES

Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and

HMAC with any algorithm

•

One crypto-channel supporting multi-command descriptor chains

1.4

DDR Memory Controller

The MPC8313E DDR1/DDR2 memory controller includes the following features:

•

Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM

Support for up to 333 MHz

Support for two physical banks (chip selects), each bank independently addressable

64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16/x32 data ports (no

direct x4 support)

•

Support for one 16-bit device or two 8-bit devices on a 16-bit bus, or one 32-bit device or two

16-bit devices on a 32-bit bus

•

Support for up to 16 simultaneous open pages

Supports auto refresh

On-the-fly power management using CKE

1.8-/2.5-V SSTL2 compatible I/O

1.5

PCI Controller

The MPC8313E PCI controller includes the following features:

•

PCI specification revision 2.3 compatible

Single 32-bit data PCI interface operates at up to 66 MHz

PCI 3.3-V compatible (not 5-V compatible)

Support for host and agent modes

On-chip arbitration, supporting three external masters on PCI

Selectable hardware-enforced coherency

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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1.6

USB Dual-Role Controller

The MPC8313E USB controller includes the following features:

•

Supports USB on-the-go mode, which includes both device and host functionality, when using an

external ULPI (UTMI + low-pin interface) PHY

•

Compatible with Universal Serial Bus Specification, Rev. 2.0

Supports operation as a stand-alone USB device

— Supports one upstream facing port

— Supports three programmable USB endpoints

Supports operation as a stand-alone USB host controller

— Supports USB root hub with one downstream-facing port

— Enhanced host controller interface (EHCI) compatible

•

Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation.

Low-speed operation is supported only in host mode.

Supports UTMI + low pin interface (ULPI) or on-chip USB 2.0 full-speed/high-speed PHY

1.7

Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)

The MPC8313E eTSECs include the following features:

•

Two RGMII/SGMII/MII/RMII/RTBI interfaces

Two controllers designed to comply with IEEE Std 802.3®, 802.3u®, 802.3x®, 802.3z®,

802.3au®, and 802.3ab®

•

Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating

mode

•

MII management interface for external PHY control and status

Three-speed support (10/100/1000 Mbps)

On-chip high-speed serial interface to external SGMII PHY interface

Support for IEEE Std 1588™

Support for two full-duplex FIFO interface modes

Multiple PHY interface configuration

TCP/IP acceleration and QoS features available

IP v4 and IP v6 header recognition on receive

IP v4 header checksum verification and generation

TCP and UDP checksum verification and generation

Per-packet configurable acceleration

Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2®, PPPoE session, MPLS

stacks, and ESP/AH IP-security headers

•

Transmission from up to eight physical queues.

Reception to up to eight physical queues

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

•

Full and half-duplex Ethernet support (1000 Mbps supports only full-duplex):

— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or

software-programmed PAUSE frame generation and recognition)

— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and

IEEE 802.1 virtual local area network (VLAN) tags and priority

— VLAN insertion and deletion

– Per-frame VLAN control word or default VLAN for each eTSEC

– Extracted VLAN control word passed to software separately

— Retransmission following a collision

— CRC generation and verification of inbound/outbound packets

— Programmable Ethernet preamble insertion and extraction of up to 7 bytes

MAC address recognition:

•

— Exact match on primary and virtual 48-bit unicast addresses

– VRRP and HSRP support for seamless router fail-over

— Up to 16 exact-match MAC addresses supported

— Broadcast address (accept/reject)

— Hash table match on up to 512 multicast addresses

— Promiscuous mode

Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet

programming models

•

RMON statistics support

10-Kbyte internal transmit and 2-Kbyte receive FIFOs

MII management interface for control and status

1.8

Programmable Interrupt Controller (PIC)

The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible

solution for general-purpose interrupt control. The PIC programming model supports 5 external and 34

internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.

1.9

Power Management Controller (PMC)

The MPC8313E power management controller includes the following features:

•

Provides power management when the device is used in both host and agent modes

Supports PCI power management 1.2 D0, D1, D2, D3hot, and D3cold states

On-chip split power supply controlled through external power switch for minimum standby power

Support for PME generation in PCI agent mode, PME detection in PCI host mode

Supports wake-up from Ethernet (Magic Packet), USB, GPIO, and PCI (PME input as host)

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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1.10 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) allows the MPC8313E to exchange data between other PowerQUICC

family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time

clocks, A/D converters, and ISDN devices.

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface

(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an

independent baud-rate generator, and a control unit.

2

1.11 DMA Controller, Dual I C, DUART, Local Bus Controller, and

Timers

The MPC8313E provides an integrated four-channel DMA controller with the following features:

•

Allows chaining (both extended and direct) through local memory-mapped chain descriptors

(accessible by local masters)

•

Supports misaligned transfers

2

There are two I C controllers. These synchronous, multi-master buses can be connected to additional

devices for expansion and system development.

The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550

programming models. The 16-byte FIFOs are supported for both the transmitter and the receiver.

The MPC8313E local bus controller (LBC) port allows connections with a wide variety of external DSPs

and ASICs. Three separate state machines share the same external pins and can be programmed separately

to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses

to asynchronous devices using a simple handshake protocol. The three user programmable machines

(UPMs) can be programmed to interface to synchronous devices or custom ASIC interfaces. Each chip

select can be configured so that the associated chip interface can be controlled by the GPCM or UPM

controller. The FCM provides a glueless interface to parallel-bus NAND Flash E2PROM devices. The

FCM contains three basic configuration register groups—BRn, ORn, and FMR. Both may exist in the

same system. The local bus can operate at up to 66 MHz.

The MPC8313E system timers include the following features: periodic interrupt timer, real time clock,

software watchdog timer, and two general-purpose timer blocks.

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8313E. The MPC8313E is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

This table provides the absolute maximum ratings.

1

Table 1. Absolute Maximum Ratings

Characteristic

Symbol

Max Value

Unit Note

Core supply voltage

PLL supply voltage

V_DD

–0.3 to 1.26

V

—

AV_DD

Core power supply for SerDes transceivers

Pad power supply for SerDes transceivers

DDR and DDR2 DRAM I/O voltage

XCOREV_DD

XPADV_DD

GV_DD

–0.3 to 2.75

–0.3 to 1.98

PCI, local bus, DUART, system control and power management, I²C,

and JTAG I/O voltage

NV_DD/LV_DD

–0.3 to 3.6

V

—

eTSEC, USB

LV_DDA/LV_DDB

MV_IN

–0.3 to 3.6

V

—

Input voltage

DDR DRAM signals

–0.3 to (GV_DD+ 0.3)

2, 5

4, 5

DDR DRAM reference

MV_REF

LV_IN

Enhanced three-speed Ethernet signals

–0.3 to (LV_DDA+ 0.3)

or

–0.3 to (LV_DDB+ 0.3)

Local bus, DUART, SYS_CLK_IN, system control,

and power management, I²C, and JTAG signals

NV_IN

–0.3 to (NV_DD+ 0.3)

V

3, 5

PCI

NV_IN

T_STG

–0.3 to (NV_DD+ 0.3)

–55 to 150

V

6

Storage temperature range

C

—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: NV_INmust not exceed NV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: LV_INmust not exceed LV_DDA/LV_DDBby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

2.1.2

Power Supply Voltage Specification

This table provides the recommended operating conditions for the MPC8313E. Note that the values in this

table are the recommended and tested operating conditions. If a particular block is given a voltage falling

within the range in the Recommended Value column, the MPC8313E is capable of delivering the amount

of current listed in the Current Requirement column; this is the maximum current possible. Proper device

operation outside of these conditions is not guaranteed.

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

7

Table 2. Recommended Operating Conditions

Current

Requirement

Characteristic

Symbol

Recommended Value¹Unit

Core supply voltage

V_DD

1.0 V ± 50 mV

1.0

V

469 mA

377 mA

170 mA

—

Internal core logic constant power

SerDes internal digital power

V_DDC

XCOREV_DD

XCOREV_SS

XPADV_DD

SerDes internal digital ground

0.0

SerDes I/O digital power

1.0

10 mA

—

SerDes I/O digital ground

XPADV_SS

0.0

SerDes analog power for PLL

SDAV_DD

1.0 V ± 50 mV

0.0

10 mA

—

SerDes analog ground for PLL

SDAV_SS

Dedicated 3.3 V analog power for USB PLL

Dedicated 1.0 V analog power for USB PLL

Dedicated analog ground for USB PLL

Dedicated USB power for USB bias circuit

Dedicated USB ground for USB bias circuit

Dedicated power for USB transceiver

Dedicated ground for USB transceiver

Analog power for e300 core APLL

Analog power for system APLL

USB_PLL_PWR3

USB_PLL_PWR1

USB_PLL_GND

USB_VDDA_BIAS

USB_VSSA_BIAS

USB_VDDA

USB_VSSA

3.3 V ± 300 mV

1.0 V ± 50 mV

0.0

2–3 mA

—

3.3 V ± 300 mV

0.0

4–5 mA

—

3.3 V ± 300 mV

0.0

75 mA

—

6

AV_DD1

1.0 V ± 50 mV

2.5 V ± 125 mV

1.8 V ± 80 mV

2–3 mA

131 mA

140 mA

—

6

AV_DD2

DDR1 DRAM I/O voltage (333 MHz, 32-bit operation)

DDR2 DRAM I/O voltage (333 MHz, 32-bit operation)

Differential reference voltage for DDR controller

GV_DD

MV_REF

1/2 DDR supply

(0.49  GV_DDto

0.51  GV_DD

)

Standard I/O voltage

eTSEC2 I/O supply

NV_DD

LV_DDA

3.3 V ± 300 mV²

V

74 mA

22 mA

2.5 V ± 125 mV/

3.3 V ± 300 mV

eTSEC1/USB DR I/O supply

LV_DDB

2.5 V ± 125 mV/

3.3 V ± 300 mV

V

44 mA

Supply for eLBC IOs

LV_DD

V_SS

3.3 V ± 300 mV

0.0

V

16 mA

—

Analog and digital ground

Junction temperature range

3

T_A/T_J

0 to 105

C

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

8

Table 2. Recommended Operating Conditions (continued)

Characteristic Symbol

Recommended Value¹Unit

Current

Requirement

Note:

1. GV_DD, NV_DD, AV_DD, and V_DDmust track each other and must vary in the same direction—either in the positive or negative direction.

2. Some GPIO pins may operate from a 2.5-V supply when configured for other functions.

3. Min temperature is specified with T_A; Max temperature is specified with T_J.

4. All Power rails must be connected and power applied to the MPC8313 even if the IP interfaces are not used.

5. All I/O pins should be interfaced with peripherals operating at same voltage level.

6. This voltage is the input to the filter discussed in Section 22.2, “PLL Power Supply Filtering” and not necessarily the voltage at the

AVDD pin, which may be reduced from VDD by the filter.

This figure shows the undershoot and overshoot voltages at the interfaces of the MPC8313E.

G/L/NV_DD+ 20%

G/L/NV_DD+ 5%

G/L/NV_DD

V_IH

V_SS

V_SS– 0.3 V

V_IL

V_SS– 0.7 V

Not to Exceed 10%

1

of t_interface

Note:

1. Note that t_interfacerefers to the clock period associated with the bus clock

interface.

Figure 2. Overshoot/Undershoot Voltage for GV /NV /LV

DD

2.1.3

Output Driver Characteristics

This table provides information on the characteristics of the output driver strengths.

Table 3. Output Drive Capability

Driver Type

Output Impedance ()

Supply Voltage

Local bus interface utilities signals

PCI signals

42

25

18

NV_DD= 3.3 V

DDR signal

GV_DD= 2.5 V

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Table 3. Output Drive Capability (continued)

Driver Type

Output Impedance ()

Supply Voltage

DDR2 signal

18

42

GV_DD= 1.8 V

NV_DD= 3.3 V

DUART, system control, I²C, JTAG, SPI

GPIO signals

NV_DD= 3.3 V

eTSEC signals

LV_DDA, LV_DDB= 2.5/3.3 V

LV_DDB= 2.5/3.3 V

USB signals

2.2

Power Sequencing

The MPC8313E does not require the core supply voltage (V and V

) and I/O supply voltages

DD

DDC

(GV , LV , and NV ) to be applied in any particular order. Note that during power ramp-up, before

DD

the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a

period of time that all input and output pins are actively driven and cause contention and excessive current.

In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core

voltage (V and V

) before the I/O voltage (GV , LV , and NV ) and assert PORESET before

DD

DDC

DD DD DD

the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply

must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the

power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before

negating PORESET.

Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies

(GV , LV , and NV ) do not have any ordering requirements with respect to one another.

DD

I/O Voltage (GV_DD, GV_DD, and NV_DD

)

V

Core Voltage (V_DD, V_DDC

)

0.7 V

90%

t

0

PORESET

t_{SYS_CLK_IN PCI_SYNC_IN}

/t

>= 32 clocks

Figure 3. Power-Up Sequencing Example

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

10

3 Power Characteristics

The estimated typical power dissipation, not including I/O supply power, for this family of MPC8313E

devices is shown in this table. Table 5 shows the estimated typical I/O power dissipation.

1

Table 4. MPC8313E Power Dissipation

Core Frequency

(MHz)

CSB Frequency

(MHz)

Maximum for

Typical²

Unit

Rev. 1.0 Silicon³

Rev. 2.x or Later Silicon³

333

400

167

133

820

1020

1200

mW

Note:

1. The values do not include I/O supply power or AV_DD, but do include core, USB PLL, and a portion of SerDes digital power

(not including XCOREV_DD, XPADV_DD, or SDAV_DD, which all have dedicated power supplies for the SerDes PHY).

2. Typical power is based on a voltage of V_DD= 1.05 V and an artificial smoker test running at room temperature.

3. Maximum power is based on a voltage of V_DD= 1.05 V, a junction temperature of T_J= 105C, and an artificial smoker test.

This table describes a typical scenario where blocks with the stated percentage of utilization and

impedances consume the amount of power described.

1

Table 5. MPC8313E Typical I/O Power Dissipation

LV_DDA

LV_DDB

(3.3 V)

/

LV_DDA/

LV_DDB

(2.5 V)

GV_DDGV_DDNV_DD

(1.8 V) (2.5 V) (3.3 V)

LV_DD

(3.3 V)

Interface

Parameter

Unit

Comments

DDR 1, 60% utilization,

50% read/write

R_s= 22 

333 MHz,

32 bits

—

0.355

0.323

—

W

—

266 MHz,

32 bits

—

R_t= 50 

single pair of clock

capacitive load: data = 8 pF,

control address = 8 pF,

clock = 8 pF

DDR 2, 60% utilization,

50% read/write

R_s= 22 

333 MHz,

32 bits

0.266

0.246

—

W

—

266 MHz,

32 bits

R_t= 75 

single pair of clock

capacitive load: data = 8 pF,

control address = 8 pF,

clock = 8 pF

PCI I/O load = 50 pF

33 MHz

66 MHz

50 MHz

—

0.120

0.249

—

W

—

Local bus I/O load = 20 pF

TSEC I/O load = 20 pF

—

0.056

0.040

—

MII,

25 MHz

—

0.008

Multiple by

number of

interface used

RGMII,

—

0.078

0.044

—

W

125 MHz

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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Table 5. MPC8313E Typical I/O Power Dissipation (continued)

LV_DDA

LV_DDB

(3.3 V)

/

LV_DDA/

LV_DDB

(2.5 V)

GV_DDGV_DDNV_DD

(1.8 V) (2.5 V) (3.3 V)

LV_DD

(3.3 V)

Interface

Parameter

Unit

Comments

USBDR controller load = 20 pF

Other I/O

60 MHz

—

0.078

—

W

—

0.015

This table shows the estimated core power dissipation of the MPC8313E while transitioning into the

D3 warm low-power state.

1

Table 6. MPC8313E Low-Power Modes Power Dissipation

2

3

333-MHz Core, 167-MHz CSB

Rev. 1.0

Rev. 2.x or Later

Unit

D3 warm

400

425

mW

Note:

1. All interfaces are enabled. For further power savings, disable the clocks to unused blocks.

2. The interfaces are run at the following frequencies: DDR: 333 MHz, eLBC 83 MHz, PCI 33 MHz,

eTSEC1 and TSEC2: 167 MHz, SEC: 167 MHz, USB: 167 MHz. See the SCCR register for more

information.

3. This is maximum power in D3 Warm based on a voltage of 1.05 V and a junction temperature of 105C.

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8313E.

4.1

DC Electrical Characteristics

This table provides the system clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for

the MPC8313E.

Table 7. SYS_CLK_IN DC Electrical Characteristics

Parameter

Input high voltage

Condition

Symbol

Min

Max

Unit

—

V_IH

V_IL

I_IN

2.4

–0.3

—

NV_DD+ 0.3

0.4

V

Input low voltage

SYS_CLK_IN input current

PCI_SYNC_IN input current

0 V  V_IN NV_DD

±10

A

0 V  V_IN 0.5 V

or

I_IN

—

±10

NV_DD– 0.5 V  V_IN NV_DD

PCI_SYNC_IN input current

0.5 V  V_IN NV_DD– 0.5 V

I_IN

—

±50

A

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

12

4.2

AC Electrical Characteristics

The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,

depending on whether the device is configured in PCI host or PCI agent mode. This table provides the

system clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E.

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Note

SYS_CLK_IN/PCI_CLK frequency

SYS_CLK_IN/PCI_CLK cycle time

SYS_CLK_IN rise and fall time

PCI_CLK rise and fall time

SYS_CLK_IN/PCI_CLK duty cycle

SYS_CLK_IN/PCI_CLK jitter

Notes:

f_{SYS_CLK_IN}

t_{SYS_CLK_IN}

t_KH, t_KL

24

15

0.6

40

—

66.67

—

MHz

ns

1

—

2

0.8

—

4

ns

t_PCH, t_PCL

1.2

60

ns

2

t_{KHK SYS_CLK_IN}

/t

%

3

—

±150

ps

4, 5

1. Caution: The system, core, security block must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYS_CLK_IN/PCI_CLK are measured at 0.4 and 2.4 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be

set low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the MPC8313E.

5.1

RESET DC Electrical Characteristics

This table provides the DC electrical characteristics for the RESET pins.

Table 9. RESET Pins DC Electrical Characteristics

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

2.1

–0.3

—

NV_DD+ 0.3

V

Input low voltage

Input current

—

0.8

±5

I_IN

0 V  V_IN NV_DD

I_OH= –8.0 mA

I_OL= 8.0 mA

A

V

Output high voltage

Output low voltage

V_OH

V_OL

2.4

—

0.5

0.4

V

I

= 3.2 mA

OL

—

V

OL

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

13

5.2

RESET AC Electrical Characteristics

This table provides the reset initialization AC timing specifications.

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Note

Required assertion time of HRESET or SRESET (input) to activate reset flow

32

—

t_{PCI_SYNC_IN}

t_{SYS_CLK_IN}

1

2

Required assertion time of PORESET with stable clock and power applied to

SYS_CLK_IN when the device is in PCI host mode

Required assertion time of PORESET with stable clock and power applied to

PCI_SYNC_IN when the device is in PCI agent mode

32

—

t_{PCI_SYNC_IN}

1

HRESET assertion (output)

512

4

—

t_{PCI_SYNC_IN}

t_{SYS_CLK_IN}

1

2

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]

and CFG_CLK_IN_DIV) with respect to negation of PORESET when the

device is in PCI host mode

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]

and CFG_CLKIN_DIV) with respect to negation of PORESET when the

device is in PCI agent mode

4

—

t_{PCI_SYNC_IN}

1

Input hold time for POR configuration signals with respect to negation of

HRESET

0

—

1

—

4

ns

—

3

Time for the device to turn off POR configuration signal drivers with respect

to the assertion of HRESET

Time for the device to turn on POR configuration signal drivers with respect to

the negation of HRESET

—

t_{PCI_SYNC_IN}

1, 3

Notes:

1. t_{PCI_SYNC_IN}is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the

primary clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.

2. t_{SYS_CLK_IN}is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.

3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

This table provides the PLL lock times.

Table 11. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Note

PLL lock times

—

100

s

—

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that

DDR SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.

DD

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

14

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR2 SDRAM component(s) when

GV (typ) = 1.8 V.

DD

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Note

GV_DD

MV_REF

V_TT

1.7

0.49  GV_DD

MV_REF– 0.04

MV_REF+ 0.125

–0.3

1.9

0.51  GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.125

9.9

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.420 V)

Output low current (V_OUT= 0.280 V)

Notes:

I_OZ

–9.9

A

mA

I_OH

–13.4

—

I_OL

13.4

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5  GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MV_REFmay not exceed ±2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V  V_OUTGV_DD

.

This table provides the DDR2 capacitance when GV (typ) = 1.8 V.

DD

Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V ± 0.090 V, f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

This table provides the recommended operating conditions for the DDR SDRAM component(s) when

GV (typ) = 2.5 V.

DD

Table 14. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Note

GV_DD

MV_REF

V_TT

2.3

2.7

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

0.49  GV_DD

MV_REF– 0.04

MV_REF+ 0.15

–0.3

0.51  GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

3

V_IH

—

Input low voltage

V_IL

MV_REF– 0.15

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

15

Table 14. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V (continued)

DD

Parameter/Condition

Output leakage current

Symbol

Min

Max

Unit

Note

I_OZ

I_OH

I_OL

–9.9

–16.2

16.2

–9.9

—

A

mA

4

Output high current (V_OUT= 1.95 V)

Output low current (V_OUT= 0.35 V)

Note:

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5  GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MV_REFmay not exceed ±2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V  V_OUTGV_DD

.

This table provides the DDR capacitance when GV_DD(typ) = 2.5 V.

Table 15. DDR SDRAM Capacitance for GV (typ) = 2.5 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 2.5 V ± 0.125 V, f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

This table provides the current draw characteristics for MV

.

REF

Table 16. Current Draw Characteristics for MV

REF

Parameter/Condition

Symbol

Min

Max

Unit

Note

Current draw for MV_REF

Note:

I_MVREF

—

500

A

1

1. The voltage regulator for MV_REFmust be able to supply up to 500 A current.

6.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM when GV (typ) = 1.8 V.

DD

Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GV_DDof 1.8 ± 5%.

Parameter

Symbol

Min

Max

Unit

Note

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.25

—

V

—

V_IH

MV_REF+ 0.25

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

16

This table provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 2.5 V.

DD

Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions with GV_DDof 2.5 ± 5%.

Parameter

Symbol

Min

Max

Unit

Note

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.31

—

V

—

V_IH

MV_REF+ 0.31

This table provides the input AC timing specifications for the DDR2 SDRAM interface.

Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions. with GV_DDof 2.5 ± 5%.

Parameter

Symbol

Min

Max

Unit

Note

Controller skew for MDQS—MDQ

t_CISKEW

—

ps

1, 2

333 MHz

266 MHz

Notes:

—

–750

750

—

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW. This can be

determined by the following equation: t_DISKEW= ± (T/4 – abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the

absolute value of t_CISKEW

.

This figure illustrates the DDR input timing diagram showing the t

timing parameter.

DISKEW

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

D0

D1

t_DISKEW

Figure 4. DDR Input Timing Diagram

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

17

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Rev. 1.0 Silicon

Parameter

Symbol ¹

Min

Max

Unit

Note

MCK[n] cycle time, MCK[n]/MCK[n] crossing

t_MCK

6

10

ns

2

3

ADDR/CMD output setup with respect to MCK

t_DDKHAS

333 MHz

266 MHz

2.1

2.5

—

ADDR/CMD output hold with respect to MCK

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3

333 MHz

266 MHz

2.4

3.15

—

MCS[n] output setup with respect to MCK

333 MHz

266 MHz

2.4

3.15

—

MCS[n] output hold with respect to MCK

333 MHz

266 MHz

2.4

3.15

—

MCK to MDQS Skew

–0.6

0.6

ns

ps

4

5

MDQ//MDM output setup with respect to

MDQS

t_DDKHDS,

t_DDKLDS

333 MHz

266 MHz

800

900

—

MDQ//MDM output hold with respect to MDQS

t_DDKHDX,

t_DDKLDX

ps

5

333 MHz

266 MHz

900

1100

—

MDQS preamble start

MDQS epilogue end

Notes:

t_DDKHMP

t_DDKHME

–0.5  t_MCK– 0.6

–0.5  t_MCK+ 0.6

ns

6

–0.6

0.6

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through

control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust

in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the

same adjustment value. See the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, for a

description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t_DDKHMPfollows the

symbol conventions described in note 1.

MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

18

Freescale Semiconductor

Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Silicon Rev 2.x or Later

Parameter

Symbol¹

Min

Max

Unit

Note

MCK[n] cycle time, MCK[n]/MCK[n] crossing

t_MCK

6

10

ns

2

3

ADDR/CMD output setup with respect to MCK

t_DDKHAS

333 MHz

266 MHz

2.1

2.5

—

ADDR/CMD output hold with respect to MCK

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3

333 MHz

266 MHz

2.0

2.7

—

MCS[n] output setup with respect to MCK

333 MHz

266 MHz

2.1

3.15

—

MCS[n] output hold with respect to MCK

333 MHz

266 MHz

2.0

2.7

—

MCK to MDQS Skew

–0.6

0.6

ns

ps

4

5

MDQ//MDM output setup with respect to

MDQS

t_DDKHDS,

t_DDKLDS

333 MHz

266 MHz

800

900

—

MDQ//MDM output hold with respect to MDQS

t_DDKHDX,

t_DDKLDX

ps

5

333 MHz

266 MHz

750

1000