MPC8343EZQADDX [NXP]
32-BIT, 266MHz, MICROPROCESSOR, PBGA620, 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620;
| 型号： | MPC8343EZQADDX |
| 厂家： | 
NXP |
| 描述： | 32-BIT, 266MHz, MICROPROCESSOR, PBGA620, 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620 |
| 文件： | 总92页 (文件大小：987K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC8343EEC
Rev. 6,11/2005
Freescale Semiconductor
Technical Data
MPC8343E PowerQUICC™ II Pro
Integrated Host Processor Hardware
Specifications
Contents
The MPC8343E contains a PowerPC™ processor core with
system logic required for networking, storage, and
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8
general-purpose embedded applications. For functional
3. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11
characteristics of the processor, refer to the MPC8349E
PowerQUICC II™ Pro Integrated Host Processor
Reference Manual, Rev. 1.
5. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Ethernet: Three-Speed Ethernet, MII Management . 22
8. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
To locate any published errata or updates for this document,
contact your Freescale sales office.
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
17. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 55
18. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
19. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
20. System Design Information . . . . . . . . . . . . . . . . . . . 82
21. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 87
22. Document Revision History . . . . . . . . . . . . . . . . . . . 91
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 91
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Overview
1 Overview
This section provides a high-level overview of the MPC8343E features. Figure 1 shows the major
functional units within the MPC8343E.
e300 Core
DUART
Dual I2C
DDR
Timers
GPIO
Interrupt
Controller
32KB
32KB
I-Cache
SDRAM
Security
Local Bus
D-Cache
Controller
High-Speed
USB 2.0
10/100/1000
Ethernet
10/100/1000
Ethernet
SEQ
PCI
DMA
Dual
Role
Figure 1. MPC8343E Block Diagram
Major features of the MPC8343E are as follows:
• Embedded PowerPC processor core; operates at up to 400 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement the PowerPC
architecture
•
DDR SDRAM memory controller
— Programmable timing supporting DDR-1 SDRAM
— 32-bit data interface, up to 333 MHz data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Freescale Semiconductor
Overview
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O
•
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 820.3x, 802.3z, 802.3 AC compliant controllers
— Support for different Ethernet physical interfaces:
– 1000 Mbps IEEE 802.3 RGMII, 802.3z RTBI, full-duplex
– 10/100 Mbps IEEE 802.3 MII full- and half-duplex
— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFO’s per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
PCI interface
•
— PCI specification Revision 2.2 compatible
— Data bus width:
– 32-bit data PCI interface that operates at up to 66 MHz, or
— PCI 3.3-V compatible
— PCI host bridge capabilities
— PCI agent mode supported on PCI interface
— Support for PCI to memory and memory to PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor to PCI and PCI to memory writes
— On-chip arbitration, supporting 5 masters on PCI
— Support for accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle support when target
— Internal configuration registers accessible from PCI
•
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs). The execution units are:
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
3
Overview
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Universal serial bus (USB) dual role controller
— Supports USB on-the-go mode, which includes both device and host functionality
— Complies with USB specification Rev. 2.0
•
— Supports operation as a stand-alone USB device
– Supports one upstream facing port
– Supports six programmable USB endpoints
— Supports operation as a stand-alone USB host controller
– Supports USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
— Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Supports external PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
Local bus controller (LBC)
•
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Four chip selects support four external slaves
— Up to eight-beat burst transfers
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Freescale Semiconductor
Overview
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
•
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin when in core disable mode.
— Unique vector number for each interrupt source
2
•
•
Dual industry-standard I C interfaces
— Two-wire interface
— Multiple master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
2
— System initialization data is optionally loaded from I C-1 EPROM by boot sequencer
embedded hardware
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
DUART
•
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Serial peripheral interface (SPI)
•
•
— Master or slave support
General-purpose parallel I/O (GPIO)
— parallel I/O pins multiplexed on various chip interfaces
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
5
Overview
•
System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
IEEE 1149.1 compliant, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
•
•
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 6
6
Freescale Semiconductor
Overview
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
7
Power Characteristics
2 Power Characteristics
The estimated typical power dissipation for this family of MPC8343E devices is shown in Table 1.
1
Table 1. MPC8343E Power Dissipation
Core
Frequency
(MHz)
CSB
Frequency
(MHz)
Typical at TJ
= 65
,
2
3
Typical
Maximum 4
Unit
266
400
400
266
133
266
133
200
100
1.3
1.1
1.5
1.4
1.5
1.3
1.6
1.4
1.9
1.7
1.8
1.7
1.8
1.6
2.1
1.9
2.0
1.9
W
W
W
W
W
W
PBGA
1
2
The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For IO power values, see Table 2.
Typical power is based on a voltage of Vdd = 1.2 V, a junction temperature of TJ = 105 C, and a Dhrystone benchmark
application.
3
4
Thermal solutions will likely need to design to a value higher than typical power based on the end application, TA
target, and I/O power.
Maximum Power is based on a voltage of Vdd = 1.2 V, worst case process, a junction temperature of TJ = 105 C, and
an artificial smoke test.
Table 2 shows the typical I/O power dissipation for MPC8343E.
Table 2. MPC8343 Typical I/O Power Dissipation
Interface
DDR I/O
Parameter
GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3V) LVDD (2.5V) Unit
Comments
200 MHz, 3-bit
266 MHz, 32-bit
300 MHz, 32-bit
333 MHz, 32-bit
0.42
0.5
W
W
W
W
65% utilization
2.5 V
0.54
0.58
Rs = 20 Ω
Rt = 50 Ω
2 pair of clocks
33 MHz, 32-bit
66 MHz, 32-bit
167 MHz, 32-bit
133 MHz, 32-bit
83 MHz, 32-bit
66 MHz, 32-bit
50 MHz, 32-bit
0.04
0.07
0.34
0.27
0.17
0.14
0.11
W
W
W
W
W
W
W
PCI I/O load = 30pf
Local Bus I/O
Load = 25 pf
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
8
Power Characteristics
Comments
Table 2. MPC8343 Typical I/O Power Dissipation (continued)
Parameter GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3V) LVDD (2.5V) Unit
Interface
MII
Mutiply by number of
interfaces used.
0.01
0.06
W
W
W
W
W
W
TSEC I/O
GMII or TBI
RGMII or RTBI
12 MHz
Load = 25 pf
0.04
0.01
0.2
USB
480 MHz
0.01
Other I/O
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
9
Clock Input Timing
3 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8343E.
3.1
DC Electrical Characteristics
Table 4 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8343E.
Table 3. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
—
VIH
VIL
IIN
2.7
-0.3
—
OVDD+0.3
0.4
V
V
Input low voltage
CLKIN Input current
PCI_SYNC_IN Input current
0V ≤VIN ≤ OVDD
+/- 10
+/- 10
µA
µA
0V ≤VIN ≤ 0.5V or
IIN
—
OVDD - 0.5V ≤VIN ≤ OVDD
PCI_SYNC_IN Input current
0.5V ≤VIN ≤ OVDD - 0.5V
IIN
—
+/- 50
µA
3.2
AC Electrical Characteristics
The primary clock source for the MPC8343E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 4 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the MPC8343E.
Table 4. CLKIN AC Timing Specifications
Parameter/Condition
CLKIN/PCI_CLK frequency
Symbol
Min
Typical
Max
Unit
Notes
fCLKIN
tCLKIN
—
15
0.6
40
—
—
—
66
—
MHz
ns
1
—
2
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
tKH, tKL
1.0
—
1.2
ns
tKHK CLKIN
/t
60
%
3
—
—
+/- 150
ps
4, 5
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum
operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Freescale Semiconductor
RESET Initialization
4 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8343E.
4.1
RESET DC Electrical Characteristics
Table 5 provides the DC electrical characteristics for the RESET pins of the MPC8343E.
Table 5. RESET Pins DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
2.0
OVDD+0.3
V
V
Input low voltage
Input current
-0.3
0.8
5
IIN
µA
V
Output high voltage
Output low voltage
Output low voltage
Notes:
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
4.2
RESET AC Electrical Characteristics
Table 6 provides the reset initialization AC timing specifications of the MPC8343E.
Table 6. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET
(input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable
clock applied to CLKIN when the MPC8343E is in
PCI host mode
32
32
—
—
tCLKIN
2
Required assertion time of PORESET with stable
clock applied to PCI_SYNC_IN when the MPC8343E
is in PCI agent mode
tPCI_SYNC_IN
1
HRESET/SRESET assertion (output)
512
16
4
—
—
—
tPCI_SYNC_IN
tPCI_SYNC_IN
tCLKIN
1
1
2
HRESET negation to SRESET negation (output)
Input setup time for POR config signals
(CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of
PORESET when the MPC8343E is in PCI host mode
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
11
RESET Initialization
Table 6. RESET Initialization Timing Specifications (continued)
Input setup time for POR config signals
4
—
tPCI_SYNC_IN
1
(CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of
PORESET when the MPC8343E is in PCI agent
mode
Input hold time for POR config signals with respect to
negation of HRESET
0
—
1
—
4
ns
ns
Time for the MPC8343Eto turn offPOR config signals
with respect to the assertion of HRESET
3
Time for the MPC8343Eto turn onPOR config signals
with respect to the negation of HRESET
—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8343E is In PCI
host mode the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of
CFG_CLKIN_DIV. See the MPC8349E Integrated Host Processor Reference Manual Rev. 0 for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8343E is in PCI host
mode. See the MPC8349E Integrated Host Processor Reference Manual Rev. 0 for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 7 provides the PLL and DLL lock times.
Table 7. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
DLL lock times
Notes:
—
100
µs
7680
122,880
csb_clk cycles
1, 2
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk).
A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 18, “Clocking,” for more information.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
12
Freescale Semiconductor
RESET Initialization
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
13
DDR SDRAM
5 DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8343E.
5.1
DDR SDRAM DC Electrical Characteristics
Table 8 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8343E.
Table 8. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GVDD
MVREF
VTT
2.375
0.49 × GVDD
MVREF – 0.04
MVREF + 0.18
–0.3
2.625
V
V
1
2
3
I/O reference voltage
0.51 × GVDD
I/O termination voltage
Input high voltage
MVREF + 0.04
V
VIH
GVDD + 0.3
V
Input low voltage
VIL
MVREF – 0.18
V
Output leakage current
Output high current (VOUT = 1.95 V)
Output low current (VOUT = 0.35 V)
MVREF input leakage current
Notes:
IOZ
–10
10
—
—
5
µA
mA
mA
µA
4
IOH
–15.2
IOL
15.2
IVREF
—
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected
to be equal to MVREF. This rail should track variations in the DC level of MVREF
.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD
.
Table 9 provides the DDR capacitance.
Table 9. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note:
CIO
6
8
pF
pF
1
1
CDIO
—
0.5
1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) =
0.2 V.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Freescale Semiconductor
DDR SDRAM
5.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
5.2.1
DDR SDRAM Input AC Timing Specifications
Table 10 provides the input AC timing specifications for the DDR SDRAM interface.
Table 10. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
AC input low voltage
Symbol
Min
Max
Unit
Notes
VIL
VIH
—
MVREF + 0.31
—
MVREF – 0.31
GVDD + 0.3
V
V
AC input high voltage
MDQS—MDQ/MECC input skew per
byte
tDISKEW
ps
1
333 MHz
750
266 MHz
1125
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 <= n <= 7) or ECC (MECC[{0...7}] if n = 8).
5.2.2
DDR SDRAM Output AC Timing Specifications
Table 11 and Table 12 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 11. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
tMCK
6
10
ns
ps
2
3
tAOSKEW
-1000
-1100
-1200
200
300
400
333 MHz
266 MHz
200 MHz
ADDR/CMD output setup with respect to MCK tDDKHAS
—
ns
ns
4
4
2.8
3.45
4.6
333 MHz
266 MHz
200 MHz
ADDR/CMD output hold with respect to MCK
tDDKHAX
—
2.0
2.65
3.8
333 MHz
266 MHz
200 MHz
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
15
DDR SDRAM
Table 11. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCS(n) output setup with respect to MCK
tDDKHCS
tDDKHCX
tDDKHMH
—
ns
4
2.8
3.45
4.6
333 MHz
266 MHz
200 MHz
MCS(n) output hold with respect to MCK
—
ns
ns
ps
4
5
6
2.0
2.65
3.8
333 MHz
266 MHz
200 MHz
MCK to MDQS
-0.9
-1.1
-1.2
0.3
0.5
0.6
333 MHz
266 MHz
200 MHz
MDQ/MECC/MDM output setup with respect
to MDQS
tDDKHDS,
tDDKLDS
—
900
900
1200
333 MHz
266 MHz
200 MHz
MDQ/MECC/MDM output hold with respect to tDDKHDX,
MDQS tDDKLDX
—
ps
6
900
900
1200
333 MHz
266 MHz
200 MHz
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
16
DDR SDRAM
Table 11. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
MDQS preamble start
Symbol 1
Min
Max
Unit
Notes
tDDKHMP -0.25 × tMCK – 0.9 -0.25 × tMCK +0.3
tDDKLME -0.9 0.3
ns
ns
7
7
MDQS epilogue end
Notes:
1.
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can
be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went
invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR
timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data
output hold time.
2.
3.
All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock
Control Register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set
to align the address/command valid with the rising edge of MCK.
4.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
For the ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the
memory clocks by 1/2 applied cycle.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR
timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be
modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode,
this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed
in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8349E
Integrated Host Processor Preliminary Reference Manual Rev.0 for a description and understanding of the
timing modifications enabled by use of these bits.
6.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data
(MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins
of the MPC8343E.
7.
All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8343E. Note that tDDKHMP follows
the symbol conventions described in note 1.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
17
DDR SDRAM
Figure 2 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
tMCK
tAOSKEWmax)
ADDR/CMD
ADDR/CMD
CMD
NOOP
tAOSKEW(min)
CMD
NOOP
Figure 2. Timing Diagram for tAOSKEW Measurement
Figure 3 provides the AC test load for the DDR bus.
Output
GVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 3. DDR AC Test Load
Table 12 shows the DDR SDRAM measurement conditions.
Table 12. DDR SDRAM Measurement Conditions
Symbol DDR
Unit
Notes
VTH
MVREF 0.31 V
V
V
1
2
V
0.5 × GVDD
OUT
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
18
DDR SDRAM
Figure 4 shows the DDR SDRAM output timing diagram for source synchronous mode.
MCK[n]
MCK[n]
tMCK
tDDKHAS DDKHCS
,t
tDDKHAX DDKHCX
,t
ADDR/CMD
Write A0
tDDKHMP
NOOP
tDDKHMH
MDQS[n]
MDQ[x]
tDDKHME
tDDKHDS
tDDKLDS
D0
D1
tDDKLDX
tDDKHDX
Figure 4. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 13 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Table 13. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
9 devices (27 pF)
3.0
3.6
5.0
5.2
ns
ns
ns
ns
36 devices (108 pF) + 40 pF compensation capacitor
36 devices (108 pF) + 80 pF compensation capacitor
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
19
DUART
6 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8343E.
6.1
DUART DC Electrical Characteristics
Table 14 provides the DC electrical characteristics for the DUART interface of the MPC8343E.
Table 14. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
VIH
VIL
IIN
2
OVDD + 0.3
0.8
V
V
–0.3
—
Input current
+/- 5
µA
(0.8V ≤VIN ≤ 2V)
High-level output voltage,
IOH = –100 µA
VOH
OVDD – 0.2
—
—
V
V
Low-level output voltage,
VOL
0.2
IOL = 100 µA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in
Table 55 and Table 56.
6.2
DUART AC Electrical Specifications
Table 15 provides the AC timing parameters for the DUART interface of the MPC8343E.
Table 15. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
256
> 1,000,000
16
baud
baud
—
1
2
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit
values are sampled each 16th sample.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
20
Freescale Semiconductor
DUART
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
21
Ethernet: Three-Speed Ethernet, MII Management
7 Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
7.1
Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—MII/RGMII/RTBI Electrical Characteristics
The electrical characteristics specified here apply to all the MII (media independent interface), RGMII
(reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except MDIO
(management data input/output) and MDC (management data clock). The MII interface is defined for
3.3Vwhile the RGMII and RTBI interfaces can be operated at 3.3 or 2.5 V. The RGMII and RTBI interfaces
follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device
Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in
Section 7.3, “Ethernet Management Interface Electrical Characteristics.”
7.1.1
TSEC DC Electrical Characteristics
All MII, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in
Table 16 and Table 17. The potential applied to the input of a MII, RGMII, or RTBI receiver may exceed
the potential of the receiver’s power supply. The RGMII and RTBI signals are based on a 2.5-V CMOS
interface voltage as defined by JEDEC EIA/JESD8-5.
Table 16. and MII DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
2
Supply voltage 3.3 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
LVDD
—
2.97
2.40
GND
2.0
3.63
LVDD + 0.3
0.50
V
V
VOH
VOL
VIH
VIL
IIH
IOH = –4.0 mA
LVDD = Min
IOL = 4.0 mA
LVDD = Min
V
—
—
—
—
LVDD + 0.3
0.90
V
–0.3
—
V
VIN 1 = LVDD
VIN 1 = GND
40
µA
µA
IIL
–600
—
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 55 and Table 56.
2. MII pins that are not needed for RGMII or RTBI operation are powered by OVDD supply.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
22
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 17. RGMII/RTBI (When Operating at 2.5 V), DC Electrical Characteristics
Parameters
Symbol
Conditions
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
LVDD
VOH
VOL
VIH
VIL
—
2.37
2.00
2.63
LVDD + 0.3
0.40
V
V
IOH = –1.0 mA
LVDD = Min
LVDD = Min
LVDD = Min
LVDD =Min
IOL = 1.0 mA
GND – 0.3
1.7
V
—
—
LVDD + 0.3
0.70
V
–0.3
V
IIH
VIN 1 = LVDD
VIN 1 = GND
—
10
µA
µA
IIL
–15
—
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 55and Table 56.
7.2
MII, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for MII, RGMII, and RTBI are presented in this section.
7.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
7.2.1.1
MII Transmit AC Timing Specifications
Table 18 provides the MII transmit AC timing specifications.
Table 18. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
TX_CLK clock period 100 Mbps
tMTX
tMTX
—
—
400
40
—
5
—
—
ns
ns
%
TX_CLK duty cycle
tMTXH/ MTX
t
35
1
65
15
4.0
4.0
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise VIL(min) to VIH(max)
TX_CLK data clock fall VIH(max) to VIL(min)
Note:
tMTKHDX
tMTXR
tMTXF
ns
ns
ns
1.0
1.0
—
—
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs
(D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters
representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
23
Ethernet: Three-Speed Ethernet, MII Management
Figure 5 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 5. MII Transmit AC Timing Diagram
7.2.1.2
MII Receive AC Timing Specifications
Table 19 provides the MII receive AC timing specifications.
Table 19. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
tMRX
tMRX
—
—
400
40
—
—
—
ns
ns
%
RX_CLK duty cycle
tMRXH MRX
/t
35
65
—
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise VIL(min) to VIH(max)
RX_CLK clock fall time VIH(max) to VIL(min)
Note:
tMRDVKH
tMRDXKH
tMRXR
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
—
—
—
4.0
4.0
tMRXF
—
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V)
relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII
receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference
(K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based
on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the
MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise)
or F (fall).
Figure 6 provides the AC test load for TSEC.
Output
LVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 6. TSEC AC Test Load
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
24
Ethernet: Three-Speed Ethernet, MII Management
Figure 7 shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXF
Valid Data
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRDVKH
tMRDXKH
Figure 7. MII Receive AC Timing Diagram
7.2.2
RGMII and RTBI AC Timing Specifications
Table 20 presents the RGMII and RTBI AC timing specifications.
Table 20. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver) 2
Clock cycle duration 3
tSKRGT
tSKRGT
tRGT
-0.5
1.0
7.2
45
40
—
—
—
0.5
2.8
8.8
55
ns
ns
ns
%
8.0
50
50
—
Duty cycle for 1000Base-T 4, 5
Duty cycle for 10BASE-T and 100BASE-TX 3, 5
Rise time (20%–80%)
tRGTH RGT
tRGTH/tRGT
tRGTR
tRGTF
/t
60
%
0.75
0.75
—
ns
ns
ns
%
Fall time (20%–80%)
—
—
6
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
tG12
—
8.0
—
tG125H G125
/t
47
53
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to
represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock.
Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For
symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than
1.5 ns will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock
domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the
lowest speed transitioned between.
5. Duty cycle reference is LVdd/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming
convention.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
25
Ethernet: Three-Speed Ethernet, MII Management
Figure 8 shows the RBMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
tSKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
tSKRGT
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
tSKRGT
RX_CLK
(At PHY)
Figure 8. RGMII and RTBI AC Timing and Multiplexing Diagrams
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
26
7.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 7.1, “Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—MII/RGMII/RTBI Electrical Characteristics.”
7.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5V or 3.3 V. The DC electrical
characteristics for MDIO and MDC are provided in Table 21 and Table 22.
Table 21. MII Management DC Electrical Characteristics when powered at 2.5V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (2.5 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
LVDD
VOH
VOL
VIH
VIL
—
2.37
2.00
2.63
LVDD + 0.3
0.40
V
V
IOH = –1.0 mA
LVDD = Min
LVDD = Min
LVDD = Min
LVDD = Min
IOL = 1.0 mA
GND - 0.3
1.7
V
—
—
—
V
-0.3
0.70
V
IIH
VIN 1 = LVDD
VIN = LVDD
—
10
µA
µA
IIL
-15
—
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 55 and Table 56.
Table 22. MII Management DC Electrical Characteristics when powered at 3.3V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
LVDD
VOH
VOL
VIH
VIL
—
2.97
2.10
GND
2.00
—
3.63
LVDD + 0.3
0.50
V
V
IOH = –1.0 mA
LVDD = Min
LVDD = Min
IOL = 1.0 mA
V
—
—
—
V
0.80
V
IIH
LVDD = Max
LVDD = Max
VIN 1 = 2.1 V
VIN = 0.5 V
—
40
µA
µA
IIL
–600
—
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 55 and Table 56.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
27
7.3.2
MII Management AC Electrical Specifications
Table 23 provides the MII management AC timing specifications.
Table 23. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V 10% or 2.5 V 5%
Parameter/Condition
MDC frequency
Symbol 1
Min
Typ
Max
Unit
Notes
fMDC
tMDC
—
—
32
10
5
2.5
400
—
—
—
—
70
—
—
10
10
MHz
ns
2
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
tMDCH
ns
tMDKHDX
tMDDVKH
tMDDXKH
tMDCR
—
ns
3
—
ns
0
—
ns
—
—
—
ns
MDC fall time
tMDHF
—
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data
outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect
to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high
(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is
8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz
and the minimum frequency is 1.7 MHz).
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a
csb_clk of 333 MHz, the delay is 58 ns).
Figure 9 shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 9. MII Management Interface Timing Diagram
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
28
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
29
USB
8 USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8343E.
8.1
USB DC Electrical Characteristics
Table 24 provides the DC electrical characteristics for the USB interface.
Table 24. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
VIH
VIL
2
–0.3
OVDD + 0.3
V
V
0.8
5
IIN
—
µA
V
High-level output voltage,
VOH
OVDD – 0.2
—
IOH = –100 µA
Low-level output voltage,
VOL
—
0.2
V
IOL = 100 µA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in
Table 55 and Table 56.
8.2
USB AC Electrical Specifications
Table 25 describes the general timing parameters of the USB interface of the MPC8343E.
Table 25. USB General Timing Parameters
Parameter
usb clock cycle time
Symbol 1
Min
Max
Unit
Notes
tUSCK
tUSIVKH
tUSIXKH
15
4
—
—
—
ns
ns
ns
Input setup to usb clock - all inputs
input hold to usb clock - all inputs
1
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
30
USB
Table 25. USB General Timing Parameters (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
usb clock to output valid - all
outputs
tUSKHOV
—
7
ns
Output hold from usb clock - all
outputs
tUSKHOX
2
—
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of
functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional
block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing
(US) for the input (I) to go invalid (X) with respect to the time the usb clock reference (K)
goes high (H). Also, tUSKHOX symbolizes usb timing (US) for the usb clock reference (K)
to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to usb clock.
3. All signals are measured from OVDD/2 of the rising edge of usb clock to 0.4 × OVDD of the
signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be
when the total current delivered through the component pin is less than or equal to the
leakage current specification.
Figure 10 and Figure 11 provide the AC test load and signals for the USB, respectively.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 10. USB AC Test Load
USB0_CLK/USB1_CLK/DR_CLK
Input Signals
tUSIXKH
tUSIVKH
tUSKHOX
tUSKHOV
Output Signals:
Figure 11. USB Signals
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
31
Local Bus
9 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8343E.
9.1
Local Bus DC Electrical Characteristics
Table 26 provides the DC electrical characteristics for the local bus interface.
Table 26. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
VIH
VIL
2
–0.3
OVDD + 0.3
V
V
0.8
5
IIN
—
µA
V
High-level output voltage,
VOH
OVDD – 0.2
—
I
OH = –100 µA
Low-level output voltage,
VOL
—
0.2
V
IOL = 100 µA
9.2
Local Bus AC Electrical Specification
Table 27 and Table 28 describe the general timing parameters of the local bus interface of the MPC8343E.
Table 27. Local Bus General Timing Parameters—DLL on
Parameter
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
1.5
—
—
ns
ns
2
Input setup to local bus clock
(except LUPWAIT)
tLBIVKH1
3, 4
LUPWAIT input setup to local bus
clock
tLBIVKH2
tLBIXKH1
tLBIXKH2
tLBOTOT1
tLBOTOT2
tLBOTOT3
tLBKHLR
1.7
1.0
1.0
1.5
3
—
—
—
—
—
—
4.5
ns
ns
ns
ns
ns
ns
ns
3, 4
3, 4
3, 4
5
Input hold from local bus clock
(except LUPWAIT)
LUPWAIT Input hold from local bus
clock
LALE output fall to LAD output
transition (LATCH hold time)
LALE output fall to LAD output
transition (LATCH hold time)
6
LALE output fall to LAD output
transition (LATCH hold time)
2.5
—
7
Local bus clock to LALE rise
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
32
Local Bus
Table 27. Local Bus General Timing Parameters—DLL on (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
Local bus clock to output valid
(except LAD/LDP and LALE)
tLBKHOV1
—
4.5
ns
Local bus clock to data valid for
LAD/LDP
tLBKHOV2
—
—
1
4.5
4.5
—
ns
ns
ns
ns
ns
3
3
3
3
Local bus clock to address valid for tLBKHOV3
LAD
Output hold from local bus clock
(except LAD/LDP and LALE)
tLBKHOX1
Output hold from local bus clock for tLBKHOX2
LAD/LDP
1
—
Local bus clock to output high
impedance for LAD/LDP
tLBKHOZ
—
3.8
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of
functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional
block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference
(K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing
(LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going
invalid (X) or output hold time.
2. All timings are in reference to rising edge of LSYNC_IN.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of
the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output
pin is at least 10pF less than the load on LAD output pins.
6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin
is at least 10pF less than the load on LAD output pins.
7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin
equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be
when the total current delivered through the component pin is less than or equal to the
leakage current specification.
Table 28. Local Bus General Timing Parameters—DLL bypass
Parameter
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
7
—
—
—
—
ns
ns
ns
ns
2
Input setup to local bus clock
Input hold from local bus clock
tLBIVKH
tLBIXKH
tLBOTOT1
3, 4
3, 4
5
1.0
1.5
LALE output fall to LAD output
transition (LATCH hold time)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
33
Local Bus
Table 28. Local Bus General Timing Parameters—DLL bypass (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
LALE output fall to LAD output
transition (LATCH hold time)
tLBOTOT2
3
—
ns
6
LALE output fall to LAD output
transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
3
Local bus clock to output valid
tLBKHOV
tLBKHOZ
—
—
3
4
ns
ns
Local bus clock to output high
impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of
functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional
block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference
(K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing
(LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going
invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and
LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD
of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output
pin is at least 10pF less than the load on LAD output pins.
6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin
is at least 10pF less than the load on LAD output pins.
7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin
equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be
when the total current delivered through the component pin is less than or equal to the
leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66MHz.
Figure 12 provides the AC test load for the local bus.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 12. Local Bus C Test Load
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
34
Local Bus
Figure 13 through Figure 18 show the local bus signals.
LSYNC_IN
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
tLBKHOX
tLBKHOV
tLBKHOV
tLBKHOV
tLBKHLR
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
tLBKHOZ
tLBKHOX
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOX
Output (Address) Signal:
LAD[0:31]
tLBOTOT
LALE
Figure 13. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
35
Local Bus
LCLK[n]
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
tLBIVKH
Input Signal:
LGTA
tLBIXKH
tLBKHOV
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
tLBKHOZ
tLBKHOV
Output Signals:
LAD[0:31]/LDP[0:3]
tLBOTOT
LALE
Figure 14. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
LSYNC_IN
T1
T3
tLBKHOZ1
tLBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH2
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ1
tLBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 15. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
36
Freescale Semiconductor
Local Bus
LCLK
T1
T3
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKHOZ
tLBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 16. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
37
Local Bus
LCLK
T1
T2
T3
T4
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKHOZ
tLBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 17. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
38
Freescale Semiconductor
Local Bus
LSYNC_IN
T1
T2
T3
T4
tLBKHOZ1
tLBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH2
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ1
tLBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 18. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
39
JTAG
10 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the MPC8343E.
10.1 JTAG DC Electrical Characteristics
Table 29 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the
MPC8343E.
Table 29. JTAG interface DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
2.5
OVDD+0.3
V
V
Input low voltage
Input current
-0.3
0.8
5
IIN
µA
V
Output high voltage
Output low voltage
Output low voltage
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
10.2 JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8343E.
Table 30 provides the JTAG AC timing specifications as defined in Figure 20 through Figure 23.
1
Table 30. JTAG AC Timing Specifications (Independent of CLKIN)
At recommended operating conditions (see Table 56).
Parameter
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
fJTG
t JTG
0
33.3
—
MHz
ns
30
15
0
tJTKHKL
tJTGR & tJTGF
tTRST
—
ns
2
ns
25
—
ns
3
4
Input setup times:
ns
tJTDVKH
tJTIVKH
4
4
—
—
Boundary-scan data
TMS, TDI
Input hold times:
ns
ns
tJTDXKH
tJTIXKH
10
10
—
—
4
5
Boundary-scan data
TMS, TDI
Valid times:
tJTKLDV
tJTKLOV
2
2
11
11
Boundary-scan data
TDO
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
40
JTAG
1
Table 30. JTAG AC Timing Specifications (Independent of CLKIN) (continued)
At recommended operating conditions (see Table 56).
Parameter
Symbol 2
Min
Max
Unit
Notes
Output hold times:
ns
tJTKLDX
tJTKLOX
2
2
—
—
5
Boundary-scan data
TDO
JTAG external clock to output high impedance:
Boundary-scan data
TDO
ns
tJTKLDZ
tJTKLOZ
2
2
19
9
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 19). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
(V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K)
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK
.
5. Non-JTAG signal output timing with respect to tTCLK
.
6. Guaranteed by design and characterization.
Figure 19 provides the AC test load for TDO and the boundary-scan outputs of the MPC8343E.
Z0 = 50 Ω
Output
OVDD/2
RL = 50 Ω
Figure 19. AC Test Load for the JTAG Interface
Figure 20 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
tJTKHKL
VM
VM
tJTGR
tJTGF
tJTG
VM = Midpoint Voltage (OV /2)
DD
Figure 20. JTAG Clock Input Timing Diagram
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
41
JTAG
Figure 21 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OV /2)
DD
Figure 21. TRST Timing Diagram
Figure 22 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Output Data Valid
Boundary
Data Outputs
VM = Midpoint Voltage (OV /2)
DD
Figure 22. Boundary-Scan Timing Diagram
Figure 23 provides the test access port timing diagram.
JTAG
VM
VM
External Clock
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOV
tJTKLOX
TDO
Output Data Valid
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 23. Test Access Port Timing Diagram
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
42
JTAG
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
43
I2C
11 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the MPC8343E.
2
11.1 I C DC Electrical Characteristics
Table 31 provides the DC electrical characteristics for the I C interface of the MPC8343E.
2
2
Table 31. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 10%.
Parameter
Input high voltage level
Symbol
Min
Max
Unit
Notes
VIH
VIL
0.7 × OVDD
OVDD+ 0.3
0.3 × OVDD
0.2 × OVDD
250
V
V
Input low voltage level
Low level output voltage
–0.3
0
VOL
V
1
2
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10 to 400 pF
t
20 + 0.1 × CB
ns
I2KLKV
Pulse width of spikes which must be suppressed
by the input filter
tI2KHKL
0
50
10
10
ns
µA
pF
3
4
Input current each I/O pin (input voltage is
between 0.1 × OVDD and 0.9 × OVDD(max)
II
–10
—
Capacitance for each I/O pin
CI
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8349E Integrated Host Processor Reference Manual Rev.0 for information on the digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
2
11.2 I C AC Electrical Specifications
2
Table 32 provides the AC timing parameters for the I C interface of the MPC8343E. Note that all values
refer to V (min) and V (max) levels (see Table 31).
IH
IL
2
Table 32. I C AC Electrical Specifications
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
tI2CL
0
400
—
kHz
µs
Low period of the SCL clock
1.3
0.6
0.6
0.6
High period of the SCL clock
tI2CH
—
µs
Setup time for a repeated START condition
tI2SVKH
tI2SXKL
—
µs
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
—
µs
Data setup time
tI2DVKH
100
—
ns
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
44
I2C
2
Table 32. I C AC Electrical Specifications (continued)
Parameter
Symbol 1
Min
Max
Unit
Data hold time:
tI2DXKL
µs
—
—
CBUS compatible masters
I2C bus devices
0 2
0.9 3
4
4
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
tI2CR
20 + 0.1 Cb
20 + 0.1 Cb
0.6
300
300
—
ns
ns
µs
µs
V
t
I2CF
t
I2PVKH
Bus free time between a STOP and START condition
tI2KHDX
VNL
1.3
—
Noise margin at the LOW level for each connected device
(including hysteresis)
0.1 × OVDD
—
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2 × OVDD
—
V
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C
clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that
the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low
(L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop
condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. MPC8343E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
2
Figure 24 provides the AC test load for the I C.
Output
OVDD/2
Z0 = 50 Ω
RL = 50 Ω
2
Figure 24. I C AC Test Load
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
45
I2C
2
Figure 25 shows the AC timing diagram for the I C bus.
SDA
tI2CF
tI2CL
tI2DVKH
tI2KHKL
tI2CF
tI2SXKL
tI2CR
SCL
tI2SXKL
tI2CH
tI2SVKH
tI2PVKH
tI2DXKL
S
Sr
P
S
2
Figure 25. I C Bus AC Timing Diagram
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
46
PCI
12 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8343E.
12.1 PCI DC Electrical Characteristics
Table 33 provides the DC electrical characteristics for the PCI interface of the MPC8343E.
1
Table 33. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
VIH
VIL
VOUT ≥ VOH (min) or
VOUT ≤ VOL (max)
2
–0.3
OVDD + 0.3
V
V
0.8
5
IIN
VIN 2 = 0 V or VIN = VDD
—
µA
V
High-level output voltage
VOH
OVDD = min,
OVDD – 0.2
—
IOH = –100 µA
Low-level output voltage
VOL
OVDD = min,
—
0.2
V
IOL = 100 µA
Notes:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 55 and Table 56.
12.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8343E. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8343E
is configured as a host or agent device. Table 34 provides the PCI AC timing specifications at 66 MHz.
6
Table 34. PCI AC Timing Specifications at 66 MHz
Parameter
Clock to output valid
Symbol 1
Min
Max
Unit
Notes
t
—
1
6.0
—
ns
ns
ns
2
2
PCKHOV
Output hold from Clock
t
PCKHOX
Clock to output high impedance
tPCKHOZ
—
14
2, 3
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
47
PCI
6
Table 34. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
Input setup to Clock
tPCIVKH
tPCIXKH
3.0
0
—
—
ns
ns
2, 4
2, 4
Input hold from Clock
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
6. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to User Manual, PCI chapter, description
of M66EN paragraph.
Table 35 provides the PCI AC timing specifications at 33 MHz.
Table 35. PCI AC Timing Specifications at 33 MHz
Parameter
Clock to output valid
Symbol 1
Min
Max
Unit
Notes
t
—
2
11
—
14
—
—
ns
ns
ns
ns
ns
2
PCKHOV
Output hold from Clock
Clock to output high impedance
Input setup to Clock
Input hold from Clock
Notes:
2
t
PCKHOX
tPCKHOZ
tPCIVKH
tPCIXKH
—
3.0
0
2, 3
2, 4
2, 4
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Freescale Semiconductor
PCI
Figure 26 provides the AC test load for PCI.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 26. PCI AC Test Load
Figure 27 shows the PCI input AC timing diagram.
CLK
tPCIVKH
tPCIXKH
Input
Figure 27. PCI Input AC Timing Diagram
Figure 28 shows the PCI output AC timing diagram.
CLK
tPCKHOV
tPCKHOX
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 28. PCI Output AC Timing Diagram
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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49
Timers
13 Timers
This section describes the DC and AC electrical specifications for the Timers of the MPC8343E.
13.1 Timers DC Electrical Characteristics
Table 36 provides the DC electrical characteristics for the MPC8343E Timers pins, including TIN, TOUT,
TGATE and RTC_CLK.
Table 36. Timers DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
2.0
OVDD+0.3
V
V
Input low voltage
Input current
-0.3
0.8
5
IIN
µA
V
Output high voltage
Output low voltage
Output low voltage
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
13.2 Timers AC Timing Specifications
Table 37 provides the Timers input and output AC timing specifications.
1
Table 37. Timers Input AC Timing Specifications
Characteristic
Symbol 2
Min
Unit
ns
Timers inputs—minimum pulse width
Notes:
tTIWID
20
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2.Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use
by any external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper
operation.
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Freescale Semiconductor
GPIO
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8343E.
14.1 GPIO DC Electrical Characteristics
Table 38 provides the DC electrical characteristics for the MPC8343E GPIO.
Table 38. GPIO DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
2.0
OVDD+0.3
V
V
Input low voltage
Input current
-0.3
0.8
5
IIN
µA
V
Output high voltage
Output low voltage
Output low voltage
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
14.2 GPIO AC Timing Specifications
Table 39 provides the GPIO input and output AC timing specifications.
1
Table 39. GPIO Input AC Timing Specifications
Characteristic
Symbol 2
Min
Unit
ns
GPIO inputs—minimum pulse width
Notes:
tPIWID
20
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2.GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use
by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper
operation.
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51
IPIC
15 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the
MPC8343E.
15.1 IPIC DC Electrical Characteristics
Table 40 provides the DC electrical characteristics for the external interrupt pins of the MPC8343E.
Table 40. IPIC DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
IIN
2.0
OVDD+0.3
V
V
Input low voltage
Input current
-0.3
0.8
5
µA
V
Output low voltage
Output low voltage
Notes:
VOL
IOL = 8.0 mA
—
—
0.5
0.4
V
I
= 3.2 mA
OL
V
OL
1. This table applies for pins IRQ[0:7], IRQ_OUT and MCP_OUT.
2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
15.2 IPIC AC Timing Specifications
Table 41 provides the IPIC input and output AC timing specifications.
1
Table 41. IPIC Input AC Timing Specifications
Characteristic
Symbol 2
Min
Unit
ns
IPIC inputs—minimum pulse width
Notes:
tPICWID
20
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2.IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by
any external synchronous logic. IPIC inputs are required to be valid for at least tPICWID ns to ensure proper operation
when working in edge triggered mode.
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Freescale Semiconductor
SPI
16 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8343E.
16.1 SPI DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the MPC8343E SPI.
Table 42. SPI DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
2.0
OVDD+0.3
V
V
Input low voltage
Input current
-0.3
0.8
5
IIN
µA
V
Output high voltage
Output low voltage
Output low voltage
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
16.2 SPI AC Timing Specifications
Table 43 and provide the SPI input and output AC timing specifications.
1
Table 43. SPI AC Timing Specifications
Characteristic
Symbol 2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
SPI outputs hold—Master mode (internal clock) delay
SPI outputs valid—Slave mode (external clock) delay
SPI outputs hold—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock input setup time
SPI inputs—Master mode (internal clock input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Notes:
tNIKHOV
tNIKHOX
tNEKHOV
tNEKHOX
tNIIVKH
6
ns
ns
ns
ns
ns
ns
ns
ns
0.5
8
2
4
0
4
2
tNIIXKH
tNEIVKH
tNEIXKH
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until
outputs (O) are invalid (X).
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
53
SPI
Figure 29 provides the AC test load for the SPI.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 29. SPI AC Test Load
Figure 30 through Figure 31 represent the AC timing from Table 43. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 30 shows the SPI timing in Slave mode (external clock).
SPICLK (input)
tNEIXKH
tNEIVKH
Input Signals:
SPIMOSI
(See Note)
tNEKHOX
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 30. SPI AC Timing in Slave mode (External Clock) Diagram
Figure 31 shows the SPI timing in Master mode (internal clock).
SPICLK (output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOX
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 31. SPI AC Timing in Master mode (Internal Clock) Diagram
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Package and Pin Listings
17 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8343E is available in
a plastic ball grid array (PBGA), see Section 17.1, “Package Parameters for the MPC8343E PBGA,”and
Section 17.2, “Mechanical Dimensions of the MPC8343E PBGA,” on the PBGA.
17.1 Package Parameters for the MPC8343E PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 620
Plastic ball grid array (PBGA).
Package outline
29 mm × 29 mm
Interconnects
620
Pitch
1.00 mm
Module height (maximum)
Module height (typical)
Module height (minimum)
Solder Balls
2.46 mm
2.23 mm
2.00 mm
62 Sn/36 Pb/2 Ag (ZQ package)
95.5 Sn/0.5 Cu/4Ag (VR package)
0.60 mm
Ball diameter (typical)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Package and Pin Listings
17.2 Mechanical Dimensions of the MPC8343E PBGA
Figure 32 the mechanical dimensions and bottom surface nomenclature of the MPC8343E, 620-PBGA
package.
Figure 32. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8343E PBGA
NOTE
1. All dimensions in millimeters
2. Dimensioning and tolerancing per ASME Y14. 5M-1994
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Package and Pin Listings
3. Maximum solder ball diameter measured parallel to datum A
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
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17.3 Pinout Listings
Table 44 provides the pin-out listing for the MPC8343E, 620 PBGA package.
Table 44. MPC8343E (PBGA) Pinout Listing
Power
Supply
Signal
Package Pin Number
PCI
Pin Type
Notes
PCI1_INTA/IRQ_OUT
PCI1_RESET_OUT
PCI1_AD[31:0]
D20
B21
O
O
OVDD
OVDD
OVDD
2
E19, D17, A16, A18, B17, B16, D16, B18,
E17, E16, A15, C16, D15, D14, C14, A12,
D12, B11, C11, E12, A10, C10, A9, E11,
E10, B9, B8, D9, A8, C9, D8, C8
I/O
PCI1_C/BE[3:0]
PCI1_PAR
A17, A14, A11, B10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
D13
PCI1_FRAME
PCI1_TRDY
B14
5
5
5
5
5
A13
PCI1_IRDY
E13
PCI1_STOP
C13
PCI1_DEVSEL
PCI1_IDSEL
B13
C17
PCI1_SERR
C12
I/O
I/O
I/O
I
5
5
PCI1_PERR
B12
PCI1_REQ[0]
A21
PCI1_REQ[1]/CPCI1_HS_ES
PCI1_REQ[2:4]
PCI1_GNT0
C19
C18, A19, E20
B20
I
I/O
O
PCI1_GNT1/CPCI1_HS_LED
C20
PCI1_GNT2/CPCI1_HS_ENUM B19
O
PCI1_GNT[3:4]
M66EN
A20, E18
L26
O
I
DDR SDRAM Memory Interface
MDQ[0:31]
AC25, AD27, AD25, AH27, AE28, AD26,
AD24, AF27, AF25, AF28, AH24, AG26,
AE25, AG25, AH26, AH25, AG22, AH22,
AE21, AD19, AE22, AF23, AE19, AG20,
AG19, AD17, AE16, AF16, AF18, AG18,
AH17, AH16
I/O
GVDD
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Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
MECC[0:4]/MSRCID[0:4]
MECC[5]/MDVAL
MECC[6:7]
AG13, AE14, AH12, AH10, AE15
AH14
I/O
I/O
I/O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
AE13, AH11
MDM[0:3]
AG28, AG24, AF20, AG17
AG12
MDM[8]
O
MDQS[0:3]
MDQS[8]
AE27, AE26, AE20, AH18
AH13
I/O
I/O
O
MBA[0:1]
AF10, AF11
MA[0:14]
AF13, AF15, AG16, AD16, AF17, AH20,
AH19, AH21, AD18, AG21, AD13, AF21,
AF22, AE1, AA5
O
MWE
AD10
O
O
O
O
O
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
MRAS
AF7
MCAS
AG6
MCS[0:3]
MCKE[0:1]
MCK[0:3]
MCK[0:3]
AE7, AH7, AH4, AF2
AG23, AH23
3
AH15, AE24, AE2, AF14
AG15, AD23, AE3, AG14
Local Bus Controller Interface
LAD[0:31]
T4, T5, T1, R2, R3, T2, R1, R4, P1, P2, P3,
P4, N1, N4, N2, N3, M1, M2, M3, N5, M4,
L1, L2, L3, K1, M5, K2, K3, J1, J2, L5, J3
I/O
OVDD
LDP[0]/CKSTOP_OUT
LDP[1]/CKSTOP_IN
LDP[2]
H1
I/O
I/O
I/O
I/O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
K5
H2
LDP[3]
G1
LA[27:31]
J4, H3, G2, F1, G3
J5, H4, F2, E1
F3, G4, D1, E2
LCS[0:3]
O
LWE[0:3]/LSDDQM[0:3]/
LBS[0:3]
O
LBCTL
H5
E3
F4
O
O
OVDD
OVDD
OVDD
LALE
LGPL0/LSDA10/
I/O
cfg_reset_source0
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
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Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
LGPL1/LSDWE/
Package Pin Number
Pin Type
Notes
D2
C1
I/O
OVDD
OVDD
cfg_reset_source1
LGPL2/
O
LSDRAS/LOE
LGPL3/LSDCAS/
cfg_reset_source2
C2
I/O
OVDD
LGPL4/LGTA/LUPWAIT/LPBSE C3
I/O
I/O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
LGPL5/cfg_clkin_div
LCKE
B3
E4
LCLK[0:2]
D4, A3, C4
O
LSYNC_OUT
LSYNC_IN
U3
Y2
O
I
General Purpose I/O Timers
GPIO1[0]/
GTM1_TIN1/
GTM2_TIN2
D27
E26
I/O
I/O
OVDD
OVDD
GPIO1[1]/
GTM1_TGATE1/
GTM2_TGATE2
GPIO1[2]/
GTM1_TOUT1
D28
G25
I/O
I/O
OVDD
OVDD
GPIO1[3]/
GTM1_TIN2/
GTM2_TIN1
GPIO1[4]/
GTM1_TGATE2/
GTM2_TGATE1
J24
F26
E27
E28
H25
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
GPIO1[5]/
GTM1_TOUT2/
GTM2_TOUT1
GPIO1[6]/
GTM1_TIN3/
GTM2_TIN4
GPIO1[7]/
GTM1_TGATE3/
GTM2_TGATE4
GPIO1[8]/
GTM1_TOUT3
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Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
GPIO1[9]/
GTM1_TIN4/
GTM2_TIN3
F27
K24
G26
I/O
OVDD
OVDD
OVDD
GPIO1[10]/
GTM1_TGATE4/
GTM2_TGATE3
I/O
I/O
GPIO1[11]/
GTM1_TOUT4/
GTM2_TOUT3
USB
DR_D0_ENABLEN
DR_D1_SER_TXD
DR_D2_VMO_SE0
DR_D3_SPEED
C28
F25
B28
C27
D26
E25
C26
D25
B26
E24
A27
C25
A26
B25
A25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
DR_D4_DP
DR_D5_DM
DR_D6_SER_RCV
DR_D7_DRVVBUS
DR_SESS_VLD_NXT
DR_XCVR_SEL_DPPULLUP
DR_STP_SUSPEND
DR_RX_ERROR_PWRFAULT
DR_TX_VALID_PCTL0
DR_TX_VALIDH_PCTL1
DR_CLK
I/O
O
I
O
O
I
Programmable Interrupt Controller
MCP_OUT
E8
O
OVDD
OVDD
OVDD
OVDD
2
IRQ0/MCP_IN/GPIO2[12]
IRQ[1:5]/GPIO2[13:17]
J28
I/O
I/O
I/O
K25, J25, H26, L24, G27
G28
IRQ[6]/GPIO2[18]/
CKSTOP_OUT
IRQ[7]/GPIO2[19]/
CKSTOP_IN
J26
I/O
OVDD
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Freescale Semiconductor
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Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
Ethernet Management Interface
EC_MDC
EC_MDIO
Y24
Y25
O
LVDD1
LVDD1
I/O
2
Gigabit Reference Clock
EC_GTX_CLK125
Y26
I
LVDD1
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_COL/GPIO2[20]
TSEC1_CRS/GPIO2[21]
TSEC1_GTX_CLK
TSEC1_RX_CLK
M26
I/O
OVDD
LVDD1
LVDD1
LVDD1
LVDD1
OVDD
LVDD1
OVDD
LVDD1
LVDD1
OVDD
U25
I/O
O
I
V24
3
U26
TSEC1_RX_DV
U24
I
TSEC1_RX_ER/GPIO2[26]
TSEC1_RXD[3:0]
L28
I/O
I
W26, W24, Y28, Y27
TSEC1_TX_CLK
N25
I
TSEC1_TXD[3:0]
V28, V27, V26, W28
O
O
I/O
TSEC1_TX_EN
W27
N24
TSEC1_TX_ER/GPIO2[31]
Three-Speed Ethernet Controller (Gigabit Ethernet 2)
TSEC2_COL/GPIO1[21]
TSEC2_CRS/GPIO1[22]
TSEC2_GTX_CLK
P28
I/O
OVDD
LVDD2
LVDD2
LVDD2
LVDD2
LVDD2
OVDD
LVDD2
OVDD
LVDD2
OVDD
AC28
AC27
AB25
AC26
I/O
O
TSEC2_RX_CLK
I
TSEC2_RX_DV/GPIO1[23]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TSEC2_RXD[3:0]/GPIO1[13:16] AA25, AA26, AA27, AA28
TSEC2_RX_ER/GPIO1[25] R25
TSEC2_TXD[3:0]/GPIO1[17:20] AB26, AB27, AA24, AB28
TSEC2_TX_ER/GPIO1[24]
TSEC2_TX_EN/GPIO1[12]
TSEC2_TX_CLK/GPIO1[30]
R27
AD28
R26
3
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
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Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
DUART
Pin Type
Notes
UART_SOUT[1:2]/
MSRCID[0:1]/LSRCID[0:1]
B4, A4
D5, C5
B5
O
OVDD
OVDD
OVDD
OVDD
OVDD
UART_SIN[1:2]/
MSRCID[2:3]/LSRCID[2:3]
I/O
I/O
I/O
O
UART_CTS[1]/
MSRCID4/LSRCID4
UART_CTS[2]/
MDVAL/ LDVAL
A5
UART_RTS[1:2]
D6, C6
I2C interface
IIC1_SDA
IIC1_SCL
IIC2_SDA
IIC2_SCL
E5
A6
B6
E7
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
2
2
2
2
SPI
SPIMOSI
SPIMISO
SPICLK
SPISEL
D7
C7
B7
A7
I/O
I/O
I/O
I
OVDD
OVDD
OVDD
OVDD
Clocks
PCI_CLK_OUT[0:4]
PCI_SYNC_IN/PCI_CLOCK
PCI_SYNC_OUT
RTC/PIT_CLOCK
CLKIN
Y1, W3, W2, W1, V3
O
I
OVDD
OVDD
OVDD
OVDD
OVDD
U4
U5
E9
W5
O
I
3
I
JTAG
TCK
TDI
H27
H28
M24
J27
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
4
3
4
4
TDO
TMS
TRST
O
I
K26
I
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
63
Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Test
Pin Type
Notes
TEST
F28
T3
I
I
OVDD
OVDD
6
7
TEST_SEL
PMC
QUIESCE
K27
O
OVDD
System Control
PORESET
HRESET
SRESET
K28
M25
L27
I
OVDD
OVDD
OVDD
I/O
I/O
1
2
Thermal Management
THERM0
B15
I
—
9
Power and Ground Signals
AVDD
AVDD
1
2
C15
U1
Power for e300
PLL (1.2 V)
AVDD
AVDD
1
2
Power for
system PLL
(1.2 V)
AVDD3
AF9
U2
Power for DDR
DLL (1.2 V)
AVDD
AVDD
—
3
4
AVDD
GND
4
Power for LBIU
DLL (1.2 V)
A2, B1, B2, D10, D18, E6, E14, E22, F9,
F12, F15, F18, F21, F24, G5, H6, J23, L4,
L6, L12, L13, L14, L15, L16, L17, M11, M12,
M13, M14, M15, M16, M17, M18, M23, N11,
N12, N13, N14, N15, N16, N17, N18, P6,
P11, P12, P13, P14, P15, P16, P17, P18,
P24, R5, R23, R11, R12, R13, R14, R15,
R16, R17, R18, T11, T12, T13, T14, T15,
T16, T17, T18, U6, U11, U12, U13, U14,
U15, U16, U17, U18, V12, V13, V14, V15,
V16, V17, V23, V25, W4, Y6, AA23, AB24,
AC5, AC8, AC11, AC14, AC17, AC20, AD9,
AD15, AD21, AE12, AE18, AF3, AF26
—
GVDD
U9, V9, W10, W19, Y11, Y12, Y14, Y15,
Y17, Y18, AA6, AB5, AC9, AC12, AC15,
AC18, AC21, AC24, AD6, AD8, AD14,
AD20, AE5, AE11, AE17, AG2, AG27
Power for DDR
DRAM I/O
Voltage
GVDD
(2.5 V)
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
64
Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
LVDD1
U20, W25
Power for
Three Speed
Ethernet #1
and for
LVDD1
Ethernet
Management
Interface I/O
(2.5V, 3.3V)
LVDD2
V20, Y23
Power for
Three Speed
Ethernet#2I/O
(2.5V, 3.3V)
LVDD2
VDD
J11, J12, J15, K10, K11, K12, K13, K14,
K15, K16, K17, K18, K19, L10, L11, L18,
L19, M10, M19, N10, N19, P9, P10, P19,
R10, R19, R20, T10, T19, U10, U19, V10,
V11, V18, V19, W11, W12, W13, W14, W15,
W16, W17, W18
Power for Core
(1.2 V)
VDD
OVDD
B27, D3, D11, D19, E15, E23, F5, F8, F11,
PCI, 10/100
OVDD
F14, F17, F20, G24, H23, H24, J6, J14, J17, Ethernet, and
J18, K4, L9, L20, L23, L25, M6, M9, M20,
P5, P20, P23, R6, R9, R24, U23, V4, V6
other Standard
(3.3 V)
MVREF1
MVREF2
AF19
I
I
DDR
Reference
Voltage
AE10
DDR
Reference
Voltage
No Connection
NC
A22, A23, A24, B22, B23, B24, C21, C22,
C23, C24, D21, D22, D23, D24, E21, M27,
M28, N26, N27, N28, P25, P26, P27, R28,
T24, T25, T26, T27, T28, U27, U28, Y3, Y4,
Y5, AA1, AA2, AA3, AA4, AB1, AB2, AB3,
AB4, AC1, AC2, AC3, AC4, AD1, AD2, AD3,
AD5, AD7, AD11, AD12, AE4, AE6, AE8,
AE9, AE23, AF1, AF5, AF6, AF8, AF24,
AG1, AG3, AG4, AG7, AG8, AG9, AG10,
AH2, AH3, AH5, AH8, AH9, V5, V2, V1
Pins Reserved for future DDR2
(they should be left unconnected for MPC8343)
ODT[0:3]
MBA[2]
AG5, AD4, AH6, AF4
AD22
—
—
—
—
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
65
Table 44. MPC8343E (PBGA) Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
SPARE1
SPARE2
Notes:
AF12
AG11
—
—
—
—
8
6
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
.
5.This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. This pin must be always be tied to GND
7. This pin must always be pulled up to OVDD
8. This pin must always be left no connected
9. Thermal sensitive resistor.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
66
Freescale Semiconductor
Clocking
18 Clocking
Figure 33 shows the internal distribution of clocks within the MPC8343E.
MPC8343E
e300 core
core_clk
Core PLL
csb_clk
to DDR
memory
controller
4
4
DDR
DDR
Memory
Device
MCK[0:3]
MCK[0:3]
Clock
Div
/2
ddr_clk
lbiu_clk
Clock
Unit
System PLL
/n
LCLK[0:2]
to local bus
memory
Local Bus
Memory
Device
LBIU
DLL
LSYNC_OUT
LSYNC_IN
controller
csb_clk to rest
of the device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
5
PCI_CLK_OUT[0:4]
Figure 33. MPC8343E Clock Subsystem
The primary clock source for the MPC8343E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. When the MPC8343E is configured
as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn]
parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8343E to function. When the
MPC8343E is configured as a PCI agent device, PCI_CLK is the primary input clock. When the
MPC8343E is configured as a PCI agent device the CLKIN signal should be tied to GND.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
67
Clocking
As shown in Figure 33, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8349E Reference Manual for more information on the clock
subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM]
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWL[LBIUCM]
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the a LBIU clock divider
to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider
ratio is controlled by LCCR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 45 specifies which units have a configurable clock
frequency.
Table 45. Configurable Clock Units
Default
Frequency
Unit
Options
TSEC2, I2C1
Security Core
csb_clk/3
csb_clk/3
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
PCI and DMA complex
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
68
Table 45 provides the operating frequencies for the MPC8343E PBGA under recommended operating
conditions (see).
Table 45. Operating Frequencies for PBGA
1
Characteristic
266 MHz
333 MHz
400 MHz
Unit
e300 core frequency (core_clk)
200–266
200–333
100–333
200–400
MHz
MHz
Coherent system bus frequency
(csb_clk)
DDR memory bus frequency
100–166.67
16.67–133
MHz
MHz
2
(MCLK)
Local bus frequency
3
(LCLKn)
PCI input frequency (CLKIN or
PCI_CLK)
25–66
133
MHz
MHz
MHz
Security core maximum internal
operating frequency
USB_DR, USB_MPH maximum
internal operating frequency
133
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the
resulting ccb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum
or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and
SCCR[USBMPHCM] must be programmed such that the maximum internal operating frequency of the
Security core and USB modules will not exceed their respective value listed in this table.
2
3
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which
is in turn 1x or 2x the ccb_clk frequency (depending on RCWL[LBIUCM]).
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
69
17.4 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 46 shows the multiplication factor
encodings for the system PLL.
Table 46. System PLL Multiplication Factors
System PLL Multiplication
RCWL[SPMF]
Factor
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
× 16
Reserved
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
70
Clocking
As described in Section 18, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 48
and Table 49 shows the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
Table 48. CSB Frequency Options for host mode
Input Clock Frequency (MHz)2
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
16.67
25
33.33
66.67
at reset 1
2
Ratio
csb_clk Frequency (MHz)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0010
0011
0100
0101
0110
0111
1000
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
7 : 1
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
7 : 1
8 : 1
133
200
266
333
100
100
125
150
175
200
225
250
275
300
325
133
166
200
233
266
300
333
100
116
133
150
166
183
200
216
233
250
266
133
200
266
333
100
133
166
200
233
1
2
CFG_CLKIN_DIV select the ratio between CLKIN and PCI_SYNC_OUT.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
71
Clocking
Table 49. CSB Frequency Options for Agent Mode
Input Clock Frequency (MHz)2
csb_clk :
CFG_CLKIN_DIV
at reset 1
SPMF
Input Clock
16.67
25
33.33
66.67
2
Ratio
csb_clk Frequency (MHz)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
high
High
High
High
High
High
High
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0010
0011
0100
0101
0110
0111
1000
2 : 1
3 : 1
133
200
266
333
100
4 : 1
100
125
150
175
200
225
250
275
300
325
133
166
200
233
266
300
333
5 : 1
6 : 1
100
116
133
150
166
183
200
216
233
250
266
7 : 1
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
4 : 1
100
150
200
250
300
133
200
266
333
266
6 : 1
100
133
166
200
233
266
8 : 1
10 : 1
12 : 1
14 : 1
16 : 1
1
2
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
18.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 50 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 50 should be considered as reserved.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
72
Freescale Semiconductor
Clocking
NOTE
Core VCO frequency = Core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
Table 50. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO divider 1
0-1
nn
2-5
6
0000
n
PLL bypassed
PLL bypassed
(PLL off, csb_clk clocks
core directly)
(PLL off, csb_clk clocks
core directly)
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1:1
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
1:1
1:1
1:1
1.5:1
1.5:1
1.5:1
1.5:1
2:1
2:1
2:1
2:1
2.5:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
3:1
1
Core VCO frequency = Core frequency × VCO divider. Note that VCO divider
has
to be set properly so that the core VCO frequency is in the range of 800–1800 MHz.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
73
Clocking
18.3 Suggested PLL Configurations
Table 51 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks, when
CFG_CLKIN_DIV is low at reset.
Table 51. Suggested PLL Configurations
Ref
No.
RCWL
266 MHz Device
333 MHz Device
400 MHz Device
1
Input
Clock
Freq
Input
Input
CSB
Freq
(MHz)
Core
Freq
(MHz)
CSB
Freq
(MHz)
Core
Freq
(MHz)
CSB
Freq
(MHz)
Core
Freq
(MHz)
CORE
PLL
Clock
Freq
Clock
Freq
SPMF
2
2
2
(MHz)
(MHz)
(MHz)
33 MHz CLKIN/PCI_CLK Options
343
324
423
622
523
424
822
326
623
922
425
524
A22
723
604
624
0011
0011
0100
0110
0101
0100
1000
0011
0110
1001
0100
0101
1010
0111
0110
0110
1000011
0100100
0100011
0100010
0100011
0100100
0100010
0100110
0100011
0100010
0100101
0100100
0100010
0100011
0000100
0100100
33
33
33
33
33
33
33
100
100
133
200
166
133
266
—
150
200
200
200
250
266
266
33
33
33
33
33
33
33
33
33
33
33
33
33
100
100
133
200
166
133
266
100
200
300
133
166
333
—
150
200
200
200
250
266
266
300
300
300
333
333
333
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
100
100
133
200
166
133
266
100
200
300
133
166
333
233
200
200
150
200
200
200
250
266
266
300
300
300
333
333
333
350
400
400
—
—
—
—
—
—
—
—
—
—
66 MHz CLKIN/PCI_CLK Options
242
322
224
422
323
223
522
304
324
403
423
0010
0011
0010
0100
0011
0010
0101
0011
0011
0100
0100
1000010
0100010
0100100
0100010
0100011
0100101
0100010
0000100
0100100
0000011
0100011
66
66
66
66
133
200
133
266
—
133
200
266
266
66
66
66
66
66
66
66
133
200
133
266
200
133
333
—
133
200
266
266
300
333
333
66
66
66
66
66
66
66
66
66
66
66
133
200
133
266
200
133
333
200
200
266
266
133
200
266
266
300
333
333
400
400
400
400
—
—
—
—
—
—
—
—
—
1
2
The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4-15 associated with the SPMF
and COREPLL settings given in the table.
The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
74
Freescale Semiconductor
Thermal
19 Thermal
This section describes the thermal specifications of the MPC8343E.
19.1 Thermal Characteristics
.Table 52 provides the package thermal characteristics for the 620 29x29 mm PBGA of the MPC8343E
Table 52. Package Thermal Characteristics for PBGA
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection on single layer board (1s)
Junction-to-ambient Natural Convection on four layer board (2s2p)
Junction-to-ambient (@200 ft/min) on single layer board (1s)
Junction-to-ambient (@ 200 ft/min) on four layer board (2s2p)
Junction-to-board thermal
RθJA
RθJMA
RθJMA
RθJMA
RθJB
21
15
17
12
6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
Junction-to-case thermal
RθJC
5
5
Junction-to-Package Natural Convection on Top
ψJT
5
6
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
19.2 Thermal Management Information
For the following sections, P = (V X I ) + P where P is the power dissipation of the I/O drivers.
D
DD
DD
I/O
I/O
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
75
Thermal
19.2.1 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature for the package (°C)
RθJA = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity T - T ) are possible.
J
A
19.2.2 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package will be approximately the same as the local air temperature near the device.
Specifying the local ambient conditions explicitly as the board temperature provides a more precise
description of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature for the package (°C)
RθJA = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
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Thermal
19.2.3 Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TT = thermocouple temperature on top of package (°C)
ΨJT = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
19.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink will be required to provide the necessary thermal
management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction to ambient thermal resistance (°C/W)
RθJC = junction to case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
Rθ is device related and cannot be influenced by the user. The user controls the thermal environment to
JC
change the case to ambient thermal resistance, Rθ . For instance, the user can change the size of the heat
CA
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, air flow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
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Thermal
Table 53 showsheat sinks and junction-to-case thermal resistance for PBGA of the MPC8343E.
Table 53. Heat Sinks and Junction-to-Case Thermal Resistance MPC8343E (PBGA)
29x29 mm PBGA
Heat Sink Assuming Thermal Grease
Air Flow
Junction-to-Ambient
Thermal Resistance
AAVID 30x30x9.4 mm Pin Fin
AAVID 30x30x9.4 mm Pin Fin
Natural Convection
1 m/s
13.5
9.6
AAVID 30x30x9.4 mm Pin Fin
2 m/s
8.8
AAVID 31x35x23 mm Pin Fin
Natural Convection
1 m/s
11.3
8.1
AAVID 31x35x23 mm Pin Fin
AAVID 31x35x23 mm Pin Fin
2 m/s
7.5
Wakefield, 53x53x25 mm Pin Fin
Natural Convection
1 m/s
9.1
Wakefield, 53x53x25 mm Pin Fin
7.1
Wakefield, 53x53x25 mm Pin Fin
2 m/s
6.5
MEI, 75x85x12 no adjacent board, extrusion
MEI, 75x85x12 no adjacent board, extrusion
MEI, 75x85x12 no adjacent board, extrusion
MEI, 75x85x12 mm, adjacent board, 40 mm Side bypass
Natural Convection
1 m/s
10.1
7.7
2 m/s
6.6
1 m/s
6.9
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
Heat sink vendors include the following list:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
408-567-8082
Alpha Novatech
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC)
413 North Moss St.
818-842-7277
Burbank, CA 91502
Internet: www.ctscorp.com
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Thermal
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
408-436-8770
800-522-2800
603-635-5102
Internet: www.mei-thermal.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Interface material vendors include the following:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com
781-935-4850
800-248-2481
Dow-Corning Corporation
Dow-Corning Electronic Materials
P.O. Box 994
Midland, MI 48686-0997
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
888-642-7674
800-347-4572
Internet: www.microsi.com
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
19.3 Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (4.5 kg
force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted
or plastic surfaces and its performance verified under the application requirements.
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Thermal
19.3.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
TJ = TC + (RθJA × PD)
where:
TC = case temperature of the package (°C)
RθJC = junction to case thermal resistance (°C/W)
PD = power dissipation (W)
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System Design Information
20 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8343E.
20.1 System Clocking
The MPC8343E includes two PLLs.
1. The platform PLL (AV 1) generates the platform clock from the externally supplied CLKIN
DD
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in Section 18.1, “System PLL Configuration.”
2. The e300 Core PLL (AV 2) generates the core clock as a slave to the platform clock. The
DD
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section , “.”
20.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AV 1,AV 2 respectively). The AV level should always be equivalent to V , and preferably these
DD
DD
DD
DD
voltages will be derived directly from V through a low frequency filter scheme such as the following.
DD
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 34, one to each of the five AV pins. By
DD
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
DD
Figure 34 shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD (or L2AVDD)
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 34. PLL Power Supply Filter Circuit
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System Design Information
20.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8343E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8343E system, and the
MPC8343E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each V , OV , GV , and LV pins
DD
DD
DD
DD
of the MPC8343E. These decoupling capacitors should receive their power from separate V , OV
,
DD
DD
GV , LV , and GND power planes in the PCB, utilizing short traces to minimize inductance.
DD
DD
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , OV , GV , and LV planes, to enable quick recharging of the smaller chip
DD
DD
DD
DD
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
20.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV , GV , or LV as required. Unused active high
DD
DD
DD
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of
DD
DD
DD
DD
the MPC8343E.
20.5 Output Buffer DC Impedance
The MPC8343E drivers are characterized over process, voltage, and temperature. For all buses, the driver
2
is a push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 35). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
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System Design Information
OVDD
RN
SW2
SW1
Pad
Data
RP
OGND
Figure 35. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
× I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = 1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
= R
2
1
2
source
source term
× (V /V – 1). The drive current is then I
= V /R
.
1
2
source
1
source
Table 54 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105°C.
DD
Table 54. Impedance Characteristics
Local Bus, Ethernet,
PCI Signals
(not including PCI
output clocks)
PCI Output Clocks
(including
PCI_SYNC_OUT)
DUART, Control,
Configuration, Power
Management
Impedance
DDR DRAM Symbol
Unit
R
R
42 Target
42 Target
NA
25 Target
25 Target
NA
42 Target
42 Target
NA
20 Target
20 Target
NA
Z0
Z0
Ω
Ω
Ω
N
P
Differential
ZDIFF
Note: Nominal supply voltages. See Table 55, Tj = 105°C.
20.6 Configuration Pin Muxing
The MPC8343E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
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System Design Information
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
20.7 Pull-Up Resistor Requirements
The MPC8343E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
2
including I C pins, Ethernet Management MDIO pin and EPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 36. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
20.8 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. The
MPC8343E requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, generally systems will assert TRST during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to PORESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert TRST without causing
PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these
signals with logic.
The arrangement shown in Figure 36 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is
asserted.
The COP header shown Figure 36 in adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in Figure 36; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
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System Design Information
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 36 is common to all known emulators.
PORESET
PORESET
From Target
Board Sources
(if any)
SRESET
HRESET
SRESET
HRESET
10 kΩ
HRESET
OVDD
OVDD
13
11
SRESET
10 kΩ
10 kΩ
10 kΩ
OVDD
OVDD
TRST
TRST
4
2
4
1
3
2 kΩ
VDD_SENSE
6 1
5
OVDD
5
6
NC
7
8
CHKSTP_OUT
CHKSTP_OUT
OVDD
15
10 kΩ
9
10
12
11
10 kΩ
14 2
OVDD
CHKSTP_IN
TMS
KEY
No pin
13
15
CHKSTP_IN
TMS
8
9
1
3
16
TDO
TDI
COP Connector
Physical Pin Out
TDO
TDI
TCK
7
2
TCK
NC
NC
10
12
16
NC
Notes:
1. Some systems require power to be fed from the application board into the debugger repeater card
via the COP header. In this case the resistor value for VDD_SENSE should be around 20Ω.
2. Key location; pin 14 is not physically present on the COP header.
Figure 36. JTAG Interface Connection
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Electrical Characteristics
21 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal charaistics for the MPC8343E.
The MPC8343E is currently targeted to these specifications. Some of these specifications are independent
of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design
specifications.
21.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
21.1.1 Absolute Maximum Ratings
Table 55 provides the absolute maximum ratings.
1
Table 55. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
PLL supply voltage
VDD
AVDD
GVDD
LVDD
OVDD
–0.3 to 1.32
–0.3 to 1.32
–0.3 to 3.63
–0.3 to 3.63
–0.3 to 3.63
V
V
V
V
V
DDR DRAM I/O voltage
Three-speed Ethernet I/O, MII management voltage
PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
Input voltage
DDR DRAM signals
MVIN
MVREF
LVIN
–0.3 to (GVDD + 0.3)
–0.3 to (GVDD + 0.3)
–0.3 to (LVDD + 0.3)
–0.3 to (OVDD + 0.3)
V
V
V
V
2, 5
2, 5
4, 5
3, 5
DDR DRAM reference
Three-speed Ethernet signals
Local bus, DUART, CLKIN,
system control and power
management, I2C, and JTAG
signals
OVIN
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
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Electrical Characteristics
1
Table 55. Absolute Maximum Ratings (continued)
Characteristic
Symbol
Max Value
–55 to 150
Unit
Notes
Storage temperature range
TSTG
°C
Notes:
1. Functional and tested operating conditions are given in Table 56. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms
during power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms
during power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 37.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V
operation, as shown in Figure 3.
21.1.2 Power Supply Voltage Specification
Table 56 provides the recommended operating conditions for the MPC8343E. Note that the values in
Table 56 are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 56. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Notes
Value
Core supply voltage
PLL supply voltage
VDD
1.2 V 60 mV
1.2 V 60 mV
2.5 V 125 mV
V
V
V
V
1
1
AVDD
GVDD
LVDD1
DDR DRAM I/O supply voltage
Three-speed Ethernet I/O supply voltage
3.3 V 330 mV
2.5 V 125 mV
Three-speed Ethernet I/O supply voltage
LVDD2
OVDD
3.3 V 330 mV
2.5 V 125 mV
V
V
PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
3.3 V 330 mV
Notes:
1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the
positive or negative direction.
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Electrical Characteristics
Figure 37 shows the undershoot and overshoot voltages at the interfaces of the MPC8343E.
G/L/OVDD + 20%
G/L/OVDD + 5%
G/L/OVDD
VIH
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
1
of tinterface
Note:
1. Note that tinterface refers to the clock period associated with the bus clock interface.
Figure 37. Overshoot/Undershoot Voltage for GV /OV /LV
DD
DD
DD
Figure 38 shows the undershoot and overshoot voltage of the PCI interface of the MPC8343E for the 3.3-V
signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 38. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
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Electrical Characteristics
21.1.3 Output Driver Characteristics
Table 57 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 57. Output Drive Capability
Output Impedance
Supply
Voltage
Driver Type
(Ω)
Local bus interface utilities signals
PCI signals (not including PCI output clocks)
PCI output clocks (including PCI_SYNC_OUT)
DDR signal
42
25
42
20
42
42
42
OVDD = 3.3 V
GVDD = 2.5 V
LVDD = 2.5/3.3 V
OVDD = 3.3 V
TSEC/10/100 signals
DUART, system control, I2C, JTAG
GPIO signals
OVDD = 3.3 V,
LVDD = 2.5/3.3 V
21.2 Power Sequencing
MPC8343E does not require the core supply voltage and IO supply voltages to be applied in any particular
order. Note that during the power ramp up, before the power supplies are stable, there might be a period
of time that IO pins are actively driven. After the power is stable, as long as PORESET is asserted, most
IO pins are tri-stated. In order to minimize the time that IO pins being actively driven, it is recommended
to apply core voltage before IO voltage and assert PORESET before the power supplies fully ramp up.
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Document Revision History
22 Document Revision History
Table 58 provides a revision history of this document.
Table 58. Document Revision History
Revision
Date
Substantive Change(s)
6
11/2005
Updated values in Table 51, “ Suggested PLL Configurations.”
Updated values in Table 46, “ Operating Frequencies for PBGA.”
5
4
3
10/2005
9/2005
8/2005
Changed classification of document to “Technical Data.”
Added Table 2, "MPC8343E Typical I/O Power Dissipation."
Table 1: Updated values for power dissipation that were TBD in Revision 2.
Table 44: Deleted package pin number AD22 from NC signal row.
2
1
5/2005
4/2005
Table 1: Typical values for power dissipation are changed to "TBD".
Table 1: Addition of note 1
Table 44: Addition of Therm0 (B15)
0
4/2005
—
23 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 23.1, “Part Numbers Fully Addressed by this Document.”
23.1 Part Numbers Fully Addressed by this Document
Table 59 provides the Freescale part numbering nomenclature for the MPC8343E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 59. Part Numbering Nomenclature
MPC nnnn
pp
aa
a
r
e
t
1
Product
Code Identifier
Part
Encryption
Acceleration
Temperature
Range
Processor
Frequency
Platform
Frequency
Revision
Level
2
Package
3
MPC
8343
Blank = Not
included
Blank = 0 to
105°C
C= -40 to 105°C
ZQ = PBGA
e300 core
speed
AD =266
AG = 400
D = 266
Contactlocal
Freescale
sales office
VR = PB Free
PBGA
E = included
Notes:
1. For temperature range = C, processor frequency is limited to "TBD" with a platform frequency of "TBD".
2. See Section 1.13, “Package and Pin Listings” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
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Document Number: MPC8343EEC
Rev. 6
11/2005
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