MPC8536EBVJAVLA_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC8536EEC

Rev. 7, 07/2015

MPC8536E

MPC8536E PowerQUICC III

Integrated Processor

Hardware Specifications

MAPBGA–783

29 mm x 29 mm

• High-performance, 32-bit e500 core, scaling up to

1.5 GHz, that implements the Power Architecture®

technology

– Support for various Ethernet physical interfaces: GMII,

TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII

– Support TCP/IP acceleration and QOS features

– MAC address recognition and RMON statistics support

– Support ARP parsing and generating wake-up events

based on the parsing results while in deep sleep mode

– Support accepting and storing packets while in deep

sleep mode

– 36-bit physical addressing

– Double-precision embedded floating point APU using

64-bit operands

– Embedded vector and scalar single-precision

floating-point APUs using 32- or 64-bit operands

– Memory management unit (MMU)

• High-speed interfaces (multiplexed) supporting:

– Three PCI Express interfaces

• Integrated L1/L2 cache

– L1 cache—32-Kbyte data and 32-Kbyte instruction

– L2 cache—512-Kbyte (8-way set associative)

• DDR2/DDR3 SDRAM memory controller with full ECC

support

– PCI Express 1.0a compatible

– One x8/x4/x2/x1 PCI Express interface

– Two x4/x2/x1 ports, or,

– One x4/x2/x1 port and Two x2/x1 ports

– Two SGMII interfaces

– One 64-bit/32-bit data bus

– Up to 333-MHz clock (667-MHz data rate)

– Supporting up to 16 Gbytes of main memory

– Using ECC, detects and corrects all single-bit errors and

detects all double-bit errors and all errors within a nibble

– Invoke a level of system power management by

asserting MCKE SDRAM signal on-the-fly to put the

memory into a low-power sleep mode

– Two Serial ATA (SATA) controllers support SATA I and

SATA I data rates

• PCI 2.2 compatible PCI controller

• Three universal serial bus (USB) dual-role controllers

comply with USB specification revision 2.0

• 133-MHz, 32-bit, enhanced local bus (eLBC) with memory

controller

– Both hardware and software options to support

battery-backed main memory

• Enhanced secured digital host controller (eSDHC) used for

SD/MMC card interface

• Integrated security engine (SEC) optimized to process all

the algorithms associated with IPsec, IKE, SSL/TLS,

iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.

– XOR engine for parity checking in RAID storage

applications

– Support boot capability from eSDHC

• Integrated four-channel DMA controller

• Dual I C and dual universal asynchronous

receiver/transmitter (DUART) support

• Programmable interrupt controller (PIC)

2

• Enhanced Serial peripheral interfaces (eSPI)

– Support boot capability from eSPI

• Two enhanced three-speed Ethernet controllers (eTSECs)

with SGMII support

• Power management, low standby power

– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode

– PMC wake on: LAN activity, USB connection or remote

wakeup, GPIO, internal timer, or external interrupt event

• System performance monitor

• IEEE Std 1149.1™-compatible, JTAG boundary scan

• 783-pin FC-PBGA package, 29 mm × 29 mm

– Three-speed support (10/100/1000 Mbps)

– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and

IEEE Std 1588™-compatible controllers

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

Table of Contents

1

2

Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3

2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113

3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113

3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114

3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114

1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21

2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30

2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31

2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2.10 Ethernet Management Interface Electrical Characteristics

60

3

3.5 SerDes

Block

Power

Supply

Decoupling

Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115

3.7 Pull-Up and Pull-Down Resistor Requirements. . . . . 115

3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115

3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116

3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117

3.11 Guidelines for High-Speed Interface Termination . . . 119

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 121

4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

5.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 122

5.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 124

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . 125

2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

2.12 Enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65

2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74

2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76

2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

2.17 I²C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

2.18 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90

2.21 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

4

5

6

7

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

2

Pin Assignments and Reset States

This figure shows the major functional units within the chip.

e500 Core

512-Kbyte

L2 Cache

Power

Management

32-Kbyte

D-Cache

32-Kbyte

I-Cache

MPC8536E

64-bit

Performance

Async

Queue

DDR2/DDR3

SDRAM Controller

with ECC

eSPI

Enhanced

Local Bus

Coherency

Module

Monitor

Timers

DUART

SEC

OpenPIC

2x I²C

PCI 32

PCI-e

DMA

Gigabit

Ethernet

Gigabit

USB

Host/

USB

SD

MMC

Ethernet

Host/

Device

SATA

SATA w/ IEEE 1588 w/ IEEE 1588

PCI-e

SGMII

ULPI

2 Lane SERDES

8 Lane SERDES

Figure 1. Chip Block Diagram

1

Pin Assignments and Reset States

NOTE

The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails

for the eTSEC blocks and to ease the port of existing PowerQUICC III software

NOTE

The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR

configuration. See Table 1 for more details.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

3

Pin Assignments and Reset States

1.1

Pin Map

The following figures provide the pin map of the chip.

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AVDD_

SRDS2

TSEC3_

RXD

TSEC1_

RXD

MDQ

[32]

MDQ

[46]

MDQ

[47]

MDQ

[34]

MDQ

[56]

MDQ

[57]

MDQS

[7]

MDQ

[58]

MDQ

[59]

TSEC3_

RX_CLK

TSEC1_

TX_EN

TSEC1_

RX_DV

MDQS

[5]

USB1_

CLK

USB1_ USB1_

USB1_D USB1_D

[0] [2]

USB1_D USB1_D

GV

DD

GV

DD

GND

1

2

1

2

3

4

5

6

7

8

9

10

STP

DIR

[5]

[7]

[3]

[1]

USB1_

PWR-

FAULT

TSEC3_

RXD

TSEC1_ TSEC1_

RXD

[0]

AGND_

SRDS2

TSEC1_

GTX_CLK

MDQ

[44]

MDQ

[40]

MDM

[5]

MDQS

[5]

MDQ

[42]

MDQ

[43]

MDQ

[35]

MDQ

[60]

MDQ

[61]

MDM

[7]

MDM

[62]

MDQ

[63]

TSEC3_

RX_DV

MDQS

[7]

USB1_

NXT

USB1_D USB1_D USB1_D USB1_D

GV

DD

OV

GND

DD

RXD

[3]

[1]

[3]

[4]

[6]

[1]

USB1_

PCTL0/

GPIO[6]

SD2_

PLL_

TPA

TSEC3_ TSEC3_ TSEC1_ TSEC1_

TSEC1_

RXD

MDQ

[45]

MDQ

[41]

MCS

[0]

MDQ

[33]

MDQ

[38]

MDQ

[52]

MDM

[6]

MDQS

[6]

MDQ

[50]

MDQ

[51]

TSEC1_

RX_CLK

USB2_D USB2_D

[0] [1]

USB3_D USB3_D

[1] [0]

GV

DD

GV

DD

GV

DD

GND

3

RXD

[2]

RXD

[0]

TXD

[3]

RXD

[2]

[7]

USB1_

TSEC1_

TXD

MBA

[0]

MDQ

[36]

MDM

[4]

MDQ

[39]

MDQ

[53]

MDQ

[49]

MDQ

[54]

MDQ

[55]

Rvsd

TSEC3_

RX_ER

TSEC1_

TX_CLK

MCS

[2]

MDQS

[6]

USB2_D USB2_D USB3_D USB3_D

[2] [3] [3] [2]

GV

DD

TV

LV

PCTL1/ OV

GPIO[7]

MWE

GND

4

DD

[1]

TSEC3_

TXD

TSEC1_ TSEC1_ TSEC1_

TSEC3_

GTX_CLK

MA

[10]

MBA

[1]

MODT

[0]

MDQ

[37]

MDQS

[4]

MDQ

[48]

TSEC3_

TX_EN

TSEC1_

TX_ER

MDQS

[4]

USB2_ USB2_D USB2_D USB3_D USB3_

CLK

GV

DD

GV

DD

GV

DD

MRAS

GND

5

TXD

[2]

TXD

[4]

TXD

[6]

[4]

[5]

[4]

CLK

[1]

DMA_

DACK[0]/

GPIO[10]

SD2_

IMP_CAL

_TX

SD2_

REF_

CLK

TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_

MODT

[2]

MODT

[3]

MCK

[2]

TSEC1_

COL

SD2_RX

[0]

MCS

[3]

MCS

[1]

MCK

[2]

EC_GTX_

CLK125

MAPAR_

OUT

USB2_D

[6]

USB2_D

[7]

USB3_D USB3_D

[6] [5]

GV

DD

NC

S2GND

S2V

DD

OV

DD

6

TXD

[0]

RXD

[5]

RXD

[4]

TXD

[0]

RXD

[4]

SD2_

IMP_CAL

_RX

TSEC_

1588_TRIG

_IN[1]

SD2_

REF_

CLK

SD2_

PLL_

TPD

TSEC3_

TXD

TSEC1_

RXD

MA

[0]

MA

[13]

MODT

[1]

SD2_RX

[0]

USB2_ USB2_

NXT STP

USB2_ USB3_ USB3_D

GV

DD

GV

DD

TV

LV

MCAS

GND

NC

GND

NC

S2V

DD

GND

7

DD

DIR

NXT

[7]

[2]

[6]

SEE DETAIL A

SEE DETAIL B

SDHC_

DAT[4]/SPI

_CS[0]

TSEC_

1588_TRIG

_IN[0]

USB2_

TSEC3_ TSEC3_ TSEC3_

TSEC1_ TSEC1_ TSEC1_

SPI_

CLK

SPI_

MOSI

MCK

[3]

MCK

[3]

MA

[2]

MA

[1]

MCK

[5]

MCK

[5]

SD2_RX

[1]

USB3_ USB3_

GV

GND

Rsvd

NC

S2GND

NC

PWR-

FAULT

8

DD

TXD

[3]

TXD

[5]

TXD

[6]

TXD

[5]

TXD

[7]

RXD

[5]

DIR

STP

SDHC_

DAT[6]/SPI

_CS[2]

USB2_

PCTL1/

GPIO[9]

USB2_

PCTL0/

GPIO[8]

TSEC_

1588_

CLK

TSEC3_

TXD

SPI_

MISO

MCK

[0]

MCK

[0]

MA

[4]

MA

[8]

MA

[7]

MCKE

[3]

TSEC3_ TSEC3_

COL TX_ER

TSEC1_ TSEC1_

RX_ER

SD2_RX

[1]

GV

DD

GV

DD

NC

S2V

DD

GND

Rsvd

9

CRS

[4]

SDHC_

TSEC_

DMA_

DACK[1]/

GPIO[11]

SDHC_

SOUT WP/GPIO

UART_

EC_

MDC

MA

[3]

MA

[5]

MA

[14]

MA

[15]

TSEC3_ TSEC3_

CRS

SDHC_

CMD

MCKE

[2]

MCKE

[0]

MCKE

[1]

GV

DD

1588_CLK 1588_TRIG

DAT[7]/SPI DREQ[0]/ DAT[5]/SPI OV

_CS[3]

GND

NC

X2GND

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DD

TX_CLK

_OUT

GPIO[14]

_OUT[1]

_CS[1]

[0]

[5]

TSEC_

DMA_

DDONE[0]/ DDONE[1]/

GPIO[12] GPIO[13]

DMA_

DREQ[1]/

GPIO[15]

SDHC_

UART_

CTS

[0]

SDHC_

DAT

EC_

MDIO

MA

[6]

MECC

[3]

MA

MECC

[2]

MCK

[1]

MCK

[1]

SD2_TX

[1]

SD2_TX

[0]

MSRCID

[4]

GV

DD

GV

DD

1588_PULSE1588_TRIG1588_PULSE

_OUT2

OV

DD

GND

X2V

DD

X2GND

X2V

DD

GND

DD

CD/GPIO 11

[12]

_OUT[0]

_OUT1

[3]

[4]

UART_ UART_ UART_ UART_ UART_

UART_ SDHC_ SDHC_

TSEC3_ TSEC3_

TXD

[7]

MA

[11]

MA

[9]

MECC

[7]

MECC

[0]

SD2_TX

[1]

SD2_TX

[0]

MSRCID MSRCID

[2]

GV

DD

GV

DD

X2V

DD

GND

X2GND

GND

X2GND

GND

NC

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SOUT

[1]

SIN

[0]

SIN

[1]

DAT

[0]

DAT

[1]

RXD

[7]

CTS

[1]

RTS

[0]

RTS

[1]

[0]

IRQ[10]/

DMA_

DACK[3] DREQ[3]

IRQ[9]/

DMA_

PCI1_

SDHC_

DAT

[2]

TSEC3_

RXD

MBA

[2]

MECC

[6]

VDD_

CORE

VDD_

CORE

VDD_

CORE

VDD_

CORE

TEST_

SEL

SDHC_

CLK

MDQS

[8]

MDM

[8]

MCK

[4]

MDQS

[8]

MCK

[4]

MAPAR_

ERR

MSRCID

[1]

GND

MDVAL

GND

MCP

OV

DDRCLK

GND

REQ

DD

[6]

[2]

IRQ[11]/

DMA_

DDONE[3]

PCI1_

PCI1_GNT

[4]/GPIO

[3]

MDQ

[27]

MECC

[1]

MECC

[5]

MECC

[4]

VDD_

CORE

VDD_

CORE

VDD_

CORE

VDD_

CORE

IIC2_

SDA

MSRCID

[3]

GV

DD

GV

DD

GV

DD

GV

DD

OV

DD

GND

SYSCLK

GND

UDE

GNT

[2]

SENSE-

VDD_

CORE

PCI1_

AD

PCI1_

AD

PCI1_REQ PCI1_GNT

[3]/GPIO [3]/GPIO

PCI1_REQ

CLK_

OUT

MDQ

[26]

MDIC

[0]

MDIC

[1]

VDD_

CORE

VDD_

CORE

VDD_

CORE

IIC2_

SCL

MDQ

[31]

HRESET_

REQ

GV

DD

GV

DD

GND

RTC

[4]/GPIO

[31]

[28]

[0]

[2]

[1]

LCS5/

DMA_

DREQ2

LCS6/

DMA_

DACK2

PCI1_

AD

PCI1_

IDSEL

MDQ

[30]

MDQS

[3]

MDQ

[19]

MDQ

[23]

MDQ

[18]

LA

[28]

VDD_

CORE

VDD_

CORE

VDD_

CORE

VDD_

CORE

IRQ

[5]

AVDD_

CORE

LCS

[4]

SENSE-

VSS

OV

DD

OV

DD

GND

HRESET

REQ

GNT

REQ

[26]

[1]

[0]

SENSE- PCI1_

PCI1_

AD

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDM

[3]

VDD_

PLAT

VDD_

PLAT

VDD_

PLAT

VDD_

PLAT

IRQ_

OUT

IRQ

[1]

IRQ

[4]

MDQS

[3]

MDQS

[2]

MDQ

[22]

LA

[31]

LA

[30]

LA

[29]

CKSTP_

OUT

GV

DD

GND

AD

VDD_

PLAT

[30]

[29]

[27]

[24]

[23]

LCS7/

DMA_

DDONE2

PCI1_

C_BE

[3]

PCI1_

OV

PCI1_

AD

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDQ

[25]

MDQ

[24]

MDM

[2]

MDQ

[21]

VDD_

PLAT

VDD_

PLAT

VDD_

PLAT

AVDD_

PLAT

MDQS

[2]

LCS

[0]

LGPL3/

LFWP

CKSTP_

IN

GV

DD

BV

DD

OV

DD

GND

DD

GNT

[0]

[25]

[22]

[20]

[18]

TRIG_

OUT/READY

/QUIESCE

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDQ

[29]

MDQ

[28]

MDQ

[17]

MDQ

[16]

MDQ

[20]

LA

[27]

VDD_

PLAT

VDD_

PLAT

VDD_

PLAT

AVDD_

DDR

LCS

[1]

LCS

[2]

IRQ

[7]

IRQ

[3]

BV

DD

NC

LGPL5

GND

TRIG_IN

GND

SRESET

ASLEEP

[21]

[19]

[17]

LGPL4/

PCI1_

C_BE

[2]

LGPL2/

LOE/

LFRE

PCI1_

AD

LGTA/

LUPWAIT/

LPBSE/

LFRB

L2_

TSTCLK

PCI1_

FRAME

MDQ

[11]

MDQ

[10]

PCI1_

IRDY

AVDD_

PCI1

LCS

[3]

LGPL0/ LGPL1/

LFCLE LFALE

SD1_TX

[1]

SD1_TX

[3]

SD1_TX

[4]

SD1_TX

[6]

GV

DD

BV

DD

XV

DD

XV

DD

XV

OV

DD

GND

XGND

DD

[16]

L1_

TSTCLK

PCI1_

STOP

PCI1_

TRDY

MDQ

[15]

MDQ

[14]

MDQ

[3]

MDQ

[7]

LAD

[31]

LAD

[1]

PCI1_

PERR DEVSEL

IIC1_

SCL

LWE[3]/

LBS[3]

SD1_TX

[1]

SD1_TX

[3]

SD1_TX

[4]

SD1_TX

[6]

GV

DD

BV

XV

DD

XV

DD

GND

DD

XGND

Rsvd

XGND

GND

TRST

GND

SEE DETAIL C

SEE DETAIL D

PCI1_

C_BE

[1]

LWE0/

LBS0/

LFWE

MDQS

[1]

MDQ

[2]

MDQ

[6]

LAD

[29]

LAD

[30]

LWE[1]/

LBS[1]

LAD

[0]

LAD

[2]

PCI1_

PAR

PCI1_

SERR

IIC1_

SDA

IRQ

[6]

IRQ

[8]

IRQ

[0]

MDQS

[1]

SD1_TX

[0]

SD1_TX

[2]

SD1_TX

[5]

SD1_TX

[7]

GV

XV

DD

XV

DD

OV

DD

XGND

DD

PCI1_

AD

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDQ

[9]

MDM

[1]

MDQS

[0]

LAD

[28]

LWE[2]/

LBS[2]

SD1_TX

[0]

SD1_TX

[2]

SD1_TX

[5]

SD1_TX

[7]

IRQ

[2]

LAD

[3]

BV

DD

BV

DD

XV

DD

XV

DD

XV

DD

GND

XGND

GND

DD

[27]

[13]

[14]

[15]

[11]

PCI1_

AD

PCI1_

AD

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDQ

[8]

MDQ

[13]

MDQS

[0]

LAD

[24]

LAD

[23]

LAD

[26]

LCLK

[0]

LCLK

[1]

LAD

[4]

LAD

[5]

GV

DD

SV

DD

SV

DD

SV

DD

SV

DD

OV

DD

XGND

NC

SGND

NC

SGND

[5]

[7]

[9]

[10]

[12]

PCI1_

C_BE

[0]

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDQ

[12]

MDQ

[5]

MDM

[0]

MDQ

[4]

LCLK

[2]

LAD

[7]

LAD

[6]

LDP

[3]

LAD

[19]

LSSD_

MODE

SD1_RX

[1]

SD1_RX

[3]

SD1_RX

[4]

SD1_RX

[6]

SV

DD

SV

DD

SV

DD

OV

DD

LBCTL

LALE

GND

NC

SGND

GND

[1]

[4]

[8]

SD1_

PLL_

TPA

PCI1_

AD

PCI1_

AD

PCI1_

AD

MDQ

[0]

MDQ

[1]

PCI1_

CLK

LAD

[25]

LAD

[22]

LAD

[18]

LAD

[16]

SD1_RX

[1]

SD1_RX

[3]

SD1_RX

[4]

SD1_RX

[6]

LDP

[0]

POWER_

OK

BV

DD

SV

DD

SV

DD

GND

GND IMP_CAL SGND

_RX

SGND

GND

[0]

[2]

[3]

SD1_

REF_

CLK

PCI1_

AD

LDP

[2]

LAD

[21]

LAD

[15]

LAD

[14]

LAD

[11]

LAD

[9]

AGND_

SRDS

SD1_RX

[0]

SD1_RX

[2]

SD1_RX

[5]

SD1_RX

[7]

POWER_

EN

LSYNC_

IN

SV

DD

SV

DD

SV

DD

OV

DD

SV

DD

SGND

NC

SGND

TMS

GND

[6]

SD1_

REF_

CLK

SD1_

PLL_

TPD

SD1_

AVDD_

SRDS

AVDD_ LSYNC_

LBIU

LAD

[20]

LAD

[17]

LAD

[13]

LAD

[12]

LAD

[10]

LAD

[8]

SD1_RX

[0]

SD1_RX

[2]

SD1_RX

[5]

SD1_RX

[7]

LDP

[1]

SV

DD

SV

DD

MVREF

A

GND

B

SGND

M

SGND

T

SGND

Y

SGND IMP_CAL TDO

_TX

TCK

AG

TDI

OUT

C

D

E

F

G

H

J

K

L

N

P

R

U

V

W

AA

AB

AC

AD

AE

AF

AH

Figure 2. Chip Pin Map Bottom View

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

4

Pin Assignments and Reset States

A

B

C

D

E

F

G

H

J

K

L

M

N

P

MDQ

[32]

MDQ

[46]

MDQ

[47]

MDQ

[34]

MDQ

[56]

MDQ

[57]

MDQS

[7]

MDQ

[58]

MDQS

[5]

GV

DD

GND

1

2

DD

MDQ

[42]

MDQ

[35]

MDQ

[44]

MDQ

[40]

MDM

[5]

MDQS

[5]

MDQ

[43]

MDQ

[60]

MDQ

[61]

MDM

[7]

MDM

[62]

MDQS

[7]

GV

DD

GND

MDQ

[38]

MDM

[6]

MDQ

[50]

MDQ

[51]

MDQ

[45]

MDQ

[41]

MCS

[0]

MDQ

[33]

MDQ

[52]

MDQS

[6]

GV

DD

GV

DD

GND

3

MBA

[0]

MDQ

[36]

MDM

[4]

MDQ

[39]

MDQ

[53]

MDQ

[49]

MDQ

[54]

MDQ

[55]

MCS

[2]

MDQS

[6]

GV

DD

MWE

GND

4

MA

MBA

[1]

MODT

[0]

MDQ

[37]

MDQS

[4]

MDQ

[48]

MDQS

[4]

GV

DD

GV

DD

GV

DD

MRAS

GND

5

[10]

SD2_

IMP_CAL

_TX

SD2_

REF_

CLK

MODT

[2]

MODT

[3]

MCK

[2]

SD2_RX

[0]

MCS

[3]

MCS

[1]

MCK

[2]

MAPAR_

OUT

GV

DD

NC

S2GND

6

SD2_

REF_

CLK

SD2_

PLL_

TPD

MA

[0]

MA

MODT

[1]

SD2_RX

[0]

GV

DD

GV

DD

MCAS

GND

NC

GND

NC

S2V

DD

7

[13]

MCK

[3]

MCK

[3]

MA

[2]

MA

[1]

MCK

[5]

MCK

[5]

SD2_RX

[1]

GV

DD

GND

Rsvd

NC

S2GND

NC

8

MCK

[0]

MCK

[0]

MA

[4]

MA

[8]

MA

[7]

MCKE

[3]

SD2_RX

[1]

GV

DD

GV

DD

NC

S2V

DD

9

MA

[3]

MA

[5]

MA

[14]

MA

[15]

MCKE

[2]

MCKE

[0]

MCKE

[1]

GV

DD

GND

NC

10

11

12

13

14

X2GND

NC

MA

[6]

MECC

[3]

MA

MECC

[2]

MCK

[1]

MCK

[1]

SD2_TX

[1]

SD2_TX

[0]

GV

DD

GV

DD

GV

DD

GND

X2V

DD

X2GND

[12]

MA

[11]

MA

[9]

MECC

[7]

MECC

[0]

SD2_TX

[1]

SD2_TX

[0]

GV

DD

GV

DD

X2V

DD

GND

X2GND

GND

NC

MBA

[2]

MECC

[6]

VDD_

CORE

VDD_

CORE

VDD_

CORE

MDQS

[8]

MDM

[8]

MCK

[4]

MDQS

[8]

MCK

[4]

MAPAR_

ERR

GND

MDQ

[27]

MECC

[1]

MECC

[5]

MECC

[4]

VDD_

CORE

VDD_

CORE

GV

DD

GV

DD

GV

DD

GV

DD

GND

DETAIL A

Figure 3. Chip Pin Map Detail A

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

5

Pin Assignments and Reset States

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AVDD_

SRDS2

TSEC3_

RXD

[3]

TSEC1_

RXD

[1]

MDQ

[59]

TSEC3_

RX_CLK

TSEC1_

TX_EN

TSEC1_

RX_DV

USB1_

CLK

USB1_

STP

USB1_

DIR

USB1_D USB1_D

[0] [2]

USB1_D USB1_D

1

[5]

[7]

USB1_

PWR-

FAULT

TSEC3_

RXD

[1]

TSEC1_ TSEC1_

AGND_

SRDS2

TSEC1_

GTX_CLK

MDQ

[63]

TSEC3_

RX_DV

USB1_

NXT

USB1_D USB1_D USB1_D USB1_D

OV

DD

2

RXD

[1]

[3]

[4]

[6]

[0]

[3]

USB1_

PCTL0/

GPIO[6]

SD2_

PLL_

TPA

TSEC3_ TSEC3_ TSEC1_ TSEC1_

TSEC1_

RXD

[7]

TSEC1_

RX_CLK

USB2_D USB2_D

[0] [1]

USB3_D USB3_D

[1] [0]

GV

DD

GND

3

RXD

TXD

RXD

[2]

[0]

[3]

[2]

USB1_

PCTL1/

GPIO[7]

TSEC1_

TXD

[1]

Rvsd

TSEC3_

RX_ER

TSEC1_

TX_CLK

USB2_D USB2_D USB3_D USB3_D

[2] [3] [3] [2]

TV

LV

OV

DD

GND

4

DD

TSEC3_

TXD

[1]

TSEC1_ TSEC1_ TSEC1_

TSEC3_

GTX_CLK

TSEC3_

TX_EN

TSEC1_

TX_ER

USB2_ USB2_D USB2_D USB3_D USB3_

GND

5

TXD

Rvsd

CLK

[4]

[5]

[4]

CLK

[2]

[4]

[6]

DMA_

DACK[0]/

GPIO[10]

TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_

TSEC1_

COL

EC_GTX_

CLK125

USB2_D

[6]

USB2_D

[7]

USB3_D USB3_D

[6] [5]

S2V

DD

OV

DD

6

TXD

RXD

TXD

RXD

[0]

[5]

[4]

[0]

[4]

TSEC_

1588_TRIG

_IN[1]

SD2_

IMP_CAL

_RX

TSEC3_

TXD

[2]

TSEC1_

RXD

[6]

USB2_

NXT

USB2_

STP

USB2_

DIR

USB3_ USB3_D

TV

LV

GND

7

DD

NXT

[7]

SDHC_

DAT[4]/SPI

_CS[0]

TSEC_

1588_TRIG

_IN[0]

USB2_

PWR-

FAULT

TSEC3_ TSEC3_ TSEC3_

TSEC1_ TSEC1_ TSEC1_

SPI_

MOSI

SPI_

CLK

USB3_

DIR

USB3_

STP

NC

8

TXD

RXD

[3]

[5]

[6]

[5]

[7]

[5]

SDHC_

DAT[6]/SPI

_CS[2]

USB2_

PCTL1/

GPIO[9]

USB2_

PCTL0/

GPIO[8]

TSEC_

1588_

CLK

TSEC3_

TXD

[4]

SPI_

MISO

TSEC3_ TSEC3_

COL TX_ER

TSEC1_ TSEC1_

GND

Rsvd

GND

DMA_

9

RX_ER

CRS

TSEC_

1588_TRIG

_OUT[1]

SDHC_

TSEC_

1588_CLK

_OUT

DMA_

DACK[1]/

GPIO[11]

SDHC_

WP/GPIO

[5]

UART_

SOUT

[0]

EC_

TSEC3_ TSEC3_

SDHC_

CMD

OV

DD

DAT[7]/SPI DREQ[0]/ DAT[5]/SPI

10

11

12

13

14

MDC

CRS

TX_CLK

GPIO[14]

_CS[3]

DMA_

_CS[1]

GND

TSEC_

DMA_

DDONE[0]/ DDONE[1]/

DMA_

DREQ[1]/

GPIO[15]

SDHC_

CD/GPIO

[4]

UART_

CTS

[0]

SDHC_

DAT

[3]

EC_

MDIO

MSRCID

[4]

1588_PULSE 1588_TRIG 1588_PULSE

_OUT[0]

OV

DD

X2V

DD

GPIO[12]

GPIO[13]

_OUT2

_OUT1

UART_

CTS

[1]

UART_

RTS

[0]

UART_

RTS

[1]

UART_

SOUT

[1]

UART_

SIN

[0]

UART_

SIN

[1]

SDHC_ SDHC_

DAT

[0]

TSEC3_ TSEC3_

MSRCID MSRCID

X2GND

GND

DAT

[1]

TXD

[7]

RXD

[7]

[2]

[0]

IRQ[9]/

DMA_

DREQ[3]

IRQ[10]/

DMA_

DACK[3]

PCI1_

REQ

[2]

SDHC_

DAT

[2]

TSEC3_

RXD

[6]

TEST_

SEL

VDD_

CORE

SDHC_

CLK

MSRCID

[1]

MDVAL

GND

MCP

DDRCLK

OV

DD

IRQ[11]/

DMA_

DDONE[3]

PCI1_

GNT

[2]

PCI1_GNT

[4]/GPIO

[3]

VDD_

CORE

VDD_

CORE

IIC2_

SDA

MSRCID

[3]

OV

DD

GND

UDE

SYSCLK

DETAIL B

Figure 4. Chip Pin Map Detail B

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

6

Pin Assignments and Reset States

DETAIL C

MDQ

[26]

MDIC

[1]

VDD_

CORE

VDD_

CORE

MDQ

[31]

GV

DD

GV

DD

GND

[0]

GND

15

16

17

18

19

20

21

22

23

24

25

26

27

28

LCS5/

DMA_

DREQ2

LCS6/

DMA_

DACK2

VDD_

CORE

VDD_

CORE

MDQ

[30]

MDQS

[3]

MDQ

[19]

MDQ

[23]

MDQ

[18]

LA

[28]

LCS

[4]

GND

MDM

[3]

VDD_

PLAT

VDD_

PLAT

MDQS

[2]

MDQ

[22]

LA

[31]

LA

[30]

LA

[29]

MDQS

[3]

GV

DD

GND

LCS7/

DMA_

DDONE2

MDQ

[25]

MDQ

[24]

MDM

[2]

MDQ

[21]

VDD_

PLAT

MDQS

[2]

LCS

[0]

LGPL3/

LFWP

GV

DD

BV

DD

GND

MDQ

[29]

MDQ

[28]

MDQ

[17]

MDQ

[16]

MDQ

[20]

LA

[27]

VDD_

PLAT

VDD_

PLAT

LCS

[1]

LCS

[2]

BV

DD

NC

LGPL5

GND

LGPL4/

LGPL2/

LOE/

LFRE

LGTA/

LUPWAIT/

LPBSE/

LFRB

MDQ

[11]

MDQ

[10]

LGPL0/ LGPL1/

LCS

[3]

SD1_TX

[1]

GV

DD

BV

DD

XV

DD

GND

XGND

LFCLE

LFALE

MDQ

[15]

MDQ

[14]

MDQ

[3]

MDQ

[7]

LAD

[31]

LAD

[1]

LWE[3]/

LBS[3]

SD1_TX

[1]

GV

DD

BV

DD

XV

DD

GND

XGND

GND

LWE0/

LBS0/

LFWE

MDQS

[1]

MDQ

[2]

MDQ

[6]

LAD

[29]

LAD

[30]

LWE[1]/

LBS[1]

LAD

[0]

LAD

[2]

MDQS

[1]

SD1_TX

[0]

SD1_TX

[2]

GV

DD

XGND

MDQ

[9]

MDM

[1]

MDQS

[0]

LAD

[27]

LAD

[28]

LWE[2]/

LBS[2]

SD1_TX

[0]

SD1_TX

[2]

LAD

[3]

BV

DD

BV

DD

BV

DD

XV

DD

GND

MDQ

[8]

MDQ

[13]

MDQS

[0]

LAD

[24]

LAD

[23]

LAD

[26]

LCLK

[0]

LCLK

[1]

LAD

[4]

LAD

[5]

GV

DD

XGND

NC

SGND

MDQ

[12]

MDQ

[5]

MDM

[0]

MDQ

[4]

LCLK

[2]

LAD

[7]

LAD

[6]

LDP

[3]

LAD

[19]

SD1_RX

[1]

SV

DD

LBCTL

LALE

GND

SD1_

IMP_CAL

_RX

MDQ

[0]

MDQ

[1]

LAD

[25]

LAD

[22]

LAD

[18]

LAD

[16]

SD1_RX

[1]

LDP

[0]

BV

DD

GND

SGND

LDP

[2]

LAD

[21]

LAD

[15]

LAD

[14]

LAD

[11]

LAD

[9]

SD1_RX

[0]

LSYNC_

IN

SV

DD

SGND

GND

AVDD_ LSYNC_

LAD

[20]

LAD

[17]

LAD

[13]

LAD

[12]

LAD

[10]

LAD

[8]

SD1_RX

[0]

LDP

[1]

SV

DD

MVREF

A

GND

B

SGND

M

LBIU

OUT

C

D

E

F

G

H

J

K

L

N

P

Figure 5. Chip Pin Map Detail C

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

7

Pin Assignments and Reset States

DETAIL D

SENSE-

VDD_

CORE

PCI1_

AD

PCI1_

AD

PCI1_REQ PCI1_GNT

CLK_

OUT

PCI1_REQ

[4]/GPIO

[1]

IIC2_

SCL

VDD_

CORE

HRESET_

REQ

GND

RTC

15

16

17

18

19

20

21

22

23

24

25

26

27

28

[3]/GPIO

[0]

[3]/GPIO

[2]

[31]

[28]

PCI1_

REQ

[1]

PCI1_

AD

[26]

PCI1_

IDSEL

VDD_

CORE

VDD_

CORE

IRQ

[5]

AVDD_

CORE

SENSE-

VSS

OV

DD

OV

DD

GND

HRESET

GNT

[1]

REQ

[0]

SENSE-

VDD_

PLAT

PCI1_

AD

[30]

PCI1_

AD

[29]

PCI1_

AD

[27]

PCI1_

AD

[24]

PCI1_

AD

[23]

VDD_

PLAT

VDD_

PLAT

IRQ_

OUT

IRQ

[1]

IRQ

[4]

CKSTP_

OUT

GND

PCI1_

C_BE

[3]

PCI1_

GNT

[0]

PCI1_

AD

[25]

PCI1_

AD

[22]

PCI1_

AD

[20]

PCI1_

AD

[18]

VDD_

PLAT

VDD_

PLAT

AVDD_

PLAT

CKSTP_

IN

OV

DD

OV

DD

GND

TRIG_

OUT/READY

/QUIESCE

PCI1_

AD

[21]

PCI1_

AD

[19]

PCI1_

AD

[17]

VDD_

PLAT

AVDD_

DDR

IRQ

[7]

IRQ

[3]

GND

TRIG_IN

GND

SRESET

ASLEEP

PCI1_

C_BE

[2]

PCI1_

AD

[16]

L2_

PCI1_

AVDD_

PCI1

PCI1_

IRDY

SD1_TX

[3]

SD1_TX

[4]

SD1_TX

[6]

XV

DD

XV

DD

OV

DD

XGND

TSTCLK

FRAME

L1_

PCI1_

DEVSEL

PCI1_

STOP

PCI1_

TRDY

IIC1_

SCL

PCI1_

PERR

SD1_TX

[3]

SD1_TX

[4]

SD1_TX

[6]

XV

DD

XGND

Rsvd

XGND

GND

TRST

TSTCLK

PCI1_

C_BE

[1]

IIC1_

SDA

PCI1_

PAR

PCI1_

SERR

IRQ

[6]

IRQ

[8]

IRQ

[0]

SD1_TX

[5]

SD1_TX

[7]

XV

DD

XV

DD

OV

DD

XGND

PCI1_

AD

[13]

PCI1_

AD

[14]

PCI1_

AD

[15]

PCI1_

AD

[11]

SD1_TX

[5]

SD1_TX

[7]

IRQ

[2]

XV

DD

XV

DD

XGND

GND

PCI1_

AD

[5]

PCI1_

AD

[7]

PCI1_

AD

[9]

PCI1_

AD

[10]

PCI1_

AD

[12]

SV

DD

SV

DD

SV

DD

SV

DD

OV

DD

SGND

NC

SGND

PCI1_

C_BE

[0]

PCI1_

AD

[1]

PCI1_

AD

[4]

PCI1_

AD

[8]

LSSD_

MODE

SD1_RX

[3]

SD1_RX

[4]

SD1_RX

[6]

SV

DD

SV

DD

OV

DD

SGND

SD1_

PLL_

TPA

PCI1_

AD

[0]

PCI1_

AD

[2]

PCI1_

AD

[3]

PCI1_

CLK

SD1_RX

[3]

SD1_RX

[4]

SD1_RX

[6]

POWER_

OK

SV

DD

SV

DD

SGND

GND

SD1_

REF_

CLK

PCI1_

AD

[6]

AGND_

SRDS

SD1_RX

[2]

SD1_RX

[5]

SD1_RX

[7]

POWER_

EN

OV

DD

SV

DD

SV

DD

SV

DD

NC

SGND

TMS

SD1_

REF_

CLK

SD1_

PLL_

TPD

SD1_

SGND IMP_CAL

_TX

AVDD_

SRDS

SD1_RX

[2]

SD1_RX

[5]

SD1_RX

[7]

SV

DD

SGND

T

SGND

Y

TDO

AF

TCK

AG

TDI

AH

R

U

V

W

AA

AB

AC

AD

AE

Figure 6. Chip Pin Map Detail D

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

8

Pin Assignments and Reset States

This table provides the pin-out listing for the 783 FC-PBGA package.

Table 1. Pinout Listing

Power

Supply

Signal

Signal Name

Package Pin Number Pin Type

Notes

PCI

AB15,Y17,AA17,AC15,

PCI1_AD[31:0]

Muxed Address / data

I/O

OV_DD

29

AB17,AC16,AA18,

AD17,AE17,AB18,

AB19,AE18,AC19,

AF18,AE19,AC20,

AF23,AE23,AC23,

AH24,AH23,AG24,

AE24,AG25,AD24,

AG27,AC24,AF25,

AG26,AF26,AE25,

AD26

PCI1_C_BE[3:0]

Command/Byte Enable

AD18, AD20,AD22,

AH25

I/O

OV_DD

29

PCI1_PAR

Parity

AC22

I/O

I

OV_DD

29

2,29

29

PCI1_FRAME

PCI1_TRDY

Frame

AE20

Target Ready

Initiator Ready

Stop

AF21

PCI1_IRDY

AB20

PCI1_STOP

AD21

PCI1_DEVSEL

PCI1_IDSEL

Device Select

Init Device Select

Parity Error

System Error

Request

AC21

AE16

PCI1_PERR

AB21

I/O

I

2,29

2,4,29

—

PCI1_SERR

AF22

PCI1_REQ[4:3]/GPIO[1:0]

PCI1_REQ[2:1]

PCI1_REQ[0]

PCI1_GNT[4:3]/GPIO[3:2]

PCI1_GNT[2:1]

PCI1_GNT[0]

PCI1_CLK

AE15,Y15

AF13,W16

AA16

Request

I

29

Request

I/O

O

29

Grant

AC14, AA15

AF14,Y16

W18

—

Grant

O

5,9,25,29

29

Grant

I/O

I

PCI Clock

AH26

29

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

9

Pin Assignments and Reset States

Table 1. Pinout Listing (continued)

Signal Name Package Pin Number Pin Type

Power

Supply

Signal

Notes

DDR SDRAM Memory Interface

A26,B26,C22,D21,D25,

MDQ[0:63]

Data

I/O

GV_DD

—

B25,D22,E21,A24,A23,

B20,A20,A25,B24,B21,

A21,E19,D19,E16,C16,

F19,F18,F17,D16,B18,

A18,A15,B14,B19,A19,

A16,B15,D1,F3,G1,H2,

E4,G5,H3,J4,B2,C3,F2,

G2,A2,B3,E1,F1,L5,L4,

N3,P3,J3,K4,N4,P4,J1,

K1,P1,R1,J2,K2,P2,R2

MECC[0:7]

Error Correcting Code

G12,D14,F11,C11,

G14,F14,C13,D12

I/O

GV_DD

—

MAPAR_ERR

MAPAR_OUT

MDM[0:8]

Address Parity Error

Address Parity Out

Data Mask

A13

A6

I

GV_DD

—

O

C25,B23,D18,B17,G4,

C2,L3,L2,F13

MDQS[0:8]

MA[0:15]

Data Strobe

Address

D24,B22,C18,A17,J5,

C1,M4,M2,E13

I/O

O

GV_DD

—

C23,A22,E17,B16,K5,

D2,M3,N1,D13

B7,G8,C8,A10,D9,C10,

A11,F9,E9,B12,A5,

A12,D11,F7,E10,F10

MBA[0:2]

MWE

Bank Select

A4,B5,B13

O

GV_DD

—

11

—

Write Enable

B4

MRAS

Row Address Strobe

Column Address Strobe

Chip Select

C5

MCAS

E7

MCS[0:3]

MCKE[0:3]

MCK[0:5]

D3,H6,C4,G6

H10,K10,G10,H9

A9,J11,J6,A8,J13,H8

Clock Enable

Differential Clock 3 Pairs /

DIMM

MCK[0:5]

Differential Clock 3 Pairs /

DIMM

B9,H11,K6,B8,H13,J8

O

GV_DD

—

MODT[0:3]

MDIC[0:1]

On Die Termination

Calibration

E5,H7,E6,F6

H15,K15

O

GV_DD

—

I/O

26

Local Bus Controller Interface

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

10

Pin Assignments and Reset States

Power

Table 1. Pinout Listing (continued)

Signal Name

Signal

Package Pin Number Pin Type

Notes

Supply

LAD[0:31]

Muxed data / address

K22,L21,L22,K23,K24,

L24,L25,K25,L28,L27,

K28,K27,J28,H28,H27,

G27,G26,F28,F26,F25,

E28,E27,E26,F24,E24,

C26,G24,E23,G23,F22,

G22,G21

I/O

BV_DD

5,9,29

LDP[0:3]

LA[27]

Data parity

K26,G28,B27,E25

L19

I/O

O

BV_DD

29

Burst address

Port address

Chip selects

5,9,29

5,7,9,29

29

LA[28:31]

LCS[0:4]

K16,K17,H17,G17

K18,G19,H19,H20,G16

O

LCS5/DMA_DREQ2

LCS6/DMA_DACK2

LCS7/DMA_DDONE2

LWE0/LBS0/LFWE

LWE[1:3]/LBS[1:3]

LBCTL

Chips selects / DMA Request H16

I/O

O

1,29

Chips selects / DMA Ack

Chips selects / DMA Done

Write enable / Byte select

Buffer control

J16

1,29

L18

O

1,29

J22

O

5,9,29

5,8,9,29

5,9,29

H22,H23,H21

O

J25

J26

O

LALE

Address latch enable

O

LGPL0/LFCLE

UPM general purpose line 0 / J20

FLash command latch enable

O

LGPL1/LFALE

UPM general purpose line 1 / K20

Flash address latch enable

O

BV_DD

5,9,29

LGPL2/LOE/LFRE

UPM general purpose line 2 / G20

Output enable/Flash read

enable

5,8,9,29

LGPL3/LFWP

UPM general purpose line 3 / H18

Flash write protect

O

BV_DD

5,9,29

29, 33

LGPL4/LGTA/LUPWAIT

/LPBSE/LFRB

UPM general purpose line 4 / L20

Target Ack/Wait/SDRAM

parity byte select/Flash

Ready-busy

I/O

LGPL5

UPM general purpose line 5 / K19

Amux

O

BV_DD

5,9,29

LCLK[0:2]

Local bus clock

Synchronization

Local bus DLL

H24,J24,H25

O

I

BV_DD

29

LSYNC_IN

LSYNC_OUT

D27

D28

O

DMA

AD6,AE10

DMA_DACK[0:1]

/GPIO[10:11]

DMA Acknowledge

O

OV_DD

—

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

11

Pin Assignments and Reset States

Table 1. Pinout Listing (continued)

Signal Name Package Pin Number Pin Type

DMA Request

DMA Done

Power

Supply

Signal

Notes

DMA_DREQ[0:1]

/GPIO[14:15]

AB10,AD11

AA11,AB11

I

OV_DD

—

DMA_DDONE[0:1]

/GPIO[12:13]

O

OV_DD

—

DMA_DREQ[2]/LCS[5]

DMA_DACK[2]/LCS[6]

DMA_DDONE[2]/LCS[7]

DMA_DREQ[3]/IRQ[9]

Chips selects / DMA Request H16

I/O

O

I

BV_DD

OV_DD

1,29

1

Chips selects / DMA Ack

Chips selects / DMA Done

J16

L18

External interrupt/DMA

request

AE13

DMA_DACK[3]/IRQ[10]

DMA_DDONE[3]/IRQ[11]

External interrupt/DMA Ack

AD13

I/O

OV_DD

1

External interrupt/DMA done AD14

USB Port 1

USB1_D[7:0]

USB1 Data bits

AF1,AE2,AE1,AD2,

I/O

OV_DD

—

AC2,AC1,AB2,AB1

USB1_NXT

USB1 Next data

AF2

AH1

AG1

AH2

AC3

AC4

AD1

I

OV_DD

—

5,9

—

USB1_DIR

USB1 Data Direction

USB1 Stop

USB1_STP

O

I

USB1_PWRFAULT

USB1_PCTL0/GPIO[6]

USB1_PCTL1/GPIO[7]

USB1_CLK

USB1 bus power fault.

USB1 Port control 0

USB1 Port control 1

USB1 bus clock

O

I

USB Port 2

USB2_D[7:0]

USB2 Data bits

AE6,AC6,AF5,AE5,

AF4,AE4,AE3,AD3

I/O

OV_DD

—

USB2_NXT

USB2 Next data

AC7

AF7

AD7

AC8

AG9

AC9

AD5

I

OV_DD

—

5,9

—

USB2_DIR

USB2 Data Direction

USB2 Stop

USB2_STP

O

I

USB2_PWRFAULT

USB2_PCTL0/GPIO[8]

USB2_PCTL1/GPIO[9]

USB2_CLK

USB2 bus power fault.

USB2 Port control 0

USB2 Port control 1

USB2 bus clock

O

I

USB Port 3

USB3_D[7:0]

USB3_NXT

USB3 Data bits

USB3 Next data

AH7,AG6,AH6,AG5,

AG4,AH4,AG3,AH3

I/O

I

OV_DD

—

AG7

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

12

Pin Assignments and Reset States

Power

Table 1. Pinout Listing (continued)

Signal Name

Signal

Package Pin Number Pin Type

Notes

Supply

USB3_DIR

USB3_STP

Reserved

USB3 Data Direction

AG8

AH8

AH9

AH5

I

O

—

I

OV_DD

—

27

—

USB3 Stop

—

USB3_CLK

USB3 bus clock

OV_DD

Programmable Interrupt Controller

MCP

Machine check processor

Y14

I

OV_DD

—

UDE

Unconditional debug event

External interrupts

AB14

IRQ[0:8]

AG22,AF17,AB23,

AF19,AG17,AF16,

AA22,Y19,AB22

IRQ[9]/DMA_DREQ[3]

External interrupt/DMA

request

AE13

I

OV_DD

1

IRQ[10]/DMA_DACK[3]

IRQ[11]/DMA_DDONE[3]

IRQ_OUT

External interrupt/DMA Ack

AD13

I/O

O

OV_DD

1

External interrupt/DMA done AD14

Interrupt output AC17

Ethernet Management Interface

2,4

EC_MDC

EC_MDIO

Management data clock

Management data In/Out

Y10

Y11

O

OV_DD

5,9,22

—

I/O

Gigabit Reference Clock

EC_GTX_CLK125

TSEC1_TXD[7:0]

Reference clock

AA6

I

LV_DD

31

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

Transmit data

AA8,AA5,Y8,Y5,W3,

W5,W4,W6

O

5,9,22

TSEC1_TX_EN

TSEC1_TX_ER

TSEC1_TX_CLK

TSEC1_GTX_CLK

TSEC1_CRS

Transmit Enable

Transmit Error

Transmit clock In

Transmit clock Out

Carrier sense

W1

O

I

LV_DD

23

5,9

—

AB5

AB4

W2

O

I/O

I

—

AA9

AB6

17

—

TSEC1_COL

Collision detect

Receive data

TSEC1_RXD[7:0]

AB3,AB7,AB8,Y6,AA2,

Y3,Y1,Y2

I

—

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_RX_CLK

Receive data valid

Receive data error

Receive clock

AA1

Y9

I

LV_DD

—

AA3

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

13

Pin Assignments and Reset States

Table 1. Pinout Listing (continued)

Signal Name Package Pin Number Pin Type

Transmit data

Transmit Enable

Power

Supply

Signal

Notes

TSEC3_TXD[7:0]

T12,V8,U8,V9,T8,T7,

T5,T6

O

TV_DD

5,9,22

TSEC3_TX_EN

TSEC3_TX_ER

TSEC3_TX_CLK

TSEC3_GTX_CLK

TSEC3_CRS

V5

O

I

TV_DD

23

5,9

—

Transmit Error

Transmit clock In

Transmit clock Out

Carrier sense

U9

U10

U5

O

I/O

I

—

T10

T9

17

—

TSEC3_COL

Collision detect

Receive data

TSEC3_RXD[7:0]

U12,U13,U6,V6,V1,U3,

U2,V3

I

—

TSEC3_RX_DV

TSEC3_RX_ER

TSEC3_RX_CLK

Receive data valid

Receive data error

Receive clock

V2

T4

U1

I

TV_DD

—

IEEE 1588

TSEC_1588_CLK

Clock In

W9

I

LV_DD

29

TSEC_1588_TRIG_IN[0:1]

Trigger In

W8,W7

U11,W10

V10

I

29

TSEC_1588_TRIG_OUT[0:1] Trigger Out

TSEC_1588_CLK_OUT Clock Out

O

5,9,29

TSEC_1588_PULSE_OUT1 Pulse Out1

TSEC_1588_PULSE_OUT2 Pulse Out2

V11

T11

eSDHC

SDHC_CMD

Command line

Card detection

Data line

AH10

AH11

I/O

I

OV_DD

29

—

29

SDHC_CD/GPIO[4]

SDHC_DAT[0:3]

AG12,AH12,AH13,

AG11

I/O

SDHC_DAT[4:7] /

SPI_CS[0:3]

8-bit MMC Data line / SPI chip AE8,AC10,AF9,AA10

select

I/O

OV_DD

29

SDHC_CLK

SD/MMC/SDIO clock

Card write protection

AG13

AG10

I/O

I

OV_DD

29

SDHC_WP/GPIO[5]

1, 32

eSPI

SPI_MOSI

SPI_MISO

SPI_CLK

Master Out Slave In

Master In Slave Out

eSPI clock

AF8

AD9

AD8

I/O

I

OV_DD

29

I/O

SPI_CS[0:3] /

SDHC_DAT[4:7]

eSPI chip select / SDHC 8-bit AE8,AC10,AF9,AA10

MMC data

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

14

Pin Assignments and Reset States

Power

Table 1. Pinout Listing (continued)

Signal

Signal Name

Package Pin Number Pin Type

Notes

Supply

DUART

UART_CTS[0:1]

Clear to send

AE11,Y12

I

OV_DD

29

UART_RTS[0:1]

UART_SIN[0:1]

UART_SOUT[0:1]

Ready to send

Receive data

Transmit data

AB12,AD12

AC12,AF12

AF10,AA12

O

I

O

5,9,22,

10,29

I²C interface

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

Serial clock

Serial data

Serial clock

Serial data

AG21

AH22

AH15

AG14

I/O

OV_DD

4,21,29

SerDes1(x8)

SD1_TX[7:0]

SD1_RX[7:0]

Transmit Data (+)

Transmit Data(-)

Receive Data(+)

Receive Data(–)

Y23,W21,V23,U21,

R21,P23,N21,M23

O

I

XV_DD

—

Y22,W20,V22,U20,

R20,P22,N20,M22

AC28,AB26,AA28,Y26,

T26,R28,P26,N28

AC27,AB25,AA27,Y25,

T25,R27,P25,N27

I

SD1_PLL_TPD

SD1_REF_CLK

PLL test point Digital

PLL Reference clock

V28

U28

U27

O

I

XV_DD

18

—

PLL Reference clock

complement

I

Reserved

—

T22

T23

—

18

SerDes2(x2)

SD2_TX[1:0]

SD2_RX[1:0]

SD2_PLL_TPD

SD2_REF_CLK

Transmit data(+)

Transmit data(-)

M11, P11

M12, P12

N8, P6

N9, P7

L7

O

I

X2V_DD

—

18

—

Receive data(+)

Receive data(-)

I

PLL test point Digital

PLL Reference clock

O

I

M6

PLL Reference clock

complement

M7

I

Reserved

—

L8

—

X2V_DD

18

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

15

Pin Assignments and Reset States

Table 1. Pinout Listing (continued)

Power

Supply

Signal

Signal Name

Package Pin Number Pin Type

Notes

Reserved

—

L9

—

X2V_DD

18

General-Purpose Input/Output

GPIO[0:1]/PCI1_REQ[3:4]

GPIO[2:3]/PCI1_GNT[3:4]

GPIO[4]/SDHC_CD

GPIO/PCI request

GPIO/PCI grant

GPIO/SDHC card detection AH11

GPIO/SDHC write protection AG10

Y15,AE15

I/O

OV_DD

—

32

—

AA15,AC14

GPIO[5]/SDHC_WP

GPIO[6]/USB1_PCTL0

GPIO[7]/USB1_PCTL1

GPIO[8]/USB2_PCTL0

GPIO[9]/USB2_PCTL1

GPIO/USB1 PCTL0

GPIO/USB1 PCTL1

GPIO/USB2 PCTL0

GPIO/USB2 PCTL1

GPIO/DMA Ack

AC3

AC4

AG9

AC9

GPIO[10:11]

AD6,AE10

/DMA_DACK[0:1]

GPIO[12:13]

/DMA_DDONE[0:1]

GPIO/DMA done

AA11,AB11

AB10,AD11

I/O

OV_DD

—

GPIO[14:15]

GPIO/DMA request

/DMA_DREQ[0:1]

System Control

HRESET

Hard reset

AG16

AG15

AG19

AG18

AH17

I

O

I

OV_DD

—

22

—

HRESET_REQ

SRESET

Hard reset - request

Soft reset

CKSTP_IN

CKSTP_OUT

CheckStop in

CheckStop Output

I

—

O

2,4

Debug

TRIG_IN

Trigger in

W19

V19

I

OV_DD

—

TRIG_OUT/READY

/QUIESCE

Trigger out/Ready/Quiesce

O

22

MSRCID[0:1]

MSRCID[2:4]

MDVAL

Memory debug source port ID W12,W13

O

OV_DD

6,9

6,9,22

6,22

11

Memory debug source port ID V12, W14,W11

Memory debug data valid

Clock Out

V13

CLK_OUT

W15

Clock

RTC

Real time clock

AF15

AH14

AC13

I

OV_DD

—

30

SYSCLK

DDRCLK

System clock / PCI clock

DDR clock

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

16

Pin Assignments and Reset States

Power

Table 1. Pinout Listing (continued)

Signal

Signal Name

Package Pin Number Pin Type

Notes

Supply

JTAG

TCK

TDI

Test clock

AG28

AH28

AF28

AH27

AH21

I

OV_DD

—

12

11

12

Test data in

TDO

TMS

TRST

Test data out

Test mode select

Test reset

O

I

DFT

L1_TSTCLK

L2_TSTCLK

LSSD_MODE

TEST_SEL

L1 test clock

L2 test clock

LSSD Mode

Test select

AA21

AA20

AC25

AA13

I

OV_DD

19

Power Management

ASLEEP

Asleep

AG20

AC26

AE27

O

I

OV_DD

9,16,22

—

POWER_OK

POWER_EN

Power OK

Power enable

O

—

Power and Ground Signals

OVDD

General I/O supply

Y18,AG2,AD4,AB16,

AF6,AC18,AB13,AD10,

AE14,AD16,AD25,

AF27,AE22,AF11,

AF20,AF24

—

OV_DD

—

LVDD

TVDD

GVDD

GMAC 1 I/O supply

GMAC 3 I/O supply

SSTL2 DDR supply

AA7, AA4

Power for

TSEC1

interfaces

LV_DD

TV_DD

GV_DD

—

V4,U7

Power for

TSEC3

interfaces

B1,B11,C7,C9,C14,

C17,D4,D6,R3,D15,E2,

E8,C24,E18,F5,E14,

C21,G3,G7,G9,G11,

H5,H12,E22,F15,J10,

K3,K12,K14,H14,D20,

E11,M1,N5

Power for

DDR

DRAM I/O

BVDD

Local bus I/O supply

L23,J18,J23,J19,F20,

F23,H26,J21

Power for

Local Bus

BV_DD

—

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

17

Pin Assignments and Reset States

Table 1. Pinout Listing (continued)

Signal Name Package Pin Number Pin Type

SerDes 1 core logic supply

Power

Supply

Signal

Notes

SVDD

XVDD

M27,N25,P28,R24,

R26,T24,T27,U25,

W24,W26,Y24,Y27,

AA25,AB28,AD27

—

SV_DD

—

SerDes 1 transceiver supply M21,N23,P20,R22,T20,

—

XV_DD

—

U23,V21,W22,Y20,

AA23

S2VDD

SerDes 2 core logic supply

R6,N7,M9

—

S2V_DD

X2V_DD

—

X2VDD

SerDes 2 transceiver supply R11,N12,L11

VDD_CORE

Core, L2 logic supply

Platform logic supply

P13,U16,L16,M15,N14,

V_{DD_CORE}

R14,P15,N16,M13,

U14,T13,L14,T15,R16,

K13

VDD_PLAT

T19,T17,V17,U18,R18,

N18,M19,P19,P17,M17

—

V_{DD_PLAT}

—

AVDD_CORE

AVDD_PLAT

AVDD_DDR

CPU PLL supply

Platform PLL supply

DDR PLL supply

Local Bus PLL supply

PCI PLL supply

SerDes 1 PLL supply

SerDes 2 PLL supply

—

AH16

AH18

AH19

C28

—

AV_{DD_CORE}

AV_{DD_PLAT}

AV_{DD_DDR}

AV_{DD_LBIU}

AV_{DD_PCI1}

AV_{DD_SRDS}

AV_{DD_SRDS2}

V_{DD_CORE}

V_{DD_PLAT}

—

20,28

20

AVDD_LBIU

20

AVDD_PCI1

AH20

W28

T1

20

AVDD_SRDS

AVDD_SRDS2

SENSEVDD_CORE

SENSEVDD_PLAT

GND

20

V15

13

—

W17

13

Ground

D5,AE7,F4,D26,D23,

C12,C15,E20,D8,B10,

AF3,E3,J14,K21,F8,A3,

F16,E12,E15,D17,L1,

F21,H1,G13,G15,G18,

C6,A14,A7,G25,H4,

C20,J12,J15,J17,F27,

M5,J27,K11,L26,K7,

K8,T14,V14,M16,M18,

P14,N15,N17,N19,N2,

P5,P16,P18,M14,R15,

R17,R19,T16,T18,L17,

U15,U17,U19,V18,C27,

Y13,AE26,AA19,AE21,

B28,AC11,AD19,AD23,

L15,AD15,AG23,AE9,

A27,V7,Y7,AC5,U4,Y4,

AE12,AB9,AA14,N13,

R13,L13

—

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

18

Pin Assignments and Reset States

Power

Table 1. Pinout Listing (continued)

Signal Name

Signal

Package Pin Number Pin Type

Notes

Supply

XGND

SGND

SerDes 1Transceiver pad

GND (xpadvss)

M20,M24,N22,P21,

R23,T21,U22,V20,

W23, Y21

—

SerDes 1 Transceiver core

logic GND (xcorevss)

M28,N26,P24,P27,

R25,T28,U24,U26,V24,

W25,Y28,AA24,AA26,

AB24,AB27,AD28

—

X2GND

S2GND

SerDes 2 Transceiver pad

GND (xpadvss)

R12,M10,N11,L12

—

SerDes 2 Transceiver core

logic GND (xcorevss)

P8,P9,N6,M8

AGND_SRDS

AGND_SRDS2

SENSEVSS

SerDes 1 PLL GND

SerDes 2 PLL GND

GND Sensing

V27

T2

—

13

V16

Analog Signals

MVREF

SSTL2 reference voltage

A28

Reference

voltage for

DDR

GVDD/2

—

SD1_IMP_CAL_RX

SD1_IMP_CAL_TX

SD1_PLL_TPA

Rx impedance calibration

Tx impedance calibration

PLL test point analog

M26

AE28

V26

R7

—

200Ω (±1%)

to GND

—

18

—

18

100Ω (±1%)

to GND

AVDD_SRD

S analog

SD2_IMP_CAL_RX

SD2_IMP_CAL_TX

SD2_PLL_TPA

Rx impedance calibration

Tx impedance calibration

PLL test point analog

200Ω (±1%)

to GND

L6

100Ω (±1%)

to GND

T3

AVDD_SRD

S2 analog

Reserved

R4

R5

—

No Connect Pins

C19,D7,D10,L10,R10,

NC

—

B6,F12,J7,P10,M25,

W27,N24,N10,R8,J9,

K9,V25,R9

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

19

Pin Assignments and Reset States

Table 1. Pinout Listing (continued)

Signal Name Package Pin Number Pin Type

Power

Supply

Signal

Notes:

Notes

1. All multiplexed signals may be listed only once and may not re-occur.

2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OV_DD

.

3. This pin must always be pulled-high.

4. This pin is an open drain signal.

5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if

the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net

at reset, then a pullup or active driver is needed.

6. Treat these pins as no connects (NC) unless using debug address functionality.

7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down

resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.”

8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ

pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.”

9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.

10. For proper state of these signals during reset, these pins can be left without any pulldowns, thus relying on the internal

pullup to get the values to the require 2'b11.However, if there is any device on the net which might pull down the value of the

net at reset, then a pullup is needed.

11. This output is actively driven during reset rather than being three-stated during reset.

12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13. These pins are connected to the V_{DD_CORE}/V_{DD_PLAT}/GND planes internally and may be used by the core power supply to

improve tracking and regulation.

15. These pins have other manufacturing or debug test functions. It is recommended to add both pull-up resistor pads to OVDD

and pull-down resistor pads to GND on board to support future debug testing when needed.

16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe

state during reset.

17. This pin is only an output in FIFO mode when used as Rx Flow Control.

18. Do not connect.

19.These must be pulled up (100 Ω- 1 kΩ) to OVDD.

20. Independent supplies derived from board VDD.

21. Recommend a pull-up resistor (1 KΩ) be placed on this pin to OVDD.

22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0:1], EC_MDC,

TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.

23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is

actively driven.

24. General-Purpose POR configuration of user system.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

20

Freescale Semiconductor

Electrical Characteristics

Table 1. Pinout Listing (continued)

Signal Name Package Pin Number Pin Type

Power

Notes

Signal

Supply

25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled

down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No

Connect” or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the address pins are not

connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through

POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is

any other PCI device connected on the bus.

26. When operating in DDR2 mode, connect MDIC[0] to ground through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength

mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength

mode) precision 1% resistor. When operating in DDR3 mode, connect MDIC[0] to ground through an 20-Ω (full-strength

mode) or 40-Ω (half-strength mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 20-Ω (full-strength

mode) or 40-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs.

27. Connect to GND through a pull down 1 kΩ resistor

28. It must be the same as VDD_CORE

29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when

GCR[DEEPSLEEP_Z] =1.

30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is

configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is

recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICC

III Integrated Host Processor Family Reference Manual, Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2

“DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding DDR controller

operation in asynchronous and synchronous modes.

31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and

RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.

32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for

SD/MMC card specification.

33. For systems that boot from Local Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is

required.

2

Electrical Characteristics

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

This table provides the absolute maximum ratings.

1

Table 2. Absolute Maximum Ratings

Characteristic

Symbol

Max Value

Unit Notes

Core supply voltage

V_{DD_CORE}

V_{DD_PLAT}

AV_{DD_CORE}

AV_DD

–0.3 to 1.21

–0.3 to 1.1

–0.3 to 1.21

–0.3 to 1.1

V

—

Platform supply voltage

PLL core supply voltage

PLL other supply voltage

Core power supply for SerDes transceivers

SV_DD, S2V_DD

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

21

Electrical Characteristics

1

Table 2. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Max Value

Unit Notes

Pad power supply for SerDes transceivers and PCI Express

XV_DD,X2V_DD

GV_DD

–0.3 to 1.1

–0.3 to 1.98

–0.3 to 1.65

V

—

DDR SDRAM

Controller I/O

supply voltage

DDR2 SDRAM Interface

DDR3 SDRAM Interface

Three-speed Ethernet I/O

LV_DD(eTSEC1)

TV_DD(eTSEC3)

OV_DD

–0.3 to 3.63

–0.3 to 2.75

V

2

–0.3 to 3.63

–0.3 to 2.75

PCI, DUART, system control and power management, I²C, USB,

eSDHC, eSPI and JTAG I/O voltage, MII management voltage

–0.3 to 3.63

—

Local bus I/O voltage

BV_DD

–0.3 to 3.63

–0.3 to 2.75

–0.3 to 1.98

Input voltage

DDR2/DDR3 DRAM signals

DDR2/DDR3 DRAM reference

Three-speed Ethernet signals

MV_IN

–0.3 to (GV_DD+ 0.3)

V

3

—

3

MV_REF

LV_IN

TV_IN

–0.3 to (LV_DD+ 0.3)

–0.3 to (TV_DD+ 0.3)

Local bus signals

BV_IN

OV_IN

–0.3 to (BV_DD+ 0.3)

–0.3 to (OV_DD+ 0.3)

—

V

—

3

PCI, DUART, SYSCLK, system control and

power management, I²C, and JTAG signals

Storage temperature range

T_STG

–55 to 150

⁰C

—

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect chip reliability or cause

permanent damage to the chip.

2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V

maximum applies. See Section 2.9.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on

the recommended operating conditions per protocol.

3. (M,L,O)V_INand MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7.

2.1.2

Recommended Operating Conditions

This table provides the recommended operating conditions for this chip. Note that the values in this table are the recommended

and tested operating conditions. Proper chip operation outside these conditions is not guaranteed.

Table 3. Recommended Operating Conditions

Characteristic

Symbol

Recommended Value Unit Notes

Core supply voltage

V_{DD_CORE}

1.0 50 mV

1.1 55 mV

V

1

Platform supply voltage

PLL core supply voltage

V_{DD_PLAT}

1.0 50 mV

V

—

AV_{DD_CORE}

1.0 50 mV

1.1 55 mV

1,2

PLL other supply voltage

AV_DD

1.0 50 mV

V

2

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

22

Electrical Characteristics

Table 3. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended Value Unit Notes

Core power supply for SerDes transceivers

SV_DD

XV_DD

GV_DD

1.0 50 mV

1.8 V 90 mV

1.5 V 75 mV

V

—

3

Pad power supply for SerDes transceivers and PCI Express

DDR SDRAM

Controller I/O supply

voltage

DDR2 SDRAM Interface

DDR3 SDRAM Interface

Three-speed Ethernet I/O voltage

LV_DD

(eTSEC1)

3.3 V 165 mV

2.5 V 125 mV

V

5

TV_DD

(eTSEC3)

3.3 V 165 mV

2.5 V 125 mV

PCI, DUART, system control and power management, I²C, USB, eSDHC,

eSPI and JTAG I/O voltage, MII management voltage

OV_DD

3.3 V 165 mV

V

4

Local bus I/O voltage

BV_DD

3.3 V 165 mV

2.5 V 125 mV

1.8 V 90 mV

—

Input voltage

DDR2 and DDR3 SDRAM Interface signals

DDR2 and DDR3 SDRAM Interface reference

Three-speed Ethernet signals

MV_IN

GND to GV_DD

GV_DD/2 1%

V

3

—

5

MV_REF

LV_IN

TV_IN

GND to LV_DD

GND to TV_DD

Local bus signals

BV_IN

OV_IN

GND to BV_DD

GND to OV_DD

V

—

4

PCI, Local bus, DUART, SYSCLK, system control

and power management, I²C, and JTAG signals

Operating

Temperature range

Commercial

T_A= 0 (min) to

T_J= 90(max)

T_A= 0 (min) to

T_J= 105 (max)

Industrial

T_A

T_J

°C

6

standard temperature range

Extended temperature range

T_A= -40 (min) to

T_J= 105 (max)

Notes:

1. VDD = 1.0 V for 600 to 1333 MHz, 1.1 V for 1500 MHz,

2. This voltage is the input to the filter discussed in Section 3.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AVDD pin, which may be reduced from VDD by the filter.

3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

6. Minimum temperature is specified with T_A; maximum temperature is specified with T_J.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

23

Electrical Characteristics

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

B/G/L/OV_DD+ 20%

B/G/L/OV_DD+ 5%

B/G/L/OV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

1

of t_CLOCK

Note:

1. t_CLOCKrefers to the clock period associated with the respective interface:

For I²C and JTAG, t_CLOCKreferences SYSCLK.

For DDR, t_CLOCKreferences MCLK.

For eTSEC, t_CLOCKreferences EC_GTX_CLK125.

For eLBC, t_CLOCKreferences LCLK.

For PCI, t_CLOCKreferences PCI1_CLK or SYSCLK.

2. With the PCI overshoot allowed (as specified above), the device

does not fully comply with the maximum AC ratings and device protection

guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).

Figure 7. Overshoot/Undershoot Voltage for GV /OV /LV

DD

The core voltage must always be provided at nominal 1.0 V or 1.1 V. (See Table 3 for actual recommended core voltage).

Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages

shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. OV and LV based

DD

receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM

interface uses differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is

appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS

receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

24

Freescale Semiconductor

Electrical Characteristics

2.1.3

Output Driver Characteristics

This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 4. Output Drive Capability

Programmable

Supply

Driver Type

Output Impedance

Notes

Voltage

(Ω)

Local bus interface utilities signals

25

35

BV_DD= 3.3 V

BV_DD= 2.5 V

1

45(default)

125

BV_DD= 3.3 V

BV_DD= 2.5 V

BV_DD= 1.8 V

PCI signals

25

OV_DD= 3.3 V

2

42 (default)

DDR2 signal

DDR3 signal

16

GV_DD= 1.8 V

GV_DD= 1.5 V

3

2

32 (half strength mode)

20

40 (half strength mode)

TSEC signals

42

LV_DD= 2.5/3.3 V

OV_DD= 3.3 V

—

DUART, system control, JTAG

I²C

150

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset.

3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at T_j= 105°C and at GV_DD(min)

2.2

Power Sequencing

The chip requires its power rails to be applied in a specific sequence in order to ensure proper chip operation. These

requirements are as follows for power up:

1.

V

, V

(if POWER_EN is not used to control V

), AV , BV , LV , OV

,

DD_PLAT DD_CORE

DD_CORE

DD

SV ,S2V , TV , XV and X2V

DD

DD_CORE

2. [Wait for POWER_EN to assert], then V

(if POWER_EN is used to control V

)

DD_CORE

3. GV

DD

All supplies must be at their stable values within 50 ms.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered

sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step

reach 10% of theirs.

In order to guarantee MCKE low during power-up, the above sequencing for GV is required. If there is no concern about any

DD

of the DDR signals being in an indeterminate state during power-up, then the sequencing for GV is not required.

DD

From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with

that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the chip.

During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is

no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

25

Electrical Characteristics

2.3

Power Characteristics

The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III

chips is shown in the following table.

5

Table 5. Power Dissipation

Core

CCB

DDR

V_DD

Junction

Tempera

ture

V_DD

Frequen Frequen Frequen Platfor

Core Power

mean⁷

Platform Power⁹

Core ⁵

Power Mode

Notes

cy

m

(MHz)

(V)

(°C)

Max

mean⁷

Max

Maximum (A)

Thermal (W)

Typical (W)

Doze (W)

105

/90

—

4.1/3.3

3.7/2.9

—

4.7/3.7 1, 3, 8

4.7/3.7 1, 4, 8

1.5

1.2

0.8

0

1.5

1.4

1.0

0.6

—

1, 2

1

1.9

1.6

1.1

600

400

1.0

65

Nap (W)

1.5

1

Sleep (W)

1.5

1

Deep Sleep

(W)

35

0

6

Maximum (A)

Thermal (W)

Typical (W)

Doze (W)

105

/ 90

—

4.5/3.7

3.9/3.1

—

4.7/3.7 1, 3, 8

4.7/3.7 1, 4, 8

1.7

1.3

0.8

0

1.5

1.4

1.0

0.6

—

1, 2

1

2.1

1.9

1.6

1.1

800

1.0

65

Nap (W)

1.5

1

Sleep (W)

1.5

1

Deep Sleep

(W)

35

0

1,6

Maximum (A)

Thermal (W)

Typical (W)

Doze (W)

105

/ 90

—

4.8/4.0

4.1/3.3

—

4.7/3.7 1, 3, 8

4.7/3.7 1, 4, 8

1.9

1.4

0.8

0

1.5

1.4

1.0

0.6

—

1, 2

1

2.2

1.9

1.6

1.1

1000

1.0

65

35

Nap (W)

1.6

1

Sleep (W)

1.6

1

Deep Sleep

(W)

0

1, 6

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

26

Electrical Characteristics

5

Table 5. Power Dissipation (continued)

Core

CCB

DDR

V_DD

Junction

Tempera

ture

V_DD

Frequen Frequen Frequen Platfor

Core Power

Platform Power⁹

Notes

Core ⁵

Power Mode

cy

m

(MHz)

(V)

(°C)

mean⁷

Max

mean⁷

Max

Maximum (A)

Thermal (W)

Typical (W)

Doze (W)

105

/ 90

—

5.3/4.4

4.4/3.6

—

5.0/4.0 1, 3, 8

5.0/4.0 1, 4, 8

1

1250

500

1.0

65

2.2

1.6

0.8

0

1.7

1.5

1.1

0.6

2.4

1.6

0

2.1

1.7

1.2

1

Nap (W)

Sleep (W)

1

Deep Sleep

(W)

35

1, 6

Maximum (A)

Thermal (W)

—

5.4/4.6

4.5/3.7

—

5.2/4.1 1, 3, 8

5.2/4.1 1, 4, 8

1333

533

667

1.0

105

/ 90

Typical (W)

Doze (W)

Nap (W)

65

2.3

1.7

0.8

0

1.8

1.6

1.2

0.6

—

1, 2

1

2.5

1.6

0

2.1

1.7

1.2

1

Sleep (W)

1

Deep Sleep

(W)

35

1, 6

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

27

Electrical Characteristics

5

Table 5. Power Dissipation (continued)

Core

CCB

DDR

V_DD

Junction

Tempera

ture

V_DD

Frequen Frequen Frequen Platfor

Core Power

Platform Power⁹

Core ⁵

Power Mode

Notes

cy

m

(MHz)

(V)

(°C)

mean⁷

Max

mean⁷

Max

Maximum (A)

Thermal (W)

Typical (W)

Doze (W)

105

/ 90

—

7.1/6.1

5.9/4.9

—

5.0/4.0 1, 3, 8

5.0/4.0 1, 4, 8

1, 2

1500

500

667

1.0

1.1

65

3.0

2.2

1.1

0

1.7

1.5

1.1

0.6

3.3

2.1

0

2.1

1.7

1.2

1

Nap (W)

Sleep (W)

1

Deep Sleep

(W)

35

1, 6

Notes:

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (V_DD) and 65°C junction temperature

(see Table 3) while running the Dhrystone benchmark.

3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (V_DD

at maximum operating junction temperature (see Table 3) while running a smoke test which includes an entirely

L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy.

)

4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (V_DD

at maximum operating junction temperature (see Table 3) while running the Dhrystone benchmark.

)

5. VDD Core = 1.0 V for 600 to 1333 MHz, 1.1 V for 1500 MHz.

6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the

mean power measured with only external interrupts enabled and DDR in self refresh.

7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of

devices.

8. Maximum operating junction temperature (see Table 3) for Commercial Tier is 90 ⁰C, for Industrial Tier is 105 ⁰C.

9. Platform power is the power supplied to all the V

pins.

DD_PLAT

See Section 2.23.6.1, “SYSCLK to Platform Frequency Options,” for the full range of CCB frequencies that the chip supports.

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Electrical Characteristics

2.4

Input Clocks

2.4.1

System Clock Timing

This table provides the system clock (SYSCLK) AC timing specifications for the chip.

Table 6. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV_DD= 3.3 V 165 mV.

Parameter/Condition

SYSCLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f_SYSCLK

t_SYSCLK

t_KH, t_KL

33

7.5

0.6

40

—

133

30

MHz

ns

1

—

2

SYSCLK cycle time

SYSCLK rise and fall time

SYSCLK duty cycle

SYSCLK jitter

1.0

—

2.1

ns

t_{KHK SYSCLK}

/t

60

%

—

3, 4

—

+/-150

ps

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” and Section 2.23.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.

3. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on

SYSCLK.

2.4.2

PCI Clock Timing

When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK

input, but instead the PCI_CLK. This table provides the PCI reference clock AC timing specifications for the chip.

Table 7. PCICLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV_DD= 3.3 V 165 mV.

Parameter/Condition

PCICLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f_PCICLK

t_PCICLK

33

15

0.6

40

—

66

30

2.1

60

MHz

ns

—

1

PCICLK cycle time

PCICLK rise and fall time

PCICLK duty cycle

Notes:

t_KH, t_KL

1.0

—

ns

t

_KHK/t_PCICLK

%

—

1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.

2.4.3

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the

counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC

signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × t

, and minimum clock

CCB

low time is 2 × t

. There is no minimum RTC frequency; RTC may be grounded if not needed.

CCB

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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29

Electrical Characteristics

2.4.4

eTSEC Gigabit Reference Clock Timing

This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the chip.

Table 8. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time

f_G125

t_G125

—

125

8

—

MHz

ns

—

1

EC_GTX_CLK rise and fall time

LV_DD,TV_{DD =}2.5V

LV_DD,TV_{DD =}3.3V

t

_G125R/t_G125F

—

ns

0.75

1.0

EC_GTX_CLK125 duty cycle

t_G125H/t_G125

—

%

2

GMII, TBI

1000Base-T for RGMII, RTBI

45

47

55

53

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6 and 2.7V for

L/TVDD=3.3V at 0.6 V and 2.7 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125

duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 2.9.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T

reference clock.

2.4.5

DDR Clock Timing

This table provides the DDR clock (DDRCLK) AC timing specifications for the chip.

Table 9. DDRCLK AC Timing Specifications

At recommended operating conditions with OV_DDof 3.3V 5%.

Parameter/Condition

DDRCLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f_DDRCLK

t_DDRCLK

t_KH, t_KL

66

6.0

0.6

40

—

166

15.15

1.2

MHz

ns

1

—

2

DDRCLK cycle time

DDRCLK rise and fall time

DDRCLK duty cycle

DDRCLK jitter

1.0

—

ns

t_{KHK DDRCLK}

/t

60

%

—

3, 4

—

+/– 150

ps

Notes:

1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex

clock frequency does not exceed the maximum or minimum operating frequencies. See Section 2.23.4,

“DDR/DDRCLK PLL Ratio,” for ratio settings.

2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.

3. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.

4. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and

60 kHz on DDRCLK.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Freescale Semiconductor

Electrical Characteristics

2.4.6

Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency”

in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is

defined in Table 73.

For FIFO GMII mode:

FIFO TX/RX clock frequency <= platform clock frequency/3.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz

For FIFO encoded mode:

FIFO TX/RX clock frequency <= platform clock frequency/3.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than

167 MHz

2.4.7

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific

section of this document.

2.5

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of the chip. This table

provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min Max

Unit

Notes

Required assertion time of HREST

Minimum assertion time for SRESET

100

3

—

μs

Sysclk

μs

—

1

PLL input setup time with stable SYSCLK before HRESET negation

100

4

—

1

Input setup time for POR configurations (other than PLL config) with respect to negation of

HRESET

SYSCLKs

Input hold time for all POR configurations (including PLL config) with respect to negation of

HRESET

2

—

5

SYSCLKs

SYSCLK

1

Maximum valid-to-high impedance time for actively driven POR configurations with respect to

negation of HRESET

—

HRESET rise time

1

—

Notes:

1. SYSCLK is the primary clock input for the chip.

This table provides the PLL lock times.

Table 11. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

Local bus PLL

—

100

50

μs

—

PCI bus lock time

50

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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31

Electrical Characteristics

2.6

DDR2 and DDR3 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip. Note that DDR2

SDRAM is GV (type) = 1.8 V and DDR3 SDRAM is GV (type) = 1.5 V.

DD

2.6.1

DDR2 and DDR3 SDRAM DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR SDRAM component(s) of the chip when interfacing to

DDR2 SDRAM.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Notes

GV_DD

MV_REF

V_TT

1.7

0.49 × GV_DD

MV_REF– 0.04

MV_REF+ 0.125

–0.3

1.9

0.51 × GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.125

50

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.420 V)

Output low current (V_OUT= 0.280 V)

Notes:

I_OZ

–50

μA

mA

I_OH

–13.4

—

I_OL

13.4

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver.

Peak-to-peak noise on MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the chip. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

.

This table provides the recommended operating conditions for the DDR SDRAM controller of the chip when interfacing to

DDR3 SDRAM.

Table 13. DDR3 SDRAM Interface DC Electrical Characteristics for GV (typ) = 1.5 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Notes

GV_DD

MV_REFn

V_IH

1.425

0.49 × GV_DD

MV_REFn + 0.100

GND

1.575

0.51 × GV_DD

GV_DD

V

1

2

I/O reference voltage

Input high voltage

Input low voltage

Output leakage current

Notes:

V

—

3

V_IL

MV_REFn – 0.100

50

V

I_OZ

–50

μA

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFn is expected to be equal to 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver.

Peak-to-peak noise on MV_REFn may not exceed 1% of the DC value.

3. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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32

Electrical Characteristics

This table provides the DDR capacitance when GV (type) = 1.8 V.

DD

Table 14. DDR2 SDRAM Capacitance for GV (typ)=1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1, 2

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V 0.090 V (for DDR2), f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT

(peak-to-peak) = 0.2 V.

2. This parameter is sampled. GVDD = 1.5 V 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT

(peak-to-peak) = 0.175 V.

This table provides the current draw characteristics for MV

.

REF

Table 15. Current Draw Characteristics for MV

REF

Parameter/Condition

Current draw for MV_REFn

Symbol

Min

Max

Unit

Note

DDR2 SDRAM

DDR3 SDRAM

I_MVREFn

—

1500

1250

μA

1

1.The voltage regulator for MV_REFmust be able to supply up to 1500 μA or 1250 uA current for DDR2 or DDR3 respectively.

2.6.2

DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The DDR controller supports

both DDR2 and DDR3 memories. Please note that although the minimum data rate for most off-the-shelf DDR3 DIMMs

available is 800 MHz, JEDEC specification does allow the DDR3 to run at the data rate as low as 606 MHz. Unless otherwise

specified, the AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and

667 MHz, as long as the DC and AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications

as well as the specifications and requirements described in this document.

2.6.2.1

DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications

These tables provide the input AC timing specifications for the DDR controller.

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GVDD of 1.8 V 5%

Parameter

AC input low voltage

Symbol

Min

Max

Unit

667

V_ILAC

—

MV_REF– 0.20

V

<=533

667

—

MV_REF– 0.25

AC input high voltage

V_IHAC

MV_REF+ 0.20

MV_REF+ 0.25

—

<=533

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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33

Electrical Characteristics

Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface

At recommended operating conditions with GVDD of 1.5 V 5%. DDR3 data rate is between 606MHz and 667MHz.

Parameter

AC input low voltage

AC input high voltage

Symbol

Min

Max

Unit

Notes

V_IL

V_IH

—

MV_REF– 0.175

—

V

—

MV_REF+ 0.175

Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

t_CISKEW

—

ps

1, 2

667 MHz

533 MHz

400 MHz

—

–240

–300

–365

240

300

365

—

3

—

Note:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will

be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW.This can be determined

by the following equation: t_DISKEW=+/-(T/4 - abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the absolute value

of t_CISKEW

.

3. Maximum DDR2 and DDR3 frequency is 667MHz.

This figure shows the DDR2 and DDR3 SDRAM interface input timing diagram.

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

D0

D1

t_DISKEW

Figure 8. DDR SDRAM Input Timing Diagram

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Electrical Characteristics

2.6.2.2

DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications

This table contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.

Table 19. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.

Parameter

Symbol ¹

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

t_MCK

3.0

5

ns

2

3

7

ADDR/CMD output setup with respect to MCK t_DDKHAS

667 MHz

533 MHz

400 MHz

1.10

1.48

1.95

—

ADDR/CMD output hold with respect to MCK

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3

7

667 MHz

1.10

1.48

1.95

—

533 MHz

400 MHz

MCS[n] output setup with respect to MCK

3

7

667 MHz

1.10

1.48

1.95

—

533 MHz

400 MHz

MCS[n] output hold with respect to MCK

3

7

667 MHz

1.10

1.48

1.95

—

533 MHz

400 MHz

MCK to MDQS Skew

ns

ps

4

7

5

<= 667 MHz

–0.6

0.6

MDQ/MECC/MDM output setup with respect to t_DDKHDS,

MDQS t_DDKLDS

667 MHz

533 MHz

400 MHz

450

538

700

—

7

MDQ/MECC/MDM output hold with respect to t_DDKHDX,

ps

ns

5

7

MDQS

t_DDKLDX

667 MHz

533 MHz

400 MHz

450

538

700

—

MDQS preamble start

t_DDKHMP

6

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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35

Electrical Characteristics

Table 19. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.

Parameter

Symbol ¹

Min

Max

Unit

Notes

<= 667 MHz

0.9 × t_MCK

7

6

7

MDQS epilogue end

t_DDKHME

ns

0.4 × t_MCK

0.6 × t_MCK

Note:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t

_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for a description and

understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t_DDKHMPfollows the

symbol conventions described in note 1.

7. Maximum DDR2 and DDR3 frequency is 667 MHz

NOTE

For the ADDR/CMD setup and hold specifications in Table 19, it is assumed that the Clock

Control register is set to adjust the memory clocks by 1/2 applied cycle.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Freescale Semiconductor

Electrical Characteristics

).

This figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t

DDKHMH

MCK[n]

t_MCK

t_{DDKHMHmax) = 0.6 ns}

MDQS

t_{DDKHMH(min) = –0.6 ns}

MDQS

Figure 9. Timing Diagram for tDDKHMH

This figure shows the DDR SDRAM output timing diagram.

MCK[n]

t_MCK

t_DDKHAS,t_DDKHCS

t_DDKHAX,t_DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 10. DDR SDRAM Output Timing Diagram

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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37

Electrical Characteristics

This figure provides the AC test load for the DDR bus.

GV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 11. DDR AC Test Load

2.7

eSPI

This section describes the DC and AC electrical specifications for the eSPI of the chip.

2.7.1

eSPI DC Electrical Characteristics

This table provides the DC electrical characteristics for the chip eSPI.

Table 20. SPI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

0 V ≤ V_IN≤ OV_DD

10

μA

2.7.2

eSPI AC Timing Specifications

This table and provide the eSPI input and output AC timing specifications.

1

Table 21. SPI AC Timing Specifications

Characteristic

Symbol ²

Min

Max

Unit

Note

SPI_MOSI output—Master data hold time

t_NIKHOX

t_NIKHOV

t_NIKHOX2

0.5

4.0

3

4

—

ns

SPI_MOSI output—Master data delay

SPI_CS outputs—Master data hold time

6.0

7.4

—

3

—

0

ns

4

—

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Electrical Characteristics

1

Table 21. SPI AC Timing Specifications (continued)

Characteristic

Symbol ²

Min

Max

Unit

Note

SPI_CS outputs—Master data delay

SPI inputs—Master data input setup time

SPI inputs—Master data input hold time

Notes:

t_NIKHOV2

t_NIIVKH

t_NIIXKH

—

5

6.0

—

ns

—

0

—

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example,

t_NIKHOVsymbolizes the NMSI outputs internal timing (NI) for the time t_SPImemory clock reference (K) goes from

the high state (H) until outputs (O) are valid (V).

3. SPCOM[RxDelay] is set to 0.

4. SPCOM[RxDelay] is set to 1.

This figure provides the AC test load for the SPI.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 12. SPI AC Test Load

This figure represents the AC timing from Table 21. Note that although the specifications generally reference the rising edge of

the clock, these AC timing diagrams also apply when the falling edge is the active edge.

SPICLK (output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO

(See Note)

t_NIKHOX

t_NIKHOV

Output Signals:

SPIMOSI

(See Note)

t_NIKHOV2

t_NIKHOX2

Output Signals:

SPI_CS[0:3]

(See Note)

Note: The clock edge is selectable on SPI.

Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Electrical Characteristics

2.8

DUART

This section describes the DC and AC electrical specifications for the DUART interface of the chip.

2.8.1

DUART DC Electrical Characteristics

This table provides the DC electrical characteristics for the DUART interface.

Table 22. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

– 0.3

—

0.8

5

Input current

μA

(V_IN¹= 0 V or V_IN= V_DD)

High-level output voltage

(OV_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.4

—

V

Low-level output voltage

(OV_DD= min, I_OL= 2 mA)

0.4

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

2.8.2

DUART AC Electrical Specifications

This table provides the AC timing parameters for the DUART interface.

Table 23. DUART AC Timing Specifications

Parameter

Minimum baud rate

Value

Unit

Notes

CCB clock/1,048,576

CCB clock/16

16

baud

—

2

2,3

4

Maximum baud rate

Oversample rate

Notes:

2. CCB clock refers to the platform clock.

3. Actual attainable baud rate will be limited by the latency of interrupt processing.

4. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit.

Subsequent bit values are sampled each 16^thsample.

2.9

Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management

This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management.

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Freescale Semiconductor

Electrical Characteristics

2.9.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps) — FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical

Characteristics

The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface (GMII), media

independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit

interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and

management data clock (MDC), and serial gigabit media independent interface (SGMII). The RGMII, RTBI and FIFO mode

interfaces are defined for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can operate at 3.3V.

The GMII, MII, or TBI interface timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced

Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII

Consortium RMII Specification Version 1.2 (3/20/1998).

The electrical characteristics for MDIO and MDC are specified in Section 2.10, “Ethernet Management Interface Electrical

Characteristics.”

The electrical characteristics for SGMII is specified in Section 2.9.3, “SGMII Interface Electrical Characteristics.” The SGMII

interface conforms (with exceptions) to the Serial-GMII Specification Version 1.8.

2.9.1.1

GMII, MII, TBI, RGMII, RMII and RTBI DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in the

following tables. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC

EIA/JESD8-5.

Table 24. GMII, MII, RMII, and TBI DC Electrical Characteristics

Parameter

Supply voltage 3.3 V

Symbol

Min

Max

Unit

Notes

1, 2

LV_DD

TV_DD

3.13

3.47

V

Output high voltage

(LV_DD/TV_DD= Min, IOH = –4.0 mA)

VOH

2.40

LV_DD/TV_DD+ 0.3

0.50

V

—

Output low voltage

(LV_DD/TV_DD= Min, IOL = 4.0 mA)

VOL

GND

Input high voltage

Input low voltage

Input high current

V_IH

V_IL

I_IH

1.90

–0.3

—

LV_DD/TV_DD+ 0.3

V

0.90

40

—

1, 2,3

μA

(V_IN= LV_DD, V_IN= TV_DD

)

3

Input low current

(V_IN= GND)

I_IL

–600

—

μA

Notes:

1

LV_DDsupports eTSECs 1.

TV_DDsupports eTSECs 3.

2

3

The symbol V_IN, in this case, represents the LV_INand TV_INsymbols referenced in Table 1 and Table 2.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Electrical Characteristics

Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics

Parameters

Symbol

LV_DD/TV_DD

V_OH

Min

2.37

2.00

Max

2.63

Unit

V

Notes

1,2

Supply voltage 2.5 V

Output high voltage

(LV_DD/TV_DD= Min, IOH = –1.0 mA)

LV_DD/TV_DD+ 0.3

V

—

Output low voltage

(LV_DD/TV_DD= Min, I_OL= 1.0 mA)

V_OL

GND – 0.3

0.40

V

Input high voltage

Input low voltage

Input high current

V_IH

V_IL

I_IH

1.70

–0.3

—

LV_DD/TV_DD+ 0.3

V

0.70

10

—

1, 2,3

μA

(V_IN= LV_DD, V_IN= TV_DD

)

3

Input low current

(V_IN= GND)

I_IL

–15

—

μA

Note:

1

LV_DDsupports eTSECs 1.

TV_DDsupports eTSECs 3.

2

3

Note that the symbol V_IN, in this case, represents the LV_INand TV_INsymbols referenced in Table 1 and Table 2.

2.9.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.

2.9.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI specifications, since

they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO

interface provides deliberate skew between the transmitted data and source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface.

That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin

TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed

copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for

example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-

synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the

eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and

the platform speed. For more information see Section 2.4.6, “Platform to FIFO Restrictions.”

A summary of the FIFO AC specifications appears in the following tables.

Table 26. FIFO Mode Transmit AC Timing Specification

Parameter/Condition

TX_CLK, GTX_CLK clock period²

Symbol

Min

Typ

Max

Unit

t_FIT

t_FITH

t_FITJ

6.0

45

—

8.0

50

—

100

55

ns

%

TX_CLK, GTX_CLK duty cycle

TX_CLK, GTX_CLK peak-to-peak jitter

250

ps

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Electrical Characteristics

Table 26. FIFO Mode Transmit AC Timing Specification (continued)

Parameter/Condition

Rise time TX_CLK (20%–80%)

Fall time TX_CLK (80%–20%)

Symbol

Min

Typ

Max

Unit

t_FITR

—

0.75

3.0

ns

t_FITF

1

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time t_FITDX

0.5

Note:

1. Data valid tFITDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time

– Max Hold)

2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency

of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO

Restrictions,” for more detailed description.

Table 27. FIFO Mode Receive AC Timing Specification

Parameter/Condition

RX_CLK clock period¹

Symbol

Min

Typ

Max

Unit

t_FIR

6.0

45

—

8.0

50

—

100

55

ns

%

RX_CLK duty cycle

t_FIRH/t_FIRH

RX_CLK peak-to-peak jitter

Rise time RX_CLK (20%–80%)

Fall time RX_CLK (80%–20%)

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

Note:

t_FIRJ

t_FIRR

t_FIRF

250

0.75

—

ps

ns

—

t_FIRDV

t_FIRDX

1.5

0.5

—

1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency

of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO

Restrictions,” for more detailed description.

Timing diagrams for FIFO appear in the following figures.

t_FITF

t_FITR

t_FIT

GTX_CLK

t_FITH

t_FITDV

t_FITDX

TXD[7:0]

TX_EN

TX_ER

Figure 14. FIFO Transmit AC Timing Diagram

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Freescale Semiconductor

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Electrical Characteristics

t_FIRR

t_FIR

RX_CLK

t_FIRH

t_FIRF

RXD[7:0]

RX_DV

RX_ER

valid data

t_FIRDV

Figure 15. FIFO Receive AC Timing Diagram

t_FIRDX

2.9.2.2

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

2.9.2.2.1

GMII Transmit AC Timing Specifications

This table provides the GMII transmit AC timing specifications.

Table 28. GMII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

GTX_CLK clock period

t_GTK

—

0.5

—

8.0

—

ns

3

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK data clock rise time (20%-80%)

GTX_CLK data clock fall time (80%-20%)

Notes:

t_GTKHDX

5.0

1.0

t_GTXR

t_GTXF

—

1. The symbols used for timing specifications herein follow the pattern t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GTKHDVsymbolizes GMII

transmit timing (GT) with respect to the t_GTXclock reference (K) going to the high state (H) relative to the time date input

signals (D) reaching the valid state (V) to state or setup time. Also, t_GTKHDXsymbolizes GMII transmit timing (GT) with respect

to the t_GTXclock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of t_GTXrepresents the GMII(G) transmit (TX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Data valid tGTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time -

Max Hold)

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Freescale Semiconductor

Electrical Characteristics

This figure shows the GMII transmit AC timing diagram.

t_GTXR

t_GTX

GTX_CLK

t_GTXF

t_GTXH

TXD[7:0]

TX_EN

TX_ER

t_GTKHDX

t_GTKHDV

Figure 16. GMII Transmit AC Timing Diagram

2.9.2.2.2

GMII Receive AC Timing Specifications

This table provides the GMII receive AC timing specifications.

Table 29. GMII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

RX_CLK clock period

t_GRX

—

35

2.0

0

8.0

—

65

—

ns

%

RX_CLK duty cycle

t_GRXH/t_GRX

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20%-80%)

RX_CLK clock fall time (80%-20%)

Note:

t_GRDVKH

t_GRDXKH

t_GRXR

ns

—

1.0

t_GRXF

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GRDVKHsymbolizes GMII

receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_RXclock

reference (K) going to the high state (H) or setup time. Also, t_GRDXKLsymbolizes GMII receive timing (GR) with respect to the

time data input signals (D) went invalid (X) relative to the t_GRXclock reference (K) going to the low (L) state or hold time. Note

that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of t_GRXrepresents the GMII (G) receive (RX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

This figure provides the AC test load for eTSEC.

LV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 17. eTSEC AC Test Load

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

45

Electrical Characteristics

This figure shows the GMII receive AC timing diagram.

t_GRXR

t_GRX

RX_CLK

t_GRXF

t_GRXH

RXD[7:0]

RX_DV

RX_ER

t_GRDXKH

t_GRDVKH

Figure 18. GMII Receive AC Timing Diagram

2.9.2.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

2.9.2.3.1

MII Transmit AC Timing Specifications

This table provides the MII transmit AC timing specifications.

Table 30. MII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t_MTX

t_{MTXH/ MTX}

t_MTKHDX

t_MTXR

—

400

40

—

5

—

ns

%

t

35

1

65

15

4.0

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise (20%-80%)

TX_CLK data clock fall (80%-20%)

Note:

ns

1.0

—

t_MTXF

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII

transmit timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Freescale Semiconductor

Electrical Characteristics

This figure shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 19. MII Transmit AC Timing Diagram

2.9.2.3.2

MII Receive AC Timing Specifications

This table provides the MII receive AC timing specifications.

Table 31. MII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t_MRX

—

400

40

—

ns

%

t

_MRXH/t_MRX

t_MRDVKH

t_MRDXKH

t_MRXR

35

65

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20%–80%)

RX_CLK clock fall time (80%–20%)

Note:

10.0

1.0

—

ns

—

4.0

t_MRXF

—

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference (K) going

to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in general, the

clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,

the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

This figure provides the AC test load for eTSEC.

Output

LV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 20. eTSEC AC Test Load

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

47

Electrical Characteristics

This figure shows the MII receive AC timing diagram.

t_MRXR

t_MRX

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKL

Figure 21. MII Receive AC Timing Diagram

2.9.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

2.9.2.4.1

TBI Transmit AC Timing Specifications

This table provides the TBI transmit AC timing specifications.

Table 32. TBI Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

GTX_CLK clock period

GTX_CLK duty cycle

t_TTX

—

40

1.0

—

8.0

—

60

ns

%

t_{TTXH TTX}

/t

2

GTX_CLK to TCG[9:0] delay time

GTX_CLK rise (20%–80%)

GTX_CLK fall time (80%–20%)

Notes:

t_TTKHDX

t_TTXR

5.0

1.0

ns

t_TTXF

—

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state )(reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TTKHDVsymbolizes the TBI

transmit timing (TT) with respect to the time from t_TTX(K) going high (H) until the referenced data signals (D) reach the valid

state (V) or setup time. Also, t_TTKHDXsymbolizes the TBI transmit timing (TT) with respect to the time from t_TTX(K) going high

(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol

representation is based on three letters representing the clock of a particular functional. For example, the subscript of t_TTX

represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R

(rise) or F (fall).

2. Data valid tTTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max

Hold)

This figure shows the TBI transmit AC timing diagram.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Freescale Semiconductor

Electrical Characteristics

t_TTXR

t_TTX

GTX_CLK

TCG[9:0]

t_TTXH

t_TTXF

t_TTKHDV

t_TTXR

t_TTKHDX

Figure 22. TBI Transmit AC Timing Diagram

2.9.2.4.2

TBI Receive AC Timing Specifications

This table provides the TBI receive AC timing specifications.

Table 33. TBI Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition²

Symbol ¹

Min

Typ

Max

Unit

Clock period for TBI Receive Clock 0, 1

Skew for TBI Receive Clock 0, 1

t_TRX

—

16.0

—

8.5

60

—

ns

%

t_SKTRX

7.5

40

Duty cycle for TBI Receive Clock 0, 1

t

_TRXH/t_TRX

t_TRDVKH

t_TRDXKH

t_TRXR

—

RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1

RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1

Clock rise time (20%-80%) for TBI Receive Clock 0, 1

Clock fall time (80%-20%) for TBI Receive Clock 0, 1

Note:

2.5

1.5

0.7

—

ns

—

2.4

t_TRXF

—

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TRDVKHsymbolizes TBI receive

timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_TRXclock reference (K) going

to the high (H) state or setup time. Also, t_TRDXKHsymbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the t_TRXclock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of

t_TRXrepresents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).

2. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively.

These two clock signals are also referred as PMA_RX_CLK[0:1].

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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49

Electrical Characteristics

This figure shows the TBI receive AC timing diagram.

t_TRXR

t_TRX

TBI Receive Clock 1

(TSECn_TX_CLK)

t_TRXH

t_TRXF

Valid Data

RCG[9:0]

Valid Data

t_TRDVKH

t_SKTRX

t_TRDXKH

TBI Receive Clock 0

(TSECn_RX_CLK)

t_TRDXKH

t_TRXH

t_TRDVKH

Figure 23. TBI Receive AC Timing Diagram

2.9.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.

In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this

mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all

TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in the following table.

Table 34. TBI single-clock Mode Receive AC Timing Specification

At recommended operating conditions with LV_DD/TV_DDof 3.3 V 5%

Parameter/Condition

RX_CLK clock period

Symbol

Min

Typ

Max

Unit

t_TRR

t_TRRH

t_TRRJ

7.5

40

—

8.0

50

—

8.5

60

ns

%

RX_CLK duty cycle

RX_CLK peak-to-peak jitter

250

1.0

—

ps

ns

Rise time RX_CLK (20%–80%)

Fall time RX_CLK (80%–20%)

RCG[9:0] setup time to RX_CLK rising edge

RCG[9:0] hold time to RX_CLK rising edge

t_TRRR

t_TRRF

t_TRRDV

t_TRRDX

—

2.0

1.0

—

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50

Electrical Characteristics

A timing diagram for TBI receive appears in the following figure.

.

t_TRRR

t_TRR

RX_CLK

t_TRRH

t_TRRF

RCG[9:0]

valid data

t_TRRDV

t_TRRDX

Figure 24. TBI Single-Clock Mode Receive AC Timing Diagram

2.9.2.6

RGMII and RTBI AC Timing Specifications

This table presents the RGMII and RTBI AC timing specifications.

Table 35. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with L/TV_DDof 2.5 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver) ²

Clock period duration ³

t_{SKRGT_TX}

t_{SKRGT_RX}

t_RGT

–500

1.0

7.2

45

0

—

8.0

—

50

—

500

2.8

8.8

55

ps

ns

%

Duty cycle for 1000BASE-T⁴

Duty cycle for 10BASE-T and 100BASE-TX ^{3, 4}

Rise time (20%–80%)

t_{RGTH RGT}

t_RGTH/t_RGT

t_RGTR

t_RGTF

/t

40

60

%

—

0.75

ns

Fall time (20%–80%)

—

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to

represent RGMII and RTBI timing. For example, the subscript of t_RGTrepresents the TBI (T) receive (RX) clock. Note

also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than

1.5 ns will be added to the associated clock signal.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed

transitioned between.

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Electrical Characteristics

This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.

t_RGT

t_RGTH

GTX_CLK

(At Transmitter)

t_{SKRGT_TX}

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t_{SKRGT_RX}

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t_{SKRGT_TX}

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t_{SKRGT_RX}

RX_CLK

(At PHY)

Figure 25. RGMII and RTBI AC Timing and Multiplexing Diagrams

2.9.2.7

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

2.9.2.7.1

RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in the following table.

Table 36. RMII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

TSECn_TX_CLK clock period

TSECn_TX_CLK duty cycle

t_RMT

t_RMTH

t_RMTJ

15.0

35

20.0

50

25.0

65

ns

%

TSECn_TX_CLK peak-to-peak jitter

—

250

ps

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Electrical Characteristics

Table 36. RMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

Rise time TSECn_TX_CLK (20%–80%)

Fall time TSECn_TX_CLK (80%–20%)

TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay

Note:

t_RMTR

t_RMTF

1.0

2.0

—

2.0

ns

t_RMTDX

10.0

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDX

symbolizes MII transmit timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid

(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock

of a particular functional. For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure shows the RMII transmit AC timing diagram.

t_RMTR

t_RMT

TSECn_TX_CLK

t_RMTF

t_RMTH

TXD[1:0]

TX_EN

TX_ER

t_RMTDX

Figure 26. RMII Transmit AC Timing Diagram

2.9.2.7.2

RMII Receive AC Timing Specifications

Table 37. RMII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

TSECn_RX_CLK clock period

t_RMR

t_RMRH

t_RMRJ

t_RMRR

15.0

35

20.0

50

25.0

65

ns

%

TSECn_RX_CLK duty cycle

TSECn_RX_CLK peak-to-peak jitter

Rise time TSECn_RX_CLK (20%–80%)

—

250

2.0

ps

ns

1.0

—

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Electrical Characteristics

Table 37. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

Fall time TSECn_RX_CLK (80%–20%)

t_RMRF

t_RMRDV

t_RMRDX

1.0

4.0

2.0

—

2.0

—

ns

RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge

RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge

Note:

—

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference (K) going

to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For example, the

subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

This figure provides the AC test load for eTSEC.

Output

LV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 27. eTSEC AC Test Load

This figure shows the RMII receive AC timing diagram.

t_RMR

t_RMRR

TSECn_RX_CLK

t_RMRF

Valid Data

t_RMRH

RXD[1:0]

CRS_DV

RX_ER

t_RMRDV

t_RMRDX

Figure 28. RMII Receive AC Timing Diagram

2.9.3

SGMII Interface Electrical Characteristics

Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of the chip as shown in

Figure 29, where C is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential

TX

pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to

S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68.

When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be

left floating. The input signals should be terminated based on the guidelines described in Section 3.6, “Connection

Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if

applicable.

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Electrical Characteristics

When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference

clock is required on SD2_REF_CLK and SD2_REF_CLK pins.

2.9.3.1

DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK

The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20, “High-Speed

Serial Interfaces.”

2.9.3.2

AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK

This table lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are

not intended to be used with, and should not be clocked by, a spread spectrum clock source.

Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements

Symbol

Parameter Description

Min Typical Max Units Notes

t_REF

REFCLK cycle time

—

10 (8)

—

ns

ps

1

t_REFCJREFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent

REFCLK cycles

100

—

t_REFPJPhase jitter. Deviation in edge location with respect to mean edge location

–50

—

50

ps

2,3

Notes:

1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.

2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.

3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.

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Electrical Characteristics

2.9.3.3

SGMII Transmitter and Receiver DC Electrical Characteristics

The following tables describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics.

Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) as depicted in Figure 30.

Table 39. SGMII DC Transmitter Electrical Characteristics

Parameter

Supply Voltage

Symbol

Min

Typ

Max

Unit

Notes

X2V_DD

VOH

0.95

—

1.0

—

1.05

V

—

1

Output high voltage

Output low voltage

Output ringing

X2V_DD-Typ/2 +

mV

|V_{OD -max}/2

|

VOL

X2V_DD-Typ/2 -

—

mV

%

1

|V_{OD -max}/2

|

V_RING

—

10

—

323

500

725

Equalization

setting: 1.0x

296

269

243

215

189

162

459

417

376

333

292

250

665

604

545

483

424

362

Equalization

setting: 1.09x

Equalization

setting: 1.2x

Output differential voltage^{2, 3, 5}

Equalization

setting: 1.33x

|V_OD

|

mV

Equalization

setting: 1.5x

Equalization

setting: 1.71x

Equalization

setting: 2.0x

Output offset voltage

V_OS

R_O

425

40

—

500

—

575

60

10

25

40

mV

Ω

1, 4

—

Output impedance (single-ended)

Mismatch in a pair

Δ R_O

Δ |V_OD

Δ V_OS

—

%

—

Change in V_ODbetween “0” and “1”

Change in V_OSbetween “0” and “1”

Output current on short to GND

Notes:

|

—

mV

mA

—

I

_SA, I_SB

—

1. This will not align to DC-coupled SGMII. X2V_DD-Typ=1.0V.

2. |V_OD| = |V_{SD2_TXn}- V_{SD2_TXn}|. |V_OD| is also referred as output differential peak voltage. V_TX-DIFFp-p= 2*|V_{OD .}

|

3. The |V_OD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes

A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of the chip’s SerDes 2 control register:

• The MSbit (bit 0) of the above bit field is set to zero (selecting the full V_DD-DIFF-p-pamplitude - power up default);

• The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.

4. V_OSis also referred to as output common mode voltage.

• 5.The |V_OD| value shown in the Typ column is based on the condition of X2V_DD-Typ=1.0V, no common mode offset variation

(VOS =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n].

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Electrical Characteristics

SD2_TXn

SD_RXm

50 Ω

C_TX

50 Ω

Receiver

Transmitter

C_TX

SD2_TXn

SD2_RXn

SGMII

SerDes Interface

C_TX

SD_TXm

50 Ω

Receiver

Transmitter

50 Ω

C_TX

SD2_RXn

SD_TXm

Figure 29. 4-Wire AC-Coupled SGMII Serial Link Connection Example

SGMII

SerDes Interface

SD2_TXn

50 Ω

50

Ω

Transmitter

V_os

V_OD

50 Ω

Ω

SD2_TXn

Figure 30. SGMII Transmitter DC Measurement Circuit

Table 40. SGMII DC Receiver Electrical Characteristics

Parameter

Supply Voltage

Symbol

Min

Typ

Max

Unit

Notes

X2V_DD

—

0.95

1.0

N/A

—

1.05

V

—

1

DC Input voltage range

Input differential voltage

—

LSTS = 0

LSTS = 1

LSTS = 0

LSTS = 1

V_{RX_DIFFp-p}

100

175

30

1200

mV

2, 4

—

Loss of signal threshold

VLOS

—

100

175

100

mV

3, 4

5

65

—

Input AC common mode voltage

V_{CM_ACp-p}

—

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Electrical Characteristics

Table 40. SGMII DC Receiver Electrical Characteristics (continued)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Receiver differential input impedance

Z_{RX_DIFF}

Z_{RX_CM}

80

20

100

—

120

35

Ω

—

Receiver common mode input

impedance

Common mode input voltage

V_CM

—

V_xcorevss

—

V

6

Notes:

1. Input must be externally AC-coupled.

2. V_{RX_DIFFp-p}is also referred to as peak to peak input differential voltage

3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. See Table 72

for further explanation.

4. The LSTS shown in the table refers to the LSTSA or LSTSE bit field of chip’s SerDes 2 control register.

5. V_{CM_ACp-p}is also referred to as peak to peak AC common mode voltage.

6. On-chip termination to S2GND (xcorevss).

2.9.3.4

SGMII AC Timing Specifications

This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are

measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver inputs (SD2_RX[n] and SD2_RX[n]) as

depicted in Figure 32 respectively.

2.9.3.4.1

SGMII Transmit AC Timing Specifications

This table provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.

Table 41. SGMII Transmit AC Timing Specifications

At recommended operating conditions with X2V_DD= 1.0V 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic Jitter

Total Jitter

JD

JT

—

0.17

0.35

UI p-p

ps

—

1

Unit Interval

UI

799.92

50

800

—

800.08

120

V_ODfall time (80%-20%)

V_ODrise time (20%-80%)

tfall

t_rise

ps

—

50

—

120

ps

Notes:

1. Each UI is 800 ps 100 ppm.

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Electrical Characteristics

2.9.3.4.2

SGMII Receive AC Timing Specifications

This table provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is

recovered from the data. Figure 31 shows the SGMII Receiver Input Compliance Mask eye diagram.

Table 42. SGMII Receive AC Timing Specifications

At recommended operating conditions with X2V_DD= 1.0V 5%.

Parameter

Deterministic Jitter Tolerance

Symbol

Min

Typ

Max

Unit

Notes

JD

JDR

JSIN

JT

0.37

0.55

0.1

—

UI p-p

1

Combined Deterministic and Random Jitter Tolerance

Sinusoidal Jitter Tolerance

Total Jitter Tolerance

—

1

0.65

—

1

Bit Error Ratio

BER

UI

—

10^-12

800.08

200

—

2

Unit Interval

799.92

5

800

—

ps

AC Coupling Capacitor

C_TX

nF

3

Notes:

1. Measured at receiver.

2. Each UI is 800 ps 100 ppm.

3. The external AC coupling capacitor is required. It is recommended to be placed near the chip transmitter outputs.

V_{RX_DIFFp-p-max}/2

V_{RX_DIFFp-p-min}/2

0

/2

- V

RX_DIFFp-p-min

− V_{RX_DIFFp-p-max}/2

1

0

0.275

0.4

0.6

0.725

Time (UI)

Figure 31. SGMII Receiver Input Compliance Mask

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Electrical Characteristics

D+ Package

C = C_TX

TX

Silicon

+ Package

C = C_TX

R = 50 Ω

D– Package

R = 50 Ω

Figure 32. SGMII AC Test/Measurement Load

2.9.4

eTSEC IEEE 1588 AC Specifications

This figure shows the data and command output timing diagram.

t_T1588CLKOUT

t_T1588CLKOUTH

TSEC_1588_CLK_OUT

t_T1588OV

TSEC_1588_PULSE_OUT

TSEC_1588_TRIG_OUT

Figure 33. eTSEC IEEE 1588 Output AC timing

1

The output delay is count starting rising edge if t_T1588CLKOUTis non-inverting. Otherwise, it is count starting falling edge.

This figure provides the data and command input timing diagram.

t_T1588CLK

t_T1588CLKH

TSEC_1588_CLK

TSEC_1588_TRIG_IN

t_T1588TRIGH

Figure 34. eTSEC IEEE 1588 Input AC timing

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Electrical Characteristics

The IEEE 1588 AC timing specifications are in the following table.

Table 43. eTSEC IEEE 1588 AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

Parameter/Condition

TSEC_1588_CLK clock period

TSEC_1588_CLK duty cycle

Symbol

Min

Typ

Max

Unit

Note

t_T1588CLK

T_{TX_CLK}*7

3.8

—

ns

1

t_T1588CLKH

/t_T1588CLK

—

40

50

60

%

TSEC_1588_CLK peak-to-peak jitter

Rise time eTSEC_1588_CLK (20%–80%)

Fall time eTSEC_1588_CLK (80%–20%)

TSEC_1588_CLK_OUT clock period

TSEC_1588_CLK_OUT duty cycle

t_T1588CLKINJ

t_T1588CLKINR

t_T1588CLKINF

t_T1588CLKOUT

—

1.0

—

250

2.0

—

ps

ns

1.0

2*t_T1588CLK

t_T1588CLKOTH

/t_T1588CLKOUT

30

50

70

%

TSEC_1588_PULSE_OUT

TSEC_1588_TRIG_IN pulse width

Note:

t_T1588OV

0.5

—

3.0

—

ns

—

2

t_T1588TRIGH

2*t_{T1588CLK_MAX}

1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source,

with the timing defined in the Table above. The maximum value of t_T1588CLKis defined in terms of T_{TX_CLK}, which is the

maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running.

When eTSEC1 is configured to operate in the parallel mode, the T_{TX_CLK}is the maximum clock period of the

TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of t_T1588CLKis defined in terms of the

recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of t_T1588CLKwill be

2800, 280, and 56 ns respectively.

See the MPC8536E PowerQUICC III Integrated Communications Processor Reference Manual for a description of

TMR_CTRL registers.

2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8536E PowerQUICC

III Integrated Processor Reference Manual for a description of TMR_CTRL registers.

2.10 Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data

input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and

RTBI are specified in Section 2.9, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management”

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Electrical Characteristics

2.10.1 MII Management DC Electrical Characteristics

The EC_MDC and EC_MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for

EC_MDIO and EC_MDC are provided in the following table.

Table 44. MII Management DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Supply voltage (3.3 V)

OV_DD

V_OH

3.13

2.40

3.47

V

Output high voltage

OV_DD+ 0.3

(OV_DD= Min, I_OH= –4.0 mA)

Output low voltage

V_OL

GND

0.40

V

(OV_DD=Min, I_OL= 4.0 mA)

Input high voltage

Input low voltage

V_IH

V_IL

I_IH

2.0

—

0.90

40

V

Input high current

—

μA

(OV_DD= Max, V_IN¹= 2.1 V)

Input low current

I_IL

–600

—

μA

(OV_DD= Max, V_IN= 0.5 V)

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

2.10.2 MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

Table 45. MII Management AC Timing Specifications

At recommended operating conditions with OVDD is 3.3 V 5%.

Parameter/Condition

EC_MDC frequency

Symbol ¹

Min

Typ

Max

Unit

Notes

f_MDC

t_MDC

0.74

2.5

400

—

8.3

MHz

ns

2

—

EC_MDC period

120

1350

EC_MDC clock pulse width high

EC_MDC to EC_MDIO delay

EC_MDIO to EC_MDC setup time

t_MDCH

32

—

(16 * t_{plb_clk})+3

—

ns

—

t_MDKHDX

t_MDDVKH

(16 * t_{plb_clk})-3

5

—

ns

3,5,6

—

ns

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Electrical Characteristics

Table 45. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OVDD is 3.3 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

Notes

EC_MDIO to EC_MDC hold time

EC_MDC rise time

EC_MDC fall time

Notes:

t_MDDXKH

t_MDCR

0

—

10

ns

—

t_MDHF

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDX

symbolizes management data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise

and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f_CCB). The actual

EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of chip’s

MIIMCFG register, based on the platform (CCB) clock running for the chip. The formula is: Platform Frequency

(CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if MIICFG[MgmtClk] = 000

and the platform (CCB) is currently running at 533 MHz, f_MDC= 533/(2*4*8) = 533/64 = 8.3 MHz. That is, for a system

running at a particular platform frequency (f_CCB), the EC_MDC output clock frequency can be programmed between

maximum f_MDC= f_CCB/64 and minimum f_MDC= f_CCB/448. See the MPC8536E reference manual’s MIIMCFG register section

for more detail.

3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods +/-3ns. For

example, with a platform clock of 333MHz, the min/max delay is 48ns +/-3ns. Similarly, if the platform clock is 400MHz, the

min/max delay is 40ns +/-3ns).

5. t_{CLKplb_clk}is the platform (CCB) clock

6. EC_MDC to EC_MDIO Data valid t_MDKHDVis a function of clock period and max delay time t_MDKHDX. (Min Setup = Cycle

time - Max Hold)

This figure shows the MII management AC timing diagram.

t_MDC

t_MDCR

EC_MDC

t_MDCF

t_MDCH

EC_MDIO

(Input)

t_MDDVKH

t_MDDXKH

EC_MDIO

(Output)

t_MDKHDX

Figure 35. MII Management Interface Timing Diagram

2.11 USB

This section provides the AC and DC electrical specifications for the USB interface of the chip.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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Electrical Characteristics

2.11.1 USB DC Electrical Characteristics

This table provides the DC electrical characteristics for the USB interface.

Table 46. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

0.8

5

I_IN

—

μA

V

High-level output voltage,

V_OH

OV_DD– 0.2

—

I_OH= –100 μA

Low-level output voltage,

V_OL

—

0.2

V

I_OL= 100 μA

Note:

1. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

2.11.2 USB AC Electrical Specifications

This table describes the general timing parameters of the USB interface of the chip.

6

Table 47. USB General Timing Parameters

Parameter

usb clock cycle time

Symbol ¹

Min

Max

Unit

Notes

t_USCK

t_USIVKH

t_USIXKH

t_USKHOV

t_USKHOX

15

4

—

7

ns

2-5

Input setup to usb clock - all inputs

input hold to usb clock - all inputs

usb clock to output valid - all outputs

Output hold from usb clock - all outputs

Notes:

1

—

2

—

1. The symbols for timing specifications follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}for inputs

and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_USIXKHsymbolizes usb timing (US) for

the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, t_USKHOXsymbolizes USB

timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to USB clock.

3. All signals are measured from OV_DD/2 of the rising edge of the USB clock to 0.4 × OV_DDof the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the

component pin is less than or equal to that of the leakage current specification.

6. When switching the data pins from outputs to inputs using the USBn_DIR pin, the output timings will be violated on that cycle

because the output buffers are tristated asynchronously. This should not be a problem, because the PHY should not be

functionally looking at these signals on that cycle as per ULPI specifications

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Electrical Characteristics

This figures provide the AC test load and signals for the USB, respectively.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 36. USB AC Test Load

USB0_CLK/USB1_CLK/DR_CLK

Input Signals

t_USIXKH

t_USIVKH

t_USKHOX

t_USKHOV

Output Signals:

Figure 37. USB Signals

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Electrical Characteristics

2.12 Enhanced Local Bus Controller (eLBC)

This section describes the DC and AC electrical specifications for the local bus interface of the chip.

2.12.1 Local Bus DC Electrical Characteristics

This table provides the DC electrical characteristics for the local bus interface operating at BV = 3.3 V DC.

DD

Table 48. Local Bus DC Electrical Characteristics (3.3 V DC)

Parameter

Symbol

Min

Max

Unit

Supply voltage 3.3V

BV_DD

V_IH

V_IL

3.13

1.9

3.47

V

High-level input voltage

Low-level input voltage

BV_DD+ 0.3

–0.3

—

0.8

5

V

Input current

I_IN

μA

(BV_IN¹= 0 V or BV_IN= BV_DD

)

High-level output voltage

(BV_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.4

—

V

Low-level output voltage

(BV_DD= min, I_OL= 2 mA)

0.4

Note:

1. The symbol BV_IN, in this case, represents the BV_INsymbol referenced in Table 1.

This table provides the DC electrical characteristics for the local bus interface operating at BV = 2.5 V DC.

DD

Table 49. Local Bus DC Electrical Characteristics (2.5 V DC)

Parameter

Supply voltage 2.5V

Symbol

Min

Max

Unit

BV_DD

V_IH

V_IL

2.37

1.70

–0.3

—

2.63

BV_DD+ 0.3

0.7

V

High-level input voltage

Low-level input voltage

V

Input current

I_IH

10

μA

(BV_IN¹= 0 V or BV_IN= BV_DD

)

I_IL

–15

High-level output voltage

(BV_DD= min, I_OH= –1 mA)

V_OH

2.0

BV_DD+ 0.3

V

Low-level output voltage

(BV_DD= min, I_OL= 1 mA)

V_OL

GND – 0.3

0.4

Note:

1. Note that the symbol BV_IN, in this case, represents the BV_INsymbol referenced in Table 1.

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Electrical Characteristics

This table provides the DC electrical characteristics for the local bus interface operating at BV = 1.8 V DC.

DD

Table 50. Local Bus DC Electrical Characteristics (1.8 V DC)

Parameter

Supply voltage 1.8V

Symbol

Condition

Min

Max

Unit

BV_DD

V_IH

V_IL

—

1.71

0.65*BV_DD

–0.3

1.89

0.3+BV_DD

0.35*BV_DD

10

V

High-level input voltage

Low-level input voltage

V

Input current

I_IN

-15

μA

(BV_IN¹= 0 V or BV_IN= BV_DD

)

High-level output voltage

Low-level output voltage

Note:

V_OH

I_OH= –100 μA

BV_DD– 0.2

—

V

I

_OH= –2 mA

BV_DD– 0.45

V_OL

I_OH= 100 μA

—

0.2

0.45

I_OH= 2 mA

1. Note that the symbol BV_IN, in this case, represents the BV_INsymbol referenced in Table 1.

2.12.2 Local Bus AC Electrical Specifications

This table describes the general timing parameters of the local bus interface at BV = 3.3 V DC. For information about the

DD

frequency range of local bus see Section 2.23.1, “Clock Ranges.”

Table 51. Local Bus General Timing Parameters (BV = 3.3 V DC)

DD

Parameter

Symbol ¹

Min

Max

Unit Notes

Local bus cycle time

Local bus duty cycle

t_LBK

7.5

43

12

57

ns

%

2

—

7

t_{LBKH/ LBK}

t

tLBKSKEW

150

ps

LCLK[n] skew to LCLK[m] or LSYNC_OUT

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

t_LBIVKH1

t_LBIVKH2

t_LBIXKH1

t_LBIXKH2

t_LBOTOT

1.8

1.7

1.0

1.5

—

ns

3, 4

6

Input hold from local bus clock (except LUPWAIT)

LUPWAIT input hold from local bus clock

—

LALE output transition to LAD/LDP output transition (LATCH setup and hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

—

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

t_LBKHOV4

t_LBKHOX1

2.3

2.4

2.3

—

3

—

Local bus clock to address valid for LAD

—

3

Local bus clock to LALE assertion

—

3

Output hold from local bus clock (except LAD/LDP and LALE)

0.7

3

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Electrical Characteristics

Table 51. Local Bus General Timing Parameters (BV = 3.3 V DC) (continued)

DD

Parameter

Symbol ¹

Min

Max

Unit Notes

Output hold from local bus clock for LAD/LDP

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

Note:

t_LBKHOX2

t_LBKHOZ1

t_LBKHOZ2

0.7

—

ns

3

5

2.5

—

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for

clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV_DD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 × BV_DDof the signal in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

6.t_LBOTOTis a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed

with LBCR[AHD] = 0.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

This table describes the general timing parameters of the local bus interface at BV = 2.5 V DC.

DD

Table 52. Local Bus General Timing Parameters (BV = 2.5 V DC)

DD

Parameter

Configuration Symbol ¹

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

—

t_LBK

7.5

43

—

12

57

ns

%

2

—

7

t

_LBKH/t_LBK

tLBKSKEW

150

ps

LCLK[n] skew to LCLK[m] or LSYNC_OUT

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

—

t_LBIVKH1

t_LBIVKH2

t_LBIXKH1

t_LBIXKH2

t_LBOTOT

1.9

1.8

1.1

1.5

—

ns

3, 4

6

Input hold from local bus clock (except LUPWAIT)

LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH

setup and hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

—

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

t_LBKHOV4

t_LBKHOX1

—

2.4

2.5

2.4

—

ns

—

3

Local bus clock to address valid for LAD

—

3

Local bus clock to LALE assertion

—

3

Output hold from local bus clock (except LAD/LDP and LALE)

0.8

3

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Electrical Characteristics

Table 52. Local Bus General Timing Parameters (BV = 2.5 V DC) (continued)

DD

Parameter

Configuration Symbol ¹

Min

Max

Unit

Notes

Output hold from local bus clock for LAD/LDP

—

t_LBKHOX2

t_LBKHOZ1

0.8

—

ns

3

5

Local bus clock to output high Impedance (except LAD/LDP

and LALE)

2.6

Local bus clock to output high impedance for LAD/LDP

—

t_LBKHOZ2

—

2.6

ns

5

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for

clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV_DD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 × BV_DDof the signal in question for 2.5-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

6. t_LBOTOTis a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed

with LBCR[AHD] = 0.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

This table describes the general timing parameters of the local bus interface at BV = 1.8 V DC.

DD

Table 53. Local Bus General Timing Parameters (BV = 1.8 V DC)

DD

Parameter

Configuration Symbol ¹

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

—

t_LBK

7.5

43

12

57

ns

%

2

t

_LBKH/t_LBK

tLBKSKEW

150

ps

7

LCLK[n] skew to LCLK[m] or LSYNC_OUT

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

—

t_LBIVKH1

t_LBIVKH2

t_LBIXKH1

t_LBIXKH2

t_LBOTOT

2.4

1.9

1.1

1.2

—

ns

3, 4

6

Input hold from local bus clock (except LUPWAIT)

LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH

setup and hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

—

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

t_LBKHOV4

t_LBKHOX1

—

3.2

—

ns

—

3

Local bus clock to address valid for LAD

—

3

Local bus clock to LALE assertion

—

3

Output hold from local bus clock (except LAD/LDP and LALE)

0.9

3

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Electrical Characteristics

Table 53. Local Bus General Timing Parameters (BV = 1.8 V DC) (continued)

DD

Parameter

Configuration Symbol ¹

Min

Max

Unit

Notes

Output hold from local bus clock for LAD/LDP

—

t_LBKHOX2

t_LBKHOZ1

0.9

—

ns

3

5

Local bus clock to output high Impedance (except LAD/LDP

and LALE)

2.6

Local bus clock to output high impedance for LAD/LDP

—

t_LBKHOZ2

—

2.6

ns

5

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for

clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV_DD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4 × BV_DDof the signal in question for 1.8-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

6. t_LBOTOTis a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed

with LBCR[AHD] = 0.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

This figure provides the AC test load for the local bus.

Figure 38. Local Bus AC Test Load

Output

BV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

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70

Electrical Characteristics

This figures show the local bus signals.

LSYNC_IN

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH2

t_LBIVKH2

Input Signal:

LGTA

UPM Mode Input Signal:

LUPWAIT

t_LBKHOZ1

t_LBKHOX1

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

Output Signals:

LA[27:31]/LBCTL/LOE

t_LBKHOZ2

t_LBKHOX2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ2

t_LBKHOX2

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

t_LBKHOV4

LALE

Figure 39. Local Bus Signals, Non-Special Signals Only (PLL Enabled)

NOTE

In PLL bypass mode, some signals are launched and captured on the opposite edge of

LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the

falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n]

with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the

LCLK[n]).

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Electrical Characteristics

LCLK[n]

t_LBIVKH1

t_LBIXKH1

Input Signals:

LAD[0:31]/LDP[0:3]

Input Signal:

LGTA

t

LBIXKL2

t

LBIVKL2

UPM Mode Input Signal:

LUPWAIT

t_LBKLOV1

t_LBKLOZ1

t_LBKLOX1

Output Signals:

LA[27:31]/LBCTL/LOE

t_LBKLOZ2

t_LBKLOV2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKLOX2

t_LBKLOV3

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

t_LBKLOV4

LALE

Figure 40. Local Bus Signals (PLL Bypass Mode)

This table describes the general timing parameters of the local bus interface at V = 3.3 V DC with PLL disabled.

DD

Table 54. Local Bus General Timing Parameters—PLL Bypassed

Parameter

Symbol ¹

Min

Max

Unit Notes

Local bus cycle time

Local bus duty cycle

t_LBK

12

43

—

57

—

0.5

ns

%

2

t

_LBKH/t_LBK

t_LBIVKH1

t_LBIVKL2

t_LBIXKH1

t_LBIXKL2

t_LBOTOT

t_LBKLOV1

—

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

5.1

4.2

-1.4

-2.0

1.4

—

ns

4, 5

6

Input hold from local bus clock (except LUPWAIT)

LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

4

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Electrical Characteristics

Table 54. Local Bus General Timing Parameters—PLL Bypassed (continued)

Parameter

Local bus clock to data valid for LAD/LDP

Symbol ¹

Min

Max

Unit Notes

t_LBKLOV2

t_LBKLOV3

t_LBKLOV4

t_LBKLOX1

t_LBKLOX2

t_LBKLOZ1

t_LBKLOZ2

—

0.5

2.2

0.1

ns

4

Local bus clock to address valid for LAD, and LALE

Local bus clock to LALE assertion

4

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

Notes:

4,8

7

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for

clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the

output (O) going invalid (X) or output hold time.

2. All timings are in reference to local bus clock for PLL bypass mode.

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV_DD/2.

4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal

in question for 3.3-V signaling levels.

5. Input timings are measured at the pin.

6. t_LBOTOTis a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed

with LBCR[AHD] = 0.

7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

8. These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing

parameters.

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Electrical Characteristics

LSYNC_IN

T1

T3

t_LBKHOZ1

t_LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t_LBIXKH2

t_LBIVKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ1

t_LBKHOV1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled)

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Electrical Characteristics

LSYNC_IN

T1

T2

T3

T4

t

LBKHOZ1

t

LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal

LGTA

t

LBIXKH2

t

LBIVKH2

UPM Mode Input Signal:

LUPWAIT

t

LBIXKH1

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

(PLL Bypass Mode)

t

LBKHOZ1

t

LBKHOV1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 42. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 8 or 16(PLL Enabled)

2.13 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface of the chip.

2.13.1 eSDHC DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSDHC interface of the chip.

Table 55. eSDHC interface DC Electrical Characteristics

At recommended operating conditions (see Table 3)

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

Notes

V_IH

V_IL

—

0.625 * OVDD

–0.3

OVDD+0.3

V

—

Input low voltage

0.25 * OVDD

Input/Output leakage current

Output high voltage

I_IN/I_OZ

V_OH

–10

10

—

uA

V

I_OH= -100 uA @OVDDmin 0.75 * OVDD

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Electrical Characteristics

Table 55. eSDHC interface DC Electrical Characteristics (continued)

At recommended operating conditions (see Table 3)

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

Output low voltage

Output high voltage

Output low voltage

Notes:

V_OL

V_OH

V_OL

I_OL= 100uA @OVDDmin

I_OH= -100 uA

—

OV_DD- 0.2

—

0.125 * OVDD

V

—

2

—

I_OL= 2 mA

0.3

2

1. The min V_ILand V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. Open drain mode for MMC cards only.

2.13.2 eSDHC AC Timing Specifications

This table provides the eSDHC AC timing specifications as defined in the following figure.

Table 56. eSDHC AC Timing Specifications

At recommended operating conditions (see Table 3)

Parameter

SD_CLK clock frequency:

Symbol¹

Min

Max

Unit

Notes

f_SHSCK

MHz

2, 5

SD/SDIO Full speed/high speed mode

MMC Full speed/high speed mode

0

25/50

20/52

SD_CLK clock frequency - identification mode

f_SIDCK

0

400

KHz

3, 5

100

SD_CLK clock low time - High speed/Full speed mode

SD_CLK clock high time - High speed/Full speed mode

SD_CLK clock rise and fall times

t_SHSCKL

t_SHSCKH

t_SHSCKR/

7/10

—

3

ns

5

t_SHSCKF

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

t_SHSIVKH

2.5

—

ns

4,5,6

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

Notes:

t_SHSIXKH

t_SHSKHOV

2.5

–3

—

3

ns

5,6

1. The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_FHSKHOVsymbolizes eSDHC

high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching

the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation is based on five letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed

mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52MHz for a MMC card.

3. 0 Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required.

4. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should

not exceed 1 ns.

5. C_CARD≤10 pF, (1 card), and C_L= C_BUS+ C_HOST+C_CARD≤ 40 pF

6. The parameter values apply to both full speed and high speed modes.

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Electrical Characteristics

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock

VM

operational mode

t_SHSCKL

t_SHSCKH

t_SHSCK

t_SHSCKF

t_SHSCKR

VM = Midpoint Voltage (OV_DD/2)

Figure 43. eSDHC Clock Input Timing Diagram

This figure provides the data and command input/output timing diagram.

VM

SD_CK

External Clock

t_SHSIXKH

t_SHSIVKH

SD_DAT/CMD

Inputs

SD_DAT/CMD

Outputs

t_SHSKHOV

VM = Midpoint Voltage (OV_DD/2)

Figure 44. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock

2.14 Programmable Interrupt Controller (PIC)

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain

the assertion for at least 3 system clocks (SYSCLK periods).

2.15 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.

2.15.1 JTAG DC Electrical Characteristics

This table provides the DC electrical characteristics for the JTAG interface.

Table 57. JTAG DC Electrical Characteristics

Parameter

Symbol ¹

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

2

OV_DD+ 0.3

0.8

V

-0.3

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Electrical Characteristics

Table 57. JTAG DC Electrical Characteristics (continued)

Parameter

Symbol ¹

Min

Max

Unit

Input current

I_IN

—

5

μA

(V_IN¹= 0 V or V_IN= V_DD

)

High-level output voltage

(OV_DD= min, I_OH= -2 mA)

V_OH

V_OL

2.4

—

V

Low-level output voltage

(OV_DD= min, I_OL= 2 mA)

0.4

Notes:

1. Note that the symbol V_IN, in this case, represents the OV_IN.

2.15.2 JTAG AC Electrical Specifications

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.

This table provides the JTAG AC timing specifications as defined in the following figures.

Table 58. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions (see Table 3).

Parameter

Symbol ¹

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f_JTG

t _JTG

0

30

15

0

33.3

—

2

MHz

ns

—

2

t_JTKHKL

t_JTGR& t_JTGF

t_TRST

ns

25

4

—

10

—

ns

Input setup times:

t_JTDVKH

t_JTDXKH

t_JTKLDV

t_JTKLDX

ns

Input hold times:

10

—

0

ns

Output Valid times:

ns

3

Output hold times:

ns

Notes:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference

(K) going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input

signals (D) went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that, in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3.) The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays

must be added for trace lengths, vias, and connectors in the system.

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Electrical Characteristics

This figure provides the AC test load for TDO and the boundary-scan outputs.

Z₀= 50 Ω

OV_DD/2

Output

R_L= 50 Ω

Figure 45. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTGF

t_JTG

VM = Midpoint Voltage (OV /2)

DD

Figure 46. JTAG Clock Input Timing Diagram

This figure provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 47. TRST Timing Diagram

This figure provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 48. Boundary-Scan Timing Diagram

2.16 Serial ATA (SATA)

This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the chip. Note that the external

cabled applications or long backplane applications (Gen1x & Gen2x) are not supported.

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Electrical Characteristics

2.16.1 Requirements for SATA REF_CLK

The AC requirements for the SATA reference clock are listed in the following table.

Table 59. Reference Clock Input Requirements

Parameter

Symbol

Min

Typical

Max

Unit

Notes

SD2_REF_CLK/_B reference clock cycle time

SD2_REF_CLK/_B frequency tolerance

SD_REF_CLK/_B rise/fall time (80%-20%)

SD_REF_CLK/_B duty cycle (@50% X2VDD)

SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)

SD_REF_CLK/_B phase jitter (peak-to-peak)

Note:

t_{CLK_REF}

t_{CLK_TOL}

t_{CLK_RISE}/t_{CLK_FALL}

t_{CLK_DUTY}

t_{CLK_CJ}

100

–350

—

0

150

+350

1

MHz

ppm

ns

1

—

2,3

—

50

—

45

55

%

—

100

+50

ps

t_{CLK_PJ}

–50

ps

1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.

2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.

3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.

T_H

Ref_CLK

T_L

Figure 49. Reference Clock Timing Waveform

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Electrical Characteristics

2.16.2 Differential Transmitter (TX) Output Characteristics

This table provides the differential transmitter (TX) output characteristics for the SATA interface.

Table 60. Differential Transmitter (TX) Output Characteristics

Parameter

Channel Speed

Symbol

Min

Typical

Max

Units

Notes

—

1.5G

3.0G

t_{CH_SPEED}

—

1.5

3.0

—

Gbps

Unit Interval

1.5G

3.0G

—

T_UI

666.4333

333.2167

666.4333

333.3333

670.2333

335.1167

ps

DC Coupled

Common Mode

Voltage

V_{dc_cm}

200

250

450

mV

3

TX Diff Output Voltage

1.5G

3.0G

—

V_{SATA_TXDIFF}

400

500

—

600

700

TX rise/fall time

1.5G

3.0G

—

t_{SATA_20-80TX}

t_{SATA_TXSKEW}

Z_{SATA_TXDIFFIM}

100

67

—

273

136

ps

TX differential skew

—

85

40

—

20

115

—

TX Differential pair

impedance

1.5G

ohm

TX Single ended

impedance

1.5G

—

Z_{SATA_TXSEIM}

ohm

TX AC common mode

voltage (peak to peak)

1.5G

V_{SATA_TXCMMOD}

—

50

mV

3.0G

OOB Differential Delta

V_{SATA_OOBvdoff}

V_{SATA_OOBcm}

—

25

50

mV

1

OOB Common mode

Delta

TX Rise/Fall Imbalance

TX Amplitude Imbalance

T_{SATA_TXR/Fbal}

T_{SATA_TXampbal}

—

20

10

%

—

TX Differential Mode

Return loss

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

—

14

8

6

1, 2

RL_{SATA_TXDD11}

dB

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

6

3

1

—

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Electrical Characteristics

Table 60. Differential Transmitter (TX) Output Characteristics (continued)

Parameter

Symbol

Min

Typical

Max

Units

Notes

TX Common Mode Return

loss

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

—

5

2

1, 2

RL_{SATA_TXCC11}

dB

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

—

2

1

TX Impedance Balance

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

—

30

20

10

1, 2

dB

RL_{SATA_TXDC11}

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

—

10

4

Deterministic jitter

1.5G

3.0G

—

U_{SATA_TXDJ}

—

0.18

0.14

UI

Total Jitter

1.5G

3.0G

U_{SATA_TXTJ}

0.42

0.32

Notes:

1. Only applies when operating in 3.0Gb data rate mode.

2. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode.

3. Only applies to Gen1i mode.

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Electrical Characteristics

80%

Differential

data lines

20%

t_{SATA_20-80TXfall}

t_{SATA_20-80TXrise}

TX+

TX-

TX+

TX-

t_{SAT_TXSKEW}

EARLY (TX+ is early)

LATE (TX+ is late)

Figure 50. Signal Rise and Fall Times and Differential Skew

2.16.3 Differential Receiver (RX) Input Characteristics

This table provides the differential receiver (RX) input characteristics for the SATA interface.

Table 61. Differential Receiver (RX) Input Characteristics

Parameter

Symbol

Min

Typical

Max

Units

Notes

RX Differential Input

Voltage

1.5G

3.0G

V_{SATA_RXDIFF}

1

240

400

—

600

750

mVp-p

ps

RX rise/fall time

1.5G

3.0G

—

5

t_{SATA_20-80RX}

100

67

—

273

136

RX Differential skew

1.5G

3.0G

t_{SATA_RXSKEW}

—

50

ps

RX Differential pair

impedance

1.5G

Z_{SATA_RXDIFFIM}

Z_{SATA_RXSEIM}

85

—

115

ohm

RX Single-Ended

impedance

1.5G

40

—

DC Coupled

Common Mode

Voltage

V_{dc_cm}

200

250

450

mV

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Electrical Characteristics

Table 61. Differential Receiver (RX) Input Characteristics (continued)

Parameter

Symbol

Min

Typical

Max

Units

Notes

RX Differential Mode

Return loss

2, 3

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

—

18

14

10

RL_{SATA_RXDD11}

dB

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

—

8

3

1

RX Common Mode

Return loss

2, 3, 4

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

—

5

2

RL_{SATA_RXCC11}

dB

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

—

2

1

RX Impedance Balance

2, 3

150 MHz - 300 MHz

300 MHz - 600 MHz

600 MHz - 1.2 GHz

—

30

20

dB

RL_{SATA_RXDC11}

1.2 GHz - 2.4 GHz

2.4 GHz - 3.0 GHz

3.0 GHz - 5.0 GHz

—

10

4

Deterministic jitter

1.5G

3.0G

—

U_{SATA_RXDJ}

—

0.4

0.47

UI

Total Jitter

1.5G

3.0G

U_{SATA_RXTJ}

0.65

Notes:

1. The min values apply only to Gen1m, and Gen2m. the min values for Gen1i is 325 mVp-p and for Gen2i is 275 mVp-p.

2. Only applies when operating in 3.0Gb data rate mode.

3. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode.

4. The max value stated for 2.4 GHz - 3.0 GHz range only applies to Gen2i mode for Gen2m the value is 1.

5. Only applies to Gen1i mode.

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Electrical Characteristics

2.16.4 Out-of-Band (OOB) Electrical Characteristics

This table provides the Out-of-Band (OOB) electrical characteristics for the SATA interface of the chip.

Table 62. Out-of-Band (OOB) Electrical Characteristics

Parameter

Symbol

Min

Typical

Max

Units

Notes

OOB Signal Detection Threshold

—

1.5G

3.0G

V_{SATA_OOBDETE}

T_{SATA_UIOOB}

50

75

100

125

200

mVp-p

ps

UI During OOB Signaling

646.67

666.67

686.67

—

COMINIT/ COMRESET and COMWAKE

Transmit Burst Length

T_{SATA_UIOOBTXB}

—

160

—

UI

COMINIT/ COMRESET Transmit Gap Length T_{SATA_UIOOBTXG}

—

480

—

UI

ap

COMWAKE Transmit Gap Length

COMWAKE Gap Detection Windows

T_{SATA_UIOOBTX}

—

160

—

UI

ns

WakeGap

T_{SATA_OOBDet}

55

175

WakeGap

COMINIT/ COMRESET

Gap Detection Windows

T_{SATA_OOBDet}

175

—

525

ns

COMGap

2

2.17 I C

2

This section describes the DC and AC electrical characteristics for the I C interfaces of the chip.

2.17.1 I²C DC Electrical Characteristics

2

This table provides the DC electrical characteristics for the I C interfaces.

2

Table 63. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Supply voltage 3.3 V

Input high voltage level

Input low voltage level

Low level output voltage

OV_DD

V_IH

3.13

0.7 × OV_DD

–0.3

3.47

V

—

1

OV_DD+ 0.3

0.3 × OV_DD

0.2 × OV_DD

V_IL

V_OL

0

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Electrical Characteristics

2

Table 63. I C DC Electrical Characteristics (continued)

At recommended operating conditions with OV_DDof 3.3 V 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Pulse width of spikes which must be suppressed by the input

filter

t_I2KHKL

0

50

ns

2

Input current each I/O pin (input voltage is between 0.1 ×

OV_DDand 0.9 × OV_DD(max)

I_I

–10

—

10

μA

3

Capacitance for each I/O pin

C_I

pF

—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OV_DDis switched off.

2.17.2 I²C AC Electrical Specifications

2

This table provides the AC timing parameters for the I C interfaces.

2

Table 64. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 63).

Parameter

Symbol ¹

Min

Max

Unit

Notes

SCL clock frequency

f_I2C

t_I2CL

0

400

—

kHz

μs

—

Low period of the SCL clock

1.3

0.6

High period of the SCL clock

t_I2CH

—

μs

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

—

μs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

—

μs

Data setup time

t_I2DVKH

t_I2DXKL

100

—

ns

—

2

Data hold time:

μs

CBUS compatible masters

I²C bus devices

—

0

—

Data output delay time

t_I2OVKL

—

0.6

—

0.9

—

μs

ns

3

—

4

Set-up time for STOP condition

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

t

I2PVKH

t

300

I2CR

t

—

4

I2CF

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2

Table 64. I C AC Electrical Specifications (continued)

All values refer to V_IH(min) and V_IL(max) levels (see Table 63).

Parameter

Symbol ¹

Min

Max

Unit

Notes

Bus free time between a STOP and START condition

t_I2KHDX

V_NL

1.3

—

μs

—

Noise margin at the LOW level for each connected device

(including hysteresis)

0.1 × OV_DD

V

Noise margin at the HIGH level for each connected device

(including hysteresis)

V_NH

0.2 × OV_DD

—

V

—

Note:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t_I2Cclock reference (K) going to the

high (H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal)

to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the

chip acts as the I²C bus master while transmitting, the chip drives both SCL and SDA. As long as the load on SCL and SDA

are balanced, the chip would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output

delay time is not a concern. For details of the I²C frequency calculation, refer to Determining the I²C Frequency Divider Ratio

for SCL (AN2919). Note that the I²C Source Clock Frequency is half of the CCB clock frequency for the chip.

3. The maximum t_I2DVKHhas only to be met if the chip does not stretch the LOW period (t_I2CL) of the SCL signal.

4. C_B= capacitance of one bus line in pF.

2

This figure provides the AC test load for the I C.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

2

Figure 51. I C AC Test Load

2

This figure shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_{I2DXKL, I2OVKL}

t_I2SVKH

t_I2PVKH

t

S

Sr

P

S

2

Figure 52. I C Bus AC Timing Diagram

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Electrical Characteristics

2.18 GPIO

This section describes the DC and AC electrical specifications for the GPIO interface of the chip.

2.18.1 GPIO DC Electrical Characteristics

This table provides the DC electrical characteristics for the GPIO interface.

Table 65. GPIO DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

Low-level input voltage

– 0.3

—

0.8

5

Input current

μA

(V_IN¹= 0 V or V_IN= V_DD)

High-level output voltage

(OV_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.4

—

V

Low-level output voltage

(OV_DD= min, I_OL= 2 mA)

0.4

Note:

1. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

2.18.2 GPIO AC Electrical Specifications

This table provides the GPIO input and output AC timing specifications.

1

Table 66. GPIO Input and Output AC Timing Specifications

Characteristic

GPIO inputs—minimum pulse width

Symbol ²

Min

Unit

Notes

t_PIWID

7.5

12

ns

3

GPIO outputs—minimum pulse width

t_GTOWID

—

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings

are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDns to ensure proper operation.

3. The minimum pulse width is a function of the MPX/Platform clock. The minimum pulse width must be greater than or equal

to 4 times the MPX/Platform clock period.

This figure provides the AC test load for the GPIO.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 53. GPIO AC Test Load

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2.19 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the chip.

2.19.1 PCI DC Electrical Characteristics

This table provides the DC electrical characteristics for the PCI interface.

1

Table 67. PCI DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

Low-level input voltage

–0.3

—

0.8

5

Input current

μA

(V_IN²= 0 V or V_IN= V_DD

)

High-level output voltage

(OV_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.4

—

V

Low-level output voltage

(OV_DD= min, I_OL= 2 mA)

0.4

Notes:

1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

2.19.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input

clock. This table provides the PCI AC timing specifications at 66 MHz.

Table 68. PCI AC Timing Specifications at 66 MHz

Parameter

SYSCLK to output valid

Symbol ¹

Min

Max

Unit

Notes

t_PCKHOV

t_PCKHOX

t_PCKHOZ

t_PCIVKH

t_PCIXKH

t_PCRVRH

t_PCRHRX

—

6.0

—

14

—

50

ns

2, 3

2

Output hold from SYSCLK

SYSCLK to output high impedance

Input setup to SYSCLK

2.0

—

ns

2, 4

2, 5

6, 7

7

3.0

ns

Input hold from SYSCLK

0

10 × t_SYS

0

ns

REQ64 to HRESET ⁹setup time

clocks

ns

HRESET to REQ64 hold time

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Table 68. PCI AC Timing Specifications at 66 MHz (continued)

Parameter

Symbol ¹

Min

Max

Unit

Notes

HRESET high to first FRAME assertion

Rise time (20%–80%)

Failing time (20%–80%)

Notes:

t_PCRHFV

tPCICLK

10

0.6

—

clocks

ns

8

2.1

—

ns

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_PCIVKHsymbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t_SYS, reference (K)

going to the high (H) state or setup time. Also, t_PCRHFVsymbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. All PCI signals are measured from OV_DD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV_DDof the signal in question for 3.3-V

PCI signaling levels.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

6. The timing parameter t_SYSindicates the minimum and maximum CLK cycle times for the various specified frequencies. The

system clock period must be kept within the minimum and maximum defined ranges. For values see Section 22, “Clocking.”

7. The setup and hold time is with respect to the rising edge of HRESET.

8. The timing parameter t_PCRHFVis a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus

Specifications.

9. The reset assertion timing requirement for HRESET is 100 μs.

This figure provides the AC test load for PCI.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 54. PCI AC Test Load

This figure shows the PCI input AC timing conditions.

CLK

t_PCIVKH

t_PCIXKH

Input

Figure 55. PCI Input AC Timing Measurement Conditions

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This figure shows the PCI output AC timing conditions.

CLK

t_PCKHOV

Output Delay

t_PCKHOZ

High-Impedance

Output

Figure 56. PCI Output AC Timing Measurement Condition

2.20 High-Speed Serial Interfaces

This chip features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The

SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for SGMII or SATA.

This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes

Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.

2.20.1 Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description

and specification of differential signals.

Figure 57 shows how the signals are defined. For illustration purposes, only one SerDes lane is used for description. The figure

shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each

signal swings between A Volts and B Volts where A > B.

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes

transmitter and receiver operate in a fully symmetrical differential signaling environment.

1. Single-Ended Swing

The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a

peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s Single-Ended Swing.

2. Differential Output Voltage, V (or Differential Output Swing):

OD

The Differential Output Voltage (or Swing) of the transmitter, V , is defined as the difference of the two complimentary output

OD

voltages: V

- V

The V value can be either positive or negative.

SDn_TX

SDn_TX. OD

3. Differential Input Voltage, V (or Differential Input Swing):

ID

The Differential Input Voltage (or Swing) of the receiver, V , is defined as the difference of the two complimentary input

ID

voltages: V

- V

The V value can be either positive or negative.

SDn_RX

SDn_RX. ID

4. Differential Peak Voltage, V

DIFFp

The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak

Voltage, V

= |A - B| Volts.

DIFFp

5. Differential Peak-to-Peak, V

DIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to

-(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential

receiver input signal is defined as Differential Peak-to-Peak Voltage, V

= 2*V

=

DIFFp-p

DIFFp

2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential

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peak. For example, the output differential peak-peak voltage can also be calculated as V

TX-DIFFp-p

= 2*|V |.

OD

6. Common Mode Voltage, V

cm

The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange

circuit and ground. In this example, for SerDes output, V = V + V = (A + B)

cm_out

SDn_TX

/ 2, which is the arithmetic mean of the two complimentary output voltages within a differential

pair. In a system, the common mode voltage may often differ from one component’s output to the

other’s input. Sometimes, it may be even different between the receiver input and driver output

circuits within the same component. It is also referred as the DC offset in some occasion.

SDn_TX or

SDn_RX

A Volts

B Volts

V_cm= (A + B) / 2

SDn_TX or

SDn_RX

Differential Swing, V_IDor V_OD= A – B

Differential Peak Voltage, V_DIFFp= |A – B|

Differential Peak-Peak Voltage, V_DIFFpp= 2*V_DIFFp(not shown)

Figure 57. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common

mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values,

the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each

signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential

swing (V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500

OD

mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage

OD

(V

) is 500 mV. The peak-to-peak differential voltage (V

) is 1000 mV p-p.

DIFFp

DIFFp-p

2.20.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding

SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference

clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.

The following sections describe the SerDes reference clock requirements and some application information.

2.20.2.1 SerDes Reference Clock Receiver Characteristics

Figure 58 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for X2V are specified in Table 2 and Table 3.

DD

SerDes Reference Clock Receiver Reference Circuit Structure

— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 58.

Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss)

followed by on-chip AC-coupling.

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— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and

Single-ended Mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the

maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage

is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the

following bullet for more detail), since the input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)

while the minimum common mode input level is 0.1V above SnGND (xcorevss). For example, a clock with a

50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA

(0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800mV with the

common mode voltage at 400mV.

— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SnGND (xcorevss)

DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

50 Ω

SDn_REF_CLK

Input

Amp

SDn_REF_CLK

50 Ω

Figure 58. Receiver of SerDes Reference Clocks

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2.20.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the chip’s SerDes reference clock inputs is different depending on the signaling mode used to

connect the clock driver chip and SerDes reference clock inputs as described below.

•

Differential Mode

— The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or

between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have

a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external

DC-coupled or AC-coupled connection.

— For external DC-coupled connection, as described in Section 2.20.2.1, “SerDes Reference Clock Receiver

Characteristics,” the maximum average current requirements sets the requirement for average voltage (common

mode voltage) to be between 100 mV and 400 mV. Figure 59 shows the SerDes reference clock input requirement

for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since

the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver

operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has

its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and

above the command mode voltage (SnGND). Figure 60 shows the SerDes reference clock input requirement for

AC-coupled connection scheme.

•

Single-ended Mode

— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be

between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or

tied to ground.

— The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 61 shows the SerDes

reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled

externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused

phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.

200 mV < Input Amplitude or Differential Peak < 800 mV

SDn_REF_CLK

Vmax < 800 mV

100 mV < Vcm < 400 mV

Vmin > 0 V

SDn_REF_CLK

Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)

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200mV < Input Amplitude or Differential Peak < 800 mV

SDn_REF_CLK

Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm – 400 mV

SDn_REF_CLK

Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled)

400 mV < SDn_REF_CLK Input Amplitude < 800 mV

SDn_REF_CLK

0V

SDn_REF_CLK

Figure 61. Single-Ended Reference Clock Input DC Requirements

2.20.2.3 Interfacing With Other Differential Signaling Levels

With on-chip termination to SnGND (xcorevss), the differential reference clocks inputs are HCSL (High-Speed Current

Steering Logic) compatible DC-coupled.

Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to

be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection.

LVPECL (Low Voltage Positive Emitter-Coupled Logic) outputs can produce signal with too large amplitude and may need to

be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

NOTE

Figure 62 to Figure 65 below are for conceptual reference only. Due to the fact that clock

driver chip's internal structure, output impedance and termination requirements are

different between various clock driver chip manufacturers, it is very possible that the clock

circuit reference designs provided by clock driver chip vendor are different from what is

shown below. They might also vary from one vendor to the other. Therefore, Freescale

Semiconductor can neither provide the optimal clock driver reference circuits, nor

guarantee the correctness of the following clock driver connection reference circuits. The

system designer is recommended to contact the selected clock driver chip vendor for the

optimal reference circuits with the chip’s SerDes reference clock receiver requirement

provided in this document.

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This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC

levels of the clock driver chip is compatible with chip’s SerDes reference clock input’s DC requirement.

HCSL CLK Driver Chip

50 Ω

SDn_REF_CLK

CLK_Out

33 Ω

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

Clock Driver

33 Ω

SDn_REF_CLK

CLK_Out

50 Ω

Clock driver vendor dependent

source termination resistor

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

Figure 62. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock

driver’s common mode voltage is higher than the chip’s SerDes reference clock input’s allowed range (100 to 400mV),

AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also

assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external

component.

LVDS CLK Driver Chip

50 Ω

SDn_REF_CLK

10 nF

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

Clock Driver

SDn_REF_CLK

CLK_Out

10 nF

50 Ω

Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

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This figure shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL

driver’s DC levels (both common mode voltages and output swing) are incompatible with chip’s SerDes reference clock input’s

DC requirement, AC-coupling has to be used. This figure assumes that the LVPECL clock driver’s output impedance is 50Ω.

R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending on

clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to

attenuate the LVPECL output’s differential peak level such that it meets the chip’s SerDes reference clock’s differential input

amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak

is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which

requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with

a particular clock driver chip.

LVPECL CLK

Driver Chip

50 Ω

SDn_REF_CLK

CLK_Out

10nF

R2

SerDes Refer.

CLK Receiver

R1

100 Ω differential PWB trace

10 nF

Clock Driver

R2

SDn_REF_CLK

CLK_Out

50 Ω

Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC

levels of the clock driver are compatible with chip’s SerDes reference clock input’s DC requirement.

Single-Ended

CLK Driver Chip

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

SDn_REF_CLK

33 Ω

Clock Driver

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

SDn_REF_CLK

50 Ω

Figure 65. Single-Ended Connection (Reference Only)

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2.20.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase

noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz

is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock

driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system.

This table describes some AC parameters common to SGMII and PCI Express protocols.

Table 69. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with XV_{DD_SRDS1}or XV_{DD_SRDS2}= 1.0V 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Rising Edge Rate

Falling Edge Rate

Rise Edge Rate

1.0

+200

—

4.0

—

V/ns

mV

%

2, 3

2

Fall Edge Rate

Differential Input High Voltage

Differential Input Low Voltage

V_IH

V_IL

–200

20

2

Rising edge rate (SDn_REF_CLK) to falling edge rate

(SDn_REF_CLK) matching

Rise-Fall

Matching

—

1, 4

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is

centered on the differential zero crossing. See Figure 66.

4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200

mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross

point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate

of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not

exceed 20% of the slowest edge rate. See Figure 67.

Rise Edge Rate

Fall Edge Rate

V_IH= +200 mV

0.0 V

V_IL= –200 mV

SDn_REF_CLK –

SDn_REF_CLK

Figure 66. Differential Measurement Points for Rise and Fall Time

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T_FALL

T_RISE

SDn_REF_CLK

V_{CROSS MEDIAN}

SDn_REF_CLK

V_{CROSS MEDIAN}+ 100 mV

V_{CROSS MEDIAN}

V_{CROSS MEDIAN}– 100 mV

SDn_REF_CLK

Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application

usage. See the following sections for detailed information:

•

Section 2.9.3.2, “AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK”

Section 2.21.2, “AC Requirements for PCI Express SerDes Clocks”

2.20.2.4.1

Spread Spectrum Clock

SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30–33 kHz

rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended

modulation should be used.

SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock

source.

2.20.3 SerDes Transmitter and Receiver Reference Circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

SD1_RXn or

SD2_RXn

SD1_TXn or

SD2_TXn

50 Ω

Receiver

Transmitter

SD1_TXn or

SD2_TXn

SD1_RXn or

SD2_RXn

Figure 68. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or

SGMII) in this document based on the application usage:

•

Section 2.9.3, “SGMII Interface Electrical Characteristics”

Section 2.21, “PCI Express”

Section 2.16, “Serial ATA (SATA)”

Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor

value defined in specification of each protocol section.

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2.21 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the chip.

2.21.1 DC Requirements for PCI Express SD1_REF_CLK and

SD1_REF_CLK

For more information, see Section 2.20.2, “SerDes Reference Clocks.”

2.21.2 AC Requirements for PCI Express SerDes Clocks

This table lists AC requirements.

Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

t_REF

REFCLK cycle time

—

10

—

ns

ps

1

t_REFCJREFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

100

—

t_REFPJPhase jitter. Deviation in edge location with respect to mean edge

location

–50

—

50

ps

1,2,3

Notes:

1. Tj at BER of 10E-6 86 ps Max.

2. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 42 ps.

3. Limits from “PCI Express CEM Rev 2.0” and measured per “PCI Express Rj, D, and Bit Error Rates”.

2.21.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all

times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.

2.21.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this chip. For further details as well

as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.

2.21.4.1 Differential Transmitter (TX) Output

This table defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the

component pins.

Table 71. Differential Transmitter (TX) Output Specifications

Symbol

Parameter

Unit Interval

Min

Nom Max Units

Comments

UI

399.88 400 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for

Spread Spectrum Clock dictated variations. See Note

1.

V_TX-DIFFp-p

Differential

0.8

—

1.2

V

V_TX-DIFFp-p= 2*|V_TX-D+– V_TX-D-| See Note 2.

Peak-to-Peak

Output Voltage

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Table 71. Differential Transmitter (TX) Output Specifications (continued)

Symbol

Parameter

Min

Nom Max Units

Comments

V_TX-DE-RATIO

De- Emphasized

Differential Output

Voltage (Ratio)

–3.0

–3.5

–4.0

dB Ratio of the V_TX-DIFFp-pof the second and following

bits after a transition divided by the V_TX-DIFFp-pof the

first bit after a transition. See Note 2.

T_TX-EYE

Minimum TX Eye

Width

0.70

—

UI The maximum Transmitter jitter can be derived as

T

_{TX-MAX-JITTER}= 1 – T_TX-EYE= 0.3 UI.

See Notes 2 and 3.

T_{TX-EYE-MEDIAN-to-}

Maximum time

between the jitter

median and

maximum

deviation from the

median.

—

0.15

UI Jitter is defined as the measurement variation of the

crossing points (V_TX-DIFFp-p= 0 V) in relation to a

recovered TX UI. A recovered TX UI is calculated over

3500 consecutive unit intervals of sample data. Jitter

is measured using all edges of the 250 consecutive UI

in the center of the 3500 UI used for calculating the TX

UI. See Notes 2 and 3.

MAX-JITTER

T_TX-RISE, T_TX-FALL

D+/D- TX Output

Rise/Fall Time

0.125

—

UI See Notes 2 and 5

V_TX-CM-ACp

RMS AC Peak

Common Mode

Output Voltage

20

mV V_TX-CM-ACp= RMS(|V_TXD++V_TXD-|/2 – V_TX-CM-DC

V_TX-CM-DC= DC_(avg)of |V_TX-D++V_TX-D-|/2

See Note 2

)

V_{TX-CM-DC-ACTIVE-}

Absolute Delta of

DC Common

Mode Voltage

During L0 and

Electrical Idle

0

—

100

25

mV |V_{TX-CM-DC (during L0)}– V_{TX-CM-Idle-DC (During Electrical}

_Idle)|<=100 mV

IDLE-DELTA

V_TX-CM-DC= DC_(avg)of |V_TX-D++V_TX-D-|/2 [L0]

V_{TX-CM-Idle-DC}= DC_(avg)of |V_TX-D++ V_TX-D-|/2

[Electrical Idle]

See Note 2.

V_{TX-CM-DC-LINE-DELTA}Absolute Delta of

DC Common

0

—

mV |V_TX-CM-DC-D+– V_TX-CM-DC-D-| <= 25 mV

V_TX-CM-DC-D+= DC_(avg)of |V_TX-D+

|

Mode between D+

and D–

V_TX-CM-DC-D-= DC_(avg)of |V_TX-D-

See Note 2.

|

V_{TX-IDLE-DIFFp}

Electrical Idle

differential Peak

Output Voltage

0

—

20

mV V_{TX-IDLE-DIFFp}= |V_TX-IDLE-D+-V_TX-IDLE-D-| <= 20 mV

See Note 2.

V_{TX-RCV-DETECT}

The amount of

voltage change

allowed during

Receiver Detection

—

600

mV The total amount of voltage change that a transmitter

can apply to sense whether a low impedance

Receiver is present. See Note 6.

V_TX-DC-CM

The TX DC

Common Mode

Voltage

0

—

3.6

V

The allowed DC Common Mode voltage under any

conditions. See Note 6.

I_TX-SHORT

TX Short Circuit

Current Limit

—

90

—

mA The total current the Transmitter can provide when

shorted to its ground

T_TX-IDLE-MIN

Minimum time

spent in Electrical

Idle

50

UI Minimum time a Transmitter must be in Electrical Idle

Utilized by the Receiver to start looking for an

Electrical Idle Exit after successfully receiving an

Electrical Idle ordered set

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Electrical Characteristics

Table 71. Differential Transmitter (TX) Output Specifications (continued)

Symbol

Parameter

Min

Nom Max Units

Comments

T_{TX-IDLE-SET-TO-IDLE}Maximum time to

transition to a valid

electrical idle after

sending an

—

20

UI After sending an Electrical Idle ordered set, the

Transmitter must meet all Electrical Idle Specifications

within this time. This is considered a debounce time

for the Transmitter to meet Electrical Idle after

transitioning from L0.

electrical Idle

ordered set

T_{TX-IDLE-TO-DIFF-DATA}Maximum time to

transition to valid

TX specifications

after leaving an

—

20

UI Maximum time to meet all TX specifications when

transitioning from Electrical Idle to sending differential

data. This is considered a debounce time for the TX to

meet all TX specifications after leaving Electrical Idle

electrical idle

condition

RL_TX-DIFF

RL_TX-CM

Z_TX-DIFF-DC

Z_TX-DC

Differential Return

Loss

12

6

—

dB Measured over 50 MHz to 1.25 GHz. See Note 4

Common Mode

Return Loss

DC Differential TX

Impedance

80

40

—

75

100

—

120

—

Ω

TX DC Differential mode Low Impedance

Transmitter DC

Impedance

Required TX D+ as well as D- DC Impedance during

all states

L_TX-SKEW

Lane-to-Lane

Output Skew

—

500 +

2 UI

ps Static skew between any two Transmitter Lanes within

a single Link

C_TX

AC Coupling

Capacitor

—

200

nF All Transmitters shall be AC coupled. The AC coupling

is required either within the media or within the

transmitting component itself. See Note 8.

T_crosslink

Crosslink Random

Timeout

0

—

1

ms This random timeout helps resolve conflicts in

crosslink configuration by eventually resulting in only

one Downstream and one Upstream Port. See Note 7.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over

any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50)

3. A T_TX-EYE= 0.70 UI provides for a total sum of deterministic and random jitter budget of T_{TX-JITTER-MAX}= 0.30 UI for the

Transmitter collected over any 250 consecutive TX UIs. The T_{TX-EYE-MEDIAN-to-MAX-JITTER}median is less than half of the total

TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed

to the averaged time value.

4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+

and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 52). Note that the series

capacitors C_TXis optional for the return loss measurement.

5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both V_TX-D+and V_TX-D-

.

6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a

7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a

8. SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.

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Electrical Characteristics

2.21.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of

any real PCI Express interconnect + RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter

median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the

transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges

of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in the 3500

consecutive UI interval with a fit algorithm using a minimization merit function (that is,

least squares and median deviation fits).

V_RX-DIFF= 0 mV

V_TX-DIFF= 0 mV

(D+ D– Crossing Point)

[Transition Bit]

_{TX-DIFFp-p-MIN}= 800 mV

V

[De-Emphasized Bit]

566 mV (3 dB ) >= V_{TX-DIFFp-p-MIN}>= 505 mV (4 dB )

0.07 UI = UI – 0.3 UI (J_TX-TOTAL-MAX

)

[Transition Bit]

_{TX-DIFFp-p-MIN}= 800 mV

V

Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications

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Electrical Characteristics

2.21.4.3 Differential Receiver (RX) Input Specifications

This table defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the

component pins.

Table 72. Differential Receiver (RX) Input Specifications

Symbol

Parameter

Min

Nom

Max

Units

Comments

UI

Unit Interval

399.8

8

400

400.12

ps

Each UI is 400 ps 300 ppm. UI does not

account for Spread Spectrum Clock dictated

variations. See Note 1.

V_RX-DIFFp-p

Differential

Peak-to-Peak

Output Voltage

0.175

0.4

—

1.200

—

V

_RX-DIFFp-p= 2*|V_RX-D+– V_RX-D-

|

See Note 2.

T_RX-EYE

Minimum

Receiver Eye

Width

UI

The maximum interconnect media and

Transmitter jitter that can be tolerated by the

Receiver can be derived as T_{RX-MAX-JITTER}

1 - T_RX-EYE= 0.6 UI.

=

See Notes 2 and 3.

T_{RX-EYE-MEDIAN-to-MAX}Maximum time

—

0.3

UI

Jitter is defined as the measurement variation

of the crossing points (V_RX-DIFFp-p= 0 V) in

relation to a recovered TX UI. A recovered TX

UI is calculated over 3500 consecutive unit

intervals of sample data. Jitter is measured

using all edges of the 250 consecutive UI in

the center of the 3500 UI used for calculating

the TX UI. See Notes 2, 3 and 7.

between the jitter

median and

maximum

-JITTER

deviation from

the median.

V_RX-CM-ACp

AC Peak

Common Mode

Input Voltage

—

150

—

mV

dB

V_RX-CM-ACp= |V_RXD+– V_RXD-|/2 +V_RX-CM-DC

V_RX-CM-DC= DC_(avg)of |V_RX-D++V_RX-D-|/2

See Note 2

RL_RX-DIFF

Differential

Return Loss

15

Measured over 50 MHz to 1.25 GHz with the

D+ and D- lines biased at +300 mV and –300

mV, respectively.

See Note 4

RL_RX-CM

Common Mode

Return Loss

6

—

100

50

—

120

60

dB

Ω

Measured over 50 MHz to 1.25 GHz with the

D+ and D- lines biased at 0 V. See Note 4

Z_RX-DIFF-DC

DC Differential

Input Impedance

80

40

RX DC Differential mode impedance. See

Note 5

Z_RX-DC

DC Input

Impedance

Ω

Required RX D+ as well as D- DC Impedance

(50 20% tolerance). See Notes 2 and 5.

Z_{RX-HIGH-IMP-DC}

Powered Down 200 k

DC Input

Impedance

—

Ω

Required RX D+ as well as D– DC

Impedance when the Receiver terminations

do not have power. See Note 6.

V_{RX-IDLE-DET-DIFFp-p}

Electrical Idle

Detect Threshold

65

—

175

10

mV

ms

V_{RX-IDLE-DET-DIFFp-p}= 2*|V_RX-D+–V_RX-D-

Measured at the package pins of the Receiver

|

T_{RX-IDLE-DET-DIFF-}

Unexpected

Electrical Idle

Enter Detect

Threshold

An unexpected Electrical Idle (V_RX-DIFFp-p<

V_{RX-IDLE-DET-DIFFp-p}) must be recognized no

longer than T_{RX-IDLE-DET-DIFF-ENTERING}to

signal an unexpected idle condition.

ENTERTIME

Integration Time

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Electrical Characteristics

Table 72. Differential Receiver (RX) Input Specifications (continued)

Symbol

L_TX-SKEW

Parameter

Total Skew

Min

Nom

Max

Units

Comments

—

20

ns

Skew across all lanes on a Link. This includes

variation in the length of SKP ordered set (for

example, COM and one to five Symbols) at

the RX as well as any delay differences

arising from the interconnect itself.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 71 should be used

as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 70). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3. A T_RX-EYE= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and

interconnect collected any 250 consecutive UIs. The T_{RX-EYE-MEDIAN-to-MAX-JITTER}specification ensures a jitter distribution in

which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any

250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point

in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as the reference for the eye diagram.

4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The

reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured

by a Vector Network Analyzer with 50 ohm probes - see Figure 71). Note: that the series capacitors CTX is optional for the

return loss measurement.

5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)

there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.

6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps

ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated

data.

2.22

Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 70 is specified using the passive compliance/test measurement load (see Figure 71) in place of

any real PCI Express RX component.

Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see Figure 71) will

be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI

Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon

parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test

measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer

should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in

Figure 70) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss

measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate

the center of the eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

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Electrical Characteristics

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges

of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.

NOTE

The reference impedance for return loss measurements is 50. to ground for both the D+ and

D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see

Figure 71). Note that the series capacitors, CTX, are optional for the return loss

measurement.

V_RX-DIFF= 0 mV

(D+, D– Crossing Point

V

= 0 mV

RX-DIFF

(D+, D– Crossing Point

V_{RX-DIFFp-p-MIN}> 175 mV

0.4 UI = T_RX-EYE-MIN

Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification

2.22.1 Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package

pins, into a test/measurement load shown in the following figure.

NOTE

The allowance of the measurement point to be within 0.2 inches of the package pins is

meant to acknowledge that package/board routing may benefit from D+ and D– not being

exactly matched in length at the package pin boundary.

D+ Package

C = C_TX

TX

Silicon

+ Package

C = C_TX

D– Package

R = 50 Ω

Figure 71. Compliance Test/Measurement Load

2.23 Clocking

This section describes the PLL configuration of the chip. Note that the platform clock is identical to the core complex bus (CCB)

clock.

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Electrical Characteristics

2.23.1 Clock Ranges

This table provides the clocking specifications for the processor cores and Table 74 provides the clocking specifications for the

memory bus.

Table 73. Processor Core Clocking Specifications

Maximum Processor Core Frequency

Characteristic

600 MHz

800 MHz

1000 MHz

1250 MHz

1333 MHZ

1500 MHz

Min Max

Unit Notes

Min Max Min Max Min Max Min Max

Min

Max

e500 core processor 600

frequency

600 600

800 600 1000 600 1250 600 1333 600 1500 MHz 1, 2, 3

CCB frequency

DDR Data Rate

Notes:

400

400 400

400 333 400 333 500

400 400 400 400 500

333

400

533

667

333

400

500

667

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 2.23.2, “CCB/SYSCLK PLL Ratio” and Section 2.23.3, “e500 Core PLL Ratio“, Section 2.23.4,

“DDR/DDRCLK PLL Ratio,” for ratio settings.

2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency

supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically

possible via valid clock ratio setting in some condition, is not supported.

3. As defined by JEDEC, the minimum allowed data rate for DDR3 is 606 MHz data rate. Therefore, only the processors with a

DDR data rate of 667 MHz support DDR3.

The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the

memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is

clocked with its own dedicated PLL. This table provides the clocking specifications for the memory bus.

Table 74. Memory Bus Clocking Specifications

Characteristic

Min

Max

Unit

Notes

DDR Memory bus clock speed

200

333

MHz

1, 2, 3, 4, 5

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” Section 2.23.3, “e500 Core PLL Ratio,” and

Section 2.23.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.

2. The Memory bus clock refers to the chip’s memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of the

DDR data rate.

3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is

the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,

asynchronous mode must be used.

4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 2.23.4, “DDR/DDRCLK PLL

Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR

data rate.

5. See Table 73 for a list of supported ranges of DDR data to corresponding processor frequency.

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Electrical Characteristics

2.23.2 CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency

of the CCB is set using the following reset signals, as shown in the following table:

•

SYSCLK input signal

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values.

Table 75. CCB Clock Ratio

Binary Value of

LA[28:31] Signals

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

0000

0001

0010

0011

0100

0101

0110

0111

16:1

Reserved

3:1

1000

1001

1010

1011

1100

1101

1110

1111

8:1

9:1

10:1

Reserved

12:1

4:1

5:1

Reserved

6:1

Reserved

2.23.3 e500 Core PLL Ratio

This table describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined

by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in this table.

Table 76. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2 Signals

Binary Value of

LBCTL, LALE,

LGPL2 Signals

e500 core: CCB Clock Ratio

000

001

010

011

4:1

9:2

100

101

110

111

2:1

5:2

3:1

7:2

Reserved

3:2

2.23.4 DDR/DDRCLK PLL Ratio

The DDR memory controller complex can be synchronous with, or asynchronous to, the CCB, depending on configuration.

The following table describes the clock ratio between the DDR memory controller complex and the DDR/DDRCLK PLL

reference clock, DDRCLK, which is not the memory bus clock.

When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default mode of operation

is for the DDR data rate for the DDR controller to be equal to the CCB clock rate in synchronous mode, or the resulting DDR

PLL rate in asynchronous mode.

In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 77 reflects the DDR data rate to DDRCLK ratio,

since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output.

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Electrical Characteristics

Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.

The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down

mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed

prior to initialization of the DDR controller.

Table 77. DDR Clock Ratio

Reset Configuration

Functional Signals

Value (Binary)

DDR:DDRCLK Ratio

Name

000

001

010

011

100

101

110

111

3:1

4:1

6:1

8:1

TSEC_1588_TRIG_OUT[0:1],

TSEC1_1588_CLK_OUT

cfg_ddr_pll[0:2]

10:1

12:1

Reserved

Synchronous mode

2.23.5 PCI Clocks

The integrated PCI controller in this chip supports PCI input clock frequency in the range of 33–66 MHz. The PCI input clock

can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the PCI1_CLK,

refer to the PCI 2.2 Specification.

The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of

PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.

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Electrical Characteristics

2.23.6 Frequency Options

2.23.6.1 SYSCLK to Platform Frequency Options

This table shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in

comparison to the memory bus clock speed.

Table 78. Frequency Options of SYSCLK with Respect to Memory Bus Speeds

CCB to

SYSCLK (MHz)

SYSCLK Ratio

33.33

41.66

66.66

83

100

111

133.33

Platform /CCB Frequency (MHz)

3

4

333

444

400

533

333

415

500

400

500

5

333

400

533

6

8

333

417

500

10

12

16

333

400

533

2.23.6.2 Minimum Platform Frequency Requirements for High-speed Interfaces

Section 4.4.3.8 “SerDes1 I/O Port Selection” and Section 4.4.3.9 “SerDes2 I/O Port Selection” of the MPC8536E

PowerQUICC III Integrated Host Processor Family Reference Manual, describes various high-speed interface configuration

options. Note that the CCB clock frequency must be considered for proper operation of such interfaces as described below.

For proper PCI Express operation, the CCB clock frequency must be equal or greater than:

527 MHz × (PCI Express link width)

----------------------------------------------------------------------------------------------

8

See Section 18.1.3.2, “Link Width,” of the MPC8536E PowerQUICC III Integrated Host Processor Family Reference Manual,

for PCI Express interface width details. Note that the “PCI Express link width” in the above equation refers to the negotiated

link width as the result of PCI Express link training, which may or may not be the same as the link width POR selection.

2.24 Thermal

This section describes the thermal specifications of the chip.

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Electrical Characteristics

2.24.1 Thermal Characteristics

This table provides the package thermal characteristics.

Table 79. Package Thermal Characteristics

Characteristic

JEDEC Board

Symbol

Value

Unit

Notes

Junction-to-ambient Natural Convection

Junction-to-ambient (@200 ft/min)

Junction-to-board thermal

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

R_θJA

R_θJB

R_θJC

23

18

°C/W

1, 2

3

18

14

10

Junction-to-case thermal

—

< 0.1

4

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method

(MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 °C/W

Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material

was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the chip’s thermal

model without a lid is shown in Figure 72 The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane conductivity

of 19.8 W/m•K and a through-plane conductivity of 1.13 W/m•K. The solder balls and air are modeled as a single block

29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/m•K and a through plane conductivity of 12.1 W/m•K. The die is

modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal resistance

between the die and substrate assuming a conductivity of 7.5 W/m•K in the thickness dimension of 0.07 mm. The die is centered

on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual

dimensions.

2.24.2 Recommended Thermal Model

This table shows the chip’s thermal model.

Table 80. Thermal Model

Conductivity

Value

Units

Die (9.6x9.6 × 0.85 mm)

Silicon

Temperature dependent

—

Bump/Underfill (9.6 x 9.6 × 0.07 mm) Collapsed Thermal Resistance

Kz

7.5

W/m•K

Substrate (29 × 29 × 1.2 mm)

Kx

Ky

Kz

19.8

1.13

W/m•K

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

111

Electrical Characteristics

Table 80. Thermal Model (continued)

Conductivity

Value

Units

Solder and Air (29 × 29 × 0.5 mm)

Kx

Ky

Kz

0.034

12.1

W/m•K

Figure 72. System-Level Thermal Model for the Chip (Not to Scale)

The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part

in standard JEDEC environments, as well as the heat spreading in the board under the package. In a real system, however, the

part will require a heat sink to be mounted on it. In this case, the predominant heat flow path will be from the die to the heat

sink. Grid density lower than currently in the package library file will suffice for these simulations. The user will need to

determine the optimal grid for their specific case.

2.24.3 Thermal Management Information

This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for

air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,

and thermal interface material.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

112

Freescale Semiconductor

Electrical Characteristics

The recommended attachment method to the heat sink is illustrated in the following figure. The heat sink should be attached to

the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45

Newton).

FC-PBGA Package

Heat Sink

Clip

Thermal Interface Material

Die

Printed-Circuit Board

Figure 73. Package Exploded Cross-Sectional View with Several Heat Sink Options

The system board designer can choose between several types of heat sinks to place on the chip. Ultimately, the final selection

of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass,

attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha

Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient

thermal resistances, that will allow the chip to function in various environments.

2.24.3.1 Internal Package Conduction Resistance

For the packaging technology, shown in Table 70, the intrinsic internal conduction thermal resistance paths are as follows:

•

The die junction-to-case thermal resistance

The die junction-to-board thermal resistance

This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Internal Resistance

Package/Solder Spheres

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance)

Figure 74. Package with Heat Sink Mounted to a Printed-Circuit Board

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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113

Hardware Design Considerations

The heat sink removes most of the heat from the chip for most applications. Heat generated on the active side of the chip is

conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat

sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance

are the dominant terms.

2.24.3.2 Thermal Interface Materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The

performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is

generally provided by the thermal interface vendors.

3

Hardware Design Considerations

This section provides electrical and thermal design recommendations for successful application of the chip.

3.1

System Clocking

This chip includes seven PLLs:

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio

between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 2.23.2, “CCB/SYSCLK PLL Ratio.”

•

The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500

core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3,

“e500 Core PLL Ratio.”

•

The PCI PLL generates the clocking for the PCI bus

The local bus PLL generates the clock for the local bus.

There is a PLL for the SerDes1 block to be used for PCI Express interface

There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.

The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The

frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, “DDR/DDRCLK PLL Ratio.”

3.2

Power Supply Design and Sequencing

PLL Power Supply Filtering

3.2.1

Each of the PLLs listed above is provided with power through independent power supply pins (AV _PLAT, AV _CORE,

DD

AV _PCI, AV _LBIU, and AV _SRDS respectively). The AV level should always be equivalent to V , and

DD

preferably these voltages will be derived directly from V through a low frequency filter scheme such as the following.

DD

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent

filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AV pins. By providing independent filters

DD

to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built

with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.

Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors

of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize noise coupled from

DD

nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of 783

DD

FC-PBGA the footprint, without the inductance of vias.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

114

Freescale Semiconductor

Hardware Design Considerations

This figure shows the PLL power supply filter circuit.

10 Ω

V_DD

AV_DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 75. Chip PLL Power Supply Filter Circuit

The AV _SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,

DD

the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 76. For maximum

effectiveness, the filter circuit is placed as closely as possible to the AV _SRDSn balls to ensure it filters out as much noise

DD

as possible. The ground connection should be near the AV _SRDSn balls. The 0.003-µF capacitor is closest to the balls,

DD

followed by the 1-µF capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from

AV _SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces

DD

should be kept short, wide and direct.

1.0 Ω

SnV_DD

AV_{DD -}SRDS

2.2 µF ¹

0.003 µF

GND

1. An 0805 sized capacitor is recommended for system initial bring-up

Figure 76. SerDes PLL Power Supply Filter Circuit

Note the following:

•

AV should be a filtered version of SV

.

DD

Signals on the SerDes interface are fed from the XV power plane.

DD

3.3

Pin States in Deep Sleep State

In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain

enabled.

The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable

the receivers of input pads as defined in Table 1. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual

for details.

3.4

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, this chip can generate transient power surges and high

frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching

other components in the chip system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each V , TV , BV , OV , GV , and

DD

LV pin of the chip. These decoupling capacitors should receive their power from separate V TV , BV , OV , GV ,

DD

DD,

DD

and LV , and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors must

DD

be placed directly under the chip using a standard escape pattern as much as possible. If some caps are to be placed surrounding

the part it should be routed with short and large trace to minimize the inductance.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

115

Hardware Design Considerations

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to

minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V , TV

,

DD

BV , OV , GV , and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should

DD

have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected

to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types

and quantity of bulk capacitors.

3.5

SerDes Block Power Supply Decoupling Recommendations

he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnV and XnV ) to ensure low jitter on

DD

transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to

power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls

of the chip. Where the board has blind vias, these capacitors should be placed directly below the chip supply and

ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the

chip as close to the supply and ground connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SnV and XnV ) to the board

DD DD

ground plane on each side of the chip. This should be done for all SerDes supplies.

Third, between the chip and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance

(ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all

SerDes supplies.

3.6

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active

low inputs should be tied to V TV , BV , OV , GV , and LV as required. All unused active high inputs should be

DD,

DD

connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all

external V TV , BV , OV , GV , and LV and GND pins of the chip.

DD,

DD

3.7

Pull-Up and Pull-Down Resistor Requirements

2

The chip requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins including I C pins and MPIC

interrupt pins.

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.

Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most

have asynchronous behavior and spurious assertion will give unpredictable results.

The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ,

TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a

proper state during POR configuration. Please refer to the pinlist table (see Table 62) of the individual chip for more details.

See the PCI 2.2 specification for all pull-ups required for PCI.

3.8

Output Buffer DC Impedance

The chip drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended

2

driver type (open drain for I C).

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116

Freescale Semiconductor

Hardware Design Considerations

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV or GND. Then, the

0

DD

value of each resistor is varied until the pad voltage is OV /2 (see Figure 77). The output impedance is the average of two

DD

components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

R is trimmed until the voltage at the pad equals OV /2. R then becomes the resistance of the pull-up devices. R and R

P

DD

P

N

are designed to be close to each other in value. Then, Z = (R + R )/2.

0

P

N

OV_DD

R_N

SW2

SW1

Pad

Data

R_P

OGND

Figure 77. Driver Impedance Measurement

This table summarizes the signal impedance targets. The driver impedances are targeted at minimum V , nominal OV

,

DD

105°C.

Table 81. Impedance Characteristics

Local Bus, Ethernet, DUART,

Impedance Control, Configuration, Power

Management

PCI

DDR DRAM

Symbol Unit

R

45 Target

45 Target (cfg_pci_impd=1) 18 Target (full strength mode)

25 Target (cfg_pci_impd=0) 36 Target (full strength mode)

Z₀

Ω

N

P

R

45 Target

45 Target (cfg_pci_impd=1) 18 Target (full strength mode)

25 Target (cfg_pci_impd=0) 36 Target (full strength mode)

Z₀

Ω

Note: Nominal supply voltages. See Table 1.

3.9

Configuration Pin Muxing

The chip provides the user with power-on configuration options which can be set through the use of external pull-up or

pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as

output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is

asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal

function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 kΩ. This

value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled

only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When

the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal

quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage

level puts the chip into the default state and external resistors are needed only when non-default settings are required by the user.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

117

Hardware Design Considerations

Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down

resistor should minimize the disruption of signal quality or speed for output pins thus configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.

3.10 JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.

Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most

have asynchronous behavior and spurious assertion will give unpredicatable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1

specification, but it is provided on all processors built on Power Architecture technology. The chip requires TRST to be asserted

during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the

TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST during the

power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the

common on-chip processor (COP), which implements the debug interface to the chip.

The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging

software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG

port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert

HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage

monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into

these signals with logic.

The arrangement shown in Figure 78 allows the COP port to independently assert HRESET or TRST, while ensuring that the

target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 79, for connection to the target system, and is based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a

connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and

other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.

There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from

emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while

still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement

recommended in Figure 79 is common to all known emulators.

3.10.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•

TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal

(HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale

recommends that the COP header be designed into the system as shown in Figure 78. If this is not possible, the

isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in

future debug situations.

•

No pull-up/pull-down is required for TDI, TMS, or TDO.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

118

Freescale Semiconductor

Hardware Design Considerations

OV_DD

10 kΩ

SRESET ⁶

HRESET¹

SRESET

HRESET

From Target

Board Sources

(if any)

COP_HRESET

13

11

10 kΩ

COP_SRESET

5

TRST¹

COP_TRST

4

2

1

3

COP_VDD_SENSE²

NC

10 Ω

4

6

5

7

6

8

5 ³

COP_CHKSTP_OUT

CKSTP_OUT

15

10 kΩ

9

10

12

14 ³

11

10 kΩ

KEY

13

15

COP_CHKSTP_IN

COP_TMS

No pin

CKSTP_IN

TMS

8

9

1

3

16

COP_TDO

COP_TDI

COP_TCK

COP Connector

Physical Pinout

TDO

TDI

7

2

TCK

NC

10 kΩ

10

4

12

16

Notes:

1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in

order to fully control the processor as shown here.

2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing

to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to

position B.

6. Asserting SRESET causes a machine check interrupt to the e500 core.

Figure 78. JTAG Interface Connection

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

119

Hardware Design Considerations

2

1

3

COP_TDO

COP_TDI

NC

4

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

NC

5

7

6

8

COP_TCK

COP_TMS

COP_SRESET

9

10

12

NC

11

KEY

13

15

COP_HRESET

No pin

GND

COP_CHKSTP_OUT

16

Figure 79. COP Connector Physical Pinout

3.11 Guidelines for High-Speed Interface Termination

3.11.1 SerDes1 Interface Entirely Unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However,

the SerDes must always have power applied to its supply pins. See SerDes1 in Table 1 for details.

The following pins must be left unconnected (float):

•

SD1_TX[7:0]

Reserved pins T22, T23

The following pins must be connected to XGND:

•

SD1_RX[7:0]

SD1_REF_CLK

The POR configuration pin cfg_io_ports[0:2] on TSEC3_TXD[6:3] can be used to power down SerDes 1 block for power

saving. Note that both SVDD and XVDD must remain powered.

3.11.2 SerDes 1 Interface Partly Unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as

described in this section.

The following pins must be left unconnected (float) if not used:

•

SD1_TX[7:0]

Reserved pins: T22, T23

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

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120

Ordering Information

The following pins must be connected to XGND if not used:

•

SD1_RX[7:0]

SD1_REF_CLK

3.11.3 SerDes 2 Interface Entirely Unused

If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this

section. See SerDes2 in Table 1 for details.

The following pins must be left unconnected (float):

•

SD2_TX[1:0]

Reserved pins L8, L9

The following pins must be connected to X2GND:

•

SD2_RX[1:0]

SD2_REF_CLK

The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be

used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered.

3.11.4 SerDes 2 Interface Partly Unused

If only part of the high speed SerDes 2 (SGMII/SATA) interface pins are used, the remaining high-speed serial I/O pins should

be terminated as described in this section.

The following pins must be left unconnected (float) if not used:

•

SD2_TX[1:0]

Reserved pins: T22, T23

The following pins must be connected to X2GND if not used:

•

SD2_RX[1:0]

4

Ordering Information

Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbering

Nomenclature.”

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

121

Ordering Information

4.1

Part Numbering Nomenclature

This table shows the part numbering nomenclature.

Table 82. Part Numbering Nomenclature

MPC

nnnn

E

C

VT

AA

X

R

Product

Code Identifier

Part

Security

Engine

Tiers and Temperature

Range

Processor

DDR

Package ¹

Revision Level

Frequency ²

Frequency³

MPC

8536

• A = Commercial tier

standard temperature

range (0° to 90°C)

• VT = FC-PBGA • AK = 600 MHz • G = 400 MHz Blank = Ver. 1.0

(Pb-free)⁴

• PX = plastic

standard

• AN = 800 MHz • H = 500 MHz or 1.1 (SVR =

• AQ = 1000 MHz • J = 533 MHz 0x803F0090,

• AT = 1250 MHz • L = 667 MHz 0x803F0091)

E = included • B or Blank = industrial

tier standard

temperature range (0°

to 105°C)

• VJ = lead-free • AU = 1333 MHz

A = Ver. 1.2

• (SVR =

FC-PBGAs⁵

• AV = 1500 MHz

0x803F0092)

• C = Industrial tier

Blank = not

Blank = Ver. 1.0

or 1.1 (SVR =

0x80370090,

0x80370091)

A = Ver. 1.2

• (SVR =

extended temperature

included

range (–40° to 105°C)

0x80370092)

Notes:

1. See Section 5, “Package Information,” for more information on available package types.

2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support

all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies.

3. See Table 84 for the corresponding maximum platform frequency.

4. The VT part number is ROHS-compliant, with the permitted exception of the C4 die bumps.

5. The VJ part number is entirely lead-free, including the C4 die bumps.

4.2

Part Marking

Parts are marked as in the example shown in the following figure.

MPC853nVTnnnn

ATWLYYWW

MMMMM CCCCC

YWWLAZ

FC-PBGA

Notes:

MMMMM is the 5-digit mask number.

ATWLYYWW is the traceability code.

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

Figure 80. Part Marking for FC-PBGA

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122

Freescale Semiconductor

Package Information

4.3

Part Numbering

This table lists all part numbers that are offered for the chip.

Table 83. MPC8536 Part Numbers Commercial Tier

Core/Platform/DDR (MHz)

Standard Temp Without Security

Standard Temp With Security

Notes

600/400/400

800/400/400

1000/400/400

1250/500/500

1333/533/667

1500/500/667

Note:

MPC8536AVJAKG(A)

MPC8536AVJANG(A)

MPC8536AVJAQG(A)

MPC8536AVJATH(A)

MPC8536AVJAUL(A)

MPC8536AVJAVL(A)

MPC8536EAVJAKG(A)

MPC8536EAVJANG(A)

MPC8536EAVJAQG(A)

MPC8536EAVJATH(A)

MPC8536EAVJAUL(A)

MPC8536EAVJAVL(A)

1

1. The last letter A indicates a Rev 1.2 silicon. It would be Rev 1.0 or Rev 1.1 silicon without a letter A

Table 84. MPC8536 Part Numbers Industrial Tier

Core/Platform/

DDR (MHz)

Standard Temp

Without Security

Standard Temp

With Security

Extended Temp

Without Security

Extended Temp

With Security

Notes

600/400/400

800/400/400

1000/400/400

1250/500/500

1333/533/667

1500/500/667

Note:

MPC8536BVJAKG(A) MPC8536EBVJAKG(A) MPC8536CVJAKG(A) MPC8536ECVJAKG(A)

MPC8536BVJANG(A) MPC8536EBVJANG(A) MPC8536CVJANG(A) MPC8536ECVJANG(A)

MPC8536BVJAQG(A) MPC8536EBVJAQG(A) MPC8536CVJAQG(A) MPC8536ECVJAQG(A)

MPC8536BVJATH(A) MPC8536EBVJATH(A) MPC8536CVJATH(A) MPC8536ECVJATH(A)

MPC8536BVJAUL(A) MPC8536EBVJAUL(A) MPC8536CVJAUL(A) MPC8536ECVJAUL(A)

MPC8536BVJAVL(A) MPC8536EBVJAVL(A) MPC8536CVJAVL(A) MPC8536ECVJAVL(A)

1

1. The last letter A indicates a Rev 1.2 silicon. It would be Rev 1.0 or Rev 1.1 silicon without a letter A

5

Package Information

This section details package parameters, pin assignments, and dimensions.

5.1

Package Parameters for the FC-PBGA

The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783 flip chip plastic ball

grid array (FC-PBGA) without a lid.

Package outline

Interconnects

29 mm × 29 mm

783

Pitch

1 mm

Minimum module height

Maximum module height

Solder Balls

2.23 mm

2.8 mm

96.5Sn/3.5Ag

0.6 mm

Ball diameter (typical)

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

123

Package Information

5.2

Mechanical Dimensions of the FC-PBGA

The mechanical dimensions and bottom surface nomenclature of the 783 FC-PBGA package are shown in the following figure.

Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA

NOTES for Figure 81

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

124

Freescale Semiconductor

Product Documentation

5. Capacitors may not be present on all devices

6. Caution must be taken not to short exposed metal capacitor pads on package top.

7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.

6

Product Documentation

The following documents are required for a complete description of the chip and are needed to design properly with the part.

•

MPC8536E PowerQUICC III Integrated Processor Reference Manual (document number: MPC8536ERM)

e500 PowerPC Core Reference Manual (document number: E500CORERM)

7

Document Revision History

This table provides a revision history for this hardware specification.

Table 85. Document Revision History

Substantive Change(s)

Revision

Date

7

07/2015 • In Section 4, “Ordering Information,” added back the “A” temperature range parts and the MPC8536

Part Numbers Commercial Tier table.

6

09/2014 • In Table 82, “Part Numbering Nomenclature,” added footnotes 4 and 5, and updated the Package

and Tiers and Temperature Range columns.

• In Section 4, “Ordering Information,” removed the “A” temperature range parts and the MPC8536

Part Numbers Commercial Tier table.

• Updated Table 73 and added note 3.

• Updated and added note 5 to Table 74.

• Updated section title to Section 4.1, “Part Numbering Nomenclature.”

• Removed part MPC8536BVTATL(A) from Table 84.

5

4

09/2011 Removed PVDD from Table 1, “Pinout Listing.”

06/2011 • In Table 1, “Pinout Listing,” updated the power supply for TSEC3 pins to TVDD.

• Updated Table 56, “eSDHC AC Timing Specifications.”

• In Section 4.3, “Part Numbering,” added an extra bin (1250/500/667) to support DDR3.

3

11/2010 • In Table 1, “Pinout Listing,” added the following note: “For systems that boot from Local Bus

(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required...”

In addition, updated footnote 26 and added footnote 29 to PCI1_AD.

• Updated Table 21

• Updated Figure 25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.”

• In Table 44, “MII Management DC Electrical Characteristics,” changed the Voh/Vol values for

MDIO/MDC.

• Added Note 6 regarding USBn_DIR pin to Table 47, “USB General Timing Parameters6.”

• In Table 64, “I2C AC Electrical Specifications,” updated footnote 2.

• In Table 82, Table 83, Table 84, added the Revision Level A for Rev 1.2

2

09/2009 Note:

• In Section 1, “Pin Assignments and Reset States,”updated the first sentence of the note to say, “The

UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.”

• In Table 40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and

LSTSEF to LSTSE for Note 4.

Note: Updated Figure 81, “Mechanical Dimensions and Bottom Surface Nomenclature of the

FC-PBGA,” and its notes.

1

0

09/2009 • In Table 5, ”Power Dissipation 5,” changed an “—”’ to “0.”

08/2009 Initial public release.

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Freescale Semiconductor

125

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. Freescale does not convey any

license under its patent rights nor the rights of others. Freescale sells products pursuant

to standard terms and conditions of sale, which can be found at the following address:

freescale.com/SalesTermsandConditions.

Freescale, the Freescale logo, and PowerQUICC are trademarks of Freescale

Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are

the property of their respective owners. The Power Architecture and Power.org word

marks and the Power and Power.org logos and related marks are trademarks and

service marks licensed by Power.org.

Document Number: MPC8536EEC

Rev. 7

07/2015


型号：	MPC8536EBVJAVLA
厂家：	NXP
描述：	PowerQUICC, 32 Bit Power Arch SoC, 1.5GHz, DDR2/3, SDHC, PCI/PCIe,SATA,GbE,USB,SEC, 0 to 105C, Rev1 PC 双倍数据速率
文件：	总126页 (文件大小：2355K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC8536EBVJAVLA [NXP]

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