MPC8548EPXATJB_技术文档

Document Number: MPC8548EEC

Rev. 5, 10/2009

Freescale Semiconductor

Technical Data

MPC8548E PowerQUICC™ III

Integrated Processor

Hardware Specifications

Contents

1 Overview

This section provides a high-level overview of MPC8548E

features. Figure 1 shows the major functional units within

the MPC8548E.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 26

Although this document is written from the perspective of

the MPC8548E, most of the material applies to the other

family members—MPC8547E, MPC8545E, and

MPC8543E—as well. When specific differences occur, such

as pinout differences and processor frequency ranges, they

will be identified as such.

9. Ethernet Management Interface Electrical

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11. Programmable Interrupt Controller . . . . . . . . . . . . . 51

12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60

16. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

17. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 86

19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

21. System Design Information . . . . . . . . . . . . . . . . . . 127

22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 136

23. Document Revision History . . . . . . . . . . . . . . . . . . 139

For specific PVR and SVR numbers, refer to the MPC8548E

PowerQUICC™ III Integrated Processor Family Reference

Manual.

Overview

Security

Engine

DDR/DDR2/

Memory Controller

DDR

SDRAM

512-Kbyte

L2 Cache/

SRAM

Flash

SDRAM

GPIO

XOR

Engine

Local Bus Controller

e500 Core

Programmable Interrupt

Controller (PIC)

IRQs

e500

Coherency

Module

32-KbyteL1

32-Kbyte

L1 Data

Cache

Core Complex

Bus

Instruction

Cache

Serial

DUART

2

I C

2

I C

Controller

Serial RapidIO™

2

I C

2

or

4x RapidIO

x8 PCI Express

I C

Controller

PCI Express

MII, GMII, TBI,

RTBI, RGMII,

RMII

eTSEC

10/100/1Gb

eTSEC

OceaN

Switch

Fabric

PCI 32-bit

66 MHz

32-bit PCI Bus Interface

(If 64-bit not used)

MII, GMII, TBI,

RTBI, RGMII,

RMII

10/100/1Gb

eTSEC

32-bit PCI/

64-bit PCI/PCI-X

Bus Interface

PCI/PCI-X

133 MHz

MII, GMII, TBI,

RTBI, RGMII,

RMII

10/100/1Gb

eTSEC

4-Channel DMA

Controller

RTBI, RGMII,

RMII

10/100/1Gb

Figure 1. MPC8548E Block Diagram

1.1

Key Features

The following list provides an overview of the MPC8548E feature set:

High-performance 32-bit core built on Power Architecture™ technology.

•

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can

be locked entirely or on a per-line basis, with separate locking for instructions and data.

— Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive

instruction set for vector (64-bit) integer and fractional operations. These instructions use both

the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.

— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

— 36-bit real addressing

— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

— Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

— Enhanced hardware and software debug support

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

2

Freescale Semiconductor

Overview

— Performance monitor facility that is similar to, but separate from, the MPC8548E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some features

that this device implements more specifically. An understanding of these differences can be critical to

ensure proper operations.

•

512-Kbyte L2 cache/SRAM

— Flexible configuration.

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

— 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and Flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be Flash cleared separately.

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

•

Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

– Four inbound windows plus a default window on RapidIO™

– Four outbound windows plus default translation for PCI/PCI-X and PCI Express

– Eight outbound windows plus default translation for RapidIO with segmentation and

sub-segmentation support

•

DDR/DDR2 memory controller

— Programmable timing supporting DDR and DDR2 SDRAM

— 64-bit data interface

— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports

— Full ECC support

— Page mode support

– Up to 16 simultaneous open pages for DDR

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

3

Overview

– Up to 32 simultaneous open pages for DDR2

— Contiguous or discontiguous memory mapping

— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear

transactions

— Sleep mode support for self-refresh SDRAM

— On-die termination support when using DDR2

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access via JTAG port

— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)

— Support for battery-backed main memory

Programmable interrupt controller (PIC)

•

— Programming model is compliant with the OpenPIC architecture.

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

— Four global high resolution timers/counters that can generate interrupts

— Supports a variety of other internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing.

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.

— Interrupt summary registers allow fast identification of interrupt source.

•

Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,

IKE, WTLS/WAP, SSL/TLS, and 3GPP

— Four crypto-channels, each supporting multi-command descriptor chains

– Dynamic assignment of crypto-execution units via an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— PKEU—public key execution unit

– RSA and Diffie-Hellman; programmable field size up to 2048 bits

– Elliptic curve cryptography with F m and F(p) modes and programmable field size up to

2

511 bits

— DEU—Data Encryption Standard execution unit

– DES, 3DES

– Two key (K1, K2) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

4

Freescale Semiconductor

Overview

— AESU—Advanced Encryption Standard unit

– Implements the Rijndael symmetric key cipher

– ECB, CBC, CTR, and CCM modes

– 128-, 192-, and 256-bit key lengths

— AFEU—ARC four execution unit

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— MDEU—message digest execution unit

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— KEU—Kasumi execution unit

– Implements F8 algorithm for encryption and F9 algorithm for integrity checking

– Also supports A5/3 and GEA-3 algorithms

— RNG—random number generator

— XOR engine for parity checking in RAID storage applications

2

•

Dual I C controllers

— Two-wire interface

— Multiple master support

2

— Master or slave I C mode support

— On-chip digital filtering rejects spikes on the bus

Boot sequencer

2

— Optionally loads configuration data from serial ROM at reset via the I C interface

— Can be used to initialize configuration registers and/or memory

2

— Supports extended I C addressing mode

— Data integrity checked with preamble signature and CRC

DUART

•

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

Local bus controller (LBC)

— Multiplexed 32-bit address and data bus operating at up to 133 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

5

Overview

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)

Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

•

— Four controllers designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™, 802.3z™,

802.3ac™, and 802.3ab™

— Support for various Ethernet physical interfaces:

– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII

– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII

— Flexible configuration for multiple PHY interface configurations. See Section 8.1, “Enhanced

Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics,” for

more information.

— TCP/IP acceleration and QoS features available

– IP v4 and IP v6 header recognition on receive

– IP v4 header checksum verification and generation

– TCP and UDP checksum verification and generation

– Per-packet configurable acceleration

– Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2™, PPPoE session,

MPLS stacks, and ESP/AH IP-security headers

– Supported in all FIFO modes

— Quality of service support:

– Transmission from up to eight physical queues

– Reception to up to eight physical queues

— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):

– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or

software-programmed PAUSE frame generation and recognition)

— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and

IEEE Std. 802.1™ virtual local area network (VLAN) tags and priority

— VLAN insertion and deletion

– Per-frame VLAN control word or default VLAN for each eTSEC

– Extracted VLAN control word passed to software separately

— Retransmission following a collision

— CRC generation and verification of inbound/outbound frames

— Programmable Ethernet preamble insertion and extraction of up to 7 bytes

— MAC address recognition:

– Exact match on primary and virtual 48-bit unicast addresses

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

6

Freescale Semiconductor

Overview

– VRRP and HSRP support for seamless router fail-over

– Up to 16 exact-match MAC addresses supported

– Broadcast address (accept/reject)

– Hash table match on up to 512 multicast addresses

– Promiscuous mode

— Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet

programming models

— RMON statistics support

— 10-Kbyte internal transmit and 2-Kbyte receive FIFOs

— MII management interface for control and status

— Ability to force allocation of header information and buffer descriptors into L2 cache

OCeaN switch fabric

•

— Full crossbar packet switch

— Reorders packets from a source based on priorities

— Reorders packets to bypass blocked packets

— Implements starvation avoidance algorithms

— Supports packets with payloads of up to 256 bytes

Integrated DMA controller

— Four-channel controller

— All channels accessible by both the local and remote masters

— Extended DMA functions (advanced chaining and striding capability)

— Support for scatter and gather transfers

— Misaligned transfer capability

— Interrupt on completed segment, link, list, and error

— Supports transfers to or from any local memory or I/O port

— Selectable hardware-enforced coherency (snoop/no snoop)

— Ability to start and flow control each DMA channel from external 3-pin interface

— Ability to launch DMA from single write transaction

Two PCI/PCI-X controllers

•

— PCI 2.2 and PCI-X 1.0 compatible

— One 32-/64-bit PCI/PCI-X port with support for speeds of up to 133 MHz (maximum PCI-X

frequency in synchronous mode is 110 MHz)

— One 32-bit PCI port with support for speeds from 16 to 66 MHz (available when the other port

is in 32-bit mode)

— Host and agent mode support

— 64-bit dual address cycle (DAC) support

— PCI-X supports multiple split transactions

— Supports PCI-to-memory and memory-to-PCI streaming

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

7

Overview

— Memory prefetching of PCI read accesses

— Supports posting of processor-to-PCI and PCI-to-memory writes

— PCI 3.3-V compatible

— Selectable hardware-enforced coherency

•

Serial RapidIO™ interface unit

— Supports RapidIO™ Interconnect Specification, Revision 1.2

— Both 1x and 4x LP-serial link interfaces

— Long- and short-haul electricals with selectable pre-compensation

— Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane

— Auto detection of 1x- and 4x-mode operation during port initialization

— Link initialization and synchronization

— Large and small size transport information field support selectable at initialization time

— 34-bit addressing

— Up to 256 bytes data payload

— All transaction flows and priorities

— Atomic set/clr/inc/dec for read-modify-write operations

— Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at

a remote memory system

— Receiver-controlled flow control

— Error detection, recovery, and time-out for packets and control symbols as required by the

RapidIO specification

— Register and register bit extensions as described in part VIII (Error Management) of the

RapidIO specification

— Hardware recovery only

— Register support is not required for software-mediated error recovery.

— Accept-all mode of operation for fail-over support

— Support for RapidIO error injection

— Internal LP-serial and application interface-level loopback modes

— Memory and PHY BIST for at-speed production test

RapidIO-compatible message unit

•

— 4 Kbytes of payload per message

— Up to sixteen 256-byte segments per message

— Two inbound data message structures within the inbox

— Capable of receiving three letters at any mailbox

— Two outbound data message structures within the outbox

— Capable of sending three letters simultaneously

— Single segment multicast to up to 32 devIDs

— Chaining and direct modes in the outbox

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Freescale Semiconductor

Overview

— Single inbound doorbell message structure

— Facility to accept port-write messages

PCI Express interface

•

— PCI Express 1.0a compatible

— Supports x8, x4, x2, and x1 link widths

— Auto-detection of number of connected lanes

— Selectable operation as root complex or endpoint

— Both 32- and 64-bit addressing

— 256-byte maximum payload size

— Virtual channel 0 only

— Traffic class 0 only

— Full 64-bit decode with 32-bit wide windows

•

Pin multiplexing for the high speed I/O interfaces supports one of the following configurations:

— x8 PCI Express

— x4 PCI Express and 4x serial RapidIO

Power management

— Supports power saving modes: doze, nap, and sleep

— Employs dynamic power management, which automatically minimizes power consumption of

blocks when they are idle

•

System performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the eight counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

•

System access port

— Uses JTAG interface and a TAP controller to access entire system memory map

— Supports 32-bit accesses to configuration registers

— Supports cache-line burst accesses to main memory

— Supports large block (4-Kbyte) uploads and downloads

— Supports continuous bit streaming of entire block for fast upload and download

JTAG boundary scan, designed to comply with IEEE Std. 1149.1™

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

9

Electrical Characteristics

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8548E. This device is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

1

Table 1. Absolute Maximum Ratings

Characteristic

Symbol

Max Value

Unit

Notes

Core supply voltage

PLL supply voltage

V

–0.3 to 1.21

V

—

DD

AV

SV

XV

DD

Core power supply for SerDes transceivers

Pad power supply for SerDes transceivers

DDR and DDR2 DRAM I/O voltage

GV

–0.3 to 2.75

–0.3 to 1.98

DD

Three-speed Ethernet I/O voltage

LV (for eTSEC1

and eTSEC2)

–0.3 to 3.63

–0.3 to 2.75

V

3

DD

TV (for eTSEC3

–0.3 to 3.63

–0.3 to 2.75

DD

and eTSEC4)

PCI/PCI-X, DUART, system control and power management,

I C, Ethernet MII management, and JTAG I/O voltage

OV

–0.3 to 3.63

V

—

DD

2

Local bus I/O voltage

BV

–0.3 to 3.63

–0.3 to 2.75

Input voltage DDR/DDR2 DRAM signals

DDR/DDR2 DRAM reference

MV

–0.3 to (GV + 0.3)

V

4

IN

DD

MV

–0.3 to

—

REF

(GV /2 + 0.3)

DD

Three-speed Ethernet I/O signals

LV

–0.3 to (LV + 0.3)

V

4

IN

DD

TV

–0.3 to (TV + 0.3)

IN

DD

Local bus signals

BV

–0.3 to (BV + 0.3)

—

V

—

4

IN

DD

DUART, SYSCLK, system control and power

OV

–0.3 to (OV + 0.3)

DD

IN

2

management, I C, Ethernet MII management,

and JTAG signals

PCI/PCI-X

–0.3 to (OV + 0.3)

V

4

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

10

Electrical Characteristics

1

Table 1. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Max Value

–55 to 150

Unit

Notes

Storage temperature range

T

°C

—

STG

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.

3. The 3.63 V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75 V

maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on

the recommended operating conditions per protocol.

4. (M,L,O)V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

IN

2.1.2

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for this device. Note that the values in Table 2 are

the recommended and tested operating conditions. Proper device operation outside these conditions is not

guaranteed.

Table 2. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit

Notes

Value

Core supply voltage

PLL supply voltage

V

1.1 V 55 mV

V

—

1

DD

AV

SV

XV

DD

Core power supply for SerDes transceivers

Pad power supply for SerDes transceivers

DDR and DDR2 DRAM I/O voltage

—

GV

2.5 V 125 mV

1.8 V 90 mV

DD

Three-speed Ethernet I/O voltage

LV

3.3 V 165 mV

2.5 V 125 mV

V

4

DD

—

TV

OV

BV

3.3 V 165 mV

2.5 V 125 mV

DD

2

PCI/PCI-X, DUART, system control and power management, I C,

Ethernet MII management, and JTAG I/O voltage

3.3 V 165 mV

V

3

Local bus I/O voltage

3.3 V 165 mV

2.5 V 125 mV

—

Input voltage

DDR and DDR2 DRAM signals

DDR and DDR2 DRAM reference

Three-speed Ethernet signals

MV

GND to GV

V

2

4

IN

DD

MV

GND to GV /2

DD

REF

LV

GND to LV

DD

IN

TV

GND to TV

IN

DD

Local bus signals

BV

GND to BV

V

—

3

IN

DD

PCI, DUART, SYSCLK, system control and power

OV

GND to OV

DD

IN

2

management, I C, Ethernet MII management, and

JTAG signals

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

11

Electrical Characteristics

Table 2. Recommended Operating Conditions (continued)

Recommended

Value

Characteristic

Symbol

Unit

Notes

Junction temperature range

Tj

0 to 105

°C

—

Notes:

1. This voltage is the input to the filter discussed in Section 21.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AV pin, which may be reduced from V by the filter.

DD

2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

IN

DD

power-on reset and power-down sequences.

3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

IN

DD

power-on reset and power-down sequences.

4. Caution: L/TV must not exceed L/TV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

IN

DD

power-on reset and power-down sequences.

Figure 2 shows the undershoot and overshoot voltages at the interfaces of this device.

B/G/L/O/TV + 20%

DD

B/G/L/O/TV + 5%

DD

B/G/L/O/TV

V

DD

IH

GND

GND – 0.3 V

V

IL

GND – 0.7 V

Not to Exceed 10%

1

of t

CLOCK

Notes:

1. t

refers to the clock period associated with the respective interface:

CLOCK

2

For I C and JTAG, t

For DDR, t

references SYSCLK.

CLOCK

references MCLK.

CLOCK

For eTSEC, t

references EC_GTX_CLK125.

For LBIU, t

CLOCK

For SerDes, t

references LCLK.

CLOCK

For PCI, t

references PCIn_CLK or SYSCLK.

references SD_REF_CLK.

CLOCK

2. Please note that with the PCI overshoot allowed (as specified above), the device

does not fully comply with the maximum AC ratings and device protection

guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).

Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV /BV /TV

DD

The core voltage must always be provided at nominal 1.1 V. Voltage to the processor interface I/Os are

provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The

input voltage threshold scales with respect to the associated I/O supply voltage. OV and LV based

DD

receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR

SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV

REF

signal (nominally set to GV /2) as is appropriate for the SSTL2 electrical signaling standard.

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

12

Freescale Semiconductor

Electrical Characteristics

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 3. Output Drive Capability

Programmable

Supply

Driver Type

Output Impedance

Notes

Voltage

(Ω)

Local bus interface utilities signals

25

BV = 3.3 V

1

DD

BV = 2.5 V

DD

45(default)

BV = 3.3 V

DD

BV = 2.5 V

DD

PCI signals

25

OV = 3.3 V

2

DD

45(default)

DDR signal

18

GV = 2.5 V

3

DD

36 (half strength mode)

DDR2 signal

18

GV = 1.8 V

DD

36 (half strength mode)

TSEC/10/100 signals

45

L/TV = 2.5/3.3 V

—

DD

DUART, system control, JTAG

OV = 3.3 V

DD

I2C

150

OV = 3.3 V

DD

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.

3. The drive strength of the DDR interface in half-strength mode is at T = 105°C and at GV (min).

j

DD

2.2

Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. These requirements are as follows for power-up:

1. V , AV _n, BV , LV , OV , SV , TV , XV

DD

2. GV

DD

All supplies must be at their stable values within 50 ms.

NOTE

Items on the same line have no ordering requirement with respect to one

another. Items on separate lines must be ordered sequentially such that

voltage rails on a previous step must reach 90% of their value before the

voltage rails on the current step reach 10% of theirs.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

13

Power Characteristics

NOTE

In order to guarantee MCKE low during power-up, the above sequencing for

GV is required. If there is no concern about any of the DDR signals being

DD

in an indeterminate state during power-up, then the sequencing for GV is

DD

not required.

NOTE

From a system standpoint, if any of the I/O power supplies ramp prior to the

V

core supply, the I/Os associated with that I/O supply may drive a logic

DD

one or zero during power-up, and extra current may be drawn by the device.

3 Power Characteristics

The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this

family of PowerQUICC III devices is shown in Table 4.

Table 4. MPC8548E Power Dissipation

1

2

3

4

5

CCB Frequency

Core Frequency

SLEEP

Typical-65

Typical-105

Maximum

Unit

400

800

1000

1200

1500

1333

2.7

4.6

5.0

7.5

7.9

8.1

8.5

W

2.7

5.4

8.3

8.9

500

533

11.5

6.2

13.6

7.9

16.5

10.8

18.6

12.8

W

Notes:

1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.

2. SLEEP is based on V = 1.1 V, T = 65°C.

DD

j

3. Typical-65 is based on V = 1.1 V, T = 65°C, running Dhrystone.

DD

j

4. Typical-105 is based on V = 1.1 V, T = 105°C, running Dhrystone.

DD

j

5. Maximum is based on V = 1.1 V, T = 105°C, running a smoke test.

DD

j

4 Input Clocks

4.1

System Clock Timing

Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8548E.

Table 5. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV = 3.3 V 165 mV.

DD

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

SYSCLK frequency

SYSCLK cycle time

f

t

16

—

133

60

MHz

ns

1, 6, 7, 8

6, 7, 8

SYSCLK

7.5

SYSCLK

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

14

Input Clocks

Notes

Table 5. SYSCLK AC Timing Specifications (continued)

At recommended operating conditions (see Table 2) with OV = 3.3 V 165 mV.

DD

Parameter/Condition

SYSCLK rise and fall time

Symbol

, t

Min

Typ

Max

Unit

t

0.6

40

—

1.0

—

1.2

60

ns

%

2

3

KH KL

SYSCLK duty cycle

SYSCLK jitter

Notes:

t

/t

KHK SYSCLK

—

150

ps

4, 5

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies.Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.

7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on

SYSCLK.

8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum..

4.2

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter

specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2 × t

, and minimum clock low time is 2 × t

. There is

CCB

no minimum RTC frequency; RTC may be grounded if not needed.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

15

Input Clocks

4.3

eTSEC Gigabit Reference Clock Timing

Table 6 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for

the MPC8548E.

Table 6. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

EC_GTX_CLK125 frequency

Symbol

Min

Typ

Max

Unit

Notes

f

t

—

125

8

—

MHz

ns

—

G125

EC_GTX_CLK125 cycle time

EC_GTX_CLK125 rise and fall time

t

, t

—

ns

1

G125R G125F

L/TVDD = 2.5 V

L/TVDD = 3.3 V

0.75

1.0

EC_GTX_CLK125 duty cycle

t

/t

—

%

2, 3

G125H G125

GMII, TBI

1000Base-T for RGMII, RTBI

45

47

55

53

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TV = 2.5 V, and from 0.6 and 2.7 V for

DD

L/TV = 3.3 V.

DD

2. Timing is guaranteed by design and characterization.

3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation.

EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated

by the TSECn_ GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and

100Base-T reference clock.

4.4

PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the

PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. Table 7 provides the

PCI/PCI-X reference clock AC timing specifications for the MPC8548E.

Table 7. PCIn_CLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV = 3.3 V 165 mV.

DD

Parameter/Condition

PCIn_CLK frequency

Symbol

Min

Typ

Max

Unit

Notes

f

t

16

7.5

0.6

40

—

133

60

MHz

ns

—

PCICLK

PCIn_CLK cycle time

PCIn_CLK rise and fall time

PCIn_CLK duty cycle

Notes:

PCICLK

t

, t

1.0

—

2.1

60

ns

1, 2

2

PCIKH PCIKL

t

/t

%

PCIKHKL PCICLK

1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

2. Timing is guaranteed by design and characterization.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

16

Input Clocks

4.5

Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency <= platform clock frequency/4.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more

than 127 MHz

For FIFO encoded mode:

FIFO TX/RX clock frequency <= platform clock frequency/4.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more

than 167 MHz.

4.6

Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The CCB clock frequency must be considered for proper operation of the high-speed PCI-Express and

Serial RapidIO interfaces as described below.

For proper PCI Express operation, the CCB clock frequency must be greater than:

527 MHz × (PCI-Express link width)

8

See MPC8548ERM, Rev. 2, PowerQUICC™ III Integrated Processor Family Reference Manual,

Section 18.1.3.2, “Link Width,” for PCI Express interface width details.

For proper serial RapidIO operation, the CCB clock frequency must be greater than:

2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)

64

See MPC8548ERM, Rev. 2, PowerQUICC™ III Integrated Processor Family Reference Manual,

Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency

details.

4.7

Other Input Clocks

For information on the input clocks of other functional blocks of the platform see the specific section of

this document.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

17

RESET Initialization

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8548E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM

component(s).

Table 8. RESET Initialization Timing Specifications

Parameter/Condition

Required assertion time of HRESET

Min

Max

Unit

Notes

100

3

—

μs

—

1

Minimum assertion time for SRESET

SYSCLKs

μs

PLL input setup time with stable SYSCLK before HRESET negation

100

4

—

1

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

2

—

5

SYSCLKs

1

Maximum valid-to-high impedance time for actively driven POR configs with

respect to negation of HRESET

—

Note:

1. SYSCLK is the primary clock input for the MPC8548E.

Table 9 provides the PLL lock times.

Table 9. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Core and platform PLL lock times

Local bus PLL lock time

—

100

50

μs

PCI/PCI-X bus PLL lock time

50

5.1

Power-On Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Table 10

provides the power supply ramp rate specifications.

Table 10. Power Supply Ramp Rate

Parameter

Required ramp rate for MVREF

Min

Max

Unit

Notes

—

545

Volts/Sec

1

Required ramp rate for VDD/XVDD/SVDD

Note:

1. Ramp rate is specified as a linear ramp. If non-linear (e.g. exponential), ramp rate from near zero to 400 mV is most critical

as this range might falsely trigger the ESD circuitry.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

18

Freescale Semiconductor

DDR and DDR2 SDRAM

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8548E. Note that GV (typ) = 2.5 V for DDR SDRAM, and GV (typ) = 1.8 V for DDR2

DD

SDRAM.

6.1

DDR SDRAM DC Electrical Characteristics

Table 11 provides the recommended operating conditions for the DDR2 SDRAM controller of the

MPC8548E when GV (typ) = 1.8 V.

DD

Table 11. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Max

Parameter/Condition

I/O supply voltage

Symbol

Min

Unit

Notes

GV

MV

1.71

1.89

V

1

2

DD

I/O reference voltage

I/O termination voltage

Input high voltage

0.49 × GV

0.51 × GV

DD

REF

TT

DD

V

MV

– 0.04

MV

+ 0.04

REF

V

3

REF

V

MV

+ 0.125

GV + 0.3

V

—

4

IH

DD

Input low voltage

V

I

–0.3

MV

– 0.125

REF

V

IL

Output leakage current

–50

–13.4

13.4

50

μA

mA

OZ

OH

Output high current (V

= 1.420 V)

I

—

OUT

Output low current (V

= 0.280 V)

I

OL

OUT

Notes:

1. GV is expected to be within 50 mV of the DRAM V at all times.

DD

2. MV

is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak

REF

DD DD

may not exceed 2% of the DC value.

noise on MV

REF

3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV

. This rail should track variations in the DC level of MV

.

REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV

.

DD

Table 12 provides the DDR2 I/O capacitance when GV (typ) = 1.8 V.

DD

Table 12. DDR2 SDRAM Capacitance for GV (typ)=1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C

6

8

pF

1

IO

C

—

0.5

DIO

1. This parameter is sampled. GV = 1.8 V 0.090 V, f = 1 MHz, T = 25°C, V

= GV /2, V

(peak-to-peak) = 0.2 V.

DD

A

OUT

DD

OUT

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

19

DDR and DDR2 SDRAM

Table 13 provides the recommended operating conditions for the DDR SDRAM controller when

GV (typ) = 2.5 V.

DD

Table 13. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Notes

GV

MV

2.375

2.625

V

1

2

DD

I/O reference voltage

I/O termination voltage

Input high voltage

0.49 × GV

0.51 × GV

DD

REF

TT

DD

V

MV

– 0.04

+ 0.15

MV

+ 0.04

REF

V

3

REF

V

MV

GV + 0.3

V

—

4

IH

DD

Input low voltage

V

I

–0.3

MV

– 0.15

REF

V

IL

Output leakage current

–50

–16.2

16.2

50

μA

mA

OZ

OH

Output high current (V

= 1.95 V)

I

—

OUT

Output low current (V

= 0.35 V)

I

OL

OUT

Notes:

1. GV is expected to be within 50 mV of the DRAM V at all times.

DD

2. MV

is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak

REF

DD DD

may not exceed 2% of the DC value.

noise on MV

REF

3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV

. This rail should track variations in the DC level of MV

.

REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV

.

DD

Table 14 provides the DDR I/O capacitance when GV (typ) = 2.5 V.

DD

Table 14. DDR SDRAM Capacitance for GV (typ) = 2.5 V

DD

Parameter/Condition

Input/output capacitance: DQ, DQS

Symbol

Min

Max

Unit

Notes

C

6

8

pF

1

IO

Delta input/output capacitance: DQ, DQS

C

—

0.5

DIO

Note:

1. This parameter is sampled. GV = 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V

= GV /2, V

(peak-to-peak) = 0.2 V.

DD

A

OUT

DD

OUT

Table 15 provides the current draw characteristics for MV

.

REF

Table 15. Current Draw Characteristics for MV

REF

Parameter/Condition

Current draw for MV

Symbol

Min

Max

Unit

Notes

I

—

500

μA

1

REF

MVREF

Note:

1. The voltage regulator for MV

must be able to supply up to 500 μA current.

REF

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

20

DDR and DDR2 SDRAM

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR

controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings

at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to

333 MHz.

6.2.1

DDR SDRAM Input AC Timing Specifications

Table 16 provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 1.8 V.

DD

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions

Parameter

Symbol

Min

Max

– 0.25

REF

Unit

AC input low voltage

AC input high voltage

V

—

MV

V

IL

V

MV

+ 0.25

REF

—

IH

Table 17 provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 2.5 V.

DD

Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions.

Parameter

Symbol

Min

Max

– 0.31

REF

Unit

AC input low voltage

AC input high voltage

V

—

MV

V

IL

V

MV

+ 0.31

REF

—

IH

Table 18 provides the input AC timing specifications for the DDR SDRAM interface.

Table 18. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

t

ps

1, 2

CISKEW

533 MHz

400 MHz

333 MHz

–300

–365

–390

300

365

390

Notes:

1. t

represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

CISKEW

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t

. This can be

DISKEW

determined by the following equation: t

=

(T/4 – abs(t

)) where T is the clock period and abs(t

) is the

DISKEW

CISKEW

absolute value of t

.

CISKEW

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

21

DDR and DDR2 SDRAM

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 19. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

1

Parameter

Symbol

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

t

3.75

6

ns

2

3

MCK

ADDR/CMD output setup with respect to MCK

t

DDKHAS

DDKHAX

DDKHCS

DDKHCX

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

ADDR/CMD output hold with respect to MCK

ns

3

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output setup with respect to MCK

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output hold with respect to MCK

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCK to MDQS Skew

t

–0.6

0.6

ns

ps

4

5

DDKHMH

MDQ/MECC/MDM output setup with respect

t

DDKHDS,

t

DDKLDS

to MDQS

533 MHz

400 MHz

333 MHz

538

700

900

—

MDQ/MECC/MDM output hold with respect to

MDQS

ps

ns

5

6

DDKHDX,

t

DDKLDX

533 MHz

400 MHz

333 MHz

538

700

900

—

MDQS preamble start

–0.5 × t

– 0.6

–0.5 × t

+ 0.6

MCK

DDKHMP

MCK

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

22

DDR and DDR2 SDRAM

Table 19. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions.

1

Parameter

Symbol

Min

Max

Unit

Notes

MDQS epilogue end

Notes:

1. The symbols used for timing specifications follow the pattern of t

t

–0.6

0.6

ns

6

DDKHME

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. Output hold time can be read as DDR timing

(first two letters of functional block)(reference)(state)(signal)(state)

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until outputs

t

DDKHAS

MCK

(A) are setup (S) or output valid time. Also, t

symbolizes DDR timing (DD) for the time t

memory clock reference

DDKLDX

MCK

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that t follows the symbol conventions described in note 1. For example, t describes the DDR timing (DD)

DDKHMH

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t

can be modified through control

DDKHMH

of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same

delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2

parameters have been set to the same adjustment value. See the MPC8548E PowerQUICC™ III Integrated Processor

Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t

symbol conventions described in note 1.

follows the

DDKHMP

NOTE

For the ADDR/CMD setup and hold specifications in Table 19, it is

assumed that the clock control register is set to adjust the memory clocks by

1/2 applied cycle.

Figure 3 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t

).

DDKHMH

MCK[n]

t

MCK

t

= 0.6 ns

DDKHMHmax)

MDQS

t

= –0.6 ns

DDKHMH(min)

Figure 3. Timing Diagram for tDDKHMH

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

23

DDR and DDR2 SDRAM

Figure 4 shows the DDR SDRAM output timing diagram.+

MCK[n]

t_MCK

t_DDKHAS, t

DDKHCS

t_DDKHAX, t

DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 4. DDR SDRAM Output Timing Diagram

Figure 5 provides the AC test load for the DDR bus.

Output

GV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 5. DDR AC Test Load

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

24

DUART

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the

MPC8548E.

7.1

DUART DC Electrical Characteristics

Table 20 provides the DC electrical characteristics for the DUART interface.

Table 20. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

V

2

–0.3

—

OV + 0.3

V

IH

DD

Low-level input voltage

V

I

0.8

5

IL

1

Input current (V

= 0 V or V = V

μA

V

IN

DD)

IN

High-level output voltage (OV = min, I = –2 mA)

V

OH

2.4

—

0.4

DD

OH

Low-level output voltage (OV = min, I = 2 mA)

V

OL

V

DD

OL

Note:

1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.

IN

7.2

DUART AC Electrical Specifications

Table 21 provides the AC timing parameters for the DUART interface.

Table 21. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

Maximum baud rate

Oversample rate

f

/1,048,576

baud

—

1, 2

1, 2, 3

1, 4

CCB

f

/16

CCB

16

Notes:

1. Guaranteed by design.

2. f

refers to the internal platform clock.

CCB

3. Actual attainable baud rate will be limited by the latency of interrupt processing.

th

4. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

th

sampled each 16 sample.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

25

Enhanced Three-Speed Ethernet (eTSEC)

8 Enhanced Three-Speed Ethernet (eTSEC)

This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet

controller. The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet

Management Interface Electrical Characteristics.”

8.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical

Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media

independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI

interfaces are defined for 2.5 V, while the GMII, MII, and TBI interfaces can be operated at 3.3 or 2.5 V.

The GMII, MII, or TBI interface timing is compliant with the IEEE 802.3. The RGMII and RTBI interfaces

follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3

(12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2

(3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet

Management Interface Electrical Characteristics.”

8.1.1

eTSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII, and RTBI drivers and receivers comply with the DC parametric

attributes specified in Table 22 and Table 23. The RGMII and RTBI signals are based on a 2.5-V CMOS

interface voltage as defined by JEDEC EIA/JESD8-5.

Table 22. GMII, MII, RMII, and TBI DC Electrical Characteristics

Parameter

Symbol

LV

Min

Max

Unit

Notes

Supply voltage 3.3 V

3.13

3.47

V

1, 2

DD

TV

DD

Output high voltage (LV /TV = min, I = –4.0 mA)

V

2.40

GND

2.0

LV /TV + 0.3

V

—

DD

OH

DD

Output low voltage (LV /TV = min, I = 4.0 mA)

V

0.50

DD

OL

Input high voltage

Input low voltage

V

LV /TV + 0.3

V

—

IH

DD

V

I

–0.3

—

0.90

V

—

IL

Input high current (V = LV , V = TV

)

40

—

μA

1, 2, 3

—

IN

DD IN

DD

IH

Input low current (V = GND)

I

–600

IN

IL

Notes:

1. LV supports eTSECs 1 and 2.

DD

2. TV supports eTSECs 3 and 4.

DD

3. The symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.

IN

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

26

Enhanced Three-Speed Ethernet (eTSEC)

Table 23. GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical Characteristics

Parameters

Supply voltage 2.5 V

Output high voltage (LV /TV = Min,

Symbol

LV /TV

Min

Max

Unit

Notes

2.37

2.00

2.63

V

1, 2

—

DD

V

LV /TV + 0.3

DD DD

DD

OH

I

= –1.0 mA)

OH

Output low voltage (LV /TV = Min,

V

OL

GND –0.3

0.40

V

—

DD

I

= 1.0 mA)

OL

Input high voltage

Input low voltage

V

1.70

–0.3

—

LV /TV + 0.3

V

—

IH

DD

V

I

0.90

IL

Input high current (V = LV , V = TV

)

10

—

μA

1, 2, 3

3

IN

DD IN

DD

IH

Input low current (V = GND)

I

–15

IN

IL

Notes:

1. LV supports eTSECs 1 and 2.

DD

2. TV supports eTSECs 3 and 4.

DD

3. Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.

IN

8.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this

section.

8.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performances and are described in a source-synchronous fashion

like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is

relationship between the maximum FIFO speed and the platform speed. For more information see

Section 4.5, “Platform to FIFO Restrictions.”

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

27

Enhanced Three-Speed Ethernet (eTSEC)

A summary of the FIFO AC specifications appears in Table 24 and Table 25.

Table 24. FIFO Mode Transmit AC Timing Specification

Parameter/Condition

TX_CLK, GTX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

5.3

45

—

8.0

50

—

100

55

ns

%

FIT

TX_CLK, GTX_CLK duty cycle

t

/t

FITH FIT

TX_CLK, GTX_CLK peak-to-peak jitter

Rise time TX_CLK (20%–80%)

t

250

0.75

—

ps

ns

FITJ

t

—

FITR

Fall time TX_CLK (80%–20%)

t

—

FITF

FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time

t

2.0

0.5

FITDV

FITDX

t

3.0

Table 25. FIFO Mode Receive AC Timing Specification

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period

RX_CLK duty cycle

t

5.3

45

—

8.0

50

—

100

55

ns

%

FIR

t

/t

FIRH FIR

RX_CLK peak-to-peak jitter

t

250

0.75

—

ps

ns

FIRJ

Rise time RX_CLK (20%–80%)

Fall time RX_CLK (80%–20%)

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

Note:

t

—

FIRR

t

—

FIRF

t

1.5

0.5

FIRDV

t

—

FIRDX

1. The minimum cycle period of the TX_CLK and RX_CLK is dependent on the maximum platform frequency of t he speed bins

the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to FIFO Restrictions.”

Timing diagrams for FIFO appear in Figure 6 and Figure 7.

t

FITR

FIT

FITF

GTX_CLK

t

FITH

t

FITDX

FITDV

TXD[7:0]

TX_EN

TX_ER

Figure 6. FIFO Transmit AC Timing Diagram

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

28

Enhanced Three-Speed Ethernet (eTSEC)

t

FIRR

FIR

RX_CLK

t

FIRF

FIRH

RXD[7:0]

RX_DV

RX_ER

Valid Data

t

FIRDX

FIRDV

Figure 7. FIFO Receive AC Timing Diagram

8.2.2

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1

GMII Transmit AC Timing Specifications

Table 26 provides the GMII transmit AC timing specifications.

Table 26. GMII Transmit AC Timing Specifications

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

GMII data TXD[7:0], TX_ER, TX_EN setup time

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK data clock rise time (20%–80%)

t

2.5

0.5

—

ns

GTKHDV

t

5.0

1.0

GTKHDX

2

t

GTXR

2

GTX_CLK data clock fall time (80%–20%)

t

—

GTXF

Notes:

1. The symbols used for timing specifications follow the pattern t

for inputs

(first two letters of functional block)(signal)(state)(reference)(state)

and t

for outputs. For example, t

symbolizes GMII transmit timing

(first two letters of functional block)(reference)(state)(signal)(state)

GTKHDV

(GT) with respect to the t

clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching

GTX

the valid state (V) to state or setup time. Also, t

symbolizes GMII transmit timing (GT) with respect to the t

clock

GTKHDX

GTX

reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of t

represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is

GTX

used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

29

Enhanced Three-Speed Ethernet (eTSEC)

Figure 8 shows the GMII transmit AC timing diagram.

t

GTXR

GTX

GTX_CLK

t

GTXF

GTXH

TXD[7:0]

TX_EN

TX_ER

t

GTKHDX

t

GTKHDV

Figure 8. GMII Transmit AC Timing Diagram

8.2.2.2

GMII Receive AC Timing Specifications

Table 27 provides the GMII receive AC timing specifications.

Table 27. GMII Receive AC Timing Specifications

1

Parameter/Condition

RX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

—

35

2.0

0

8.0

—

75

—

ns

GRX

RX_CLK duty cycle

t

/t

GRXH GRX

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20%-80%)

RX_CLK clock fall time (80%-20%)

Notes:

t

GRDVKH

t

—

GRDXKH

2

t

—

1.0

GRXR

2

t

GRXF

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes GMII receive

(first two letters of functional block)(reference)(state)(signal)(state)

GRDVKH

timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock reference (K)

RX

going to the high state (H) or setup time. Also, t

input signals (D) went invalid (X) relative to the t

symbolizes GMII receive timing (GR) with respect to the time data

clock reference (K) going to the low (L) state or hold time. Note that, in

GRDXKL

GRX

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention

GRX

is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 9 provides the AC test load for eTSEC.

Output

LV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 9. eTSEC AC Test Load

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

30

Enhanced Three-Speed Ethernet (eTSEC)

Figure 10 shows the GMII receive AC timing diagram.

t

GRXR

GRX

RX_CLK

t

GRXF

GRXH

RXD[7:0]

RX_DV

RX_ER

t

GRDXKH

t

GRDVKH

Figure 10. GMII Receive AC Timing Diagram

8.2.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.3.1

MII Transmit AC Timing Specifications

Table 28 provides the MII transmit AC timing specifications.

Table 28. MII Transmit AC Timing Specifications

1

Parameter/Condition

TX_CLK clock period 10 Mbps

Symbol

Min

Typ

Max

Unit

2

t

—

400

40

—

5

—

ns

%

MTX

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t

MTX

t

35

1

65

15

4.0

MTXH/ MTX

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise (20%–80%)

TX_CLK data clock fall (80%–20%)

Notes:

t

ns

MTKHDX

2

t

1.0

—

MTXR

2

t

MTXF

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes MII transmit

(first two letters of functional block)(reference)(state)(signal)(state)

MTKHDX

timing (MT) for the time t

clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

MTX

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

MTX

used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

31

Enhanced Three-Speed Ethernet (eTSEC)

Figure 11 shows the MII transmit AC timing diagram.

t

MTXR

MTX

TX_CLK

t

MTXF

MTXH

TXD[3:0]

TX_EN

TX_ER

t

MTKHDX

Figure 11. MII Transmit AC Timing Diagram

8.2.3.2

MII Receive AC Timing Specifications

Table 29 provides the MII receive AC timing specifications.

Table 29. MII Receive AC Timing Specifications

1

Parameter/Condition

RX_CLK clock period 10 Mbps

Symbol

Min

Typ

Max

Unit

2

t

—

400

40

—

ns

%

MRX

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t

MRX

t

/t

35

65

—

MRXH MRX

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20%–80%)

RX_CLK clock fall time (80%–20%)

Notes:

t

10.0

1.0

—

ns

MRDVKH

t

—

MRDXKH

2

t

—

4.0

MRXR

2

t

—

MRXF

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes MII receive

(first two letters of functional block)(reference)(state)(signal)(state)

MRDVKH

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

clock reference (K)

MRX

going to the high (H) state or setup time. Also, t

symbolizes MII receive timing (GR) with respect to the time data input

MRDXKL

signals (D) went invalid (X) relative to the t

clock reference (K) going to the low (L) state or hold time. Note that, in general,

MRX

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

MRX

with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 12 provides the AC test load for eTSEC.

Output

LV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 12. eTSEC AC Test Load

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

32

Enhanced Three-Speed Ethernet (eTSEC)

Figure 13 shows the MII receive AC timing diagram.

t

MRX

MRXR

RX_CLK

t

MRXF

MRXH

RXD[3:0]

RX_DV

RX_ER

Valid Data

t

MRDVKH

t

MRDXKL

Figure 13. MII Receive AC Timing Diagram

8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1

TBI Transmit AC Timing Specifications

Table 30 provides the TBI transmit AC timing specifications.

Table 30. TBI Transmit AC Timing Specifications

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

TCG[9:0] setup time GTX_CLK going high

TCG[9:0] hold time from GTX_CLK going high

GTX_CLK rise (20%–80%)

t

2.0

1.0

—

ns

TTKHDV

t

TTKHDX

2

t

1.0

TTXR

2

GTX_CLK fall time (80%–20%)

t

—

TTXF

Notes:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state )(reference)(state)

inputs and t

for outputs. For example, t

symbolizes the TBI

(first two letters of functional block)(reference)(state)(signal)(state)

TTKHDV

transmit timing (TT) with respect to the time from t

(K) going high (H) until the referenced data signals (D) reach the valid

TTX

state (V) or setup time. Also, t

symbolizes the TBI transmit timing (TT) with respect to the time from t

(K) going high

TTKHDX

TTX

(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript

of t

represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

TTX

letter: R (rise) or F (fall).

2. Guaranteed by design.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

33

Enhanced Three-Speed Ethernet (eTSEC)

Figure 14 shows the TBI transmit AC timing diagram.

t

TTX

TTXR

GTX_CLK

TCG[9:0]

t

TTXH

t

TTXF

t

TTXF

t

TTXR

TTKHDV

t

TTKHDX

Figure 14. TBI Transmit AC Timing Diagram

8.2.4.2

TBI Receive AC Timing Specifications

Table 31 provides the TBI receive AC timing specifications.

Table 31. TBI Receive AC Timing Specifications

1

Parameter/Condition

TSECn_RX_CLK[0:1] clock period

Symbol

Min

Typ

Max

Unit

t

—

16.0

—

8.5

60

—

ns

%

TRX

TSECn_RX_CLK[0:1] skew

t

7.5

40

SKTRX

TSECn_RX_CLK[0:1] duty cycle

t

/t

—

TRXH TRX

RCG[9:0] setup time to rising TSECn_RX_CLK

RCG[9:0] hold time to rising TSECn_RX_CLK

TSECn_RX_CLK[0:1] clock rise time (20%–80%)

TSECn_RX_CLK[0:1] clock fall time (80%–20%)

Notes:

t

2.5

1.5

0.7

—

ns

TRDVKH

—

TRDXKH

2

t

—

2.4

TRXR

2

t

—

TRXF

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes TBI receive

(first two letters of functional block)(reference)(state)(signal)(state)

TRDVKH

timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

clock reference (K)

TRX

going to the high (H) state or setup time. Also, t

symbolizes TBI receive timing (TR) with respect to the time data input

TRDXKH

signals (D) went invalid (X) relative to the t

clock reference (K) going to the high (H) state. Note that, in general, the clock

TRX

reference symbol representation is based on three letters representing the clock of a particular functional. For example, the

subscript of t represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the

TRX

appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that

is being skewed (TRX).

2. Guaranteed by design.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

34

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC)

Figure 15 shows the TBI receive AC timing diagram.

t

TRXR

TRX

TSECn_RX_CLK1

t

TRXH

TRXF

RCG[9:0]

Valid Data

t

TRDVKH

t

SKTRX

TRDXKH

TSECn_RX_CLK0

t

TRDXKH

TRXH

t

TRDVKH

Figure 15. TBI Receive AC Timing Diagram

8.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock

is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,

whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied

on the TSEC_GTX_CLK125 pin in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 32.

Table 32. TBI single-clock Mode Receive AC Timing Specification

Parameter/Condition

RX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

7.5

40

—

8.0

50

—

8.5

60

ns

%

TRRX

t

TRRH/TRRX

RX_CLK duty cycle

RX_CLK peak-to-peak jitter

t

250

1.0

—

ps

ns

TRRJ

Rise time RX_CLK (20%–80%)

Fall time RX_CLK (80%–20%)

RCG[9:0] setup time to RX_CLK rising edge

RCG[9:0] hold time to RX_CLK rising edge

t

—

TRRR

t

—

TRRF

t

2.0

1.0

TRRDVKH

TRRDXKH

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

35

Enhanced Three-Speed Ethernet (eTSEC)

A timing diagram for TBI receive appears in Figure 16.

.

t

TRRX

TRRR

RX_CLK

t

TRRF

TRRH

Valid Data

RCG[9:0]

t

TRRDXKH

TRRDVKH

Figure 16. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6

RGMII and RTBI AC Timing Specifications

Table 33 presents the RGMII and RTBI AC timing specifications.

Table 33. RGMII and RTBI AC Timing Specifications

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

5

6

Data to clock output skew (at transmitter)

t

–500

1.0

7.2

45

0

—

8.0

50

—

500

ps

ns

%

SKRGT

2

Data to clock input skew (at receiver)

t

2.8

8.8

SKRGT

5

3

Clock period

t

RGT

3, 4

5

Duty cycle for 10BASE-T and 100BASE-TX

Rise time (20%–80%)

Fall time (20%–80%)

t

/t

55

RGTH RGT

5

t

—

0.75

ns

RGTR

5

t

—

RGTF

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and

RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note also that the notation for rise

RGT

(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, t

scales to 400 ns 40 ns and 40 ns 4 ns, respectively.

RGT

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three t

of the lowest speed transitioned

RGT

between.

5. Guaranteed by characterization.

6. In rev 1.0 silicon, due to errata, t

document.

is -650 ps (min) and 650 ps (max). Please refer to “eTSEC 10” in the device errata

SKRGT

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

36

Enhanced Three-Speed Ethernet (eTSEC)

Figure 17 shows the RGMII and RTBI AC timing and multiplexing diagrams.

t

RGT

t

RGTH

GTX_CLK

(At Transmitter)

t

SKRGT

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t

SKRGT

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t

SKRGT

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t

SKRGT

RX_CLK

(At PHY)

Figure 17. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.2.7

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.7.1

RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 34.

Table 34. RMII Transmit AC Timing Specifications

1

Parameter/Condition

TSECn_TX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

15.0

35

20.0

50

—

25.0

65

ns

%

RMT

TSECn_TX_CLK duty cycle

t

RMTH

TSECn_TX_CLK peak-to-peak jitter

Rise time TSECn_TX_CLK (20%–80%)

Fall time TSECn_TX_CLK (80%–20%)

t

—

250

2.0

ps

ns

RMTJ

RMTR

t

1.0

—

t

—

RMTF

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

37

Enhanced Three-Speed Ethernet (eTSEC)

Table 34. RMII Transmit AC Timing Specifications (continued)

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay

t

1.0

—

10.0

ns

RMTDX

Note:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes MII transmit

(first two letters of functional block)(reference)(state)(signal)(state)

MTKHDX

timing (MT) for the time t

clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

MTX

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

MTX

used with the appropriate letter: R (rise) or F (fall).

Figure 18 shows the RMII transmit AC timing diagram.

t

RMTR

RMT

TSECn_TX_CLK

t

RMTH

RMTF

TXD[1:0]

TX_EN

TX_ER

t

RMTDX

Figure 18. RMII Transmit AC Timing Diagram

8.2.7.2

RMII Receive AC Timing Specifications

Table 35. RMII Receive AC Timing Specifications

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

TSECn_TX_CLK clock period

t

15.0

35

20.0

50

—

25.0

65

ns

%

RMR

TSECn_TX_CLK duty cycle

t

RMRH

TSECn_TX_CLK peak-to-peak jitter

t

—

250

2.0

—

ps

ns

RMRJ

Rise time TSECn_TX_CLK(20%–80%)

Fall time TSECn_TX_CLK (80%–20%)

1.0

4.0

2.0

—

RMRR

t

—

RMRF

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge

t

—

RMRDV

t

—

RMRDX

Note:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes MII receive

(first two letters of functional block)(reference)(state)(signal)(state)

MRDVKH

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

clock reference (K)

MRX

going to the high (H) state or setup time. Also, t

symbolizes MII receive timing (GR) with respect to the time data input

MRDXKL

signals (D) went invalid (X) relative to the t

clock reference (K) going to the low (L) state or hold time. Note that, in general,

MRX

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

MRX

with the appropriate letter: R (rise) or F (fall).

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

38

Ethernet Management Interface Electrical Characteristics

Figure 19 provides the AC test load for eTSEC.

Output

LV /2

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 19. eTSEC AC Test Load

Figure 20 shows the RMII receive AC timing diagram.

t

RMRR

RMR

TSECn_TX_CLK

t

RMRF

RMRH

RXD[1:0]

CRS_DV

RX_ER

Valid Data

t

RMRDV

t

RMRDX

Figure 20. RMII Receive AC Timing Diagram

9 Ethernet Management Interface Electrical

Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

GMII, RGMII, RMII, TBI, and RTBI are specified in “Section 8, “Enhanced Three-Speed Ethernet

(eTSEC).”

9.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics

for MDIO and MDC are provided in Table 36.

Table 36. MII Management DC Electrical Characteristics

Parameter

Symbol

OV

Min

Max

Unit

Supply voltage (3.3 V)

Output high voltage (OV = Min, I = –1.0 mA)

3.13

2.10

GND

2.0

3.47

V

DD

V

OV + 0.3

DD

OH

DD

Output low voltage (OV =Min, I = 1.0 mA)

V

OL

0.50

—

DD

OL

Input high voltage

Input low voltage

V

IH

V

—

0.90

IL

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

39

Ethernet Management Interface Electrical Characteristics

Table 36. MII Management DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

1

Input high current (OV = Max, V

= 2.1 V)

I

—

40

—

μA

DD

IN

IH

Input low current (OV = Max, V = 0.5 V)

I

–600

DD

IN

IL

Note:

1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.

IN

9.2

MII Management AC Electrical Specifications

Table 37 provides the MII management AC timing specifications.

Table 37. MII Management AC Timing Specifications

At recommended operating conditions with OV_DDis 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

MDC frequency

MDC period

f

t

0.72

120.5

32

2.5

—

8.3

1389

—

MHz

ns

2, 3,4

—

MDC

MDC clock pulse width high

MDC to MDIO valid

t

ns

—

MDCH

t

16 × t

—

ns

5

MDKHDV

MDKHDX

CCB

MDC to MDIO delay

t

(16 *

*8)-3

(16 *

ns

5

t

*8)+3

ptb_clk

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

t

5

0

—

10

ns

—

4

MDDVKH

t

MDDXKH

t

—

MDCR

MDC fall time

t

4

MDHF

Notes:

1. The symbols used for timing specifications follow the pattern of t

for inputs and t

(first two

(first two letters of functional block)(signal)(state)(reference)(state)

for outputs. For example, t

symbolizes management data timing (MD) for the time t

letters of functional block)(reference)(state)(signal)(state)

MDKHDX

MDC

from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, t

symbolizes management data timing

MDDVKH

(MD) with respect to the time data input signals (D) reach the valid state (V) relative to the t

clock reference (K) going to the high (H) state

MDC

or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f ). The actual ECn_MDC output

CCB

clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of MPC8548E’s MIIMCFG register, based

on the platform (CCB) clock running for the device. The formula is: Platform Frequency (CCB)/(2*Frequency Divider determined by

MIICFG[MgmtClk] encoding selection). For example, if MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f

MDC

= 533/(2*4*8) = 533/64 = 8.3 MHz. That is, for a system running at a particular platform frequency (f

), the ECn_MDC output clock

CCB

frequency can be programmed between maximum f

= f

/64 and minimum f

= f

/448. Refer to MPC8572E reference manual’s

MDC

CCB

MDC

CCB

MIIMCFG register section for more detail.3.The maximum ECn_MDC output clock frequency is defined based on the maximum platform

frequency for MPC8548E (533 MHz) divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum

platform frequency for MPC8548E (333 MHz) divided by 448, following the formula described in Note 2 above.

4. Guaranteed by design.

5. t

is the platform (CCB) clock period.

CCB

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

40

Local Bus

Figure 21 shows the MII management AC timing diagram.

t

MDCR

MDC

t

MDCF

MDCH

MDIO

(Input)

t

MDDVKH

t

MDDXKH

MDIO

(Output)

t

MDKHDX

Figure 21. MII Management Interface Timing Diagram

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the

MPC8548E.

10.1 Local Bus DC Electrical Characteristics

Table 38 provides the DC electrical characteristics for the local bus interface operating at BV

3.3 V DC.

=

DD

Table 38. Local Bus DC Electrical Characteristics (3.3 V DC)

Parameter

Symbol

Min

Max

Unit

High-level input voltage

V

2

–0.3

—

BV + 0.3

V

IH

DD

Low-level input voltage

V

I

0.8

5

IL

1

Input current (V

= 0 V or V = BV

)

μA

V

IN

DD

IN

High-level output voltage (BV = min, I = –2 mA)

V

OH

2.4

—

0.4

DD

OH

Low-level output voltage (BV = min, I = 2 mA)

V

OL

V

DD

OL

Note:

1. Note that the symbol V , in this case, represents the BV symbol referenced in Table 1 and Table 2.

IN

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

41

Local Bus

Table 39 provides the DC electrical characteristics for the local bus interface operating at BV

2.5 V DC.

=

DD

Table 39. Local Bus DC Electrical Characteristics (2.5 V DC)

Parameter

Symbol

Min

Max

Unit

High-level input voltage

V

1.70

–0.3

—

BV + 0.3

V

IH

DD

Low-level input voltage

V

I

0.7

10

IL

1

Input current (V

= 0 V or V = BV

)

μA

IN

DD

IH

I

–15

—

IL

High-level output voltage (BV = min, I = –1 mA)

V

OH

2.0

—

V

DD

OH

Low-level output voltage (BV = min, I = 1 mA)

V

OL

0.4

DD

OL

Note:

1. Note that the symbol V , in this case, represents the BV symbol referenced in Table 1 and Table 2.

IN

10.2 Local Bus AC Electrical Specifications

Table 40 describes the timing parameters of the local bus interface at BV = 3.3 V. For information about

DD

the frequency range of local bus see Section 19.1, “Clock Ranges.”

Table 40. Local Bus Timing Parameters (BV = 3.3 V)—PLL Enabled

DD

1

Parameter

Symbol

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

t

7.5

43

—

12

57

150

—

ns

%

2

—

7, 8

3, 4

6

LBK

t

LBKH/ LBK

LCLK[n] skew to LCLK[m] or LSYNC_OUT

t

ps

ns

LBKSKEW

Input setup to local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input setup to local bus clock

t

1.8

1.7

1.0

1.5

—

LBIVKH1

LBIVKH2

LBIXKH1

LBIXKH2

—

Input hold from local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

—

t

—

LBOTOT

t

2.0

2.2

2.3

—

3

LBKHOV1

LBKHOV2

LBKHOV3

LBKHOV4

t

—

Local bus clock to address valid for LAD

—

3

Local bus clock to LALE assertion

—

3

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

t

0.7

—

3

LBKHOX1

t

—

3

LBKHOX2

Local bus clock to output high Impedance (except LAD/LDP and LALE)

t

2.5

5

LBKHOZ1

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

42

Local Bus

Table 40. Local Bus Timing Parameters (BV = 3.3 V)—PLL Enabled (continued)

DD

1

Parameter

Symbol

Min

Max

Unit

Notes

Local bus clock to output high impedance for LAD/LDP

t

—

2.5

ns

5

LBKHOZ2

Notes:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes local bus

(first two letters of functional block)(reference)(state)(signal)(state)

LBIXKH1

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

clock reference (K) goes high (H), in this case for

LBK

clock one (1). Also, t

symbolizes local bus timing (LB) for the t

clock reference (K) to go high (H), with respect to

LBKHOX

LBK

the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

DD

bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.

DD

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. t

is a measurement of the minimum time between the negation of LALE and any change in LAD. t

is

LBOTOT

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV /2.

DD

8. Guaranteed by design.

Table 41 describes the timing parameters of the local bus interface at BV = 2.5 V.

DD

Table 41. Local Bus Timing Parameters (BV = 2.5 V)—PLL Enabled

DD

1

Parameter

Symbol

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

t

7.5

43

—

12

57

150

—

ns

%

2

—

7, 8

3, 4

6

LBK

t

LBKH/ LBK

LCLK[n] skew to LCLK[m] or LSYNC_OUT

t

ps

ns

LBKSKEW

Input setup to local bus clock (except LGTA/UPWAIT)

LGTA/LUPWAIT input setup to local bus clock

Input hold from local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

t

1.9

1.8

1.1

1.5

—

LBIVKH1

LBIVKH2

LBIXKH1

LBIXKH2

—

t

—

LBOTOT

t

2.1

2.3

2.4

—

3

LBKHOV1

LBKHOV2

LBKHOV3

LBKHOV4

t

—

Local bus clock to address valid for LAD

—

3

Local bus clock to LALE assertion

—

3

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

t

0.8

3

LBKHOX1

t

—

3

LBKHOX2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

43

Local Bus

Table 41. Local Bus Timing Parameters (BV = 2.5 V)—PLL Enabled (continued)

DD

1

Parameter

Symbol

Min

Max

Unit

Notes

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

Notes:

t

—

2.6

ns

5

LBKHOZ1

LBKHOZ2

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes local bus

(first two letters of functional block)(reference)(state)(signal)(state)

LBIXKH1

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

clock reference (K) goes high (H), in this case for

LBK

clock one (1). Also, t

symbolizes local bus timing (LB) for the t

clock reference (K) to go high (H), with respect to

LBKHOX

LBK

the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

DD

bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.

DD

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. t

is a measurement of the minimum time between the negation of LALE and any change in LAD. t

is

LBOTOT

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV /2.

DD

8. Guaranteed by design.

Figure 22 provides the AC test load for the local bus.

Output

BV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 22. Local Bus AC Test Load

NOTE

PLL bypass mode is required when LBIU frequency is at or below 83 MHz.

When LBIU operates above 83 MHz, LBIU PLL is recommended to be

enabled.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

44

Freescale Semiconductor

Local Bus

Figure 23 through Figure 28 show the local bus signals.

LSYNC_IN

t

LBIXKH1

t

LBIVKH1

LBIVKH2

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH2

Input Signal:

LGTA

LUPWAIT

t

LBKHOZ1

LBKHOX1

t

LBKHOV1

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t

LBKHOZ2

LBKHOX2

LBKHOV2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t

LBKHOZ2

LBKHOX2

t

LBKHOV3

Output (Address) Signal:

LAD[0:31]

t

LBOTOT

t

LBKHOV4

LALE

Figure 23. Local Bus Signals (PLL Enabled)

Table 42 describes the timing parameters of the local bus interface at BV = 3.3 V with PLL disabled.

DD

Table 42. Local Bus Timing Parameters—PLL Bypassed

1

Parameter

Symbol

Min

Max

Unit

Notes

Local bus cycle time

Local bus duty cycle

t

12

43

—

57

4.4

—

ns

%

2

—

LBK

t

LBKH/ LBK

Internal launch/capture clock to LCLK delay

t

2.3

6.2

6.1

–1.8

–1.3

1.5

—

ns

8

LBKHKT

Input setup to local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input setup to local bus clock

t

4, 5

6

LBIVKH1

t

—

LBIVKL2

LBIXKH1

Input hold from local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input hold from local bus clock

t

—

t

—

LBIXKL2

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

t

—

LBOTOT

t

–0.3

—

LBKLOV1

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

45

Local Bus

Table 42. Local Bus Timing Parameters—PLL Bypassed (continued)

1

Parameter

Symbol

Min

Max

Unit

Notes

Local bus clock to data valid for LAD/LDP

Local bus clock to address valid for LAD

t

—

–0.1

0

ns

4

7

LBKLOV2

t

LBKLOV3

Local bus clock to LALE assertion

t

—

0

LBKLOV4

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

Notes:

t

-3.7

—

LBKLOX1

LBKLOX2

LBKLOZ1

LBKLOZ2

—

t

0.2

—

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes local bus

(first two letters of functional block)(reference)(state)(signal)(state)

LBIXKH1

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

clock reference (K) goes high (H), in this case for

LBK

clock one (1). Also, t

symbolizes local bus timing (LB) for the t

clock reference (K) to go high (H), with respect to

LBKHOX

LBK

the output (O) going invalid (X) or output hold time.

2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus

clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK

by t

.

LBKHKT

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV /2.

DD

4. All signals are measured from BV /2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BV of the signal

DD

in question for 3.3-V signaling levels.

5. Input timings are measured at the pin.

6. The value of t

is the measurement of the minimum time between the negation of LALE and any change in LAD.

LBOTOT

7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

8. Guaranteed by characterization.

9. Guaranteed by design.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

46

Freescale Semiconductor

Local Bus

Internal Launch/Capture Clock

LCLK[n]

t

LBKHKT

t

LBIVKH1

t

LBIXKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIVKL2

Input Signal:

LGTA

t

LBIXKL2

LUPWAIT

t

LBKLOV1

t

LBKLOZ1

LBKLOZ2

t

LBKLOX1

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t

LBKLOV2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t

LBKLOX2

LBKLOV3

Output (Address) Signal:

LAD[0:31]

t

LBKLOV4

LBOTOT

LALE

Figure 24. Local Bus Signals (PLL Bypass Mode)

NOTE

In PLL bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of t_LBKHKT. In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of the internal clock

with the exception of LGTA/LUPWAIT (which is captured on the rising

edge of the internal clock).

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

47

Local Bus

LSYNC_IN

T1

T3

t

LBKHOZ1

LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t

LBIVKH2

t

LBIXKH2

UPM Mode Input Signal:

LUPWAIT

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

t

LBKHOV1

LBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

48

Local Bus

Internal Launch/Capture Clock

T1

T3

LCLK

t

LBKLOX1

LBKLOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t

LBKLOZ1

GPCM Mode Input Signal:

LGTA

t

LBIVKL2

t

LBIXKL2

UPM Mode Input Signal:

LUPWAIT

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

49

Local Bus

LSYNC_IN

T1

T2

T3

T4

t

LBKHOV1

LBKHOZ1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t

LBIVKH2

t

LBIXKH2

UPM Mode Input Signal:

LUPWAIT

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

t

LBKHOV1

LBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabled)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

50

Programmable Interrupt Controller

Internal Launch/Capture Clock

T1

T2

T3

T4

LCLK

t

LBKLOX1

LBKLOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t

LBKLOZ1

GPCM Mode Input Signal:

LGTA

t

LBIVKL2

t

LBIXKL2

UPM Mode Input Signal:

LUPWAIT

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode)

11 Programmable Interrupt Controller

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed

polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).

12 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of

the MPC8548E.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

51

JTAG

12.1 JTAG DC Electrical Characteristics

Table 43 provides the DC electrical characteristics for the JTAG interface.

Table 43. JTAG DC Electrical Characteristics

1

Parameter

Symbol

Min

Max

Unit

High-level input voltage

V

2

–0.3

—

OV + 0.3

V

IH

DD

Low-level input voltage

V

I

0.8

5

IL

1

Input current (V

= 0 V or V = V

)

μA

V

IN

DD

IN

High-level output voltage (OV = min, I = –2 mA)

V

OH

2.4

—

0.4

DD

OH

Low-level output voltage (OV = min, I = 2 mA)

V

OL

V

DD

OL

Note:

1. Note that the symbol V , in this case, represents the OV .

IN

12.2 JTAG AC Electrical Specifications

Table 44 provides the JTAG AC timing specifications as defined in Figure 30 through Figure 32.

1

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f

0

33.3

—

MHz

ns

—

6

JTG

t

30

15

0

JTG

t

—

ns

JTKHKL

t

& t

2

ns

JTGR

JTGF

t

25

—

ns

3

TRST

Input setup times:

ns

Boundary-scan data

t

4

0

—

4

5

JTDVKH

TMS, TDI

JTIVKH

Input hold times:

Valid times:

ns

Boundary-scan data

TMS, TDI

t

20

25

—

JTDXKH

t

JTIXKH

Boundary-scan data

TDO

t

4

20

25

JTKLDV

JTKLOV

Output hold times:

Boundary-scan data

TDO

t

30

—

JTKLDX

JTKLOX

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

52

JTAG

1

Table 44. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock to output high impedance:

ns

Boundary-scan data

TDO

t

3

19

9

5, 6

JTKLDZ

JTKLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

to the midpoint of the signal in question.

TCLK

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 29).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes JTAG device

(first two letters of functional block)(reference)(state)(signal)(state)

JTDVKH

timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

clock reference (K)

JTG

going to the high (H) state or setup time. Also, t

symbolizes JTAG timing (JT) with respect to the time data input signals

JTDXKH

(D) went invalid (X) relative to the t

clock reference (K) going to the high (H) state. Note that, in general, the clock reference

JTG

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t

.

TCLK

5. Non-JTAG signal output timing with respect to t

6. Guaranteed by design.

.

TCLK

Figure 29 provides the AC test load for TDO and the boundary-scan outputs.

Output

OV /2

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 29. AC Test Load for the JTAG Interface

Figure 30 provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t

VM

t

JTGR

JTKHKL

t

JTGF

JTG

VM = Midpoint Voltage (OV /2)

DD

Figure 30. JTAG Clock Input Timing Diagram

Figure 31 provides the TRST timing diagram.

TRST

VM

t

TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 31. TRST Timing Diagram

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

53

I²C

Figure 32 provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t

JTDVKH

t

JTDXKH

Boundary

Data Inputs

Input

Data Valid

t

JTKLDV

t

JTKLDX

Boundary

Data Outputs

Output Data Valid

t

JTKLDZ

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 32. Boundary-Scan Timing Diagram

13 I²C

2

This section describes the DC and AC electrical characteristics for the I C interfaces of the MPC8548E.

2

13.1 I C DC Electrical Characteristics

2

Table 45 provides the DC electrical characteristics for the I C interfaces.

2

Table 45. I C DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

Input low voltage level

V

0.7 × OV

OV + 0.3

V

—

1

IH

DD

V

–0.3

0

0.3 × OV

IL

DD

Low level output voltage

V

0.2 × OV

V

OL

DD

Pulse width of spikes which must be suppressed by the

input filter

t

0

50

10

ns

2

I2KHKL

Input current each I/O pin (input voltage is between

I

–10

—

μA

3

I

0.1 × OV and 0.9 × OV (max)

DD

Capacitance for each I/O pin

C

pF

—

I

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual, for information on the digital filter

used.

3. I/O pins will obstruct the SDA and SCL lines if OV is switched off.

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

54

I²C

2

13.2 I C AC Electrical Specifications

2

Table 46 provides the AC timing parameters for the I C interfaces.

2

Table 46. I C AC Electrical Specifications

1

Parameter

Symbol

Min

Max

Unit

Notes

SCL clock frequency

f

0

400

—

kHz

μs

—

4

I2C

Low period of the SCL clock

t

1.3

0.6

I2CL

High period of the SCL clock

—

μs

4

I2CH

Setup time for a repeated START condition

t

—

μs

4

I2SVKH

Hold time (repeated) START condition (after this period,

the first clock pulse is generated)

t

—

μs

4

I2SXKL

Data setup time

t

100

—

ns

4

2

I2DVKH

Data input hold time:

t

μs

I2DXKL

I2OVKL

CBUS compatible masters

—

0

—

2

I C bus devices

Data output delay time:

t

—

0.6

0.9

—

μs

V

3

Set-up time for STOP condition

t

—

I2PVKH

Bus free time between a STOP and START condition

t

1.3

I2KHDX

Noise margin at the LOW level for each connected device

(including hysteresis)

V

0.1 × OV

NL

DD

Noise margin at the HIGH level for each connected

device (including hysteresis)

V

0.2 × OV

—

V

—

NH

Notes:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

2

inputs and t

for outputs. For example, t

symbolizes I C timing (I2)

(first two letters of functional block)(reference)(state)(signal)(state)

I2DVKH

with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high

I2C

2

(H) state or setup time. Also, t

symbolizes I C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the t clock reference (K) going to the low (L) state or hold time. Also, t

I2SXKL

2

symbolizes I C

I2C

I2PVKH

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t

clock

I2C

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8548E provides a delay time of at least 300 ns for the SDA signal (refer to the V (min) of the SCL

IH

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

2

When MPC8548E acts as the I C bus master while transmitting, MPC8548E drives both SCL and SDA. As long as the load

on SCL and SDA are balanced, MPC8548E would not cause unintended generation of Start or Stop condition. Therefore,

the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required

for MPC8548E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure

2

both the desired I C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I C SCL clock

frequency is 400 kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of

0x10 (decimal 16):

2

I C source clock frequency

FDR bit setting

333 MHz 266 MHz

200 MHz

0x26

512

133 MHz

0x00

384

0x2A

896

0x05

704

Actual FDR divider selected

Actual I C SCL frequency generated 371 kHz

For the detail of I C frequency calculation, refer to Freescale Application Note AN2919, Determining the I C Frequency

Divider Ratio for SCL. Note that the I C source clock frequency is half of the CCB clock frequency for MPC8548E.

2

378 kHz

390 kHz

346 kHz

2

3. The maximum t

has only to be met if the device does not stretch the LOW period (t

) of the SCL signal.

I2CL

I2DXKL

4. Guaranteed by design.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

55

PCI/PCI-X

2

Figure 29 provides the AC test load for the I C.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

2

Figure 33. I C AC Test Load

2

Figure 34 shows the AC timing diagram for the I C bus.

SDA

t

I2CF

I2DVKH

I2KHKL

t

I2CR

I2CL

I2SXKL

SCL

t

I2PVKH

I2SXKL

I2CH

I2SVKH

t

I2DXKL, I2OVKL

S

Sr

P

S

2

Figure 34. I C Bus AC Timing Diagram

14 PCI/PCI-X

This section describes the DC and AC electrical specifications for the PCI/PCI-X bus of the MPC8548E.

Note that the maximum PCI-X frequency in synchronous mode is 110 MHz.

14.1 PCI/PCI-X DC Electrical Characteristics

Table 47 provides the DC electrical characteristics for the PCI/PCI-X interface.

1

Table 47. PCI/PCI-X DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

Notes

V

2

–0.3

—

OV + 0.3

V

—

2

IH

DD

Low-level input voltage

V

I

0.8

5

IL

Input current (V = 0 V or V = V

)

μA

V

IN

DD

IN

High-level output voltage (OV = min, I = –2 mA)

V

OH

2.4

—

0.4

—

DD

OH

Low-level output voltage (OV = min, I = 2 mA)

V

OL

V

DD

OL

Notes:

1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.

2. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.

IN

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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56

PCI/PCI-X

14.2 PCI/PCI-X AC Electrical Specifications

This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock

reference CLK is represented by SYSCLK when the PCI controller is configured for asynchronous mode

and by PCIn_CLK when it is configured for asynchronous mode.

Table 48 provides the PCI AC timing specifications at 66 MHz.

Table 48. PCI AC Timing Specifications at 66 MHz

1

Parameter

Symbol

Min

Max

Unit

Notes

CLK to output valid

t

—

2.0

6.0

—

14

—

50

—

ns

2, 3

PCKHOV

PCKHOX

PCKHOZ

Output hold from CLK

2, 10

CLK to output high impedance

Input setup to CLK

—

ns

2, 4, 11

2, 5, 10

6, 7, 11

7, 11

t

3.0

ns

PCIVKH

PCIXKH

PCRVRH

PCRHRX

Input hold from CLK

t

0

ns

9

REQ64 to HRESET setup time

t

10 × t

clocks

ns

SYS

HRESET to REQ64 hold time

HRESET high to first FRAME assertion

Notes:

0

t

10

clocks

8, 11

PCRHFV

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state)(reference)(state)

inputs and t

for outputs. For example, t

symbolizes PCI/PCI-X

(first two letters of functional block)(reference)(state)(signal)(state)

PCIVKH

timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t

, reference

SYS

(K) going to the high (H) state or setup time. Also, t

symbolizes PCI/PCI-X timing (PC) with respect to the time hard

PCRHFV

reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. All PCI signals are measured from OV /2 of the rising edge of SYSCLK or PCI_CLKn to 0.4 × OV of the signal in question

DD

for 3.3-V PCI signaling levels.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

6. The timing parameter t

indicates the minimum and maximum CLK cycle times for the various specified frequencies. The

SYS

system clock period must be kept within the minimum and maximum defined ranges. For values see Section 19, “Clocking.”

7. The setup and hold time is with respect to the rising edge of HRESET.

8. The timing parameter t

Specifications.

is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus

PCRHFV

9. The reset assertion timing requirement for HRESET is 100 μs.

10.Guaranteed by characterization.

11.Guaranteed by design.

Figure 35 provides the AC test load for PCI and PCI-X.

Output

LV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 35. PCI/PCI-X AC Test Load

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

57

PCI/PCI-X

Figure 36 shows the PCI/PCI-X input AC timing conditions.

CLK

t

PCIVKH

t

PCIXKH

Input

Figure 36. PCI/PCI-X Input AC Timing Measurement Conditions

Figure 37 shows the PCI/PCI-X output AC timing conditions.

CLK

t

PCKHOV

Output Delay

t

PCKHOZ

High-Impedance

Output

Figure 37. PCI/PCI-X Output AC Timing Measurement Condition

Table 49 provides the PCI-X AC timing specifications at 66 MHz.

Table 49. PCI-X AC Timing Specifications at 66 MHz

Parameter

SYSCLK to signal valid delay

Symbol

Min

Max

Unit

Notes

t

—

0.7

—

3.8

—

7

ns

1, 2, 3, 7, 8

1, 10

1, 4, 8, 11

3, 5

PCKHOV

Output hold from SYSCLK

t

PCKHOX

PCKHOZ

SYSCLK to output high impedance

Input setup time to SYSCLK

t

ns

t

1.7

0.5

10

0

—

50

—

ns

PCIVKH

Input hold time from SYSCLK

t

ns

10

PCIXKH

PCRVRH

PCRHRX

REQ64 to HRESET setup time

HRESET to REQ64 hold time

t

clocks

ns

11

t

11

HRESET high to first FRAME assertion

PCI-X initialization pattern to HRESET setup time

t

10

clocks

9, 11

11

PCRHFV

PCIVRH

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

58

PCI/PCI-X

Table 49. PCI-X AC Timing Specifications at 66 MHz (continued)

Parameter

Symbol

Min

Max

Unit

Notes

6, 11

HRESET to PCI-X initialization pattern hold time

t

0

50

ns

PCRHIX

Notes:

1. See the timing measurement conditions in the PCI-X 1.0a Specification.

2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and

load circuit.

3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.

6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, t

).

PCRHFV

The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks

before the first FRAME and must be floated no later than one clock before FRAME is asserted.

7. A PCI-X device is permitted to have the minimum values shown for t

and t

only in PCI-X mode. In conventional

CYC

PCKHOV

mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.

8. Device must meet this specification independent of how many outputs switch simultaneously.

9. The timing parameter t

is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification.

PCRHFV

10.Guaranteed by characterization.

11.Guaranteed by design.

Table 50 provides the PCI-X AC timing specifications at 133 MHz.

Note that the maximum PCI-X frequency in synchronous mode is 110 MHz.

Table 50. PCI-X AC Timing Specifications at 133 MHz

Parameter

SYSCLK to signal valid delay

Symbol

Min

Max

Unit

Notes

t

—

0.7

—

3.8

—

7

ns

1, 2, 3, 7, 8

1, 11

PCKHOV

Output hold from SYSCLK

t

PCKHOX

PCKHOZ

SYSCLK to output high impedance

Input setup time to SYSCLK

t

ns

1, 4, 8, 12

3, 5, 9, 11

11

t

1.2

0.5

10

0

—

50

—

ns

PCIVKH

Input hold time from SYSCLK

t

ns

PCIXKH

PCRVRH

PCRHRX

REQ64 to HRESET setup time

HRESET to REQ64 hold time

t

clocks

ns

12

t

12

HRESET high to first FRAME assertion

PCI-X initialization pattern to HRESET setup time

t

10

clocks

10, 12

12

PCRHFV

PCIVRH

t

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

59

High-Speed Serial Interfaces (HSSI)

Table 50. PCI-X AC Timing Specifications at 133 MHz (continued)

Parameter

Symbol

Min

Max

Unit

Notes

HRESET to PCI-X initialization pattern hold time

t

0

50

ns

6, 12

PCRHIX

Notes:

1. See the timing measurement conditions in the PCI-X 1.0a Specification.

2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and

load circuit.

3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.

6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, t

).

PCRHFV

The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks

before the first FRAME and must be floated no later than one clock before FRAME is asserted.

7. A PCI-X device is permitted to have the minimum values shown for t

and t

only in PCI-X mode. In conventional

CYC

PCKHOV

mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.

8. Device must meet this specification independent of how many outputs switch simultaneously.

9. The timing parameter t

is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the PCI-X 1.0a Specification.

PCIVKH

10.The timing parameter t

Specification.

is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a

PCRHFV

11.Guaranteed by characterization.

11.Guaranteed by design.

15 High-Speed Serial Interfaces (HSSI)

The MPC8548E features one Serializer/Deserializer (SerDes) interface to be used for high-speed serial

interconnect applications. The SerDes interface can be used for PCI Express and/or serial RapidIO data

transfers.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits

are also shown.

15.1 Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for the

description. The figure shows a waveform for either a transmitter output (SD_TX and SD_TX) or a

receiver input (SD_RX and SD_RX). Each signal swings between A volts and B volts where A > B.

Using this waveform, the definitions are as follows. To simplify the illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

1. Single-ended swing

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High-Speed Serial Interfaces (HSSI)

The transmitter output signals and the receiver input signals SD_TX, SD_TX, SD_RX and SD_RX

each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s

single-ended swing.

2. Differential output voltage, V (or differential output swing):

OD

The differential output voltage (or swing) of the transmitter, V , is defined as the difference of

OD

the two complimentary output voltages: V

or negative.

– V

. The V value can be either positive

SD_TX

SD_TX OD

3. Differential input voltage, V (or differential input swing):

ID

The differential input voltage (or swing) of the receiver, V , is defined as the difference of the two

ID

complimentary input voltages: V

negative.

– V

. The V value can be either positive or

SD_RX

SD_RX ID

4. Differential peak voltage, V

DIFFp

The peak value of the differential transmitter output signal or the differential receiver input signal

is defined as differential peak voltage, V = |A – B| volts.

DIFFp

5. Differential peak-to-peak, V

DIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter

output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,

V

= 2 × V

= 2 × |(A – B)| volts, which is twice of differential swing in amplitude, or

DIFFp-p

DIFFp

twice of the differential peak. For example, the output differential peak-to-peak voltage can also be

calculated as V

= 2 × |V |.

TX-DIFFp-p

OD

6. Common mode voltage, V

cm

The common mode voltage is equal to one half of the sum of the voltages between each conductor

of a balanced interchange circuit and ground. In this example, for SerDes output, V = V

cm_out

SD_TX

+ V

= (A + B)/2, which is the arithmetic mean of the two complimentary output voltages

SD_TX

within a differential pair. In a system, the common mode voltage may often differ from one

component’s output to the other’s input. Sometimes, it may be even different between the receiver

input and driver output circuits within the same component. It is also referred to as the DC offset.

SD_TX or

SD_RX

A Volts

V

= (A + B)/2

cm

SD_TX or

SD_RX

B Volts

Differential Swing, V or V = A – B

ID

OD

DIFFp

Differential Peak Voltage, V

= |A – B|

Differential Peak-Peak Voltage, V

= 2*V

(not shown)

DIFFpp

DIFFp

Figure 38. Differential Voltage Definitions for Transmitter or Receiver

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High-Speed Serial Interfaces (HSSI)

To illustrate these definitions using real values, consider the case of a CML (current mode logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or

TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the

differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V

)

OD

has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between

500 and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other phase. The peak

OD

differential voltage (V

) is 500 mV. The peak-to-peak differential voltage (V

) is 1000 mVp-p.

DIFFp

DIFFp-p

15.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and

SD_REF_CLK for PCI Express and serial RapidIO.

The following sections describe the SerDes reference clock requirements and some application

information.

15.2.1 SerDes Reference Clock Receiver Characteristics

Figure 39 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for XV

are specified in Table 1 and Table 2.

DD_SRDS2

SerDes Reference clock receiver reference circuit structure:

— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown

in Figure 39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω

termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

differential mode and single-ended mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range:

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above

SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by

a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that

each phase of the differential input has a single-ended swing from 0 V to 800 mV with the

common mode voltage at 400 mV.

— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to

SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it

must be AC-coupled off-chip.

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High-Speed Serial Interfaces (HSSI)

•

The input amplitude requirement:

— This requirement is described in detail in the following sections.

50 Ω

SD_REF_CLK

Input

Amp

SD_REF_CLK

50 Ω

Figure 39. Receiver of SerDes Reference Clocks

15.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8548E SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below:

•

Differential mode

— The input amplitude of the differential clock must be between 400 and 1600 mV differential

peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of

the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.

This requirement is the same for both external DC-coupled or AC-coupled connection.

— For external DC-coupled connection, as described in Section 15.2.1, “SerDes Reference Clock

Receiver Characteristics,” the maximum average current requirements sets the requirement for

average voltage (common mode voltage) to be between 100 and 400 mV. Figure 40 shows the

SerDes reference clock input requirement for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above

the command mode voltage (SGND_SRDSn). Figure 41 shows the SerDes reference clock

input requirement for AC-coupled connection scheme.

•

Single-ended mode

— The reference clock can also be single-ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V to V ) with

min

max

SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows

the SerDes reference clock input requirement for single-ended signaling mode.

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High-Speed Serial Interfaces (HSSI)

— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC-

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

V

< 800 mV

max

100 mV < V < 400 mV

cm

SD_REF_CLK

V

> 0 V

min

Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

V

< V + 400 mV

max cm

V

cm

SD_REF_CLK

V

> V – 400 mV

cm

min

Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)

400 mV < SD_REF_CLK Input Amplitude < 800 mV

SD_REF_CLK

0 V

SD_REF_CLK

Figure 42. Single-Ended Reference Clock Input DC Requirements

15.2.3 Interfacing With Other Differential Signaling Levels

•

With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are

HCSL (high-speed current steering logic) compatible DC-coupled.

•

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can

be used but may need to be AC-coupled due to the limited common mode input range allowed (100

to 400 mV) for DC-coupled connection.

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High-Speed Serial Interfaces (HSSI)

•

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at

clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in

addition to AC-coupling.

NOTE

Figure 43 through Figure 46 below are for conceptual reference only. Due

to the fact that clock driver chip's internal structure, output impedance and

termination requirements are different between various clock driver chip

manufacturers, it’s very possible that the clock circuit reference designs

provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8548E SerDes reference clock receiver requirement

provided in this document.

Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8548E SerDes reference clock

input’s DC requirement.

HCSL CLK Driver Chip

MPC8548E

50 Ω

SD_REF_CLK

CLK_Out

33 Ω

SerDes Refer.

CLK Receiver

100 Ω Differential PWB Trace

Clock Driver

CLK_Out

SD_REF_CLK

50 Ω

Clock driver vendor dependent

source termination resistor

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8548E SerDes reference clock

input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the

LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

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High-Speed Serial Interfaces (HSSI)

LVDS CLK Driver Chip

MPC8548E

50 Ω

SD_REF_CLK

CLK_Out

10 nF

SerDes Refer.

CLK Receiver

100 Ω Differential PWB Trace

Clock Driver

10 nF

CLK_Out

50 Ω

Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

the MPC8548E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45

assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on the clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8548E SerDes

reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).

For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock

input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Consult a

clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular

clock driver chip.

LVPECL CLK Driver Chip

MPC8548E

50 Ω

SD_REF_CLK

CLK_Out

10 nF

R2

SerDes Refer.

CLK Receiver

R1

100 Ω Differential PWB Trace

10 nF

Clock Driver

CLK_Out

R2

SD_REF_CLK

50 Ω

Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

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High-Speed Serial Interfaces (HSSI)

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with the MPC8548E SerDes reference clock

input’s DC requirement.

Single-Ended CLK

Driver Chip

MPC8548E

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

SD_REF_CLK

33 Ω

Clock Driver

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω Differential PWB Trace

SD_REF_CLK

50 Ω

Figure 46. Single-Ended Connection (Reference Only)

15.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15-MHz range. The source impedance of the clock driver should be 50 Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

The detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based

on application usage. Refer to the following sections for detailed information:

•

Section 16.2, “AC Requirements for PCI Express SerDes Clocks”

Section 17.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK”

15.2.4.1 Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK are designed to work with a spread spectrum clock (+0% to –0.5%

spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

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PCI Express

15.3 SerDes Transmitter and Receiver Reference Circuits

Figure 47 shows the reference circuits for SerDes data lane’s transmitter and receiver.

SD_TXn

SD_RXn

50 Ω

Receiver

Transmitter

SD_TXn

SD_RXn

Figure 47. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express, Serial Rapid IO, or SGMII) in this document based on the application usage:

•

Section 16, “PCI Express”

Section 17, “Serial RapidIO”

Note that external an AC coupling capacitor is required for the above three serial transmission protocols

with the capacitor value defined in the specification of each protocol section.

16 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E.

16.1 DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 15.2, “SerDes Reference Clocks.”

16.2 AC Requirements for PCI Express SerDes Clocks

Table 51 lists the AC requirements for the PCI Express SerDes clocks.

Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Unit Notes

t

REFCLK cycle time

—

10

—

ns

ps

1

REF

t

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles.

100

—

REFCJ

Phase jitter. Deviation in edge location with respect to mean edge

location.

–50

—

50

ps

—

REFPJ

Note:

1. Typical based on PCI Express Specification 2.0.

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PCI Express

16.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

16.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer refer to PCI Express Base

Specification. Rev. 1.0a.

16.4.1 Differential Transmitter (TX) Output

Table 52 defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 52. Differential Transmitter (TX) Output Specifications

Symbol

Parameter

Min

Nom

Max

Unit

Comments

UI

Unit interval

399.88

400

400.12

ps Each UI is 400 ps 300 ppm. UI does not account

for spread spectrum clock dictated variations.

See Note 1.

V

Differential

peak-to-peak

output voltage

0.8

—

1.2

V

= 2*|V

– V

|. See Note 2.

TX-DIFFp-p

TX-D+

TX-D–

V

De-emphasized

differential

output voltage

(ratio)

–3.0

–3.5

–4.0

dB Ratio of the V

of the second and

TX-DE-RATIO

TX-DIFFp-p

following bits after a transition divided by the

V of the first bit after a transition.

TX-DIFFp-p

See Note 2.

T

MinimumTX eye

width

0.70

—

UI The maximum transmitter jitter can be derived as

TX-EYE

T

= 1 – T = 0.3 UI.

TX-MAX-JITTER

TX-EYE

See Notes 2 and 3.

T

Maximum time

between the

jittermedian and

maximum

deviation from

the median.

0.15

UI Jitter is defined as the measurement variation of

TX-EYE-MEDIAN-to-

MAX-JITTER

the crossing points (V = 0 V) in relation

TX-DIFFp-p

to a recovered TX UI. A recovered TX UI is

calculated over 3500 consecutive unit intervals of

sample data. Jitter is measured using all edges of

the 250 consecutive UI in the center of the 3500

UI used for calculating the TX UI.

See Notes 2 and 3.

T

, T

D+/D–TX output 0.125

rise/fall time

—

UI See Notes 2 and 5.

TX-RISE TX-FALL

V

RMS AC peak

common mode

output voltage

—

20

mV

V

= RMS(|V

+ V |/2 –

TXD–

TX-CM-ACp

TXD+

)

TX-CM-DC

= DC

of |V

+ V

|/2.

TX-D–

TX-CM-DC

(avg)

TX-D+

See Note 2.

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Table 52. Differential Transmitter (TX) Output Specifications (continued)

Symbol

Parameter

Min

Nom

Max

Unit

Comments

+ V

TX-CM-Idle-DC (during

V

Absolutedeltaof

dc common

0

—

100

mV |V

TX-CM-DC-ACTIVE-

IDLE-DELTA

TX-CM-DC (during L0)

| <= 100 mV

electrical idle)

mode voltage

during L0 and

electrical idle

V

= DC

of |V

+ V

|/2 [L0]

TX-D–

TX-CM-DC

(avg)

TX-D+

V

= DC

of |V

+ V

|/2

TX-CM-Idle-DC

(avg)

TX-D+

TX-D–

[electrical idle]

See Note 2.

V

Absolutedeltaof

DC common

mode between

D+ and D–

0

—

25

mV |V

– V

= DC

| <= 25 mV

|

TX-D+

TX-CM-DC-LINE-DELTA

TX-CM-DC-D+

TX-CM-DC-D–

V

of |V

TX-CM-DC-D+

(avg)

of |V

|.

TX-CM-DC-D–

TX-D–

See Note 2.

V

Electrical idle

differential peak

output voltage

0

—

20

mV

V

= |V

– V

|

TX-IDLE-D–

TX-IDLE-DIFFp

TX-IDLE-D+

<= 20 mV.

See Note 2.

V

The amount of

voltage change

allowed during

receiver

—

600

mV The total amount of voltage change that a

TX-RCV-DETECT

transmitter can apply to sense whether a low

impedance receiver is present. See Note 6.

detection

V

The TX DC

common mode

voltage

0

—

3.6

90

V

The allowed DC common mode voltage under any

conditions. See Note 6.

TX-DC-CM

I

TX short circuit

current limit

—

mA The total current the transmitter can provide when

shorted to its ground

TX-SHORT

T

Minimum time

spent in

electrical idle

50

UI Minimum time a transmitter must be in electrical

idle utilized by the receiver to start looking for an

electrical idle exit after successfully receiving an

electrical idle ordered set

TX-IDLE-MIN

T

Maximum time

to transition to a

valid electrical

idle after

sending an

electrical idle

ordered set

—

20

UI After sending an electrical idle ordered set, the

transmitter must meet all electrical idle

TX-IDLE-SET-TO-IDLE

specifications within this time. This is considered

a debounce time for the transmitter to meet

electrical idle after transitioning from L0.

T

Maximum time

to transition to

valid TX

specifications

after leaving an

electrical idle

condition

UI Maximum time to meet all TX specifications when

transitioning from electrical idle to sending

differential data. This is considered a debounce

time for the TX to meet all TX specifications after

leaving electrical idle

TX-IDLE-TO-DIFF-DATA

RL

Differential

return loss

12

6

—

dB Measured over 50 MHz to 1.25 GHz.

See Note 4.

TX-DIFF

RL

Common mode

return loss

dB Measured over 50 MHz to 1.25 GHz.

See Note 4.

TX-CM

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Table 52. Differential Transmitter (TX) Output Specifications (continued)

Symbol

Parameter

Min

Nom

Max

Unit

Comments

Z

DC differential

TX impedance

80

100

120

Ω

TX DC differential mode low impedance

TX-DIFF-DC

Z

Transmitter DC

impedance

40

—

75

—

Ω

Required TX D+ as well as D– DC impedance

during all states

TX-DC

L

Lane-to-lane

output skew

500

+ 2 UI

ps Static skew between any two transmitter lanes

within a single Link

TX-SKEW

C

AC coupling

capacitor

200

nF All transmitters shall be AC coupled. The AC

coupling is required either within the media or

within the transmitting component itself. See note

8.

TX

T

Crosslink

random timeout

0

—

1

ms This random timeout helps resolve conflicts in

crosslink configuration by eventually resulting in

only one downstream and one upstream port.

See Note 7.

crosslink

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 50 and measured over

any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 48.)

3. A T

= 0.70 UI provides for a total sum of deterministic and random jitter budget of T

= 0.30 UI for the

TX-EYE

TX-JITTER-MAX

transmitter collected over any 250 consecutive TX UIs. The T

median is less than half of the total

TX-EYE-MEDIAN-to-MAX-JITTER

TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as

opposed to the averaged time value.

4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and

D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see Figure 50). Note that the series capacitors

C

is optional for the return loss measurement.

TX

5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 50 for both V

6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a.

and V

.

TX-D–

TX-D+

7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a.

8. MPC8548E SerDes transmitter does not have CTX built in. An external AC coupling capacitor is required.

16.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 48 is specified using the passive compliance/test measurement load (see

Figure 50) in place of any real PCI Express interconnect +RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in

time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ

in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level

of the de-emphasized bit will always be relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

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A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the

TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (for example, least squares and median deviation fits).

V

= 0 mV

V

= 0 mV

TX-DIFF

RX-DIFF

(D+ D– Crossing Point)

[Transition Bit]

= 800 mV

V

TX-DIFFp-p-MIN

[De-Emphasized Bit]

566 mV (3 dB) >= >= 505 mV (4 dB)

V

TX-DIFFp-p-MIN

0.07 UI = UI – 0.3 UI (J

)

TX-TOTAL-MAX

[Transition Bit]

= 800 mV

V

TX-DIFFp-p-MIN

Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications

16.4.3 Differential Receiver (RX) Input Specifications

Table 53 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 53. Differential Receiver (RX) Input Specifications

Symbol

Parameter

Min

Nom

Max

Unit

Comments

UI

Unit interval

399.88

400

400.12

ps Each UI is 400 ps 300 ppm. UI does not account

for spread spectrum clock dictated variations.

See Note 1.

V

Differential

peak-to-peak

input voltage

0.175

—

1.200

V

= 2*|V

– V

|. See Note 2.

RX-D–

RX-DIFFp-p

RX-D+

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Table 53. Differential Receiver (RX) Input Specifications (continued)

Symbol

Parameter

Min

Nom

Max

Unit

Comments

T

Minimum

receiver eye

width

0.4

—

UI The maximum interconnect media and transmitter

jitter that can be tolerated by the receiver can be

RX-EYE

derived as T

= 1 – T

= 0.6 UI.

RX-MAX-JITTER

RX-EYE

See Notes 2 and 3.

T

Maximum time

between the

jittermedian and

maximum

deviation from

the median

—

0.3

UI Jitter is defined as the measurement variation of

RX-EYE-MEDIAN-to-

MAX-JITTER

the crossing points (V = 0 V) in relation

RX-DIFFp-p

to a recovered TX UI. A recovered TX UI is

calculated over 3500 consecutive unit intervals of

sample data. Jitter is measured using all edges of

the 250 consecutive UI in the center of the

3500 UI used for calculating the TX UI.

See Notes 2, 3, and 7.

V

AC peak

common mode

input voltage

—

150

—

mV

V

= |V

= DC

– V

of |V

|/2 + V

RXD- RX-CM-DC

RX-CM-ACp

RXD+

+ V

|/2.

RX-CM-DC

(avg)

RX-D+

RX-D–

See Note 2.

RL

Differential

return loss

15

dB Measured over 50 MHz to 1.25 GHz with the D+

and D– lines biased at +300 mV and –300 mV,

respectively. See Note 4.

RX-DIFF

RL

Common mode

return loss

6

80

—

100

50

—

120

60

dB Measured over 50 MHz to 1.25 GHz with the D+

and D– lines biased at 0 V. See Note 4.

RX-CM

Z

DC differential

input impedance

Ω

RX DC differential mode impedance. See Note 5.

RX-DIFF-DC

Z

DC input

impedance

40

Required RX D+ as well as D– DC impedance

(50 20% tolerance). See Notes 2 and 5.

RX-DC

Z

Powered down

DC input

impedance

200 k

—

Required RX D+ as well as D– DC impedance

when the receiver terminations do not have

power. See Note 6.

RX-HIGH-IMP-DC

V

Electrical idle

detect threshold

65

—

175

10

mV

V

= 2*|V

-V

|.

RX-D–

RX-IDLE-DET-DIFFp-p

RX-D+

Measured at the package pins of the receiver

T

Unexpected

electrical idle

enter detect

threshold

ms An unexpected electrical idle (V

<

RX-DIFFp-p

RX-IDLE-DET-DIFF-

ENTERTIME

V

) must be recognized no

RX-IDLE-DET-DIFFp-p

longer than T

an unexpected idle condition.

to signal

RX-IDLE-DET-DIFF-ENTERING

integration time

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Table 53. Differential Receiver (RX) Input Specifications (continued)

Symbol

Parameter

Min

Nom

Max

Unit

Comments

L

Total Skew

—

20

ns Skew across all lanes on a Link. This includes

variation in the length of SKP ordered set (for

example, COM and one to five symbols) at the RX

as well as any delay differences arising from the

interconnect itself.

TX-SKEW

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 50 should be used

as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 49). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3. A T

= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

RX-EYE

interconnect collected any 250 consecutive UIs. The T

specification ensures a jitter distribution

RX-EYE-MEDIAN-to-MAX-JITTER

in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over

any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes

the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time

value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500

consecutive UI must be used as the reference for the eye diagram.

4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased

to 300 mV and the D– line biased to –{300 mV and a common mode return loss greater than or equal to 6 dB (no bias

required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels.

The reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured

by a vector network analyzer with 50-Ω probes—see Figure 50). Note: that the series capacitors CTX is optional for the return

loss measurement.

5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

6. The RX DC common mode Impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit

algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental

and simulated data.

16.5 Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 49 is specified using the passive compliance/test measurement load (see

Figure 50) in place of any real PCI Express RX component.

Note: In general, the minimum receiver eye diagram measured with the compliance/test measurement load

(see Figure 50) will be larger than the minimum receiver eye diagram measured over a range of systems

at the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver

is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI

Express component to vary in impedance from the compliance/test measurement load. The input receiver

eye diagram is implementation specific and is not specified. RX component designer should provide

additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in

Figure 49) expected at the input receiver based on some adequate combination of system simulations and

the return loss measured looking into the RX package and silicon. The RX eye diagram must be aligned

in time using the jitter median to locate the center of the eye diagram.

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The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the

TX UI.

NOTE

The reference impedance for return loss measurements is 50. to ground for

both the D+ and D– line (that is, as measured by a vector network analyzer

with 50-Ω probes—see Figure 50). Note that the series capacitors, CTX, are

optional for the return loss measurement.

V

= 0 mV

V

= 0 mV

RX-DIFF

(D+ D– Crossing Point)

V

> 175 mV

RX-DIFFp-p-MIN

0.4 UI = T

RX-EYE-MIN

Figure 49. Minimum Receiver Eye Timing and Voltage Compliance Specification

16.5.1 Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within

0.2 inches of the package pins, into a test/measurement load shown in Figure 50.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

D+ Package

C = C

TX

Silicon

+ Package

C = C

TX

D– Package

R = 50 Ω

Figure 50. Compliance Test/Measurement Load

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Serial RapidIO

17 Serial RapidIO

This section describes the DC and AC electrical specifications for the RapidIO interface of the

MPC8548E, for the LP-Serial physical layer. The electrical specifications cover both single- and

multiple-lane links. Two transmitters (short and long run) and a single receiver are specified for each of

three baud rates, 1.25, 2.50, and 3.125 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to

driving two connectors across a backplane. A single receiver specification is given that will accept signals

from both the short- and long-run transmitter specifications.

The short-run transmitter should be used mainly for chip-to-chip connections on either the same

printed-circuit board or across a single connector. This covers the case where connections are made to a

mezzanine (daughter) card. The minimum swings of the short-run specification reduce the overall power

used by the transceivers.

The long-run transmitter specifications use larger voltage swings that are capable of driving signals across

backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications

allow a distance of at least 50 cm at all baud rates.

All unit intervals are specified with a tolerance of ±100 ppm. The worst case frequency difference between

any transmit and receive clock will be 200 ppm.

To ensure interoperability between drivers and receivers of different vendors and technologies, AC

coupling at the receiver input must be used.

17.1 DC Requirements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

For more information, see Section 15.2, “SerDes Reference Clocks.”

17.2 AC Requirements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

Table 54 lists the Serial RapidIO SD_REF_CLK and SD_REF_CLK AC requirements.

Table 54. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

REFCLK cycle time

Min

Typ

Max

Unit

Comments

t

—

10(8)

—

ns 8 ns applies only to serial

RapidIO with 125-MHz reference

clock

REF

t

REFCLK cycle-to-cycle jitter. Difference in the

period of any two adjacent REFCLK cycles.

—

80

40

ps

—

REFCJ

Phase jitter. Deviation in edge location with

respect to mean edge location.

–40

ps

—

REFPJ

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17.3 Signal Definitions

LP-serial links use differential signaling. This section defines terms used in the description and

specification of differential signals. Figure 51 shows how the signals are defined. The figures show

waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal

swings between A volts and B volts where A > B. Using these waveforms, the definitions are as follows:

1. The transmitter output signals and the receiver input signals TD, TD, RD, and RD each have a

peak-to-peak swing of A – B volts.

2. The differential output signal of the transmitter, V , is defined as V – V .

TD

OD

TD

3. The differential input signal of the receiver, V , is defined as V – V .

RD

ID

RD

4. The differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) volts.

5. The peak value of the differential transmitter output signal and the differential receiver input

signal is A – B volts.

6. The peak-to-peak value of the differential transmitter output signal and the differential receiver

input signal is 2 × (A – B) volts.

TD or RD

A Volts

TD or RD

B Volts

Differential Peak-to-Peak = 2 × (A – B)

Figure 51. Differential Peak–Peak Voltage of Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (current mode logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD and

TD is 500 mVp-p. The differential output signal ranges between 500 and –500 mV. The peak differential

voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVp-p.

17.4 Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the

receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss

can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.

To negate a portion of these effects, equalization can be used. The most common equalization techniques

that can be used are:

•

A passive high pass filter network placed at the receiver. This is often referred to as passive

equalization.

•

The use of active circuits in the receiver. This is often referred to as adaptive equalization.

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17.5 Explanatory Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long- and short-run interfaces at three

baud rates (a total of six cases) are described.

The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified

in Clause 47 of IEEE 802.3ae-2002.

XAUI has similar application goals to Serial RapidIO, as described in Section 8.1. The goal of this

standard is that electrical designs for Serial RapidIO can reuse electrical designs for XAUI, suitably

modified for applications at the baud intervals and reaches described herein.

17.6 Transmitter Specifications

LP-serial transmitter electrical and timing specifications are stated in the text and tables of this section.

The differential return loss, S11, of the transmitter in each case shall be better than:

•

–10 dB for (baud frequency)/10 < Freq(f) < 625 MHz, and

–10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ baud frequency

The reference impedance for the differential return loss measurements is 100-Ω resistive. Differential

return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components

related to the driver. The output impedance requirement applies to all valid output levels.

It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output,

in each case have a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-serial transmitter between the two signals

that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.

Table 55. Short Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output voltage

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential output voltage

Deterministic jitter

Total jitter

V

500

—

1000

0.17

0.35

1000

mV p-p

UI p-p

ps

—

DIFFPP

J

D

J

—

T

Multiple output skew

S

—

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

800

ps

100 ppm

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Table 56. Short Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output voltage

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential output voltage

Deterministic jitter

Total jitter

V

500

—

1000

0.17

0.35

1000

mV p-p

UI p-p

ps

—

DIFFPP

J

D

T

—

Multiple output skew

S

—

Skew at the transmitter output between lanes of a

multilane link

MO

Unit interval

UI

400

ps

100 ppm

Table 57. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output voltage

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential output voltage

Deterministic jitter

Total jitter

V

500

—

1000

0.17

0.35

1000

mVp-p

UI p-p

ps

—

DIFFPP

J

D

T

—

Multiple output skew

S

—

Skew at the transmitter output between lanes of a

multilane link

MO

Unit interval

UI

320

ps

100 ppm

Table 58. Long Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output voltage

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential output voltage

Deterministic jitter

Total jitter

V

800

—

1600

0.17

0.35

1000

mVp-p

UI p-p

ps

—

DIFFPP

J

D

T

—

Multiple output skew

S

—

Skew at the transmitter output between lanes of a

multilane link

MO

Unit interval

UI

800

ps

100 ppm

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Table 59. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output voltage

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential output voltage

Deterministic jitter

Total jitter

V

800

—

1600

0.17

0.35

1000

mVp-p

UI p-p

ps

—

DIFFPP

J

D

T

—

Multiple output skew

S

—

Skew at the transmitter output between lanes of a

multilane link

MO

Unit interval

UI

400

ps

100 ppm

Table 60. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output voltage

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential output voltage

Deterministic jitter

Total jitter

V

800

—

1600

0.17

0.35

1000

mVp-p

UI p-p

ps

—

DIFFPP

J

D

T

—

Multiple output skew

S

—

Skew at the transmitter output between lanes of a

multilane link

MO

Unit interval

UI

320

ps

100 ppm

For each baud rate at which an LP-serial transmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown

in Figure 52 with the parameters specified in Table 61 when measured at the output pins of the device and

the device is driving a 100-Ω ± 5% differential resistive load. The output eye pattern of an LP-serial

transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need

only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized.

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V

max

min

DIFF

V

DIFF

0

min

–V

DIFF

–V

max

DIFF

0

A

B

1-B

1-A

1

Time in UI

Figure 52. Transmitter Output Compliance Mask

Table 61. Transmitter Differential Output Eye Diagram Parameters

Transmitter Type

V

min (mV)

V

max (mV)

DIFF

A (UI)

B (UI)

DIFF

1.25 GBaud short range

1.25 GBaud long range

2.5 GBaud short range

2.5 GBaud long range

3.125 GBaud short range

3.125 GBaud long range

250

400

250

400

250

400

500

800

500

800

500

800

0.175

0.39

17.7 Receiver Specifications

LP-serial receiver electrical and timing specifications are stated in the text and tables of this section.

Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode

return loss better than 6 dB from 100 MHz to (0.8) × (baud frequency). This includes contributions from

on-chip circuitry, the chip package, and any off-chip components related to the receiver. AC coupling

components are included in this requirement. The reference impedance for return loss measurements is

100-Ω resistive for differential return loss and 25-Ω resistive for common mode.

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Table 62. Receiver AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential input voltage

V

J

200

0.37

0.55

1600

—

mVp-p Measured at receiver

UI p-p Measured at receiver

IN

Deterministic jitter tolerance

D

Combined deterministic and random

jitter tolerance

J

—

DR

1

Total jitter tolerance

J

0.65

—

UI p-p Measured at receiver

T

Multiple input skew

S

24

ns

Skew at the receiver input between lanes

MI

of a multilane link

–12

Bit error rate

Unit interval

Note:

BER

UI

—

10

—

ps

—

800

100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

Table 63. Receiver AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential input voltage

V

J

200

0.37

0.55

1600

—

mVp-p Measured at receiver

UI p-p Measured at receiver

IN

Deterministic jitter tolerance

D

Combined deterministic and random

jitter tolerance

J

—

DR

1

Total jitter tolerance

J

0.65

—

UI p-p Measured at receiver

T

Multiple input skew

S

24

ns

Skew at the receiver input between lanes

MI

of a multilane link

–12

Bit error rate

Unit interval

Note:

BER

UI

—

10

—

400

ps

100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

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Table 64. Receiver AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential input voltage

V

J

200

0.37

0.55

1600

—

mVp-p Measured at receiver

IN

Deterministic jitter tolerance

UI p-p

Measured at receiver

D

Combined deterministic and random

jitter tolerance

J

—

DR

1

Total jitter tolerance

J

0.65

—

UI p-p

ns

Measured at receiver

T

Multiple input skew

S

22

Skew at the receiver input between lanes

of a multilane link

MI

-12

Bit error rate

Unit interval

Note:

BER

UI

—

10

—

320

ps

100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

8.5 UI p-p

0.10 UI p-p

22.1 kHz

1.875 MHz

20 MHz

Frequency

Figure 53. Single Frequency Sinusoidal Jitter Limits

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17.8 Receiver Eye Diagrams

For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the

corresponding bit error rate specification (Table 62, Table 63, Table 64) when the eye pattern of the

receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver

input compliance mask shown in Figure 54 with the parameters specified in Table 65. The eye pattern of

the receiver test signal is measured at the input pins of the receiving device with the device replaced with

a 100-Ω ± 5% differential resistive load.

V

max

DIFF

V

min

DIFF

0

–V

min

–V

max

DIFF

0

1

A

B

1-B

1-A

Time (UI)

Figure 54. Receiver Input Compliance Mask

Table 65. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

V

min

(mV)

V

max

DIFF

(mV)

DIFF

Receiver Type

A (UI)

B (UI)

1.25 GBaud

2.5 GBaud

100

800

0.275

0.400

3.125 GBaud

17.9 Measurement and Test Requirements

Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in

Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly

guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002

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is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std.

802.3ae-2002 is recommended as a reference for additional information on jitter test methods.

17.9.1 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point

at (baud frequency)/1667 is applied to the jitter. The data pattern for template measurements is the

continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-serial

link shall be active in both the transmit and receive directions, and opposite ends of the links shall use

asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane

implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The

–12

amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10

The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V

.

differential. The left and right edges of the template shall be aligned with the mean zero crossing points of

the measured data eye. The load for this test shall be 100-Ω resistive ± 5% differential to 2.5 GHz.

17.9.2 Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud

frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter test

pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-serial link shall be

active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous

clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations

shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured

with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter

tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described

in Annex 48B of IEEE 802.3ae.

17.9.3 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive ± 5%

differential to 2.5 GHz.

17.9.4 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first

producing the sum of deterministic and random jitter defined in Section 17.7, “Receiver Specifications,”

and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening

of the receive template shown in Figure 54 and Table 65. Note that for this to occur, the test signal must

have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)

about the mean zero crossing. Eye template measurement requirements are as defined above. Random

jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade

roll-off below this. The required sinusoidal jitter specified in Section 17.7, “Receiver Specifications,” is

then added to the signal and the test load is replaced by the receiver being tested.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

85

Package Description

18 Package Description

This section details package parameters, pin assignments, and dimensions.

18.1 Package Parameters

The package parameters for both the HiCTE FC-CBGA and FC-PBGA are as provided in Table 66.

Table 66. Package Parameters

1

2

Parameter

Package outline

CBGA

PBGA

29 mm × 29 mm

783

29 mm × 29 mm

783

Interconnects

Ball pitch

1 mm

Ball diameter (typical)

Solder ball

0.6 mm

62% Sn

36% Pb

2% Ag

62% Sn

36% Pb

2% Ag

Solder ball (lead-free)

95% Sn

4.5% Ag

0.5% Cu

96.5% Sn

3.5% Ag

Notes:

1. The HiCTE FC-CBGA package is available on only Version 2.0 of the device.

2. The FC-PBGA package is available on only Version 2.1.1 and 2.1.2 of the

device.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

86

Freescale Semiconductor

Package Description

18.2 Mechanical Dimensions of the HiCTE FC-CBGA and FC-PBGA

with Full Lid

Figure 55 shows the mechanical dimensions and bottom surface nomenclature for both the MPC8548E

HiCTE FC-CBGA and FC-PBGA package with full lid.

Notes:

1. All dimensions are in millimeters.

2. Dimensioning and tolerancing per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement shall exclude any effect of mark on top surface of package.

6. All dimensions are symmetric across the package center lines unless dimensioned otherwise.

7. Package code summary:

•PBGA 8423

•CBGA 5112

Figure 55. Mechanical Dimensions and Bottom Surface Nomenclature of the HiCTE

FC-CBGA and FC-PBGA with Full Lid

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

87

Package Description

18.3 Pinout Listings

NOTE

The DMA_DACK[0:1] and TEST_SEL/TEST_SEL pins must be set to a

proper state during POR configuration. Please refer to the pinlist table of the

individual device for more details.

For MPC8548/47/45, GPIOs are still available on

PCI1_AD[63:32]/PC2_AD[31:0] pins if they are not used for PCI

functionality.

For MPC8545/43, eTSEC does not support 16 bit FIFO mode.

Table 67 provides the pinout listing for the MPC8548E 783 FC-PBGA package.

Table 67. MPC8548E Pinout Listing

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI1 and PCI2 (One 64-Bit or Two 32-Bit)

PCI1_AD[63:32]/PCI2_AD[31:0]

AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18, AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

AC20, AB20, AB22, AC22, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O

OV

17

DD

PCI1_AD[31:0]

AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, AG12, AH12, AB13, AA12,

AC13, AE13, Y14, W13, AG13, V14, AH13,

AC14, Y15, AB15

I/O

17

PCI1_C_BE[7:4]/PCI2_C_BE[3:0]

PCI1_C_BE[3:0]

PCI1_PAR64/PCI2_PAR

PCI1_GNT[4:1]

PCI1_GNT0

AF15, AD14, AE15, AD15

I/O

O

OV

17

DD

AF9, AD11, Y12, Y13

W15

AG6, AE6, AF5, AH5

5, 9, 35

AG5

AF11

AD12

AC12

V13

I/O

—

2

PCI1_IRDY

PCI1_PAR

—

2

PCI1_PERR

PCI1_SERR

2, 4

2

PCI1_STOP

W12

PCI1_TRDY

AG11

2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

88

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

PCI1_REQ[4:1]

AH2, AG4, AG3, AH4

I

OV

—

DD

—

PCI1_REQ0

PCI1_CLK

AH3

I/O

I

OV

—

DD

AH26

39

PCI1_DEVSEL

PCI1_FRAME

PCI1_IDSEL

AH11

I/O

I

2

AE11

2

AG9

—

PCI1_REQ64/PCI2_FRAME

PCI1_ACK64/PCI2_DEVSEL

PCI2_CLK

AF14

I/O

I

2, 5, 10

V15

2

AE28

39

PCI2_IRDY

AD26

I/O

O

2

PCI2_PERR

AD25

2

5, 9, 35

—

PCI2_GNT[4:1]

PCI2_GNT0

AE26, AG24, AF25, AE25

AG25

I/O

I

PCI2_SERR

AD24

2, 4

2

PCI2_STOP

AF24

AD27

PCI2_TRDY

2

PCI2_REQ[4:1]

PCI2_REQ0

AD28, AE27, W17, AF26

AH25

—

I/O

—

DDR SDRAM Memory Interface

MDQ[0:63]

L18, J18, K14, L13, L19, M18, L15, L14, A17,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B4, A2, B1, D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O

GV

—

DD

MECC[0:7]

MDM[0:8]

MDQS[0:8]

MA[0:15]

H13, F13, F11, C11, J13, G13, D12, M12

M17, C16, K17, E16, B6, C4, H4, K1, E13

M15, A16, G17, G14, A5, D3, H1, L2, C13

L17, B16, J16, H14, C6, C2, H3, L4, D13

I/O

O

GV

—

DD

I/O

O

A8, F9, D9, B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11

MBA[0:2]

F7, J7, M11

O

GV

—

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

89

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

MWE

MCAS

E7

H7

O

GV

—

11

—

36

DD

MRAS

L8

O

MCKE[0:3]

MCS[0:3]

MCK[0:5]

MODT[0:3]

MDIC[0:1]

F10, C10, J11, H11

K8, J8, G8, F8

O

H9, B15, G2, M9, A14, F1

J9, A15, G1, L9, B14, F2

E6, K6, L7, M7

A19, B19

O

I/O

Local Bus Controller Interface

LAD[0:31]

E27, B20, H19, F25, A20, C19, E28, J23, A25,

K22, B28, D27, D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O

BV

—

DD

LDP[0:3]

LA[27]

K21, C28, B26, B22

I/O

O

BV

—

DD

H21

5, 9

LA[28:31]

H20, A27, D26, A28

O

5, 7, 9

LCS[0:4]

J25, C20, J24, G26, A26

O

LCS5/DMA_DREQ2

LCS6/DMA_DACK2

LCS7/DMA_DDONE2

LWE0/LBS0/LSDDQM[0]

LWE1/LBS1/LSDDQM[1]

LWE2/LBS2/LSDDQM[2]

LWE3/LBS3/LSDDQM[3]

LALE

D23

G20

I/O

O

1

E21

O

1

G25

O

5, 9

5, 8, 9

5, 9

5, 8, 9

5, 9

—

C23

O

J21

O

A24

O

H24

O

LBCTL

G27

O

LGPL0/LSDA10

LGPL1/LSDWE

LGPL2/LOE/LSDRAS

LGPL3/LSDCAS

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5

F23

O

G22

O

B27

O

F24

O

H23

I/O

O

E26

5, 9

—

LCKE

E24

O

LCLK[0:2]

E23, D24, H22

O

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

90

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

LSYNC_IN

F27

F28

I

BV

—

DD

LSYNC_OUT

O

DMA

DMA_DACK[0:1]

AD3, AE1

O

OV

5, 9,

102

DD

DMA_DREQ[0:1]

DMA_DDONE[0:1]

AD4, AE2

I

OV

—

DD

AD2, AD1

O

Programmable Interrupt Controller

UDE

MCP

AH16

AG19

I

OV

—

DD

IRQ[0:7]

AG23, AF18, AE18, AF20, AG18, AF17, AH24,

AE20

IRQ[8]

AF19

I

OV

—

1

DD

IRQ[9]/DMA_DREQ3

IRQ[10]/DMA_DACK3

IRQ[11]/DMA_DDONE3

IRQ_OUT

AF21

I

AE19

I/O

O

1

AD20

1

AD18

2, 4

Ethernet Management Interface

EC_MDC

EC_MDIO

AB9

O

OV

5, 9

—

DD

AC8

I/O

Gigabit Reference Clock

EC_GTX_CLK125

V11

I

LV

—

DD

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0]

TSEC1_TXD[7:0]

TSEC1_COL

R5, U1, R3, U2, V3, V1, T3, T2

I

O

I

LV

—

5, 9

—

DD

T10, V7, U10, U5, U4, V6, T5, T8

R4

V5

U7

U3

V2

T1

T6

U9

T7

TSEC1_CRS

I/O

O

I

20

—

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_TX_CLK

TSEC1_TX_EN

TSEC1_TX_ER

—

I

—

I

—

I

—

O

30

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

91

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_RXD[7:0]

TSEC2_TXD[7:0]

TSEC2_COL

P2, R2, N1, N2, P3, M2, M1, N3

I

O

I

LV

—

5, 9, 33

—

DD

N9, N10, P8, N7, R9, N5, R8, N6

P1

TSEC2_CRS

R6

I/O

O

I

20

TSEC2_GTX_CLK

TSEC2_RX_CLK

TSEC2_RX_DV

TSEC2_RX_ER

TSEC2_TX_CLK

TSEC2_TX_EN

TSEC2_TX_ER

P6

N4

—

P5

I

R1

I

—

P10

I

—

P7

O

30

R10

5, 9, 33

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3:0]

TSEC3_RXD[3:0]

TSEC3_GTX_CLK

TSEC3_RX_CLK

TSEC3_RX_DV

TSEC3_RX_ER

TSEC3_TX_CLK

TSEC3_TX_EN

V8, W10, Y10, W7

O

I

TV

5, 9, 29

—

DD

Y1, W3, W5, W4

W8

O

I

—

W2

—

W1

I

—

Y2

I

—

V10

I

—

V9

O

30

Three-Speed Ethernet Controller (Gigabit Ethernet 4)

AB8, Y7, AA7, Y8

TSEC4_TXD[3:0]/TSEC3_TXD[7:4]

O

TV

1, 5, 9,

29

DD

TSEC4_RXD[3:0]/TSEC3_RXD[7:4]

TSEC4_GTX_CLK

AA1, Y3, AA2, AA4

AA5

I

O

I

TV

1

—

DD

TSEC4_RX_CLK/TSEC3_COL

TSEC4_RX_DV/TSEC3_CRS

TSEC4_TX_EN/TSEC3_TX_ER

Y5

1

AA3

I/O

O

1, 31

1, 30

AB6

DUART

AB3, AC5

AC6, AD7

AB5, AC7

AB7, AD8

UART_CTS[0:1]

UART_RTS[0:1]

UART_SIN[0:1]

UART_SOUT[0:1]

I

O

I

OV

—

DD

O

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

92

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

2

I C interface

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

AG22

I/O

OV

4, 27

DD

AG21

AG15

AG14

SerDes

SD_RX[0:7]

SD_TX[0:7]

SD_PLL_TPD

SD_REF_CLK

Reserved

M28, N26, P28, R26, W26, Y28, AA26, AB28

I

XV

—

24

3

DD

M27, N25, P27, R25, W25, Y27, AA25, AB27

M22, N20, P22, R20, U20, V22, W20, Y22

O

I

M23, N21, P23, R21, U21, V23, W21, Y23

U28

T28

T27

I

3

AC1, AC3

—

2

Reserved

M26, V28

—

32

34

38

Reserved

M25, V27

Reserved

M20, M21, T22, T23

General-Purpose Output

GPOUT[24:31]

K26, K25, H27, G28, H25, J26, K24, K23

O

BV

—

DD

System Control

AG17

HRESET

HRESET_REQ

SRESET

I

O

I

OV

—

29

—

DD

AG16

AG20

CKSTP_IN

AA9

I

—

CKSTP_OUT

AA8

O

2, 4

Debug

AB2

TRIG_IN

I

OV

—

DD

TRIG_OUT/READY/QUIESCE

AB1

O

6, 9,

19, 29

MSRCID[0:1]

MSRCID[2:4]

AE4, AG2

O

OV

5, 6, 9

DD

AF3, AF1, AF2

6, 19,

29

MDVAL

AE5

O

OV

6

DD

CLK_OUT

AE21

11

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

93

Table 67. MPC8548E Pinout Listing (continued)

Power

Supply

How to Reach Us:

Signal

Home Page:

Package Pin Number

Pin Type

Notes

www.freescale.com

Clock

AF16

Web Support:

RTC

I

OV

—

http://www.freescale.com/support

DD

USA/Europe or Locations Not Listed:

SYSCLK

AH17

OV

DD

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Information in this document is provided solely to enable system and software

JTAG

implementers to use Freescale Semiconductor products. There are no express or

TCK

AG28

I

^{implied copyright licenses granted hereunder to design or fabricate}O^anV^{y integrated}

—

Tempe, Arizona 85284

DD

circuits or integrated circuits based on the information in this document.

1-800-521-6274 or

TDI

AH28

I

OV

12

+1-480-768-2130

Freescale Semiconductor reserves the right to make changes without further notice to

www.freescale.com/support

TDO

AF28

O

OV

11

DD

any products herein. Freescale Semiconductor makes no warranty, representation or

Europe, Middle East, and Africa:

TMS

AH27 I

^{guarantee regarding the suitability of its products for any particular}O^puV^{rpose, nor does}12

DD

Freescale Halbleiter Deutschland GmbH

^{Freescale Semiconductor assume any liability arising out of the application or use of}12

Technical Information Center

TRST

AH23

I

OV

DD

any product or circuit, and specifically disclaims any and all liability, including without

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

limitation consequential or incidental damages. “Typical” parameters which may be

DFT

provided in Freescale Semiconductor data sheets and/or specifications can and do

L1_TSTCLK

AC25

I

OV

25

+46 8 52200080 (English)

DD

vary in different applications and actual performance may vary over time. All operating

+49 89 92103 559 (German)

L2_TSTCLK

AE22

_{parameters, including “Typicals” must be validated}I_{for each customer application by}

OV

25

+33 1 69 35 48 48 (French)

DD

www.freescale.com/support

LSSD_MODE

AH20

^{customer’s technical experts. Freescale Semicond}I^{uctor does not convey any license}

OV

DD

25

Japan:

under its patent rights nor the rights of others. Freescale Semiconductor products are

TEST_SEL

AH14

I

OV

25

Freescale Semiconductor Japan Ltd.

DD

not designed, intended, or authorized for use as components in systems intended for

Headquarters

ARCO Tower 15F

surgical implant into the body, or other applications intended to support or sustain life,

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or for any other application in which the failure of the Freescale Semiconductor product

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THERM0

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Tokyo 153-0064

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THERM1

AH1

—

14

purchase or use Freescale Semiconductor products for any such unintended or

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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

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ASLEEP

_claimA_s,H_co1_s8_{ts, damages, and expenses, and reaso}O_{nable attorney fe}O_esV_{arising out o}9_f,, 19,

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support.asia@freescale.com

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directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Power and Ground Signals

Semiconductor was negligent regarding the design or manufacture of the part.

GND

A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G12, G15, G18, G21, G24, H2,

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Freescale are trademarks or registered trademarks of Freescale

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AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V25, W28, Y24, Y26,

AA24, AA27, AB25, AC28, L21, L23, N22, P20,

R23, T21, U22, V20, W23, Y21, U27

OV

V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG26

Power for PCI

and other

standards

(3.3 V)

OV

—

DD

Document Number: MPC8548EEC

Rev. 5

10/2009

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Notes

Signal

LV

Package Pin Number

Pin Type

Supply

N8, R7, T9, U6

Power for

TSEC1 and

TSEC2

LV

—

DD

(2.5 V, 3.3 V)

TV

W9, Y6

Power for

TSEC3 and

TSEC4

TV

DD

(2,5 V, 3.3 V)

GV

B3, B11, C7, C9, C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2 DRAM

I/O voltage

(1.8 V, 2.5)

GV

DD

BV

C21, C24, C27, E20, E25, G19, G23, H26, J20 Power for local

BV

—

bus (1.8 V,

2.5 V, 3.3 V)

V

M19, N12, N14, N16, N18, P11, P13, P15, P17, Power for core

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

V

DD

(1.1 V)

SV

XV

L25, L27, M24, N28, P24, P26, R24, R27, T25, CorePower for

SV

XV

DD

V24, V26, W24, W27, Y25, AA28, AC27

SerDes

transceivers

(1.1 V)

L20, L22, N23, P21, R22, T20, U23, V21, W22, Pad Power for

—

Y20

SerDes

transceivers

(1.1 V)

AVDD_LBIU

AVDD_PCI1

AVDD_PCI2

J28

Power for local

bus PLL

—

26

(1.1 V)

AH21

AH22

PowerforPCI1

PLL

—

(1.1 V)

PowerforPCI2

PLL

(1.1 V)

AVDD_CORE

AVDD_PLAT

AVDD_SRDS

AH15

AH19

U25

Powerfore500

PLL (1.1 V)

—

26

Power for CCB

PLL (1.1 V)

Power for

SRDSPLL

(1.1 V)

SENSEVDD

SENSEVSS

M14

M16

O

V

13

DD

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

95

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Analog Signals

MVREF

A18

I

MVREF

—

Reference

voltage signal

for DDR

SD_IMP_CAL_RX

SD_IMP_CAL_TX

SD_PLL_TPA

L28

AB26

U26

I

200Ω to

—

24

GND

I

100Ω to

GND

O

—

Notes:

1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the

local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.

2. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV

3. A valid clock must be provided at POR if TSEC4_TXD[2] is set = 1.

4. This pin is an open drain signal.

.

DD

5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the

signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at

reset, then a pullup or active driver is needed.

6. Treat these pins as no connects (NC) unless using debug address functionality.

7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down

resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”

8. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-kΩ

pull-up or pull-down resistors. See the Section 19.3, “e500 Core PLL Ratio.”

9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.

10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI

operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit

PCI device. Refer to the PCI Specification.

11.This output is actively driven during reset rather than being three-stated during reset.

12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13.These pins are connected to the V /GND planes internally and may be used by the core power supply to improve tracking

DD

and regulation.

14.Internal thermally sensitive resistor.

15.No connections should be made to these pins if they are not used.

16.These pins are not connected for any use.

17.PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OV when using

DD

64-bit buffer mode (pins PCI_AD[63:32] and PCI1_C_BE[7:4]).

19.If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state

during reset.

20.This pin is only an output in FIFO mode when used as Rx flow control.

24.Do not connect.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

96

Freescale Semiconductor

Package Description

Table 67. MPC8548E Pinout Listing (continued)

Package Pin Number Pin Type

Power

Notes

Signal

Supply

25.These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OV for normal machine operation.

DD

26.Independent supplies derived from board V

.

DD

27.Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OV

.

DD

29. The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], TSEC4_TXD3/TSEC3_TXD7,

HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.

30.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively

driven.

31.This pin is only an output in eTSEC3 FIFO mode when used as Rx flow control.

32.These pins should be connected to XV

.

DD

33.TSEC2_TXD1, TSEC2_TX_ER are multiplexed as cfg_dram_type[0:1]. They must be valid at power-up, even before

HRESET assertion.

34.These pins should be pulled to ground through a 300-Ω ( 10%) resistor.

35.When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled

down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as ‘no

connect’ or terminated through 2–10 kΩ pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not

connected to any other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through

POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is

any other PCI device connected on the bus.

36.MDIC0 is grounded through an 18.2-Ω precision 1% resistor and MDIC1 is connected to GV through an 18.2-Ω precision

DD

1% resistor. These pins are used for automatic calibration of the DDR IOs.

38.These pins should be left floating.

39. If PCI1 or PCI2 is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI1_CLK or PCI2_CLK.

Otherwise the processor will not boot up.

40.These pins should be connected to GND.

101.This pin requires an external 4.7-kΩ resistor to GND.

102.For Rev. 2.x silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for rev. 1.x silicon, the pin values during POR

configuration are don’t care.

103.If these pins are not used as GPINn (general-purpose input), they should be pulled low (to GND) or high (to LV ) through

DD

2–10 kΩ resistors.

104.These should be pulled low to GND through 2–10 kΩ resistors if they are not used.

105.These should be pulled low or high to LV through 2–10 kΩ resistors if they are not used.

DD

106.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b10 during POR configuration; for rev. 1.x silicon, the pin values during POR

configuration are don’t care.

107.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b01 during POR configuration; for rev. 1.x silicon, the pin values during POR

configuration are don’t care.

108.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for rev. 1.x silicon, the pin values during POR

configuration are don’t care.

109.This is a test signal for factory use only and must be pulled down (100 Ω – 1 kΩ) to GND for normal machine operation.

110.These pins should be pulled high to OV through 2–10 kΩ resistors.

DD

111.If these pins are not used as GPINn (general-purpose input), they should be pulled low (to GND) or high (to OV ) through

DD

2–10 kΩ resistors.

112.This pin must not be pulled down during POR configuration.

113.These should be pulled low or high to OV through 2–10 kΩ resistors.

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

97

Package Description

Table 68 provides the pin-out listing for the MPC8547E 783 FC-PBGA package.

NOTE

All note references in the following table use the same numbers as those for

Table 67. The reader should refer to Table 67 for the meanings of these

notes.

Table 68. MPC8547E Pinout Listing

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI1 (One 64-Bit or One 32-Bit)

PCI1_AD[63:32]

AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18, AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

AC20, AB20, AB22, AC22, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O

OV

17

DD

PCI1_AD[31:0]

AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, AG12, AH12, AB13, AA12,

AC13, AE13, Y14, W13, AG13, V14, AH13,

AC14, Y15, AB15

I/O

17

PCI1_C_BE[7:4]

PCI1_C_BE[3:0]

PCI1_PAR64

PCI1_GNT[4:1]

PCI1_GNT0

PCI1_IRDY

AF15, AD14, AE15, AD15

I/O

O

OV

17

DD

AF9, AD11, Y12, Y13

17

W15

—

AG6, AE6, AF5, AH5

5, 9, 35

AG5

AF11

I/O

I

—

2

PCI1_PAR

AD12

—

PCI1_PERR

PCI1_SERR

PCI1_STOP

PCI1_TRDY

PCI1_REQ[4:1]

PCI1_REQ0

PCI1_CLK

AC12

2

V13

2, 4

W12

2

AG11

2

AH2, AG4, AG3, AH4

AH3

—

I/O

I

—

AH26

39

PCI1_DEVSEL

PCI1_FRAME

PCI1_IDSEL

PCI1_REQ64

PCI1_ACK64

Reserved

AH11

I/O

I

2

AE11

2

AG9

—

AF14

I/O

—

2, 5,10

V15

2

AE28

—

Reserved

AD26

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

98

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

Reserved

cfg_pci1_clk

Reserved

AD25

—

I

—

2

AE26

AG24

OV

5

DD

AF25

—

101

2

AE25

AG25

2

AD24

2

AF24

AD27

2

AD28, AE27, W17, AF26

AH25

2

DDR SDRAM Memory Interface

MDQ[0:63]

L18, J18, K14, L13, L19, M18, L15, L14, A17,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B4, A2, B1, D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O

GV

—

DD

MECC[0:7]

MDM[0:8]

MDQS[0:8]

MA[0:15]

H13, F13, F11, C11, J13, G13, D12, M12

M17, C16, K17, E16, B6, C4, H4, K1, E13

M15, A16, G17, G14, A5, D3, H1, L2, C13

L17, B16, J16, H14, C6, C2, H3, L4, D13

I/O

O

GV

—

DD

I/O

O

A8, F9, D9, B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11

MBA[0:2]

MWE

F7, J7, M11

E7

O

GV

—

11

—

36

DD

MCAS

H7

O

MRAS

L8

O

MCKE[0:3]

MCS[0:3]

MCK[0:5]

MODT[0:3]

MDIC[0:1]

F10, C10, J11, H11

K8, J8, G8, F8

H9, B15, G2, M9, A14, F1

J9, A15, G1, L9, B14, F2

E6, K6, L7, M7

A19, B19

O

I/O

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

99

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Local Bus Controller Interface

LAD[0:31]

E27, B20, H19, F25, A20, C19, E28, J23, A25,

K22, B28, D27, D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O

BV

—

DD

LDP[0:3]

LA[27]

K21, C28, B26, B22

I/O

O

I/O

O

I/O

O

I

BV

—

5, 9

5, 7, 9

—

DD

H21

LA[28:31]

H20, A27, D26, A28

LCS[0:4]

J25, C20, J24, G26, A26

LCS5/DMA_DREQ2

LCS6/DMA_DACK2

LCS7/DMA_DDONE2

LWE0/LBS0/LSDDQM[0]

LWE1/LBS1/LSDDQM[1]

LWE2/LBS2/LSDDQM[2]

LWE3/LBS3/LSDDQM[3]

LALE

D23

G20

1

E21

1

G25

5, 9

5, 8, 9

5, 9

5, 8, 9

5, 9

—

C23

J21

A24

H24

LBCTL

G27

LGPL0/LSDA10

LGPL1/LSDWE

LGPL2/LOE/LSDRAS

LGPL3/LSDCAS

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5

F23

G22

B27

F24

H23

E26

5, 9

—

LCKE

E24

LCLK[0:2]

E23, D24, H22

F27

—

LSYNC_IN

—

LSYNC_OUT

F28

O

—

DMA

AD3, AE1

DMA_DACK[0:1]

O

OV

5, 9,

107

DD

DMA_DREQ[0:1]

DMA_DDONE[0:1]

AD4, AE2

I

OV

—

DD

AD2, AD1

O

Programmable Interrupt Controller

UDE

MCP

AH16

AG19

I

OV

—

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

100

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

IRQ[0:7]

AG23, AF18, AE18, AF20, AG18, AF17, AH24,

AE20

I

OV

—

DD

IRQ[8]

AF19

I

OV

—

1

DD

IRQ[9]/DMA_DREQ3

IRQ[10]/DMA_DACK3

IRQ[11]/DMA_DDONE3

IRQ_OUT

AF21

I

AE19

I/O

O

1

AD20

1

AD18

2, 4

Ethernet Management Interface

EC_MDC

EC_MDIO

AB9

O

OV

5, 9

—

DD

AC8

I/O

Gigabit Reference Clock

EC_GTX_CLK125

V11

I

LV

—

DD

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0]

TSEC1_TXD[7:0]

TSEC1_COL

R5, U1, R3, U2, V3, V1, T3, T2

I

O

I

LV

—

5, 9

—

DD

T10, V7, U10, U5, U4, V6, T5, T8

R4

TSEC1_CRS

V5

I/O

O

I

20

—

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_TX_CLK

TSEC1_TX_EN

TSEC1_TX_ER

U7

U3

—

V2

I

—

T1

I

—

T6

I

—

U9

O

30

—

T7

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_RXD[7:0]

TSEC2_TXD[7:0]

TSEC2_COL

P2, R2, N1, N2, P3, M2, M1, N3

I

O

I

LV

—

5, 9, 33

—

DD

N9, N10, P8, N7, R9, N5, R8, N6

P1

R6

P6

TSEC2_CRS

I/O

O

I

20

TSEC2_GTX_CLK

TSEC2_RX_CLK

TSEC2_RX_DV

TSEC2_RX_ER

TSEC2_TX_CLK

TSEC2_TX_EN

—

N4

P5

—

I

—

R1

P10

P7

I

—

I

—

O

30

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

101

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

TSEC2_TX_ER

R10

O

LV

5, 9, 33

DD

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3:0]

TSEC3_RXD[3:0]

TSEC3_GTX_CLK

TSEC3_RX_CLK

TSEC3_RX_DV

TSEC3_RX_ER

TSEC3_TX_CLK

TSEC3_TX_EN

V8, W10, Y10, W7

O

I

TV

5, 9, 29

—

DD

Y1, W3, W5, W4

W8

O

I

—

W2

—

W1

I

—

Y2

I

—

V10

I

—

V9

O

30

Three-Speed Ethernet Controller (Gigabit Ethernet 4)

AB8, Y7, AA7, Y8

TSEC4_TXD[3:0]/TSEC3_TXD[7:4]

O

TV

1, 5, 9,

29

DD

TSEC4_RXD[3:0]/TSEC3_RXD[7:4]

TSEC4_GTX_CLK

AA1, Y3, AA2, AA4

AA5

I

O

I

TV

1

DD

TSEC4_RX_CLK/TSEC3_COL

TSEC4_RX_DV/TSEC3_CRS

TSEC4_TX_EN/TSEC3_TX_ER

Y5

1

AA3

I/O

O

1, 31

1, 30

AB6

DUART

AB3, AC5

AC6, AD7

AB5, AC7

AB7, AD8

UART_CTS[0:1]

UART_RTS[0:1]

UART_SIN[0:1]

UART_SOUT[0:1]

I

O

I

OV

—

DD

O

2

I C Interface

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

AG22

AG21

I/O

OV

4, 27

DD

AG15

AG14

SerDes

SD_RX[0:3]

SD_TX[0:3]

Reserved

M28, N26, P28, R26

M27, N25, P27, R25

M22, N20, P22, R20

M23, N21, P23, R21

W26, Y28, AA26, AB28

W25, Y27, AA25, AB27

I

XV

—

40

DD

I

O

—

Reserved

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

102

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

Reserved

U20, V22, W20, Y22

—

O

I

—

15

24

—

2

U21, V23, W21, Y23

SD_PLL_TPD

SD_REF_CLK

Reserved

U28

XV

DD

T28

XV

T27

I

AC1, AC3

—

Reserved

M26, V28

—

32

34

38

Reserved

M25, V27

Reserved

M20, M21, T22, T23

General-Purpose Output

GPOUT[24:31]

K26, K25, H27, G28, H25, J26, K24, K23

O

BV

—

DD

System Control

AG17

HRESET

HRESET_REQ

SRESET

I

O

I

OV

—

29

—

DD

AG16

AG20

CKSTP_IN

AA9

I

—

CKSTP_OUT

AA8

O

2, 4

Debug

AB2

TRIG_IN

I

OV

—

DD

TRIG_OUT/READY/QUIESCE

AB1

O

6, 9,

19, 29

MSRCID[0:1]

MSRCID[2:4]

AE4, AG2

O

OV

5, 6, 9

DD

AF3, AF1, AF2

6, 19,

29

MDVAL

AE5

O

OV

6

DD

CLK_OUT

AE21

Clock

AF16

AH17

JTAG

AG28

AH28

AF28

AH27

AH23

11

RTC

I

OV

—

DD

SYSCLK

TCK

TDI

I

OV

—

12

11

12

DD

TDO

TMS

TRST

O

I

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

103

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

DFT

L1_TSTCLK

L2_TSTCLK

LSSD_MODE

TEST_SEL

AC25

I

OV

25

DD

AE22

AH20

AH14

Thermal Management

AG1

THERM0

THERM1

—

14

AH1

—

Power Management

AH18

ASLEEP

GND

O

OV

9, 19,

29

DD

Power and Ground Signals

A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T18,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19, AA6, AA14, AA17,

AA22, AA23, AB4, AC2, AC11, AC19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V25, W28, Y24, Y26,

AA24, AA27, AB25, AC28, L21, L23, N22, P20,

R23, T21, U22, V20, W23, Y21, U27

—

OV

V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG26

Power for PCI

and other

standards

(3.3 V)

OV

—

DD

LV

N8, R7, T9, U6

Power for

TSEC1 and

TSEC2

LV

DD

(2.5 V, 3.3 V)

TV

W9, Y6

Power for

TSEC3 and

TSEC4

TV

DD

(2,5 V, 3.3 V)

GV

B3, B11, C7, C9, C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2 DRAM

I/O voltage

(1.8 V, 2.5 V)

GV

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

104

Package Description

Table 68. MPC8547E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

BV

C21, C24, C27, E20, E25, G19, G23, H26, J20 Power for local

BV

—

DD

bus (1.8 V,

2.5 V, 3.3 V)

V

M19, N12, N14, N16, N18, P11, P13, P15, P17, Power for core

V

DD

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

(1.1 V)

SV

XV

L25, L27, M24, N28, P24, P26, R24, R27, T25, Core power for

SV

XV

DD

V24, V26, W24, W27, Y25, AA28, AC27

SerDes

transceivers

(1.1 V)

L20, L22, N23, P21, R22, T20, U23, V21, W22, Pad Power for

—

Y20

SerDes

transceivers

(1.1 V)

AVDD_LBIU

AVDD_PCI1

AVDD_PCI2

J28

Power for local

bus PLL

—

26

(1.1 V)

AH21

AH22

PowerforPCI1

PLL

—

(1.1 V)

PowerforPCI2

PLL

(1.1 V)

AVDD_CORE

AVDD_PLAT

AVDD_SRDS

AH15

AH19

U25

Powerfore500

PLL (1.1 V)

—

26

Power for CCB

PLL (1.1 V)

Power for

SRDSPLL

(1.1 V)

SENSEVDD

SENSEVSS

M14

M16

O

V

13

DD

—

Analog Signals

A18

MVREF

I

MVREF

—

Reference

voltage signal

for DDR

SD_IMP_CAL_RX

SD_IMP_CAL_TX

SD_PLL_TPA

L28

AB26

U26

I

200 Ω to

—

24

GND

I

100 Ω to

GND

O

—

Note: All note references in this table use the same numbers as those for Table 67. The reader should refer to Table 67 for the

meanings of these notes.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

105

Package Description

Table 69 provides the pin-out listing for the MPC8545E 783 FC-PBGA package.

NOTE

All note references in the following table use the same numbers as those for

Table 67. The reader should refer to Table 67 for the meanings of these

notes.

Table 69. MPC8545E Pinout Listing

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI1 and PCI2 (One 64-Bit or Two 32-Bit)

PCI1_AD[63:32]/PCI2_AD[31:0]

AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18, AC17, AD16, AE16,

Y17, AC18, AB18, AA19, AB19, AB21, AA20,

AC20, AB20, AB22, AC22, AD21, AB23, AF23,

AD23, AE23, AC23, AC24

I/O

OV

17

DD

PCI1_AD[31:0]

AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, AG12, AH12, AB13, AA12,

AC13, AE13, Y14, W13, AG13, V14, AH13,

AC14, Y15, AB15

I/O

17

PCI1_C_BE[7:4]/PCI2_C_BE[3:0]

PCI1_C_BE[3:0]

PCI1_PAR64/PCI2_PAR

PCI1_GNT[4:1]

PCI1_GNT0

AF15, AD14, AE15, AD15

I/O

O

OV

17

DD

AF9, AD11, Y12, Y13

17

W15

—

AG6, AE6, AF5, AH5

5, 9, 35

AG5

AF11

I/O

I

—

PCI1_IRDY

2

PCI1_PAR

AD12

—

PCI1_PERR

AC12

2

PCI1_SERR

V13

2, 4

PCI1_STOP

W12

2

PCI1_TRDY

AG11

2

PCI1_REQ[4:1]

PCI1_REQ0

AH2, AG4, AG3, AH4

AH3

—

I/O

I

—

PCI1_CLK

AH26

39

PCI1_DEVSEL

PCI1_FRAME

AH11

I/O

I

2

AE11

2

PCI1_IDSEL

AG9

—

PCI1_REQ64/PCI2_FRAME

PCI1_ACK64/PCI2_DEVSEL

PCI2_CLK

AF14

I/O

I

2, 5, 10

V15

2

39

2

AE28

PCI2_IRDY

AD26

I/O

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

106

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

PCI2_PERR

PCI2_GNT[4:1]

PCI2_GNT0

PCI2_SERR

PCI2_STOP

PCI2_TRDY

PCI2_REQ[4:1]

PCI2_REQ0

AD25

I/O

O

OV

2

5, 9, 35

—

DD

AE26, AG24, AF25, AE25

AG25

I/O

I

AD24

2,4

2

AF24

AD27

2

AD28, AE27, W17, AF26

AH25

—

I/O

—

DDR SDRAM Memory Interface

MDQ[0:63]

L18, J18, K14, L13, L19, M18, L15, L14, A17,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B4, A2, B1, D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O

GV

—

DD

MECC[0:7]

MDM[0:8]

MDQS[0:8]

MA[0:15]

H13, F13, F11, C11, J13, G13, D12, M12

M17, C16, K17, E16, B6, C4, H4, K1, E13

M15, A16, G17, G14, A5, D3, H1, L2, C13

L17, B16, J16, H14, C6, C2, H3, L4, D13

I/O

O

GV

—

DD

I/O

O

A8, F9, D9, B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11

MBA[0:2]

MWE

F7, J7, M11

E7

O

GV

—

11

—

36

DD

MCAS

H7

O

MRAS

L8

O

MCKE[0:3]

MCS[0:3]

MCK[0:5]

MODT[0:3]

MDIC[0:1]

F10, C10, J11, H11

K8, J8, G8, F8

H9, B15, G2, M9, A14, F1

J9, A15, G1, L9, B14, F2

E6, K6, L7, M7

A19, B19

O

I/O

Local Bus Controller Interface

LAD[0:31]

LDP[0:3]

E27, B20, H19, F25, A20, C19, E28, J23, A25,

K22, B28, D27, D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O

BV

—

DD

K21, C28, B26, B22

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

107

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

LA[27]

LA[28:31]

H21

O

I/O

O

I/O

O

I

BV

5, 9

5, 7, 9

—

DD

H20, A27, D26, A28

LCS[0:4]

J25, C20, J24, G26, A26

LCS5/DMA_DREQ2

LCS6/DMA_DACK2

LCS7/DMA_DDONE2

LWE0/LBS0/LSDDQM[0]

LWE1/LBS1/LSDDQM[1]

LWE2/LBS2/LSDDQM[2]

LWE3/LBS3/LSDDQM[3]

LALE

D23

G20

1

E21

1

G25

5, 9

5, 8, 9

5, 9

5, 8, 9

5, 9

—

C23

J21

A24

H24

LBCTL

G27

LGPL0/LSDA10

LGPL1/LSDWE

LGPL2/LOE/LSDRAS

LGPL3/LSDCAS

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5

F23

G22

B27

F24

H23

E26

5, 9

—

LCKE

E24

LCLK[0:2]

E23, D24, H22

F27

—

LSYNC_IN

—

LSYNC_OUT

F28

O

—

DMA

AD3, AE1

DMA_DACK[0:1]

O

OV

5, 9,

106

DD

DMA_DREQ[0:1]

DMA_DDONE[0:1]

AD4, AE2

I

OV

—

DD

AD2, AD1

O

Programmable Interrupt Controller

UDE

MCP

AH16

AG19

I

OV

—

DD

IRQ[0:7]

AG23, AF18, AE18, AF20, AG18, AF17, AH24,

AE20

IRQ[8]

AF19

AF21

AE19

I

OV

—

1

DD

IRQ[9]/DMA_DREQ3

IRQ[10]/DMA_DACK3

I/O

1

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

108

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

IRQ[11]/DMA_DDONE3

IRQ_OUT

AD20

I/O

O

OV

1

DD

AD18

2, 4

Ethernet Management Interface

EC_MDC

EC_MDIO

AB9

O

OV

5, 9

—

DD

AC8

I/O

Gigabit Reference Clock

EC_GTX_CLK125

V11

I

LV

—

DD

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0]

TSEC1_TXD[7:0]

TSEC1_COL

TSEC1_CRS

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_TX_CLK

TSEC1_TX_EN

TSEC1_TX_ER

GPIN[0:7]

R5, U1, R3, U2, V3, V1, T3, T2

I

O

I

LV

—

5, 9

—

DD

T10, V7, U10, U5, U4, V6, T5, T8

R4

V5

I/O

O

I

20

U7

—

U3

—

V2

I

—

T1

I

—

T6

I

—

U9

O

I

30

T7

—

P2, R2, N1, N2, P3, M2, M1, N3

103

—

GPOUT[0:5]

N9, N10, P8, N7, R9, N5

O

—

I

cfg_dram_type0/GPOUT6

GPOUT7

R8

5, 9

—

N6

Reserved

P1

—

104

15

Reserved

R6

—

Reserved

P6

Reserved

N4

105

104

105

15

FIFO1_RXC2

Reserved

P5

LV

DD

R1

—

O

I

—

Reserved

P10

FIFO1_TXC2

cfg_dram_type1

P7

LV

DD

R10

LV

5

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

V8, W10, Y10, W7

TSEC3_TXD[3:0]

O

TV

5, 9, 29

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

109

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

TSEC3_RXD[3:0]

TSEC3_GTX_CLK

TSEC3_RX_CLK

TSEC3_RX_DV

TSEC3_RX_ER

TSEC3_TX_CLK

TSEC3_TX_EN

TSEC3_TXD[7:4]

TSEC3_RXD[7:4]

Reserved

Y1, W3, W5, W4

I

O

I

TV

—

DD

W8

W2

—

W1

Y2

I

—

I

—

V10

I

—

V9

O

I

30

AB8, Y7, AA7, Y8

AA1, Y3, AA2, AA4

AA5

5, 9, 29

—

I

—

15

TSEC3_COL

Y5

TV

—

DD

TSEC3_CRS

AA3

I/O

O

31

TSEC3_TX_ER

AB6

—

DUART

AB3, AC5

AC6, AD7

AB5, AC7

AB7, AD8

UART_CTS[0:1]

UART_RTS[0:1]

UART_SIN[0:1]

UART_SOUT[0:1]

I

O

I

OV

—

DD

O

2

I C interface

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

AG22

AG21

I/O

OV

4, 27

DD

AG15

AG14

SerDes

SD_RX[0:3]

SD_TX[0:3]

Reserved

M28, N26, P28, R26

M27, N25, P27, R25

M22, N20, P22, R20

M23, N21, P23, R21

W26, Y28, AA26, AB28

W25, Y27, AA25, AB27

U20, V22, W20, Y22

U21, V23, W21, Y23

U28

I

XV

—

40

15

24

—

DD

I

O

—

O

I

—

Reserved

—

Reserved

SD_PLL_TPD

SD_REF_CLK

XV

DD

T28

XV

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

110

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

SD_REF_CLK

Reserved

T27

I

XV

—

2

DD

AC1, AC3

—

Reserved

M26, V28

—

32

34

38

Reserved

M25, V27

Reserved

M20, M21, T22, T23

General-Purpose Output

GPOUT[24:31]

K26, K25, H27, G28, H25, J26, K24, K23

O

BV

—

DD

System Control

AG17

HRESET

HRESET_REQ

SRESET

I

O

I

OV

—

29

—

DD

AG16

AG20

CKSTP_IN

AA9

I

—

CKSTP_OUT

AA8

O

2, 4

Debug

AB2

TRIG_IN

I

OV

—

DD

TRIG_OUT/READY/QUIESCE

AB1

O

6, 9,

19, 29

MSRCID[0:1]

MSRCID[2:4]

AE4, AG2

O

OV

5, 6, 9

DD

AF3, AF1, AF2

6, 19,

29

MDVAL

AE5

O

OV

6

DD

CLK_OUT

AE21

Clock

AF16

AH17

JTAG

AG28

AH28

AF28

AH27

AH23

DFT

11

RTC

I

OV

—

DD

SYSCLK

TCK

TDI

I

OV

—

12

11

12

DD

TDO

TMS

TRST

O

I

L1_TSTCLK

L2_TSTCLK

LSSD_MODE

AC25

AE22

AH20

I

OV

25

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

111

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

TEST_SEL

AH14

Thermal Management

AG1

I

OV

25

DD

THERM0

THERM1

—

14

AH1

—

Power Management

AH18

ASLEEP

GND

O

OV

9, 19,

29

DD

Power and Ground Signals

A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T18,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19, AA6, AA14, AA17,

AA22, AA23, AB4, AC2, AC11, AC19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V25, W28, Y24, Y26,

AA24, AA27, AB25, AC28, L21, L23, N22, P20,

R23, T21, U22, V20, W23, Y21, U27

—

OV

V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG26

Power for PCI

and other

standards

(3.3 V)

OV

—

DD

LV

N8, R7, T9, U6

Power for

TSEC1 and

TSEC2

LV

DD

(2.5 V, 3.3 V)

TV

W9, Y6

Power for

TSEC3 and

TSEC4

TV

DD

(2,5 V, 3.3 V)

GV

B3, B11, C7, C9, C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2 DRAM

I/O voltage

(1.8 V, 2.5 V)

GV

DD

BV

C21, C24, C27, E20, E25, G19, G23, H26, J20 Power for local

BV

—

bus (1.8 V,

2.5 V, 3.3 V)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

112

Package Description

Table 69. MPC8545E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

V

M19, N12, N14, N16, N18, P11, P13, P15, P17, Power for core

V

—

DD

P19, R12, R14, R16, R18, T11, T13, T15, T17,

T19, U12, U14, U16, U18, V17, V19

(1.1 V)

SV

XV

L25, L27, M24, N28, P24, P26, R24, R27, T25, Core power for

SV

XV

—

DD

V24, V26, W24, W27, Y25, AA28, AC27

SerDes

transceivers

(1.1 V)

L20, L22, N23, P21, R22, T20, U23, V21, W22, Pad power for

—

Y20

SerDes

transceivers

(1.1 V)

AVDD_LBIU

AVDD_PCI1

AVDD_PCI2

J28

Power for local

bus PLL

—

26

(1.1 V)

AH21

AH22

PowerforPCI1

PLL

—

(1.1 V)

PowerforPCI2

PLL

(1.1 V)

AVDD_CORE

AVDD_PLAT

AVDD_SRDS

AH15

AH19

U25

Powerfore500

PLL (1.1 V)

—

26

Power for CCB

PLL (1.1 V)

Power for

SRDSPLL(1.1

V)

SENSEVDD

SENSEVSS

M14

M16

O

V

13

DD

—

Analog Signals

A18

MVREF

I

MVREF

—

Reference

voltage signal

for DDR

SD_IMP_CAL_RX

SD_IMP_CAL_TX

SD_PLL_TPA

L28

AB26

U26

I

200 Ω to

—

24

GND

I

100 Ω to

GND

O

—

Note: All note references in this table use the same numbers as those for Table 67. The reader should refer to Table 67 for the

meanings of these notes.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

113

Package Description

Table 70 provides the pin-out listing for the MPC8543E 783 FC-PBGA package.

NOTE

All note references in the following table use the same numbers as those for

Table 67. The reader should refer to Table 67 for the meanings of these

notes.

Table 70. MPC8543E Pinout Listing

Power

Supply

Signal

Package Pin Number

PCI1 (One 32-Bit)

Pin Type

Notes

Reserved

AB14, AC15, AA15, Y16, W16, AB16, AC16,

AA16, AE17, AA18, W18, AC17, AD16, AE16,

Y17, AC18,

—

110

GPOUT[8:15]

GPIN[8:15]

AB18, AA19, AB19, AB21, AA20, AC20, AB20,

AB22

O

I

OV

—

111

17

DD

AC22, AD21, AB23, AF23, AD23, AE23, AC23,

AC24

PCI1_AD[31:0]

AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,

AH9, AC10, AB10, AD10, AG10, AA10, AH10,

AA11, AB12, AE12, AG12, AH12, AB13, AA12,

AC13, AE13, Y14, W13, AG13, V14, AH13,

AC14, Y15, AB15

I/O

Reserved

PCI1_C_BE[3:0]

Reserved

AF15, AD14, AE15, AD15

—

I/O

—

110

17

110

5, 9, 35

—

AF9, AD11, Y12, Y13

OV

DD

W15

—

PCI1_GNT[4:1]

PCI1_GNT0

PCI1_IRDY

AG6, AE6, AF5, AH5

O

OV

DD

AG5

I/O

I

AF11

2

PCI1_PAR

AD12

—

PCI1_PERR

PCI1_SERR

PCI1_STOP

PCI1_TRDY

PCI1_REQ[4:1]

PCI1_REQ0

PCI1_CLK

AC12

2

V13

2, 4

2

W12

AG11

2

AH2, AG4, AG3, AH4

—

AH3

AH26

AH11

AE11

AG9

I/O

I

—

39

2

PCI1_DEVSEL

PCI1_FRAME

PCI1_IDSEL

cfg_pci1_width

Reserved

I/O

I

2

—

AF14

V15

I/O

—

112

110

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Reserved

cfg_pci1_clk

Reserved

AE28

—

I

—

2

AD26

110

5

AD25

AE26

AG24

OV

DD

AF25

—

101

110

AE25

—

AG25

AD24

AF24

AD27

AD28, AE27, W17, AF26

AH25

DDR SDRAM Memory Interface

MDQ[0:63]

L18, J18, K14, L13, L19, M18, L15, L14, A17,

B17, A13, B12, C18, B18, B13, A12, H18, F18,

J14, F15, K19, J19, H16, K15, D17, G16, K13,

D14, D18, F17, F14, E14, A7, A6, D5, A4, C8,

D7, B5, B4, A2, B1, D1, E4, A3, B2, D2, E3, F3,

G4, J5, K5, F6, G5, J6, K4, J1, K2, M5, M3, J3,

J2, L1, M6

I/O

GV

—

DD

MECC[0:7]

MDM[0:8]

MDQS[0:8]

MA[0:15]

H13, F13, F11, C11, J13, G13, D12, M12

M17, C16, K17, E16, B6, C4, H4, K1, E13

M15, A16, G17, G14, A5, D3, H1, L2, C13

L17, B16, J16, H14, C6, C2, H3, L4, D13

I/O

O

GV

—

DD

I/O

O

A8, F9, D9, B9, A9, L10, M10, H10, K10, G10,

B8, E10, B10, G6, A10, L11

MBA[0:2]

MWE

F7, J7, M11

E7

O

GV

—

11

—

36

DD

MCAS

H7

O

MRAS

L8

O

MCKE[0:3]

MCS[0:3]

MCK[0:5]

MODT[0:3]

MDIC[0:1]

F10, C10, J11, H11

K8, J8, G8, F8

H9, B15, G2, M9, A14, F1

J9, A15, G1, L9, B14, F2

E6, K6, L7, M7

A19, B19

O

I/O

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Local Bus Controller Interface

LAD[0:31]

E27, B20, H19, F25, A20, C19, E28, J23, A25,

K22, B28, D27, D19, J22, K20, D28, D25, B25,

E22, F22, F21, C25, C22, B23, F20, A23, A22,

E19, A21, D21, F19, B21

I/O

BV

—

DD

LDP[0:3]

LA[27]

K21, C28, B26, B22

I/O

O

I/O

O

I/O

O

I

BV

—

5, 9

5, 7, 9

—

DD

H21

LA[28:31]

H20, A27, D26, A28

LCS[0:4]

J25, C20, J24, G26, A26

LCS5/DMA_DREQ2

LCS6/DMA_DACK2

LCS7/DMA_DDONE2

LWE0/LBS0/LSDDQM[0]

LWE1/LBS1/LSDDQM[1]

LWE2/LBS2/LSDDQM[2]

LWE3/LBS3/LSDDQM[3]

LALE

D23

1

G20

1

E21

1

G25

5, 9

5, 8, 9

5, 9

5, 8, 9

5, 9

—

C23

J21

A24

H24

LBCTL

G27

LGPL0/LSDA10

LGPL1/LSDWE

LGPL2/LOE/LSDRAS

LGPL3/LSDCAS

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5

F23

G22

B27

F24

H23

E26

5, 9

—

LCKE

E24

LCLK[0:2]

E23, D24, H22

—

LSYNC_IN

F27

—

LSYNC_OUT

F28

O

—

DMA

DMA_DACK[0:1]

DMA_DREQ[0:1]

DMA_DDONE[0:1]

AD3, AE1

O

I

OV

5, 9, 108

DD

AD4, AE2

—

AD2, AD1

O

Programmable Interrupt Controller

UDE

MCP

AH16

AG19

I

OV

—

DD

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

IRQ[0:7]

AG23, AF18, AE18, AF20, AG18, AF17, AH24,

AE20

I

OV

—

DD

IRQ[8]

AF19

I

OV

—

1

DD

IRQ[9]/DMA_DREQ3

IRQ[10]/DMA_DACK3

IRQ[11]/DMA_DDONE3

IRQ_OUT

AF21

I

AE19

I/O

O

1

AD20

1

AD18

2, 4

Ethernet Management Interface

EC_MDC

EC_MDIO

AB9

O

OV

5, 9

—

DD

AC8

I/O

Gigabit Reference Clock

V11

EC_GTX_CLK125

I

LV

—

DD

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_RXD[7:0]

TSEC1_TXD[7:0]

TSEC1_COL

TSEC1_CRS

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_TX_CLK

TSEC1_TX_EN

TSEC1_TX_ER

GPIN[0:7]

R5, U1, R3, U2, V3, V1, T3, T2

I

LV

—

5, 9

—

DD

T10, V7, U10, U5, U4, V6, T5, T8

O

I

R4

V5

I/O

O

I

20

U7

—

U3

—

V2

I

—

T1

I

—

T6

I

—

U9

O

I

30

T7

—

P2, R2, N1, N2, P3, M2, M1, N3

103

—

GPOUT[0:5]

N9, N10, P8, N7, R9, N5

O

—

I

cfg_dram_type0/GPOUT6

GPOUT7

R8

N6

P1

R6

P6

N4

P5

R1

5, 9

—

Reserved

—

104

15

Reserved

—

Reserved

105

104

FIFO1_RXC2

Reserved

LV

DD

—

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Reserved

FIFO1_TXC2

cfg_dram_type1

P10

P7

—

O

—

105

15

LV

DD

R10

LV

5, 9

Three-Speed Ethernet Controller (Gigabit Ethernet 3)

TSEC3_TXD[3:0]

TSEC3_RXD[3:0]

TSEC3_GTX_CLK

TSEC3_RX_CLK

TSEC3_RX_DV

TSEC3_RX_ER

TSEC3_TX_CLK

TSEC3_TX_EN

TSEC3_TXD[7:4]

TSEC3_RXD[7:4]

Reserved

V8, W10, Y10, W7

O

TV

5, 9, 29

—

DD

Y1, W3, W5, W4

I

O

I

W8

—

W2

—

W1

Y2

I

—

I

—

V10

I

—

V9

O

I

30

AB8, Y7, AA7, Y8

AA1, Y3, AA2, AA4

AA5

5, 9, 29

—

I

—

15

TSEC3_COL

Y5

TV

—

DD

TSEC3_CRS

AA3

I/O

O

31

TSEC3_TX_ER

AB6

—

DUART

AB3, AC5

AC6, AD7

AB5, AC7

AB7, AD8

UART_CTS[0:1]

UART_RTS[0:1]

UART_SIN[0:1]

UART_SOUT[0:1]

I

O

I

OV

—

DD

O

2

I C interface

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

AG22

I/O

OV

4, 27

DD

AG21

AG15

AG14

SerDes

SD_RX[0:7]

SD_TX[0:7]

SD_PLL_TPD

M28, N26, P28, R26, W26, Y28, AA26, AB28

M27, N25, P27, R25, W25, Y27, AA25, AB27

M22, N20, P22, R20, U20, V22, W20, Y22

M23, N21, P23, R21, U21, V23, W21, Y23

U28

I

XV

—

24

DD

I

O

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

SD_REF_CLK

Reserved

T28

I

XV

—

2

DD

T27

I

AC1, AC3

—

Reserved

M26, V28

—

32

34

38

Reserved

M25, V27

Reserved

M20, M21, T22, T23

General-Purpose Output

GPOUT[24:31]

K26, K25, H27, G28, H25, J26, K24, K23

O

BV

—

DD

System Control

AG17

HRESET

HRESET_REQ

SRESET

I

O

I

OV

—

29

—

DD

AG16

AG20

CKSTP_IN

AA9

I

—

CKSTP_OUT

AA8

O

2, 4

Debug

AB2

TRIG_IN

I

OV

—

DD

TRIG_OUT/READY/QUIESCE

AB1

O

6, 9, 19,

29

MSRCID[0:1]

MSRCID[2:4]

MDVAL

AE4, AG2

AF3, AF1, AF2

AE5

O

OV

5, 6, 9

6, 19, 29

6

DD

CLK_OUT

AE21

11

Clock

AF16

RTC

I

OV

—

DD

SYSCLK

AH17

JTAG

TCK

TDI

AG28

I

OV

—

12

11

12

DD

AH28

TDO

TMS

TRST

AF28

O

I

AH27

AH23

I

DFT

L1_TSTCLK

L2_TSTCLK

AC25

I

OV

25

DD

AE22

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

LSSD_MODE

TEST_SEL

AH20

I

OV

25

DD

AH14

Thermal Management

AG1

109

THERM0

THERM1

—

14

AH1

—

Power Management

AH18

ASLEEP

GND

O

OV

9, 19, 29

—

DD

Power and Ground Signals

A11, B7, B24, C1, C3, C5, C12, C15, C26, D8,

D11, D16, D20, D22, E1, E5, E9, E12, E15,

E17, F4, F26, G12, G15, G18, G21, G24, H2,

H6, H8, H28, J4, J12, J15, J17, J27, K7, K9,

K11, K27, L3, L5, L12, L16, N11, N13, N15,

N17, N19, P4, P9, P12, P14, P16, P18, R11,

R13, R15, R17, R19, T4, T12, T14, T16, T18,

U8, U11, U13, U15, U17, U19, V4, V12, V18,

W6, W19, Y4, Y9, Y11, Y19, AA6, AA14, AA17,

AA22, AA23, AB4, AC2, AC11, AC19, AC26,

AD5, AD9, AD22, AE3, AE14, AF6, AF10,

AF13, AG8, AG27, K28, L24, L26, N24, N27,

P25, R28, T24, T26, U24, V25, W28, Y24, Y26,

AA24, AA27, AB25, AC28, L21, L23, N22, P20,

R23, T21, U22, V20, W23, Y21, U27

—

OV

V16, W11, W14, Y18, AA13, AA21, AB11,

AB17, AB24, AC4, AC9, AC21, AD6, AD13,

AD17, AD19, AE10, AE8, AE24, AF4, AF12,

AF22, AF27, AG26

Power for

PCI and

other

standards

(3.3 V)

OV

—

DD

LV

N8, R7, T9, U6

Power for

TSEC1 and

TSEC2

LV

—

DD

(2.5 V, 3.3 V)

TV

W9, Y6

Power for

TSEC3 and

TSEC4

TV

DD

(2,5 V, 3.3 V)

GV

B3, B11, C7, C9, C14, C17, D4, D6, D10, D15,

E2, E8, E11, E18, F5, F12, F16, G3, G7, G9,

G11, H5, H12, H15, H17, J10, K3, K12, K16,

K18, L6, M4, M8, M13

Power for

DDR1 and

DDR2

DRAM I/O

voltage

GV

DD

(1.8 V,2.5 V)

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Package Description

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

BV

C21, C24, C27, E20, E25, G19, G23, H26, J20

Power for

local bus

(1.8 V, 2.5 V,

3.3 V)

BV

—

DD

V

M19, N12, N14, N16, N18, P11, P13, P15, P17,

P19, R12, R14, R16, R18, T11, T13, T15, T17, core (1.1 V)

T19, U12, U14, U16, U18, V17, V19

Power for

V

—

DD

SV

XV

L25, L27, M24, N28, P24, P26, R24, R27, T25, Core power

SV

XV

DD

V24, V26, W24, W27, Y25, AA28, AC27

for SerDes

transceivers

(1.1 V)

L20, L22, N23, P21, R22, T20, U23, V21, W22, Pad power

—

Y20

for SerDes

transceivers

(1.1 V)

AVDD_LBIU

J28

Power for

local bus

PLL

—

26

(1.1 V)

AVDD_PCI1

AVDD_PCI2

AVDD_CORE

AVDD_PLAT

AVDD_SRDS

AH21

AH22

AH15

AH19

U25

Power for

PCI1 PLL

(1.1 V)

—

26

Power for

PCI2 PLL

(1.1 V)

Power for

e500 PLL

(1.1 V)

Power for

CCB PLL

(1.1 V)

Power for

SRDSPLL

(1.1 V)

SENSEVDD

SENSEVSS

M14

M16

O

V

13

DD

—

Analog Signals

A18

MVREF

I

MVREF

—

Reference

voltage

signal for

DDR

SD_IMP_CAL_RX

L28

I

200 Ω ( 1%)

—

to GND

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Clocking

Table 70. MPC8543E Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

SD_IMP_CAL_TX

AB26

I

100 Ω ( 1%)

—

to GND

SD_PLL_TPA

U26

O

AVDD_SRDS

24

Note: All note references in this table use the same numbers as those for Table 67. The reader should refer to Table 67 for the

meanings of these notes.

19 Clocking

This section describes the PLL configuration of the MPC8548E. Note that the platform clock is identical

to the core complex bus (CCB) clock.

19.1 Clock Ranges

Table 71 through Table 73 provide the clocking specifications for the processor cores and Table 74,

through Table 76 provide the clocking specifications for the memory bus.

Table 71. Processor Core Clocking Specifications (MPC8548E and MPC8547E)

Maximum Processor Core Frequency

Characteristic

1000 MHz

1200 MHz

1333 MHz

Unit

Notes

Min

800

Max

Min

800

Max

Min

800

Max

e500 core processor frequency

1000

1200

1333

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 72. Processor Core Clocking Specifications (MPC8545E)

Maximum Processor Core Frequency

Characteristic

800 MHz

1000 MHz

1200 MHz

Unit

Notes

Min

800

Max

Min

800

Max

Min

800

Max

e500 core processor frequency

800

1000

1200

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Clocking

Table 73. Processor Core Clocking Specifications (MPC8543E)

Maximum Processor Core Frequency

Characteristic

800 MHz

1000 MHz

Unit

Notes

Min

Max

Min

800

Max

e500 core processor frequency

800

1000

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 74. Memory Bus Clocking Specifications (MPC8548E and MPC8547E)

Maximum Processor Core Frequency

Characteristic

1000, 1200, 1333 MHz

Unit

Notes

Min

166

Max

Memory bus clock speed

Notes:

266

MHz

1, 2

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.

Table 75. Memory Bus Clocking Specifications (MPC8545E)

Maximum Processor Core Frequency

Characteristic

800, 1000, 1200 MHz

Unit

Notes

Min

166

Max

Memory bus clock speed

Notes:

200

MHz

1, 2

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Clocking

Table 76. Memory Bus Clocking Specifications (MPC8543E)

Maximum Processor Core Frequency

Characteristic

800, 1000 MHz

Unit

Notes

Min

Max

Memory bus clock speed

166

200

MHz

1, 2

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.

19.2 CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform

clock. The frequency of the CCB is set using the following reset signals, as shown in Table 77:

•

SYSCLK input signal

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note

that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB

frequency must equal the DDR data rate.

For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.

Table 77. CCB Clock Ratio

Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio Binary Value of LA[28:31] Signals CCB:SYSCLK Ratio

0000

0001

0010

0011

0100

0101

0110

0111

16:1

Reserved

2:1

1000

1001

1010

1011

1100

1101

1110

1111

8:1

9:1

10:1

3:1

Reserved

12:1

4:1

5:1

20:1

6:1

Reserved

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Clocking

19.3 e500 Core PLL Ratio

Table 78 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This

ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in Table 78.

Table 78. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE, LGPL2

Signals

Binary Value of

LBCTL, LALE, LGPL2

Signals

e500 core:CCB Clock Ratio

000

001

010

011

4:1

9:2

100

101

110

111

2:1

5:2

3:1

7:2

Reserved

3:2

19.4 Frequency Options

19.4.1 Sysclk to Platform Frequency Options

Table 79 shows the expected frequency values for the platform frequency when using a CCB clock to

SYSCLK ratio in comparison to the memory bus clock speed.

Table 79. Frequency Options of SYSCLK with Respect to Memory Bus Speeds

CCB to

SYSCLK (MHz)

SYSCLK Ratio

16.66

25

33.33

41.66

66.66

83

100

111

133.33

Platform/CCB Frequency (MHz)

2

3

333

445

400

533

4

333

400

500

5

333

400

533

415

500

6

8

333

375

417

500

9

10

12

16

20

333

400

533

400

500

333

Note: Due to errata Gen 13 the max sys clk frequency should not exceed 100 MHz if the core clk frequency is below

1200 MHz.

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Thermal

20 Thermal

This section describes the thermal specifications of the MPC8548.

20.1 Thermal for Version 2.0 Silicon HiCTE FC-CBGA with Full Lid

This section describes the thermal specifications for the HiCTE FC-CBGA package for revision 2.0

silicon.

Table 80 shows the package thermal characteristics.

Table 80. Package Thermal Characteristics for HiCTE FC-CBGA

Characteristic

JEDEC Board

Symbol

Value

Unit

Notes

Die junction-to-ambient (natural convection)

Die junction-to-ambient (200 ft/min)

Die junction-to-board

Single-layer board (1s)

Four-layer board (2s2p)

Single-layer board (1s)

Four-layer board (2s2p)

N/A

R

17

12

11

8

°C/W

1, 2

3

JA

JB

θ

3

Die junction-to-case

N/A

0.8

4

JC

θ

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). The cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the

interface layer.

20.2 Thermal for Version 2.1.1 and 2.1.2 Silicon FC-PBGA with Full Lid

This section describes the thermal specifications for the FC-PBGA package for revision 2.1.1 silicon.

Table 81 shows the package thermal characteristics.

Table 81. Package Thermal Characteristics for FC-PBGA

Characteristic

JEDEC Board

Symbol

Value

Unit

Notes

Die junction-to-ambient (natural convection)

Die junction-to-ambient (200 ft/min)

Die junction-to-board

Single-layer board (1s)

Four-layer board (2s2p)

Single-layer board (1s)

Four-layer board (2s2p)

N/A

R

18

13

9

°C/W

1, 2

3

JA

θ

JA

θ

JA

θ

JA

θ

JB

θ

5

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126

System Design Information

Table 81. Package Thermal Characteristics for FC-PBGA (continued)

Characteristic

JEDEC Board

Symbol

Value

Unit

Notes

Die junction-to-case

Notes:

N/A

R

0.8

°C/W

4

JC

θ

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). The cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the

interface layer.

20.3 Heat Sink Solution

Every system application has different conditions that the thermal management solution must solve. As

such, providing a recommended heat sink has not been found to be very useful. When a heat sink is chosen,

give special consideration to the mounting technique. Mounting the heat sink to the printed-circuit board

is the recommended procedure using a maximum of 10 lbs force (45 Newtons) perpendicular to the

package and board. Clipping the heat sink to the package is not recommended.

21 System Design Information

This section provides electrical design recommendations for successful application of the MPC8548E.

21.1 System Clocking

This device includes five PLLs, as follows:

1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The

frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio

configuration bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.”

2. The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e500 core clock and the platform clock is selected using the e500 PLL ratio

configuration bits as described in Section 19.3, “e500 Core PLL Ratio.”

3. The PCI PLL generates the clocking for the PCI bus.

4. The local bus PLL generates the clock for the local bus.

5. There is a PLL for the SerDes block.

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System Design Information

21.2 Power Supply Design

21.2.1 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins

(AV _PLAT, AV _CORE, AV _PCI, AV _LBIU, and AV _SRDS, respectively). The AV

DD

level should always be equivalent to V , and preferably these voltages will be derived directly from V

DD

through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits per PLL power supply as illustrated in Figure 56, one to each of the

AV pins. By providing independent filters to each PLL the opportunity to cause noise injection from

DD

one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize

DD

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

pin, which is on the periphery of the footprint, without the inductance of vias.

DD

Figure 56 through Figure 58 shows the PLL power supply filter circuits.

150 Ω

V

AV _PLAT

DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 56. PLL Power Supply Filter Circuit with PLAT Pins

180 Ω

AV _CORE

DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 57. PLL Power Supply Filter Circuit with CORE Pins

10 Ω

AV _PCI/AV _LBIU

DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 58. PLL Power Supply Filter Circuit with PCI/LBIU Pins

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System Design Information

The AV _SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of

DD

the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the

AV _SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near

DD

the AV _SRDS ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF capacitors,

DD

and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from AV _SRDS to

DD

the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces

should be kept short, wide and direct.

1.0 Ω

SV

AV _SRDS

DD

1

0.003 µF

2.2 µF

GND

Note:

1. An 0805 sized capacitor is recommended for system initial bring-up.

Figure 59. SerDes PLL Power Supply Filter

Note the following:

•

AV _SRDS should be a filtered version of SV

.

DD

Signals on the SerDes interface are fed from the XV power plane.

DD

21.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8548E system, and the device

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each V , TV , BV , OV , GV , and LV pin

DD

of the device. These decoupling capacitors should receive their power from separate V , TV , BV ,

DD

OV , GV , LV , and GND power planes in the PCB, utilizing short low impedance traces to

DD

minimize inductance. Capacitors must be placed directly under the device using a standard escape pattern

as much as possible. If some caps are to be placed surrounding the part it should be routed with large trace

to minimize the inductance.

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors

should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , TV , BV , OV , GV , and LV , planes, to enable quick recharging of the

DD

smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating

to ensure the quick response time necessary. They should also be connected to the power and ground

planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor

for best values, types and quantity of bulk capacitors.

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System Design Information

21.4 SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (SV and XV ) to ensure low

DD

jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is

outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections

from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible

to the supply balls of the device. Where the board has blind vias, these capacitors should be placed

directly below the chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SV and

DD

XV ) to the board ground plane on each side of the device. This should be done for all SerDes

DD

supplies.

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT

tantalum chip capacitor. This should be done for all SerDes supplies.

21.5 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. All unused active low inputs should be tied to V , TV , BV , OV , GV , and LV , as

DD

required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected. Power and ground connections must be made to all external V , TV , BV

,

DD

OV , GV , LV , and GND pins of the device.

DD

21.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8548E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins

2

including I C pins and PIC (interrupt) pins.

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 62. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,

TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1], and TEST_SEL/

TEST_SEL pins must be set to a proper state during POR configuration. Refer to the pinlist table of the

individual device for more details

Refer to the PCI 2.2 specification for all pull ups required for PCI.

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System Design Information

21.7 Output Buffer DC Impedance

The MPC8548E drivers are characterized over process, voltage, and temperature. For all buses, the driver

2

is a push-pull single-ended driver type (open drain for I C).

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV

0

DD

or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 60). The

DD

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals

P

OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each

DD

P

N

other in value. Then, Z = (R + R )/2.

0

P

N

OV

DD

R

N

SW2

SW1

Pad

Data

R

P

OGND

Figure 60. Driver Impedance Measurement

Table 82 summarizes the signal impedance targets. The driver impedances are targeted at minimum V

,

DD

nominal OV , 105°C.

DD

Table 82. Impedance Characteristics

Local Bus, Ethernet, DUART, Control,

Configuration, Power Management

Impedance

PCI

DDR DRAM

Symbol

Unit

R

N

43 Target

25 Target

20 Target

Z

W

0

R

P

Note: Nominal supply voltages. See Table 1, T = 105°C.

j

21.8 Configuration Pin Muxing

The MPC8548E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped

with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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131

System Design Information

the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and

for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input

receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with

minimal signal quality or delay disruption. The default value for all configuration bits treated this way has

been encoded such that a high voltage level puts the device into the default state and external resistors are

needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up

devices.

21.9 JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 62. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but it is provided on all processors built on Power Architecture technology. The

device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary logic

does not interfere with normal chip operation. While the TAP controller can be forced to the reset state

using only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow.

Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the

common on-chip processor (COP), which implements the debug interface to the chip.

The COP function of these processors allow a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic.

The arrangement shown in Figure 62 allows the COP port to independently assert HRESET or TRST,

while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 61, for connection to the target system, and is

based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The

connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features. An inexpensive option can be to leave

the COP header unpopulated until needed.

There is no standardized way to number the COP header; so emulator vendors have issued many different

pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Freescale Semiconductor

System Design Information

use left-to-right then top-to-bottom. Still others number the pins counter-clockwise from pin 1 (as with an

IC). Regardless of the numbering scheme, the signal placement recommended in Figure 61 is common to

all known emulators.

21.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•

TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 62. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wired onto the system in future debug situations.

•

No pull-up/pull-down is required for TDI, TMS, TDO, or TCK.

2

4

1

3

COP_TDO

COP_TDI

NC

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

COP_RUN/STOP

COP_TCK

5

7

6

8

COP_TMS

9

10

12

NC

COP_SRESET

11

KEY

13

15

COP_HRESET

No pin

GND

COP_CHKSTP_OUT

16

Figure 61. COP Connector Physical Pinout

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

133

System Design Information

OV

DD

10 kΩ

6

1

SRESET

HRESET

From Target

Board Sources

(if any)

HRESET

COP_HRESET

13

11

10 kΩ

COP_SRESET

B

A

5

1

TRST

COP_TRST

4

2

4

1

3

2

10 Ω

COP_VDD_SENSE

6

5

6

NC

7

8

COP_CHKSTP_OUT

CKSTP_OUT

15

10 kΩ

9

10

12

3

14

11

10 kΩ

KEY

13

15

COP_CHKSTP_IN

COP_TMS

No pin

CKSTP_IN

TMS

8

9

1

3

16

COP_TDO

COP_TDI

COP_TCK

COP Connector

Physical Pinout

TDO

TDI

7

2

TCK

NC

10

4

12

16

Notes:

1. The COP port and target board should be able to independently assert HRESET and TRST to the processor

in order to fully control the processor as shown here.

2. Populate this with a 10−Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL

testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be

closed to position B.

6. Asserting SRESET causes a machine check interrupt to the e500 core.

Figure 62. JTAG Interface Connection

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System Design Information

21.10 Guidelines for High-Speed Interface Termination

21.10.1 SerDes Interface Entirely Unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in

this section.

The following pins must be left unconnected (float):

•

SD_TX[7:0]

Reserved pins T22, T23, M20, M21

The following pins must be connected to GND:

•

SD_RX[7:0]

SD_REF_CLK

NOTE

It is recommended to power down the unused lane through SRDSCR1[0:7]

register (offset = 0xE_0F08) (This prevents the oscillations and holds the

receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7

accordingly.

Pins V28 and M26 must be tied to XV . Pins V27 and M25 must be tied to GND through a 300-Ω

DD

resistor.

In Rev 2.0 silicon, POR configuration pin cfg_srds_en on TSEC4_TXD[2]/TSEC3_TXD[6] can be used

to power down SerDes block.

21.10.2 SerDes Interface Partly Unused

If only part of the high-speed SerDes interface pins are used, the remaining high-speed serial I/O pins

should be terminated as described in this section.

The following pins must be left unconnected (float) if not used:

•

SD_TX[7:0]

Reserved pins: T22, T23, M20, M21

The following pins must be connected to GND if not used:

•

SD_RX[7:0]

SD_REF_CLK

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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135

Ordering Information

NOTE

It is recommended to power down the unused lane through SRDSCR1[0:7]

register (offset = 0xE_0F08) (this prevents the oscillations and holds the

receiver output in a fixed state) that maps to SERDES lane 0 to lane 7

accordingly.

Pins V28 and M26 must be tied to XV . Pins V27 and M25 must be tied to GND through a 300-Ω

DD

resistor.

21.11 Guideline for PCI Interface Termination

PCI termination if PCI 1 or PCI 2 is not used at all.

Option 1

If PCI arbiter is enabled during POR:

•

All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.

All PCI control pins can be grouped together and tied to OV through a single 10-kΩ resistor.

DD

It is optional to disable PCI block through DEVDISR register after POR reset.

Option 2

If PCI arbiter is disabled during POR:

•

All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied

to OV through a single (or multiple) 10-kΩ resistor(s).

DD

•

All PCI control pins can be grouped together and tied to OV through a single 10-kΩ resistor.

It is optional to disable PCI block through DEVDISR register after POR reset.

DD

21.12 Guideline for LBIU Termination

If the LBIU parity pins are not used, the following is the termination recommendation:

•

For LDP[0:3]—tie them to ground or the power supply rail via a 4.7-kΩ resistor.

For LPBSE—tie it to the power supply rail via a 4.7-kΩ resistor (pull-up resistor).

22 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 22.1, “Part Numbers Fully Addressed by this Document.”

22.1 Part Numbers Fully Addressed by this Document

Table 83 provides the Freescale part numbering nomenclature for the MPC8548E. Note that the individual

part numbers correspond to a maximum processor core frequency. For available frequencies, contact your

local Freescale sales office. In addition to the processor frequency, the part numbering scheme also

includes an application modifier which may specify special application conditions. Each part number also

contains a revision code which refers to the die mask revision number.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

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Freescale Semiconductor

Ordering Information

Table 83. Part Numbering Nomenclature

MPC

nnnnn

t

pp

ff

c

r

Product

Code

Part

Identifier

Processor

Frequency

Core

Frequency

1, 2, 3

Temperature

Package

Silicon Version

4

3

MPC

8548E

Blank = 0 to 105°C

C = –40° to 105°C VU = Pb-free CBGA

PX = PBGA

HX = CBGA

AV = 1500

AU = 1333

AT = 1200

AQ = 1000

J = 533

H = 500

G = 400

Blank = Ver. 2.0

(SVR = 0x80390020)

A = Ver. 2.1.1

5

VT = Pb-free PBGA

B = Ver. 2.1.2

(SVR = 0x80390021)

8548

Blank = Ver. 2.0

(SVR = 0x80310020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80310021)

8547E

8547

AU = 1333

AT = 1200

AQ = 1000

J = 533

G = 400

Blank = Ver. 2.0

(SVR = 0x80390120)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80390121)

Blank = Ver. 2.0

(SVR = 0x80390120)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80310121)

8545E

8545

AT = 1200

AQ = 1000

AN = 800

G = 400

Blank = Ver. 2.0

(SVR = 0x80390220)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80390221)

Blank = Ver. 2.0

(SVR = 0x80310220)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80310221)

8543E

8543

AQ = 1000

AN = 800

Blank = Ver. 2.0

(SVR = 0x803A0020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x803A0021)

Blank = Ver. 2.0

(SVR = 0x80320020)

A = Ver. 2.1.1

B = Ver. 2.1.2

(SVR = 0x80320021)

Notes:

1. See Section 18, “Package Description,” for more information on available package types.

2. The HiCTE FC-CBGA package is available on only Version 2.0 of the device.

3. The FC-PBGA package is available on only Version 2.1.1 and 2.1.2 of the device.

4. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by part number specifications may support other

maximum core frequencies.

5. This speed available only for silicon Version 2.1.1.and 2.1.2

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

137

Ordering Information

22.2 Part Marking

Parts are marked as the example shown in Figure 63.

(F)

MPC8548xxxxxx

TWLYWW

MMMMM CCCCC

YWWLAZ

Notes:

TWLYYWW is final test traceability code.

MMMMM is 5 digit mask number.

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

YWWLAZ is assembly traceability code.

Figure 63. Part Marking for CBGA and PBGA Device

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

138

Freescale Semiconductor

Document Revision History

23 Document Revision History

Table 84 provides a revision history for the MPC8548E hardware specification.

Table 84. Document Revision History

Revision

Date

Substantive Change(s)

5

10/2009 • In Table 27, ”GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to

35/75 for RX_CLK duty cycle.

• Updated tMDKHDX in Table 37, “MII Management AC Timing Specifications.”

• Added a reference to Revision 2.1.2.

• Updated Table 55, “MII Management AC Timing Specifications.”

• Added Section 5.1, “Power-On Ramp Rate.”

1

4

04/2009 • In Table 1, “Absolute Maximum Ratings ,” and in Table 2, “Recommended Operating Conditions,”

moved text, “MII management voltage” from LV /TV to OV , added “Ethernet management” to

DD

OVDD row of input voltage section.

• In Table 5, “SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle

time.

• In Table 36, “MII Management DC Electrical Characteristics,” changed all instances of LV /OV to

DD

OV

.

DD

• Modified Section 15, “High-Speed Serial Interfaces (HSSI),” to reflect that there is only one SerDes.

• Modified DDR clk rate min from 133 to 166 MHz.

• Modified note in Table 71, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.”

• In Table 52, “Differential Transmitter (TX) Output Specifications,” modified equations in Comments

column, and changed all instances of “LO” to “L0.” In addition, added note 8.

• In Table 53, “Differential Receiver (RX) Input Specifications,” modified equations in Comments column,

and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “T

.”

RX-EYE-MEDIAN-to-MAX-JITTER

• Modified Table 79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”

• Added a note on Section 4.1, “System Clock Timing,” to limit the SYSCLK to 100 MHz if the core

frequency is less than 1200 MHz

• In Table 67, “MPC8548E Pinout ListingTable 68, “MPC8547E Pinout ListingTable 69, “MPC8545E

Pinout ListingTable 70, “MPC8543E Pinout Listing,” added note 5 to LA[28:31].

• Added note to Table 79, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

139

Document Revision History

Table 84. Document Revision History (continued)

Substantive Change(s)

Revision

Date

3

01/2009 • [Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.” Changed

minimum frequency equation to be 527 MHz for PCI x8.

• In Table 5, added note 7.

• Section 4.5, “Platform to FIFO Restrictions.” Changed platform clock frequency to 4.2.

• Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics.” Added MII after GMII

and add ‘or 2.5 V’ after 3.3 V.

• In Table 23, modified table title to include GMII, MII, RMII, and TBI.

• In Table 24 and Table 25, changed clock period minimum to 5.3.

• In Table 25, added a note.

• In Table 26, Table 27, Table 28, Table 29, and Table 30, removed subtitle from table title.

• In Table 30 and Figure 15, changed all instances of PMA to TSECn.

• In Section 8.2.5, “TBI Single-Clock Mode AC Specifications.” Replaced first paragraph.

• In Table 34, Table 35, Figure 18, and Figure 20, changed all instances of REF_CLK to

TSECn_TX_CLK.

• In Table 36, changed all instances of OV to LV /TV .

DD

• In Table 37, “MII Management AC Timing Specifications,” changed MDC minimum clock pulse width

high from 32 to 48 ns.

• Added new section, Section 15, “High-Speed Serial Interfaces (HSSI).”

• Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.” Added new

paragraph.

• Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.” Added new

paragraph.

• Added information to Figure 63, both in figure and in note.

• Section 21.3, “Decoupling Recommendations.” Modified the recommendation.

• Table 83, “Part Numbering Nomenclature.” In Silicon Version column added Ver. 2.1.2.

2

04/2008 • Removed 1:1 support on Table 78, “e500 Core to CCB Clock Ratio.”

• Removed MDM from Table 18, “DDR SDRAM Input AC Timing Specifications.” MDM is an Output.

• Figure 56, “PLL Power Supply Filter Circuit with PLAT Pins” (AVDD_PLAT).

• Figure 57, “PLL Power Supply Filter Circuit with CORE Pins” (AVDD_CORE).

• Split Figure 58, “PLL Power Supply Filter Circuit with PCI/LBIU Pins,” (formerly called just “PLL Power

Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two

new ones.

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

140

Freescale Semiconductor

Document Revision History

Table 84. Document Revision History (continued)

Substantive Change(s)

Revision

Date

1

10/2007 • Adjusted maximum SYSCLK frequency down in Table 5, “SYSCLK AC Timing Specifications” per

device erratum GEN-13.

• Clarified notes to Table 6, “EC_GTX_CLK125 AC Timing Specifications.”

• Added Section 4.4, “PCI/PCI-X Reference Clock Timing.”

• Clarified descriptions and added PCI/PCI-X to Table 9, “PLL Lock Times.”

• Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in Section 6, “DDR and

DDR2 SDRAM.”

• Clarified Note 4 of Table 19, “DDR SDRAM Output AC Timing Specifications.”

• Clarified the reference clock used in Section 7.2, “DUART AC Electrical Specifications.”

• Corrected V (min) in Table 22, “GMII, MII, RMII, and TBI DC Electrical Characteristics.”

IH

• Corrected V (max) in Table 23, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical

IL

Characteristics.”

• Removed DC parameters from Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 32,

Table 34, and Table 35.

• Corrected V (min) in Table 36, “MII Management DC Electrical Characteristics.”

IH

• Corrected t

(min) in Table 37, “MII Management AC Timing Specifications.”

MDC

• Updated parameter descriptions for t

, t

, and t

in Table 40, “Local Bus

LBIVKH1 LBIVKH2 LBIXKH1

LBIXKH2

Timing Parameters (BV = 3.3 V)—PLL Enabled” and Table 40, “Local Bus Timing Parameters

DD

(BV = 2.5 V)—PLL Enabled.”

DD

• Updated parameter descriptions for t

, t

, and t

in Table 42, “Local Bus

LBIVKH1 LBIVKL2 LBIXKH1

LBIXKL2

Timing Parameters—PLL Bypassed.” Note that t

and t

were previously labeled t

LBIVKL2

LBIXKL2 LBIVKH2

and t

.

LBIXKH2

• Added LUPWAIT signal to Figure 23, “Local Bus Signals (PLL Enabled)” and Figure 24, “Local Bus

Signals (PLL Bypass Mode).”

• Added LGTA signal to Figure 25, Figure 26, Figure 27 and Figure 28.

• Corrected LUPWAIT assertion in Figure 26 and Figure 28.

• Clarified the PCI reference clock in Section 14.2, “PCI/PCI-X AC Electrical Specifications”

• Added Section 17.1, “Package Parameters.”

• Added PBGA thermal information in Section 20.2, “Thermal for Version 2.1.1 and 2.1.2 Silicon

FC-PBGA with Full Lid.”

• Updated.”

• Updated Table 83, “Part Numbering Nomenclature.”

0

07/2007 • Initial Release

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

141

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Document Number: MPC8548EEC

Rev. 5

10/2009


型号：	MPC8548EPXATJB
厂家：	NXP
描述：	32-BIT, 1200MHz, MICROPROCESSOR, PBGA783, 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 时钟外围集成电路
文件：	总142页 (文件大小：1504K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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