MPC9229DT [NXP]
400MHz, OTHER CLOCK GENERATOR, PDSO20, TSSOP-20;
| 型号： | MPC9229DT |
| 厂家： | 
NXP |
| 描述： | 400MHz, OTHER CLOCK GENERATOR, PDSO20, TSSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MPC9229
Rev 2, 05/2004
400 MHz Low Voltage PECL Clock
Synthesizer
MPC9229
The MPC9229 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
400 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
25 MHz to 400 MHz synthesized clock output signal
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
3.3 V power supply
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-02
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP and 20-lead PLCC packaging
32-lead and 20-lead Pb-free Package Available
SiGe Technology
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MC12429
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal
crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz.
Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the
PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 4⋅M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The
PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value must be pro-
grammed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios
(1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially
from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to VCC –2.0 V. The positive supply volt-
age for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs
to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On
the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface.
Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The
serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configura-
tion latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to the programming
section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial
data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
380
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MPC9229
XTAL_IN
XTAL_OUT
Ref
÷ 4
÷ 1
÷ 2
÷ 4
÷ 8
VCO
XTAL
÷ 16
00
01
10
11
fOUT
fOUT
10 – 20 MHz
PLL
800 – 1800 MHz
OE
FB
SYNC
÷ 0 TO ÷ 511
9-BIT M-DIVIDER
TEST
TEST
3
2
9
VCC
M-LATCH
N-LATCH
T-LATCH
LE
P/S
P_LOAD
S_LOAD
0
1
0
1
BITS 3-4
BITS 5-13
BITS 0-2
S_DATA
S_CLOCK
14-BIT SHIFT REGISTER
VCC
M[0:8]
N[1:0]
OE
Figure 1. MPC9229 Logic Diagram
24 23 22 21 20 19 18 17
25
24
23
22
21
20
19
S_CLOCK
N[1]
N[0]
M[8]
M[7]
26
27
18
17
16
15
14
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
NC
GND
TEST
VCC
M[3]
S_DATA
S_LOAD
VCC_PLL
NC
M[2]
28
1
VCC
M[1]
MPC9229
MPC9229
GND
fOUT
fOUT
VCC
M[0]
M[6]
M[5]
M[4]
2
3
4
P_LOAD
OE
NC
13
12
XTAL_IN
XTAL_OUT
1
2
3
4
5
6
7
8
5
6
7
8
9
10
11
Figure 2. MPC9229 28-Lead PLCC Pinout
Figure 3. MPC9229 32-Lead LQFP Pinout
(Top View)
(Top View)
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
381
MPC9229
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
fOUT, fOUT
Analog
Crystal oscillator interface.
Output
LVPECL Differential clock output.
TEST
Output
Input
LVCMOS Test and device diagnosis output.
LVCMOS Serial configuration control input.
S_LOAD
0
1
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low, thus
the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is
state sensitive
S_DATA
S_CLOCK
M[0:8]
Input
Input
Input
0
0
1
LVCMOS Serial configuration data input.
LVCMOS Serial configuration clock input.
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
OE
Input
Input
1
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
LVCMOS Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility of runt
pulses on the fOUT output. OE = L low stops fOUT in the logic low state
(fOUT = L, fOUT = H)
GND
VCC
Supply
Supply
Supply
Supply
Ground Negative power supply (GND).
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation.
VCC_PLL
Supply
Supply
VCC
PLL positive power supply (analog power supply).
Table 2. Output Frequency Range and Pll Post-Divider N
N
Output Division
Output Frequency Range
1
0
0
0
1
2
4
8
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
0
1
1
1
0
1
382
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MPC9229
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VTT
Output Termination Voltage
VCC –2
V
MM
HBM
LU
ESD protection (Machine Model)
ESD protection (Human Body Model)
Latch-Up Immunity
200
2000
200
V
V
mA
pF
CIN
Input Capacitance
4.0
Inputs
θJA
LQFP 32 Thermal resistance junction to ambient
JESD 51-3, single layer test board
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
θJC
LQFP 32 Thermal resistance junction to case
23.0
26.3
°C/W MIL-SPEC 883E
Method 1012.1
Table 4. Absolute Maximum Ratings1
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
VIN
Supply Voltage
–0.3
3.9
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–0.3
–0.3
VCC + 0.3
VCC + 0.3
±20
V
V
VOUT
IIN
IOUT
TS
mA
mA
°C
±50
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS control inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE)
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
2.0
VCC + 0.3
0.8
V
V
LVCMOS
LVCMOS
Input Current1
±200
µA VIN = VCC or GND
2
Differential clock output fOUT
Output High Voltage3
Output Low Voltage3
VOH
VOL
VCC –1.02
VCC –1.95
VCC –0.74
VCC –1.60
V
V
LVPECL
LVPECL
Test and diagnosis output TEST
Output High Voltage3
Output Low Voltage3
VOH
VOL
2.0
V
V
IOH = –0.8 mA
IOL = 0.8 mA
0.55
Supply current
ICC_PLL
Maximum PLL Supply Current
Maximum Supply Current
20
mA VCC_PLL Pins
mA All VCC Pins
ICC
100
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50 Ω to VTT = VCC –2 V.
3. The MPC9229 TEST output levels are compatible to the MC12429 output levels.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
383
MPC9229
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)1
Symbol
Characteristics
Crystal interface frequency range
Min
Typ
Max
Unit
Condition
fXTAL
10
20
MHz
VCO frequency range2
Output Frequency
fVCO
fMAX
800
1600
MHz
N = 00 (÷ 1)
N = 01 (÷ 2)
N = 10 (÷ 4)
N = 11 (÷ 8)
200
100
50
400
200
100
50
MHz
MHz
MHz
MHz
25
DC
Output duty cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
Serial interface programming clock frequency3
fS_CLOCK
tP,MIN
tS
0
10
MHz
ns
Minimum pulse width
Setup Time
(S_LOAD, P_LOAD)
50
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
tJIT(CC)
Cycle-to-cycle jitter
N = 00 (÷ 1)
N = 01 (÷ 2)
N = 10 (÷ 4)
N = 11 (÷ 8)
90
ps
ps
ps
ps
130
160
190
tJIT(PER) Period Jitter
N = 00 (÷ 1)
N = 01 (÷ 2)
N = 10 (÷ 4)
N = 11 (÷ 8)
70
ps
ps
ps
ps
120
140
170
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ M ÷ 4.
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as
test clock in test mode 6. Refer to APPLICATIONS INFORMATION for more details.
384
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MPC9229
PROGRAMMING INTERFACE
Programming the MPC9229
to match the VCO frequency range of 800 to 1600 MHz in order
to achieve stable PLL operation:
Programming the MPC9229 amounts to properly configuring
the internal PLL dividers to produce the desired synthesized
frequency at the output. The output frequency can be
represented by this formula:
MMIN = 4 ⋅ fVCO,MIN ÷ fXTAL and
MMAX = 4 ⋅ fVCO,MAX ÷ fXTAL
(3)
(4)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between M = 200
and M = 400. Table 7 shows the usable VCO frequency and M
divider range for other example input frequencies. Assuming
that a 16 MHz input frequency is used, equation (2) reduces to:
fOUT = (fXTAL ÷ 16) ⋅ (4 ⋅ M) ÷ (4 ⋅ N) or
fOUT = (fXTAL ÷ 16) ⋅ M ÷ N
(1)
(2)
where fXTAL is the crystal frequency, M is the PLL
feedback-divider and N is the PLL post-divider. The input
frequency and the selection of the feedback divider M is limited
by the VCO-frequency range. fXTAL and M must be configured
fOUT = M ÷ N
Table 7. MPC9229 Frequency Operating Range
Output frequency for fXTAL = 16 MHz and for N =
VCO frequency for a crystal interface frequency of
M
M[8:0]
10
12
14
16
18
20
1
2
4
16
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
510
010100000
010101010
010110100
010111110
011001000
011010010
011011100
011100110
011110000
011111010
100000100
100001110
100011000
100100010
100101100
100110110
101000000
101001010
101010100
101011110
101101000
101110010
101111100
110000110
110010000
110011010
110100100
110101110
110111000
111000010
111111110
800
850
810
855
900
950
800
840
900
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
1550
1600
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
185
190
195
200
50
52.5
55
25
945
26.25
27.50
28.75
30
880
990
805
840
920
1035
1080
1125
1170
1215
1260
1305
1350
1395
1440
1485
1530
1575
57.5
60
960
875
100
62.5
65
31.25
32.50
33.75
35
910
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
810
840
945
67.5
70
980
870
1015
1050
1085
1120
1155
1190
1225
1260
1295
1330
1365
1400
1435
1470
1505
1540
1575
72.5
75
36.25
37.5
38.75
40
900
930
77.5
80
800
825
960
990
82.5
85
41.25
42.5
43.75
45
850
1020
1050
1080
1110
1140
1170
1200
1230
1260
1290
1320
1350
1530
875
87.5
90
900
925
92.5
95
46.25
47.5
48.75
50
950
975
97.5
100
1000
1025
1050
1075
1100
1125
1275
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
385
MPC9229
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Example Frequency Calculation for an 16 MHz Input
Frequency
If an output frequency of 131 MHz was desired the following
steps would be taken to identify the appropriate M and N values.
According to Table 8, 131 MHz falls in the frequency set by an
value of 2 so N[1:0] = 01. For N = 2 the output frequency is
fOUT = M ÷ 2 and M = fOUT x 2. Therefore M = 2 x 131 = 262, so
M[8:0] = 100000110. Following this procedure a user can
generate any whole frequency between 25 MHz and 400 MHz.
Note than for N > 2 fractional values of can be realized. The size
of the programmable frequency steps (and thus the indicator of
the fractional output frequencies achievable) will be equal to:
Table 8. Output Frequency Range for fXTAL = 16 MHz
N
fOUT
fOUT Range
fOUT Step
1
0
Value
0
0
1
2
4
8
M
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
1 MHz
500 kHz
250 kHz
125 kHz
0
1
1
1
0
1
M ÷ 2
M ÷ 4
M ÷ 8
fSTEP = fXTAL ÷ 16 ÷ N
APPLICATIONS INFORMATION
useful only for performance verification of the MPC9229 itself.
Using the Parallel and Serial Interface
However the PLL bypass mode may be of interest at the board
level for functional debug. When T[2:0] is set to 110, the
MPC9229 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The N
divider drives the fOUT differential pair and the M counter drives
the TEST output pin. In this mode the S_CLOCK input could be
used for low speed board level functional test or debug.
Bypassing the PLL and driving fOUT directly gives the user more
control on the test clocks sent through the clock tree. Figure 6
shows the functional setup of the PLL bypass mode. Because
the S_CLOCK is a CMOS level, the input frequency is limited to
200 MHz. This means the fastest the fOUT pin can be toggled
via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL
divider is 2 (if N = 1). Note that the M counter output on the
TEST output will not be a 50% duty cycle.
The M and N counters can be loaded either through a parallel
or serial interface. The parallel interface is controlled via the
P_LOAD signal such that a LOW-to-HIGH transition will latch
the information present on the M[8:0] and N[1:0] inputs into the
M and N counters. When the P_LOAD signal is LOW, the input
latches will be transparent and any changes on the M[8:0] and
N[1:0] inputs will affect the fOUT output pair. To use the serial
port, the S_CLOCK signal samples the information on the
S_DATA line and loads it into a 14-bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation to
function. The Test register is loaded with the first three bits, the
N register with the next two and the M register with the final
eight bits of the data stream on the S_DATA input. For each
register the most significant bit is loaded first (T2, N1, and M8).
A pulse on the S_LOAD pin after the shift register is fully loaded
will transfer the divide values into the counters. The
HIGH-to-LOW transition on the S_LOAD input will latch the new
divide values into the counters. Figure 4 illustrates the timing
diagram for both a parallel and a serial load of the MPC9229
synthesizer. M[8:0] and N[1:0] are normally specified once at
power-up through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine-tune the clock as the ability to control the serial interface
becomes available.
Table 9. Test and Debug Configuration for TEST
T[2:0]
TEST Output
T2
T1
T0
14-bit shift register out1
Logic 1
0
0
0
0
0
0
1
1
0
f
XTAL ÷ 16
0
1
1
0
1
0
M-Counter out
fOUT
Using the Test and Diagnosis Output TEST
1
1
1
0
1
1
1
0
1
Logic 0
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
M-Counter out in PLL-bypass mode
f
OUT ÷ 4
1. Clocked out at the rate of S_CLOCK
represents fOUT, the CMOS output is not able to toggle fast
enough for higher output frequencies and should only be used
for test and diagnosis. The T2, T1, and T0 control bits are preset
to ‘000' when P_LOAD is LOW so that the PECL fOUT outputs
are as jitter-free as possible. Any active signal on the TEST
output pin will have detrimental affects on the jitter of the PECL
output pair. In normal operations, jitter specifications are only
guaranteed if the TEST output is static. The serial configuration
port can be used to select one of the alternate functions for this
pin. Most of the signals available on the TEST output pin are
Table 10. Debug Configuration for PLL Bypass1
Output
Configuration
fOUT
S_CLOCK ÷ N
M-Counter out2
TEST
1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode
2. Clocked out at the rate of S_CLOCK ÷ (4 ⋅ N)
386
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MPC9229
S_CLOCK
S_DATA
S_LOAD
T2
M0
T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1
First
Bit
Last
Bit
M[8:0]
N[1:0]
M, N
P_LOAD
Figure 4. Serial Interface Timing Diagram
Power Supply Filtering
RF = 10-15 Ω
CF = 22 µF
The MPC9229 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL pin impacts the device characteristics. The
MPC9229 provides separate power supplies for the digital
circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The
purpose of this design technique is to try and isolate the high
switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a controlled environment
such as an evaluation board, this level of isolation is sufficient.
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies a second level
of isolation may be required. The simplest form of isolation is a
power supply filter on the VCC_PLL pin for the MPC9229.
Figure 5 illustrates a typical power supply filter scheme. The
MPC9229 is most susceptible to noise with spectral content in
the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs to
be met in the final filter design is the DC voltage drop that will
be seen between the VCC supply and the MPC9229 pin of the
MPC9229. From the data sheet the VCC_PLL current (the
current sourced through the VCC_PLL pin) is maximum 20 mA,
assuming that a minimum of 2.835 V must be maintained on the
VCC_PLL pin. The resistor shown in Figure 5 must have a
resistance of 10-15 Ω to meet the voltage drop criteria. The RC
filter pictured will provide a broadband filter with approximately
100:1 attenuation for noise whose spectral content is above
20 kHz. As the noise frequency crosses the series resonant
point of an individual capacitor its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above the
bandwidth of the PLL. Generally, the resistor/capacitor filter will
be cheaper, easier to implement and provide an adequate level
of supply filtering. A higher level of attenuation can be achieved
by replacing the resistor with an appropriate valued inductor. A
1000 µH choke will show a significant impedance at 10 kHz
frequencies and above. Because of the current draw and the
voltage that must be maintained on the VCC_PLL pin, a low DC
resistance inductor is required (less than 15 Ω).
VCC_PLL
MPC9229
VCC
C2
VCC
C1, C2 = 0.01...0.1 µF
C1
Figure 5. VCC_PLL Power Supply Filter
Layout Recommendations
The MPC9229 provides sub-nanosecond output edge rates
and thus a good power supply bypassing scheme is a must.
Figure 6 shows a representative board layout for the MPC9229.
There exists many different potential board layouts and the one
pictured is but one. The important aspect of the layout in
Figure 6 is the low impedance connections between VCC and
GND for the bypass capacitors. Combining good quality general
purpose chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for the
MPC9229 outputs. It is imperative that low inductance chip
capacitors are used; it is equally important that the board layout
does not introduce back all of the inductance saved by using the
leadless capacitors. Thin interconnect traces between the
capacitor and the power plane should be avoided and multiple
large vias should be used to tie the capacitors to the buried
power planes. Fat interconnect and large vias will help to
minimize layout induced inductance and thus maximize the
series resonant point of the bypass capacitors. Note the dotted
lines circling the crystal oscillator connection to the device. The
oscillator is a series resonant circuit and the voltage amplitude
across the crystal is relatively small. It is imperative that no
actively switching signals cross under the crystal as crosstalk
energy coupled to these lines could significantly impact the jitter
of the device. Special attention should be paid to the layout of
the crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Although the MPC9229 has
several design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully differential
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
387
MPC9229
PLL), there still may be applications in which overall
performance is being degraded due to system power supply
noise. The power supply filter and bypass schemes discussed
in this section should be adequate to eliminate power supply
noise related problems in most designs.
close to the MPC9229 as possible to avoid any board level
parasitics. To facilitate co-location surface mount crystals are
recommended, but not required. Because the series resonant
design is affected by capacitive loading on the xtal terminals
loading variation introduced by crystals from different vendors
could be a potential issue. For crystals with a higher shunt
capacitance, it may be required to place a resistance across the
terminals to suppress the third harmonic. Although typically not
required, it is a good idea to layout the PCB with the provision
of adding this external resistor. The resistor value will typically
be between 500 and 1 KΩ.
C1
C1
The oscillator circuit is a series resonant circuit and thus for
optimum performance a series resonant crystal should be used.
Unfortunately most crystals are characterized in a parallel
resonant mode. Fortunately there is no physical difference
between a series resonant and a parallel resonant crystal. The
difference is purely in the way the devices are characterized. As
a result a parallel resonant crystal can be used with the
MPC9229 with only a minor error in the desired frequency. A
parallel resonant mode crystal used in a series resonant circuit
will exhibit a frequency of oscillation a few hundred ppm lower
than specified, a few hundred ppm translates to kHz
inaccuracies. In a general computer application this level of
inaccuracy is immaterial. Table 11 below specifies the
performance requirements of the crystals to be used with the
MPC9229.
1
CF
C2
R1 = 10–15 Ω
C1 = 0.01 µF
C2 = 22 µF
C3 = 0.01 µF
XTAL
= VCC
= GND
= Via
Figure 6. PCB Board Layout Recommendation
for the PLCC28 Package
Table 11. Recommended Crystal Specifications
Parameter
Value
Using the On-Board Crystal Oscillator
Crystal Cut
Resonance
Fundamental AT Cut
The MPC9229 features a fully integrated on-board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability and
eliminates the need for large on chip capacitors. The oscillator
is totally self contained so that the only external component
required is the crystal. As the oscillator is somewhat sensitive to
loading on its inputs the user is advised to mount the crystal as
Series Resonance1
±75 ppm at 25°C
±150 pm 0 to 70°C
0 to 70°C
Frequency Tolerance
Frequency/Temperature Stability
Operating Range
Shunt Capacitance
5 – 7pF
Equivalent Series Resistance (ESR)
Correlation Drive Level
Aging
50 to 80 Ω
100 µW
5 ppm/Yr (First 3 Years)
1. Refer to the accompanying text for series versus parallel resonant
discussion.
388
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
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