MPC9448AC [NXP]
9448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32;
| 型号： | MPC9448AC |
| 厂家： | 
NXP |
| 描述： | 9448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC9448
Rev. 5, 1/2005
Freescale Semiconductor
Technical Data
3.3 V/2.5 V LVCMOS 1:12 Clock
Fanout Buffer
MPC9448
The Freescale Semiconductor, Inc. MPC9448 is a 3.3 V or 2.5 V compatible,
1:12 clock fanout buffer targeted for high performance clock tree applications.
With output frequencies up to 350 MHz and output skews less than 150 ps, the
device meets the needs of most demanding clock applications.
LOW VOLTAGE
3.3 V/2.5 V LVCMOS 1:12
CLOCK FANOUT BUFFER
Features
•
•
•
•
•
•
•
•
•
•
•
•
12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL compatible clock inputs
Maximum clock frequency of 350 MHz
Maximum clock skew of 150 ps
Synchronous output stop in logic low state eliminates output runt pulses
High-impedance output control
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
3.3 V or 2.5 V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range -40°C to +85°C
32-Lead LQFP packaging
32-lead Pb-free package available
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Supports clock distribution in networking, telecommunication and computing
applications
•
Pin and function compatible to MPC948
Functional Description
The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each
output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 Ω terminated
transmission lines on the incident edge. Each output is capable of driving either one parallel terminated or two series terminated
transmission lines.
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribu-
tion systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop
of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force
the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports
a 2.5 V or 3.3 V power supply and an ambient temperature range of -40°C to +85°C. The MPC9448 is pin and function compatible
but performance-enhanced to the MPC948.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
VCC
PCLK
PCLK
24 23 22 21 20 19 18 17
0
CLK
Stop
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
GND
Q8
Q3
VCC
Q2
CCLK
1
VCC
Q9
VCC
GND
Q1
MPC9448
CLK_SEL
GND
Q10
VCC
VCC
Q0
CLK_STOP
SYNC
VCC
GND
GND
1
2
3
4
5
6
7
8
VCC
(All input resistors have a value of 25 kΩ)
OE
Figure 1. Logic Diagram
Figure 2. 32-Lead Pinout (Top View)
Table 1. Function Table
Control
CLK_SEL
OE
Default
0
1
1
1
1
PECL differential input selected
CCLK input selected
Outputs disabled (high-impedance state)(1)
Outputs enabled
Outputs active
CLK_STOP
Outputs synchronously stopped in logic low state
1. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. Pin Configurations
Pin
PCLK, PCLK
CCLK
I/O
Type
LVPECL
Function
Input
Clock signal input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Alternative clock signal input
Clock input select
CLK_SEL
CLK_STOP
OE
Input
Input
Clock output enable/disable
Input
Output enable/disable (high-impedance tristate)
Clock outputs
Q0–11
Output
Supply
Supply
GND
Negative power supply (GND)
VCC
VCC
Positive power supply for I/O and core. All VCC pins must be
connected to the positive power supply for correct operation
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 3. Absolute Maximum Ratings(1)
Symbol
VCC
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
Unit
V
Supply Voltage
VIN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
VCC + 0.3
VCC + 0.3
±20
V
VOUT
IIN
IOUT
TStor
V
mA
mA
°C
±50
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 4. General Specifications
Symbol
VTT
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
V
Condition
VCC ÷ 2
MM
ESD Protection (Machine model)
ESD Protection (Human body model)
Latch-up Immunity
200
2000
200
V
HBM
LU
V
mA
pF
pF
CPD
CIN
Power Dissipation Capacitance
Input Capacitance
10
Per output
4.0
Inputs
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to +85°C)
Symbol
VIH
Characteristics
Input HIGH Voltage
Min
2.0
Typ
Max
Unit
V
Condition
VCC + 0.3
0.8
LVCMOS
LVCMOS
VIL
Input LOW Voltage
–0.3
250
1.1
V
VPP
Peak-to-Peak Input Voltage
Common Mode Range
Input Current(2)
PCLK
PCLK
mV LVPECL
(1)
VCMR
VCC – 0.6
300
V
μA
V
LVPECL
IIN
VIN = VCC or GND
IOH = –24 mA(3)
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
2.4
0.55
0.30
V
V
IOL = 24 mA(3)
IOL = 12 mA
ZOUT
Output Impedance
17
Ω
(4)
ICCQ
Maximum Quiescent Supply Current
2.0
mA All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. Input pull-up / pull-down resistors influence input current.
3. The MPC9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines
(for VCC = 3.3 V) or one 50 Ω series terminated transmission line (for VCC = 2.5 V).
4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to +85°C)(1)
Symbol
fref
Characteristics
Min
0
Typ
Max
350
Unit
MHz
MHz
Condition
Input Frequency
fMAX
VPP
Maximum Output Frequency
Peak-to-Peak Input Voltage
Common Mode Range
0
350
PCLK
PCLK
400
1.3
1.4
1000
mV LVPECL
(2)
VCMR
VCC – 0.8
V
LVPECL
tP, REF
tr, tf
tPLH/HL
tPLH/HL
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation Delay
ns
ns
1.0(3)
0.8 to 2.0 V
PCLK to any Q
CCLK to any Q
1.6
1.3
3.6
3.3
ns
ns
tPLZ, HZ
tPZL, LZ
tS
Output Disable Time
Output Enable Time
Setup Time
11
11
ns
ns
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
ns
ns
tH
Hold Time
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.5
ns
ns
tsk(O)
tsk(PP)
tSK(P)
Output-to-Output Skew
Device-to-Device Skew
Output Pulse skew(4)
150
2.0
ps
ns
PCLK or CCLK to any Q
Using CCLK
Using PCLK
300
400
ps
ps
DCQ
tr, tf
Output Duty Cycle
fQ<170 MHz
45
50
55
%
DCREF = 50%
0.55 to 2.4 V
Output Rise/Fall Time
0.1
1.0
ns
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP)
.
.
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |.
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = -40°C to +85°C)
Symbol
VIH
Characteristics
Input high voltage
Min
1.7
Typ
Max
VCC + 0.3
0.7
Unit
V
Condition
LVCMOS
LVCMOS
VIL
Input low voltage
–0.3
250
1.0
V
VPP
Peak-to-peak input voltage
Common Mode Range
Input current(2)
PCLK
PCLK
mV LVPECL
(1)
VCMR
VCC – 0.7
300
V
μA
V
LVPECL
IIN
VIN = GND or VIN = VCC
IOH = –15 mA(3)
IOL= 15 mA(3)
VOH
VOL
ZOUT
Output High Voltage
Output Low Voltage
1.8
0.6
V
Output impedance
19
Ω
(4)
ICCQ
Maximum Quiescent Supply Current
2.0
mA All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. Input pull-up / pull-down resistors influence input current.
3. The MPC9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 Ω series terminated transmission lines at
V
CC = 2.5 V.
4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = -40°C to +85°C)(1)
Symbol
fref
Characteristics
Min
0
Typ
Max
350
Unit
MHz
MHz
Condition
Input Frequency
fMAX
VPP
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
0
350
PCLK
PCLK
400
1.2
1.4
1000
mV LVPECL
(2)
VCMR
VCC – 0.8
V
LVPECL
tP, REF
tr, tf
tPLH/HL
tPLH/HL
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
ns
ns
1.0(3)
0.8 to 2.0 V
PCLK to any Q
CCLK to any Q
1.5
1.7
4.2
4.4
ns
ns
tPLZ, HZ
tPZL, LZ
tS
Output Disable Time
Output Enable Time
Setup time
11
11
ns
ns
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
ns
ns
tH
Hold time
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.5
ns
ns
tsk(O)
tsk(PP)
tSK(p)
Output-to-output Skew
Device-to-device Skew
Output pulse skew(4)
150
2.7
ps
ns
PCLK or CCLK to any Q
Using CCLK
Using PCLK
200
300
ps
ps
DCQ
DCREF = 50%
0.6 to 1.8 V
Output Duty Cycle
fQ< 350 MHz and using CCLK
fQ<200 MHz and using PCLK
45
45
50
50
55
55
%
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP)
.
.
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
5
APPLICATION INFORMATION
3.0
CCLK or
PCLK
OutA
D = 3.8956
OutB
D = 3.9386
2.5
t
CLK_STOP
Q0 to Q11
t
2.0
1.5
1.0
0.5
0
In
Figure 3. Output Clock Stop (CLK_STOP)
Timing Diagram
Driving Transmission Lines
The MPC9448 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17 Ω (VCC = 3.3 V),
the outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks, point-to-
point distribution of signals is the method of choice. In a point-
to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to VCC÷2.
2
4
6
8
10
12
14
Time (ns)
Figure 5. Single versus Dual Line
Termination Waveforms
The waveform plots in Figure 5 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9448 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9448. The output waveform
in Figure 5 shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 33 Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
MPC9448
Output
Buffer
ZO = 50Ω
RS = 33Ω
17Ω
OutA
IN
IN
MPC9448
Output
BufferR
Z
O = 50Ω
O = 50Ω
RS = 33Ω
RS = 33Ω
OutB0
OutB1
17Ω
VL = VS (Z0 ÷ (RS+R0 +Z0))
Z0 = 50 Ω || 50 Ω
RS = 33 Ω || 33 Ω
R0 = 17 Ω
Z
Figure 4. Single versus Dual Transmission Lines
VL = 3.0 (25 ÷ (16.5+17+25)
= 1.28 V
This technique draws a fairly high level of DC current ,and
thus, only a single terminated line can be driven by each
output of the MPC9448 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9448 clock driver is effectively doubled
due to its capability to drive multiple lines at VCC = 3.3 V.
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
6
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 6 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
Table 9. Die Junction Temperature and MTFB
Junction Temperature (°C)
MTBF (Years)
100
110
120
130
20.4
9.1
4.2
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC9448 needs to be
controlled, and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC9448
is represented in equation 1.
MPC9448
Output
Buffer
Z
O = 50Ω
RS = 16Ω
RS = 16Ω
17Ω
Z
O = 50Ω
Where ICCQ is the static current consumption of the
MPC9448, CPD is the power dissipation capacitance per
output. (Μ)ΣCL represents the external capacitive output
load, and N is the number of active outputs (N is always 12 in
case of the MPC9448). The MPC9448 supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore, ΣCL
is zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output,
termination results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination. VOL, IOL, VOH and IOH are a
function of the output termination technique, and DCQ is the
clock signal duty cycle. If transmission lines are used, ΣCL is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device.
Equation 3 describes the die junction temperature TJ as a
function of the power consumption.
17Ω + 16Ω || 16Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
Power Consumption of the MPC9448 and
Thermal Management
The MPC9448 AC specification is guaranteed for the
entire operating frequency range up to 350 MHz. The
MPC9448 power consumption, and the associated long-term
reliability, may decrease the maximum frequency limit,
depending on operating conditions such as clock frequency,
supply voltage, output loading, ambient temperature, vertical
convection and thermal conductivity of package and board.
This section describes the impact of these parameters on the
junction temperature and gives a guideline to estimate the
MPC9448 die junction temperature and the associated
device reliability. For a complete analysis of power
consumption as a function of operating conditions and
associated long term device reliability, please refer to the
Freescale application note AN1545. According the AN1545,
the long-term device reliability is a function of the die junction
temperature:
Where Rthja is the thermal impedance of the package
(junction to ambient), and TA is the ambient temperature.
According to Figure 9, the junction temperature can be used
to estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC9448 in a series terminated
transmission line system, equation 4.
Equation 1
PTOT = [ ICCQ + VCC · fCLOCK · ( N · CPD + Σ CL ) ] · VCC
M
PTOT = VCC · [ ICCQ + VCC · fCLOCK · ( N · CPD + Σ CL ) ] + Σ [ DCQ · IOH · (VCC – VOH) + (1 – DCQ) · IOL · VOL ]
Equation 2
Equation 3
P
M
TJ = TA + PTOT · Rthja
Tj,MAX – TA
1
Equation 4
– (ICCQ · VCC
)
]
fCLOCK,MAX =
·
[
CPD · N · V2
Rthja
CC
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
7
TJ,MAX should be selected according to the MTBF system
requirements, and Figure 9 Rthja can be derived from
Figure 10. The Rthja represent data based on 1S2P boards.
Using 2S2P boards will result in a lower thermal impedance
than indicated below.
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the
safe frequency operation range for the MPC9448. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C (120°C), corresponding to an
estimated MTBF of 9.1 years (4 years), a supply voltage of
3.3 V and series terminated transmission line or capacitive
loading. Depending on a given set of these operating
conditions and the available device convection, a decision on
the maximum operating frequency can be made.
Table 10. Thermal Package Impedance of the 32ld LQFP
Rthja (1P2S board), Rthja (2P2S board),
Convection, LFPM
°C/W
86
°C/W
61
Still air
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
76
56
71
54
68
53
66
52
60
49
Figure 8. Maximum MPC9448 frequency, VCC = 3.3 V,
MTBF 9.1 Years, 4 pF Load per Line, 2s2p Board
Figure 7. Maximum MPC9448 Frequency, VCC = 3.3 V,
MTBF 9.1 Years, Driving Series Terminated
transmission lines, 2s2p board
Figure 9. No maximum Frequency Limitation for
VCC = 3.3 V, MTBF 4 Years, Driving Series
Terminated Transmission Lines, 2s2p Board
Figure 10. Maximum MPC9448 Frequency, VCC = 3.3 V,
MTBF 4 Years, 4 pF Load per Line, 2s2p Board
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
8
The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit
MPC9448 DUT
Pulse
Generator
Z = 50 Ω
ZO = 50 Ω
RT = 50 Ω
ZO = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 11. CCLK MPC9448 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
MPC9448 DUT
ZO = 50 Ω
Differential Pulse
Generator
ZO = 50 Ω
Z = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 12. PCLK MPC9448 AC Test Reference
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
9
PCLK
PCLK
VCC
CCLK
QX
VCC÷2
VPP
GND
VCC
VCC
VCC÷2
QX
GND
GND
tP(LH)
tP(HL)
tP(LH)
tP(HL)
Figure 13. Propagation Delay (tPD) Test Reference
Figure 14. Propagation Delay (tPD) Test Reference
VCC
VCC
VCC÷2
CCLK
QX
VCC÷2
GND
GND
VCC
VCC÷2
VCC
VCC÷2
GND
GND
tSK(LH)
tSK(HL)
tP(LH)
tP(HL)
The pin-to-pin skew is defined as the worst case differ-
ence in propagation delay between any similar delay
path within a single device.
tSK(P) = | tPLH – tPHL
|
Figure 16. Output Pulse Skew (tSK(P)) Test Reference
Figure 15. Output-to-Output Skew tSK(LH, HL)
VCC
VCC÷2
GND
tP
VCC=3.3 V VCC=2.5 V
2.4
1.8 V
T0
0.55
0.6 V
DC = (tP ? T0 x 100%)
tF
tR
The time from the output controlled edge to the non-
controlled edge, divided by the time between output
controlled edges, expressed as a percentage.
Figure 18. Output Transition Time Test Reference
Figure 17. Output Duty Cycle (DC)
VCC
CCLK
PCLK
VCC÷2
TJIT(CC) = |TN-TN+1
|
GND
TN+1
TN
VCC
VCC÷2
CLK_STOP
The variation in cycle time of a signal between ad-
jacent cycles, over a random sample of adjacent
cycle pairs.
GND
tS
tH
Figure 19. Cycle-to-Cycle Jitter
Figure 20. Setup and Hold Time (tS, tH) Test Reference
MPC9448
10
Advanced Clock Drivers Devices
Freescale Semiconductor
PACKAGE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
1
25
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC9448
Advanced Clock Drivers Devices
Freescale Semiconductor
11
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MPC9448
Rev. 5
1/2005
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