MPC961PACR2 [NXP]
961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32;
| 型号： | MPC961PACR2 |
| 厂家： | 
NXP |
| 描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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Order this document
by MPC961P/D
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The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay
buffer. With output frequencies of up to 200MHz, output skews of 150ps
the device meets the needs of the most demanding clock tree applica-
tions.
LOW VOLTAGE
• Fully Integrated PLL
• Up to 200MHz I/O Frequency
• LVCMOS Outputs
ZERO DELAY BUFFER
• Outputs Disable in High Impedance
• LVPECL Reference Clock Options
• LQFP Packaging
•
50ps Cycle–Cycle Jitter
• 150ps Output Skews
The MPC961 is offered with two different input configurations. The
MPC961C offers an LVCMOS reference clock while the MPC961P offers
an LVPECL reference clock.
When pulled high the OE pin will force all of the outputs (except QFB)
into a high impedance state. Because the OE pin does not affect the QFB
output, down stream clocks can be disabled without the internal PLL los-
ing lock.
5
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
The MPC961 is fully 2.5V or 3.3V compatible and requires no external
loop filter components. All control inputs accept LVCMOS compatible lev-
els and the outputs provide low impedance LVCMOS outputs capable of
driving terminated 50W transmission lines. For series terminated lines the
MPC961 can drive two lines per output giving the device an effective
fanout of 1:36. The device is packaged in a 32 lead LQFP package to
provide the optimum combination of board density and performance.
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Figure 1. MPC961P Logic Diagram
Rev 2
486
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MPC961P
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MPC961P
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Figure 2. 32–Lead Pinout (Top View)
5
Table 1: PIN CONFIGURATIONS
Pin
PCLK, PCLK
FB_IN
I/O
Input
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Function
PLL reference clock signal
Input
PLL feedback signal input, connect to a QFB output
PLL frequency range select
F_RANGE
OE
Input
Input
Output enable/disable
Q0 - Q16
QFB
Output
Output
Supply
Supply
Clock outputs
PLL feedback signal output, connect to a FB_IN
Negative power supply
GND
VCCA
VCC
PLL positive power supply (analog power supply). The MPC961P requires an
external RC filter for the analog power supply pin V
tions section for details.
. Please see applica-
CCA
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE
0
PLL high frequency range. MPC961P input reference
and output clock frequency range is 100 – 200 MHz
PLL low frequency range. MPC961P input reference
and output clock frequency range is 50 – 100 MHz
OE
0
Outputs enabled
Outputs disabled (high–impedance state)
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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MPC961P
Table 3: ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
–0.3
Max
Unit
V
V
V
V
Supply Voltage
3.6
CC
IN
DC Input Voltage
V
V
+ 0.3
V
CC
CC
DC Output Voltage
DC Input Current
+ 0.3
20
V
OUT
I
I
mA
mA
°C
IN
OUT
DC Output Current
Storage Temperature Range
50
T
–40
125
S
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-
tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not im-
plied.
Table 4: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = –40° to 85°C)
Symbol
Characteristic
Input HIGH Voltage
Min
2.0
Typ
Max
+ 0.3
CC
Unit
V
Condition
LVCMOS
V
V
IH
IL
V
V
Input LOW Voltage
–0.3
500
0.8
V
LVCMOS
LVPECL
a
Peak–to–peak input voltage
1000
mV
PP
PECL_CLK, PECL_CLK
PECL_CLK, PECL_CLK
a
V
V
V
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
1.2
2.4
V
– 0.8
CC
V
V
LVPECL
CMR
b
I
= –20mA
OH
OH
OL
b
0.55
20
V
I
= 20mA
OL
Z
I
14
W
OUT
5
120
µA
pF
pF
mA
mA
V
IN
C
C
Input Capacitance
4.0
8.0
2.0
IN
PD
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
10
Per Output
V Pin
CCA
I
5.0
CCA
CC
I
All VCC Pins
V
TT
V
B 2
CC
a. Exceeding the specified V /V window results in a t changes of approx. 250 ps.
CMR PP PD
b. The MPC961P is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmis-
sion line to a termination voltage of V . Alternatively, the device drives up two 50Ω series terminated transmission lines.
TT
488
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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MPC961P
Table 5: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = –40° to 85°C)a
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
f
ref
Input Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
f
Maximum Output Frequency
Reference Input Duty Cycle
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
max
f
t
25
75
%
refDC
b
Propagation Delay
PECL_CLK to FB_IN
–50
225
ps
PLL locked
0.55 to 2.4V
∅
(
)
(static phase offset)
c
t
Output–to–Output Skew
90
150
ps
%
sk(O)
DC
Output Duty Cycle
F_RANGE = 0
F_RANGE = 1
42
45
50
50
55
55
O
t , t
r
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
0.1
1.0
10
10
15
10
ns
ns
ns
ps
ps
ns
f
t
t
t
t
t
,
PLZ HZ
,
PZL LZ
d
RMS (1 s)
JIT(CC)
RMS (1 s)
7.0
JIT(PER)
I/O Phase Jitter
RMS (1 s) F_RANGE = 0
0.0015 @ T
0.0010 @ T
T = Clock Signal
Period
∅
JIT(
)
F_RANGE = 1
t
Maximum PLL Lock Time
10
ms
lock
a. AC characteristics apply for parallel output termination of 50W to V
TT
b. t applies for V
= V –1.3V and V = 800mV
PD
CMR
CC PP
c. See applications section for part–to–part skew calculation
d. See applications section for calculation for other confidence factors than 1 s
5
Table 6: DC CHARACTERISTICS (VCC = 2.5V 5%, TA = –40° to 85°C)
Symbol
Characteristic
Input HIGH Voltage
Min
1.7
Typ
Max
Unit
V
Condition
LVCMOS
LVCMOS
LVPECL
V
V
+ 0.3
CC
IH
IL
V
V
Input LOW Voltage
–0.3
500
0.7
1000
V
a
Peak–to–peak input voltage
mV
PP
PECL_CLK, PECL_CLK
PECL_CLK, PECL_CLK
a
V
V
V
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
1.2
1.8
V
– 0.7
CC
V
V
LVPECL
CMR
b
I
I
= –15mA
OH
OH
OL
b
0.6
26
V
= 15mA
OL
Z
I
18
W
OUT
120
µA
pF
pF
mA
mA
V
IN
C
C
Input Capacitance
4.0
8.0
2.0
IN
PD
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
10
Per Output
V Pin
CCA
I
5.0
CCA
CC
I
All VCC Pins
V
TT
V
B 2
CC
a. Exceeding the specified V /V window results in a t changes < 250 ps.
CMR PP PD
b. The MPC961P is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmis-
sion line to a termination voltage of V . Alternatively, the device drives up two 50Ω series terminated transmission lines.
TT
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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MPC961P
Table 7: AC CHARACTERISTICS (VCC = 2.5V 5%, TA = –40° to 85°C)a
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
f
ref
Input Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
f
Maximum Output Frequency
Reference Input Duty Cycle
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
max
f
t
25
75
%
refDC
b
Propagation Delay
PCLK to FB_IN
–50
175
ps
PLL locked
0.6 to 1.8V
∅
(
)
(static phase offset)
c
t
Output–to–Output Skew
90
150
ps
%
sk(O)
DC
Output Duty Cycle
F_RANGE = 0
F_RANGE = 1
40
45
50
50
60
55
O
t , t
r
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
0.1
1.0
10
10
15
10
ns
ns
ns
ps
ps
ns
f
t
t
t
t
t
,
PLZ HZ
,
PZL LZ
d
RMS (1 s)
JIT(CC)
RMS (1 s)
7.0
JIT(PER)
I/O Phase Jitter
RMS (1 s) F_RANGE = 0
0.0015 @ T
0.0010 @ T
T = Clock Signal
Period
∅
JIT(
)
F_RANGE = 1
t
Maximum PLL Lock Time
10
ms
lock
a. AC characteristics apply for parallel output termination of 50W to V
TT
b. t applies for V
= V –1.3V and V = 800mV
PD
CMR
CC PP
c. See applications section for part–to–part skew calculation
d. See applications section for calculation for other confidence factors than 1 s
5
490
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MPC961P
Power Supply Filtering
Driving Transmission Lines
The MPC961P clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 15Ω the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091.
The MPC961P is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally sus-
ceptible to random noise, especially if this noise is seen on the
power supply pins. The MPC961P provides separate power
supplies for the output buffers (VCC) and the phase–locked
loop (VCCA) of the device. The purpose of this design tech-
nique is to isolate the high switching noise digital outputs from
the relatively sensitive internal analog phase–locked loop. In a
controlled environment such as an evaluation board this level
of isolation is sufficient. However, in a digital system environ-
ment where it is more difficult to minimize noise on the power
supplies a second level of isolation may be required. The sim-
plest form of isolation is a power supply filter on the VCCA pin
for the MPC961P.
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50Ω resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC961P clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC961P clock driver is effectively doubled due to
its capability to drive multiple lines.
Figure 3 illustrates a typical power supply filter scheme. The
MPC961P is most susceptible to noise with spectral content in
the 10kHz to 5MHz range. Therefore the filter should be de-
signed to target this range. The key parameter that needs to be
met in the final filter design is the DC voltage drop that will be
seen between the VCC supply and the VCCA pin of the
MPC961P. From the data sheet the ICCA current (the current
sourced through the VCCA pin) is typically 2mA (5mA maxi-
mum), assuming that a minimum of 2.375V (VCC = 3.3V or VCC
= 2.5V) must be maintained on the VCCA pin. The resistor RF
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shown in Figure 3 must have a resistance of 270Ω (VCC
=
5
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3.3V) or 5 to 15Ω (VCC = 2.5V) to meet the voltage drop crite-
ria. The RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral con-
tent is above 20kHz. As the noise frequency crosses the series
resonant point of an individual capacitor it’s overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies well
above the bandwidth of the PLL.
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ꢊΩ
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ꢕΩ
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Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation results
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of an output driving a single line vs two lines. In both cases the
drive capability of the MPC961P output buffer is more than
sufficient to drive 50Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC961P. The output waveform in Figure 5 shows a step in
the waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
36Ω series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
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Figure 3. Power Supply Filter
Although the MPC961P has several design features to mini- wave launched down the two lines will equal:
mize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be ap-
plications in which overall performance is being degraded due
to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to elim-
inate power supply noise related problems in most designs.
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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MPC961P
At the load end the voltage will double, due to the near unity Using the MPC961P in zero-delay applications
reflection coefficient, to 2.62V. It will then increment towards
the quiescent 3.0V in steps separated by one round trip delay
(in this case 4.0ns).
Nested clock trees are typical applications for the
MPC961P. Designs using the MPC961P as LVCMOS PLL fan-
out buffer with zero insertion delay will show significantly lower
clock skew than clock distributions developed from CMOS fan-
out buffers. The external feedback option of the MPC961P
clock driver allows for its use as a zero delay buffer. By using
the QFB output as a feedback to the PLL the propagation delay
through the device is virtually eliminated. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device. The maxi-
mum insertion delay of the device in zero-delay applications is
measured between the reference clock input and any output.
This effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the output-
to-output skew error relative to the feedback output.
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ꢯ ꢔ
ꢯ ꢊ
ꢯ ꢔ
ꢯ ꢊ
ꢯ ꢔ
ꢊ
ꢍ ꢡꢧ ꢏ
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Calculation of part-to-part skew
The MPC961P zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC961P are connected together, the maximum overall tim-
ing uncertainty from the common PCLK input to any output is:
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ꢋ
ꢒ
ꢋ ꢌ
ꢜ
ꢇ
ꢙ
ꢑ
ꢺ
ꢥ
ꢸ
ꢻ
tSK(PP) = t ∅ + tSK(O) + tPD, LINE(FB) + tJIT( ꢁ CF
∅
)
(
)
Figure 5. Single versus Dual Waveforms
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
5
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 6 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
ꢀ ꢁꢂ ꢃ
ꢁ ꢩꣁ
ꣁ
ꢩꢥ
ꢧ
ꢀ ꢳ ꢽ ꢂ ꢇ ꢈ ꢑ ꢺ ꢄ ꢅ ꢻ
ꣀ
ꢧ
∅
ꢺ ꢻ
ꢉ ꢄꢅ
ꢳ ꢖ
ꣂ
ꣂ
ꢢ
ꢰ
ꢰ
ꢖ
ꢋ
ꢋ
ꢧ
ꢾ
∅
ꢺ
ꢇ
ꢜ
ꢻ
ꢏ ꢥꢭ ꢉ
ꢳ ꢖ
ꢢ
ꢖ
ꢙꢀꢁ ꢞꢕ ꢋ
ꢿ t
ꢸ ꢃ ꢺ ꢍ ꢻ
ꢍ ꢷꢜ ꢀꢷ ꢜ
ꢅꢷ ꢄꢄ ꢑꢎ
ꢹ
ꢹ
ꢶ
ꢶ
ꢔ
ꢔ
ꢊΩ
ꢊΩ
ꢍ
ꢍ
ꢎ
ꢶ
ꢶ
ꢒ
ꢒ
ꢒ Ω
ꢒ Ω
ꢸ
ꢸ
ꢿ
ꢧ
∅
ꢺ ꢻ
ꢋ ꢌΩ
ꢉ ꢄꢅ
ꢳꢖ ꣂ
ꢢ
ꢰ
ꢖ
ꢒ
ꢎ
ꢧ
∅
ꢾ ꢇ ꢜ ꢺ ꢻ
ꢏ ꢥꢭ ꢉ
ꢳ ꢖ ꣂ
ꢢ
ꢰ
ꢖ
ꢒ
ꢿ t
ꢸ ꢃ ꢺ ꢍ ꢻ
14Ω + 22Ω ꢀ 22Ω = 50Ω ꢀ 50Ω
25Ω = 25Ω
ꢙ
ꢤ
ꢦ
ꢯ
ꢣ
ꢲ
ꢖ
ꢬ
ꢧ
ꢸ ꢃ ꢺ ꢀ ꢀ ꢻ
Figure 6. Optimized Dual Line Termination
Figure 7. MPC961P max. device-to-device skew
Due to the statistical nature of I/O jitter a rms value (1 s) is
SPICE level and IBIS output buffer models are available for
engineers who want to simulate their specific interconnect specified. I/O jitter numbers for other confidence factors (CF)
schemes. can be derived from Table 8.
492
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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Freescale Semiconductor, Inc.
MPC961P
thermal conductivity of package and board. This section de-
scribes the impact of these parameters on the junction temper-
ature and gives a guideline to estimate the MPC961P die junc-
tion temperature and the associated device reliability. For a
complete analysis of power consumption as a function of oper-
ating conditions and associated long term device reliability
please refer to the application note AN1545. According the
AN1545, the long-term device reliability is a function of the die
junction temperature:
Table 8: Confidence Facter CF
CF
1s
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
2s
3s
4s
5s
6s
Table 9: Die junction temperature and MTBF
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% ( 3s) is assumed, resulting in a worst
case timing uncertainty from input to any output of -236 ps to
361 ps relative to PCLK (f=125 MHz, VCC=2.5V):
Junction temperature (°C)
MTBF (Years)
100
110
120
130
20.4
9.1
4.2
2.0
tSK(PP)
=
[–50ps...175ps] + [–150ps...150ps] +
[(12ps @ –3)...(12ps @ 3)] + tPD, LINE(FB)
Increased power consumption will increase the die junction
temperature and impact the device reliability (MTBF). Accord-
ing to the system-defined tolerable MTBF, the die junction tem-
perature of the MPC961P needs to be controlled and the ther-
mal impedance of the board/package should be optimized.
The power dissipated in the MPC961P is represented in equa-
tion 1.
tSK(PP)
=
[–236ps...361ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 8
“Max. I/O Jitter versus frequency” can be used for a more pre-
cise timing performance analysis.
Where ICCQ is the static current consumption of the
MPC961P, CPD is the power dissipation capacitance per out-
put, (Μ)ΣCL represents the external capacitive output load, N
is the number of active outputs (N is always 27 in case of the
MPC961P). The MPC961P supports driving transmission lines
to maintain high signal integrity and tight timing parameters.
Any transmission line will hide the lumped capacitive load at
the end of the board trace, therefore, ΣCL is zero for controlled
transmission line systems and can be eliminated from equa-
tion 1. Using parallel termination output termination results in
equation 2 for power dissipation.
5
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are a
function of the output termination technique and DCQ is the
clock signal duty cyle. If transmission lines are used ΣCL is
Figure 8. Max. I/O Jitter versus frequency
Power Consumption of the MPC961P and Thermal Man-
agement
The MPC961P AC specification is guaranteed for the entire zero in equation 2 and can be eliminated. In general, the use of
operating frequency range up to 200 MHz. The MPC961P controlled transmission line techniques eliminates the impact
power consumption and the associated long-term reliability of the lumped capacitive loads at the end lines and greatly
may decrease the maximum frequency limit, depending on op- reduces the power dissipation of the device. Equation 3 de-
erating conditions such as clock frequency, supply voltage, scribes the die junction temperature TJ as a function of the
output loading, ambient temperature, vertical convection and power consumption.
) ȍ
PTOT
+
I
CCQ ) VCC @ fCLOCK
@
ǒ
N @ CPD
CL
Ǔ
@ V
CC
ƪ
ƫ
M
Equation 1
ǒ
Ǔ
ƪ
ǒ
Ǔ
ƫ
) ȍ
) ȍ
PTOT + VCC
@
I
CCQ ) VCC @ fCLOCK
@
ǒ
N @ CPD
CL
Ǔ
DCQ @ IOH @ VCC * VOH ) 1 * DCQ @ IOL @ VOL
ƪ
ƫ
M
P
Equation 2
TJ + TA ) PTOT @ Rthja
Equation 3
Equation 4
TJ,MAX * TA
1
ǒ Ǔ
* ICCQ @ VCC
@ ƪ
ƫ
fCLOCK,MAX
+
CPD @ N @ VC2 C
Rthja
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
493
For More Information On This Product,
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Freescale Semiconductor, Inc.
MPC961P
Where Rthja is the thermal impedance of the package (junc-
TJ,MAX should be selected according to the MTBF system
tion to ambient) and TA is the ambient temperature. According requirements and Table 9. Rthja can be derived from Table 10.
to Table 9, the junction temperature can be used to estimate The Rthja represent data based on 1S2P boards, using 2S2P
the long-term device reliability. Further, combining equation 1 boards will result in a lower thermal impedance than indicated
and equation 2 results in a maximum operating frequency for below.
the MPC961P in a series terminated transmission line system.
If the calculated maximum frequency is below 200 MHz, it
becomes the upper clock speed limit for the given application
Table 10: Thermal package impedance of the 32ld
LQFP
conditions. The following two derating charts describe the safe
frequency operation range for the MPC961P. The charts were
calculated for a maximum tolerable die junction temperature of
110°C, corresponding to an estimated MTBF of 9.1 years, a
supply voltage of 3.3V and series terminated transmission line
or capacitive loading. Depending on a given set of these oper-
ating conditions and the available device convection a decision
on the maximum operating frequency can be made. There are
no operating frequency limitations if a 2.5V power supply or the
system specifications allow for a MTBF of 4 years (corre-
sponding to a max. junction temperature of 120°C.
Convection, LFPM
Still air
R
(1P2S board), K/W
thja
80
70
61
57
56
55
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
ꢒ ꢊ
ꢋ ꢵ
ꢋ ꢕ
ꢋ ꢌ
ꢋ ꢒ
ꢋ ꢊ
ꢵ
ꢕ
ꢌ
ꢒ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢒ
ꢋ
ꢋ
ꢋ
ꢋ
ꢋ
ꢊ
ꢵ
ꢕ
ꢌ
ꢒ
ꢊ
ꢵ
ꢕ
ꢌ
ꢒ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
ꢗ
ꢺ
ꢏ
ꢁ
ꢻ
ꢗ
ꢺꢏ ꢁꢻ
ꢏ ꣄
ꢙ
ꢏ
꣄
ꢙ
ꢜ
ꢏ
ꢶ
ꢵ
ꢔ
°
ꢁ
ꢜ ꢶ ꢴ ꢔ°ꢁ
ꢏ
ꢜ
ꢏ
ꢶ
ꢵ
ꢔ
°
ꢁ
5
Safe operation
Safe operation
ꢊ
ꢊ
ꢊ
ꢊ
ꢔ
ꢊ
ꢊ
ꢌ
ꢊ
ꢊ
ꢓ
ꢊ
ꢊ
ꢒ
ꢊ
ꢊ
ꢋ
ꢊ
ꢊ
ꢊ
ꢔ
ꢊ
ꢊ
ꢌ
ꢊ
ꢊ
ꢓ
ꢊ
ꢊ
ꢒ
ꢊ
ꢊ
ꢋ
ꢊ
ꢊ
ꢊ
ꢇ
ꢄ
ꢽ ꢁꢍ ꢈꢮ ꢑ ꢁꢜꢇ ꢍ ꢈ
ꢙ
ꢇ
ꢄ
ꢽ ꢁꢍ ꢈ ꢮꢑ ꢁꢜꢇ ꢍ ꢈ
ꢙ
ꢀ
ꢀ
Figure 9. Maximum MPC961P frequency, VCC = 3.3V, MTBF
9.1 years, driving series terminated transmission lines
Figure 10. Maximum MPC961P frequency,
CC = 3.3V, MTBF 9.1 years, 4 pF load per line
V
ꢙ
ꢀ
ꢁ
ꢞ
ꢕ
ꢋ
ꢀ
ꢳ
ꢷ
ꢜ
ꢹ
ꢶ
ꢔ
ꢊ
Ω
ꢍ
ꢳꢢ ꢗꢗ ꢖꢟꢖ ꢥꢧ ꢢꢤꢨ
ꢀ ꢡꢨꢣꢖ ꢐ ꢖꢥꢖ ꢟꢤ ꢧꢩꢟ
ꢹ
ꢶ
ꢔ
ꢊ
Ω
ꢍ
ꢹ
ꢶ
ꢔ
ꢊ
W
ꢎ
ꢜ
ꢶ
ꢔ
ꢊ
Ω
ꢎ
ꢜ
ꢶ
ꢔ
ꢊ
Ω
ꢮ
ꢜ
ꢜ
ꢮ
ꢜ
ꢜ
Figure 11. TCLK MPC961P AC test reference for Vcc = 3.3V and Vcc = 2.5V
494
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
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Freescale Semiconductor, Inc.
MPC961P
ꢀ
ꢀ
ꢁ
ꢁ
ꢂ
ꢂ
ꢃ
ꢃ
ꢮ
ꢀ
ꢀ
ꢮ
ꢁ
ꢙ
ꢎ
ꢮ
ꢁ
ꢶ
ꢓ
ꢯ
ꢓ
ꢮ
ꢮ ꢶꢒ ꢯ ꢔ ꢮ
ꢁ ꢁ
ꢁ
ꢒ
ꢯ
ꢌ
ꢋ
ꢯ
ꢵ
ꢮ
ꢮ
ꢮ
ꢁ
ꢁ
Bꢒ
ꢁ
ꢁ
ꢊ
ꢯ
ꢔ
ꢔ
ꢊ
ꢯ
ꢕ
ꢮ
ꢑꢦꢧ ꢆꢄ ꢅ
ꢐ ꢈꢳ
ꢧ
ꢄ
ꢧ
ꢎ
ꢧ
∅
ꢺ
ꢻ
Figure 12. Propagation delay (t(∅ , static phase
)
Figure 13. Output Transition Time Test Reference
offset) test reference
ꢮ
ꢮ
ꢁ
ꢁ
ꢁ
ꢮ
ꢮ
ꢁ
ꢁ
ꢁ
Bꢒ
ꢁ
B
ꢒ
ꢒ
ꢁ
ꢐ ꢈꢳ
ꢐ
ꢈ
ꢳ
ꢧ
ꢀ
ꢮ
ꢮ
ꢁ
ꢁ
ꢁ
B
ꢁ
ꢜ
ꢊ
ꢐ ꢈꢳ
ꢀꢁ ꢂ ꢃ ꢅ ꢆ ꢦ ꢈꢇ ꢇꢉ
ꢄ
ꢇ
ꢧ
ꢸ
ꢃ
ꢺ
ꢍ
ꢻ
ꢜ
ꢝ
ꢖ
ꢧ
ꢖ
ꢢ
ꣁ
ꢖ
ꣁ
ꢗ
ꢖ
ꢟ
ꢩ
ꣁ
ꢖ
ꢧ
ꢝ
ꢖ
ꢖ
ꢖ
ꢀ
ꢥ
ꢂ
ꢀ
ꢂ
ꢂ
ꢰ
ꢂ
ꢩ
ꢥ
ꢰ
ꢧ
ꢩ
ꢟ
ꢥ
ꢩ
ꢧ
ꢨ
ꢟ
ꢨ
ꢖ
ꢩ
ꢱ
ꢖ
ꢱ
ꢱ
ꢖ
ꢪ
ꢖ
ꢱ
ꢧ
ꢩ
ꢣ
ꢧ
ꢽ
ꢝ
ꢖ
ꢖ
ꢦ
ꢥ
ꢫ
ꢩ
ꢥ
ꢣ
ꢰ
ꢣ
ꢩ
ꢖ
ꢥ
ꢱ
ꢧ
ꢟ
ꢤ
ꢩ
ꢣ
ꢨ
ꢨ
ꢖ
ꢤ
ꢱ
ꢫ
ꢖ
ꢖ
ꢱ
ꢪ
ꢖ
ꢖ
ꢥ
ꢽ
ꢱ
ꢢ
ꢪ
ꣂ
ꢢ
ꢖ
ꢱ
ꢖ
ꢱ
ꢜ
ꢝ
ꢧ
ꢖ
ꢫ
ꢥ
ꢢ
ꢥ
ꢱ
ꢘ
ꢖ
ꢧ
ꢨ
ꢩ
ꢤ
ꢘ
ꢭ
ꢫ
ꢢ
ꢥ
ꢖ
ꢣ
ꢲ
ꢖ
ꢖ
ꢖ
ꢬ
ꢥ
ꢢ
ꢣ
ꢤ
ꢱ
ꢖ
ꢗ
ꢣ
ꢢ
ꢥ
ꢖ
ꢱ
ꢤ
ꢟ
ꢣ
ꢱ
ꢧ
ꢖ
ꢝ
ꢖ
ꢭ
ꢬ
ꢫ
ꢩ
ꢤ
ꢟ
ꢧ
ꢣ
ꢝ
ꢧ
ꢰ
ꢬ
ꢤ
ꢣ
ꢝ
ꢖ
ꢱ
ꢤ
ꢢ
ꢗ
ꢗ
ꢣ
ꢖ
ꢢ
ꢟ
ꢥ
ꢖ
ꢪ
ꢥ
ꢨ
ꢰ
ꢖ
ꢖ
ꢱ
ꢢ
ꢖ
ꢥ
ꣂ
ꢫ
ꢟ
ꢖ
ꢩ
ꢫ
ꢤꣅ
ꢭ
ꢧ
ꢝ
ꢧ
ꢢ
ꢧ
ꢬ
ꢨ
ꢨ
ꢖ
ꢪ
ꢖ
ꢟ
ꢖ
ꢟ
ꢰ
ꢧ
ꢤ
ꢪ
ꢤ
ꢢ
ꢩ
ꢧ
ꢬ
ꢥꢭ
ꢢ
ꣁ
ꢢ
ꢨ
ꢤ
ꢨ
ꢤ
ꢢ
ꢧ
ꢢ
ꢥ
ꢢ
ꢰ
Figure 14. Output Duty Cycle (DC)
Figure 15. Output–to–output Skew tSK(O)
5
ꢆ
ꢂ
ꢆ ꢏ ꢆ
ꢆ
ꢂ
ꢆ ꢏ ꢈ ꢓ
ꢎ ꢇ
ꢊ ꢋ ꢆ ꢌ ꢁ ꢁ ꢍ
ꢎ
ꢎ ꢐ ꢈ
ꢊ
ꢋ
ꢆ
ꢌ
ꢄ
ꢑ
ꢒ
ꢍ
ꢜ
ꢜ
ꢈ ꢿ ꢋ
ꢜ
ꢈ
ꢊ
ꢜ
ꢝ
ꢥ
ꢖ
ꢱ
ꣂ
ꢩ
ꢤ
ꣁ
ꢟ
ꢢ
ꢤ
ꢣ
ꢧ
ꢤ
ꢢ
ꢩ
ꣁ
ꢥ
ꢫ
ꢢ
ꢨ
ꢥ
ꢖ
ꢰ
ꢩ
ꢭ
ꢗ
ꢰ
ꢤ
ꢨ
ꢱ
ꢖ
ꢧ
ꢤ
ꢢ
ꣁ
ꢖ
ꢥ
ꢩ
ꢗ
ꢤ
ꢣ
ꢢ
ꢪ
ꢫ
ꢥ
ꢤ
ꢤ
ꢢ
ꢨ
ꢟ
ꢣ
ꢖ
ꢧ
ꢬ
ꢖ
ꢖ
ꢥ
ꢤ
ꢱ
ꢤ
ꢰ
ꢖ
ꢥ
ꢧ
ꢰ
ꢭ
ꢰ
ꢨ
ꢖ
ꢣ
ꢽ
ꢩ
ꣂ
ꢖ
ꢟ
ꢤ
ꢜ
ꢤ
ꢝ
ꢖ
ꢥ
ꢱ
ꢱ
ꢖ
ꢩ
ꣂ
ꣁ
ꢢ
ꢤ
ꢧ
ꢣ
ꢢ
ꢩ
ꢤ
ꢥ
ꣁ
ꢢ
ꢫ
ꢥ
ꢨ
ꢰ
ꢖ
ꢭ
ꢩ
ꢰ
ꢗ
ꢨ
ꢖ
ꢰ
ꢧ
ꢢ
ꣁ
ꢖ
ꢣ
ꢩ
ꢗ
ꢤ
ꢣ
ꢢ
ꢪ
ꢥ
ꢤ
ꢨ
ꢬ
ꢢ
ꢧ
ꢝ
ꢟ
ꢖ
ꢣ
ꢫ
ꢖ
ꢰ
ꢧ
ꢧ
ꢩ
ꢧ
ꢝ
ꢖ
ꢢ
ꢱ
ꢖ
ꢤ
ꢨ
ꢫ
ꢖ
ꢟ
ꢢ
ꢩ
ꢱ
ꢩ
ꣂ
ꢖ
ꢟ
ꢟ
ꢤ
ꢰ
ꢖ
ꢧ
ꢰ
ꢭ
ꢰ
ꢨ
ꢖ
ꢟ
ꢤ
ꢭ
ꢰ
ꢨ
ꢖ
Figure 16. Cycle–to–cycle Jitter
Figure 17. Period Jitter
ꢀ
ꢁ
ꢁ
ꢂ
ꢃ
ꢀ
ꢂ
ꢃ
ꢑ
ꢦ
ꢧ
ꢆ
ꢄ
ꢅ
ꢆ
ꢊ ꢋ ꢆ ꢌ
ꢂ ꢆ ꢏ ꢆ ꢔ ꢕꢖꢗ
ꢇ ꢈ
∅
ꢍ
ꢜ
ꢝ
ꢥ
ꢖ
ꢱ
ꢱ
ꢩ
ꢖ
ꣁ
ꣂ
ꢢ
ꢣ
ꢤ
ꢤ
ꢧ
ꢢ
ꢩ
ꢥ
ꢢ
ꢥ
ꢧ
ꢗ
ꢩ
ꢟ
ꢤ
ꢰ
ꢣ
ꢩ
ꢥ
ꢧ
ꢟ
ꢩ
ꢨ
ꢨ
ꢖ
ꢱ
ꢖ
ꢱ
ꢪ
ꢖ
ꢬ
ꢢ
ꢧ
ꢝ
ꢟ
ꢖ
ꢣ
ꢫ
ꢖ
ꢰ
ꢧ
ꢧ
ꢩ
ꢤ
ꢧ
ꣁ ꢖ
ꢊ
ꢤ
ꢥ
ꢢ
ꢥ
ꢤ
ꢊ
ꢟ
ꢤ
ꣁꢫ ꢨꢖ ꢩ ꢗ ꢰꢭꢰ ꢨꢖ
Figure 18. I/O Jitter
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
495
For More Information On This Product,
Go to: www.freescale.com
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