MPC962308D-5H [NXP]
962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, SOIC-16;
| 型号： | MPC962308D-5H |
| 厂家： | 
NXP |
| 描述： | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, SOIC-16 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Order number: MPC962308
Rev 3, 08/2004
SEMICONDUCTOR TECHNICAL DATA
3.3 V Zero Delay Buffer
MPC962308
The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom and other
high-performance applications. The MPC962308 uses an internal PLL and an
external feedback path to lock its low-skew clock output phase to the reference
clock phase, providing virtually zero propagation delay. The input-to-output
skew is guaranteed to be less than 250 ps and output-to-output skew is
guaranteed to be less than 200 ps.
Features
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
•
•
1:8 outputs LVCMOS zero-delay buffer
Zero input-output propagation delay, adjustable by the capacitive load on
FBK input
•
Multiple Configurations, see Table 2. Available MPC962308
Configurations
•
•
•
•
•
•
•
•
•
•
•
•
Multiple low-skew outputs
200 ps max output-output skew
700 ps max device-device skew
Two banks of four outputs, output tristate control by two select inputs
Supports a clock I/O frequency range of 10 MHz to 133 MHz
Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H)
±250 ps static phase offset (SPO)
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
16-pin SOIC package or 16-pin TSSOP package
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2308 and CY23S08
Spread spectrum compatible
Functional Description
The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1. Select
Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly
applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising
edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 µA of current draw. The PLL shuts
down in two additional cases explained in Table 1. Select Input Decoding.
Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference
between the output skews of two devices will be less than 700 ps.
The MPC962308 is available in five different configurations as shown in Table 2. Available MPC962308 Configurations. In the
MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configura-
tion, the MPC962308-1H, is available to provide faster rise and fall times of the device.
The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X
and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations
of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version
with outputs of REF/2.
The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the
incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.
For More Information On This Product,
© Motorola, Inc. 2004
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC962308
Block Diagram
Pin Configuration
SOIC/TSSOP
Top View
/2
FBK
PLL
REF
MUX
/2
CLKA1
CLKA2
CLKA3
CLKA4
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
FBK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Extra Divider (-3, -4)
Extra Divider (-5H)
CLKA4
CLKA3
VDD
S2
S1
Select Input
Decoding
GND
CLKB4
CLKB3
S1
/2
CLKB1
CLKB2
CLKB3
CLKB4
Extra Divider (-2, -3)
Table 1. Select Input Decoding
S2
0
S1
0
CLOCK A1—A4
Three-State
Driven
CLOCK B1—B4
Three-State
Output Source
PLL
PLL Shutdown
Y
N
Y
0
1
Three-State
PLL
Driven1
Driven
Driven1
Driven
1
0
Reference
1
1
PLL
N
1. Outputs inverted on MPC962308-2 in bypass mode, S2=1 and S1=0.
Table 2. Available MPC962308 Configurations
Device
MPC962308-1
Feedback From
Bank A or Bank B
Bank A Frequency
Bank B Frequency
Reference
Reference
Reference
Reference/2
Reference
MPC962308-1H
MPC962308-2
MPC962308-2
MPC962308-3
Bank A or Bank B
Bank A
Reference
Reference
Bank B
2 X Reference
2 X Reference
Reference or Reference[1]
2 X Reference
Bank A
MPC962308-3
MPC962308-4
MPC962308-5H
Bank B
4 X Reference
2 X Reference
Reference /2
Bank A or Bank B
Bank A or Bank B
2 X Reference
Reference /2
1. Output phase is indeterminate (0° or 180° from input clock). If phase integrity is required, use the MPC962308-2.
TIMING SOLUTIONS
MOTOROLA
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MPC962308
Table 3. Pin Description
Pin
Signal
Description
REF1
1
Input reference frequency, 5 V tolerant input
Clock output, Bank A
CLKA12
2
3
4
CLKA22
VDD
Clock output, Bank A
3.3 V supply
5
6
GND
Ground
CLKB12
CLKB22
S23
Clock output, Bank B
7
8
Clock output, Bank B
Select input, bit 2
S13
9
Select input, bit 1
CLKB32
10
11
Clock output, Bank B
Clock output, Bank B
CLKB42
GND
12
13
Ground
VDD
3.3 V supply
CLKA32
14
15
Clock output, Bank A
Clock output, Bank A
PLL feedback input
CLKA42
FBK
16
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Table 4. Maximum Ratings
Characteristics
Value
Unit
V
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
–0.5 to +3.9
–0.5 to VDD+0.5
V
DC Input Voltage REF
Storage Temperature
Junction
–0.5 to 5.5
–65 to +150
150
V
°C
°C
V
Static Discharge Voltage (per MIL-STD-883, Method 3015)
>2000
MOTOROLA
TIMING SOLUTIONS
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MPC962308
Table 5. Operating Conditions for MPC962308-X Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
CL
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance1
–40
85
30
°C
pF
15
7
pF
pF
CIN
1. Applies to both REF clock and FBK.
Table 6. Electrical Characteristics for MPC962308-X Industrial Temperature Devices1
Parameter
Description
Input LOW Voltage
Test Conditions
Min
Max
Unit
VIL
0.8
V
VIH
IIL
Input HIGH Voltage
Input LOW Current
Input HIGH Current
2.0
V
µA
µA
V
VIN = 0V
50.0
100.0
0.4
IIH
VIN = VDD
Output LOW Voltage2
VOL
IOL = 8 mA (-1, -2, -3, -4)
IOL = 12 mA (-1H, -5H)
Output HIGH Voltage2
VOH
IOH = -8 mA (-1, -2, -3, -4)
IOH = -12 mA (-1H, -5H)
2.4
V
I
DD (PD mode) Power Down Supply Current
IDD Supply Current
REF = 0 MHz
25.0
45.0
µA
Unloaded outputs, 100 MHz,
Select inputs at VDD or GND
mA
70(-1H, -5H)
35.0
mA
mA
Unloaded outputs, 66-MHz REF
(-1, -2, -3, -4)
Unloaded outputs, 35-MHz REF
(-1, -2, -3, -4)
20.0
mA
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
TIMING SOLUTIONS
MOTOROLA
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MPC962308
Table 7. Switching Characteristics for MPC962308-X Industrial Temperature Devices1
Parameter
Name
Test Conditions
30-pF load, All devices
Min
Typ
Max
Unit
t1
Output Frequency
10
100
MHz
Output Frequency2
Output Frequency2
t1
t1
20-pF load, -1H, -5H devices
10
10
133.3
133.3
60.0
MHz
MHz
%
15-pF load, -1, -2, -3, -4 devices
Duty Cycle2 = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT =66.66 MHz
30-pF load
40.0
Duty Cycle2 = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT <50.0 MHz
15-pF load
45.0
55.0
%
Rise Time2
(-1, -2, -3, -4)
t3
Measured between 0.8 V and 2.0 V,
30-pF load
2.50
1.50
1.50
2.50
1.50
1.25
200
ns
ns
ns
ns
ns
ns
ps
Rise Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
15-pF load
Rise Time2
(-1H, -5H)
Measured between 0.8 V and 2.0 V,
30-pF load
Fall Time2
(-1, -2, -3, -4)
t4
Measured between 0.8 V and 2.0 V,
30-pF load
Fall Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
15-pF load
Fall Time2
(-1H, -5H)
Measured between 0.8 V and 2.0 V,
30-pF load
Output-to-Output Skew on
same Bank (-1, -2, -3, -4)2
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at VDD/2
t5
Output-to-Output Skew
(-1H, -5H)
200
200
ps
ps
ps
ps
Output Bank A to Output
Bank B Skew (-1, -4, -5H)
Output Bank A to Output
Bank B Skew (-2, -3)
400
t6
Delay, REF Rising Edge to
FBK Rising Edge2
0
0
±250
Device-to-Device Skew2
Output Slew Rate2
t7
t8
Measured at VDD/2 on the FBK pins of devices
700
ps
Measured between 0.8 V and 2.0 V on -1H,
-5H device using Test Circuit # 2
Measured at 66.67 MHz, loaded outputs,
15-pF load
1
V/ns
tJ
Cycle-to-Cycle Jitter
(-1, -1H, -4, -5H)2
200
200
100
400
400
1.0
ps
ps
ps
ps
ps
ms
Measured at 66.67 MHz, loaded outputs,
30-pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
tJ
Cycle-to-Cycle Jitter
(-2, -3)2
Measured at 66.67 MHz, loaded outputs
30-pF load
Measured at 66.67 MHz, loaded outputs
15-pF load
PLL Lock Time2
tLOCK
Stable power supply, valid clocks presented
on REF and FBK pins
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
MOTOROLA
TIMING SOLUTIONS
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MPC962308
APPLICATIONS INFORMATION
VCC
VCC
1.4 V
CCLK
GND
VCC ÷ 2
GND
VCC
VCC
1.4 V
VCC ÷ 2
FB_IN
GND
GND
t5
t6
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
Figure 1. Output-to-Output Skew tSK(O)
Figure 2. Static Phase Offset Test Reference
VCC
VCC
1.4 V
DEVICE 1
DEVICE 2
VCC ÷ 2
GND
GND
t2
VCC
VCC ÷ 2
t1
DC = t2/t1 x 100%
GND
t7
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 4. Device-to-Device Skew
Figure 3. Output Duty Cycle (DC)
VCC = 3.3 V
2.0
0.8
tJ = |tN–tN+1
|
tN
tN+1
t4
t3
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
Figure 6. Output Transition Time Test Reference
TIMING SOLUTIONS
MOTOROLA
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MPC962308
Test Circuit #1
Test Circuit #2
VDD
VDD
1 KΩ
1 KΩ
0.1 µF
0.1 µF
0.1 µF
0.1 µF
CLKOUT
10 pF
OUTPUTS
GND
OUTPUTS
GND
CLKOUT
CLOAD
VDD
GND
VDD
GND
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on -1H, -5 device
Ordering Information (Available)
Ordering Code
MPC962308D-1
Package Name
D16
Package Type
16-pin 150-mil SOIC
MPC962308D-1R2
MPC962308D-1H
MPC962308D-1HR2
MPC962308DT-1H
MPC962308DT-1HR2
MPC962308D-2
D16
16-pin 150-mil SOIC — Tape and Reel
16-pin 150-mil SOIC
D16
D16
16-pin 150-mil SOIC — Tape and Reel
16-pin 150-mil TSSOP
DT16
DT16
D16
16-pin 150-mil TSSOP — Tape and Reel
16-pin 150-mil SOIC
MPC962308D-2R2
D16
16-pin 150-mil SOIC — Tape and Reel
Ordering Information (Planned)
Ordering Code
MPC962308D-3
Package Name
D16
Package Type
16-pin 150-mil SOIC
MPC962308D-3R2
MPC962308D-4
D16
16-pin 150-mil SOIC — Tape and Reel
16-pin 150-mil SOIC
D16
MPC962308D-4R2
MPC962308D-5H
D16
16-pin 150-mil SOIC — Tape and Reel
16-pin 150-mil SOIC
D16
MPC962308D-5HR2
MPC962308DT-5H
MPC962308DT-5HR2
D16
16-pin 150-mil SOIC — Tape and Reel
16-pin 150-mil TSSOP
DT16
DT16
16-pin 150-mil TSSOP — Tape and Reel
MOTOROLA
TIMING SOLUTIONS
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MPC962308
PACKAGE DIMENSIONS
D SUFFIX
16 LEAD SOIC PACKAGE
CASE 751B-05
ISSUE K
M
0.25
B
1.75
A
6.2
1.35
0.25
0.10
8X 5.8
PIN'S
NUMBER
0.49
0.35
0.25
16X
6
1
16
M
T A B
14X
1.27
PIN 1 INDEX
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
10.0
9.8
4
A
A
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15MM PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.25MM PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
8
9
SEATING
T
16X
PLANE
4.0
3.8
B
0.1 T
5
6. THIS DIMENSION DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT CAUSE
THE LEAD WIDTH TO EXCEED 0.62MM.
0.50
0.25 X45˚
0.25
0.19
1.25
0.40
7˚
0˚
SECTION A-A
TIMING SOLUTIONS
MOTOROLA
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MPC962308
PACKAGE DIMENSIONS
DT SUFFIX
16 LEAD TSSOP PACKAGE
CASE 948F-01
ISSUE O
K
16X REF
M
S
S
V
0.10 (0.004)
T
U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
0.15 (0.006) T
U
K
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K1
16
9
2X L/2
J1
B
-U-
SECTION N-N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
-V-
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
4.90
4.30
---
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
---
F
0.05
0.50
0.002
0.020
DETAIL E
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
-W-
C
0.10 (0.004)
6.40 BSC
0.252 BSC
8˚
H
DETAIL E
M
0˚
8˚
0˚
SEATING
PLANE
-T-
D
G
MOTOROLA
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MPC962308
NOTES
TIMING SOLUTIONS
10
MOTOROLA
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NOTES
MOTOROLA
11
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MPC962308
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