MPC9893AE [NXP]
9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48;
| 型号： | MPC9893AE |
| 厂家： | 
NXP |
| 描述： | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48 驱动 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC9893
Rev 5, 06/2005
Freescale Semiconductor
Technical Data
3.3 V 1:10 LVCMOS PLL Clock
Generator
MPC9893
The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic
clock switch and generator specifically designed for redundant clock distribution
systems. The device receives two LVCMOS clock signals and generates 12
phase aligned output clocks. The MPC9893 is able to detect a failing reference
clock signal and to dynamically switch to a redundant clock signal. The switch
from the failing clock to the redundant clock occurs without interruption of the
output clock signal (output clock slews to alignment). The phase bump typically
caused by a clock failure is eliminated.
LOW VOLTAGE
2.5 V AND 3.3 V IDCS AND
PLL CLOCK GENERATOR
The device offers 12 low skew clock outputs organized into two output banks,
each configurable to support the different clock frequencies.
The extended temperature range of the MPC9893 supports
telecommunication and networking requirements. The device employs a fully
differential PLL design to minimize jitter.
FA SUFFIX
48-LEAD LQFP PACKAGE
CASE 932-03
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12-output LVCMOS PLL clock generator
2.5 V and 3.3 V compatible
IDCS - on-chip intelligent dynamic clock switch
Automatically detects clock failure
Smooth output phase transition during clock failover switch
7.5 – 200 MHz output frequency range
AE SUFFIX
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 932-03
LVCMOS compatible inputs and outputs
External feedback enables zero-delay configurations
Supports networking, telecommunications and computer applications
Output enable/disable and static test mode (PLL bypass)
Low skew characteristics: maximum 50 ps output-to-output (within bank)
48-lead LQFP package
48-lead Pb-free package available
Ambient operating temperature range of -40 to 85°C
Functional Description
The MPC9893 is a 3.3 V or 2.5 V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated
PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two,
three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same fre-
quency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication
of the input reference clock by 3÷2 and 1÷2. Bank A and bank B outputs are phase-aligned(1). Due to the external PLL feedback,
the clock signals of both output banks are also phase-aligned(1) to the selected input reference clock, providing virtually zero-de-
lay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure individually for each clock
input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew
to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable, also supporting the switch
to a failed clock that was restored. The MPC9893 also provides a manual mode that allows for user-controlled clock switches.
The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the
MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can
be disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893.
On power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for
power-on sequence recommendations.
The device is packaged in a 7x7 mm2 48-lead LQFP package.
1. At coincident rising edges.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
QA0
QA1
QA2
0
1
0
1
CLK0
CLK1
FB
(Pulldown)
(Pulldown)
(Pulldown)
Ref
D
Q
PLL
240 – 400 MHz
QA3
QA4
QA5
FB
IDCS
REF_SEL
(Pulldown)
(Pullup)
MAN/A
ALARM_RST
QB0
QB1
QB2
QB3
QB4
QB5
(Pullup)
D
Q
PLL_EN
(Pulldown)
(Pulldown)
FSEL[0:3]
Data
Generator
QFB
D
Q
ALARM0
ALARM1
CLK_IND
(Pulldown)
OE/MR
Figure 1. MPC9893 Logic Diagram
36 35 34 33 32 31 30 29 28 27 26 25
GND
QA0
QA1
GND
QB0
QB1
37
24
23
22
21
20
19
18
17
16
15
14
13
38
39
40
41
42
43
44
45
46
47
48
V
V
CC
CC
GND
QA2
QA3
GND
QB2
QB3
MPC9893
V
V
CC
CC
GND
QB4
QB5
GND
QA4
QA5
V
V
CC
CC
1
2
3
4
5
6
7
8
9 10 11 12
It is recommended to use an external
RC filter for the analog power supply
pin V
. Please see application
CC_PLL
section for details.
Figure 2. MPC9893 48-Lead Pinout (Top View)
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
2
Table 1. Pin Configurations
Number
CLK0, CLK1
FB
Name
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Description
Input
Input
Input
Input
Input
Input
Input
Input
PLL reference clock inputs
PLL feedback signal input, connect directly to QFB output
Selects the primary reference clock
REF_SEL
MAN/A
Selects automatic switch mode or manual reference clock selection
Reset of alarm flags and selected reference clock
Select PLL or static test mode
ALARM_RST
PLL_EN
FSEL[0:3]
OE/MR
Clock frequency selection and configuration of clock divider modes
Output enable/disable and device reset
QA[0:5]
Output
Output
Output
Output
Output
Output
Supply
Supply
Bank A clock outputs
QB[0:5]
Bank B clock outputs
QFB
Clock feedback output. QFB must be connected to FB for correct operation
Indicates clock failure on CLK0
ALARM0
ALARM1
CLK_IND
GND
Indicates clock failure on CLK1
Indicates currently selected input reference clock
Negative power supply
V
V
Positive power supply for the PLL (analog power supply). It is recommended to use an
CC_PLL
CC
external RC filter for the analog power supply pin V
section for details.
. Please see the application
CC_PLL
V
Supply
V
Positive power supply for I/O and core
CC
CC
Table 2. Function Table
Control
Inputs
Default
0
1
PLL_EN
0
PLL enabled. The input to output frequency relationship PLL bypassed and IDCS disabled. The VCO output is
is that according to Table 3 if the PLL is frequency
locked.
replaced by the reference clock signal fref. The MPC9893
is in manual mode.
MAN/A
1
1
Manual clock switch mode. IDCS disabled. Clock
failure detection and output flags ALARM0, ALARM1, detection and output flags ALARM0, ALARM1, CLK_IND
CLK_IND are enabled.
Automatic clock switch mode. IDCS enabled. Clock failure
are enabled. IDCS overrides REF_SEL on a clock failure.
IDCS operation requires PLL_EN = 0.
ALARM_RST
ALARM0, ALARM1 and CLK_IND flags are reset:
ALARM0=H, ALARM1=H and CLK_IND=REF_SEL.
ALARM_RST is a one-shot function.
ALARM0, ALARM1 and CLK_IND active
REF_SEL
FSEL[0:3]
OE/MR
0
0000
0
Selects CLK0 as the primary clock source
Selects CLK1 as the secondary clock source
See Table 3
Outputs enabled (active)
Outputs disabled (high impedance tristate), reset of data
generators and output dividers. The MPC9893 requires
reset at power-up and after any loss of PLL lock. Loss of
PLL lock may occur when the external feedback path is
interrupted. The length of the reset pulse should be greater
than two reference clock cycles (CLK0,1). OE/MR does not
tristate the QFB output.
Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked)
ALARM0
ALARM1
CLK_IND
CLK0 failure
CLK1 failure
CLK0 is the reference clock
CLK1 is the reference clock
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
Table 3. Clock Frequency Configuration
Name FSEL0 FSEL1 FSEL2 FSEL3
QAx
f
QBx
(1)
f
range [MHz]
QFB
REF
FB
[MHz]
f
[MHz]
QBX
Ratio
* 8
Ratio
QAX
M8
M82
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
15–25
f
f
f
f
f
120–200
120–200
120–200
60–100
120–200
15–25
f
f
f
f
f
* 8
120–200
60–100
120–200
60–100
120–200
60–100
60–100
30–50
f
f
f
f
f
f
f
f
16
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
* 4
* 4
* 2
* 3
M4
30–50
40–66.6
30–50
* 4
* 3
* 2
* 2
8
6
M42
M3
M32
f
* 3 ÷ 2
REF
M2M
M22M
M2H
M22H
M1L
f
f
* 2
8
REF
f
REF
60–100
15–25
* 2
120–200
60–100
15–25
4
REF
f
f
REF
REF
f
f
f
16
8
REF
M12L
M1M
M12M
M1H
M12H
f
f
f
÷ 2
7.5–12.5
30–50
REF
30–50
30–50
f
REF
REF
REF
÷ 2
15–25
REF
60–100
60–100.0
f
60–100
30–50
4
REF
÷ 2
REF
1. FB: Internal PLL feedback divider
Table 4. General Specifications
Symbol
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Min
Typ
Max
Unit
V
Condition
V
V
÷ 2
CC
TT
MM
HBM
CDM
LU
200
2000
1500
200
V
V
ESD Protection (Charged Device Model)
Latch-Up Immunity
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
4.0
Per output
Inputs
PD
C
IN
Table 5. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
Unit
V
Condition
V
Supply Voltage
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
+0.3
V
IN
CC
CC
V
V
+0.3
V
OUT
I
±20
mA
mA
°C
IN
I
±50
OUT
T
Storage Temperature
–65
125
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
MPC9893
Advanced Clock Drivers Device Data
4
Freescale Semiconductor
Table 6. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Input High Voltage
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
2.0
IH
V
Input Low Voltage
Output High Voltage
Output Low Voltage
0.8
V
IL
(1)
V
2.4
V
I
= –24 mA
OH
OH
V
0.55
0.30
V
V
I
I
= 24 mA
= 12 mA
OL
OL
OL
Z
Output Impedance
14–17
2.0
Ω
µA
mA
mA
V
OUT
I
Input Current
±200
5.0
V
V
= V or GND
CC
IN
IN
I
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Pin
CC_PLL
CC_PLL
I
4.0
All V Pins
CC
CC
V
V
÷2
CC
TT
1. The MPC9893 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
TT
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Input High Voltage
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
1.7
IH
V
Input Low Voltage
0.7
V
IL
(1)
V
Output High Voltage
1.8
V
I
I
= –15 mA
= 15 mA
OH
OH
OL
V
Output Low Voltage
0.6
V
OL
Z
Output Impedance
17–20
2.0
Ω
OUT
I
Input Current
±200
5.0
µA
mA
mA
V
V
V
= V or GND
CC
IN
IN
I
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Pin
CC_PLL
CC_PLL
I
4.0
All V Pins
CC
CC
V
V
÷2
CC
TT
1. The MPC9893 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines per
TT
output.
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
5
Table 8. AC Characteristics (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
PLL locked
f
Input Frequency
FSEL=000x
ref
15.0
30.0
40.0
30.0
60.0
15.0
30.0
60.0
25.0
50.0
66.6
50.0
100.0
12.5
50.0
100.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FSEL=001x
FSEL=010x
FSEL=011x
FSEL=100x
FSEL=101x
FSEL=110x
FSEL=111x
f
Maximum Output Frequency
PLL locked
MAX
FSEL=000x
FSEL=001x
FSEL=010x
FSEL=011x
FSEL=100x
FSEL=101x
FSEL=110x
FSEL=111x
60.0
60.0
60.0
30.0
60.0
7.5
200.0
200.0
200.0
100.0
200.0
25.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
15.0
30.0
50.0
100.0
f
Reference Input Duty Cycle
CLK0, 1 Input Rise/Fall Time
40
60
%
refDC
t , t
1.0
ns
0.8 to 2.0 V
PLL locked
r
f
t
Propagation Delay (static phase offset, CLKx to FB)
(∅)
V
=3.3 V±5% and FSEL[0:2]=111
–60
+50
+100
+25
ps
ps
ps
ps
CC
V
=3.3 V±5%
–200
–125
–400
CC
V
=2.5 V±5% and FSEL[0:2]=111
CC
V
=2.5 V±5%
+100
CC
∆ t
Rate of Period Change (phase slew rate)
Failover switch
QAx outputs
QBx outputs (FSEL=xxx0)
QBx outputs (FSEL=xxx1)
150
150
300
ps/cycle
(2)
t
Output-to-Output Skew
(within bank)
(bank-to-bank)
(any output to QFB)
150
100
125
ps
ps
ps
sk(O)
DC
Output Duty Cycle
45
50
55
1.0
10
10
%
ns
ns
ns
O
t , t
Output Rise/Fall Time
Output Disable Time
Output Enable Time
0.1
0.55 to 2.4 V
r
f
t
PLZ, HZ
t
PZL, LZ
(3)
t
Cycle-to-Cycle Jitter
FSEL3=0
FSEL3=1
225
425
ps
ps
See applications
section
JIT(CC)
(3)
t
Period Jitter
FSEL3=0
FSEL3=1
150
250
ps
ps
See applications
section
JIT(PER)
(4)
t
I/O Phase Jitter
See applications
section
JIT(∅)
FB=4: FSEL[0:2]=100 or 111
FB=6: FSEL[0:2]=010
FB=8: FSEL[0:2]=001, 011, or 110
FB=16: FSEL[0:2]=000 or 101
RMS (1 σ)
RMS (1 σ)
RMS (1 σ)
RMS (1 σ)
40
50
55
70
ps
ps
ps
ps
(5)
BW
PLL Closed Loop Bandwidth
FSEL=111x
0.8-4.0
MHz
ms
t
Maximum PLL Lock Time
10
LOCK
1. AC characteristics apply for parallel output termination of 50 Ω to V
.
TT
2. See application section for part-to-part skew calculation.
3. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section.
4. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See APPLICATIONS INFORMATION for more information
and for the calculation for other confidence factors than 1σ.
5. –3dB point of PLL transfer characteristics.
MPC9893
Advanced Clock Drivers Device Data
6
Freescale Semiconductor
APPLICATIONS INFORMATION
positive edge of both signals. Output runt pulses are
Definitions
eliminated.
IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors
both primary and secondary clock signals. Upon a failure of
the primary clock signal, the IDCS switches to a valid
secondary clock signal and status flags are set.
Reset
ALARM_RST is asserted by a negative edge. It generates
a one-shot reset pulse that clears both ALARMx latches and
the CLK_IND latch. If both CLK0 and CLK1 are invalid or fail
when ALARM_RST is asserted, both ALARMx flags will be
latched after one FB signal period and CLK_IND will be
latched (L) indicating CLK0 is the reference signal. While
neither ALARMx flag is latched (ALARMx = H), the CLK_IND
can be freely changed with REF_SEL.
Reference clock signal fref: The clock signal that is selected
by the IDCS or REF_SEL as the input reference to the PLL.
Manual mode: The reference clock frequency is selected by
REF_SEL.
Automatic mode: The reference clock frequency is
determined by the internal IDCS logic.
Primary clock: The input clock signal selected by REF_SEL.
The primary clock may or may not be the reference clock,
depending on switch mode and IDCS status.
OE/MR: Reset the data generator and output disable.
Does not reset the IDCS flags.
Acquiring Frequency Lock at Startup
Secondary clock: The input clock signal not selected by
REF_SEL
1. On startup, OE/MR must be asserted to reset the output
dividers. The IDCS should be disabled (MAN/A=0)
during startup to select the manual mode and the
primary clock.
Selected clock: The CLK_IND flag indicates the reference
clock signal: CLK_IND = 0 indicates CLK0 is the clock
reference signal, CLK_IND =1 indicates CLK1 is the
reference clock signal.
2. The PLL will attempt to gain lock if the primary clock is
present on startup. PLL lock requires the specified lock
time.
Clock failure: A valid clock signal that is stuck (high or low) for
at least one input clock period. The primary clock and the
secondary clock is monitored for failure. Valid clock signals
must be within the AC and DC specification for the input
reference clock. A loss of clock is detected if as well as the
loss of both clocks. In the case of both clocks lost, the
MPC9893 will set the alarm flags and the PLL will stall. The
MPC9893 does not monitor and detect changes in the input
frequency.
3. Applying a high to low transition to ALARM_RST will
clear the alarm flags.
4. Enable the IDCS (MAN/A=1) to enable to IDCS.
Power Supply Filtering
The MPC9893 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL (PLL) power supply impacts the device
characteristics, for instance I/O jitter. The MPC9893 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCC_PLL) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9893. Figure 3 illustrates a typical
power supply filter scheme. The MPC9893 frequency and
phase stability is most susceptible to noise with spectral
content in the 100kHz to 20MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data sheet
the ICC_PLL current (the current sourced through the VCC_PLL
pin) is typically 2 mA (5 mA maximum), assuming that a
minimum of 2.325 V (VCC = 3.3 V or VCC = 2.5 V) must be
maintained on the VCC_PLL pin. The resistor RF shown in
Figure 3 must have a resistance of 9-10 Ω to meet the voltage
drop criteria.
Automatic Mode and IDCS Commanded Clock Switch
MAN/A = 1, IDCS enabled: Both primary and secondary
clocks are monitored. The first clock failure is reported by its
ALARMx status flag (clock failure is indicated by a logic low).
The ALARMx status is flag latched and remains latched until
reset by assertion of ALARM_RST.
If the clock failure occurs on the primary clock, the IDCS
attempts to switch to the secondary clock. The secondary
clock signal needs to be valid for a successful switch. Upon a
successful switch, CLK_IND indicates the reference clock,
which may now be different as that originally selected by
REF_SEL.
Manual Mode
MAN/A = 0, IDCS disabled: PLL functions normally and
both clocks are monitored. The reference clock signal will
always be the clock signal selected by REF_SEL and will be
indicated by CLK_IND.
Clock Output Transition
A clock switch, either in automatic or manual mode,
follows the next negative edge of the newly selected
reference clock signal. The feedback and newly selected
reference clock edge will start to slew to alignment at the next
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
7
This maximum timing uncertainty consist of four
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
R
= 5–15Ω
C = 22 µF
F
F
R
F
V
V
CC_PLL
CC
C
10 nF
F
MPC9893
TCLK
QFB
Common
t
PD,LINE(FB)
—t(ý)
V
CC
33...100 nF
Device 1
t
JIT(∅)
Figure 3. VCC_PLL Power Supply Filter
Any Q
Device 1
+t
SK(O)
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9893 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
+t
(∅)
QFB
Device2
t
JIT(∅)
Any Q
Device 2
+t
SK(O)
Max. skew
t
SK(PP)
Figure 4. MPC9893 Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1 σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 9.
Table 9. Confidence Factor CF
CF
Probability of clock edge within the distribution
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
Using the MPC9893 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9893. Designs using the MPC9893 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9893 clock driver allows for its use as a zero delay
buffer. The the propagation delay through the device is
virtually eliminated. The PLL aligns the feedback clock output
edge with the clock input reference edge resulting a near zero
delay through the device. The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or long-
term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a I/
O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from the common
clock input to any MPC9893 output of –275 ps to +265 ps
relative to the reference clock input CLK0/1:
tSK(PP)
=
[–60ps...50ps] + [-125ps...125ps] +
[(30ps ⋅ –3)...(30ps ⋅ 3)] + tPD, LINE(FB)
Calculation of Part-to-Part Skew
tSK(PP)
=
[–275ps...265ps] + tPD, LINE(FB)
The MPC9893 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9893 are connected together, the maximum overall
timing uncertainty from the common CLK0 or CLK1 input to
any output is:
Example configuration: fref = 100 MHz, VCC = 3.3 V
VCO = 400 MHz, FSEL[0:2]=111
f
tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) ⋅ CF
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
8
The I/O (Phase) jitter of the MPC9893 depends on the
internal VCO frequency and the PLL feedback divider
configuration. A high internal VCO frequency and a low PLL
feedback divider result in lower I/O jitter than the jitter limits in
the AC characteristics (Table 8). When calculating the part-
to-part skew, Table 10 should be used to determine the actual
VCO frequency, then use Figure 5 to determine the maximum
I/O jitter for the specific VCO frequency and divider
configuration. In above example calculation, the internal VCO
frequency of 400 MHz corresponds to a maximum I/O jitter of
30 ps (RMS).
Period Jitter versus Frequency
Parameter: Output Configuration
300
250
200
150
100
50
PSEL=xxx1
PSEL=xxx0
0
240
260
280
300
320
340
360
380
400
Table 10. Internal VCO Frequency fVCO
VCO frequency [MHz]
MPC9893
Configuration
PLL Feedback
Divider FB
Figure 7. Max. Period Jitter versus VCO Frequency
f
VCO
Driving Transmission Lines
M1H, M12H, M2H, M22H
M3, M32
4 * f
6 * f
8 * f
4
6
8
ref
ref
ref
The MPC9893 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50 Ω resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9893 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 8 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9893 clock driver is effectively doubled
due to its capability to drive multiple lines.
M1M, M12M, M2M, M22M,
M4, M42
M1L, M12L, M8, M82
16 * f
16
ref
I/O Phase Jitter versus Frequency
Parameter: PLL/Feedback Configuration
FB=16: FSEL[0:2]=000, 101
FB=8: FSEL[0:2]=001, 011, 110
70
60
50
40
30
20
FB=6: FSEL[0:2}=010
FB=4: FSEL[0:2]=100, 111
10
0
240
260
280
300
320
340
360
380
400
VCO frequency [MHz]
Figure 5. Max. I/O Phase Jitter versus VCO Frequency
The cycle-to-cycle jitter and period jitter of the MPC9893
depend on the output configuration and on the frequency of
the internal VCO. Using the outputs of bank A and bank B at
the same frequency (FSEL3=0) results in a lower jitter than
the split output frequency configuration (FSEL3=1). The jitter
also decreases with an increasing internal VCO frequency.
Figure 5 to Figure 7 represent the maximum jitter of the
MPC9893.
MPC9893
Output
Buffer
Z
= 50Ω
O
R
= 36Ω
S
14Ω
OutA
In
In
Cycle-to-Cycle Jitter versus Frequency
Parameter: Output Configuration
MPC9893
Output
Buffer
500
400
Z
Z
= 50Ω
= 50Ω
O
R
= 36Ω
= 36Ω
S
OutB0
OutB1
PSEL3=1
14Ω
300
O
R
S
200
PSEL3=0
100
0
240
Figure 8. Single versus Dual Transmission Lines
260
280
300
320
340
360
380
400
VCO frequency [MHz]
Figure 6. Max. Cycle-to-Cycle Jitter versus
VCO Frequency
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
9
The waveform plots in Figure 9 show the simulation results
of an output driving a single line versus two lines. In both
cases the drive capability of the MPC9893 output buffer is
more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9893. The output waveform
in Figure 9 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
3.0
2.5
2.0
1.5
1.0
0.5
0
OutA
= 3.8956
OutB
= 3.9386
t
D
t
D
In
VL = VS (Z0 ÷ (RS+R0 +Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
VL = 3.0 (25 ÷ (18+17+25)
= 1.31 V
2
4
6
8
10
12
14
Time (ns)
Figure 9. Single versus Dual Waveforms
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 10 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC9893
Output
Buffer
Z
= 50Ω
= 50Ω
O
R
R
= 22Ω
= 22Ω
S
14Ω
Z
O
S
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 10. Optimized Dual Line Termination
MPC9893 DUT
Pulse
Generator
Z = 50Ω
Z
= 50Ω
Z = 50Ω
O
O
R
= 50Ω
R = 50Ω
T
T
V
V
TT
TT
Figure 11. CLK0, CLK1 MPC9893 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
10
V
V
CC
CC
÷ 2
GND
V
V
CC
CC
V
V
CC
CC
CLK0,
CLK1
÷ 2
÷ 2
GND
GND
V
V
CC
CC
t
÷ 2
SK(O)
FB
GND
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
t
(∅)
Figure 12. Output-to-Output Skew tSK(O)
Figure 13. Propagation Delay (t(∅), static phase
offset) Test Reference
V
V
CC
÷ 2
CCLK0, 1
CC
GND
t
P
FB
T
0
DC = t /T x 100%
P
0
T
= |T –T mean|
0 1
JIT(∅)
The time from the PLL controlled edge to the noncontrolled edge, divided by
the time between PLL controlled edges, expressed as a percentage
The deviation in t for a controlled edge with respect to a t mean in a random sample
0
0
of cycles
Figure 14. Output Duty Cycle (DC)
Figure 15. I/O Jitter
T
= |T –T
|
T
= |T –1/f |
N 0
JIT(CC)
N
N+1
JIT(PER)
T
T
N+1
T
N
0
The variation in cycle time of a signal between adjacent cycles, over a random sample
of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random
sample of cycles
Figure 16. Cycle-to-Cycle Jitter
Figure 17. Period Jitter
V
=3.3 V
2.4
V
=2.5 V
1.8
CC
CC
0.55
0.6
t
t
R
F
Figure 18. Output Transition Time Test Reference
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
11
PACKAGE DIMENSIONS
4X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5m, 1994.
0.200 AB T-U
Z
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLAN AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATAUM PLANE AB.
DETAILY
P
9
A
A1
48
37
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
36
1
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
T
U
B
V
AE
AE
B1
V1
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
12
25
13
MILLIMETERS
24
DIM MIN
MAX
7.000 BSC
3.500 BSC
Z
A
A1
B
B1
C
S1
7.000 BSC
3.500 BSC
T, U, Z
1.400
1.600
0.270
1.450
0.230
S
D
E
F
0.170
1.350
0.170
DETAILY
4X
0.200 AC T-U
Z
G
H
J
K
L
M
N
P
0.500 BSC
0.050
0.090
0.500
0˚
0.150
0.200
0.700
7˚
0.080 AC
12˚ REF
G
AB
AC
0.090
0.150
0.160
0.250 BSC
R
0.250
S
S1
V
V1
W
AA
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
AD
M˚
BASE METAL
TOP & BOTTOM
R
N
J
E
C
F
D
M
0.080
AC T- U Z
SECTION AE-AE
W
H
L˚
K
DETAIL AD
AA
CASE 932-03
ISSUE F
48-LEAD LQFP PACKAGE
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
12
NOTES
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
13
NOTES
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
14
NOTES
MPC9893
Advanced Clock Drivers Device Data
Freescale Semiconductor
15
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MPC9893
Rev. 5
06/2005
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