MPE603EFE100LX_技术文档

Freescale Semiconductor, Inc.

G522-0268-00

(IBM Order Number)

MPC603EEC/D

(Motorola Order Number)

5/1999

Rev. 2

™

Advance Information

PowerPC 603e^™RISC Microprocessor Family:

PID6-603e Hardware Speciﬁcations

The PowerPC 603e microprocessor is an implementation of the PowerPC™ family of

reduced instruction set computing (RISC) microprocessors. In this document, the term

‘603e’ is used as an abbreviation for the phrase, ‘PowerPC 603e microprocessor’. The

PowerPC 603e microprocessors are available from Motorola as MPC603e and from IBM

as PPC603e.

Note that the 603e is implemented in both a 2.5-volt version (PID 0007t PowerPC 603e

microprocessor, abbreviated as PID7t-603e) and a 3.3-volt version (PID 0006 PowerPC

603e microprocessor, abbreviated as PID6-603e). This document describes the pertinent

physical characteristics of the PID6-603e. For functional characteristics of the processor,

refer to the PowerPC 603e RISC Microprocessor Users Manual.

This document contains the following topics:

Topic

Page

Section 1.1, “Overview”

2

Section 1.2, “Features”

3

Section 1.3, “General Parameters”

4

Section 1.4, “Electrical and Thermal Characteristics”

Section 1.5, “PowerPC 603e Microprocessor Pin Assignments”

Section 1.6, “PowerPC 603e Microprocessor Pinout Listings”

Section 1.7, “PowerPC 603e Microprocessor Package Description”

Section 1.8, “System Design Information”

Section 1.10, “Ordering Information”

4

14

16

20

24

31

of International Business Machines Corporation,

used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK

The PowerPC name, the PowerPC logotype, PowerPC 603, and PowerPC 603e are trademarks

This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to

change or discontinue this product without notice.

©

Portions hereof

©

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To locate any published errata or updates for this document, refer to the website at

http://www.mot.com/powerpc/ or at http://www.chips.ibm.com/products/ppc.

1.1 Overview

The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set

computer (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture

speciﬁcation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and

ﬂoating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture

provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit

architecture.

The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and

sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.

The fourth is a dynamic power management mode that causes the functional units in the 603e to

automatically enter a low-power mode when the functional units are idle without affecting operational

performance, software execution, or any external hardware.

The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.

Instructions can execute out of order for increased performance; however, the 603e makes completion

appear sequential.

The 603e integrates ﬁve execution units—an integer unit (IU), a ﬂoating-point unit (FPU), a branch

processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute ﬁve

instructions in parallel and the use of simple instructions with rapid execution times yield high efﬁciency

and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is

pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches

for instructions and data, as well as on-chip instruction and data memory management units (MMUs). The

MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB

and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized

block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e

also supports block address translation through the use of two independent instruction and data block

address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared

simultaneously with all four entries in the BAT array during block translation. In accordance with the

PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes

priority.

The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows

multiple masters to compete for system resources through a central external arbiter. The 603e provides a

three-state coherency protocol that supports the exclusive, modiﬁed, and invalid cache states. This protocol

is a compatible subset of the MESI (modiﬁed/exclusive/shared/invalid) four-state protocol and operates

coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers

for memory accesses, and supports memory-mapped I/O.

The 603e uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility

with TTL devices.

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1.2 Features

This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major features

of the 603e are as follows:

•

High-performance, superscalar microprocessor

— As many as three instructions issued and retired per clock

— As many as ﬁve instructions in execution per clock

— Single-cycle execution for most instructions

— Pipelined FPU for all single-precision and most double-precision operations

•

Five independent execution units and two register ﬁles

— BPU featuring static branch prediction

— A 32-bit IU

— Fully IEEE 754-compliant FPU for both single- and double-precision operations

— LSU for data transfer between data cache and GPRs and FPRs

— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and

integer add/compare instructions

— Thirty-two GPRs for integer operands

— Thirty-two FPRs for single- or double-precision operands

High instruction and data throughput

•

— Zero-cycle branch capability (branch folding)

— Programmable static branch prediction on unresolved conditional branches

— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache

— A six-entry instruction queue that provides lookahead capability

— Independent pipelines with feed-forwarding that reduces data dependencies in hardware

— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement

algorithm

— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU replacement

algorithm

— Cache write-back or write-through operation programmable on a per page or per block basis

— BPU that performs CR lookahead operations

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— A 64-entry, two-way set-associative ITLB

— A 64-entry, two-way set-associative DTLB

— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks

— Software table search operations and updates supported through fast-trap mechanism

— 52-bit virtual address; 32-bit physical address

•

Facilities for enhanced system performance

— A 32- or 64-bit split-transaction external data bus with burst transfers

— Support for one-level address pipelining and out-of-order bus transactions

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•

Integrated power management

— Low-power 3.3-volt design

— Internal processor/bus clock multiplier that provides 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1

ratios

— Three power saving modes: doze, nap, and sleep

— Automatic dynamic power reduction when internal functional units are idle

In-system testability and debugging features through JTAG boundary-scan capability

•

1.3 General Parameters

The following list provides a summary of the general parameters of the 603e.

Technology

Die size

0.5 µ CMOS, four-layer metal

2

11.67 mm x 8.4 mm (98 mm )

Transistor count

Logic design

Package

2.6 million

Fully-static

Surface mount 240-pin ceramic quad ﬂat pack (CQFP)

or 255-pin ceramic ball grid array (CBGA)

Power supply

3.3 ± 5% V dc

1.4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical speciﬁcations and thermal characteristics for the 603e.

1.4.1 DC Electrical Characteristics

The tables in this section describe the 603e DC electrical characteristics. Table 1 provides the absolute

maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic

Symbol

Value

Unit

Core supply voltage

PLL supply voltage

I/O supply voltage

Input voltage

Vdd

–0.3 to 4.0

–0.3 to 5.5

–55 to 150

V

AVdd

OVdd

V

in

Storage temperature range

T

°C

stg

Notes:

1. Functional operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. Caution: V must not exceed OVdd by more than 2.5 V at any time including during power-on reset.

in

3. Caution: OVdd must not exceed Vdd/AVdd by more than 2.5 V at any time including during power-on reset.

4. Caution: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time including during power-on reset.

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Table 2 provides the recommended operating conditions for the 603e.

Table 2. Recommended Operating Conditions

Characteristic

Core supply voltage

Symbol

Value

Unit

Notes

Vdd

3.3 ± 165mv

-0.3 to 5.5

0 to 105

V

PLL supply voltage

I/O supply voltage

Input voltage

AVdd

OVdd

V

in

Die-junction temperature

Notes:

T

°C

2

j

1. These are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

2. The extended temperature parts have die-junction temperature of -40 to 105 °C.

Table 3 provides the packages thermal characteristics for the 603e.

Table 3. Package Thermal Characteristics

Characteristic

Symbol

Value

Rating

Wire-bond CQFP package die junction-to-case thermal resistance

(typical)

θ

2.2

°C/W

JC

Wire-bond CQFP package die junction-to-lead thermal resistance

(typical)

θ

18.0

°C/W

JB

CBGA package die junction-to-case thermal resistance (typical)

CBGA package die junction-to-ball thermal resistance (typical)

θ

0.08

2.8

°C/W

JC

JB

Note: Refer to Section 1.8, “System Design Information,” for more details about thermal management.

Table 4 provides the DC electrical characteristics for the 603e.

Table 4. DC Electrical Specifications

At recommended operating conditions. See Table 2.

Characteristic

Symbol

Min

2.0

Max

5.5

Unit

Notes

Input high voltage (all inputs except SYSCLK)

Input low voltage (all inputs except SYSCLK)

SYSCLK input high voltage

V

IH

-0.3

2.4

-0.3

—

0.8

5.5

0.4

10

IL

CV

IH

SYSCLK input low voltage

IL

Input leakage current, V = 3.465 V

I

µA

1

in

I

—

245

V

= 5.5 V

in

Hi-Z (off-state) leakage current, V = 3.465 V

I

—

10

µA

1

in

TSI

245

V

= 5.5 V

in

Output high voltage, I = –9 mA

V

2.4

—

V

1

OH

Output low voltage, I = 14 mA

0.4

OL

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Table 4. DC Electrical Specifications (Continued)

At recommended operating conditions. See Table 2.

Characteristic

Symbol

Min

Max

10.0

Unit

pF

Notes

Capacitance, V = 0 V, f = 1 MHz (excludes TS, ABB, DBB,

C

—

2

in

and ARTRY)

Capacitance, V = 0 V, f = 1 MHz (for TS, ABB, DBB, and

C

15.0

pF

2

in

ARTRY)

Notes:

1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and JTAG signals.

2. Capacitance is periodically sampled rather than 100% tested.

Table 5 provides the power consumption for the 603e.

Table 5. Power Consumption

At recommended operating conditions. See Table 2.

Processor (CPU) Frequency

CPU Clock:

Unit

Notes

SYSCLK

100 MHz

133.33 MHz

Full-On Mode (DPM Enabled)

Typical

Max.

3.2

4.0

4.2

W

1, 3

5.3

1, 2

Doze Mode

Typical

Nap Mode

1.0

70

40

1.3

85

50

W

1, 2

Typical

Sleep Mode

Typical

mW

1, 2

Sleep Mode—PLL Disabled

Typical

5

6

mW

1, 2

Sleep Mode—PLL and SYSCLK Disabled

Typical

Notes:

3

1. These values apply for all valid bus ratios (PLL_CFG[0–3] settings). The

values do not include I/O supply power (OVdd) or PLL supply power

(AVdd). OVdd power is system dependent, but is typically <10% of Vdd

power. Worst-case power consumption for AVdd = 15 mw.

2. Maximum power is measured at Vdd = 3.465 V using a worst-case

instruction mix.

3. Typical power is an average value measured at Vdd = AVdd = OVdd = 3.3

V in a system executing typical applications and benchmark sequences

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1.4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the 603e. After fabrication, parts are sorted by

maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Speciﬁcations” and tested for

conformance to the AC speciﬁcations for that frequency. These speciﬁcations are for 100 and 133.33 MHz

processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency

and the settings of the PLL_CFG[0–3] signals. Parts are sold by maximum processor core frequency; see

Section 1.10, “Ordering Information.”

1.4.2.1 Clock AC Speciﬁcations

Table 6 provides the clock AC timing speciﬁcations as deﬁned in Figure 1.

Table 6. Clock AC Timing Specifications

At recommended operating conditions. See Table 2.

100 MHz

Min Max

133.33 MHz

Num

Characteristic

Unit

Notes

Min

50

Max

Processor frequency

50

100

133.33 MHz

266.66 MHz

1

VCO frequency

100

16.67

15.0

—

266.66

66.67

60.0

2.0

100

16.67

15.0

—

SYSCLK (bus) frequency

SYSCLK cycle time

66.67

60.0

2.0

MHz

ns

1

2,3

4

SYSCLK rise and fall time

SYSCLK duty cycle measured at 1.4 V

SYSCLK jitter

ns

2

40.0

—

60.0

±150

100

40.0

—

60.0

±150

100

%

3

ps

4

Internal PLL relock time

—

µs

3, 5

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting

SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their

respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in

Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.

2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.

3. Timing is guaranteed by design and characterization, and is not tested.

4. Cycle-to-cycle jitter, and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the

maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the

power-on reset sequence. This speciﬁcation also applies when the PLL has been disabled and

subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a

minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

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Figure 1 provides the SYSCLK input timing diagram.

1

2

3

4

CVih

VM

SYSCLK

CVil

VM = Midpoint Voltage (1.4 V)

Figure 1. SYSCLK Input Timing Diagram

1.4.2.2 Input AC Speciﬁcations

Table 7 provides the input AC timing speciﬁcations for the 603e as deﬁned in Figure 2 and Figure 3.

Table 7. Input AC Timing Specifications

At recommended operating conditions. See Table 2.

100 MHz

133.33 MHz

Num

Characteristic

Unit Notes

Min

3.0

Max

Min

3.0

Max

10a

Address/data/transfer attribute inputs valid to SYSCLK

(input setup)

—

ns

2

3

10b

10c

All other inputs valid to SYSCLK (input setup)

5.0

—

5.0

—

ns

Mode select inputs valid to HRESET (input setup) (for

DRTRY, QACK and TLBISYNC)

8*t_sysclk

4,5,6,

7

11a

SYSCLK to address/data/transfer attribute inputs

invalid (input hold)

1.0

—

1.0

—

ns

2

11b

11c

SYSCLK to all other inputs invalid (input hold)

1.0

0

—

1.0

0

—

ns

3

HRESET to mode select inputs invalid (input hold) (for

DRTRY, QACK, and TLBISYNC)

4,6,7

Notes:

1. All input speciﬁcations are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V

of the rising edge of the input SYSCLK (see Figure 2). Both input and output timings are measured at the

pin.

2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4],

TC[0–1], TBST, TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].

3. All other input signals are composed of the following— TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,

TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.

4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).

5. t_sysclkis the period of the external clock (SYSCLK) in nanoseconds.

6. These values are guaranteed by design, and are not tested.

7. This speciﬁcation is for conﬁguration mode select only. Also note that HRESET must be held asserted for a

minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

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Figure 2 provides the input timing diagram for the 603e.

VM

SYSCLK

10a

10b

11a

11b

ALL INPUTS

VM = Midpoint Voltage (1.4 V)

Figure 2. Input Timing Diagram

Figure 3 provides the mode select input timing diagram for the 603e.

HRESET

VM

10c

11c

MODE PINS

VM = Midpoint Voltage (1.4 V)

Figure 3. Mode Select Input Timing Diagram

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1.4.2.3 Output AC Speciﬁcations

Table 8 provides the output AC timing speciﬁcations for the 603e as deﬁned in Figure 4.

1

Table 8. Output AC Timing Specifications

2

At recommended operating conditions. See Table 2., C = 50 pF

L

100 MHz

Min Max

133.33 MHz

Num

Characteristic

Unit

Notes

Min

1.0

Max

12

SYSCLK to output driven (output enable time)

1.0

—

ns

13a

SYSCLK to output valid (5.5 V to 0.8 V—TS, ABB,

ARTRY, DBB)

11.0

—

11.0 ns

4

13b

14a

SYSCLK to output valid (TS, ABB, ARTRY, DBB)

—

10.0

13.0

—

10.0 ns

13.0 ns

6

4

SYSCLK to output valid (5.5 V to 0.8 V—all except TS,

ABB, ARTRY, DBB)

14b

SYSCLK to output valid (all except TS, ABB, ARTRY,

DBB)

—

11.0

—

11.0 ns

6

3

15

16

SYSCLK to output invalid (output hold)

1.5

—

1.5

—

ns

SYSCLK to output high impedance

(all except ARTRY, ABB, DBB)

9.5

17

18

19

SYSCLK to ABB, DBB, high impedance after precharge

SYSCLK to ARTRY high impedance before precharge

SYSCLK to ARTRY precharge enable

—

1.2

9.0

—

1.2

9.0

—

t

5,7

sysclk

—

ns

0.2 *

3,5,8

t

sysclk

+ 1.0

20

Maximum delay to ARTRY precharge

—

1.2

—

1.2

t

5,8

sysclk

21

SYSCLK to ARTRY high impedance after precharge

—

2.25

—

2.25

t

sysclk

Notes:

1. All output speciﬁcations are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8

V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see

Figure 4).

2. All maximum timing speciﬁcations assume C = 50 pF.

L

3. This minimum parameter assumes C = 0 pF.

L

4. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external

voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5 V CMOS levels instead of 3.3 V CMOS levels).

5. t

is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the

sysclk

table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of

the parameter in question.

6. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.

7. Nominal precharge width for ABB and DBB is 0.5 t

.

sysclk

8. Nominal precharge width for ARTRY is 1.0 t

.

sysclk

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Figure 4 provides the output timing diagram for the 603e.

VM

SYSCLK

14

15

16

12

ALL OUTPUTS

(Except TS, ABB,

DBB, ARTRY)

13

15

16

13

TS

17

ABB, DBB

21

20

19

18

ARTRY

VM = Midpoint Voltage (1.4 V)

Figure 4. Output Timing Diagram

1.4.3 JTAG AC Timing Speciﬁcations

Table 9 provides the JTAG AC timing speciﬁcations as deﬁned in Figure 5 through Figure 8.

Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions. See Table 2. C = 50 pF

L

Num

Characteristic

TCK frequency of operation

Min

Max

Unit

MHz

Notes

0

16

—

3

1

2

3

4

5

6

7

8

9

TCK cycle time

62.5

25

0

ns

TCK clock pulse width measured at 1.4 V

TCK rise and fall times

TRST setup time to TCK rising edge

TRST assert time

13

40

6

—

25

24

1

Boundary-scan input data setup time

Boundary-scan input data hold time

TCK to output data valid

2

3

27

4

TCK to output high impedance

3

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Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)

At recommended operating conditions. See Table 2. C = 50 pF

L

Num

10

Characteristic

TMS, TDI data setup time

Min

Max

Unit

Notes

0

—

24

15

ns

11

12

13

TMS, TDI data hold time

TCK to TDO data valid

25

4

TCK to TDO high impedance

3

Notes:

1. TRST is an asynchronous signal. The setup time is for test purposes only.

2. Non-test signal input timing with respect to TCK.

3. Non-test signal output timing with respect to TCK.

Figure 5 provides the JTAG clock input timing diagram.

1

2

VM

TCK

3

VM = Midpoint Voltage (1.4 V)

Figure 5. JTAG Clock Input Timing Diagram

Figure 6 provides the TRST timing diagram.

TCK

4

VM

TRST

5

Figure 6. TRST Timing Diagram

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Figure 7 provides the boundary-scan timing diagram.

VM

TCK

VM

6

7

Data Inputs

Input Data Valid

8

9

8

Data Outputs

Output Data Valid

Data Outputs

Output Data Valid

Figure 7. Boundary-Scan Timing Diagram

Figure 8 provides the test access port timing diagram.

VM

TCK

VM

10

11

TDI, TMS

Input Data Valid

12

TDO

Output Data Valid

13

TDO

12

TDO

Output Data Valid

Figure 8. Test Access Port Timing Diagram

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1.5 PowerPC 603e Microprocessor Pin Assignments

The following sections contain the pinout diagrams for the 603e. Note that the 603e is offered in both

ceramic quad ﬂat pack (CQFP) and ceramic ball grid array (CBGA) packages.

1.5.1 Pinout Diagram for the CQFP Package

Figure 9 contains the pinout diagram of the CQFP package for the 603e.

GBL

A1

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

TT4

1

2

A0

A3

A2

VDD

A4

A6

A8

OVDD

GND

OGND

A10

A12

A14

VDD

A16

A18

A20

OVDD

GND

OGND

A22

3

VDD

A5

A7

A9

OGND

GND

OVDD

A11

A13

A15

VDD

A17

A19

A21

OGND

GND

OVDD

A23

A25

A27

VDD

DBWO

DBG

BG

AACK

GND

A29

QREQ

ARTRY

OGND

VDD

OVDD

ABB

A31

DP0

GND

DP1

DP2

DP3

OGND

VDD

OVDD

DP4

4

1

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

TOP VIEW

A24

A26

VDD

DRTRY

TA

TEA

DBDIS

GND

A28

CSE1

TS

OVDD

VDD

OGND

DBB

A30

DL0

GND

DL1

DL2

DL3

OVDD

VDD

OGND

DL4

DL5

DL6

GND

DL7

DL8

DL9

DP5

DP6

GND

DP7

DL23

DL24

OGND

OVDD

DL25

DL26

DL27

DL28

VDD

OGND

OVDD

OGND

DL10

DL11

DL12

DL13

VDD

OVDD

Figure 9. Pinout Diagram for the CQFP Package

14

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1.5.2 Pinout Diagram for the CBGA Package

Figure 10 (in part A) shows the pinout of the CBGA package as viewed from the top surface. Part B

shows the side profile of the CBGA package to indicate the direction of the top surface view.

Part A

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Not to Scale

Part B

View

Substrate Assembly

Encapsulant

Die

Figure 10. Pinout of the CBGA Package as Viewed from the Top Surface

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1.6 PowerPC 603e Microprocessor Pinout Listings

The following sections contain the pinout listings for the 603e CQFP and CBGA packages.

1.6.1 Pinout Listing for the CQFP Package

Table 10 provides the pinout listing for the 603e CQFP package.

Table 10. Pinout Listing for the 240-pin CQFP Package

Signal Name

Pin Number

Active

High

I/O

A[0–31]

179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12,

168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22,

158, 23, 151, 30, 144, 37

AACK

ABB

28

Low

High

Low

High

Low

—

Input

I/O

36

AP[0–3]

APE

231, 230, 227, 226

I/O

218

32

Output

I/O

ARTRY

AVDD

BG

209

27

Input

Output

Input

Output

I/O

BR

219

237

221

215

216

225, 150

145

153

26

CI

CLK_OUT

CKSTP_IN

CKSTP_OUT

Low

High

Low

High

1

CSE[0–1]

DBB

DBDIS

DBG

Input

I/O

DBWO

DH[0–31]

25

115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92,

91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73,

72, 71, 68, 67, 66

DL[0–31]

143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126,

125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101,

100, 51, 52, 55, 56, 57, 58, 62, 63, 64

High

I/O

DP[0–7]

DPE

38, 40, 41, 42, 46, 47, 48, 50

High

Low

I/O

217

156

1

Output

Input

I/O

DRTRY

GBL

GND

9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172,

182, 206, 239

Input

HRESET

INT

214

188

Low

Input

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Table 10. Pinout Listing for the 240-pin CQFP Package (Continued)

Signal Name

Pin Number

Active

I/O

2

LSSD_MODE

205

204

203

186

Low

—

Input

2

L1_TSTCLK

2

L2_TSTCLK

—

MCP

Low

OGND

8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127,

136, 146, 161, 171, 181, 193, 220, 228, 238

3

OVDD

10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121,

128, 138, 148, 163, 173, 183, 194, 222, 229, 240

High

Input

PLL_CFG[0–3]

QACK

QREQ

RSRV

SMI

213, 211, 210, 208

High

Low

—

Input

Output

Input

I/O

235

31

232

187

SRESET

SYSCLK

TA

189

212

155

Low

High

Low

High

—

TBEN

TBST

234

192

TC[0–1]

TCK

224, 223

Output

Input

Output

Input

I/O

201

TDI

199

High

Low

High

Low

High

Low

High

TDO

198

TEA

154

TLBISYNC

TMS

233

200

TRST

202

TSIZ[0–2]

TS

197, 196, 195

149

I/O

TT[0–4]

191, 190, 185, 184, 180

I/O

3

VDD

4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 High

236 Low

Input

Output

WT

Notes:

1. There are two CSE signals in the 603e—CSE0 and CSE1. The XATS signal in the PowerPC 603™

microprocessor is replaced by the CSE1 signal in 603e.

2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.

3. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. Future

members of the 603 family may use different OVdd and Vdd input levels.

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1.6.2 Pinout Listing for the CBGA Package

Table 11 provides the pinout listing for the 603e CBGA package.

Table 11. Pinout Listing for the 255-pin CBGA Package

Signal Name

A[0–31]

Pin Number

Active

High

I/O

C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13,

GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16,

F04, G13, K01, G15, K02, H16, M01, J15, P01

I/O

AACK

L02

Low

High

Low

—

Input

I/O

ABB

K04

AP[0–3]

APE

C01, B04, B03, B02

I/O

A04

J04

Output

I/O

ARTRY

AVDD

A10

L01

—

BG

Low

—

Input

Output

Input

Output

I/O

BR

B06

E01

D08

A06

D07

B01, B05

J14

CI

CKSTP_IN

CKSTP_OUT

CLK_OUT

CSE[0–1]

DBB

High

Low

High

DBG

N01

H15

G04

Input

I/O

DBDIS

DBWO

DH[0–31]

P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10,

P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07,

P06, N06, R06, T06, R05, N05, T05, T04

DL[0–31]

K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15,

N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03,

N03, N04, R03, T01, T02, P04, T03, R04

High

I/O

DP[0–7]

DPE

M02, L03, N02, L04, R01, P02, M04, R02

High

Low

—

I/O

A05

G16

F01

Output

Input

I/O

DRTRY

GBL

GND

C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12,

G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12,

K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09,

M11, M14, P05, P12

—

HRESET

INT

A07

B15

D11

Low

—

Input

1

L1_TSTCLK

18

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Table 11. Pinout Listing for the 255-pin CBGA Package (Continued)

Signal Name

Pin Number

Active

I/O

Input

1

L2_TSTCLK

D12

B10

C13

—

1

LSSD_MODE

MCP

Low

—

Input

—

NC

B07, B08, C03, C06, C08, D05, D06, F03, H04, J16

OVDD

C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05,

K12, K14, M05, M07, M10, M12, P07, P10

PLL_CFG[0–3]

QACK

QREQ

RSRV

SMI

A08, B09, A09, D09

High

Low

—

Input

Output

Input

I/O

D03

J03

D01

A16

SRESET

SYSCLK

TA

B14

C09

H14

Low

High

Low

High

—

TBEN

TBST

C02

A14

TC[0–1]

TCK

A02, A03

Output

Input

Output

Input

I/O

C11

TDI

A11

High

Low

High

Low

High

Low

—

TDO

A12

TEA

H13

TLBISYNC

TMS

C04

B11

TRST

TS

C10

J13

TSIZ[0–2]

TT[0–4]

WT

A13, D10, B12

B13, A15, B16, C14, C15

D02

I/O

Output

—

2

VDD

F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08,

J09, J11, K07, K10, L06, L08, L09, L11

Notes:

1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.

2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. Future

members of the 603 family may use different OVdd and Vdd input levels.

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1.7 PowerPC 603e Microprocessor Package

Description

The following sections provide the package parameters and the mechanical dimensions for the 603e.

1.7.1 CQFP Package Description

The following sections provide the package parameters and mechanical dimensions for the Motorola CQFP

package.

1.7.1.1 Package Parameters

The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin

ceramic quad ﬂat pack.

Package outline

Interconnects

Pitch

32 mm x 32 mm

240

0.5 mm

20

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1.7.1.2 Mechanical Dimensions of the CQFP Package

Figure 11 shows the mechanical dimensions of the Motorola CQFP package.

AB

θI

R

–H–

θ2

R

H

G

AA

F

C

A

J

B

*Reduced pin count shown for clarity. 60 pins per side

Min. Max.

30.86 31.75

34.6 BSC

A

B

C

3.75 4.15

0.5 BSC

D

E

0.18 0.30

3.10 3.90

0.13 0.175

0.45 0.55

F

G

H

J

0.25

–

AA

AB

θ1

θ2

R

1.80 REF

0.95 REF

2°

1°

6°

7°

0.15 REF

Pin 240

Pin 1

Notes: 1. BSC—Between Standard Centers.

2. All measurements in mm.

D

E

Die

Wire Bonds

Ceramic Body

Alloy 42 Leads

*Not to scale

Figure 11. Mechanical Dimensions of the Wire-Bond CQFP Package

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1.7.2 CBGA Package Description

The following sections provide the package parameters and mechanical dimensions for the CBGA package.

1.7.2.1 Package Parameters

The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-pin

ceramic ball grid array (CBGA).

Package outline

Interconnects

21 mm

255

Pitch

1.27 mm

2.45 mm

3.00 mm

0.89 mm (35 mil)

Minimum module height

Maximum module height

Ball diameter

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1.7.2.2 Mechanical Dimensions of the CBGA Package

Figure 12 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package.

2X

0.200

A

A1 CORNER

– E –

– T –

0.150T

B

P

2X

NOTES:

1. DIMENSIONING ANDTOLERANCING PER

0.200

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

N

– F –

MILLIMETERS

MIN MAX

21.000 BSC

INCHES

MIN MAX

DIM

A

B

C

D

G

H

K

N

P

0.827 BSC

1

2

3

4

5

6

7

8

9 10111213141516

T

R

P

N

M

L

K

J

H

G

F

2.450

3.000

0.930

0.096

0.118

0.036

0.820

0.790

0.032

0.031

1.270 BSC

0.050 BSC

K

0.990

0.039

0.635 BSC

0.025 BSC

H

5.000

16.000

0.197

0.630

C

E

D

C

B

A

G

K

255X

D

S

F

T E

T

0.300

0.150

S

Figure 12. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package

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1.8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the 603e.

1.8.1 PLL Conﬁguration

The 603e PLL is conﬁgured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the PLL

conﬁguration signals set the internal CPU and VCO frequency of operation. The PLL conﬁguration for the

603e is shown in Table 12 for nominal frequencies.

Table 12. PowerPC 603e Microprocessor PLL Configuration

CPU Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier Multiplier

Core -to-

VCO

Bus

16.67

MHz

Bus

20

MHz

Bus

25

MHz

Bus

33.33

MHz

Bus

40

MHz

Bus

50

MHz

Bus

60

MHz

Bus

66.67

MHz

PLL_CFG[0–3]

0000

0001

1100

0100

0101

0110

1000

1110

1010

1x

2x

4x

2x

4x

2x

—

50

(100)

60

(120)

66.67

(133)

1x

—

50

(200)

60

(240)

66.67

(266)

1.5x

2x

50

(100)

60

(120)

75

(150)

90

(180)

100

(200)

—

66.67

(133)

80

(160)

100

(200)

120

(240)

133.33

(266)

2x

50

(200)

66.67

(266)

—

2.5x

3x

50

(100)

62.5

(125)

83.33

(166)

100

(200)

125

(250)

50

(100)

60

(120)

75

(150)

100

(200)

120

(240)

—

3.5x

4x

58.4

(117)

70

(140)

87.5

(175)

116.67

(233)

—

66.67

(133)

80

(160)

100

(200)

133.33

(266)

—

0011

1111

PLL bypass

Clock off

Notes:

1. PLL_CFG[0–3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL conﬁgurations may select bus, core,

or VCO frequencies which are not useful, not supported, or not tested for by the 603e; see Section 1.4.2.1, “Clock

AC Speciﬁcations,” for valid SYSCLK and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the

bus mode is set for 1:1 mode operation. This mode is intended for factory use only.

Note: The AC timing speciﬁcations given in this document do not apply in PLL-bypass mode.

4. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.

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1.8.2 PLL Power Supply Filtering

The AVdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop.

To ensure stability of the internal clock, the power supplied to the AVdd input signal should be ﬁltered using

a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd

pin to ensure it ﬁlters out as much noise as possible.

10 Ω

Vdd

AVdd

10 µF

0.1 µF

GND

Figure 13. PLL Power Supply Filter Circuit

1.8.3 Decoupling Recommendations

Due to the 603e’s dynamic power management feature, large address and data buses, and high operating

frequencies, the 603e can generate transient power surges and high frequency noise in its power supply,

especially while driving large capacitive loads. This noise must be prevented from reaching other

components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power.

Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor at

each Vdd and OVdd pin of the 603e. It is also recommended that these decoupling capacitors receive their

power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize

inductance.

These capacitors should vary in value from 220 pF to 10 µF to provide both high- and low-frequency

ﬁltering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values

for the Vdd pins—220 pF (ceramic), 0.01 µF (ceramic), and 0.1 µF (ceramic). Suggested values for the

OVdd pins—0.01 µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT (surface mount

technology) capacitors should be used to minimize lead inductance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk

capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time

necessary. They should also be connected to the power and ground planes through two vias to minimize

inductance. Suggested bulk capacitors—100 µF (AVX TPS tantalum) or 330 µF (AVX TPS tantalum).

1.8.4 Connection Recommendations

To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level.

Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND.

All NC (no-connect) signals must remain unconnected.

1.8.5 Pull-up Resistor Requirements

The 603e requires high-resistive (weak: 10 KOhms) pull-up resistors on several control signals of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the 603e or other bus master. These signals are—TS, ABB, DBB, ARTRY.

In addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger:

4.7 KOhms–10 KOhms) if they are used by the system. These signals are—APE, DPE, and CKSTP_OUT.

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During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master

and may ﬂoat in the high-impedance state for relatively long periods of time. Since the 603e must

continually monitor these signals for snooping, this ﬂoat condition may cause excessive power draw by the

input receivers on the 603e. It is recommended that these signals be pulled up through weak (10 KOhms)

pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs

are—A[0–31], AP[0–3], TT[0–4], TBST, TSIZ[0–2], and GBL.

The data bus input receivers are normally turned off when no read operation is in progress and do not require

pull-up resistors on the data bus.

1.8.6 Thermal Management Information

This section provides thermal management information for the ceramic quad-ﬂat package (CQFP) and the

ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is

primarily dependent upon the system-level design—the heat sink, airﬂow and thermal interface material. To

reduce the die-junction temperature, heat sinks may be attached to the package by several methods—

adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly

(CBGA package); see Figure 14. This spring force should not exceed 5.5 pounds of force.

WB/C4-CQFP Package

CBGA Package

Heat Sink

Clip

Adhesive

or

Thermal Interface Material

Printed-Circuit Board

Option

Figure 14. Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the 603e. There are several

commercially-available heat sinks for the 603e provided by the following vendors:

Chip Coolers Inc.

800-227-0254 (USA/Canada)

401-739-7600

333 Strawberry Field Rd.

Warwick, RI 02887-6979

International Electronic Research Corporation (IERC)

135 W. Magnolia Blvd.

818-842-7277

Burbank, CA 91502

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Thermalloy

214-243-4321

2021 W. Valley View Lane

P.O. Box 810839

Dallas, TX 75731

Wakeﬁeld Engineering

60 Audubon Rd.

617-245-5900

603-528-3400

Wakeﬁeld, MA 01880

Aavid Engineering

One Kool Path

Laconia, NH 03247-0440

Ultimately, the ﬁnal selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

1.8.6.1 Internal Package Conduction Resistance

For this packaging technology the intrinsic thermal conduction resistance (shown in Table 3) versus the

external thermal resistance paths are shown in Figure 15 for a package with an attached heat sink mounted

to a printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Internal Resistance

Package/Leads

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance)

Figure 15. Package with Heat Sink Mounted to a Printed-Circuit Board

1.8.6.2 Adhesives and Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the

thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,

Figure 16 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,

graphite/oil, ﬂoroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increasing contact pressure.

The use of thermal grease signiﬁcantly reduces the interface thermal resistance. That is, the bare joint results

in a thermal resistance approximately 7 times greater than the thermal grease joint.

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Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see

Figure 14). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers

the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal

interface material depends on many factors—thermal performance requirements, manufacturability, service

temperature, dielectric properties, cost, etc.

Silicone Sheet (0.006 inch)

Bare Joint

Floroether Oil Sheet (0.007 inch)

2

Graphite/Oil Sheet (0.005 inch)

Synthetic Grease

1.5

1

0.5

0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

Contact Pressure (psi)

Figure 16. Thermal Performance of Select Thermal Interface Material

The board designer can choose between several types of thermal interface. Heat sink adhesive materials

should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment

shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive

materials provided by the following vendors:

Dow-Corning Corporation

Dow-Corning Electronic Materials

PO Box 0997

517-496-4000

Midland, MI 48686-0997

Chomerics, Inc.

617-935-4850

77 Dragon Court

Woburn, MA 01888-4850

28

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Thermagon Inc.

216-741-7659

3256 West 25th Street

Cleveland, OH 44109-1668

Loctite Corporation

860-571-5100

609-882-2332

1001 Trout Brook Crossing

Rocky Hill, CT 06067

AI Technology (e.g. EG7655)

1425 Lower Ferry Rd.

Trent, NJ 08618

The following section provides a heat sink selection example using one of the commercially available heat

sinks.

1.8.6.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (θ + θ + θ ) * P

d

j

a

r

jc

int

sa

Where:

T is the die-junction temperature

j

T is the inlet cabinet ambient temperature

a

T is the air temperature rise within the computer cabinet

r

θ is the junction-to-case thermal resistance

jc

θ

is the adhesive or interface material thermal resistance

int

θ is the heat sink base-to-ambient thermal resistance

sa

P is the power dissipated by the device

d

During operation the die-junction temperatures (T ) should be maintained less than the value speciﬁed in

j

Table 2. The temperature of the air cooling the component greatly depends upon the ambient inlet air

temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air

temperature (T ) may range from 30 to 40 °C. The air temperature rise within a cabinet (T ) may be in the

a

r

range of 5 to 10 °C. The thermal resistance of the thermal interface material (θ ) is typically about 1 °C/W.

int

Assuming a T of 30 °C, a T of 5 °C, a CQFP package θ = 2.2, and a power consumption (P ) of 4.5 watts,

a

r

jc

d

the following expression for T is obtained:

j

Die-junction temperature: T = 30 °C + 5 °C + (2.2 °C/W + 1.0 °C/W + R ) * 4.5 W

j

sa

For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (R ) versus airﬂow

sa

velocity is shown in Figure 17.

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8

7

6

5

4

3

2

1

Thermalloy #2328B Pin-fin Heat Sink

(25 x 28 x 15 mm)

0

0.5

1

1.5

2

2.5

3

3.5

Approach Airflow Velocity (m/s)

Figure 17. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity

Assuming an air velocity of 0.5 m/s, we have an effective R of 7 °C/W, thus

sa

T = 30°C + 5°C + (2.2 °C/W +1.0 °C/W + 7 °C/W) * 4.5 W,

j

resulting in a die-junction temperature of approximately 81 °C which is well within the maximum operating

temperature of the component.

Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakeﬁeld Engineering, and Aavid

Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air ﬂow.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common

ﬁgure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management

because no single parameter can adequately describe three-dimensional heat ﬂow. The ﬁnal die-junction

operating temperature, is not only a function of the component-level thermal resistance, but the system-level

design and its operating conditions. In addition to the component's power consumption, a number of factors

affect the ﬁnal operating die-junction temperature—airﬂow, board population (local heat ﬂux of adjacent

components), heat sink efﬁciency, heat sink attach, heat sink placement, next-level interconnect technology,

system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today's

microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and

conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for

the board, as well as, system-level designs. To expedite system-level thermal analysis, several “compact”

thermal-package models are available within FLOTHERM®. These are available upon request.

30

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1.9 Document Revision History

Table 13. Document Revision History

Document Revision

Substantive Change(s)

Rev 2

In Table 6, the minimun processor frequency for the 100 mhz and the 133 mhz parts was

changed to 50 mhz. The maximum VCO frequency was changed to 266.66 mhz on and

the minimum VCO frequency on the 133 mhz part was changed to 100 mhz.

In Table 12 the CPU and VCO frequencies were changed to correspond to the valid clock

speciﬁcations as shown in Table 6.

Table 2 includes notes on extended temperature parts.

1.10 Ordering Information

This section provides the part numbering nomenclature for the 603e. Note that the individual part numbers

correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola

or IBM sales ofﬁce.

1.10.1 Motorola Part Number Key

Figure 18 provides the Motorola part numbering nomenclature for the 603e. In addition to the processor

frequency, the part numbering scheme also consists of a part modiﬁer and application modiﬁer. The part

modiﬁer indicates any enhancement(s) in the part from the original production design. The bus divider may

specify special bus frequencies or application conditions. Each part number also contains a revision code.

This refers to the die mask revision number and is speciﬁed in the part numbering scheme for identiﬁcation

purposes only.

MPC 603 E XX XXX X X

Revision Level

(Contact Motorola Sales Office)

Product Code

Application Modifier

Part Identifier

(L = Full Spec, 0-105°C T )

j

(T = Ext. Temp.Spec, -40-105°C T )

j

Part Modifier

(E = Enhanced)

Max. Internal Processor Speed

Package

(FE = Wire-Bond CQFP,

RX = Ceramic Ball Grid Array)

Figure 18. Motorola Part Number Key

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Mfax and EC603e are trademarks of Motorola, Inc.

The PowerPC name, the PowerPC logotype, and PowerPC 603 are trademarks of International Business Machines Corporation used by Motorola under license

from International Business Machines Corporation.

FLOTHERM is a registered trademark of Flomerics Ltd., UK.

Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied

copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or

circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in

different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola

does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components

in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure

of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afﬁrmative Action Employer.

Motorola Literature Distribution Centers:

USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or 1-303-675-2140;

World Wide Web Address: http://ldc.nmd.com/

JAPAN: Nippon Motorola Ltd SPD, Strategic Planning Ofﬁce 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd Silicon Harbour Centre 2, Dai King Street Tai Po Industrial Estate Tai Po, New Territories, Hong Kong

Mfax™: RMFAX0@email.sps.mot.com; TOUCHTONE 1-602-244-6609; US & Canada ONLY (800) 774-1848;

World Wide Web Address: http://sps.motorola.com/mfax

INTERNET: http://motorola.com/sps

Technical Information: Motorola Inc. SPS Customer Support Center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com.

Document Comments: FAX (512) 895-2638, Attn: RISC Applications Engineering.

World Wide Web Addresses: http://www.motorola.com/PowerPC

http://www.motorola.com/netcomm

http://www.motorola.com/HPESD

MPC603EEC/D

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型号：	MPE603EFE100LX
厂家：	NXP
描述：	32-BIT, 100MHz, RISC PROCESSOR, CQFP240, 32 X 32 MM, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240 时钟外围集成电路
文件：	总32页 (文件大小：250K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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