MPF5023AVNA0ES_技术文档

PF5023

Power management integrated circuit (PMIC) for high

performance applications

Rev. 1 — 15 April 2020

Product data sheet

1 Overview

The PF5023 integrates multiple high performance buck regulators. It can operate as a

stand-alone point-of-load regulator IC, or as a companion chip to a larger PMIC.

Built-in one-time programmable (OTP) memory stores key startup configurations,

drastically reducing external components typically used to set output voltage and

sequence of regulators. Regulator parameters are adjustable through high-speed I²C

after start up offering flexibility for different system states.

2 Features

• Three high efficiency buck converters

• Watchdog timer/monitor

• Monitoring circuit to fit ASIL B safety level

• One-time programmable device configuration

• 3.4 MHz I²C communication interface

• 40-pin QFN package with wettable flank and exposed pad

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

3 Simplified application diagram

VIN

V1P5D

V1P5A

VPRE

SW1IN

SW1FB

SW1LX

SW2IN

SW3IN

SW2FB

SW2LX

SW3FB

SW3LX

VDDIO

PWRON

PF5023

VDDIO

STANDBY

3

ENx

WDI

VDDIO

PGOOD

SYNC

PGOODx

3

VDDIO

SDA

RESETBMCU

VDDIO

SCL

V1P5A

TBBEN

INTB

VDDOTP

XFAILB

AGND

EP

aaa--032234

Figure 1.ꢀSimplified application diagram

4 Ordering information

Table 1.ꢀOrdering information

Type number ^[1]

Package

Name

Description

Version

MPF5023AMBA0ES ^[2]

MPF5023AMMA0ES ^[3]

Plastic thermal enhanced very thin quad flat pack; no leads, wettable

flank, 40 terminals, 0.5 mm pitch, 6 mm x 6 mm x 0.85 mm body

Temperature grade: 125

℃

HVQFN40

SOT618-14

MPF5023AVNA0ES ^[4]

Plastic thermal enhanced very thin quad flat pack; no leads, wettable

flank, 40 terminals, 0.5 mm pitch, 6 mm x 6 mm x 0.85 mm body

Temperature grade: 105

℃

[1] To order parts in tape and reel, add the R2 suffix to the part number.

[2] Automotive part, Safety grade: ASIL B

[3] Automotive part, Safety grade: QM

[4] Industrial part

PF5023

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Product data sheet

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

5 Applications

• Automotive Infotainment

• High-end consumer and industrial

6 Internal block diagram

ABIST

PGOOD

SW1FB

MONITOR

SW1

VMON

MONITORING

BANDGAP

V

BG2

REF

SELEC.

WATCHDOG

TIMER

SW1IN

SW1LX

BANDGAP

COMPARATOR

V

BG2

EA

AND

DRIVER

SW1 DVS

AND MISC

REFERENCE

V

BG1

WD monitoring

V

BG1

REGULATION

BANDGAP

V1P5A

V1P5D

V1P5A

LDO

DIGITAL CORE

AND

STATE MACHINE

EPAD

V1P5D

LDO

ABIST

SW2FB

SW2

VMON

XFAILB

OTP MEMORY

REF

SELEC.

SW2IN

SW2LX

THERMAL MONITORING

/ SHUTDOWN

V

BG1

V

BG2

VIN

OVLO

EA

AND

V

SW2 DVS

AND MISC

BG1

DRIVER

REFERENCE

SW1VMON

SW2VMON

SW3VMON

SW1FB/2

EPAD

AGND

PGOOD

CONTROL

ABIST

SW3FB

SW3

VMON

CLOCK MANAGEMENT

(100 kHz / 20 MHz / PLL /

DIGITAL MODULE)

V

BG1

REF

SYNC

SELEC.

MANUAL TUNING

SPREAD SPECTRUM

EXTERNAL CLOCK

SYNC

SW3IN

SW3LX

V

BG2

EA

AND

SW3 DVS

AND MISC

V

BG1

DRIVER

REFERENCE

Digital Signal(s)

Analog Reference(s)

20 MHz Clock/Derivative

100 kHz Clock/Derivative

EPAD

aaa-032235

Figure 2.ꢀInternal block diagram

PF5023

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Product data sheet

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

7 Pinning information

7.1 Pinning

1

2

30

29

28

27

26

25

24

23

22

21

SW2FB

SW1IN

SW1LX

SW2LX

SW2IN

SW3IN

SW3LX

NC1

SCL

SDA

3

VDDOTP

SYNC

4

5

PGOOD

INTB

EPAD

6

7

V1P5D

V1P5A

STANDBY

XFAILB

8

9

NC2

10

NC3

aaa-032236

Figure 3.ꢀPin configuration for 40-pin QFN

7.2 Pin description

Table 2.ꢀPin description

QFN pin

number

Pin name

Pin description

Min

Max

Units

1

SW2FB

SW1IN

SW1LX

SW2LX

SW2IN

SW3IN

SW3LX

NC1

SW2 feedback input

SW1 input supply

SW1 switching node

SW2 switching node

SW2 input supply

SW3 input supply

SW3 switching node

not connected

−0.3

6.0

V

2

3

4

5

6

7

8

9

NC2

not connected

10

11

12

13

14

NC3

not connected

SW3FB

NC4

SW3 feedback input

not connected

EN3

SW3 enable input

not connected

NC5.

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

QFN pin

number

Pin name

Pin description

Min

Max

Units

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

NC6

not connected

−0.3

6.0

2.0

6.0

10

V

NC7

not connected

VIN

Main input voltage

AGND

PGOOD1

PGOOD2

XFAILB

STANDBY

V1P5A

V1P5D

INTB

Ground

SW1 PGOOD output

SW2 PGOOD output

XFAILB bidirectional IO

STANDBY input

1.6 V regulator output or internal analog

1.6 V regulator output or internal digital

Interrupt open-drain output

Global PGOOD output

External clock input/output for synchronization

Power supply for programming block

I²C SDA

PGOOD

SYNC

VDDOTP

SDA

6.0

0.3

SCL

I²C SCL

PWRON

PGOOD3

n.c.

PWRON input

SW3 PGOOD output

not connected

WDI

External watchdog reset input

TBBEN mode control input

TBBEN

VDDIO

RESETBMCU

EN1

I/O supply voltage. Connect to voltage rail at 1.8 V or 3.3 V −0.3

RESETBMCU open-drain output

SW1 enable input

−0.3

EN2

SW2 enable input

SW1FB

EPAD

SW1 feedback input

Exposed pad. Connect to ground

8 Absolute maximum ratings

Table 3.ꢀAbsolute maximum ratings

Symbol

Parameter

Min

Typ

—

Max

Unit

[1]

VIN

Main input supply voltage

Regulator input supply voltage

OTP programming input supply voltage

−0.3

6.0

10

V

SWxVIN

VDDOTP

—

[1] Pin reliability may be affected if system voltages are above the maximum operating range of 5.5 V for extended period of time. To minimize system

reliability impact, system must not operate above 5.5 V for more than 1800 sec over the lifetime of the device.

9 ESD ratings

Table 4.ꢀESD ratings

All ESD specifications are compliant with AEC-Q100 specification.

Symbol

Parameter

Min

Typ

Max

Unit

[1]

V_ESD

Human body model

—

2000

V

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Symbol

Parameter

Min

Typ

Max

Unit

[1]

V_ESD

Charge device model

All pins

V

—

500

100

I_LATCHUP

Latch-up current

mA

[1] ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),

robotic (CZAP = 4.0 pF).

10 Thermal characteristics

Table 5.ꢀThermal characteristics

Symbol

Parameter

Min

−40

—

Typ

—

Max

125

150

260

Unit

°C

T_A

Ambient operating temperature

Junction temperature

T_J

—

°C

T_ST

Storage temperature range

Peak package reflow temperature

—

°C

T_PPRT

—

°C

Table 6.ꢀQFN40 thermal resistance and package dissipation ratings

Symbol

Parameter

Typ

Unit

[1] [2] [3]

R_θJA

Junction to Ambient Thermal Resistance

JESD51-7, 2s2p

32.6

°C/W

[1] [2] [4]

[1] [2] [3]

[1] [2] [4]

R_θJA

Ψ_JT

Junction to Ambient Thermal Resistance

JESD51-7, 2s6p

26.8

0.46

0.39

°C/W

Junction to Top of Package Thermal Parameter

JESD51-7, 2s2p

Junction to Top of Package Thermal Parameter

JESD51-7, 2s6p

[1] Determined in accordance to JEDEC JESD51-2A natural convection environment and uniform power.

[2] Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment.

It is not meant to predict the performance of a package in an application-specific environment.

[3] Thermal test board meets JEDEC specification for this package (JESD51-7, 2s2p). PCB has a 3×3 array of thermal via under the exposed pad.

[4] 2s6p PCB identical to 51-7 but with four additional internal layers at 35 µm thickness.

11 Operating conditions

Table 7.ꢀOperating conditions

Symbol

Parameter

Min

Typ

Max

Unit

V_IN

Main input supply voltage

UVDET

—

5.5

V

12 General description

12.1 Features

The PF5023 is a power management integrated circuit (PMIC) designed to be the

primary power management building block for NXP high-end multimedia application

processors from the i.MX 8 and S32V series. It is also capable of providing power

solution to the high end i.MX 6 series as well as several non-NXP processors.

• Buck regulators

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

– SW1 to SW3: 0.4 V to 1.8 V; 2500 mA; 2 % accuracy

– Dynamic voltage scaling

– Configurable as a multiphase regulator

– VTT termination mode on SW2

– Programmable current limit

– Spread-spectrum and manual tuning of switching frequency

• PGOOD output and monitor

– Global PGOOD output and PGOOD monitor

– Independent PGOOD output for each regulator

• Independent enable input for each regulator

• Clock synchronization through configurable input/output sync pin

• System features

– Fast PMIC startup

– Advanced state machine for seamless processor interface

– High speed I²C interface support (up to 3.4 MHz)

– User programmable Standby and Off modes

– Programmable soft start sequence and power down sequence

– Programmable regulator configuration

• OTP (One-time programmable) memory for device configuration

• Monitoring circuit to fit ASIL B safety level

– Independent voltage monitoring with programmable fault protection

– Advance thermal monitoring and protection

– External watchdog monitoring and programmable internal watchdog counter

– I²C CRC and write protection mechanism

– Analog built-in self-test (ABIST)

12.2 Functional block diagram

PF5023

FUNCTIONAL BLOCK DIAGRAM

OTP

SW1 (SINGLE/MULTI)

(FLEXIBLE CONFIGURATION)

(0.4 V TO 1.8 V, 2.5 A)

LOGIC AND CONTROL

2

I C

WATCHDOG

MCU INTERFACE

REGULATOR CONTROL

FAULT DETECTION

FUNCTIONAL SAFETY

FAULT DETECTION AND

PROTECTION

(THERMAL/UV/OV/ILIM)

SW2 (SINGLE/MULTI)

(VTT/0.4 V TO 1.8 V, 2.5 A)

CLOCK MANAGEMENT

EXTERNAL CLOCK SYNC

SPREAD SPECTRUM

SW3 (SINGLE/MULTI)

(0.4 V TO 1.8 V, 2.5 A)

MANUAL FREQUENCY TUNING

aaa-032237

Figure 4.ꢀFunctional block diagram

12.3 Power tree summary

The following table provides a summary of the voltage regulators in the PF5023.

PF5023

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Product data sheet

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Table 8.ꢀVoltage supply summary

Regulator

Type

Input supply

Regulated output

range (V)

VOUT

programmable step

(mV)

IRATED (mA)

SW1

SW2

SW3

Buck

SW1IN

SW2IN

SW3IN

0.4 V to 1.8 V

6.25

2500

VTT/0.4 V to 1.8 V

0.4 V to 1.8 V

12.4 Device differences

Table 9.ꢀDevice differences

Description

PF5023 non-safety PF5023 ASIL B

Bits not available on PF5023 non-

safety

During the self-test, the device checks:

Not available

Available

AB_SWx_OV

AB_SWx_UV

STEST_NOK

AB_RUN

• The high speed oscillator circuit is operating within

a maximum of 15 % tolerance

• A CRC is performed on the mirror registers during

the self-test routine to ensure the integrity of the

registers before powering up

• The output of both the voltage generation bandgap

and the monitoring bandgap are not more than 5 %

to 12 % apart from each other

• ABIST test on all voltage monitors and toggling

signals

Fail-safe state: to lock down the system in case of

critical failures cycling the PMIC ON/OFF.

Not available

Available

FS_CNT[3:0]

OTP_FS_BYPASS

OTP_FS_MAX_CNT[3:0]

OTP_FS_OK_TIMER[2:0]

Secure I²C write: I²C write procedure to modify

registers dedicated to safety features (I²C CRC is still

available).

I2C_SECURE_EN

OTP_I2C_SECURE _EN (always 0)

RANDOM_GEN[7:0]

RANDOM_CHK[7:0]

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

13 State machine

The PF5023 features a state of the art state machine for seamless processor interface.

The state machine handles the IC start up, provides fault monitoring and reporting, and

protects the IC and the system during fault conditions.

NO

POWER

Legend

VIN < UVDET

PF502x ASILB only

CRITICAL FAILURE

Regulators off

PF502x QM only

VIN > UVDET

V1P5D_POR

Fail-Safe

State

FS_CNT = FS_MAX_CNT

&& OTP_FS_BYPASS = 0

P

1. FS_CNT < FS_MAX_CNT

OR

OTP &

Trim Load

2. OTP_FS_BYPASS = 1

Fail-Safe

Transition

U

FS_CNT++

Regulators off

R

LP_Off

J

BG_OK

OTP_OK

20 MHz_OK

Self-

Test

F

K

Fail self-test

(ST_COUNT < 3)

QPU_Off

2 ms

delay

L

Off Modes

TRIM_NOK = 0

&& OTP_NOK = 0

&& STEST_NOK = 0

System ON

O

Power up regulators

per OTP sequence

RESETBMCU = HIGH

Sys ON

Sequence

Power Up

Sequence

M

D

WD_Reset

E

PU_FAIL = True

B

A

Power up

failure

C WD Reset Event

WD_FAIL_CNT++

RUN

Standby

Q

Turn-Off

POWER DOWN

Z

Fault

1. PWRON = 0

OR

Fault

POWER DOWN

S

2. PWRON H to L &&

PWRON = 0 > TRESET

OR

3. PMIC_OFF = 1 &&

500 µs_Shutdown_timer_expired

OR

1. WD_FAIL_CNT = WD_MAX_CNT

N

Turn-off

OR

2. PU_FAIL = True

OR

Power Down

3. FAULT_CNT = FAULT_MAX_CNT

4. VIN_OVLO_SDWN = 1 &&

VIN_OVLO detected

OR

4. Fault_Timer_Expired

OR

5. Tj > TSD

aaa-030044

Figure 5.ꢀState diagram

Table 10 lists the conditions for the different state machine transitions.

PF5023

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Product data sheet

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Table 10.ꢀState machine transition definition

Symbol

Description

Conditions

1. (STANDBY = 0 && STANDBYINV bit = 0)

2. (STANDBY = 1 && STANDBYINV bit = 1)

1. (STANDBY = 1 && STANDBYINV bit = 0)

2. (STANDBY = 0 && STANDBYINV bit = 1)

1. Hard WD Reset event

Transition A

Standby to run

Transition B

Run to standby

Transition C

Transition D

Transition E

System ON to WD reset

WD reset to system ON

1. 30 µs delay passed && WD_EVENT_CNT < WD_MAX_CNT

1. WD_EVENT_CNT = WD_MAX_CNT

WD reset to power down (fault)

Transitory off state: device pass through LP_Off to self-test to QPU_

Off (no power up event present)

1. LPM_OFF = 1 && TBBEN = Low

Power up event from LP_Off state

2. LPM_OFF = 0

&& TBBEN = Low

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET< VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0

LP_Off to self-test (PF5023 ASIL B

only)

Transition J

Transition K

Transition F

Power up event from LP_Off state

3. LPM_OFF = 0

&& TBBEN = Low

&& (PWRON H to L && OTP_PWRON_MODE = 1

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0

Conditions: Transitory OFF state to go into TBB mode. Device pass

through LP_Off to self-test to QPU_Off (no power up event present)

4. TBBEN = high (V1P5D)

1. Pass self-tests

Self-test to QPU_Off (PF5023 ASIL B

only)

2. TBBEN = high (V1P5D)

Transitory OFF state: device pass through LP_Off to QPU_Off (no

power up event present)

1. LPM_OFF = 1

&& TBBEN = Low

Power up event from LP_Off state

2. LPM_OFF = 0

&& TBBEN = Low

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET< VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

LP_Off to QPU_Off (PF5023 QM only)

&& TRIM_NOK = 0 && OTP_NOK = 0

Power up event from LP_Off state

3. LPM_OFF =0

&& TBBEN = Low

&& (PWRON H to L && OTP_PWRON_MODE = 1)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD&& TRIM_NOK = 0 && OTP_NOK = 0

Transitory OFF state: device pass through LP_Off to QPU_Off (no

power up event present)

4. TBBEN = High (V1P5D)

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Symbol

Description

Conditions

Transitory QPU_Off state, power on event occurs from LP_Off

state, after self-test is passed, QPU_Off is just a transitory state until

power up sequence starts.

1. LPM_OFF = 0

&& TBBEN = Low

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

2. LPM_OFF = 1

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

3. LPM_OFF = 1

&& (PWRON H to L && OTP_PWRON_MODE = 1)

Transition L

QPU_Off to power up

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

4. TBBEN = High

&& (PWRON = 1 && OTP_PWRON_MODE = 0)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Power up event from QPU_Off state

5. TBBEN = High

&& (PWRON H to L && OTP_PWRON_MODE = 1)

&& UVDET < VIN < VIN_OVLO (or VIN_OVLO disabled)

&& Tj < TSD

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK=0

Transition M

Transition N

Power up sequence to system ON

1. RESETBMCU is released as part of the power up sequence

Requested turn off event

1. OTP_PWRON_MODE = 0 && PWRON = 0

Requested turn off event

2. OTP_PWRON_MODE = 1 && (PWRON H to L && PWRON = low

for t > TRESET)

System ON to power down (turn off)

Requested turn off event

3. PMIC_OFF = 1 && 500µs_Shutdown_Timer_Expired

Protective turn off event (no PMIC fault)

4. VIN_OVLO_SDWN=1 && VIN_OVLO detected for longer than

VIN_OVLO_DBNC time

Turn off event due to PMIC fault

1. Fault Timer expired

Turn off event due to PMIC fault

Transition Z

System ON to power down (fault)

2. FAULT_CNT = FAULT_MAX_CNT

Turn off event due to PMIC fault

3. Thermal shutdown Tj > TSD

Transition O

Transition Q

Power down (turn off) to LP_Off

Power up to power down (fault)

Requested turn off event moves directly to LP_Off

1. Power down sequences finished

Power up failure

1. Failure during power up sequence

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Symbol

Description

Self-test to fail-safe transition

Conditions

Transition R

1. Self-tests fail 3 times

&& TBBEN = low

Transition S

Power down (fault) to fail-safe transition Turn off event due to a fault condition moves to fail-safe transition

1. Power down sequence is finished

1. FS_CNT < FS_MAX_CNT

Fail-safe transition to LP_Off

Transition U

Transition P

2. OTP_FS_BYPASS = 1

Fail-safe transition to fail-safe state

1. FS_CNT = FS_MAX_CNT

&& OTP_FS_BYPASS = 0

(PF5023 ASIL B only)

13.1 State descriptions

13.1.1 OTP/TRIM load

Upon VIN application, the V1P5D and V1P5A regulators are turned on automatically.

Once the V1P5D and V1P5A cross their respective POR thresholds, the fuses (for trim

and OTP) are loaded into the mirror registers and into the functional I²C registers if

configured by the voltage on the VDDOTP pin.

The fuse circuits have a CRC error check routine which reports and protects against

register loading errors on the mirror registers. If a register loading error is detected, the

corresponding TRIM_NOK or OTP_NOK flag is asserted. See Section 17 "OTP/TBB and

hardwire default configurations" for details on handling fuse load errors.

If no fuse load errors are present, the state machine moves to the LP_off state.

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during the

system On mode. By default, the LPM_OFF = 0 when VIN crosses the UVDET threshold,

therefore the state machine stops at the LP_Off state until a valid power up event

is present. When LPM_OFF = 1, the state machine transitions automatically to the

QPU_Off state if no power up event has been present and waits in the QPU_Off until a

valid power up event is present.

The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current

(stay in the LP_Off state) or quick power up (move to the QPU_Off state).

If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error

is detected, the PF5023 ignores the power up event and remains in the LP_Off state to

avoid any potential damage to the system.

13.1.3 Self-test routine (PF5023 ASIL B only)

When the device transitions from the LP_Off state, it turns on all necessary internal

circuits as it moves into the self-test routine and performs a self-check routine to verify

the integrity of the internal circuits.

During the self-test routine the following blocks are verified:

• The high speed clock circuit is operating within a maximum of 15 % tolerance

• The output of both the voltage generation bandgap and the monitoring bandgap are not

more than 5 % to 12 % apart from each other

PF5023

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Product data sheet

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

• A CRC is performed on the mirror registers during the self-test routine, to ensure the

integrity of the registers before powering up

• ABIST test on all voltage monitors.

To allow for varying settling times for the internal bandgap and clocks, the self-test block

is executed up to three times (with 2.0 ms between each test) if a failure is encountered,

the state machine proceeds to the fail-safe transition.

A failure in the ABIST test is not interpreted as a self-test failure and it only sets the

corresponding ABIST flag for system information. The MCU is responsible for reading the

information and deciding whether it can continue with a safe operation. See Section 18.1

"System safety strategy" for the functional safety strategy of PF5023.

Upon a successful self-test, the state machine proceeds to the QPU_Off state.

13.1.4 QPU_Off state

The QPU_Off state is a higher power consumption Off mode, in which all internal circuitry

required for a power on is biased and ready to start a power up sequence.

If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state,

and waits until a valid turn on event is present.

In this state, if VDDIO supply is provided externally, the device is able to communicate

through I²C to access and modify the mirror registers in order to operate the device in

TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and

hardwire default configurations".

If a power up event is started and any of the TRIM_NOK, OTP_NOK or STEST_NOK

flags are asserted, the device ignores the power up event and remains in the QPU_Off

state. See Section 17 "OTP/TBB and hardwire default configurations" for debugging a

fuse loading failure.

Upon a power up event, the default configuration from OTP or hardwire is loaded into

their corresponding I²C functional register in the transition from QPU_Off to power up

state.

13.1.5 Power up sequence

During the power up sequence, the external regulators are turned on in a predefined

order as programmed by the default (OTP or hardwire) sequence.

The RESETBMCU is also programmed as part of the power up sequence, and it is used

as the condition to enter the system On state. The RESETBMCU may be released in the

middle of the power up sequence, in this case, the remaining supplies in the power up

continues to power up as the device is in the run state. See Section 14.5.2 "Power up

sequencing" for details.

13.1.6 System On state

During the system On state, the MCU is powered and out of reset and the system is fully

operational.

The system On is a virtual state composed by two modes of operations:

• Run state

• Standby state

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Register to control the regulators output voltage, regulator enable, interrupt masks, and

other miscellaneous functions can be written to or read from the functional I²C register

map during the system On state.

13.1.6.1 Run state

If the power up state is successfully completed, the state machine transitions to the run

state. In this state, RESETBMCU is released high, and the MCU is expected to boot up

and set up specific registers on the PMIC as required during the system boot up process.

The Run mode is intended to be used as the normal mode of operation for the system.

Each regulator has specific registers to control its output voltage, operation mode and/or

enable/disable state during the run state.

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_RUN_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNC_MODE = 1, default SWx_RUN_MODE at power up is always set to

PWM (0b01)

• When OTP_SYNC_MODE = 0 and OTP_SYNCOUT_EN = 1, default

SWx_RUN_MODE at power up is always set to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_RUN_MODE at power up shall always set to

PWM (0b01)

• If none of the above conditions are met, the default value of the SWx_RUN_MODE bits

at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_RUN_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_RUN_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_RUN_MODE[1:0] bits are loaded with 0b00 (Off mode).

In a typical system, each time the processor boots up (PMIC transitions from Off mode

to run state), all output voltage configurations are reset to the default OTP configuration,

and the MCU should configure the PMIC to its desired usage in the application.

13.1.6.2 Standby state

The standby state is intended to be used as a low power (state retention) mode of

operation. In this state, the voltage regulators can be preset to a specific low power

configuration in order to reduce the power consumption during system’s sleep or state

retention modes of operations.

The standby state is entered when the STANDBY pin is pulled high or low as defined

by the STANBYINV bit. The STANDBY pin is pulled high/low by the MCU to enter/exit

system low power mode. See Section 14.9.2 "STANDBY" for detailed configuration of the

STANDBY pin.

Each regulator has specific registers to control its output voltage, operation mode and/or

enable/disable state during the standby state.

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_STBY_MODE[1:0] bits will be loaded as needed by the system:

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• When OTP_SYNC_MODE = 1, default SWx_STBY_MODE at power up is always set

to PWM (0b01)

• When OTP_SYNC_MODE = 0 and OTP_SYNCOUT_EN = 1, default

SWx_STBY_MODE at power up is always set to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_STBY_MODE at power up shall always set to

PWM (0b01)

• If none of the above conditions are met, the default value of the SWx_STBY_MODE

bits at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_STBY_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_STBY_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_STBY_MODE[1:0] bits are loaded with 0b00 (Off mode).

Upon power up, the standby registers are loaded with the same default OTP values as

the run mode. The MCU is expected to program the desired standby values during boot

up.

If any of the external regulators are disabled in the standby state, the power down

sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.7 WD_Reset

When a hard watchdog reset is present, the state machine increments the

WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register.

If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic

watchdog failure, it powers down the external regulators and proceeds to the fail-safe

transition.

If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD

reset.

A hard WD reset can be generated from either a transition in the WDI pin or a WD event

initiated by the internal watchdog counter as described in Section 15.7.2 "Watchdog reset

behaviors".

13.1.8 Power down state

Two types of events may lead to the power down sequence:

• Non faulty turn off events: move directly into LP_Off state as soon as power down

sequence is finalized.

• Turn off events due to a PMIC fault: move to the fail-safe transition as soon as the

power down sequence is finalized.

13.1.9 Fail-safe transition

The fail-safe transition is entered if the PF5023 initiates a turn off event due to a PMIC

fault.

If the fail-safe transition is entered, the PF5023 provides four FAIL bits to indicate the

source of the failure:

• The PU_FAIL is set to 1 when the device shuts down due to a power up failure

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• The WD_FAIL is set to 1 when the device shuts down due to a watchdog event counter

max out

• The REG_FAIL is set to 1 when the device shuts down due to a regulator failure (fault

counter maxed out or fault timer expired)

• The TSD_FAIL is set to 1 when the device shuts down due to a thermal shutdown

The value of the FAIL bits is retained as long as VIN > UVDET.

The MCU can read the FAIL bits during the system On state in order to obtain

information about the previous failure and can clear them by writing a 1 to them, provided

the state machine is able to power up successfully after such failure.

In the PF5023, when the state machine enters the fail-safe transition, a fail-safe counter

is compared and increased, if the FS_CNT[3:0] reaches the maximum count, the device

can be programmed to move directly to the fail-safe state to prevent a cyclic failure from

happening.

13.1.10 Fail-safe state (PF5023 ASIL B only)

The fail-safe state works as a safety lock-down upon a critical device/system failure. It is

reached when the FS_CNT [3:0] = FS_MAX_CNT [3:0].

A bit is provided to enable or disable the device to enter the fail-safe state upon a cyclic

failure. When the OTP_FS_BYPASS = 1, the fail-safe bypass operation is enabled and

the device always move to the LP_Off state, regardless of the value of the FS_CNT[3:0].

If the OTP_FS_BYPASS = 0, the fail-safe bypass is disabled, and the device moves to

the fail-safe state when the proper condition is met.

The maximum number of times the device can pass through the fail-safe

transition continuously prior to moving to a fail state is programmed by the

OTP_FS_MAX_CNT[3:0] bits. If the FS_MAX_CNT[3:0] = 0x00, the device moves into

the fail-safe state as soon as it fails for the very first time.

The device can exit the fail-safe state only after a power cycle (VIN crossing UVDET)

event is present.

To avoid reaching the fail-safe state due to isolated fail-safe transition events,

the FS_CNT [3:0] is gradually decreased based on a fail-safe OK timer. The

OTP_FS_OK_TIME[2:0] bits select the default time configuration for the fail-safe OK

timer between 1 to 60 min.

Table 11.ꢀFail-safe OK timer configuration

OTP_FS_OK_TIME[2:0]

FS_CNT decrease period (min)

000

001

010

011

100

101

110

111

1

5

10

15

20

30

45

60

When the fail-safe OK timer reaches the configured time during the system On state, the

state machine decreases the FS_CNT[3:0] bits by one and starts a new count until the

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FS_CNT[3:0] is 0x00. The FS_CNT[3:0] may be manually cleared during the System On

state if the system wants to control this counter manually.

14 General device operation

14.1 UVDET

UVDET works as the main operation threshold for the PF5023. Crossing UVDET on the

rising edge is a mandatory condition for OTP fuses to be loaded into the mirror registers

and allows the main PF5023 operation.

If VIN is below the UVDET threshold, the device remains in an unpowered state. A

200 mV hysteresis is implemented on the UVDET comparator to set the falling threshold.

Table 12.ꢀUVDET threshold

Symbol

UVDET

Parameter

Min

2.7

2.5

Typ

2.8

2.6

Max

2.9

Unit

V

Rising UVDET

Falling UVDET

2.7

V

14.2 VIN OVLO condition

The VIN_OVLO circuit monitors the main input supply of the PF5023. When this block is

enabled, the PF5023 monitors its input voltage and can be programmed to react to an

overvoltage in two ways:

• When the VIN_OVLO_SDWN = 0, the VIN_OVLO event triggers an OVLO interrupt but

does not turn off the device

• When the VIN_OVLO_SDWN = 1, the VIN_OVLO event initiates a power down

sequence

When the VIN_OVLO_EN = 0, the OVLO monitor is disabled and when the

VIN_OVLO_EN = 1, the OVLO monitor is enabled. The default configuration of the

VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit in OTP. Likewise, the default

value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon power

up.

During a power up transition, if the OTP_VIN_OVLO_SDWN = 0 the device allows the

external regulators to come up and the PF5023 announces the VIN_OVLO condition

through an interrupt. If the OTP_VIN_OVLO_SDWN = 1, the device stops the power up

sequence and returns to the corresponding Off mode.

Debounce on the VIN_OVLO comparator is programmable to 10 µs, 100 µs or 1.0 ms, by

the VIN_OVLO_DBNC[1:0] bits. The default value for the VIN_OVLO debounce is set by

the OTP_VIN_OVLO_DBNC[1:0] bits upon power up.

Table 13.ꢀVIN_OVLO debounce configuration

VIN_OVLO_DBNC[1:0]

VIN OVLO debounce value (µs)

00

01

10

11

10

100

1000

Reserved

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Table 14.ꢀVIN_OVLO specifications

Symbol

Parameter

Min

5.6

—

Typ

5.8

—

Max

6.0

Unit

V

[1]

VIN_OVLO

VIN_OVLO_HYS

VIN overvoltage lockout rising

VIN overvoltage lockout hysteresis

200

mV

[1] Operating the device above the maximum VIN = 5.5 V for extended period of time may degrade and cause permanent

damage to the device.

14.3 IC startup timing with PWRON pulled up

The PF5023 features a fast internal core power up sequence to fulfill system power

up timings of 5.0 ms or less, from power application until MCU is out of reset. Such

requirement needs a maximum ramp up time of 1.5 ms for VIN to cross the UVDET

threshold in the rising edge.

A maximum core biasing time of 1.5 ms from VIN crossing to UVDET until the beginning

of the power up sequence is ensured to allow up to 1.5 ms time frame for the voltage

regulators power up sequence.

Timing for the external regulators to start up is programmed by default in the OTP fuses.

The 5.0 ms power up timing requirement is only applicable when the PWRON pin

operates in level sensitive mode OTP_PWRON_MODE = 0, however turn on timing is

expected to be the same for both level or edge sensitive modes after the power on event

is present.

t

vin_rise

UVDET

VIN

1.6 V

V1P5D

t

stest_done

PWRON

t

first

STEST done

(internal signal)

Regulator Outputs

(enable signals)

t

reg2reset

RESETBMCU

Fuse

Load

Self

Test

aaa-030045

Figure 6.ꢀStartup with PWRON pulled up

Table 15.ꢀStartup timing requirements (PWRON pulled up)

Symbol

Parameter

Min

Typ

Max

Unit

t_{vin_rise}

Rise time of VIN from VPWR application to UVDET

(system dependent)

10

—

1500

µs

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Symbol

Parameter

Min

Typ

Max

Unit

t_{stest_done}

Time from VIN crossing UVDET to fist slot of power up

sequence

—

1.5

ms

14.4 IC startup timing with PWRON pulled low during VIN application

It is possible that PWRON is held low when VIN is applied. By default, LPM_OFF bit

is reset to 0 upon crossing UVDET, therefore the PF5023 remains in the LP_Off state

as described in Section 13.1.2 "LP_Off state". In this scenario, the quiescent current in

the LP_Off state is kept to a minimum. When PWRON goes high with LPM_OFF = 0,

the PMIC startup is expected to take longer, since it has to enable most of the internal

circuits and perform the self-test before starting a power up sequence.

Figure 7 shows startup timing with LPM_OFF = 0.

t

vin_rise

UVDET

1.6 V

VIN

V1P5D

PWRON

t

pwrup_lpm

t

fuseLoad

Fuse load OK

(internal signal)

t

first

STEST done

(internal signal)

Regulator Outputs

RESETBMCU

t

reg2reset

Fuse

Load

Self-Test

LP_OFF State

aaa-030046

Figure 7.ꢀStartup with PWRON driven high externally and bit LPM_OFF = 0

Table 16.ꢀStartup with PWRON driven high externally and LPM_OFF = 0

Symbol

Parameter

Min

Typ

Max

Unit

t_{vin_rise}

Rise time of VIN from VPWR application to UVDET

(system dependent)

10

—

1500

µs

t_fuseload

Time from VIN crossing UVDET to Fuse_Load_done

(fuse loaded correctly)

—

600

800

t_{pwrup_lpm}

Time from PWRON going high to the first slot of the

power up sequence

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14.5 Power up

14.5.1 Power up events

Upon a power cycle (VIN > UVDET), the LPM_OFF bit is reset to 0, therefore the device

moves to the LP_Off state by default. The actual value of the LPM_OFF bit can be

changed during the Run mode and is maintained until VIN crosses the UVDET threshold.

In either one of the Off modes, the PF5023 can be enabled by the following power up

events:

1. When OTP_PWRON_MODE = 0, PWRON pin is pulled high.

2. When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition

and remains low for as long as the PWRON_DBNC timer.

A power up event is valid only if:

• VIN > UVDET

• VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)

• Tj < thermal shutdown threshold

• TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

14.5.2 Power up sequencing

The power up sequencer controls the time and order in which the voltage regulators and

other controlling I/O are enabled when going from the Off mode into the run state.

The OTP_SEQ_TBASE[1:0] bits set the default time base for the power up and power

down sequencer.

The SEQ_TBASE[1:0] bits can be modified during the system On state in order to

change the sequencer timing during run/standby transitions as well as the power down

sequence.

Table 17.ꢀPower up time base register

OTP bits

Functional bits

Sequencer time base

(µs)

OTP_SEQ_TBASE[1:0]

SEQ_TBASE[1:0]

00

01

10

11

00

01

10

11

30

120

250

500

The power up sequence may include any of the following:

• Switching regulators

• PGOOD pin if programmed as a GPO

• RESETBMCU

The default sequence slot for each one of these signals is programmed via the OTP

configuration registers. They can be modified in the functional I²C register map to change

the order in which the sequencer behaves during the run/standby transitions as well as

the power down sequence.

The x_SEQ[7:0] bits set the regulator/pin sequence from 0 to 254. Sequence code 0x00

indicates that the particular output is not part of the startup sequence and remains in OFF

(in case of a regulator) or remains low/disabled (in case PGOOD pin used as a GPO).

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Table 18.ꢀPower up sequence registers

OTP bits

Functional bits

Sequence slot

Startup time

(µs)

OTP_SWx_SEQ[7:0]/

OTP_PGOOD_SEQ[7:0]/

OTP_RESETBMCU_SEQ[7:0]

SWx_SEQ[7:0]/

PGOOD_SEQ[7:0]/

RESETBMCU_SEQ[7:0]

00000000

00000001

00000000

00000001

Off

0

Off

SLOT0

(right after PWRON event is

valid)

00000010

1

SEQ_TBASE x SLOT1

.

11111111

254

SEQ_TBASE x SLOT254

If RESETBMCU is not programmed in the OTP sequence, it will be enabled by default

after the last regulator programmed in the power up sequence.

When the _SEQ[7:0] bits of all regulators and PGOOD used as a GPIO are set to 0x00

(OFF) and a power on event is present, the device moves to the run state in slave mode.

In this mode, the device is enabled without any voltage regulator or GPO enabled. If the

RESETBMCU is not programed in a power up sequence slot, it is released when the

device enters the run state.

The slave mode is a special case of the power up sequence to address the scenario

where the PF5023 is working as a slave PMIC, and supplies are meant to be enabled

by the MCU during the system operation. In this scenario, if RESETBMCU is used, it is

connected to the master RESETBMCU pin.

Figure 8 provides an example of the power up/down sequence coming from the Off

modes.

SW1

SW3

RESETBMCU

SW2

System On

INTB

Power up Seq.

Off to Run

Power down Seq.

Run to Off

End of

Start of

End of

PWRUP

PWRDN

aaa-032747

Figure 8.ꢀPower up/down sequence between Off and system On state

When transitioning from Standby mode to Run mode, the power up sequencer is

activated only if any of the external regulators is re-enabled during this transition. If none

of the regulators toggle from Off to On and only voltage changes are being performed

when entering or exiting Standby mode, the changes for the voltage regulators are made

simultaneously rather than going through the power up sequencer.

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Figure 9 shows an example of the power up/down sequence when transitioning between

Run and Standby modes.

SW1

SW2

SW3

RESETBMCU

INTB

Run Mode PWRDN Sequence

from Run to STBY

STBY Mode

PWRUP Sequence

from STBY to Run

PWRDN_l

PWRUP_l

aaa-032745

Figure 9.ꢀPower up/down sequence between run and standby

The PWRUP_I interrupt is set while transitioning from standby to run, even if the

sequencer is not used. This is used to indicate that the transition is complete and device

is ready to perform proper operation.

14.6 Power down

14.6.1 Turn off events

Turn off events may be requested by the MCU (non-PMIC fault related) or due to a

critical failure of the PMIC (hard fault condition).

The following are considered non-PMIC failure turn off events:

1. When OTP_PWRON_MODE = 0, the device starts a power down sequence when the

PWRON pin is pulled low.

2. When OTP_PWRON_MODE = 1, the device starts a power down sequence when

the PWRON pin sees a transition from high to low and remains low for longer than

TRESET.

3. When bit PMIC_OFF is set to 1, the device starts a 500 µs shutdown timer. When

the shutdown timer is started, the PF5023 sets the SDWN_I interrupt and asserts

the INTB pin provided it is not masked. At this point, the MCU can read the interrupt

and decide whether to continue with the turn off event or stop it in case it was sent by

mistake.

If the SDWN_I bit is cleared before the 500 µs shutdown timer is expired, the

shutdown request is canceled and the shutdown timer is reset; otherwise, if the

shutdown timer is expired, the PF5023 starts a power down sequence.

The PMIC_OFF bit self-clears after SDWN_I flag is cleared.

4. When VIN_OVLO_EN = 1 and VIN_OVLO_SDWN = 1, and a VIN_OVLO event is

present.

Turn off events due to a hard fault condition:

1. If an OV, UV or ILIM condition is present long enough for the fault timer to expire.

2. In the event that an OV, UV or ILIM condition appears and clears cyclically, and the

FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0].

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3. If the watchdog fail counter is overflown, that is WD_EVENT_CNT = WD_MAX_CNT.

4. When Tj crosses the thermal shutdown threshold as the temperature rises.

When the PF5023 experiences a turn off event due to a hard fault condition, the device

pass through the fail-safe transition after regulators have been powered down.

14.6.2 Power down sequencing

During a power down sequence, output voltage regulators can be turned off in two

different modes as defined by the PWRDWN_MODE bit.

1. When PWRDWN_MODE = 0, the regulators power down in sequential mode.

2. When PWRDWN_MODE = 1, the regulators power down by groups.

During transition from run to standby, the power down sequencer is activated in the

corresponding mode, if any of the external regulators are turned off in the standby

configuration. If external regulators are not turned off during this transition, the power

down sequencer is bypassed and the transition happens at once (any associated DVS

transitions could still take time).

The PWRDN_I interrupt is set at the end of the transition from run to standby when the

last regulator has reached its final state, even if external regulators are not turned off

during this transition.

14.6.2.1 Sequential power down

When the device is set to the sequential power down, it uses the same _SEQ[7:0]

registers as the power up sequence to power down in reverse order.

All regulators with the _SEQ[7:0] bits set to 0x00, power down immediately and the

remaining regulators power down one OTP_SEQ_TBASE[1:0] delay after, in reverse

order as defined in the _SEQ[7:0] bits.

If PGOOD pin is used as a GPO, it is de-asserted as part of the power down sequence

as indicated by the PGOOD_SEQ[7:0] bits.

If the MCU requires a different power down sequence, it can change the values of the

SEQ_TBASE[1:0] and the _SEQ[7:0] bits during the system On state.

When the state machine passes through any of the Off modes, the contents of the

SEQ_TBASE[1:0] and _SEQ[7:0] bits are reloaded with the corresponding mirror register

(OTP) values before it starts the next power up sequence.

14.6.2.2 Group power down

When the device is configured to power down in groups, the regulators are assigned to a

specific power down group. All regulators assigned to the same group are disabled at the

same time when the corresponding group is due to be disabled.

Power down groups shut down in decreasing order starting from the lowest hierarchy

group with a regulator shutting down (for instance Group 4 being the lowest hierarchy

and Group 1 the highest hierarchy group). If no regulators are set to the lowest hierarchy

group, the power down sequence timer starts off the next available group that contains a

regulator to power down.

Each regulator has its own _PDGRP[1:0] bits to set the power down group it belongs to

as shown in Table 19.

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PF5023

Power management integrated circuit (PMIC) for high performance applications

Table 19.ꢀPower down regulator group bits

OTP_SWx_PDGRP[1:0]

SWx_PDGRP[1:0]

Description

OTP_PGOOD_PDGRP[1:0]

PGOOD_PDGRP[1:0]

OTP_RESETBMCU_PDGRP[1:0] RESETBMCU_PDGRP[1:0]

00

01

10

11

00

01

10

11

Regulator belongs to Group 4

Regulator belongs to Group 3

Regulator belongs to Group 2

Regulator belongs to Group 1

If PGOOD pin is used as a GPO, the PGOOD_PDGRP[1:0] is used to turn off the

PGOOD pin in a specific group during the power down sequence. If PGOOD pin is used

in power good mode, it is recommended that the OTP_PGOOD_PDGRP bits are set

to 11 to ensure the group power down sequencer does not detect these bits as part of

Group 4.

Each one of power down groups have programmable time delay registers to set the time

delay after the regulators in this group have been turned off, and the next group can start

to power down.

Table 20.ꢀPower down counter delay

OTP bits

Functional bits

GRPx_DLY[1:0]

Power down delay

(µs)

OTP_GRPx_DLY[1:0]

00

01

10

11

00

01

10

11

120

250

500

1000

If RESETBMCU is required to be asserted first before any of the external regulators from

the corresponding group, the RESETBMCU_DLY provides a selectable delay to disable

the regulators after RESETBMCU is asserted.

Table 21.ꢀProgrammable delay after RESETBMCU is asserted

OTP bits

Functional bits

RESETBMCU delay

(µs)

OTP_RESETBMCU_DLY[1:0]

RESETBMCU_DLY[1:0]

00

01

10

11

00

01

10

11

No delay

10

100

500

If RESETBMCU_DLY is set to 0x00, all regulators in the same power down group as

RESETBMCU is disabled at the same time RESETBMCU is asserted.

Figure 10 shows an example of the power down sequence when PWRDWN_MODE = 1.

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PDWN_GRP1

GPR1_DLY = 120 µs

SW1

PDWN_GRP2

GPR2_DLY = 120 µs

SW2

PDWN_GRP3

GPR3_DLY = 120 µs

SW3

PDWN_GRP4

NA

RESETBMCU_DLY = 10 µS

PWRON

SW3

SW2

RESETBMCU

SW1

120 µs

GRP3_DLY

120 µs

GRP2_DLY

10 µs

120 µs

GRP1_DLY

aaa-034856

Figure 10.ꢀGroup power down sequence example

14.6.2.3 Power down delay

After a power down sequence is started, the PWRON pin shall be masked until the

sequence is finished and the programmable power down delay is reached. The device

can power up again if a power up event is present. The power down delay time can be

programmed on an OTP via the OTP_PD_SEQ_DLY[1:0] bits.

Table 22.ꢀPower down delay selection

OTP_PD_SEQ_DLY[1:0]

Delay after power down sequence

00

01

10

11

No delay

1.5 ms

5.0 ms

10 ms

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Power Down Delay

System On

State

Power Down

Sequence

OFF State

Shutdown

Event

PWRON

Regulator

Outputs

RESETBMCU

Power Down

Sequence

Power Down

Delay

aaa-030050

Figure 11.ꢀPower down delay

The default value of the OTP_PD_SEQ_DLY[1:0] bits on an unprogrammed OTP device

shall be 00.

14.7 Fault detection

Three types of faults are monitored per regulator: UV, OV and ILIM. Faults are monitored

during power up sequence, run, standby and WD reset states. A fault event is notified to

the MCU through the INTB pin if the corresponding fault is not masked.

The fault configuration registers are reset to their default value after the power up

sequences, and system must configure them as required during the boot-up process via

I²C commands.

For each type of fault, there is an I²C bit that is used to select whether the regulator is

kept enabled or disabled when the corresponding regulator experience a fault event.

SWx_ILIM_STATE

• 0 = regulator disables upon an ILIM fault event

• 1 = regulator remains on upon an ILIM fault event

SWx_OV_STATE

• 0 = regulator disables upon an OV fault event

• 1 = regulator remains on upon an OV fault event

SWx_UV_STATE

• 0 = regulator disables upon an UV fault event

• 1 = regulator remains on upon an UV fault event

The following table lists the functional bits associated with enabling/disabling the external

regulators when they experience a fault.

Table 23.ꢀRegulator control during fault event bits

Regulator

Bit to disable the

regulator during current regulator during

limit

Bit to disable the

regulator during

overvoltage

undervoltage

SWx

SWx_ILIM_STATE

SWx_UV_STATE

SWx_OV_STATE

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

ILIM faults are debounced for 1.0 ms before they can be detected as a fault condition. If

the regulator is programed to disable upon an ILIM condition, the regulator turns off as

soon as the ILIM condition is detected.

OV/UV faults are debounced for defined filter time before they are detected as a fault

condition. If the regulator is programmed to disable upon an OV or UV, the regulator will

turn off if the fault persist for longer than 300 µs after the OV/UV fault has been detected.

RegX_STATE = 0 && Regx_FLT_REN = 0

OV/UV fault

REGx

REGx_EN

RegX_PG

PGOOD

User

Enabled

300 µs

RegX_STATE = 0 && Regx_FLT_REN = 0

ILIM fault

REGx

ILIM

I_REGx

REGx_EN

User

Enabled

aaa-028057

1 ms

Figure 12.ꢀRegulator turned off upon with RegX_STATE = 0 and FLT_REN = 0

When a regulator is programmed to disable upon an OV, UV, or ILIM fault, a bit is

provided to decide whether a regulator can return to its previous configuration or remain

disabled when the fault condition is cleared.

SWx_FLT_REN

• 0 = regulator remains disabled after the fault condition is cleared or no longer present

• 1 = regulator returns to its previous state if fault condition is cleared

If a regulator is programmed to remain disabled after clearing the fault condition, the

MCU can turn it back ON during the system On state by toggling OFF and ON the

corresponding mode/enable bits.

When the bit SWx_FLT_REN = 1, if a regulator is programmed to turn off upon an OV,

UV or ILIM condition, the regulator returns to its previous state 500 µs after the fault

condition is cleared. If the regulator is programmed to turn off upon an ILIM condition, the

device may take up to 1.0 ms to debounce the ILIM condition removal, in addition to the

500 µs wait period to re-enable the regulator.

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

RegX_STATE = 0 && FLT_REN = 1

OV/UV fault

REGx

REGx_EN

REGx_PG

PGOOD

300 µs

500 µs

RegX_STATE = 0 && FLT_REN = 1

ILIM fault

REGx

I_REGx

ILIM

REGx_EN

1 ms

1.5 ms

1 ms

1.5 ms

aaa-028058

Figure 13.ꢀRegulator turned off upon with RegX_STATE = 0 and FLT_REN = 1

When any of the regulators is controlled by hardware using the ENx pins and

programmed to turn off upon an OV, UV or ILIM fault, the _FLT_REN bit still controls

whether the regulator returns to its previous state or not regardless the state of the ENx

pin.

To avoid fault cycling, a global fault counter is provided. Each time any of the

external regulators encounter a fault event, the PF5023 compares the value of the

FAULT_CNT[3:0] against the FAULT_MAX_CNT, and if it not equal, it increments the

FAULT_CNT[3:0] and proceeds with the fault protection mechanism.

The processor is expected to read the counter value and reset it when the faults have

been cleared and the device returns to a normal operation. If the processor does not

reset the fault counter and it equals the FAULT_MAX_CNT[3:0] value, the state machine

initiates a power down sequence.

The default value of the FAULT_MAX_CNT[3:0] is loaded from the

OTP_FAULT_MAX_CNT[3:0] bits during the power up sequence.

When the FAULT_MAX_CNT[3:0] is set to 0x00, the system disables the turn-off events

due to a fault counter maxing out.

When a regulator experiences a fault event, a fault timer is started. While this timer

is in progress, the expectation is that the processor takes actions to clear the fault.

For example, it could reduce its load in the event of a current limit fault, or turn off the

regulator in the event of an overvoltage fault.

If the fault clears before the timer expires, the state machine resumes the normal

operation, and the fault timer gets reset. If the fault does not clear before the timer

expires, a power down sequence is initiated to turn off the voltage regulators.

The default value of the fault timer is set by the OTP_TIMER_FAULT[3:0], however the

duration of the fault timer can be changed during the system On state by modifying the

TIMER_FAULT[3:0] bits in the I²C registers.

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Table 24.ꢀFault timer register configuration

OTP bits

Functional bits

Timer value

(ms)

OTP_TIMER_FAULT [3:0]

TIMER_FAULT [3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

4

8

16

32

64

128

256

512

1024

2056

Reserved

Disabled

Each voltage regulator has a dedicated I²C bit that is used to bypass the fault detection

mechanism for each specific fault.

SWx_ILIM_BYPASS

• 0 = ILIM protection enabled

• 1 = ILIM fault bypassed

SWx_OV_BYPASS

• 0 = OV protection enabled

• 1 = OV fault bypassed

SWx_UV_BYPASS

• 0 = UV protection enabled

• 1 = UV fault bypassed

Table 25.ꢀFault bypass bits

Regulator

Bit to bypass a current

limit

Bit to bypass an

undervoltage

Bit to bypass an

overvoltage

SWx

SWx_ILIM_BYPASS

SWx_UV_BYPASS

SWx_OV_BYPASS

The default value of the OV_BYPASS, UV_BYPASS and ILIM_BYPASS bits upon power

up can be configured by their corresponding OTP bits.

Bypassing the fault detection prevents the specific fault from starting any of the protective

mechanism:

• Increment the counter

• Start the fault timer

• Disable the regulator if the corresponding _STATE bit is 0

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PF5023

Power management integrated circuit (PMIC) for high performance applications

• OV/UV condition asserting the PGOOD and PGOODx pins low

When a fault is bypassed, the corresponding interrupt bit is still set and the INTB pin is

asserted, provided the interrupt has not been masked.

14.7.1 Fault monitoring during power up state

An OTP bit is provided to select whether the output of the switching regulators is

verified during the power up sequence and used as a gating condition to release the

RESETBMCU or not.

• When OTP_PG_CHECK = 0, the output voltage of the regulators is not checked during

the power up sequence and power good indication is not required to de-assert the

RESETBMCU. In this scenario, the OV/UV monitors are masked until RESETBMCU

is released; after this event, all regulators may start checking for faults after their

corresponding blanking period.

• When OTP_PG_CHECK = 1, the output voltage of the regulators is verified during

the power up sequence and a power good condition is required to release the

RESETBMCU.

When OTP_PG_CHECK = 1, OV and UV faults during the power up sequence are

reported based on the internal PG (Power Good) signals of the corresponding external

regulator. The PGOOD pin can be used as an external indicator of an OV/UV failure

when the RESETBMCU is ready to be de-asserted and it has been configured in the

PGOOD mode. See Section 14.9.6 "PGOOD" for details on PGOOD pin operation and

configuration.

Regardless of the PGOOD pin configured as a power good indicator or not, the PF5023

masks the detection of an OV/UV failure until RESETBMCU is ready to be released, at

this point the device checks for any OV/UV condition for the regulators turned on so far.

If all regulators powered up before or in the same sequence slot than RESETBMCU are

in regulation, RESETBMCU is de-asserted and the power up sequence can continue as

shown in Figure 14.

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

RESETBMCU

PGOOD

(optional)

PGOOD3

SW3

PGOOD2

SW2

PGOOD1

SW1

SYSTEM ON

aaa-032238

Figure 14.ꢀCorrect power up (no fault during power up)

If any of the regulators are powered up before RESETBMCU is out of regulator,

RESETBMCU is not de-asserted and the power up sequence is stopped for up to 2.0

ms. If the fault is cleared and all internal PG signals are asserted within the 2.0 ms timer,

RESETBMCU is de-asserted and the power up sequence continues where it stopped as

shown in Figure 15.

RESETBMCU

PGOOD

(optional)

PGOOD3

SW3

PGOOD2

SW2

PGOOD1

SW1

SYSTEM ON

Regulator

Recovery

< 2 ms

aaa-032239

Figure 15.ꢀPower up sequencer with a temporary failure

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

If the faulty condition is not cleared within the 2.0 ms timer, the power up sequence

is aborted and the PF5023 turns off all voltage regulators enabled so far as shown in

Figure 16.

RESETBMCU

PGOOD

(optional)

PGOOD3

SW3

PGOOD2

SW2

PGOOD1

SW1

2 ms (max)

Recovery

Reg Power down

aaa-032240

Figure 16.ꢀPower up sequencer aborted as fault persists for longer than 2.0 ms

Supplies enabled after RESETBMCU are checked for OV, UV and ILIM faults after each

of them are enabled. If an OV, UV or ILIM condition is present, the PF5023 starts a fault

detection and protection mechanism as described in Section 14.7 "Fault detection". At

this point, the MCU should be able to read the interrupt and react upon a fault event as

defined by the system.

If a regulator fault occurs after RESETBMCU is de-asserted but before the power

up sequence is finalized, the power up sequences continue to turn on the remaining

regulators as configured, even if a fault detection mechanism is active on an earlier

regulator.

14.8 Interrupt management

The MCU is notified of any interrupt through the INTB pin and various interrupt registers.

The interrupt registers are composed by three types of bits to help manage all the

interrupt requests in the PF5023:

• The interrupt latch XXXX_I: this bit is set when the corresponding interrupt event

occurs. It can be read at any time, and is cleared by writing a 1 to the bit.

• The mask bit XXXX_M: this bit controls whether a given interrupt latch pulls the INTB

pin low or not.

• When the mask bit is 1, the interrupt latch does not control the INTB pin.

• When the mask bit is 0, the INTB pin is pulled low as long as the corresponding latch

bit is set.

• The sense bit XXXX_S: if available, the sense bit provides the actual status of the

signal triggering the interrupt.

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PF5023

Power management integrated circuit (PMIC) for high performance applications

The INTB pin is a reflection of an “OR” logic of all the interrupt status bits which control

the pin.

Interrupts are stored in two levels on the interrupts registers. At first level, the SYS_INT

register provides information about the Interrupt register that originated the interrupt

event.

The corresponding SYS_INT bits is set as long as the INTB pin is programmed to assert

with any of the interrupt bits of the respective interrupt registers.

• STATUS1_I: this bit is set when the interrupt is generated within the INT STATUS1

register

• STATUS2_I: this bit is set when the interrupt is generated within the INT STATUS2

register

• MODE_I: this bit is set when the interrupt is generated within the SW MODE INT

register

• ILIM_I: this bit is set when the interrupt is generated within any of the SW ILIM INT

register

• UV_I: this bit is set when the interrupt is generated within any of the SW UV INT

• OV_I: this bit is set when the interrupt is generated within any of the SW OV register

• PWRON_I: this bit is set when the interrupt is generated within the PWRON INT

register

• EWARN_I: is set when an early warning event occurs to indicate an imminent

shutdown

The SYS_INT bits are set when the INTB pin is asserted by any of the second level

interrupt bits that have not been masked in their corresponding mask registers. When

the second level interrupt bit is cleared, the corresponding first level interrupt bit on the

SYS_INT register will be cleared automatically.

The INTB pin will remain asserted if any of the first level interrupts bit is set, and it will be

de-asserted only when all the unmasked second level interrupts are cleared and thus all

the first level interrupts are cleared as well.

At second level the remaining registers provide the exact source for the interrupt event.

Table 26 shows a summary of the interrupt latch, mask and sense pins available on the

PF5023.

Table 26.ꢀInterrupt registers

Register name

INT STATUS1

INT MASK1

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

SDWN_I

FREQ_RDY_I

CRC_I

PWRUP_I

PWRDN_I

—

PGOOD_I

VIN_OVLO_I

VIN_OVLO_M

VIN_OVLO_S

THERM_80_I

THERM_80_M

THERM_80_S

SW1_MODE_I

SW1_MODE_M

SW1_ILIM_I

SW1_ILIM_M

SW1_ILIM_S

SW1_UV_I

SDWN_M

FREQ_RDY_M

CRC_M

PWRUP_M

PWRDN_M

—

PGOOD_M

PGOOD_S

INT SENSE1

THERM INT

—

WDI_I

FSYNC_FLT_I

THERM_155_I

THERM_140_I

THERM_125_I

THERM_110_I

THERM_110_M

THERM_110_S

SW3_MODE_I

SW3_MODE_M

SW3_ILIM_I

SW3_ILIM_M

SW3_ILIM_S

SW3_UV_I

SW3_UV_M

SW3_UV_S

SW3_OV_I

SW3_OV_M

SW3_OV_S

PWRON_1S_I

THERM_95_I

THERM_95_M

THERM_95_S

SW2_MODE_I

SW2_MODE_M

SW2_ILIM_I

SW2_ILIM_M

SW2_ILIM_S

SW2_UV_I

THERM MASK

THERM SENSE

SW MODE INT

SW MODE MASK

SW ILIM INT

WDI_M

FSYNC_FLT_M

THERM_155_M

THERM_140_M

THERM_125_M

WDI_S

FSYNC_FLT_S

THERM_155_S

THERM_140_S

THERM_125_S

—

SW ILIM MASK

SW ILIM SENSE

SW UV INT

—

SW UV MASK

SW UV SENSE

SW OV INT

—

SW2_UV_M

SW2_UV_S

SW2_OV_I

SW1_UV_M

SW1_UV_S

SW1_OV_I

—

SW OV MASK

SW OV SENSE

PWRON INT

—

SW2_OV_M

SW2_OV_S

PWRON_REL_I

SW1_OV_M

SW1_OV_S

PWRON_PUSH_I

—

BGMON_I

PWRON_8S_I

PWRON_4S_I

PRON_3S_I

PWRON_2S_I

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PF5023

Power management integrated circuit (PMIC) for high performance applications

Register name

PWRON MASK

PWRON SENSE

EN_SENSE

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

BGMON_M

BGMON_S

—

PWRON_8S_M

PWRON_4S_M

PRON_3S_M

PWRON_2S_M

PWRON_1S_M

—

PWRON_REL_M

—

PWRON_PUSH_M

PWRON_S

EN1_S

—

EN3_S

MODE_I

EN2_S

SYS INT

EWARN_I

PWRON_I

OV_I

UV_I

ILIM_I

STATUS2_I

STATUS1_I

14.9 I/O interface pins

The PF5023 PMIC is fully programmable via the I²C interface. Additional communication

between MCU, PF5023 and other companion PMIC is provided by direct logic interfacing

including INTB, RESETBMCU, PGOOD, among other pins.

PMIC1

PMIC2

PF5023

V1P5A

MCU

aaa-032260

Figure 17.ꢀI/O interface diagram

Table 27.ꢀI/O electrical specifications

Symbol

Parameter

Min

—

Typ

—

Max

Unit

PWRON_V_IL

PWRON_V_IH

STANDBY_V_IL

STANDBY_V_IH

RESETBMCU_V_OL

PWRON low input voltage

PWRON high input voltage

STANDBY low input voltage

STANDBY high input voltage

0.4

5.5

0.4

5.5

V

1.4

—

1.4

—

RESETBMCU low output voltage

−2.0 mA load current

0

—

0.4

INTB_V_OL

INTB low output voltage

−2.0 mA load current

V

0

—

0.4

ENx_V_IL

ENx_V_IH

WDI_V_IL

ENx low input voltage

ENx high input voltage

WDI low input voltage

—

1.4

—

0.4

V

5.5

0.3*VDDIO

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PF5023

Power management integrated circuit (PMIC) for high performance applications

Symbol

Parameter

Min

Typ

—

Max

5.5

—

Unit

V

WDI_V_IH

R_{WDI_PD}

WDI high input voltage

WDI internal pull-down resistance

0.7*VDDIO

0.475

1.0

MΩ

V

PGOOD_V_OL

PGOOD low output voltage

−2.0 mA load current

0

—

0.4

PGOODx_V_OL

PGOODx low output voltage

−2.0 mA load current

V

0

—

1.0

—

0.4

5.5

—

TBBEN_V_IL

TBBEN_V_IH

R_{TBBEN_PD}

TBBEN low input voltage

—

V

TBBEN high input voltage

TBBEN internal pull-down resistance

XFAILB low input voltage

1.4

0.475

—

V

MΩ

V

XFAILB_V_IL

XFAILB_V_IH

XFAILB_V_OH

0.4

5.5

XFAILB high input voltage

1.4

V

XFAILB high output voltage

Pulled-up to V1P5A

V

V1P5A − 0.5

—

XFAILB_V_OL

XFAILB low output voltage

−2.0 mA load current

V

0

—

0.4

SCL_V_IL

SCL_V_IH

SDA_V_IL

SDA_V_IH

SDA_V_OL

SCL low input voltage

SCL high input voltage

SDA low input voltage

SDA high input voltage

—

0.3*VDDIO

VDDIO

V

0.7*VDDIO

—

0.3*VDDIO

VDDIO

0.7*VDDIO

SDA low output voltage

−20 mA load current

0

—

0.4

14.9.1 PWRON

PWRON is an input signal to the IC that acts as a power up event signal in the PF5023.

The PWRON pin has two modes of operation as programed by the

OTP_PWRON_MODE bit.

When OTP_PWRON_MODE = 0, the PWRON pin operates in level sensitive mode. In

this mode, the device is in the corresponding off mode when the PWRON pin is pulled

low. Pulling the PWRON pin high is a necessary condition to generate a power on event.

When OTP_PWRON_MODE = 1, the PWRON pin operates in edge sensitive mode. In

this mode, PWRON is used as an input from a push button connected to the PMIC.

When the switch is not pressed, the PWRON pin is pulled up to VIN externally through

a 100 kΩ resistor. When the switch is pressed, the PWRON pin should be shorted to

ground. The PWRON_S bit is low whenever the PWRON pin is at logic 0 and is high

whenever the PWRON pin is at logic 1.

The PWRON pin has a programmable debounce on the rising and falling edges as

shown in Table 28.

Table 28.ꢀPWRON debounce configuration in edge detection mode

Bits

Value

Falling edge debounce

(ms)

Rising edge debounce

(ms)

PWRON_DBNC[1:0]

00

01

10

11

32

125

750

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Power management integrated circuit (PMIC) for high performance applications

The default value for the power on debounce is set by the OTP_PWRON_DBNC[1:0]

bits.

Pressing the PWRON switch for longer than the debounce time starts a power on

event as well as generate interrupts which the processor may use to initiate PMIC state

transitions.

During the system On state, when the PWRON button is pushed (logic 0) for longer than

the debounce setting, the PWRON_PUSH_I interrupt is generated. When the PWRON

button is released (logic 1) for longer than the debounce setting, the PWRON_REL_I

interrupt is generated.

The PWRON_1S_I, PWRON_2S_I, PWRON_3S_I, PWRON_4S_I and PWRON_8S_I

interrupts are generated when the PWRON pin is held low for longer than 1, 2, 3, 4 and 8

seconds respectively.

If PWRON_RST_EN = 1, pressing the PWRON for longer than the delay programmed by

TRESET[1:0] forces a PMIC reset. A PMIC reset initiates a power down sequence, wait

for 30 µs to allow all supplies to discharge and then it powers back up with the default

OTP configuration.

If PWRON_RST_EN = 0, the device starts a turn off event after push button is pressed

for longer than TRESET[1:0].

Table 29.ꢀ TRESET configuration

TRESET[1:0]

Time to reset

00

01

10

11

2 s

4 s

8 s

16 s

The default value of the TRESET delay is programmable through the OTP_TRESET[1:0]

bits.

14.9.2 STANDBY

STANDBY is an input signal to the IC, when this pin is asserted, the device enters the

standby mode and when de-asserted, the part exits Standby mode.

STANDBY can be configured as active high or active low using the STANDBYINV bit.

Table 30.ꢀStandby pin polarity control

STANDBY (pin)

STANDBYINV (I²C bit)

STANDBY control

Not in Standby mode

In Standby mode

0

1

0

1

0

1

In Standby mode

Not in Standby mode

14.9.3 RESETBMCU

RESETBMCU is an open-drain, active low output used to bring the processor (and

peripherals) in and out of reset.

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The time slot RESETBMCU is de-asserted during the power up sequence is programmed

by the OTP_RESETBMCU_SEQ[7:0] bits, and it is a condition to enter the system On

state.

During the system On state, the RESETBMCU is de-asserted (pulled high), and it is

asserted (pulled low) as indicated in the power down sequence, when a system power

down or reset is initiated.

In the application, RESETBMCU can be pulled up to VDDIO or VSNVS by a 10 kΩ

external resistor. It is also recommended to add a 10 nF bypass capacitor close to the pin

to improve the EM immunity performance.

14.9.4 INTB

INTB is an open-drain, active low output. This pin is asserted (pulled low) when any

interrupt occurs, provided that the interrupt is not masked.

INTB is de-asserted after the corresponding interrupt latch is cleared by software, which

requires writing a “1” to the interrupt bit.

An INTB_TEST bit is provided to allow a manual test of the INTB pin. When INTB_TEST

is set to 1, the interrupt pin asserts for 100 µs and then de-asserts to its normal state.

The INTB_TEST bit self-clears to 0 automatically after the test pulse is generated.

In the application, INTB can be pulled up to VDDIO with an external 100 kΩ resistor.

14.9.5 WDI

WDI is an input pin to the PF5023 and is intended to operate as an external watchdog

monitor.

When the WDI pin is connected to the watchdog output of the processor, this pin is used

to detect a pulse to indicate a watchdog event is requested by the processor. When the

WDI pin is asserted, the device starts a watchdog event to place the PMIC outputs in a

default known state.

The WDI pin is monitored during the system On state. In the Off modes and during the

power up sequence, the WDI pin is masked until RESETBMCU is de-asserted.

The WDI can be configured to assert on the rising or the falling edge using the

OTP_WDI_INV bit.

• When OTP_WDI_INV = 0, the device starts a WD event on the falling edge of the WDI.

• When OTP_WDI_INV = 1, the device starts a WD event on the rising edge of the WDI.

A 10 µs debounce filter is implemented on either rising or falling edge detection to

prevent false WDI signals to start a watchdog event.

The WDI_MODE bit allows the WDI pin to react in two different ways:

• When WDI_MODE = 1, a WDI asserted performs a hard WD reset.

• When WDI_MODE = 0, a WDI asserted performs a soft WD reset.

The default value of the WDI_MODE bit is set by the OTP _WDI_MODE bit in the OTP

register space.

The WDI_STBY_ACTIVE bit allows the WDI pin to generate a watchdog event during the

standby state.

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• When WDI_STBY_ACTIVE = 0, asserting the WDI will not generate a watchdog event

during the standby state.

• When WDI_STBY_ACTIVE = 1, asserting the WDI will start a watchdog event during

the standby state.

The OTP_WDI_STBY_ACTIVE is used to configure whether the WDI is active in the

standby state or not by default upon power up.

See Section 15.7 "Watchdog event management" for details on watchdog event.

14.9.6 PGOOD

PGOOD is an open drain output programmable as a power good indicator pin or GPO. In

the application, PGOOD can be pulled up to VDDIO with a 100 kΩ resistor.

When OTP_PG_ACTIVE = 0, the PGOOD pin is used as a general purpose output.

As a GPO, during the run state, the state of the pin is controlled by the RUN_PG_GPO

bit in the functional I²C registers:

• When RUN_PG_GPO = 1, the PGOOD pin is high

• When RUN_PG_GPO = 0, the PGOOD pin is low

During the standby state, the state of the pin is controlled by the STBY_PG_GPO bit in

the functional I²C registers:

• When STBY_PG_GPO = 1, the PGOOD pin is high

• When STBY_PG_GPO = 0, the PGOOD pin is low

When used as a GPO, the PGOOD pin can be enabled high as part of the

power up sequence as programmed by the OTP_SEQ_TBASE[1:0] and the

OTP_PGOOD_SEQ[7:0] bits. If enabled as part of the power up sequence, both the

RUN_PG_GPO and STBY_PG_GPO bits are loaded with 1, otherwise they are loaded

with 0 upon power up.

When OTP_PG_ACTIVE = 1, the PGOOD pin is in Power good (PG) mode and it acts as

a PGOOD indicator for the selected output voltages in the PF5023.

The PGOOD pin is pulled low when any of the selected regulator outputs falls above

or below the programmed OV/UV thresholds and the corresponding OV/UV interrupt is

generated. If the faulty condition is removed, the corresponding OV_S/UV_S bit goes low

to indicate the output is back in regulation, however, the interrupt remains latched until it

is cleared.

The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt

registers. For more details on handling interrupts, see Section 14.8 "Interrupt

management".

When a particular regulator is disabled (via OTP, or I²C, or by change in state of PMIC

such as going to standby mode), it no longer controls the PGOOD pin.

In the Off mode and during the power up sequence, the PGOOD pin is held low until

RESETBMCU is ready to be released, at this point, the PG monitors are unmasked and

the PGOOD pin is released high if all the internal PG monitors are in regulation. In the

event that one or more outputs are not in regulation by the time RESETBMCU is ready to

de-assert, the PGOOD pin is held low and the PF5023 performs the corresponding fault

protection mechanism as described in Section 14.7.1 "Fault monitoring during power up

state".

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14.9.7 PGOODx

The PGOODx pins are open drain outputs to provide the power good status of each

regulator. In the application, PGOODx can be pulled up to VDDIO with a 100 kΩ resistor.

The PGOODx pin is pulled low when the corresponding regulator output falls above or

below the programmed OV/UV thresholds.

The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt

registers. For more details on handling interrupts, see Section 14.8 "Interrupt

management".

Table 31.ꢀPGOODx assignment

PF5023 regulator

PGOOD1

PGOOD2

PGOOD3

SW1

SW2

SW3

14.9.8 ENx

The ENx input pin is used to enable or disable the dedicated regulator via hardware.

When the ENx pin is asserted low, the corresponding regulator is turned off.

Table 32.ꢀENx assignment

PF5023 regulator

EN1

EN2

EN3

SW1

SW2

SW3

The status of the ENx pin can be monitored via the corresponding ENx_S flag bit in the

EN SENSE register.

• When ENx is in low state, ENx_S flag is set to 0.

• When ENx is in high state, ENx_S flag is set to 1.

14.9.9 TBBEN

The TBBEN is an input pin provided to allow the user to program the mirror registers

in order to operate the device with a custom configuration as well as programming the

default values on the OTP fuses.

• When TBBEN pin is pulled low to ground, the device is operating in normal mode.

• When TBBEN pin is pulled high to V1P5D, the device enables the TBB configuration

mode.

See Section 17 "OTP/TBB and hardwire default configurations" for details on TBB and

OTP operation.

When TBBEN pin is pulled high to V1P5D the following conditions apply:

• The device uses a fixed I²C device address (0x08)

• Disable the watchdog operation, including WDI monitoring and internal watchdog timer

• Disable the CRC and I²C secure write mechanism while no power up event is present

(TBB/OTP programming mode).

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Disabling the watchdog operation may be required for in-line MCU programming where

output voltages are required but watchdog operation should be completely disabled.

14.9.10 XFAILB

XFAILB is a bidirectional pin with an open drain output used to synchronize the power

up and power down sequences of two or more PMICs. It should normally be pulled up

externally to V1P5A supply.

The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation.

• When OTP_XFAILB_EN = 0, the XFAILB mode is disabled and any events on this pin

are ignored.

• When OTP_XFAILB_EN = 1, the XFAILB mode is enabled

When the XFAILB mode is enabled, and the PF5023 has a turn off event generated by

an internal fault, the XFAILB pin is asserted low 20 µs before starting the power down

sequence.

A power down event caused by the following conditions will assert the XFAILB pin:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT (Regulator fault counter max out)

• WD_EVENT_CNT = WD_MAX_CNT (Watchdog event counter max out)

• Power up failure

• Thermal shutdown

• Hard WD event

The XFAILB pin is forced low during the Off mode.

During the system On state, if the XFAILB pin is externally pulled low, it will detect an

XFAIL event after a 20 µs debounce. When an XFAIL event is detected, the XFAILB pin

is asserted low internally and the device starts a power down sequence.

If a PWRON event is present, the device will start a turn on event and proceed to release

the XFAILB pin when its ready to start the power up sequence state. If the XFAILB pin

is pulled down externally during the power up event, the PF5023 will stop the power up

sequence until the pin is no longer pulled down externally. This will help both PMICs to

synchronize the power up sequence allowing it to continue only when both PMICs are

ready to initiate the power up sequence.

A hard WD event will set the XFAILB pin 20 µs before it starts its power down sequence.

After all regulator outputs have been turned off, the device will release the XFAILB pin

internally after a 30 µs delay, proceed to load the default OTP configuration and wait for

the XFAILB pin to be released externally before it can restart the power up sequence.

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Bidirectional XFAILB (Power UP)

PWRON

Power Up

Sequence

States

LP_Off

Self-Test QPU_Off

System On

XFAILB

RESETBMCU

POWER UP

Sequence

aaa-029989

Figure 18.ꢀXFAILB behavior during a power up sequence

Bidirectional XFAILB (Power Down)

Power Down

Sequence

System On

Off Mode

States

FAULT EVENT

EWARN

XFAILB

100 µs

20 µs

POWER DOWN

Signal

POWER DOWN

Sequence

aaa-029990

Figure 19.ꢀXFAILB behavior during a power down sequence

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Dual PMIC interaction (Fault on Master PMIC)

PWRON

FAULT EVENT

EWARN

100 µs

Power Up Sequence is started

until both XFAILB are pulled high

XFAILB

MASTER

20 µs

PMIC

POWER DOWN

Signal

POWER DOWN

Sequence

POWER UP

Sequence

EWARN

XFAILB

Pin externally pulled down

XFAILB

Debounced

POWER DOWN

Signal

20 µs

SLAVE

PMIC

POWER DOWN

Sequence

POWER UP

Sequence

Slave Ready to start Power Up Sequence (waiting)

aaa-029991

Figure 20.ꢀBehavior during an external XFAILB event

XFAILB During Power Up Sequence

PWRON

POWER UP

Sequence

RESETBMCU

XFAILB

MASTER

PMIC

2 ms

Power Up Sequence is started

until both XFAILB are pulled high

POWER DOWN

Signal

POWER UP

Sequence

Slave Ready to start Power Up Sequence (waiting)

SLAVE

PMIC

XFAILB

Pin externally pulled down

POWER DOWN

Signal

aaa-029992

Figure 21.ꢀExternal XFAILB event during a power up sequence

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14.9.11 SDA and SCL (I²C bus)

Communication with the PF5023 is done through I²C and it supports high-speed

operation mode with up to 3.4 MHz operation. SDA and SCL are pulled up to VDDIO with

1.5 kΩ resistors.

The PF5023 is designed to operate as a slave device during I²C communication. The

default I²C device address is set by the OTP_I2C_ADD[2:0].

Table 33.ꢀI²C address configuration

OTP_I2C_ADD[2:0]

Device address

0x08

000

001

010

011

100

101

110

111

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

See http://www.nxp.com/documents/user_manual/UM10204.pdf for detailed information

on the digital I²C communication protocol implementation.

During an I²C transaction, the communication will latch after the 8th bit sent. If the data

sent is not a multiple of 8 bit, any word with less than 8 bits will be ignored. If only 7 bits

are sent, no data is written and the logic will not provide an ACK bit to the MCU.

From an IC level, a wrong I²C command can create a system level safety issue. For

example, though the MCU may have intended to set a given regulator’s output to 1.0 V, it

may be erroneously registered as 1.1 V due to noise in the bus.

To prevent a wrong I²C configuration, various protective mechanisms are implemented.

14.9.11.1 I²C CRC verification

When this feature is enabled, a selectable CRC verification is performed on each I²C

transaction.

• When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.

• When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled.

After each I²C transaction, the device calculates the corresponding CRC byte to ensure

the configuration command has not been corrupted.

When a CRC fault is detected, the PF5023 ignores the erroneous configuration

command and triggers a CRC_I interrupt asserting the INTB pin, provided the interrupt is

not masked.

The PF5023 implements a CRC-8-SAE, per the SAE J1850 specification.

• Polynomial = 0x11D

• Initial value = 0xFF

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2

MSB Data

I C CRS Polynominal

Seed: 1 1 1 1 1 1 1 1

7

6

5

4

3

2

1

0

aaa-028696

Figure 22.ꢀ8 bit SAE J1850 CRC polynomial

14.9.11.2 I²C secure write

A secure write mechanism is implemented for specific registers critical to the functional

safety of the device.

• When OTP_I2C_ SECURE_EN = 0, the secure write is disabled.

• When OTP_I2C_ SECURE_EN = 1, the secure write is enabled.

When the secure write is enabled, a specific sequence must be followed in order to grant

writing access on the corresponding secure register.

Secure write sequence is as follows:

• MCU sends command to modify the secure registers

• PMIC generates a random code in the RANDOM_GEN register

• MCU reads the random code from the RANDOM_GEN register and writes it back on

the RANDOM_CHK register

The PMIC compares the RANDOM_CHK against the RANDOM_GEN register:

• If RANDOM_CHK [7:0] = RANDOM_GEN[7:0], the device applies the configuration

on the corresponding secure register, and self-clears both the RANDOM_GEN and

RANDOM_CHK registers.

• If RANDOM_CHK[7:0] different from RANDOM_GEN[7:0], the device ignores the

configuration command and self-clears both the RANDOM_GEN and RANDOM_CHK

registers.

In the event the MCU sends any other command instead of providing a value for the

RANDOM_CHK register, the state machine cancels the ongoing secure write transaction

and performs the new I²C command.

In the event the MCU does not provide a value for the RANDOM_CHK register, the I²C

transaction will time out 10 ms after the RANDOM_GEN code is generated, and device is

ready for a new transaction.

Table 34.ꢀSecure bits

Register

Bit

Description

ABIST OV1

AB_SWx_OV

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST UV1

AB_SWx_UV

Writing a 1 to this flag to clear the ABIST fault

notification

ABIST RUN

CTRL1

AB_RUN

Writing a 1 starts an ABIST on demand

TMP_MON_EN

Writing a 0 disables the thermal monitor, preventing

the thermal interrupts and thermal shutdown event

from being detected

CTRL1

VIN_OVLO_EN

Writing a 0 disables the VIN overvoltage lockout

monitor completely

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Register

Bit

Description

CTRL1

WDI_MODE

Writing a 0 set the WDI event to soft WD reset

Writing a 1 set the WDI event to hard WD reset

CTRL1

VIN_OVLO_SDWN

Writing a 0 disables a shutdown event upon a VIN

overvoltage condition (only interrupts are provided)

CTRL1

WD_EN

Writing a 0 disables the watchdog counter block

WD_STBY_EN

Writing a 0 disables the watchdog counter during the

standby mode

CTRL1

WDI_STBY_ACTIVE

Writing a 0 disables the monitoring of WDI input

during standby mode

CTRL1

I2C_SECURE_EN

SWxVMON_EN

Writing a 0 disables de I²C secure write mode

VMONENx

Writing a 0 disables the OV/UV monitor for SWx

15 Functional blocks

15.1 Analog core and internal voltage references

All regulators use the main bandgap as the reference for the output voltage generations,

this bandgap is also used as reference for the internal analog core and digital core

supplies. The performance of the regulators is directly dependent on the performance of

the bandgap.

No external DC loading is allowed on V1P5A and V1P5D. V1P5D is kept powered

as long as there is a valid supply and it may be used as a reference voltage for the

VDDOTP and TBBEN pins during system power on.

The analog reference supply V1P5A is used as the internal reference supply for the

voltage regulators. it is disabled in the LP_OFF state to achieve low quiescent currents.

In applications where there is two or more PMICs supplying a system, the V1P5A

may be used to pull up the XFAILB pin to achieve proper power up and power down

synchronization during system operation.

A second bandgap is provided as the reference for all the monitoring circuits. This

architecture allows the PF5023 to provide a reliable way to detect not only single point

but also latent faults in order to meet the metrics required by an ASIL B level application.

Table 35.ꢀInternal supplies electrical characteristics

Symbol

V_1P5D

C_1P5D

V_1P5A

Parameter

Min

1.50

—

Typ

1.60

1.0

Max

1.65

—

Unit

V

V1P5D output voltage

V1P5D output capacitor

V1P5A output voltage

V1P5A output capacitor

µF

V

1.50

—

1.60

1.0

1.65

—

C_1P5A

µF

15.2 Type 1 buck regulators (SWx)

The PF5023 features four low voltage regulators with input supply range from 2.5 V

to 5.5 V and output voltage range from 0.4 V to 1.8 V in 6.25 mV steps. Each voltage

regulator is capable to supply 2.5 A and features a programmable soft-start and DVS

ramp for system power optimization.

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VIN

SWxIN

SWxMODE

C

INSWx

SWxILIM

CONTROLLER

L

SWx

SWxLX

SWx

DRIVER

SWxPHASE

C

OSWx

I

SENSE

+

2

I C

2 to 3 MHz

clock

+

INTERFACE

slope

compensation

TYPE II INTERNAL

COMPENSATION

duty cycle

generator

R1

SWxFB

EA

R2

Z2

VSWx

DAC

aaa-028064

Figure 23.ꢀBuck regulator block diagram

The OTP_SWxDVS_RAMP bit sets the default step/time ratio for the power up ramp

during the power up/down sequence as well as the DVS slope during the system On.

The power down ramp and DVS rate during the system On of SW1 to SW3 can be

modified during the system On state by changing the SWxDVS_RAMP bit on the I²C

register map.

The DVS ramp rate between 0.4 V and 1.5 V output setting is based on the internal clock

configuration as shown in Table 36.

The ramp rate at 1.8 V output setting is 20 % faster than the values in Table 36.

Table 36.ꢀSWx ramp rates

All ramp rates are typical values.

Clock frequency tolerance = ± 6 %.

CLK_

FREQ[3:0]

Switching

regulators

frequency

(MHz)

DVS_RAMP = 00

DVS_RAMP = 01

DVS_RAMP = 10

DVS_RAMP = 11

Ramp up rate

Ramp down

rate (mV/µs)

Ramp up rate

Ramp down

rate (mV/µs)

Ramp up rate

Ramp down

rate (mV/µs)

Ramp up rate

Ramp down

rate (mV/µs)

(mV/µs)

0000

0001

0010

0011

0100

1001

1010

1011

1100

2.500

2.625

2.750

2.875

3.000

2.000

2.125

2.250

2.375

7.81

8.20

8.59

8.98

9.38

6.25

6.64

7.03

7.42

5.21

5.47

5.73

5.99

6.25

4.17

4.43

4.69

4.95

15.63

16.41

17.19

17.97

18.75

12.50

13.28

14.06

14.84

10.42

10.94

11.46

11.98

12.50

8.33

3.91

4.10

4.30

4.49

4.69

3.13

3.32

3.52

3.71

2.60

2.73

2.86

2.99

3.13

2.08

2.21

2.34

2.47

1.95

2.05

2.15

2.25

2.34

1.56

1.66

1.76

1.86

1.30

1.37

1.43

1.50

1.56

1.04

1.11

1.17

1.24

8.85

9.38

9.90

Buck regulators SWx use 8 bits to set the output voltage.

• The VSWx_RUN[7:0] set the output voltage during Run mode.

• The VSWx_STBY[7:0] set the output voltage during Standby mode.

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The default output voltage configuration for Run and Standby modes is loaded from the

OTP_VSWx[7:0] registers upon power up.

Table 37.ꢀSWx output voltage configuration

Set point

VSWx_RUN[7:0]

VSWx_STBY[7:0]

V_SWxFB(V)

0

1

2

3

00000000

00000001

00000010

00000011

0.40000

0.40625

0.41250

0.41875

.

175

10101111

1.49375

1.50000

1.80000

Reserved

176

10110000

177

10110001

178 to 255

10110010 to 11111111

DVS operation is available for all voltage settings between 0.4 V to 1.5 V. However,

the SWx regulator is not intended to perform DVS transitions to or from the 1.8 V

configuration. In the event a voltage change is requested between any of the low voltage

settings and 1.8 V, the switching regulator is automatically disabled first and then re-

enabled at the selected voltage level to avoid an uncontrolled transition to the new

voltage setting.

Each regulator is provided with two bits to set its mode of operation.

• The SWx_RUN_MODE[1:0] bits allow the user to change the mode of operation of the

SWx regulators during the run state. If the regulator was programmed as part of the

power up sequence, the SWx_RUN_MODE[1:0] bits are loaded with 0b11 (autoskip) by

default. Otherwise it is loaded with 0b00 (disabled).

• The SWx_STBY_MODE[1:0] bits allow the user to change the mode of operation of

the SWx regulators during the standby state. If the regulator was programmed as part

of the power up sequence, the SWx_STBY_MODE[1:0] bits are loaded with 0b11

(autoskip) by default. Otherwise it is loaded with 0b00 (disabled).

Table 38.ꢀSWx regulator mode configuration

SWx_MODE[1:0]

Mode of operation

OFF

00

01

10

11

PWM mode

PFM mode

Auto skip mode

The SWx_MODE_I interrupt asserts the INTB pin when any of the Type 1 regulators

have changed the mode of operation, provided the corresponding interrupt is not

masked.

To avoid potential detection of an OV/UV fault during SWx ramp up, it is recommended to

power up the regulator in PWM or autoskip mode.

SWx regulators use 2 bits SWxILIM[1:0], to program the current limit detection.

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Table 39.ꢀSWx current limit selection

SWxILIM[1:0]

Typical current limit

00

01

10

11

2.1 A

2.6 A

3.0 A

4.5 A

During single phase operation, all buck regulators use 3 bits (SWxPHASE[2:0]) to control

the phase shift of the switching frequency. Upon power up, the switching phase of all

regulators is defaulted to 0 degrees and can be modified during the system On state.

Table 40.ꢀSWx phase configuration

SWx_PHASE[2:0]

Phase shift [degrees]

000

001

010

011

100

101

110

111

45

90

135

180

225

270

315

0 (default)

Each one of the buck regulator provides 2 OTP bits to configure the value of the inductor

used in the corresponding block. The OTP_SWx_LSELECT[1:0] allows to choose the

inductor as shown in Table 41.

Table 41.ꢀSWx inductor selection bits

OTP_SWx_LSELECT[1:0]

Inductor value

1.0 µH

00

01

10

11

0.47 µH

1.5 µH

Reserved

15.2.1 SW2 VTT operation

SW2 features a selectable VTT mode to create VTT termination for DDR memories.

When SW2_VTTEN = 1, the VTT mode is enabled. In this mode, SW2 reference voltage

is internally connected to SW1FB output through a divider by 2.

During the VTT mode, the DVS operation on SW2 is disabled and SW2 output is given

by V_SW1FB/ 2. In this mode, the minimum output voltage configuration for SW1 should be

800 mV to ensure the SW2 is still within the regulation range at its output.

During the power up sequence, the SW2 (VTT) may be turned on in the same or at a slot

higher than SW1, as required by the system. When SW2 and SW1 are enabled in the

same slot, SW2 will always track the VSW1/2. When SW2 is enabled after SW1, it will

ramp up gradually to a predefined voltage and once this voltage is reached, it will start

tracking VSW1/2. The user may adjust the value at which the SW2 should start tracking

the voltage on the SW1 regulator by setting the OTP_VSW2 register accordingly.

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During normal operation, if the SW1 is disabled via the I²C command, SW2 tracks the

output of SW1 and both regulators are discharged together and pulled down internally.

When SW1 is enabled back via the I²C commands, the SW1 output ramps up to the

corresponding voltage while SW2 is always VSW1/2.

When only SW2 is disabled the PMIC uses the OTP_VTT_PDOWN bit to program

whether the SW2 regulator is disabled with the output in high impedance or discharged

internally.

• When OTP_VTT_PDOWN = 0, the output is disabled in high impedance mode.

• When OTP_VTT_PDOWN = 1, the output is disabled with the internal pull down

enabled.

When SW2 is requested to enable back again, the SW2 ramps up to the voltage set on

the VSW2_RUN or VSW2_STBY registers. Once it reaches the final DVS value, it will

change its reference to start tracking SW1 output again. Note that VSW2_RUN(STBY)

must be set to VSW1_RUN(STBY)/2 or the closest code by the MCU to ensure proper

operation.

When operating in VTT mode, the minimum output voltage configuration for SW1 should

be 800 mV to ensure the SW2 is still within the regulation range at its output.

15.2.2 Multiphase operation

Regulators SW1, SW2 and SW3 can be configured in dual and triple phase mode. In

this mode, SW1 registers control the output voltage and other configurations. Likewise,

SW1FB pin becomes the main feedback node for the resulting voltage rail, however the

two FB pins should be connected together.

The OTP_SW1CONFIG[1:0] bits are used to select the multiphase configuration for

SW1/SW2/SW3.

Table 42.ꢀOTP_SW1CONFIG register description

OTP_SW1CONFIG[1:0]

Description

00

01

10

11

SW1 and SW2 operate in single phase mode

SW1/SW2 operate in dual phase mode

Reserved

SW1/SW2/SW3 operate in triple phase mode

15.2.3 Electrical characteristics

Table 43.ꢀType 1 buck regulator electrical characteristics

All parameters are specified at T_A= −40 to 125 °C, V_SWxIN= UVDET to 5.5 V, V_SWxFB= 1.0 V, I_SWx= 500 mA, typical

external component values, f_SW= 2.25 MHz, unless otherwise noted. Typical values are characterized at V_SWxIN= 5.0 V,

V_SWxFB= 1.0 V, I_SWx= 500 mA, and T_A= 25 °C, unless otherwise noted.

Symbol

V_SWxIN

Parameter ^[1][2]

Min

Typ

Max

Unit

V

Operating functional input voltage

UVDET

—

5.5

V_SWxACC

Output voltage accuracy

PWM mode

mV

−10

—

10

0.4 V ≤ V_SWxFB≤ 0.8 V

0 ≤ I_SWx≤ 2.5 A

V_SWxACC

Output voltage accuracy

PWM mode

%

−2.0

2.0

0.8 V < V_SWxFB≤ 1.5 V

0 ≤ I_SWx≤ 2.5 A

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Symbol

Parameter ^[1][2]

Min

Typ

Max

Unit

V_SWxACC

Output voltage accuracy

PWM mode

%

−1.5

—

1.5

V_SWxFM= 1.1 V

0 ≤ I_SWx≤ 2.5 A

V_SWxACC

Output voltage accuracy

PWM mode

%

−2.0

−36

−57

—

2.0

36

57

V_SWxFB= 1.8 V

0 ≤ I_SWx≤ 2.5 A

V_SWxACCPFM

Output voltage accuracy

PFM mode

mV

0.4 V ≤ V_SWxFB≤ 1.5 V

0 ≤ I_SWx≤ 100 mA

V_SWxACCPFM

Output voltage accuracy

PFM mode

V_SWxFB= 1.8 V

0 ≤ I_SWx≤ 100 mA

t_PFMtoPWM

I_SWx

I_{SWx_DP}

I_SWxLIM

PFM to PWM transition time

Max load current in single phase

Max load current in dual phase

30

—

µs

2500

5000

mA

A

Current limiter - inductor peak current detection

SWxILIM[1:0] = 00

1.6

2.0

2.4

2.1

2.6

3.0

2.5

3.1

3.7

I_SWxLIM

Current limiter - inductor peak current detection

SWxILIM[1:0] = 01

A

Current limiter - inductor peak current detection

SWxILIM[1:0] = 10

Current limiter - inductor peak current detection

SWxILIM[1:0] = 11

3.6

0.6

4.5

1.0

5.45

1.4

I_SWxNLIM

Negative current limit in single phase mode

A

I_{SWxxLIM_DP}

Current limit in dual phase operation

SWxILIM = 00 (master)

3.2

4.0

4.8

7.2

4.8

6.0

7.2

10.8

−25

4.2

5.2

6.0

9.0

6.3

7.8

9.0

13.5

25

5.0

I_{SWxxLIM_DP}

I_{SWxxLIM_TP}

V_SWxOSH

Current limit in dual phase operation

SWxILIM = 01 (master)

A

6.2

Current limit in dual phase operation

SWxILIM = 10 (master)

A

7.4

Current limit in dual phase operation

SWxILIM = 11 (master)

A

10.9

7.5

Current limit in triple phase operation

SWxILIM = 00 (master)

A

Current limit in triple phase operation

SWxILIM = 01 (master)

A

9.3

Current limit in triple phase operation

SWxILIM = 10 (master)

A

11.1

16.35

50

Current limit in triple phase operation

SWxILIM = 11 (master)

A

Startup overshoot

mV

SWxDVS RAMP = 6.25 mV/µs

VSWxIN = 5.5 V, VSWxFB= 1.0 V

t_ONSWxMAX

Maximum turn on time

µs

From enable to 90 % of end value

SWxDVS RAMP = 11 (1.56 mV/µs, 2 MHz)

VSWxIN = 5.5 V, VSWxFB= 1.5 V

—

895

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Symbol

Parameter ^[1][2]

Min

Typ

Max

Unit

t_{ONSWx_MIN}

Minimum turn on time

µs

From enable to 90 % of end value

SWxDVS RAMP = 01 (18.75 mV/µs, 3 MHz)

VSWxIN = 5.5 V, VSWxFB= 0.4 V

49.2

—

η_SWx

Efficiency (PFM mode, 1.0 V, 1.0 mA)

Efficiency (PFM mode, 1.0 V, 50 mA)

Efficiency ( PFM Mode, 1.0 V, 100 mA)

Efficiency (PWM mode, 1.0 V, 500 mA)

Efficiency (PWM mode, 1.0 V, 1000 mA)

Efficiency (PWM mode, 1.0 V, 2000 mA)

—

80

81

82

83

82

79

—

%

mV

η_SWx

V_SWxLOTR

Transient load regulation (overshoot/undershoot)

at 0.8 V < VSWxFB ≤ 1.2 V, COUT = 44 µF per phase

ILOAD = 200 mA to 1.0 A, di/dt = 2.0 A/µs (Single

phase)

−25

—

25

ILOAD = 400 mA to 2.0 A, di/dt = 4.0 A/µs (Dual

phase)

ILOAD = 600 mA to 3.0 A, di/dt = 6.0 A/µs (Triple

phase)

V_SWxLOTR

Transient load regulation (overshoot/undershoot)

%

at 1.25 V < VSWxFB ≤ 1.8 V, COUT = 44 µF per phase

ILOAD = 200 mA to 1.0 A, di/dt = 2.0 A/µs (Single

phase)

−3.0

—

3.0

ILOAD = 400 mA to 2.0 A, di/dt = 4.0 A/µs (Dual

phase)

ILOAD = 600 mA to 3.0 A, di/dt = 6.0 A/µs (Triple

phase)

F_SWx

PWM switching frequency range

Frequency set by CLK_FREQ[3:0]

MHz

1.9

—

2.5

27

3.0

—

3.15

—

T_OFFminSWx

T_DBSWx

T_slew

Minimum off time

ns

%

Deadband time

—

Slewing time (10 % to 90 %)

5.0

D_VSWx

Output ripple in PWM mode

at V_SWxFB= 1.0 V

—

14

1.0

200

—

I_RCS

DCM (skip mode) reverse current sense threshold

Current flowing from PGND to SWxLX

mA

µA

−200

—

I_SWxQ

Quiescent current

PFM mode

I_SWxQ

Quiescent current

Auto skip mode

—

160

200

—

250

320

135

80

I_{SWxQ_DP}

R_ONSWxHS

R_ONSWxLS

R_SWxDIS

Quiescent current in dual phase PWM mode

SWx high-side P-MOSFET R_DS(on)

SWx low-side N-MOSFET R_DS(on)

µA

mΩ

Ω

[3]

—

Discharge resistance

Regulator disabled and ramp down completed

50

100

200

[1] For VSWx configurations greater than 1.35 V, full parametric operation is guaranteed for 2.7 V < SWxVIN < 5.5 V. Below 2.7 V, the SWx regulators are

fully functional with degraded operation due to headroom limitation.

[2] For VSWx = 1.8 V, output capacitance should be kept at or below the maximum recommended value. Likewise, it is recommended to use the slow turn

on/off ramp rate to ensure the output is discharged completely when it is disabled.

[3] Max R_DS(on)does not include bondwire resistance. Consider +/- 50 % tolerance to account for bondwire and pin loss.

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Table 44.ꢀRecommended external components

Symbol

Parameter

Min

Typ

Max

Unit

[1]

L

Output inductor

µH

Maximum inductor DC resistance 50 mΩ

Minimum saturation current at full load: 3.0 A

0.47

1.0

1.5

C_out

Output capacitor

µF

Use 2 × 22 µF, 6.3 V X7T ceramic capacitor to

reduce output capacitance ESR

35

44

53

C_in

Input capacitor

4.7 μF, 10 V X7R ceramic capacitor

4.23

4.7

5.17

[1] Keep inductor DCR as low as possible to improve regulator efficiency.

15.3 Voltage monitoring

The PF5023 provides OV and UV monitoring capability for the following voltage

regulators:

• SW1, SW2, SW3

A programmable UV threshold is selected via the OTP_SWxUV_TH[1:0]. UV threshold

selection represents a percentage of the nominal voltage programmed on each regulator.

Table 45.ꢀUV threshold configuration register

OTP_SWxUV_TH[1:0]

UV threshold level

00

01

10

11

95 %

93 %

91 %

89 %

A programmable OV threshold is selected via the OTP_SWxOV_TH[1:0]. OV threshold

selection represents a percentage of the nominal voltage programmed on each regulator.

Table 46.ꢀOV threshold configuration register

OTP_SWxOV_TH

OV threshold level

105 %

00

01

10

11

107 %

109 %

111 %

Two functional bits are provided to program the UV debounce time for the voltage

regulators.

Table 47.ꢀUV debounce timer configuration

UV_DB[1:0]

UV debounce time

00

01

10

11

5 µs

15 µs

30 µs

40 µs

The default value of the UV_DB[1:0] upon a full register reset is 0b10.

Two functional bits to program the OV debounce time for all the voltage regulators.

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Table 48.ꢀOV debounce timer configuration

OV_DB[1:0]

OV debounce time

30 µs

00

01

10

11

50 µs

80 µs

125 µs

The default value of the OV_DB[1:0] upon a full register reset is 0b00.

The VMON_EN bits enable or disable the OV/UV monitor for each one of the external

regulators (SWxVMON_EN).

• When the VMON_EN bit of a specific regulator is 1, the voltage monitor for that specific

regulator is enabled.

• When the VMON_EN bit of a specific regulator is 0, the voltage monitor for that specific

regulator is disabled.

By default, the VMON_EN bits are set to 1 on power up.

When the I2C_SECURE_EN = 1, a secure write must be performed to set or clear the

VMON_EN bits to enable or disable the voltage monitoring for a specific regulator.

On enabling a regulator, the UV/OV monitor is masked until the corresponding regulator

reaches the point of regulation. If a voltage monitor is disabled, the UV_S and OV_S

indicators from that monitor are reset to 0.

Figure 24 shows the PF5023 voltage monitoring architecture.

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SW1FB

SW1 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

VSW1[7:0]

OV_TH_SEL[3:0]

PGOOD

GENERATOR

SW1_PG

OV/UV

TH Gen

VMON

LOGIC

CONTROL

DVS/REF

Selector

SW1VMON_EN[0]

SW1_PG_EN

Digital

Filter

MON_TRIM[2:0]

UV_TH_SEL[3:0]

MON_ENB

UV

Hyst

V

BG2

SW2FB

SW2 VMON

OV

Hyst

OV

UV

Digital

Filter

OV_TH

UV_TH

VSW2[7:0]

OV_TH_SEL[3:0]

PGOOD

GENERATOR

SW2_PG

OV/UV

TH Gen

PGOOD

VMON

LOGIC

CONTROL

DVS/REF

Selector

SW2VMON_EN[0]

Digital

Filter

MON_TRIM[2:0]

UV_TH_SEL[3:0]

MON_ENB

UV

Hyst

V

BG2

SW3FB

SW3 VMON

OV

Hyst

VSW3[4:0]

VMON

LOGIC

CONTROL

OV

UV

Digital

Filter

OV_TH

UV_TH

OV_TH_SEL[3:0]

MON_VREF

PGOOD

GENERATOR

SW3_PG

OV/UV

TH Gen

SW3VMON_EN[0]

Digital

Filter

MON_TRIM[2:0]

UV_TH_SEL[3:0]

UV

Hyst

MON_ENB

aaa-032241

V

BG2

Figure 24.ꢀVoltage monitoring architecture

15.3.1 Electrical characteristics

Table 49.ꢀVMON electrical characteristics

All parameters are specified at T_A= –40 °C to 125 °C, unless otherwise noted. Typical values are characterized at V_IN

5.0 V, V_xFB= 1.5 V (Type 1 Buck regulator), and T_A= 25 °C, unless otherwise noted.

=

Symbol

Parameter

Min

Typ

Max

Unit

I_QON

Block quiescent current, when block is enabled one block

per regulator

µA

—

10

13

one block per regulator

I_OFF

Block leakage current when disabled

Voltage monitor settling time after enabled

Power good (UV) hysteresis

—

500

30

nA

µs

%

t_{ON_MON}

V_{xFBUVHysteresis}

Voltage difference between UV rising and falling

thresholds

—

0.5

—

V_{UV_Tol}

Undervoltage falling threshold accuracy

%

With respect to target feedback voltage tolerance

For type 1 switching regulator when V_SWxFB> 0.75 V

−2

−3

—

2

3

V_{UV_Tol}

Under voltage falling threshold accuracy

With respect to target feedback voltage

For type 1 switching regulator when VSWxFB ≤ 0.75 V

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Symbol

Parameter

Min

2.5

10

Typ

5.0

15

Max

7.5

20

Unit

t_{UV_DB}

Power good (UV) debounce time UV_DV = 00

Power good (UV) debounce time UV_DV = 01

Power good (UV) debounce time UV_DV = 10

Power good (UV) debounce time UV_DV = 11

µs

20

30

40

25

40

55

V_{OV_Tol}

Overvoltage rising threshold accuracy

%

With respect to target feedback voltage tolerance

For type 1 switching regulator when V_SWxFB> 0.75 V

−2

−3

—

2

3

V_{OV_Tol}

Overvoltage rising threshold

With respect to target feedback voltage tolerance

For type 1 switching regulator when V_SWxFB≤ 0.75 V

V_{xFBOVHysteresis}

Overvoltage (OV) hysteresis

%

Voltage difference between OV rising and falling

thresholds

—

0.5

—

t_{OV_DB}

Power good (OV) debounce time OV_DV = 00

Power good (OV) debounce time OV_DV = 01

Power good (OV) debounce time OV_DV = 10

Power good (OV) debounce time OV_DV = 11

20

35

55

90

30

40

µs

50

65

80

105

160

135

15.4 Clock management

The clock management provides a top-level management control scheme of internal

clock and external synchronization intended to be primarily used for the switching

regulators. The clock management incorporates various subblocks:

• Low power 100 kHz clock

• Internal high frequency clock with programmable frequency

• Phase Locked Loop (PLL)

A digital clock management interface is in charge of supporting interaction among these

blocks.

The clock management provides clocking signals for the internal state machine, the

switching frequencies for the buck converters as well as the multiples of those switching

frequencies in order to enable phase shifting for multiple phase operation.

CLOCK MANAGEMENT BLOCK

INTERNAL

OSCILLATOR

100 kHz ± 5 %

100 kHz

system clock

DLY

f

+ 315°

+ 270°

+ 225°

+ 180°

+ 135°

+ 90°

1

16 to 24 MHz

0

16 to 24 MHz

CKL_FRQ[3:0]

FSS_RANGE

FSS_EN

MUX

1

INTERNAL

DIVIDE

BY

48

416.67 kHz

centered

OSCILLATOR

20 MHz ± 20 %

16 to 24 MHz

0

DIV 1

BY 8

333 kHz - 500 kHz

MUX

DIVIDE

BY

1 OR 6

SYNC

333 kHz - 500 kHz

1

333 to 500 kHz

or 2 - 3 MHz

+ 45°

FREQUENCY

WATCHDOG

FSYNC_RANGE

IN

OUT

PLL

X48

En

SYNCOUT

SYNC_MODE

SYNCOUT_EN

I/O

aaa-033243

Figure 25.ꢀClock management architecture

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15.4.1 Low frequency clock

A low power 100 kHz clock is provided for overall logic and digital control. Internal logic

and debounce timers are based on this 100 kHz clock.

15.4.2 High frequency clock

The PF5023 features a high frequency clock with nominal frequency of 20 MHz. Clock

frequency is programmable over a range of ±20 % via the CLK_FREQ[3:0] control bits.

15.4.3 Manual frequency tuning

The PF5023 features a manual frequency tuning to set the switching frequency of the

high frequency clock. The CLK_FREQ [3:0] bits allow a manual frequency tuning of the

high frequency clock from 16 MHz to 24 MHz.

If a frequency change of two or more steps is requested by a single I²C command, the

device performs a gradual frequency change passing through all steps in between with a

5.2 µs time between each frequency step. When the frequency reaches the programmed

value, The FREQ_RDY_I asserts the INTB pin, provided it is not masked.

When the internal clock is used as the main frequency for the power generation, an

internal frequency divider by 8 is used to generate the switching frequency for all the

buck regulators. Adjusting the frequency of the high frequency clock allows for manual

tuning of the switching frequencies for the buck regulators from 2.0 MHz to 3.0 MHz.

Table 50.ꢀManual frequency tuning configuration

CLK_FREQ[3:0]

High speed clock frequency

(MHz)

Switching regulators frequency

(MHz)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20

2.500

21

2.625

22

2.750

23

2.875

24

3.000

Not used

16

Not used

2.000

17

2.125

18

2.250

19

2.375

Not used

The default switching frequency is set by the OTP_CLK_FREQ[3:0] bits.

Manual tuning cannot be applied when frequency spread-spectrum or external

clock synchronization is used. However, during external clock synchronization, it is

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recommended to program the CLK_FREQ[3:0] bits to match the external frequency as

close as possible.

15.4.4 Spread-spectrum

The internal clock provides a programmable frequency spread spectrum with two ranges

for narrow spread and wide spread to help manage EMC in the automotive applications.

• When the FSS_EN = 1, the frequency spread-spectrum is enabled.

• When the FSS_EN = 0, the frequency spread-spectrum is disabled.

The default state of the FSS_EN bit upon a power up can be configured via the

OTP_FSS_EN bit.

The FSS_RANGE bit is provided to select the clock frequency range.

• When FSS_RANGE = 0, the maximum clock frequency range is ±5 %.

• When FSS_RANGE = 1, the maximum clock frequency range is ±10 %.

The default value of the FSS_RANGE bit upon a power up can be configured via the

OTP_FSS_RANGE bit.

The frequency spread-spectrum is performed at a 24 kHz modulation frequency when

the internal high frequency clock is used to generate the switching frequency for the

switching regulators. When the external clock synchronization is enabled, the spread-

spectrum is disabled.

Figure 26 shows implementation of spread-spectrum for two settings.

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f

= 24 kHz

mod

5 %

f

osc

10.4 µs

SS_RANGE = 0

time

f

= 24 kHz

mod

10 %

f

osc

SS_RANGE = 1

time

5.2 µs

aaa-028069

Figure 26.ꢀSpread-spectrum waveforms

If the frequency spread-spectrum is enabled, the switching regulators should be set in

PWM mode to ensure clock synchronization at all time.

If the external clock synchronization is enabled, (SYNC_MODE = 1), the spread

spectrum is disabled regardless of the value of the FSS_EN bit.

15.4.5 Clock synchronization

An external clock can be fed via the SYNC pin to synchronize the switching regulators to

this external clock.

When the OTP_SYNC_MODE = 0, the external clock synchronization is disabled. In this

case, the PLL is disabled, and the device always uses the internal high frequency clock

to generate the main frequency for the switching regulators.

When the OTP_SYNC_MODE = 1, the external clock synchronization is enabled. In this

case, the internal PLL is always enabled and it uses either the internal high frequency

clock or the SYNC pin as the source to generate the main frequency for the switching

regulators.

If the SYNCIN function is not used, the pin should be grounded. If the external clock is

meant to start up after the PMIC has started, the SYNC pin must be maintained low until

the external clock is applied.

The SYNC pin is prepared to detect clock signals with a 1.8 V or 3.3 V amplitude and

within the frequency range set by the FSYNC_RANGE bit.

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• When the FSYNC_RANGE = 0, the input frequency range at SYNC pin should be

between 2000 kHz and 3000 kHz.

• When the FSYNC_RANGE = 1, the input frequency range at SYNC pin should be

between 333 kHz and 500 kHz.

The OTP_FSYNC_RANGE bit is used to select the default frequency range accepted in

the SYNC pin.

The external clock duty cycle at the SYNC pin should be between 40 % and 60 %. An

input frequency in the SYNC pin outside the range defined by the FSYNC_RANGE bit is

detected as invalid. If the external clock is not present or invalid, the device automatically

switches to the internal clock and sets the FSYNC_FLT_I interrupt, which in turn asserts

the INTB pin provided it is not masked.

The FSYNC_FLT_S bit is set to 1 as long as the input frequency is not preset or invalid,

and it is cleared to 0 when the SYNC has a valid input frequency.

The device switches back to the external switching frequency only when both, the

FSYNC_FLT_I interrupt has been cleared and the SYNC pin sees a valid frequency.

When the external clock is selected, the switching regulators should be set in PWM mode

to ensure clock synchronization at all time.

When the OTP_SYNC_MODE = 0 and OTP_SYNCOUT_EN = 1, the SYNC pin is used

to synchronize an external device to the PF5023.

The SYNC pin outputs the main frequency used for the switching regulators in the range

of 2.0 MHz to 3.0 MHz. The SYNCOUT_EN bit can be used to enable or disable the

SYNCOUT feature via I²C during the system On state.

• When SYNCOUT_EN = 0, the SYNCOUT feature is disabled and the pin is internally

pulled to ground.

• When SYNCOUT_EN = 1, the SYNC pin toggles at the base frequency used by the

switching regulators.

The SYNCOUT function can be enabled or disabled by default by using the

OTP_SYNCOUT_EN bit.

Table 51.ꢀClock management specifications

All parameters are specified at T_A= −40 to 125 °C, unless otherwise noted. Typical values are characterized at V_IN= 5.0 V

and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

Low frequency clock

I_Q100KHz

100 kHz clock quiescent current

100 kHz clock accuracy

—

3.0

5.0

µA

%

f_100KHzACC

−5.0

High frequency clock

f_20MHz

High frequency clock nominal frequency

via CLK_FREQ[3:0] = 0000

MHz

—

20

—

f_20MzACC

High frequency clock accuracy

Clock step transition time

−6.0

6.0

%

t_20MHzStep

µs

Minimum time to transition from one frequency step to

the next in manual tuning mode

—

5.2

—

FSS_RANGE

Spread-spectrum range

FSS_RANGE= 0

%

±5.0

via CLK_FREQ[3:0]

Spread-spectrum is done around center frequency of

20 MHz

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Symbol

Parameter

Min

—

Typ

±10

24

Max

—

Unit

FSS_RANGE

Spread-spectrum range

FSS_RANGE= 1

%

via CLK_FREQ[3:0]

Spread-spectrum is done around center frequency of

20 MHz

FSS_mod

Spread spectrum frequency modulation

—

kHz

Clock synchronization

f_SYNCIN

SYNC input frequency range

FSYNC_RANGE = 0

kHz

2000

333

—

3000

500

f_SYNCIN

SYNC input frequency range

FSYNC_RANGE = 1

f_SYNCOUT

SYNC output frequency range

via CLK_FREQ[3:0]

2000

—

1.0

—

3000

V_SYNCINLO

V_SYNCINHI

Input frequency low voltage threshold

Input frequency high voltage threshold

SYNC internal pull down resistance

Output frequency low voltage threshold

Output frequency high voltage threshold

—

0.3*VDDIO

V

0.7*VDDIO

0.475

—

V

R_{PD_SYNCIN}

V_SYNCOUTLO

V_SYNCOUTHI

__

0.4

—

MΩ

V

0

VDDIO − 0.5

V

15.5 Thermal monitoring

The PF5023 features a temperature sensor at the center of the die which is used to

generate the thermal interrupts and thermal shutdown.

Figure 27 shows a high level block diagram of the thermal monitoring architecture in

PF5023.

COMP

V165C

(TSD)

V

Temp

Tsense

TEMP_IC

V155C

AMUX

DIGITAL LOGIC

STATE MACHINE

V140C

V125C

V110C

V95C

(THERMAL INTERRUPT

DECODING)

V80C

BG

aaa-029998

Figure 27.ꢀThermal monitoring architecture

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Table 52.ꢀThermal monitor specifications

Symbol

Parameter

Min

Typ

—

Max

5.5

—

Unit

V

V_IN

Operating voltage range of thermal circuit

Thermal sensor coefficient

UVDET

—

TCOF

V_TSROMM

−3.8

mV/ºC

V

Thermal sensor voltage

24 ºC

—

1.414

—

T_{SEN_RANGE}

T_80C

Thermal sensor temperature range

80 ºC temperature threshold

–40

70

175

90

ºC

µs

ms

80

T_95C

95 ºC temperature threshold

85

95

105

120

135

150

165

175

—

T_110C

110 ºC temperature threshold

125 ºC temperature threshold

140 ºC temperature threshold

155 ºC temperature threshold

Thermal shutdown threshold

100

115

130

145

155

—

110

125

140

155

165

5.0

10

T_125C

T_140C

T1_55C

T_SD

T_{WARN_HYS}

T_{SD_HYS}

t_temp_db

t_Sinterval

Thermal threshold hysteresis

Thermal shutdown hysteresis

Debounce timer for temperature thresholds (bidirectional)

—

10

—

Sampling interval time

When TMP_MON_AON = 1

—

3.0

—

t_Swindow

Sampling window

µs

When TMP_MON_AON = 1

450

As the temperature crosses the thermal thresholds, the corresponding interrupts are

set to notify the system. The processor may take appropriate action to bring down the

temperature (either by turning off external regulators, reducing load, or turning on a fan).

A 5 ºC hysteresis is implemented on a falling temperature in order to release the

corresponding THERM_x_S signal. When the shutdown threshold is crossed, the

PF5023 initiates a thermal shutdown and it prevents from turning back on until the 15 ºC

thermal shutdown hysteresis is crossed as the device cools down.

The temperature monitor can be enabled or disabled via I²C with the TMP_MON_EN bit.

• When TMP_MON_EN = 0, the temperature monitor circuit is disabled.

• When TMP_MON_EN = 1, the temperature monitor circuit is enabled.

In the Run state, the temperature sensor can operate in always On or Sampling modes.

• When the TMP_MON_AON = 1, the device is always on during the Run mode.

• When the TMP_MON_AON = 0, the device operates in sampling mode to reduce

current consumption in the system. In Sampling mode, the thermal monitor is turned on

during 450 µs at a 3.0 ms sampling interval.

In the Standby mode, the thermal monitor operates only in sampling mode as long as the

TMP_MON_EN = 1.

Table 53.ꢀThermal monitor bit description

Bit(s)

Description

THERM_80_I, THERM_80_S, THERM_80_M

THERM_95_I, THERM_95_S, THERM_95_M

THERM_110_I, THERM_110_S, THERM_110_M

THERM_125_I, THERM_125_S, THERM_125_M

THERM_140_I, THERM_140_S, THERM_140_M

Interrupt, sense and mask bits for 80 ºC threshold

Interrupt, sense and mask bits for 95 ºC threshold

Interrupt, sense and mask bits for 110 ºC threshold

Interrupt, sense and mask bits for 125 ºC threshold

Interrupt, sense and mask bits for 140 ºC threshold

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Bit(s)

Description

THERM_155_I, THERM_155_S, THERM_155_M

Interrupt, sense and mask bits for 155 ºC threshold

TMP_MON_EN

Disables temperature monitoring circuits when

cleared

TMP_MON_AON

When set, the temperature monitoring circuit is always

ON.

When cleared, the temperature monitor operates in

Sampling mode.

15.6 Analog multiplexer

An analog multiplexer (AMUX) is provided to allow access to internal temperature

monitor. The selected voltage is buffered and made available on the PGOOD1 output

pin.

When the AMUX_EN bit is 0, the AMUX block is disabled and the PGOOD1 block is

enabled.

When the AMUX_EN bit is 1, the AMUX block is enabled and the PGOOD1 block is

disabled. The system can select the channel to be read using the AMUX_SEL bits. The

AMUX output is selected by the AMUX_SEL[4:0] bits.

Table 54.ꢀAMUX channel selection

AMUX_EN

AMUX_SEL[4:0]

AMUX selection

PGOOD mode

Disabled - high impedance

Reserved

0

1

XXXXX

00000

00001 to 00110

00111

TEMP_IC

01000 to 11111

Reserved

When the AMUX_EN = 1, and the AMUX_SEL = 00000, the AMUX output is set to a

high impedance mode to allow an external signal to drive the AMUX node. The AMUX is

enabled and accessible during the system On states.

15.7 Watchdog event management

A watchdog event may be started in two ways:

• The WDI pin toggles low due to a watchdog failure on the MCU

• The internal watchdog expiration counter reaches the maximum value the WD timer is

allowed to expire

A watchdog event initiated by the WDI pin may perform a hard WD reset or a soft WD

reset as defined by the WDI_MODE bit. A watchdog event initiated by the internal

watchdog always performs a hard WD reset.

15.7.1 Internal watchdog timer

The internal WD timer counts up and it expires when it reaches the value in the

WD_DURATION[3:0] register. When the WD timer starts counting, the WD_CLEAR

flag is set to 1. Clearing the WD_CLEAR flag within the valid window is interpreted as a

successful watchdog refresh and the WD timer gets reset. The MCU must write a 1 to

clear the WD_CLEAR flag.

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The WD timer is reset when device goes into any of the Off modes and does not start

counting until RESETBMCU is deasserted in the next power up sequence.

The OTP_WD_DURATION[3:0] selects the initial configuration for the watchdog window

duration between 1.0 ms and 32768 ms (typical values).

The watchdog window duration can change during the system On state by modifying the

WD_DURATION[3:0] bits in the functional register map. If the WD_DURATION[3:0] bits

get changed during the system On state, the WD timer is reset.

Table 55.ꢀWatchdog duration register

WD_DURATION[3:0]

Watchdog timer duration (ms)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

4

8

16

32

64

128

256

512

1024

2048

4096

8192

16384

32768

The WD_EXPIRE_CNT[2:0] counter is used to ensure no cyclic watchdog condition

occurs. When the WD_CLEAR flag is cleared successfully before the WD timer

expires, the WD_EXPIRE_CNT[2:0] is decreased by 1. Every time the WD

timer is not successfully refreshed, it gets reset and starts a new count and the

WD_EXPIRE_CNT[2:0] is increased by 2.

If WD_EXPIRE_CNT[2:0] = WD_MAX_EXPIRE[2:0], a WD event is initiated. The default

maximum amount of time the watchdog can expire before starting a WD reset, is set

by the OTP_WD_MAX_EXPIRE[2:0]. Writing a value less than or equal to 0x02 on the

OTP_WD_MAX_EXPIRE causes the watchdog event to be initiated, as soon as the WD

timer expires for the first time.

The OTP_WDWINDOW bit selects whether the watchdog is single ended or window

mode.

• When OTP_WDWINDOW = 0, the WD_CLEAR flag can be cleared within 100 % of the

watchdog timer.

• When OTP_WDWINDOW = 1, the WD_CLEAR flag can only be cleared within the

second half of the programmed watchdog timer. Clearing the WD_CLEAR flag within

the first half of the watchdog window is interpreted as a failure to refresh the watchdog.

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WD_TIMER

100 % Window

WD_EXPIRE_CNT

WD refresh OK

0

WD refresh OK

WD refresh

NOK

1

WD refresh OK

WD refresh

NOK

2

WD_TIMER

Expired

WD refresh OK

WD refresh NOK

WD refresh

NOK

3

WD_TIMER

WD refresh OK

50 % Window

WD refresh

NOK

4

0

WD refresh OK

WD refresh

5

NOK

WD refresh

NOK

WD refresh OK

WD refresh NOK

n =

WD_MAX

_EXPIRE

WD_TIMER

Expired

WD EVENT

WD refresh NOK

aaa-028072

Figure 28.ꢀWatchdog timer operation

The watchdog function can be enabled or disabled by writing the WD_EN bit in the I²C

register map. When the I2C_SECURE_EN = 1, a secure write must be performed to

change the WD_EN bit.

• When WD_EN = 0 the internal watchdog timer operation is disabled.

• When WD_EN = 1 the internal watchdog timer operation is enabled.

The OTP_WD_EN bit is used to select the default status of the watchdog counter upon

power up.

The watchdog function can be programmed to be enabled or disabled during the

Standby state by writing the WD_STBY_EN bit in the I²C register map. When the

I2C_SECURE_EN = 1, a secure write must be performed to modify the WD_STBY_EN

bit.

• When WD_STBY_EN = 0 the internal watchdog timer operation during standby is

disabled.

• When WD_STBY_EN = 1 the internal watchdog timer operation during standby is

enabled.

The OTP_WD_STBY_EN bit selects whether the watchdog is active in Standby mode by

default or not.

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15.7.2 Watchdog reset behaviors

When a watchdog event is started, a watchdog (WD) reset is performed. There are two

types of watchdog reset:

• Soft WD reset

• Hard WD reset

A soft WD reset is used as a safe way for the MCU to force the PMIC to return to a

known default configuration without forcing a POR reset on the MCU. During a soft WD

reset, the RESETBMCU remains de-asserted all the time.

Upon a soft WD reset, a partial OTP register reload is performed on the registers as

shown in Table 56.

Table 56.ꢀSoft WD register reset

Bit name

Register

Bits

Configuration registers

STANDBYINV

CTRL2

2

RUN_PG_GPO

CTRL2

1

STBY_PG_GPO

RESETBMCU_SEQ[7:0]

PGOOD_SEQ[7:0]

WD_EN

CRTL2

0

RESETBMCU PWRUP

PGOOD PWRUP

CTRL1

7:0

3

WD_DURATION[3:0]

WD_STBY_EN

WD CONFIG

CTRL1

3:0

2

WDI_STBY_ACTIVE

SW registers

CTRL1

1

SWx_WDBYPASS

SWx_PG_EN

SWx CONFIG1

SWx CONFIG2

SWx PWRUP

SWx MODE

1

0

SWxDVS_RAMP

SWxILIM[1:0]

5

4:3

2:0

7:0

5:4

3:2

1:0

7:0

6

SWxPHASE[2:0]

SWx_SEQ[7:0]

SWx_PDGRP[1:0]

SWx_STBY_MODE [1:0]

SWx RUN_MODE [1:0]

VSWx_RUN [7:0]

VSWx_STBY [7:0]

SW2_VTTEN

SWx MODE

SWx RUN VOLT

SWx STBY VOLT

SW2_CONFIG2

A soft WD reset may require all or some regulators to be reset to their default OTP

configuration. In the event a regulator is required to keep its current configuration

during a soft WD reset, a watchdog bypass bit is provided for each regulator

(SWx_WDBYPASS).

• When the WDBYPASS = 0, the watchdog bypass is disabled and the output of the

corresponding regulator is returned to its default OTP value during the soft WD reset.

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• When the WDBYPASS = 1, the watchdog bypass is enabled and the output of the

corresponding regulator is not affected by the soft WD reset, keeping its current

configuration.

During a soft WD reset, only regulators that are activated in the power up sequence go

back to their default voltage configuration if their corresponding WDBYPASS = 0.

Switching regulators returning to their default voltages configuration, will gradually reach

the new output voltage using its DVS configuration. Regulators with WDBYPASS = 0 and

which are not activated during the power up sequence will turn off immediately.

After all output voltages have transitioned to their corresponding default values, the

device waits for at least 30 μs before returning to the Run state and announces it has

finalized the soft WD reset by asserting the INTB pin, provided the WDI_I interrupt is not

masked.

Soft WD Reset Behavior

WDI Event

WDI OK

WDI Event

WDI OK

Regulator with

WDBYPASS = 1

Configuration Maintained

Not in Power

up Sequence

Default OTP Configuration

WDBYPASS = 0

In Power up

Sequence

RESETBMCU

INTB

30 µs

WDI_I Delay

Soft WD

reset

System ON

aaa-030056

Figure 29.ꢀSoft WD reset behavior

A hard WD reset is used to force a system power-on reset when the MCU has become

unresponsive. In this scenario, a full OTP register reset is performed.

During a hard WD reset, the device turns off all regulators and asserts RESETBMCU

as indicated by the power down sequence. If PGOOD is programmed as a GPO and

configured as part of the power up sequence, it will also be disabled accordingly.

After all regulator's outputs have gone through the power down sequence and the power

down delay is finished , the device waits for 30 µs before reloading the default OTP

configuration and get ready to start a power up sequence if the XFAILB pin is not held

low externally.

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Hard WD Reset Behavior

WD Event

WD OK

WD Event

WD OK

WD

Reset

Regulator

Outputs

Default OTP

RESETBMCU

30 µs

Power Down

Delay

System ON

Power Down

Sequence

Power Up

Sequence

aaa-030057

Figure 30.ꢀHard WD reset behavior

After a WD reset, the PMIC may enter the Standby state depending on the status of

STANDBY pin.

Every time a WD event occurs, the WD_EVENT_CNT[3:0] nibble is incremented.

To prevent continuous failures, if the WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0]

the state machine will proceed to the fail-safe transition. The MCU is expected to

clear the WD_EVENT_CNT[3:0] when it is able to do so in order to keep proper

operation. Upon power up, the WD_MAX_CNT[3:0] is loaded with the values on the

OTP_WD_MAX_CNT[3:0] bits.

Every time the device passes through the off states, the WD_EVENT_CNT[3:0] is reset

to 0x00, to ensure the counter has a fresh start after a device power down.

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WD_EVENT_CNT

0

reset by MCU

WD EVENT

1

WD EVENT

2

WD EVENT

WD_EVENT_CNT

reset by Fail-safe

Transition

3

WD EVENT

4

WD EVENT

5

WD EVENT

n =

WD_MAX

_CNT

FAIL-SAFE

TRANSITION

aaa-028075

Figure 31.ꢀWatchdog event counter

16 I²C register map

The PF5023 provides a complete set of registers for control and diagnostics of the PMIC

operation. The configuration of the device is done at two different levels.

At first level, the OTP mirror registers provide the default hardware and software

configuration for the PMIC upon power up. These are one-time programmable and

should be defined during the system development phase, and are not meant to be

modified during the application. See Section 17 "OTP/TBB and hardwire default

configurations" for the OTP configuration feature.

At a second level, the PF5023 provides a set of functional registers intended for

system configuration and diagnostics during the system operation. These registers are

accessible during the system On state and can be modified at any time by the system

control unit.

The device ID register provides general information about the PMIC:

• DEVICE_FAM[3:0]: indicates the PF50x0 family of devices.

0101 (fixed)

• DEVICE_ID[3:0]: provides the device type identifier

0011 = PF5023 QM

1011 = PF5023 ASIL B

Registers 0x02 and 0x03 provide a customizable program ID registers to identify the

specific OTP configuration programmed in the part.

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• EMREV (Address 0x02): contains the MSB bits PROG_ID[8:11]

• PROG_ID (Address 0x03): contains the LSB bit PROG_ID[7:0]

16.1 PF5023 OTP mirror register map

Reset types

OFF_OTP

OTP

Register loads the OTP mirror register values during power up

Register available in OTP bank only, Reset From fuses when VIN crosses UVDET threshold

MR

FUSE Register name BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

ADDR ADDR

A0

0

OTP I2C

—

OTP_I2C_

OTP_I2C_CRC_EN

OTP_I2C_ADD[2:0]

SECURE_EN

A1

A2

1

2

OTP CTRL1

OTP CTRL2

—

OTP_EWARN_TIME[1:0]

OTP_FS_BYPASS

OTP_STANDBYINV OTP_PG_ACTIVE

OTP_PG_CHECK

OTP_FSS_EN

OTP_FSS_RANGE

—

OTP_XFAILB_EN

OTP_VIN_OVLO_

SDWN

OTP_VIN_OVLO_

EN

OTP_VIN_OVLO_DBNC[1:0]

A3

A4

3

4

OTP CTRL3

OTP_VTT_PDOWN OTP_SW2_VTTEN

—

Reserved

OTP_SW1CONFIG[1:0]

OTP FREQ

CTRL

OTP_SW_MODE

OTP_SYNC_MODE OTP_SYNCOUT_

EN

OTP_FSYNC_

RANGE

OTP_CLK_FREQ[3:0]

A5

5

OTP PWRON

—

OTP_PWRON_

MODE

OTP_PWRON_DBNC[1:0]

OTP_PWRON_

RST_EN

OTP_TRESET[1:0]

A6

A7

A8

A9

AA

AB

AC

AD

AE

6

OTP WD

CONFIG

—

OTP_WDI_MODE

OTP_WDI_INV

—

OTP_WD_EN

—

OTP_ WD_STBY_

EN

OTP_WDI_STBY_

ACTIVE

OTP_WDWINDOW

7

OTP WD

EXPIRE

—

OTP_WD_MAX_EXPIRE[2:0]

8

OTP WD

COUNTER

OTP_WD_DURATION[3:0]

OTP_FS_MAX_CNT[3:0]

OTP_WD_MAX_CNT [3:0]

9

OTP FAULT

COUNTERS

OTP_FAULT_MAX_CNT[3:0]

OTP_TIMER_FAULT[3:0]

A

B

C

D

E

OTP FAULT

TIMERS

—

OTP_FS_OK_TIMER[2:0]

OTP PWRDN

DLY1

OTP_GRP4_DLY[1:0]

OTP_PD_SEQ_DLY[1:0]

OTP_GRP3_DLY[1:0]

—

OTP_GRP2_DLY[1:0]

—

OTP_GRP1_DLY[1:0]

OTP PWRDN

DLY2

—

OTP_RESETBMCU_DLY[1:0]

OTP_SEQ_TBASE[1:0]

OTP PWRUP

CTRL

—

OTP_PWRDWN_

MODE

OTP_PGOOD_PDGRP[1:0]

OTP_RESETBMCU_PDGRP[1:0]

OTP

OTP_RESETBMCU_SEQ[7:0]

RESETBMCU

PWRUP

AF

B0

B1

B2

B3

F

OTP PGOOD

PWRUP

OTP_PGOOD_SEQ[7:0]

OTP_VSW1[7:0]

10

11

12

13

OTP SW1

VOLT

OTP SW1

PWRUP

OTP_SW1_SEQ[7:0]

OTP SW1

CONFIG1

OTP_SW1UV_TH[1:0]

OTP_SW1OV_TH[1:0]

OTP_SW1_PDGRP[1:0]

OTP_SW1ILIM[1:0]

OTP SW1

CONFIG2

OTP_SW1_LSELECT[1:0]

OTP_SW1PHASE[2:0]

—

OTP_SW1_PG_EN

OTP_SW1_

WDBYPASS

B4

B5

B6

B7

B8

B9

BA

BB

14

15

16

17

18

19

1A

1B

OTP SW2

VOLT

OTP_VSW2[7:0]

OTP SW2

PWRUP

OTP_SW2_SEQ[7:0]

OTP SW2

CONFIG1

OTP_SW2UV_TH[1:0]

OTP_SW2OV_TH[1:0]

OTP_SW2_PDGRP[1:0]

—

OTP_SW2ILIM[1:0]

OTP SW2

CONFIG2

OTP_SW2_LSELECT[1:0]

OTP_SW2PHASE[2:0]

OTP_SW2_PG_EN

OTP_SW2_

WDBYPASS

OTP SW3_

VOLT

OTP_VSW3[7:0]

OTP SW3

PWRUP

OTP_SW3_SEQ[7:0]

OTP SW3

CONFIG1

OTP_SW3UV_TH[1:0]

OTP_SW3OV_TH[1:0]

OTP_SW3_PDGRP[1:0]

—

OTP_SW3ILIM[1:0]

OTP SW3

CONFIG2

OTP_SW3_LSELECT[1:0]

OTP_SW3PHASE[2:0]

OTP_SW3_PG_EN

OTP_SW3_

WDBYPASS

BC

1C

OTP SW4

VOLT

Reserved

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

MR

FUSE Register name BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

ADDR ADDR

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

OTP SW4

PWRUP

Reserved

OTP SW4

CONFIG1

Reserved

OTP SW4

CONFIG2

Reserved

—

Reserved

OTP SWND1_

VOLT

—

Reserved

OTP SWND1

PWRUP

Reserved

OTP SWND1

CONFIG1

Reserved

OTP SWND1

CONFIG2

Reserved

—

Reserved

OTP LDO1

VOLT

Reserved

OTP LDO1

PWRUP

Reserved

OTP LDO1

CONFIG

Reserved

—

Reserved

—

Reserved

OTP VSNVS

CONFIG

—

Reserved

—

Reserved

OTP_OV_

BYPASS1

—

Reserved

OTP_SW3_

OVBYPASS

OTP_SW2_

OVBYPASS

OTP_SW1_

OVBYPASS

OTP_OV_

BYPASS2

—

Reserved

OTP_UV_

BYPASS1

—

Reserved

—

Reserved

OTP_SW3_

UVBYPASS

OTP_SW2_

UVBYPASS

OTP_SW1_

UVBYPASS

OTP_UV_

BYPASS2

—

Reserved

OTP_ILIM_

BYPASS1

—

Reserved

—

Reserved

OTP_SW3_

ILIMBYPASS

OTP_SW2_

ILIMBYPASS

OTP_SW1_

ILIMBYPASS

OTP_ILIM_

BYPASS2

—

OTP_PROG_ID10

OTP_PROG_ID2

—

OTP_PROG_ID9

OTP_PROG_ID1

—

Reserved

OTP_PROG_

IDH

—

OTP_PROG_ID11

OTP_PROG_ID3

—

OTP_PROG_ID8

OTP_PROG_ID0

BGMON_BYPASS

OTP_PROG_

IDL

OTP_PROG_ID7

OTP_PROG_ID6

OTP_PROG_ID5

—

OTP_PROG_ID4

—

D0

D1

30

31

OTP DEBUG1

—

OTP SW

COMP1

OTP_SW2_GM_COMP[2:0]

OTP_SW1_GM_COMP[2:0]

OTP_SW3_GM_COMP[2:0]

—

D2

D3

32

33

OTP SW

COMP2

—

Reserved

—

OTP SW

COMP3

Reserved

—

D4

D5

34

35

OTP SW RAMP

Reserved

OTP_SW3DVS_RAMP[1:0]

OTP_SW2DVS_RAMP[1:0]

OTP_SW1DVS_RAMP[1:0]

OTP_S0_CRC_

LSB

OTP_S0_CRC_LSB[7:0]

D6

36

OTP_SO_

CRC_MSB

OTP_SO_CRC_MSB[7:0]

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

16.2 PF5023 functional register map

RESET Signals

R/W types

Default values

UVDET

Reset when VIN crosses UVDET threshold

Bits are loaded with OTP values (mirror register)

Reset when device goes to OFF mode

Self-clear after write

R

Read only

1

0

x

bit set on reset

OFF_OTP

OFF_TOGGLE

SC

R/W

Read and Write

bit cleared on reset

unknown state

RW1C

R/SW

R/TW

Read, Write a 1 to clear

Read/Secure Write

Read/Write on TBB only

F

T

loaded from OTP fuse

Hard coded

AD Register name

DR

R/W

Default

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

00

01

02

03

04

05

06

07

08

09

0A

0B

DEVICE ID

REV ID

R

0101_TTTT

TTTT_TTTT

FFFF_TTTT

FFFF_FFFF

0000_0000

1111_1011

0000_00xx

0000_0000

1111_1111

xxxx_xxxx

DEVICE_FAM[3:0]

FULL_LAYER_REV[3:0]

PROG_ID[11:8]

DEVICE_ID[3:0]

METAL_LAYER_REV[3:0]

EMREV[2:0]

R

EMREV

R

—

PROG ID

R

PROG_ID[7:0]

INT STATUS1

INT MASK1

INT SENSE1

INT STATUS2

INT MASK2

INT SENSE2

SW MODE INT

RW1C

R/W

R

SDWN_I

SDWN_M

—

FREQ_RDY_I

FREQ_RDY_M

—

CRC_I

PWRUP_I

PWRUP_M

—

PWRDN_I

PWRDN_M

—

PGOOD_I

VIN_OVLO_I

VIN_OVLO_M

VIN_OVLO_S

THERM_80_I

THERM_80_M

THERM_80_S

SW1_MODE_I

SW1_MODE_M

CRC_M

—

PGOOD_M

—

PGOOD_S

RW1C

R/W

R

WDI_I

WDI_M

WDI_S

—

FSYNC_FLT_I

FSYNC_FLT_M

FSYNC_FLT_S

Reserved

THERM_155_I

THERM_155_M

THERM_155_S

—

THERM_140_I

THERM_140_M

THERM_140_S

—

THERM_125_I

THERM_125_M

THERM_125_S

Reserved

THERM_110_I

THERM_110_M

THERM_110_S

SW3_MODE_I

SW3_MODE_M

THERM_95_I

THERM_95_M

THERM_95_S

SW2_MODE_I

SW2_MODE_M

RW1C

R/W

0000_0000

0100_1111

SW MODE

MASK

—

Reserved

—

Reserved

0C

0D

0E

SW ILIM INT

RW1C

0000_0000

0100_1111

0x00_00xx

—

Reserved

—

Reserved

SW3_ILIM_I

SW3_ILIM_M

SW3_ILIM_S

SW2_ILIM_I

SW2_ILIM_M

SW2_ILIM_S

SW1_ILIM_I

SW1_ILIM_M

SW1_ILIM_S

SW ILIM MASK R/W

SW ILIM

SENSE

R

0F

10

LDO ILIM INT

RW1C

R/W

0000_0000

0000_0001

—

Reserved

LDO ILIM

MASK

11

LDO ILIM

SENSE

R

0000_000x

—

Reserved

12

13

14

15

16

17

18

19

1A

SW UV INT

RW1C

R/W

R

0000_0000

0100_1111

0x00_00xx

0000_0000

0100_1111

0x00_00xx

0000_0000

0000_0001

0000_000x

—

Reserved

—

Reserved

—

SW3_UV_I

SW3_UV_M

SW3_UV_S

SW3_OV_I

SW3_OV_M

SW3_OV_S

—

SW2_UV_I

SW2_UV_M

SW2_UV_S

SW2_OV_I

SW2_OV_M

SW2_OV_S

—

SW1_UV_I

SW1_UV_M

SW1_UV_S

SW1_OV_I

SW1_OV_M

SW1_OV_S

Reserved

SW UV MASK

SW UV SENSE

SW OV INT

RW1C

R/W

R

SW OV MASK

SW OV SENSE

LDO UV INT

RW1C

R/W

R

LDO UV MASK

—

Reserved

LDO UV

SENSE

—

Reserved

1B

1C

1D

LDO OV INT

RW1C

R/W

R

0000_0000

0000_0001

0000_000x

—

Reserved

LDO OV MASK

LDO OV

SENSE

1E

1F

PWRON INT

RW1C

0000_0000

1111_1111

BGMON_I

PWRON_8S_I

PWRON_8S_M

PWRON_4S_I

PWRON_4S_M

PRON_3S_I

PWRON_2S_I

PWRON_2S_M

PWRON_1S_I

PWRON_1S_M

PWRON_REL_I

PWRON_REL_M

PWRON_PUSH_I

PWRON MASK R/W

BGMON_M

PRON_3S_M

PWRON_PUSH_

M

20

PWRON

SENSE

R

x000_000x

BGMON_S

—

PWRON_S

21

22

23

EN SENSE

SYS INT

R

0000_xxxx

0000_0000

—

EWARN_I

—

PWRON_I

—

OV_I

—

UV_I

Reserved

ILIM_I

EN3_S

EN2_S

EN1_S

R

MODE_I

WD_FAIL

STATUS2_I

REG_FAIL

STATUS1_I

TSD_FAIL

HARDFAULT

FLAGS

RW1C

—

PU_FAIL

24

25

ABIST PGOOD

MON

R/SW

0000_0000

—

AB_PGOOD_

MON

26

27

ABIST OV1

ABIST OV2

R/SW

0000_0000

—

Reserved

—

Reserved

—

AB_SW3_OV

—

AB_SW2_OV

—

AB_SW1_OV

Reserved

PF5023

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

AD Register name

DR

R/W

Default

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

28

29

2A

2B

2C

2D

2E

2F

30

31

ABIST UV1

ABIST UV2

TEST FLAGS

ABIST RUN

R/SW

R/TW

R/SW

0000_0000

—

Reserved

—

Reserved

AB_SW3_UV

AB_SW2_UV

AB_SW1_UV

Reserved

—

STEST_NOK

—

TRIM_NOK

—

OTP_NOK

AB_RUN

RANDOM GEN

RANDOM CHK

VMONEN1

VMONEN2

CTRL1

R

xxxx_xxxx

0000_0000

0100_1111

0000_0001

FFF1_FFFF

RANDOM_GEN[7:0]

RANDOM_CHK[7:0]

Reserved

R/W

R/SW

—

Reserved

—

SW3VMON_EN

—

SW2VMON_EN

—

SW1VMON_EN

Reserved

—

VIN_OVLO_EN

VIN_OVLO_

SDWN

WDI_MODE

TMP_MON_EN

WD_EN

WD_STBY_EN

WDI_STBY_

ACTIVE

I2C_SECURE_EN

32

33

34

CTRL2

R/W

FF01_0FFF

0010_0000

0FFF_FFFF

VIN_OVLO_DBNC[1:0]

OV_DB[1:0]

—

TMP_MON_AON

LPM_OFF

—

STANDBYINV

—

RUN_PG_GPO

PMIC_OFF

STBY_PG_GPO

INTB_TEST

CTRL3

UV_DB[1:0]

PGOOD_PDGRP[1:0]

PWRUP CTRL

—

PWRDWN_

MODE

RESETBMCU_PDGRP[1:0]

SEQ_TBASE[1:0]

35

36

RESETBMCU

PWRUP

R/W

FFFF_FFFF

RESETBMCU_SEQ[7:0]

37

PGOOD

PWRUP

PGOOD_SEQ[7:0]

38

39

3A

3B

3C

PWRDN DLY1

PWRDN DLY2

FREQ CTRL

R/W

FFFF_FFFF

0000_00FF

FFFF_FFFF

GRP4_DLY[1:0]

GRP3_DLY[1:0]

GRP2_DLY[1:0]

GRP1_DLY[1:0]

—

RESETBMCU_DLY[1:0]

SYNCOUT_EN

FSYNC_RANGE

FSS_EN

FSS_RANGE

CLK_FREQ[3:0]

PWRON

R/W

000F_FFFF

0000_FFFF

—

PWRON_DBNC [1:0]

PWRON_RST_

EN

TRESET[1:0]

3D

3E

3F

40

41

WD CONFIG

WD CLEAR

—

WD_DURATION[3:0]

R/W1C 0000_0000

—

WD_CLEAR

WD EXPIRE

WD COUNTER

R/W

0FFF_0000

FFFF_0000

WD_MAX_EXPIRE[2:0]

WD_EXPIRE_CNT[2:0]

WD_MAX_CNT[3:0]

FAULT_MAX_CNT[3:0]

WD_EVENT_CNT [3:0]

FAULT_CNT [3:0]

FAULT

COUNTER

42

FSAFE

COUNTER

R/W

0000_0000

—

FS_CNT [3:0]

43

44

45

46

47

FAULT TIMERS R/W

0000_FFFF

0000_0000

—

TIMER_FAULT[3:0]

AMUX

R/W

AMUX_EN

AMUX_SEL[4:0]

SW RAMP

R/W

FFFF_FFFF

FFF1_11FF

Reserved

SW3DVS_RAMP[1:0]

SW2DVS_RAMP[1:0]

SW1DVS_RAMP[1:0]

SW1_PG_EN

SW1 CONFIG1

SW1_UV_

BYPASS

SW1_OV_

BYPASS

SW1_ILIM_

BYPASS

SW1_UV_STATE SW1_OV_STATE SW1_ILIM_

STATE

SW1_

WDBYPASS

48

49

4A

4B

SW1 CONFIG2

SW1 PWRUP

SW1 MODE

R/W

10FF_FFFF

FFFF_FFFF

00FF_FFFF

FFFF_FFFF

SW1_FLT_REN

—

SW1ILIM[1:0]

SW1PHASE[2:0]

SW1_SEQ[7:0]

—

SW1_PDGRP[1:0]

SW1_STBY_MODE[1:0]

SW1_RUN_MODE[1:0]

SW1 RUN

VOLT

VSW1_RUN[7:0]

4C

SW1 STBY

VOLT

R/W

FFFF_FFFF

VSW1_STBY[7:0]

4D

4E

4F

SW2 CONFIG1

R/W

FFF1_11FF

SW2_UV_

BYPASS

SW2_OV_

BYPASS

SW2_ILIM_

BYPASS

SW2_UV_STATE SW2_OV_STATE SW2_ILIM_

STATE

SW2_

SW2_PG_EN

WDBYPASS

50

51

52

53

SW2 CONFIG2

SW2 PWRUP

SW2 MODE1

R/W

1FFF_FFFF

FFFF_FFFF

00FF_FFFF

FFFF_FFFF

SW2_FLT_REN

SW2_VTTEN

—

SW2ILIM[1:0]

SW2PHASE[2:0]

SW2_SEQ[7:0]

—

SW2_PDGRP[1:0]

SW2_STBY_MODE[1:0]

SW2_RUN_MODE[1:0]

SW2 RUN

VOLT

VSW2_RUN[7:0]

54

SW2 STBY

VOLT

R/W

FFFF_FFFF

VSW2_STBY[7:0]

55

56

57

SW3 CONFIG1

R/W

FFF1_11FF

SW3_UV_

BYPASS

SW3_OV_

BYPASS

SW3_ILIM_

BYPASS

SW3_UV_STATE SW3_OV_STATE SW3_ILIM_

STATE

SW3_

SW3_PG_EN

WDBYPASS

58

59

5A

SW3 CONFIG2

SW3 PWRUP

SW3 MODE

R/W

10FF_FFFF

FFFF_FFFF

00FF_FFFF

SW3_FLT_REN

—

SW3ILIM[1:0]

SW3PHASE[2:0]

SW3_SEQ[7:0]

—

SW3_PDGRP[1:0]

SW3_STBY_MODE[1:0]

SW3_RUN_MODE[1:0]

72 / 91

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

AD Register name

DR

R/W

Default

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

5B

SW3 RUN

VOLT

FFFF_FFFF

VSW3_RUN[7:0]

VSW3_STBY[7:0]

5C

SW3 STBY

VOLT

5D

5E

5F

60

61

62

63

SW4 CONFIG1

SW4 CONFIG2

SW4 PWRUP

SW4 MODE

R/W

FFF1_11FF

10FF_FFFF

FFFF_FFFF

00FF_FFFF

FFFF_FFFF

Reserved

—

Reserved

—

Reserved

SW4 RUN

VOLT

Reserved

64

SW4 STBY

VOLT

R/W

FFFF_FFFF

65

66

67

SWND1

CONFIG1

R/W

FFF1_11FF

100F_FFFF

FFFF_FFFF

00FF_FFFF

000F_FFFF

Reserved

68

69

6A

6B

SWND1

CONFIG2

—

Reserved

SWND1

PWRUP

Reserved

SWND1

MODE1

—

Reserved

SWND1 RUN

VOLT

—

Reserved

6C

6D

6E

6F

70

71

LDO1 CONFIG1 R/W

LDO1 CONFIG2 R/W

FFF1_11FF

1FF0_00FF

FFFF_FFFF

0000_FFFF

Reserved

—

LDO1 PWRUP

R/W

Reserved

LDO1 RUN

VOLT

—

Reserved

72

LDO1 STBY

VOLT

R/W

0000_FFFF

—

Reserved

73

74

75

VSNVS

0000_00FF

0000_0000

—

Reserved

CONFIG1

76

77

PAGE SELECT R/TW

PAGE[2:0]

17 OTP/TBB and hardwire default configurations

The PF5023 supports OTP fuse bank configuration and a predefined hardwire

configuration to select the default power up configuration via the VDDOTP pin.

The default power up configuration is loaded into the functional I²C registers based on

the voltage on VDDOTP pin on register loading.

• If VDDOTP = GND, the device loads the configuration from the OTP mirror registers.

• If VDDOTP = V1P5D, the device loads the configuration from the default hardwire

configuration.

When OTP configuration is selected, the register loading occurs in two stages:

• In the first stage, the fuses are loaded in the OTP mirror registers each time VIN

crosses the UVDET threshold in the rising edge.

• At the second stage, the data from the mirror registers are loaded into the functional

I²C registers for device operation.

When VDDOTP = GND, the mirror registers hold the default configuration to be used on

a power-on event. The mirror registers can be modified during the TBB mode in order to

PF5023

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Product data sheet

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NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

test a custom power up configuration and/or burn the configuration into the OTP fuses to

generate a customized default power up configuration.

When VDDOTP = V1P5D, the I²C functional register will always be loaded from the

hardwire configuration each time a default loading is required. Therefore, no TBB

operation is possible in this configuration.

In the event of a TRIM/OTP loading failure or a self-test failure, the corresponding fault

flag is set and any PWRUP event is ignored until the flags are cleared by writing a 1

during the QPU_OFF state.

The TRIM_NOK, OTP_NOK and STEST_NOK flags can only be written when the

TBBEN = V1P5D (in TBB mode). In normal operation, the TRIM_NOK, OTP_NOK and

STEST_NOK flags can only be read, but not cleared.

17.1 TBB (Try Before Buy) operation

The PF5023 allows temporary configuration (TBB) to debug or test a customized power

up configuration in the system. In order to access the TBB mode, the TBBEN pin should

be pulled up to V1P5D.

In this mode of operation, the device ignores the default value of the LPM_OFF bit and

moves into the QPU_Off state, regardless of the result of the self-test. However, the

actual result of the self-test is notified by the STEST_NOK flag.

• When the self-test is successful the STEST_NOK flag is set to 0.

• When the self-test has failed, the STEST_NOK flag is set to 1.

In the TBB mode, the following conditions are valid:

• I²C communication uses standard communication with no CRC and secure write

disabled.

• Default I²C address is 0x08 regardless of the address configured by OTP.

• Watchdog monitoring is disabled (including WDI and internal watchdog timer).

• The PF5023 can communicate through I²C as long as V_DDIOis provided to the PMIC

externally.

The PAGE[2:0] bits are provided to grant access to the mirror registers and other OTP

dedicated bits. When the device is in the TBB mode, it can access the mirror registers

in the extended register Page 1. With the TBBEN pin pulled low, access to the extended

register pages is not allowed.

The mirror registers are preloaded with the values from the OTP configuration. These

may be modified to set the proper power up configuration during TBB operation.

If a power up event is present with the TBBEN pin pulled to V1P5D, the device will power

up with the proper configuration but limited functionality.

Limited functionality includes:

• Default I²C address = 0x08

• CRC and secure write disabled

• Watchdog operation/monitoring disable

In order to allow TBB operation with full functionality, the TBBEN pin must be low when

the power up event occurs.

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

74 / 91

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

The PF5023 can operate normally using the TBB configuration, as long as VIN does not

go below the UVDET threshold. If VIN is lost (VIN < UVDET) the mirror register will be

reset and TBB configuration must be performed again.

Vin > UVDET

FUSE LOAD

Hardwire

Config

OTP

Config

VDDOTP = 0v

2

I C Register

Mirror

Map

Registers

TBB Default

Configuration

TBBEN = V1P5D

LP_Off

Self-Test

QPU_Off

2

I C Register

Map

Modified TBB

Configuration

2

l C

Mirror

Registers

POWER OFF

Mirror

Registers

Power On

Event

2

TBB Power up

Configuration

l C Register

Map

lf TBBEN = V1P5D

(Limited Functionality)

POWER UP

lf TBBEN = GND

(Full Functionality)

SYSTEM ON

aaa-028076

Figure 32.ꢀTBB operation diagram

17.2 OTP fuse programming

A permanent OTP configuration is possible by burning the OTP fuses. OTP fuse

burning is performed in the TBBEN mode during the QPU_Off state. Contact your NXP

representative for detailed information on OTP fuse programming.

PF5023

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Product data sheet

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17.3 Default hardwire configuration

If VDDOTP = V1P5D, the device loads the configuration from the default hardwire

configuration directly into the corresponding I²C functional registers each time the

registers need to be reloaded.

When using the hardwire configuration, the TRIM values are still loaded from the OTP

fuses. In the event of a TRIM loading failure, the corresponding fault flag is set to 1.

When the hardwire configuration is used, the PF5023 does not allow TBB mode

operation. When TBBEN = V1P5D, the device enters a debug mode. In this mode of

operation, the device ignores the default value of the LPM_OFF bit and moves into the

QPU_Off state, regardless of the result of the self-test. However, the actual result of the

self-test is notified by the STEST_NOK flag.

• When the self-test is successful, the STEST_NOK flag is set to 0

• When the self-test has failed, the STEST_NOK flag is set to 1

During hardwire configuration, the OTP_NOK flag is always set to 0.

When any of the TRIM_NOK, OTP_NOK or STEST_NOK flags are set, any PWRUP

event is ignored until the flags are cleared by writing a 0. These flags can only be written

when the system is in the debug mode, (TBBEN = V1P5D). In normal operation, the

TRIM_NOK, OTP_NOK and STEST_NOK flags are read only.

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Power management integrated circuit (PMIC) for high performance applications

Vin > UVDET

FUSE LOAD

Default

Config

OTP

Config

VDDOTP = V1P5D

2

I C Register

Map

Mirror

Registers

TBB Default

Configuration

TBBEN = V1P5D

· WDI disabled

LP_Off

· Watchdog Disabled

2

· l C CRC disabled

PWRON

event

2

· l C Address = 0x08

· Access Miscellaneous

Debug flags

Self-Test

QPU_Off

2

I C Register

Map

Mirror

Registers

POWER OFF

PWRON

event

Hardwire

Power up Configuration

2

I C Register

Map

POWER UP

SYSTEM ON

lf TBBEN = V1P5D

(Limited Functionality)

lf TBBEN = GND

(Full Functionality)

aaa-028077

Figure 33.ꢀHardwire operation diagram

For simplicity, the default hardwire configuration in PF5023 is organized based on the

OTP register map as shown in Table 57.

Table 57.ꢀDefault hardwire configuration

ADDR

Register Name

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Configuration

A0

OTP I2C

0

Secured I2C disabled | I2C CRC disabled | I2C address =

0x08

A1

OTP CTRL1

OTP CTRL2

0

1

0

EWARN_TIME=100 µs | Fail-safe state enabled |

STANDBY active high | PGOOD indicator | RESETBMCU

is not influenced by power-up

A2

0

1

0

1

XFAIL = disabled | VIN_OVLO shutdown disabled | VIN_

OVLO enabled | VIN_OVLO debounce = 100 µs

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ADDR

Register Name

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Configuration

A3

OTP CTRL3

0

1

VTT pull down enabled | Single phase: SW3 | Dual phase:

SW1/SW2

A4

OTP FREQ CTRL

0

SYNCIN = Disabled | SYNCOUT disabled | SYNCIN range

= 2 MHz to 3 MHz | CLK frequency = 2.5 MHz

A5

A6

OTP PWRON

0

1

0

PWRON = Level sensitive

OTP WD CONFIG

WDI generates soft WD Reset | WDI detect on rising edge

| WD timer disabled | WD timer in Standby disabled |WDI

detect in Standby disabled | WD Windows = 100 %

A7

A8

A9

OTP WD EXPIRE

0

1

0

1

0

1

0

1

0

1

Max WD Expire count = 8

OTP WD COUNTER

WD Duration = 1024 ms | Max WD count = 16

OTP FAULT

COUNTERS

Fail-safe MAX counter = 16 | Regulator Fault Max Counter

= 16

AA

AB

OTP FAULT

TIMERS

0

1

0

1

0

1

0

1

0

Fail-safe OK timer = 1 minute | Regulator Fault timer =

Disabled

OTP PWRDN DLY1

GRP4 delay = 125 µs | GRP 3 delay = 125 µs | GRP 2

delay = 125 µs | GRP 1 delay = 125 µs

AC

AD

OTP PWRDN DLY2

OTP PWRUP CTRL

0

1

0

Power Down Delay = 0 | RESETBMCU delay = 10 µs

PD Mirror Sequence | RESETBMCU PD Group2 | TBASE

= 250 µs

AE

AF

OTP RESETBMCU

PWRUP

0

1

0

1

0

1

0

RESETBMCU SEQ = Slot 6 (TBASE x 6 = 1500 µs)

OTP PGOOD

PWRUP

PGOOD SEQ = OFF

B0

B1

B2

OTP SW1 VOLT

0

1

0

1

0

1

0

1

0

1

Voltage = 1.0 V

SEQ = Slot 0

OTP SW1 PWRUP

OTP SW1 CONFIG1

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min

3.1 A

B3

OTP SW1 CONFIG2

0

1

0

L = 1 µH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN

| WDBYPASS = Disable

B4

B5

B6

OTP SW2 VOLT

0

1

0

1

0

1

0

1

0

1

Voltage = 1.0 V

SEQ = Slot 0

OTP SW2 PWRUP

OTP SW2 CONFIG1

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min

3.1 A

B7

OTP SW2 CONFIG2

0

1

0

L = 1 µH | Phase = 180º | DVS Ramp = 12.5 mV/µs | PG =

EN | WDBYPASS = Disabled

B8

B9

BA

OTP SW3_VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Voltage = 1.1 V

OTP SW3 PWRUP

OTP SW3 CONFIG1

SEQ = Slot 4 (TBASE x 4 = 1000 µs)

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min

3.1 A

BB

OTP SW3 CONFIG2

0

1

0

L = 1 µH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN

| WDBYPASS = Disable

BC

BD

BE

OTP SW4 VOLT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Voltage = 1.1 V

OTP SW4 PWRUP

OTP SW4 CONFIG1

SEQ = Slot 4 (TBASE x 4 = 1000 µs)

UV mon = 7 % | OV mon = 7 % | SW PD Group4 | ILIM min

3.1 A

BF

OTP SW4 CONFIG2

0

1

0

L = 1 µH | Phase = 0º | DVS Ramp = 12.5 mV/µs | PG = EN

| WDBYPASS = Disable

C8

CA

CC

OTP_OV_BYPASS1

OTP_UV_BYPASS1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SWx OVBYPASS disabled

SWx UVBYPASS disabled

SWx ILIMBYPASS Enabled

OTP_ILIM_

BYPASS1

CE

CF

OTP_PROG_IDH

OTP_PROF_IDL

0

1

0

1

0

1

0

1

Default Program ID high Nibble = 0x0F

Default Program ID low Byte = 0xFF

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ADDR

D0

Register Name

OTP DEBUG1

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Configuration

0

BG Monitor Disabled

SW2 = 65GM | SW1 = 65GM

SW3 = 65GM

D1

OTP SW COMP1

OTP SW COMP2

D2

18 Functional safety

18.1 System safety strategy

The PF5023 is defined in a context of safety and shall provide a set of features to

achieve the safety goals on such context. It provides a flexible yet complete safety

architecture to comply with ASIL B systems providing full programmability to enable

or disable features to address the safety goal. This architecture includes protective

mechanisms to avoid unwanted modification on the respective safety features, as

required by the system.

The following are features considered to be critical for the functional safety strategy:

• Internal watchdog timer

• External watchdog monitoring input (WDI)

• Output voltage monitoring with dedicated bandgap reference

• Protected I²C protocol with CRC verification

• Input overvoltage protection

• Analog built-in self-test (ABIST)

18.2 Output voltage monitoring with dedicated bandgap reference

For the type 1 buck regulators, the OV/UV monitor operate from the same reference

as the regulator. To ensure the integrity of the type 1 buck regulators, a comparison

between the regulator bandgap and the monitoring bandgap is performed. A 5 % to

12 % difference between the two bandgaps is an indicator of a potential regulation or

monitoring fault and is considered as a critical issue. Therefore, the device prevents the

switching regulators from powering up.

On the PF5023 ASIL B device, if a bandgap error is detected during a power up event,

the self-test will fail and prevent the device from powering up regardless of the value of

the OTP_BGMON_BYPASS bit.

During system On state, if a drift between two bandgaps is detected:

• When OTP_BGMON_BYPASS = 0, the power stage of the voltage regulators will be

shutdown.

• When OTP_BGMON_BYPASS = 1, The bandgap monitor only sends an interrupt to

the system to announce the bandgap failure.

The BGMON_I is asserted when a bandgap failure occurs, provided it is not masked.

The BGMON_S bit is set to 0 when the bandgaps are within range, and set to 1 when the

bandgaps are out of range.

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18.3 ABIST verification

The PF5023 ASIL B implements an ABIST verification of all output voltage monitors as

well as PGOOD pin. The ABIST verification on the output voltage monitoring behaves as

follows:

• Device tests the OV comparators for each individual SWx supply during the self-test

routine

• Device tests the UV comparators for each individual SWx supply during the self-test

routine

• During the ABIST verification, it is required to ensure the corresponding OV/UV

comparators are able to toggle, which in turn is a sign of the integrity of these functions

• If any of the comparators is not able to toggle, a warning bit is set on the I²C register

map.

– The ABIST_OV1 register contains the AB_SWx_OV bits for all external regulators.

– The ABIST_UV1 register contains the AB_SWx_UV bits for all external regulators.

• The ABIST registers are cleared or overwritten each time the ABIST check is

performed.

• The ABIST registers are part of the secure registers and will require an I²C secure write

to be cleared if this feature is enabled.

Once ABIST check is performed, the PF5023 can proceed with the power up sequence

and the MCU should be able to request the value of these registers and learn if ABIST

failed for any of the voltage monitors.

The AB_RUN bit is provided to perform an ABIST verification on demand.

When the AB_RUN bit is set to 1, the control logic perform an ABIST verification on all

OV/UV monitoring circuits. When the ABIST verification is finished, the AB_RUN bit self-

clear to 0 and a new ABIST verification can be commanded as needed.

When the secure write feature is enabled, the system must perform a secure write

sequence in order to start an ABIST verification on demand.

When the PF5023 performs an ABIST verification on demand, the OV/UV fault

monitoring is blanked for a maximum period of 200 µs. During this time, the system must

ensure it is in a safe state, or it is safe to perform this action without violating the safety

goals of the system.

If a failure on the OV/UV monitor is detected during the ABIST on demand request,

the PMIC will assert the corresponding ABIST flags. It is responsibility of the system to

perform a diagnostic check after each ABIST verification to ensure it places the system in

safe state if an ABIST fault is detected.

19 IC level quiescent current requirements

Table 58.ꢀQuiescent current requirements

All parameters are specified at T_A= −40 to 125 °C, unless otherwise noted. Typical values are characterized at V_IN= 5.0 V

and T_A= 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

I_LPOFF

LP_Off state

µA

LPM_OFF = 0

VIN > UVDET

—

40

150

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Symbol

Parameter

Min

Typ

Max

Unit

I_QPUOFF

QPU_Off

µA

LPM_OFF = 1

—

750

1000

System ready to power on

I_SYSON

System On core current

µA

Run or standby and all regulators disabled

Coin cell charger disabled

AMUX disabled

—

750

40

1000

150

I_FSAFE

Fail-safe mode

VIN > UVDET

20 Typical applications

100 kΩ

3

FAIL-SAFE

CONTROL

3

ENx

WATCHDOG

MONITORING

ENx

STATUS FLG

from MCU

PF5023

PGOOD

MONITOR

LOGIC

CONTROL

VDDOTP

TBBEN

ABIST

WD TIMER

PGOOD

SW1

OV/UV

MONITOR

2

FUSE CRC

VERIFICATION

SW1FB

I C CONTROL

VSW1

I/O supply

VDDIO

2 x 22 µF

1 µH

MIRROR

SW1LX

SW1IN

(SWx/LDOx)

ABIST

REGISTERS

2.2 kΩ

OTP/

TRIM

MEMORY

SCL

SDA

TEMP SENSE

SW1

I2C CLK

VIN

FUNCTIONAL

REGISTERS

4.7 µF

I2C CRC

I2C DATA

SW2

OV/UV

MONITOR

SW2FB

SW2LX

VSW2

Syncin

CLOCK MANAGEMENT

2 x 22 µF

1 µH

100 KH CLOCK

20 MHz CLOCK +/-25 %

SPREAD SPECTRUM

SYNC

MUX

sync CLK

ABIST

Syncout

CLOCK SYNCHRONIZATION

SW2IN

TEMP SENSE

SW2

VIN

20 MHz OSC DIAGNOSTIC

4.7 µF

V1P5A POR

V1P5A

BANDGAP

COMPARATOR

SW3

OV/UV

MONITOR

V1P5A

GND

SW3FB

SW3LX

V1P5A

1.0 µF

VSW3

THERMAL

MONITOR

2 x 22 µF

1 µH

ABIST

BG2

BG1

V1P5D POR

V1P5D

SW3IN

TEMP

SENSE MAIN

TEMP SENSE

SW3

V1P5D

VIN

V1P5D

1.0 µF

IREF 2

IREF 1

4.7 µF

VIN OVLO

VIN

1.0 µF

UVDET

EP

functional block

functional safety block

aaa-032242

Figure 34.ꢀTypical application diagram

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21 Package outline

Figure 35.ꢀPackage outline for HVQFN40 (SOT618-14)

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Figure 36.ꢀPackage outline detail for HVQFN40 (SOT618-14)

Figure 37.ꢀSolder mask pattern for HVQFN40 (SOT618-14)

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PF5023

Power management integrated circuit (PMIC) for high performance applications

Figure 38.ꢀI/O pads and solderable areas for HVQFN40 (SOT618-14)

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Figure 39.ꢀSolder paste stencil for HVQFN40 (SOT618-14)

Figure 40.ꢀPackage outline notes for HVQFN40 (SOT618-14)

PF5023

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22 Revision history

Table 59.ꢀRevision history

Document ID

Release date

20200415

Data sheet status

Change notice

Supersedes

PF5023 v.1.0

Product data sheet

—

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23 Legal information

23.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

23.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

23.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

23.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

I²C-bus — logo is a trademark of NXP B.V.

NXP — is a trademark of NXP B.V.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

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Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Ordering information ..........................................2

Pin description ...................................................4

Absolute maximum ratings ................................5

ESD ratings .......................................................5

Thermal characteristics ..................................... 6

QFN40 thermal resistance and package

dissipation ratings ............................................. 6

Operating conditions ......................................... 6

Voltage supply summary ...................................8

Device differences .............................................8

Tab. 29. TRESET configuration .....................................36

Tab. 30. Standby pin polarity control .............................36

Tab. 31. PGOODx assignment ......................................39

Tab. 32. ENx assignment .............................................. 39

Tab. 33. I2C address configuration ............................... 43

Tab. 34. Secure bits ...................................................... 44

Tab. 35. Internal supplies electrical characteristics ....... 45

Tab. 36. SWx ramp rates .............................................. 46

Tab. 37. SWx output voltage configuration ....................47

Tab. 38. SWx regulator mode configuration ..................47

Tab. 39. SWx current limit selection ..............................48

Tab. 40. SWx phase configuration ................................ 48

Tab. 41. SWx inductor selection bits .............................48

Tab. 42. OTP_SW1CONFIG register description .......... 49

Tab. 7.

Tab. 8.

Tab. 9.

Tab. 10. State machine transition definition .................. 10

Tab. 11. Fail-safe OK timer configuration ......................16

Tab. 12. UVDET threshold ............................................ 17

Tab. 13. VIN_OVLO debounce configuration ................ 17

Tab. 14. VIN_OVLO specifications ................................18

Tab. 15. Startup timing requirements (PWRON pulled

up) ................................................................... 18

Tab. 43. Type

1

buck

regulator

electrical

characteristics ..................................................49

Tab. 44. Recommended external components ..............52

Tab. 45. UV threshold configuration register .................52

Tab. 46. OV threshold configuration register .................52

Tab. 47. UV debounce timer configuration ....................52

Tab. 48. OV debounce timer configuration ....................53

Tab. 49. VMON electrical characteristics ...................... 54

Tab. 50. Manual frequency tuning configuration ............56

Tab. 51. Clock management specifications ...................59

Tab. 52. Thermal monitor specifications ........................61

Tab. 53. Thermal monitor bit description .......................61

Tab. 54. AMUX channel selection .................................62

Tab. 55. Watchdog duration register ............................. 63

Tab. 56. Soft WD register reset .....................................65

Tab. 57. Default hardwire configuration .........................77

Tab. 58. Quiescent current requirements ......................80

Tab. 59. Revision history ...............................................86

Tab. 16. Startup with PWRON driven high externally

and LPM_OFF = 0 ..........................................19

Tab. 17. Power up time base register ........................... 20

Tab. 18. Power up sequence registers ..........................21

Tab. 19. Power down regulator group bits .................... 24

Tab. 20. Power down counter delay ..............................24

Tab. 21. Programmable delay after RESETBMCU is

asserted ...........................................................24

Tab. 22. Power down delay selection ............................25

Tab. 23. Regulator control during fault event bits ..........26

Tab. 24. Fault timer register configuration .....................29

Tab. 25. Fault bypass bits .............................................29

Tab. 26. Interrupt registers ............................................ 33

Tab. 27. I/O electrical specifications ..............................34

Tab. 28. PWRON debounce configuration in edge

detection mode ................................................35

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 6.

Fig. 7.

Simplified application diagram ...........................2

Internal block diagram .......................................3

Pin configuration for 40-pin QFN .......................4

Functional block diagram .................................. 7

State diagram ....................................................9

Startup with PWRON pulled up .......................18

Startup with PWRON driven high externally

and bit LPM_OFF = 0 ..................................... 19

Power up/down sequence between Off and

system On state ..............................................21

Power up/down sequence between run and

standby ............................................................22

Fig. 15. Power up sequencer with a temporary failure .. 31

Fig. 16. Power up sequencer aborted as fault

persists for longer than 2.0 ms ........................32

Fig. 17. I/O interface diagram .......................................34

Fig. 18. XFAILB behavior during

a power up

sequence .........................................................41

Fig. 19. XFAILB behavior during a power down

sequence .........................................................41

Fig. 20. Behavior during an external XFAILB event ......42

Fig. 21. External XFAILB event during a power up

sequence .........................................................42

Fig. 22. 8 bit SAE J1850 CRC polynomial ................... 44

Fig. 23. Buck regulator block diagram ..........................46

Fig. 24. Voltage monitoring architecture .......................54

Fig. 25. Clock management architecture ......................55

Fig. 26. Spread-spectrum waveforms ...........................58

Fig. 27. Thermal monitoring architecture ......................60

Fig. 28. Watchdog timer operation ...............................64

Fig. 29. Soft WD reset behavior ...................................66

Fig. 8.

Fig. 9.

Fig. 10. Group power down sequence example ...........25

Fig. 11. Power down delay ...........................................26

Fig. 12. Regulator turned off upon with RegX_

STATE = 0 and FLT_REN = 0 ........................27

Fig. 13. Regulator turned off upon with RegX_

STATE = 0 and FLT_REN = 1 ........................28

Fig. 14. Correct power up (no fault during power up) ....31

PF5023

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

89 / 91

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Fig. 30. Hard WD reset behavior ................................. 67

Fig. 31. Watchdog event counter ................................. 68

Fig. 32. TBB operation diagram ................................... 75

Fig. 33. Hardwire operation diagram ............................77

Fig. 34. Typical application diagram .............................81

Fig. 35. Package outline for HVQFN40 (SOT618-14) ...82

Fig. 36. Package outline detail for HVQFN40

(SOT618-14) ....................................................83

Fig. 37. Solder mask pattern for HVQFN40

(SOT618-14) ....................................................83

Fig. 38. I/O pads and solderable areas for HVQFN40

(SOT618-14) ....................................................84

Fig. 39. Solder paste stencil for HVQFN40

(SOT618-14) ....................................................85

Fig. 40. Package outline notes for HVQFN40

(SOT618-14) ....................................................85

PF5023

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

90 / 91

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

Contents

1

2

3

4

5

6

7

7.1

7.2

8

9

10

Overview .............................................................. 1

14.9.3

14.9.4

14.9.5

14.9.6

14.9.7

14.9.8

14.9.9

RESETBMCU .................................................. 36

INTB .................................................................37

WDI ..................................................................37

PGOOD ............................................................38

PGOODx ..........................................................39

ENx .................................................................. 39

TBBEN .............................................................39

Features ............................................................... 1

Simplified application diagram ..........................2

Ordering information .......................................... 2

Applications .........................................................3

Internal block diagram ........................................3

Pinning information ............................................ 4

Pinning ...............................................................4

Pin description ...................................................4

Absolute maximum ratings ................................5

ESD ratings ..........................................................5

Thermal characteristics ......................................6

Operating conditions ..........................................6

General description ............................................ 6

Features .............................................................6

Functional block diagram ...................................7

Power tree summary ......................................... 7

Device differences ............................................. 8

State machine ......................................................9

State descriptions ............................................ 12

OTP/TRIM load ................................................12

LP_Off state .....................................................12

Self-test routine (PF5023 ASIL B only) ............12

QPU_Off state ................................................. 13

Power up sequence .........................................13

System On state ..............................................13

14.9.10 XFAILB .............................................................40

14.9.11 SDA and SCL (I2C bus) ..................................43

14.9.11.1 I2C CRC verification ........................................43

14.9.11.2 I2C secure write .............................................. 44

15

15.1

Functional blocks ..............................................45

Analog core and internal voltage references ....45

Type 1 buck regulators (SWx) .........................45

SW2 VTT operation .........................................48

Multiphase operation ....................................... 49

Electrical characteristics .................................. 49

Voltage monitoring ...........................................52

Electrical characteristics .................................. 54

Clock management ..........................................55

Low frequency clock ........................................56

High frequency clock ....................................... 56

Manual frequency tuning ................................. 56

Spread-spectrum ............................................. 57

Clock synchronization ......................................58

Thermal monitoring ..........................................60

Analog multiplexer ........................................... 62

Watchdog event management .........................62

Internal watchdog timer ................................... 62

Watchdog reset behaviors ...............................65

I2C register map ................................................68

PF5023 OTP mirror register map .................... 69

PF5023 functional register map .......................71

11

12

15.2

12.1

12.2

12.3

12.4

13

13.1

13.1.1

13.1.2

13.1.3

13.1.4

13.1.5

13.1.6

15.2.1

15.2.2

15.2.3

15.3

15.3.1

15.4

15.4.1

15.4.2

15.4.3

15.4.4

15.4.5

15.5

15.6

15.7

15.7.1

15.7.2

16

13.1.6.1 Run state ......................................................... 14

13.1.6.2 Standby state ...................................................14

13.1.7

13.1.8

13.1.9

13.1.10 Fail-safe state (PF5023 ASIL B only) .............. 16

14

14.1

14.2

14.3

14.4

WD_Reset ........................................................15

Power down state ............................................15

Fail-safe transition ........................................... 15

16.1

16.2

17

General device operation ................................. 17

UVDET .............................................................17

VIN OVLO condition ........................................ 17

IC startup timing with PWRON pulled up .........18

IC startup timing with PWRON pulled low

during VIN application ..................................... 19

Power up ......................................................... 20

Power up events ..............................................20

Power up sequencing ......................................20

Power down .....................................................22

Turn off events ................................................ 22

Power down sequencing ................................. 23

OTP/TBB

and

hardwire

default

configurations ................................................... 73

TBB (Try Before Buy) operation ...................... 74

OTP fuse programming ................................... 75

Default hardwire configuration .........................76

Functional safety ...............................................79

System safety strategy .................................... 79

Output voltage monitoring with dedicated

bandgap reference ...........................................79

ABIST verification ............................................ 80

IC level quiescent current requirements .........80

Typical applications ..........................................81

Package outline .................................................82

Revision history ................................................ 86

Legal information ..............................................87

17.1

17.2

17.3

18

18.1

18.2

14.5

14.5.1

14.5.2

14.6

14.6.1

14.6.2

18.3

19

20

21

22

14.6.2.1 Sequential power down ................................... 23

14.6.2.2 Group power down ..........................................23

14.6.2.3 Power down delay ...........................................25

14.7

14.7.1

14.8

14.9

14.9.1

14.9.2

Fault detection .................................................26

Fault monitoring during power up state ............30

Interrupt management ..................................... 32

I/O interface pins ............................................. 34

PWRON ........................................................... 35

STANDBY ........................................................36

23

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 April 2020

Document identifier: PF5023


型号：	MPF5023AVNA0ES
厂家：	NXP
描述：	Power management integrated circuit (PMIC) for high performance applications 集成电源管理电路
文件：	总91页 (文件大小：860K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPF5023AVNA0ES [NXP]

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