N74F1604N [NXP]
Latch; LATCH
| 型号： | N74F1604N |
| 厂家： | 
NXP |
| 描述： | Latch |
| 文件： | 总10页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F1604
Latch
Product specification
IC15 Data Handbook
1990 Oct 04
Philips
Semiconductors
Philips Semiconductors
Product specification
Latch
74F1604
FEATURES
PIN CONFIGURATION
• High impedance NPN base inputs for reduced loading
(20µA in high and low state)
LE
1
2
28
27
26
25
24
23
V
CC
SELECT A/B
A4
B4
A5
B5
A6
• Stores 16–bit wide data inputs, multiplexed 8–bit outputs
• Propagation delay 7.0ns typical
• Power supply current 70mA typical
A0
B0
3
4
A1
5
B1
6
A2
7
22 B6
21 A7
20 B7
19 Q7
18 Q6
DESCRIPTION
B2
8
The 74F1604 is a dual octal transparent latch. Organized as 8–bit A
and B latches, the latch outputs are connected by pairs to eight
2–input multiplexers. A select (SELECT A/B) input determines
whether the A or B latch contents are multiplexed to the eight
outputs. Data from the B inputs are selected when SELECT A/B is
low; data from the A inputs are selected when SELECT A/B is high.
Data enters the latch on the falling edge of the latch enable (LE)
input. The latch remains transparent to the data inputs while LE is
low, and stores the data that is present one setup time before the
low–to–high latch enable transition.
A3
9
B3
10
11
12
13
14
Q3
Q2
Q1
GND
Q5
17
Q4
Q
16
15
SF00553
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
TYPE
LOGIC SYMBOL
74F1604
7.0ns
70mA
3
4
5
6
7
8
9
10 27 26 25 24 2322 21 20
ORDERING INFORMATION
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6B6A7 B7
ORDER CODE
COMMERCIAL RANGE
DESCRIPTION
PKG DWG #
1
2
LE
SELCT A/B
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
Q0Q1Q2Q3Q4Q5 Q6Q7
15 13 12 11 16 17 18 19
28–pin plastic DIP
28–pin plastic SOL
N74F1604N
N74F1604D
SOT117-2
SOT136-1
V
= Pin 28
CC
GND = Pin 14
SF00554
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
IEC/IEEE SYMBOL
74F (U.L.)
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
2
1
HIGH/LOW
G2
C1
A0 – A7 Data inputs
B0 – B7 Data inputs
1.0/0.033
1.0/0.033
20µA/20µA
3
4
1D 2
1D 2
1
20µA/20µA
20µA/20µA
15
13
12
11
16
17
18
19
SELECT
Select input
A/B
5
1.0/0.033
6
7
Latch enable input
(active low)
20µA/20µA
LE
1.0/0.033
50/33
8
9
Q0 – Q7 Data outputs
1.0mA/20mA
10
27
26
25
24
23
22
21
20
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and
0.6mA in the low state.
SF00555
2
October 4, 1990
853 0088 00619
Philips Semiconductors
Product specification
Latch
74F1604
LOGIC DIAGRAM
2
1
SELECT A/B
LE
3
4
D
E
A0
Q
Q
15
13
B0
Q0
Q1
D
E
Q
Q
5
6
D
E
A1
B1
D
E
7
8
D
E
A2
B2
Q
Q
Q
Q
12
11
16
17
Q2
Q3
Q4
Q5
D
E
Q
Q
Q
Q
9
D
E
A3
B3
10
D
E
27
26
D
E
A4
B4
D
E
25
24
D
E
A5
B5
D
E
23
22
D
E
A6
B6
Q
Q
18
19
Q6
Q7
D
E
Q
Q
21
20
D
E
A7
B7
D
E
V
= Pin 28
CC
GND = Pin 14
SF00556
FUNCTION TABLE
INPUTS
OUTPUTS
OUTPUTS
OPERATING MODE
A0 – A7
B0 –B7
SELECT A/B
LE
L
Q0 – Q7
B data
A data
NC
A data
A data
X
B data
B data
X
L
H
X
l
Enable and read register
L
H
↑
Hold
A data
A data
B data
B data
B data
A data
Latch and read register
h
↑
Notes to function table
H = High–voltage level
h
L
l
=
=
=
High–voltage level one setup time before the low–to–high latch enable transition
Low–voltage level
Low–voltage level one setup time before the low–to–high latch enable transition
NC= No change ( If SELECT A/B is toggled and the A latched data is different from B latched data then the output will change accordingly.)
X
↑
=
=
Don’t care
Low–to–high latch enable transition
3
October 4, 1990
Philips Semiconductors
Product specification
Latch
74F1604
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
40
mA
°C
°C
OUT
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
Ik
High–level output current
Low–level output current
OH
OL
20
T
amb
Operating free air temperature range
0
+70
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
I
= –1mA
= –3mA
= MAX
±10%V
±5%V
2.5
V
V
V
V
OH
CC
V
OH
High-level output voltage
V
V
= MIN, V = MAX,
2.7
2.4
2.7
3.4
CC
CC
IL
I
±10%V
= MIN
OH
CC
CC
IH
±5%V
3.3
V
V
Low-level output voltage
V
V
V
V
= MIN, V = MAX,
I
OL
±10%V
0.30
0.30
0.50
0.50
V
V
OL
CC
IL
CC
= MIN
±5%V
IH
CC
Input clamp voltage
= MIN, I = I
IK
–0.73 -1.2
100
V
IK
CC
CC
I
I
I
Input current at maximum input voltage
= MAX, V = 7.0V
µA
I
I
I
High–level input current
Low–level input current
V
V
= MAX, V = 2.7V
20
µA
µA
IH
CC
I
= MAX, V = 0.5V
–20
IL
CC
I
3
Short–circuit output current
I
V
= MAX
= MAX
-60
-150
mA
mA
mA
OS
CC
CC
CC
I
Supply current (total)
I
V
60
75
80
CCH
I
100
CCL
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4
October 4, 1990
Philips Semiconductors
Product specification
Latch
74F1604
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
T
amb
= +25°C
= 0°C to +70°C
amb
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
SELECT A/B to Qn (non–inverting)
3.0
3.5
5.5
6.5
8.5
10.0
2.5
3.0
9.0
11.5
PLH
PHL
Waveform 2
Waveform 1
Waveform 3
Waveform 1, 2
ns
ns
ns
ns
t
t
Propagation delay
SELECT A/B to Qn (inverting)
4.0
2.5
7.0
4.5
10.5
7.5
3.5
2.0
12.0
8.0
PLH
PHL
t
t
Propagation delay
LE to Qn
6.5
6.0
9.5
9.0
13.0
12.5
5.5
5.0
15.0
14.0
PLH
PHL
t
t
Propagation delay
An or Bn to Qn
4.0
4.0
6.5
7.0
9.5
10.5
3.5
3.5
10.5
12.5
PLH
PHL
AC SETUP REQUIREMENTS
LIMITS
T
T
= +25°C
= +5.0V
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C
= 50pF, R = 500Ω
C = 50pF, R = 500Ω
D L
D
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time, high or low
An, Bn to LE
0.0
1.0
0.0
3.5
Waveform 4
ns
t (H)
Hold time, high or low
An, Bn to LE
1.5
3.0
2.0
3.5
h
Waveform 4
Waveform 4
ns
ns
t
h
(L)
t
w
(L)
LE Pulse width, low
6.5
7.5
AC WAVEFORMS
An, Bn,
SELCET A/B
V
V
V
V
M
M
V
M
M
M
LE
Qn
t
t
PLH
PHL
t
PHL
t
PLH
V
V
M
M
V
Qn
M
V
M
SF00557
SF00559
Waveform 1. Propagation delay for SELECT A/B to output
(A register stored data = low) or An. Bn to output
Waveform 3. Propagation delay for latch enable to output
V
V
V
V
M
An, Bn
LE
M
M
M
An, Bn,
SELCET A/B
V
V
M
M
t
su
(L)
t (L)
h
t
su
(H)
t (H)
h
t
t
PLH
PHL
V
M
V
M
V
V
M
M
Qn
SF00560
SF00558
Waveform 4. Setup time and hold times and LE pulse width
Waveform 2. Propagation delay for SELECT A/B to output
(A register stored data = low) or An. Bn to output
Note to AC waveforms
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
5
October 4, 1990
Philips Semiconductors
Product specification
Latch
74F1604
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
6
October 4, 1990
Philips Semiconductors
Product specification
Latch
74F1604
DIP28: plastic dual in-line package; 28 leads (600 mil); long body
SOT117-2
7
1990 Oct 04
Philips Semiconductors
Product specification
Latch
74F1604
SO28: plastic small outline package; 28 leads; body width 7.5mm
SOT136-1
8
1990 Oct 04
Philips Semiconductors
Product specification
Latch
74F1604
NOTES
9
1990 Oct 04
Philips Semiconductors
Product specification
Latch
74F1604
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
Production
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05194
Document order number:
Philips
Semiconductors
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