N74F166D [NXP]
8-bit bidirectional universal shift register; 8位双向通用移位寄存器
| 型号： | N74F166D |
| 厂家： | 
NXP |
| 描述： | 8-bit bidirectional universal shift register |
| 文件： | 总12页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F166
8-bit bidirectional universal shift register
Product specification
IC15 Data Handbook
1991 Feb 14
Philips
Semiconductors
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
For expansion of the register in parallel to serial converters,
the Q7 output is connected to the Ds input of the succeeding
stage. The clock input is gated OR structure which allows
one input to be used as an active–low clock enable (CE)
input. The pin assignment for the CP and CE inputs is
arbitrary and can be reversed for layout convenience. The
low–to–high transition of CE input should only take place
while the CP is high for predictable operation. A low on the
master reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all bit positions to a low
state.
FEATURES
• High impedance NPN base inputs for reduced loading
(20µA in high and low states)
• Synchronous parallel to serial applications
• Synchronous serial data input for easy expansion
• Clock enable for ”do nothing” mode
• Asynchronous master reset
• Expandable to 16 bits in 8–bit increments
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F166 is a high speed 8–bit shift register that has fully
synchronous serial parallel data entry selected by an active
low parallel enable (PE) input. When the PE is low one setup
time before the low–to–high clock transition, parallel data is
entered into the register.
TYPE
TYPICAL f
TYPICAL SUPPLY CUR-
RENT( TOTAL)
max
74F166
175MHz
50mA
When PE is high, data is entered into internal bit position Q0
from serial data input (Ds), and the remaining bits are shifted
one place to the right (Q0 → Q1 → Q2, etc.) with each
positive going clock transition.
ORDERING INFORMATION
ORDER CODE
INDUSTRIAL RANGE
= 5V ±10%,
COMMERCIAL RANGE
= 5V ±10%,
DESCRIPTION
PKG DWG #
V
V
CC
CC
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
16–pin plastic DIP
16–pin plastic SO
N74F166N
I74F166N
SOT38-4
N74F166D
I74F166D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOAD VALUE HIGH/
LOW
LOW
20µA/20µA
40µA/40µA
20µA/20µA
20µA/20µA
20µA/20µA
40µA/40µA
1.0mA/20mA
D0 – D7
Ds
Parallel data inputs
1.0/0.033
2.0/0.066
1.0/0.033
1.0/0.033
1.0/0.033
2.0/0.066
50/33
Serial data input (shift right)
Clock input (active rising edge)
Clock enable input (active low)
Parallel enable input (active low)
Master reset input (active low)
Data output
CP
CE
PE
MR
Q7
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
Feb. 14, 1991
853–0349 01718
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
PIN CONFIGURATION
IEC/IEEE SYMBOL
SRG 8
9
R
1
2
3
4
5
16
15
14
13
12
Ds
D0
15
V
CC
M1 [SHIFT]
M2 [LOAD]
PE
6
7
1
D1
D7
Q7
D6
D5
D4
MR
C3/1
D2
1
D3
1, 3D
2, 3D
2
3
6
7
8
11
10
9
CE
2,3D
CP
4
5
GND
10
11
12
14
SP000283
LOGIC SYMBOL
13
SF00285
1
2
3
4
5
10 11 12 14
Ds D0 D1 D2 D3 D4 D5 D6 D7
6
CE
CP
MR
PE
7
9
15
Q7
13
V
= Pin 16
CC
GND = Pin 8
SF00284
FUNCTION TABLE
INPUTS
Qn REGISTER
OUTPUT
OPERATING MODE
PE
l
CE
CP
↑
DS
X
X
l
D0 –D7
Q0
L
Q1 – Q6
L – L
Q7
L
l
l
l – l
Parallel load
Serial shift
l
↑
h – h
X – X
X – X
X – X
H
H – H
H
h
h
X
l
↑
L
q0 – q5
q0 – q5
q1 – q6
q6
q6
q7
l
↑
h
H
h
X
X
qn
Hold (do nothing)
Notes to function table
1. H
2. h
3. L
4. l
=
=
=
=
High–voltage level
High voltage level one setup time before the low–to–high clock transition
Low–voltage level
Low voltage level one setup time before the low–to–high clock transition
5. qn = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the low–to–high clock transition
6. X
7. ↑
=
=
Don’t care
Low–to–high clock transition
3
Feb. 14, 1991
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
LOGIC DIAGRAM
9
MR
1
DS
R
R
R
R
R
R
R
R
CP
Q
S
S
S
S
S
S
S
S
15
PE
2
D0
CP
Q
3
D1
CP
Q
4
D2
CP
Q
5
D3
CP
Q
10
D4
CP
Q
11
D5
CP
Q
12
D6
CP
Q
14
D7
7
13
CP
Q7
V
= Pin 16
6
CC
CE
SF00286
GND = Pin 8
4
Feb. 14, 1991
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
–0.5 to V
V
OUT
CC
40
mA
°C
°C
°C
OUT
T
amb
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
stg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IN
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
Ik
High–level output current
Low–level output current
OH
OL
20
T
amb
Operating free air temperature range
Commercial range
Industrial range
0
+70
°C
°C
–40
+85
5
Feb. 14, 1991
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
V
High–level output voltage
V
= MIN, V
=
I
OH
= MAX
2.5
V
V
±10%V
±5%V
OH
CC
IL
IL
CC
MAX,
V
IH
= MIN
2.7
3.4
CC
V
CC
= MIN, V
=
V
OL
Low–level output voltage
I
OL
= MAX
0.30
0.30
0.50
0.50
V
V
±10%V
CC
CC
MAX,
V
IH
= MIN
±5%V
V
Input clamp voltage
Input current at maximum
input voltage
V
V
= MIN, I = I
IK
-0.73 -1.2
100
V
IK
CC
I
I
I
others
= 0.0V, V = 7.0V
µA
CC
I
3
CE, CP
others
MR, Ds
Industrial others
20
40
µA
µA
µA
µA
µA
µA
mA
I
High–level input
V
= MAX, V = 2.7V
I
IH
CC
CC
current
40
only
MR, Ds
others
80
I
IL
Low–level input current
V
= MAX, V = 0.5V
-20
-40
-150
I
MR, Ds
4
I
I
Short–circuit output current
V
V
= MAX
-60
OS
CC
= MAX, PE = CE = Dn = GND,
CC
Supply current (total)
50
70
mA
CC
MR = Ds = 4.5V, CP = ↑
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. When testing CP, CE must remain in high state, whereas CP must remain in high state when testing CE.
4. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C
T
= 0°C to
+70°C
= +5.0V ± 10%
T
amb
= –40°C to +85°C
V = +5.0V ± 10%
CC
amb
amb
V
SYMBOL
PARAMETER
TEST
V
= +5.0V
UNIT
CC
CC
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
135
175
110
100
ns
ns
max
t
t
Propagation delay
CP to Q7
5.0
4.0
7.5
6.0
10.0
8.0
5.0
3.5
12.0
9.0
5.0
3.5
13.0
9.0
PLH
PHL
Propagation delay
MR to Q7
t
Waveform 2
4.0
6.5
8.5
4.0
9.5
4.0
9.5
ns
PHL
6
Feb. 14, 1991
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to
T
amb
= –40°C to +85°C
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn, Ds to CP, CE
3.0
2.5
4.0
3.0
4.0
3.0
su
su
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 1
ns
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, high or low
Dn, Ds to CP
0.0
0.0
1.0
0.0
1.0
0.0
h
t (L)
h
t (H)
Hold time, high or low
Dn, Ds to CE
1.5
0.0
2.0
0.0
2.0
0.0
h
t (L)
h
Setup time, low
CE to CP
t
su
(L)
5.0
0.0
6.0
0.0
6.0
0.0
Hold time, high
CE to CP
t (H)
h
t
su
t
su
(H)
(L)
Setup time, high or low
PE to CP, CE
3.0
3.0
4.0
4.0
4.0
6.0
t (H)
Hold time, high or low
PE to CP
0.0
0.0
0.0
0.0
0.0
0.0
h
t (L)
h
t
w
t
w
(H)
(L)
CP pulse width,
high or low
3.0
4.5
3.5
5.0
3.5
6.0
t
(L)
MR pulse width, low
Waveform 2
Waveform 2
4.0
4.0
4.0
4.5
4.0
4.5
ns
ns
w
,
t
Recovery time MR to CP
rec
AC WAVEFORMS
MR
CP
V
V
M
M
1/f
MAX
t
(L)
t
rec
w
CP
V
V
V
t
M
M
t
M
V
M
t
(H)
(L)
W
W
t
PHL
t
PHL
PLH
Q7
V
M
Q7
V
V
M
SF00288
SF00288
M
Waveform 2. Master reset pulse width, master reset to output
delay and master reset to clock recovery time
SF00287
Waveform 1. Propagation delay for clock input to output,
clock pulse width, and maximum clock frequency
7
Feb. 14, 1991
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
V
V
M
V
V
M
V
V
M
CE
PE
M
M
M
t
t
(L)
(L)
t
t
= 0
= 0
t
t
(L)
(H)
t
t
= 0
= 0
t
(H)
t = 0
h
su
h
su
h
su
V
V
M
V
V
M
M
M
su
h
su
h
Dn
stable
V
V
h
M
M
t
t
= 0
su
Ds
stable
V
V
t
M
M
t
= 0
su
h
CP, CE
V
V
V
M
M
M
SF00289
Waveform 3. Setup and hold times
Notes to AC waveforms
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
t
AMP (V)
90%
V
w
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
t )
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
8
Feb. 14, 1991
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
9
1991 Feb 14
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
10
1991 Feb 14
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
NOTES
11
1991 Feb 14
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05086
Document order number:
Philips
Semiconductors
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