N74F175AD [NXP]
IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-109, SO-16, FF/Latch;
| 型号： | N74F175AD |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-109, SO-16, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F175A
Quad D flip-flop
Product specification
2000 Jun 30
Supersedes data of 1996 Mar 12
IC15 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
FEATURES
PIN CONFIGURATION
• Four edge-triggered D-type flip-flops
MR
Q0
Q0
D0
D1
1
2
3
4
5
16
V
CC
• Buffered common clock
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
• Buffered asynchronous Master Reset
• True and complementary outputs
• Industrial temperature range available (–40°C to +85°C)
• PNP light loading inputs
Q1
Q1
6
7
8
DESCRIPTION
GND
9 CP
The 74F175A is a quad, edge-triggered D-type flip-flop with
individual D inputs and both Q and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
SF00718
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
TYPE
TYPICAL f
TYPICAL SUPPLY
CURRENT (TOTAL)
max
74F175A
160MHz
22mA
All Q outputs will be forced Low independently of clock or data
inputs by a Low voltage level on the MR input. The device is useful
for applications where both true and complementary outputs are
required, and the CP and MR are common to all storage elements.
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
DESCRIPTION
PKG. DWG. #
V
CC
= 5V ±10%,
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
16-pin plastic DIP
16-pin plastic SO
N74F175AN
N74F175AD
I74F175AN
SOT38-4
I74F175AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
D0 – D3
MR
Data inputs
74F175A
74F175A
74F175A
1.0/0.033
1.0/0.033
1.0/0.033
50/33
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1.0mA/20mA
Master reset input (active–Low)
Clock input (active rising edge)
True outputs
CP
Q0–Q3
Q0–Q3
Complementary outputs
50/33
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
2
2000 Jun 30
853–0047 24024
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
LOGIC SYMBOL
IEC/IEEE SYMBOL
1
9
R
4
5
12 13
C1
2
3
4
5
D0 D1 D2 D3
1D
7
6
9
1
CP
MR
10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
12
13
11
15
2
3
7
6
10 11 15 14
SF00719
14
V
= Pin 16
CC
GND = Pin 8
SF00720
LOGIC DIAGRAM
D0
4
D1
D2
12
D3
13
5
9
1
CP
D
Q
D
Q
D
Q
D
Q
Q
CP
CP
RD
CP
RD
CP
RD
RD
MR
3
2
6
7
11 10
Q2 Q2
14 15
Q3 Q3
V
= Pin 16
CC
Q0 Q0
Q1 Q1
GND = Pin 8
SF00721
FUNCTION TABLE
H = High voltage level
INPUTS
OUTPUTS
OPERATING
MODE
h
=
High state must be present one setup time before the
Low-to-High clock transition
MR
L
CP
X
Dn
X
h
Q
Q
n
n
L
l
=
=
Low voltage level
Low state must be present one setup time before the
Low-to-High clock transition
L
H
Reset (clear)
Load “1”
H
↑
H
L
L
X
↑
=
=
Don’t care
Low-to-High clock transition
H
↑
I
H
Load “0”
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
Supply voltage
Input voltage
Input current
V
IN
V
I
IN
mA
V
I
Voltage applied to output in High output state
Current applied to output in Low output state
–0.5 to V
V
OUT
CC
40
mA
°C
°C
°C
OUT
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
amb
Operating free air temperature range
Storage temperature range
T
stg
3
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
UNIT
MAX
MIN
4.5
V
CC
Supply voltage
5.5
V
V
V
IH
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
0.8
–18
–1
V
IL
IK
I
mA
mA
mA
I
High-level output current
Low-level output current
OH
I
OL
20
Commercial range
Industrial range
0
+70
°C
°C
T
amb
Operating free air temperature range
–40
+85
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN
2.5
TYP
MAX
"10%V
CC
V
V
= MIN, V = MAX,
IL
CC
V
High-level output voltage
Low-level output voltage
V
V
OH
= MIN, I = MAX
IH
OH
"5%V
2.7
3.4
CC
V
"10%V
0.30
0.30
0.5
0.5
OL
CC
CC
V
V
= MIN, V = MAX,
IL
CC
IH
= MIN, I = MAX
OL
"5%V
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73
–1.2
100
20
V
IK
I
I
Input current at maximum input voltage
High-level input current
= 0.0V, V = 7.0V
µA
µA
µA
mA
mA
I
I
I
IH
= MAX, V = 2.7V
I
I
IL
Low-level input current
= MAX, V = 0.5V
–20
–150
31
I
3
I
I
Short-circuit output current
= MAX
= MAX
–60
OS
Supply current (total)
22
CC
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= 25°C
= +5V
T
= 0°C to +70°C
= +5.0V ± 10%
T
amb
= *40°C to +85°C
V = +5.0V ± 10%
CC
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF,
R = 500Ω
L
C = 50pF,
R = 500Ω
L
C = 50pF,
R = 500Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Maximum clock
frequency
f
Waveform 1
Waveform 1
Waveform 3
Waveform 3
140
160
125
110
MHz
ns
max
t
t
Propagation delay
CP to Qn or Qn
3.0
4.5
4.0
6.0
6.5
8.5
2.5
4.0
7.5
9.0
2.5
4.0
8.0
10.0
PLH
PHL
Propagation delay
MR to Qn
t
t
PLH
PHL
4.5
4.5
6.5
6.0
9.0
8.0
4.5
4.0
10.0
9.0
4.5
4.0
11.0
10.0
ns
Propagation delay
MR to Qn
t
t
PHL
PHL
ns
4
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
AC SETUP REQUIREMENTS
LIMITS
T
= 25°C
= +5V
T
= 0°C to +70°C
= +5.0V ± 10%
T
= *40°C to +85°C
amb
amb
amb
V
V
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CC
CONDITION
C = 50pF,
R = 500Ω
L
C = 50pF,
R = 500Ω
L
C = 50pF,
L
R = 500Ω
L
L
L
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
3.0
3.0
3.5
3.5
4.0
4.0
s
Waveform 2
Waveform 2
Waveform 1
Waveform 3
Waveform 3
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
0.0
0.0
0.0
0.0
0.0
0.0
h
t (L)
h
t (H)
3.0
4.0
3.5
5.0
4.0
5.5
CP Pulse width
High or Low
w
t (L)
w
MR Pulse width
Low
t (L)
w
3.5
4.0
3.5
4.5
4.0
5.0
Recovery time
MR to CP
t
REC
AC WAVEFORMS
For all waveforms, V = 1.3V.
M
1/f
max
V
V
M
MR
CP
M
V
V
M
M
V
M
CP
t
w
(H)
t
w
(L)
t
REC
t
t
t
w
(L)
PHL
PLH
V
M
V
M
V
M
M
Q
n
Q
n
t
PHL
t
PHL
t
PLH
Q
n
V
V
M
M
V
V
M
t
PLH
SF00722
Q
n
Waveform 1. Propagation delay for clock input to output, clock
pulse width, and maximum clock frequency
SF00723
Waveform 3. Master Reset pulse width, Master Reset to output
delay and Master Reset to Clock recovery time
Dn
V
V
t
V
V
M
M
M
M
t (H)
(H)
t (L)
t
(L)
s
h
s
h
CP
V
V
M
M
SF00191
Waveform 2. Data setup time and hold times
5
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
6
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
7
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
8
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
NOTES
9
2000 Jun 30
Philips Semiconductors
Product specification
Quad D flip-flop
74F175A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-00
Document order number:
9397-750 07531
Philips
Semiconductors
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