N74F2373D [NXP]
Octal transparent latch with 30ohm equivalent output termination 3-State; 八路透明锁存器与30ohm相当于输出端接三态
| 型号： | N74F2373D |
| 厂家： | 
NXP |
| 描述： | Octal transparent latch with 30ohm equivalent output termination 3-State |
| 文件： | 总10页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F2373
Octal transparent latch with 30Ω
equivalent output termination (3-State)
Product specification
1999 Feb 01
Supersedes data of 1995 Jun 20
IC15 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
FEATURES
• 8-bit transparent latch
• 30 Ohm output termination for driving DRAM
• 3-State outputs glitch free during power-up and power-down
• Common 3-State output register
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is low, latched or
transparent data appears at the output.
• Independent register and 3-State buffer operation
When OE is high, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
DESCRIPTION
The 74F2373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
TYPE
The 30 Ohm series termination on the outputs reduces
over/undershoot, making them ideal for driving DRAM
(TOTAL)
74F2373
4.5ns
35mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
DESCRIPTION
DRAWING NUMBER
V
CC
amb
20-pin plastic DIP
20-pin plastic SOL
N74F2373N
N74F2373D
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
LOAD VALUE
HIGH/LOW
74F (U.L.)
HIGH/LOW
PINS
DESCRIPTION
20µA/0.6mA
D0 - D7
E
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
150/40
20µA/0.6mA
20µA/0.6mA
3.0mA/3.0mA
Enable input (active high)
Output enable inputs (active low)
3-State outputs
OE
Q0 - Q7
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
LOGIC SYMBOL
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
V
CC
3
4
7
8
13 14 17 18
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
D0 D1 D2 D3 D4 D5 D6 D7
11
E
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9 12 15 16 19
GND 10
11 E
V
= Pin 20
CC
GND = Pin 10
SF00250
SF00251
2
1999 Feb 01
853-2140 20747
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
IEC/IEEE SYMBOL
1
EN1
11
EN2
3
2
2D
1
5
6
9
4
7
8
13
12
15
16
19
14
17
18
SF00252
LOGIC DIAGRAM
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
Q
Q
Q
Q
Q
Q
Q
Q
11
E
1
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q0
Q1
Q2
Q3
Q7
V
= Pin 20
CC
GND = Pin 10
SF00256
FUNCTION TABLE
INPUTS
OUTPUTS
Q0 - Q7
INTERNAL
REGISTER
OPERATING MODE
OE
L
E
H
H
↓
Dn
L
L
H
L
H
Enable and read register
L
H
l
L
L
L
Latch and read register
Hold
L
↓
h
H
H
L
L
X
NC
NC
Dn
NC
Z
H
L
X
Disable outputs
H
H
Dn
Z
NOTES:
H
h
L
l
=
=
=
=
High-voltage level
High state must be present one setup time before the high-to-low enable transition
Low-voltage level
Low state must be present one setup time before the high-to-low enable transition
NC=
No change
Don’t care
High impedance “off” state
High-to-low enable transition
X
Z
↓
=
=
=
3
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
Voltage applied to output in high output state
Current applied to output in low output state
-0.5 to V
V
OUT
CC
I
24
mA
OUT
T
Operating free air temperature range
Storage temperature range
0 to +70
°C
°C
amb
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
5.0
5.5
V
V
Supply voltage
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–3*
5*
V
I
I
I
mA
mA
mA
Ik
High-level output current
Low-level output current
OH
OL
T
amb
Operating free air temperature range
0
+70
°C
*
12mA with reduced noise margin
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
2
MIN TYP
MAX
±10%V
±5%V
V
V
V
V
= MIN, V = MAX,
2.4
V
V
V
V
CC
CC
IL
= MIN, I = –3mA
2.7
2.0
2.0
3.4
CC
IH
OH
V
OH
High-level output voltage
±10%V
= MIN, V = MAX,
CC
CC
CC
IL
±5%V
= MIN, I = –12mA
IH
OH
V
V
V
V
V
V
V
V
= MIN, V = MAX,
±10%V
0.42
0.42
0.67
0.67
0.50
0.50
V
V
CC
IL
CC
= MIN, I = –5mA
±5%V
IH
OL
CC
V
V
Low-level output voltage
OL
= MIN, V = MAX,
±10%V
V
CC
IL
CC
CC
= MIN, I = 12mA
±5%V
V
IH
OL
Input clamp voltage
= MIN, I = I
IK
-0.73 -1.2
V
IK
CC
CC
CC
CC
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
100
20
µA
µA
mA
µA
I
I
= MAX, V = 2.7V
IH
IL
I
Low-level input current
= MAX, V = 0.5V
-0.6
50
I
Off-state output current, high-level voltage applied
V
CC
CC
= MAX, V = 2.7V
O
OZH
OZL
µA
I
Off-state output current, low-level voltage applied
V
= MAX, V = 0.5V
-50
O
3
Short-circuit output current
I
I
V
V
= MAX
= MAX
-60
-150
mA
mA
OS
CC
Supply current (total)
35
60
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
T
amb
= +25°C
= 0°C to +70°C
amb
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
3.0
2.0
5.3
3.7
8.0
6.0
3.0
2.0
9.0
7.0
PLH
PHL
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Propagation delay
E to Qn
5.0
3.0
9.0
4.0
12.0
8.0
5.0
3.0
12.5
8.5
PLH
PHL
t
t
Output enable time
to high or low level
Waveform 4
Waveform 5
2.0
2.0
5.0
5.6
12.0
8.0
2.0
2.0
12.5
8.5
PZH
PZL
t
t
Output disable time
from high or low level
Waveform 4
Waveform 5
2.0
2.0
4.5
3.8
6.5
5.5
2.0
2.0
7.5
6.5
PHZ
PLZ
AC SETUP REQUIREMENTS
LIMITS
T
T
= +25°C
= +5.0V
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time, high or low level
Dn to E
0
1.0
0
1.0
Waveform 3
ns
t (H)
Hold time, high or low level
Dn to E
3.0
3.0
3.0
3.0
h
Waveform 3
Waveform 1
ns
ns
t
h
(L)
t
w
(H)
E Pulse width, high
3.5
4.0
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
t
(H)
w
Dn
E
V
V
V
V
M
M
M
M
E
V
M
V
V
t
M
M
t
(L)
t (L)
h
t
(H)
t (H)
h
su
su
t
PHL
PLH
V
V
V
M
M
Qn
V
M
M
SF00261
SF00259
Waveform 3. Data setup time and hold times
Waveform 1. Propagation delay for enable to output
and enable pulse width
OEn
V
V
M
M
Dn
V
V
t
M
M
V
-0.3V
OH
t
t
PHZ
PZH
t
PHL
PLH
Qn, Qn
V
M
0V
Qn
V
V
M
M
SF00260
SF00263
Waveform 2. Propagation delay for data to output
Waveform 4. 3-State output enable time to high level
and output disable time from high level
5
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
AC WAVEFORMS (Continued)
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for
predictable output performance.
OEn
V
t
V
M
M
t
PZL
PLZ
V
M
Qn, Qn
V
+0.3V
OL
SF00264
Waveform 5. 3-State output enable time to low level
and output disable time from low level
TEST CIRCUIT AND WAVEFORMS
SWITCH POSITION
t
w
AMP (V)
90%
TEST
SWITCH
closed
open
90%
7.0V
V
CC
NEGATIVE
PULSE
t
, t
PLZ PZL
V
V
M
M
All other
10%
10%
0V
R
L
V
V
OUT
IN
t
t )
t
t )
THL ( f
TLH ( r
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
TLH ( r
THL ( f
R
C
R
L
AMP (V)
T
L
90%
M
90%
POSITIVE
PULSE
V
V
M
Test circuit for 3-state outputs
DEFINITIONS:
10%
10%
0V
t
w
Input pulse definition
R
C
Load resistor; see AC electrical characteristics for value.
L =
L =
INPUT PULSE REQUIREMENTS
V
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
family
rep. rate
t
t
t
amplitude
M
w
TLH
THL
R
T =
Termination resistance should be equal to Z
generators.
of pulse
OUT
74F
3.0V
1.5V
1MHz
500ns 2.5ns
2.5ns
SF00265
6
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
7
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
8
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
NOTES
9
1999 Feb 01
Philips Semiconductors
Product specification
Octal transparent latch with 30Ω equivalent output
termination (3-State)
74F2373
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05201
Document order number:
Philips
Semiconductors
相关型号：
©2020 ICPDF网 联系我们和版权申明