N74F299D-T [NXP]
IC F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, SOT-108, SOP-20, Shift Register;
| 型号： | N74F299D-T |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, SOT-108, SOP-20, Shift Register 光电二极管 输出元件 |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F299
8-bit universal shift/storage register
(3-State)
Product data
2003 Feb 05
Supersedes data of 1990 Mar 01
Philips
Semiconductors
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
FEATURES
PIN CONFIGURATION
• Common parallel I/O for reduced pin count
S0
OE0
OE1
I/O6
I/O4
1
2
3
4
5
20
V
CC
• Additional serial inputs and outputs for expansion
• Four operating modes: Shift left, shift right, load and store
• 3-State outputs for bus-oriented applications
19 S1
18 DS7
17 Q7
16 I/O7
DESCRIPTION
I/O2
I/O0
Q0
6
7
8
9
15 I/O5
14 I/O3
13 I/O1
12 CP
The 74F299 is an 8-bit universal shift/storage register with 3-State
outputs. Four modes of operation are possible: Hold (store), shift
left, shift right and parallel load. The parallel load inputs and flip-flop
outputs are multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q0 and Q7 to allow
easy serial cascading. A separate active-LOW Master Reset is used
to reset the register.
MR
GND 10
11 DS0
SF00865
The 74F299 contains eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift left, shift
right, parallel load and hold operations. The type of operation is
determined by S0 and S1, as shown in the Function Table. All
flip-flop outputs are brought out through 3-State buffers to separate
I/O pins that also serve as data inputs in the parallel load mode.
Q0 and Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F299
115 MHz
58 mA
ORDERING INFORMATION
A LOW signal on MR overrides the Select and CP inputs and resets
the flip-flops. All other state changes are initiated by the rising edge
of the clock. Inputs can change when the clock is in either state
provided only that the recommended set-up and hold times, relative
to the rising edge of clock are observed.
ORDER CODE
COMMERCIAL
RANGE
DESCRIPTION
PKG DWG #
V
CC
= 5 V ±10%,
T
amb
= 0 °C to +70 °C
A HIGH signal on either OE0 or OE1 disables the 3-State buffers
and puts the I/O pins in the high impedance state. In this condition
the shift, hold, load and reset operations can still occur. The 3-State
buffers are also disabled by High signals on both S0 and S1 in
preparation for a parallel load operation.
20-pin plastic DIP
20-pin plastic SOL
N74F299N
SOT146-1
SOT163-1
N74F299D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
LOAD VALUE
HIGH / LOW
PINS
DESCRIPTION
HIGH / LOW
1.0 / 1.0
1.0 / 1.0
1.0 / 2.0
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
50 / 33
DS0
Serial data input for right shift
Serial data input for left shift
Mode select inputs
20 µA / 0.6 mA
20 µA / 0.6 mA
20 µA / 1.2 mA
20 µA / 0.6 mA
20 µA / 0.6 mA
20 µA / 0.6 mA
1.0 mA / 20 mA
70 µA / 0.6 mA
3.0 mA / 24 mA
DS7
S0, S1
CP
Clock pulse input (Active rising edge)
MR
Asynchronous Master Reset input (Active LOW)
OE0, OE1 Output Enable input (Active LOW)
Q0, Q7
Serial outputs
Multiplexed parallel data inputs
3-State parallel outputs
3.5 / 1.0
150 / 40
I/On
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20 µA in the HIGH State and 0.6 mA in the LOW state.
2
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
SRG8
11
18
9
4R
&
2
3
1
3EN13
0
DS0
DS7
S0
1
0
1
M
S1
19
19
12
3
12
9
CP
C4/1→ /2←
MR
11
7
8
2
1, 4D
3, 4D
5, 13
OE0
OE1
3
Z5
Z6
13
Q0 I/00 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
3, 4D
6, 13
6
8
7
13
6
14
5
15
4
16
17
14
V
= Pin 20
CC
GND = Pin 10
SF00866
5
15
4
16
18
3, 4D
12, 13
2, 4D
Z12
17
SF00890
FUNCTION TABLE
INPUTS
INPUTS
OPERATING MODE
Asynchronous Reset; Q0 – Q7 = LOW
OEn
MR
L
S1
S0
X
H
H
L
CP
X
↑
L
L
L
L
L
H
X
H
L
H
Parallel load; I/On → Qn (I/On outputs disabled)
Shift right; DS0 → Q0, Q0 → Q1, etc.
Shift left; DS7 → Q7, Q7 → Q6, etc.
Hold
H
↑
H
H
L
↑
H
L
X
X
X
X
X
Outputs in High-Z
H = HIGH voltage level
= LOW voltage level
X = Don’t care
= LOW-to-HIGH clock transition
L
↑
3
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
LOGIC DIAGRAM
18
DS7
17
16
2
Q7
OE0
3
CP
D
OE1
I/O7
I/O6
I/O5
Q
Q
Q
19
S1
R
R
R
D
D
D
1
S0
CP
D
4
CP
D
15
CP
D
5
I/O4
I/O3
I/O2
I/O1
Q
Q
Q
Q
Q
R
R
R
R
R
D
D
D
CP
D
14
CP
D
6
CP
D
13
D
CP
D
7
8
I/O0
Q0
D
11
DS0
12
CP
9
MR
V
= Pin 20
CC
GND = Pin 10
SF00868
4
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
V
V
CC
IN
I
IN
mA
V
V
OUT
Voltage applied to output in HIGH output state
–0.5 to +V
CC
Q0, Q7
I/On
40
48
mA
mA
°C
°C
I
Current applied to output in LOW output state
OUT
T
Operating free-air temperature range
Storage temperature
0 to +70
amb
T
–65 to +150
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
UNIT
MIN
4.5
MAX
V
CC
V
IH
V
IL
Supply voltage
5.5
V
HIGH-level input voltage
LOW-level input voltage
Input clamp current
2.0
V
0.8
–18
–1
V
I
IK
mA
mA
mA
mA
mA
°C
Q0, Q7
I/On
I
HIGH-level output current
OH
OL
–3
Q0, Q7
I/On
20
I
LOW-level output current
24
T
amb
Operating free-air temperature range
0
70
5
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.5
2.7
2.4
2.7
TYP
MAX
±10%V
V
V
V
V
CC
Q0, Q7
I/On
I
= –1 mA
= –3 mA
OH
OH
I
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
IH
±5%V
3.4
CC
V
OH
HIGH-level output voltage
±10%V
CC
CC
I
±5%V
3.3
V
V
V
= MIN,
= MAX,
= MIN
±10%V
CC
IL
IH
0.35
0.50
V
CC
V
OL
LOW-level output voltage
Input clamp voltage
= MAX
OL
±5%V
0.35
0.50
–1.2
100
1
V
V
CC
V
IK
V
CC
= MIN, I = I
IK
–0.73
I
I
I
others
I/On
V
CC
= MAX, V = 7.0 V
µA
mA
I
Input current at maximum
input voltage
V
CC
= 5.5V, V = 5.5 V
I
except
I/On
I
I
HIGH-level input current
LOW-level input current
V
= MAX, V = 2.7 V
20
µA
mA
mA
IH
CC
CC
I
S0, S1
others
–1.2
–0.6
V
= MAX, V = 0.5 V
I
IL
Off-state output current,
HIGH-level voltage applied
I
I
V
V
= MAX, V = 2.7 V
70
µA
IH + OZH
CC
O
I/On
only
Off-state output current
LOW-level voltage applied
I
I
I
= MAX, V = 0.5 V
–0.6
mA
IL + OZL
CC
O
3
Short-circuit output current
V
= MAX
= MAX
–60
–150
60
mA
mA
mA
mA
OS
CC
I
55
70
65
CCH
I
Supply current (total)
I
V
CC
90
CC
CCL
I
95
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5 V, T = 25 °C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
6
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25 °C
T
amb
= 0 °C to +70 °C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
CC
= +5.0 V
V
CC
= +5.0 V ± 10%
C = 50 pF, R = 500 Ω
C = 50 pF, R = 500 Ω
L L
L
L
MIN
TYP
MAX
MIN
70
MAX
I/O
Qn
70
85
100
115
MHz
MHz
f
Maximum clock frequency
Waveform 1
MAX
85
t
t
Propagation delay
CP to Q0 or Q7
4.0
4.5
5.0
6.0
7.5
8.0
3.5
4.5
8.5
8.5
ns
ns
PLH
PHL
Waveform 1
Waveform 1
Waveform 2
Waveform 2
t
t
Propagation delay
CP to I/On
4.0
4.0
6.0
6.5
9.0
9.0
4.0
4.0
10.0
10.0
ns
ns
PLH
PHL
Propagation delay
MR to Q0 or Q7
t
t
5.5
5.5
7.5
7.5
9.5
5.5
5.5
10.5
10.5
ns
ns
PHL
Propagation delay
MR to I/On
10.0
PHL
t
t
Output Enable time
Sn, OE to I/On
Waveform 4
Waveform 5
3.5
4.0
6.0
7.5
8.0
10.0
3.5
4.0
9.0
11.0
ns
ns
PZH
PZL
t
t
Output Disable time
Sn, OE to I/On
Waveform 4
Waveform 5
2.5
1.5
4.5
2.5
7.0
5.5
2.5
1.5
8.0
6.5
ns
ns
PHZ
PLZ
AC SET-UP REQUIREMENTS
LIMITS
T
V
= +25 °C
= +5.0 V
T
V
CC
= 0 °C to +70 °C
= +5.0 V ± 10%
amb
amb
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
CC
C = 50 pF, R = 500 Ω
C = 50 pF, R = 500 Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Set-up time, HIGH or LOW
S0 or S1 to CP
6.5
6.5
7.5
7.5
ns
ns
s
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 1
t (H)
Hold time, HIGH or LOW
S0 or S1 to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
Set-up time, HIGH or LOW
3.5
3.5
4.0
4.0
ns
ns
s
t (L)
s
I/On, DS or DS to CP
L R
t (H)
Hold time, HIGH or LOW
I/On, DS or DS to CP
0
0
0
0
ns
ns
h
t (L)
h
L
R
t (H)
5.0
4.5
5.0
4.5
w
CP Pulse width, HIGH or LOW
ns
t (L)
w
t (L)
MR Pulse width, LOW
Waveform 2
Waveform 2
4.5
4.0
4.5
4.0
ns
ns
w
t
Recovery time, MR to CP
rec
7
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
AC WAVEFORMS
For all waveforms, V = 1.5 V
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
MR
V
V
t
M
t
M
CP
V
t
V
M
M
(L)
W
REC
CP
V
M
(H)
t
(L)
W
W
t
t
PLH
PHL
t
PHL
Q0, Q7, I/On
V
V
M
M
Q0, Q7, I/On
V
M
SF00869
SF00870
Waveform 2. Master Reset pulse width, Master Reset to output
delay, and Master Reset to clock recovery time
Waveform 1. Propagation delay, clock input to output,
clock width, and maximum clock frequency
S0, S1,
I/On
V
V
V
V
M
Sn, OEn
M
M
M
V
V
M
M
DS ,
L
t (H)
s
t
(H)
t (L)
t (L)
h
V
-0.3V
0V
h
s
DS
OH
R
t
t
PHZ
PZH
CP
V
V
I/On
M
M
V
M
SF00871
SF00872
Waveform 3. Set-up and hold times
Waveform 4. 3-State Output Enable time to HIGH level
and Output Disable time from HIGH level
Sn, OEn
I/On
V
t
V
M
M
t
PZL
PLZ
V
M
V
+0.3V
OL
SF00873
Waveform 5. 3-State Output Enable time to LOW level and
Output Disable time from LOW level
8
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
7.0V
90%
90%
NEGATIVE
R
V
V
M
M
L
PULSE
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
=
=
=
Load resistor;
L
INPUT PULSE REQUIREMENTS
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
family
C
L
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
R
T
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00777
9
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
10
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
11
2003 Feb 05
Philips Semiconductors
Product data
8-bit universal shift/storage register (3-State)
74F299
REVISION HISTORY
Rev
Date
Description
_3
20030205
Product data (9397 750 11037); ECN 853-0365 29307 of 17 December 2002.
Supersedes Product specification (9397 750 05117) of 01 March 1990.
Modifications:
• Delete all references to DB package. Package option was discontinued.
_2
19900301
Product specification (9397 750 05117); ECN 853-0365 29307 of 01 March 1990.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2003
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 02-03
9397 750 11037
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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