N74F323D [NXP]
8-bit universal shift/storage register with synchronous reset and common I/O pins 3-State; 8位通用移位/存储寄存器同步复位和通用I / O引脚三态
| 型号： | N74F323D |
| 厂家： | 
NXP |
| 描述： | 8-bit universal shift/storage register with synchronous reset and common I/O pins 3-State |
| 文件： | 总7页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
FEATURES
PIN CONFIGURATION
• Common parallel I/O for reduced pin count
S0
OE0
OE1
I/O6
I/O4
1
2
3
4
5
20
V
• Additional serial inputs and outputs for expansion
• Four operating modes: Shift left, shift right, load, and store
• 3-State outputs for bus-oriented applications
CC
19 S1
18 DS7
17 Q7
16 I/O7
DESCRIPTION
The 74F323 is an 8-bit universal shift/storage register with 3-State
outputs. Its function is similar to the 74F299 with the exception of
synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin counts. Separate serial inputs and
outputs are provided for flip-flops Q0 and Q7 to allow easy serial
cascading. Four modes of operation are possible: Hold (store), shift
left, shift right, and parallel load.
I/O2
I/O0
Q0
6
7
8
9
15 I/O5
14 I/O3
13 I/O1
12 CP
SR
GND 10
11 DS0
SF00888
The 74F323 contains eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous reset, shift left,
shift right, parallel load, and hold operations. The type of operation is
determined by S0 and S1, as shown in the Function Table. All
flip-flop outputs are brought out through 3-State buffers to separate
I/O pins that also serve as data inputs in the parallel load mode.
Q0 and Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F323
115MHz
55mA
ORDERING INFORMATION
A Low signal on SR overrides the Select and inputs and allows the
flip-flops to be reset by the next rising edge of clock. All other state
changes are initiated by the rising edge of the clock. Inputs can
change when the clock is in either state provided only that the
recommended setup and hold times, relative to the rising edge of
clock are observed.
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%, T = 0°C to +70°C
amb
20-pin plastic DIP
20-pin plastic SOL
N74F323N
N74F323D
A High signal on either OE0 or OE1 disables the 3-State buffers and
puts the I/O pins in the high impedance state. In this condition the
shift, hold, load and reset operations can still occur. The 3-State
buffers are also disabled by High signals on both S0 and S1 in
preparation for a parallel load operation.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
DS0
Serial data input for right shift
Serial data input for left shift
Mode select inputs
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/20mA
70µA/0.6mA
3.0mA/24mA
DS7
S0, S1
CP
Clock pulse input (Active rising edge)
Synchronous Reset input (Active Low)
SR
OE0, OE1 Output Enable input (Active Low)
Q0, Q7
Serial outputs
Multiplexed parallel data inputs or
3-State parallel outputs
3.5/1.0
150/40
I/On
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.
1
1990 Mar 01
853-0367 98987
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
SRG8
11
18
9
4R
&
2
3
1
3EN13
0
DS0
DS7
S0
1
0
1
M
S1
19
19
12
3
12
9
CP
SR
C4/1→ /2←
11
7
8
2
1, 4D
3, 4D
5, 13
OE0
OE1
3
Z5
Z6
13
Q0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
3, 4D
6, 13
6
8
7
13
6
14
5
15
4
16
17
SF00889
14
V
= Pin 20
CC
GND = Pin 10
5
15
4
16
18
3, 4D
12, 13
2, 4D
Z12
17
SF00890
FUNCTION TABLE
INPUTS
OPERATING MODE
OEn
SR
S1
X
H
L
S0
X
H
H
L
CP
↑
L
L
L
L
L
L
Synchronous Reset; Q0 - Q7 = Low
Parallel load; I/On → Qn
H
H
H
H
X
↑
↑
Shift right; DS0 → Q0, Q0 → Q1, etc.
Shift left; DS7 → Q7, Q7 → Q6, etc.
Hold
H
L
↑
L
X
X
H
X
X
Outputs disabled (3-state)
H = High voltage level
L
= Low voltage level
X = Don’t care
= Low-to-High clock transition
↑
2
1990 Mar 01
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
LOGIC DIAGRAM
18
DS7
17
2
Q7
OE0
3
CP
D
OE1
16
I/O7
Q
Q
Q
19
S1
1
S0
9
SR
CP
D
4
I/O6
CP
D
15
I/O5
CP
D
5
I/O4
I/O3
I/O2
I/O1
Q
Q
Q
Q
Q
CP
D
14
CP
D
6
CP
D
13
CP
D
7
8
I/O0
Q0
11
DS0
12
CP
V
= Pin 20
CC
GND = Pin 10
SF00883
3
1990 Mar 01
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +5.5
40
V
V
CC
IN
I
IN
mA
V
V
OUT
Voltage applied to output in High output state
Q0, Q7
I/On
mA
mA
°C
°C
I
Current applied to output in Low output state
OUT
48
T
amb
Operating free-air temperature range
Storage temperature
0 to +70
–65 to +150
T
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
UNIT
MIN
4.5
MAX
V
CC
V
IH
V
IL
Supply voltage
5.5
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
0.8
–18
–1
V
I
IK
mA
mA
mA
mA
mA
°C
Q0, Q7
I/On
I
High-level output current
OH
OL
–3
Q0, Q7
I/On
20
I
Low-level output current
24
T
amb
Operating free-air temperature range
0
70
4
1990 Mar 01
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.5
2.7
2.5
2.7
TYP
MAX
±10%V
±5%V
V
V
V
V
CC
Q0, Q7
I/On
I
= –1mA
= –3mA
OH
OH
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
IH
3.4
CC
V
OH
High-level output voltage
±10%V
CC
CC
I
±5%V
3.4
V
V
V
= MIN,
= MAX,
= MIN
±10%V
CC
IL
IH
0.35
0.50
V
CC
V
Low-level output voltage
Input clamp voltage
I
= MAX
OL
OL
±5%V
0.35
0.50
–1.2
100
1
V
V
CC
V
IK
V
= MIN, I = I
IK
–0.73
CC
I
others
I/On
V
CC
= MAX, V = 7.0V
µA
mA
I
Input current at
maximum input voltage
I
I
I
I
V
CC
= 5.5V, V = 5.5V
I
except
I/On
High-level input current
Low-level input current
V
CC
= MAX, V = 2.7V
20
µA
IH
IL
I
S0, S1
others
–1.2
–0.6
mA
mA
V
CC
= MAX, V = 0.5V
I
Off-state output current,
High-level voltage
applied
I
I
I
V
V
= MAX, V = 2.7V
70
µA
IH + OZH
CC
O
I/On
only
Off-state output current
Low-level voltage applied
I
= MAX, V = 0.5V
–0.6
mA
IL + OZL
CC
O
3
I
I
Short-circuit output current
V
= MAX
= MAX
–60
–150
75
mA
mA
mA
mA
OS
CC
I
55
65
55
CCH
Supply current (total)
I
V
CC
90
CC
CCL
I
85
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T =+ 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
5
1990 Mar 01
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
I/O
Qn
70
85
100
115
70
85
MHz
MHz
f
Maximum clock frequency
Waveform 1
MAX
t
t
Propagation delay
CP to Q0 or Q7
4.0
3.5
6.0
6.0
8.5
8.5
3.5
4.5
9.5
9.5
ns
ns
PLH
PHL
Waveform 1
Waveform 1
t
t
Propagation delay
CP to I/On
4.0
5.0
6.0
6.5
9.0
9.5
4.0
4.0
10.0
10.0
ns
ns
PLH
PHL
t
t
Output Enable time
Sn, OE to I/On
Waveform 3
Waveform 4
3.5
4.0
6.0
8.0
9.0
11.0
3.5
4.0
10.0
11.5
ns
ns
PZH
PZL
t
t
Output Disable time
Sn, OE to I/On
Waveform 3
Waveform 4
2.5
1.5
5.0
3.0
7.5
5.5
2.5
1.5
8.0
6.5
ns
ns
PHZ
PLZ
AC SETUP REQUIREMENTS
LIMITS
T
V
= +25°C
= +5.0V
T
V
CC
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
S0 or S1 to CP
6.5
6.5
7.5
7.5
s
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 1
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
S0 or S1 to CP
0
0
0
0
h
t (L)
h
t (H)
Setup time, High or Low
I/O0, DS0 or DS7 to CP
3.5
3.5
4.0
4.0
s
t (L)
s
t (H)
Hold time, High or Low
I/O0, DS0 or DS7 to CP
0
0
0
0
h
t (L)
h
t (H)
Setup time, High or Low
SR to CP
7.0
7.0
8.5
8.5
s
t (L)
s
t (H)
Hold time, High or Low
SR to CP
0
0
0
0
h
t (L)
h
t (H)
3.5
3.5
4.0
4.0
w
CP Pulse width, High or Low
t (L)
w
6
1990 Mar 01
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous
reset and common I/O pins (3-State)
74F323
AC WAVEFORMS
For all waveforms, V = 1.5V
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
S0, S1,
DS , DS
I/On, SR
1/f
MAX
V
V
V
V
M
,
R
M
M
M
L
t (H)
s
t
(H)
t (L)
t (L)
h
CP
h
s
V
t
V
M
M
(H)
t
(L)
CP
V
V
M
W
W
M
t
t
PLH
PHL
Q0, Q7, I/On
V
V
SF00885
M
M
Waveform 2. Data, Select and Reset Setup and Hold Times
SF00884
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Sn, OEn
I/On
V
t
V
M
M
Sn, OEn
I/On
V
V
M
M
t
V
-0.3V
0V
PZL
PLZ
OH
t
t
PHZ
PZH
V
M
V
M
V
+0.3V
OL
SF00886
SF00887
Waveform 3. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
0V
7.0V
90%
90%
NEGATIVE
PULSE
V
V
M
R
L
M
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
family
V
M
rep. rate
t
t
t
THL
amplitude
w
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00777
7
1990 Mar 01
相关型号：
N74F323N
8-bit universal shift/storage register with synchronous reset and common I/O pins 3-State
NXP
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