N74F373N,602 [NXP]
N74F373 - Octal transparent latch (3-State) DIP 20-Pin;
| 型号： | N74F373N,602 |
| 厂家： | 
NXP |
| 描述： | N74F373 - Octal transparent latch (3-State) DIP 20-Pin 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product data
2002 Nov 20
Supersedes data of 1994 Dec 05
Philips
Semiconductors
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
FEATURES
• 8-bit transparent latch — 74F373
• 8-bit positive edge triggered register — 74F374
• 3-State outputs glitch free during power-up and power-down
• Common 3-State output register
The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
• Independent register and 3-State buffer operation
• SSOP Type II Package
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is LOW, the data in
the register appears at the outputs. When OE is HIGH, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
TYPE
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.
(TOTAL)
74F373
4.5 ns
35 mA
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
TYPICAL SUPPLY
CURRENT
TYPE
TYPICAL f
max
(TOTAL)
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is LOW, latched or
transparent data appears at the output.
74F374
165 MHz
55 mA
When OE is HIGH, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5 V ±10%, T = 0 °C to +70 °C
DESCRIPTION
PKG DWG #
V
CC
amb
20-pin plastic DIP
20-pin plastic SOL
N74F373N, N74F374N
N74F373D, N74F374D
N74F373DB, N74F374DB
SOT146-1
SOT163-1
SOT339-1
20-pin plastic SSOP type II
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH / LOW
LOAD VALUE
PINS
DESCRIPTION
HIGH/LOW
20 µA / 0.6 mA
20 µA / 0.6 mA
20 µA / 0.6 mA
20 µA / 0.6 mA
3.0 mA / 24 mA
D0 - D7
E (74F373)
OE
Data inputs
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
150 / 40
Enable input (active-HIGH)
Output enable inputs (active-LOW)
Clock pulse input (active rising edge)
3-State outputs
CP (74F374)
Q0 - Q7
NOTE: One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
2
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
PIN CONFIGURATION – 74F373
PIN CONFIGURATION – 74F374
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
V
CC
OE
Q0
V
CC
1
2
20
19
18
17
16
15
14
13
12
11
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND 10
11 E
GND
10
SF00250
SF00253
LOGIC SYMBOL – 74F373
IEC/IEE SYMBOL – 74F374
3
4
7
8
13 14 17 18
3
4
7
8
13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
11
E
11
CP
OE
OE
1
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9 12 15 16 19
2
5
6
9 12 15 16 19
V
= Pin 20
CC
V
= Pin 20
CC
GND = Pin 10
GND = Pin 10
SF00254
SF00251
IEC/IEEE SYMBOL – 74F373
IEC/IEEE SYMBOL – 74F374
1
1
EN1
EN1
11
C2
11
EN2
2
3
2D
1
3
2
2D
1
5
6
4
7
5
6
9
4
7
9
8
8
12
15
16
19
13
13
12
15
16
19
14
14
17
18
17
18
SF00252
SF00255
3
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
LOGIC DIAGRAM FOR 74F373
D0
D1
4
D2
D3
D4
13
D5
14
D6
17
D7
18
3
7
8
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
Q
Q
Q
Q
Q
Q
Q
Q
11
1
E
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
SF00256
Q0
Q1
Q2
Q3
V
= Pin 20
CC
GND = Pin 10
LOGIC DIAGRAM FOR 74F374
D0
D1
4
D2
D3
D4
13
D5
14
D6
17
D7
18
3
7
8
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
Q
Q
Q
Q
Q
Q
Q
Q
11
1
CP
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
V
= Pin 20
CC
GND = Pin 10
Q0
Q1
Q2
Q3
SF00257
FUNCTION TABLE FOR 74F373
INPUTS
OUTPUTS
Q0 - Q7
INTERNAL
REGISTER
OPERATING MODE
OE
L
E
H
H
↓
Dn
L
L
H
L
H
Enable and read register
L
H
l
L
L
L
Latch and read register
Hold
L
↓
h
H
H
L
L
X
NC
NC
Dn
NC
Z
H
L
X
Disable outputs
H
H
Dn
Z
NOTES:
H
h
L
l
=
=
=
=
High-voltage level
HIGH state must be present one set-up time before the HIGH-to-LOW enable transition
Low-voltage level
LOW state must be present one set-up time before the HIGH-to-LOW enable transition
No change
NC=
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
HIGH-to-LOW enable transition
4
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
FUNCTION TABLE FOR 74F374
INPUTS
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
OPERATING MODE
OE
L
CP
↑
Dn
l
L
L
H
Load and read register
L
↑
h
H
L
↑
X
NC
NC
Dn
NC
Z
Hold
H
↑
X
Disable outputs
H
↑
Dn
Z
NOTES:
H
h
L
l
=
=
=
=
High-voltage level
HIGH state must be present one set-up time before the LOW-to-HIGH clock transition
Low-voltage level
LOW state must be present one set-up time before the LOW-to-HIGH clock transition
NC=
No change
Don’t care
High impedance “off” state
LOW-to-HIGH clock transition
Not LOW-to-HIGH clock transition
X
Z
↑
=
=
=
=
↑
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in HIGH output state
Current applied to output in LOW output state
Operating free air temperature range
Storage temperature range
–0.5 to V
48
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
2.0
–
NOM
MAX
5.5
–
Supply voltage
V
5.0
–
V
V
CC
IH
IL
V
V
HIGH-level input voltage
LOW-level input voltage
Input clamp current
–
0.8
–18
–3
V
I
I
I
–
–
mA
mA
mA
°C
Ik
HIGH-level output current
LOW-level output current
–
–
OH
OL
–
–
24
T
amb
Operating free air temperature range
0
–
+70
5
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
2
MIN TYP
MAX
±10%V
2.4
V
V
CC
V
V
= MIN, V = MAX,
IL
CC
IH
V
OH
HIGH-level output voltage
= MIN, I = MAX
OH
±5%V
2.7
3.4
CC
±10%V
0.35
0.35
0.50
0.50
V
CC
CC
V
V
= MIN, V = MAX,
IL
CC
V
V
LOW-level output voltage
OL
= MIN, I = MAX
IH
OL
±5%V
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73 –1.2
V
IK
I
I
I
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0 V
100
20
µA
µA
mA
µA
µA
mA
mA
mA
I
I
= MAX, V = 2.7 V
IH
I
Low-level input current
= MAX, V = 0.5 V
–0.6
50
IL
I
Off-state output current, high-level voltage applied
Off-state output current, low-level voltage applied
= MAX, V = 2.7 V
O
OZH
OZL
OS
CC
= MAX, V = 0.5 V
–50
–150
O
3
Short-circuit output current
= MAX
= MAX
–60
Supply current (total)
74F373
74F374
35
57
60
86
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5 V, T = 25 °C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25 °C
T
= 0 °C to +70 °C
= +5.0 V ± 10%
CC
amb
amb
SYMBOL
PARAMETER
TEST
V
= +5.0 V
V
UNIT
CC
CONDITION
C = 50 pF; R = 500 Ω C = 50 pF; R = 500 Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
3.0
2.0
5.3
3.7
7.0
5.0
3.0
2.0
8.0
6.0
PLH
PHL
Waveform 3
Waveform 2
ns
ns
ns
t
t
Propagation delay
E to Qn
5.0
3.0
9.0
4.0
11.5
7.0
5.0
3.0
12.0
8.0
PLH
PHL
74F373
t
t
Output enable time
to HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
5.0
5.6
11.0
7.5
2.0
2.0
11.5
8.5
PZH
PZL
t
t
Output disable time
from HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
4.5
3.8
6.5
5.0
2.0
2.0
7.0
6.0
PHZ
PLZ
ns
ns
ns
f
Maximum clock frequency
Waveform 1
Waveform 1
150
165
140
max
t
t
Propagation delay
CP to Qn
3.5
3.5
5.0
5.0
7.5
7.5
3.0
3.0
8.5
8.5
PLH
PHL
74F374
t
t
Output enable time
to HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
9.0
5.3
11.0
7.5
2.0
2.0
12.0
8.5
PZH
PZL
ns
ns
t
t
Output disable time
from HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
5.3
4.3
6.0
5.5
2.0
2.0
7.0
6.5
PHZ
PLZ
6
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
AC SET-UP REQUIREMENTS
LIMITS
T
= +25 °C
T
= 0 °C to +70 °C
= +5.0 V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
= +5.0 V
UNIT
CC
CC
CONDITION
C = 50 pF, R = 500 Ω C = 50 pF, R = 500 Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Set-up time, HIGH or LOW level
Dn to E
0
1.0
0
1.0
Waveform 4
ns
t (H)
Hold time, HIGH or LOW level
Dn to E
74F373
74F374
3.0
3.0
3.0
3.0
h
Waveform 4
Waveform 1
Waveform 5
ns
ns
ns
t
h
(L)
t
w
(H)
E Pulse width, HIGH
3.5
4.0
t
su
t
su
(H)
(L)
Set-up time, HIGH or LOW level
Dn to CP
2.0
2.0
2.0
2.0
t (H)
Hold time, HIGH or LOW level
Dn to CP
0
0
0
0
h
Waveform 5
Waveform 5
ns
ns
t
h
(L)
t
w
t
w
(H)
(L)
CP Pulse width,
HIGH or LOW
3.5
4.0
3.5
4.0
AC WAVEFORMS
For all waveforms, V = 1.5 V.
M
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Dn
V
V
M
1/f
M
max
CP
V
V
M
t
PHL
V
M
t
M
PLH
t
(H)
w
t
t
(L)
t
PHL
PLH
w
Qn
V
V
M
M
V
V
Qn
M
M
SF00260
SF00258
Waveform 3. Propagation delay for data to output
Waveform 1. Propagation delay for clock input to output,
clock pulse widths, and maximum clock frequency
Dn
E
V
V
V
V
M
M
M
M
t
(L)
t (L)
h
t
(H)
t
(H)
t (H)
h
su
w
su
E
V
M
V
V
t
M
M
V
V
M
M
t
PHL
PLH
V
SF00261
Qn
V
M
M
Waveform 4. Data set-up time and hold times
SF00259
Waveform 2. Propagation delay for enable to output
and enable pulse width
7
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
AC WAVEFORMS (continued)
For all waveforms, V = 1.5 V.
M
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Dn
V
V
V
V
M
M
M
M
OEn
V
t
V
M
M
t
(L)
t (L)
h
t
(H)
t (H)
h
su
su
t
PZL
PLZ
CP
V
M
V
M
V
M
Qn, Qn
V
+0.3V
OL
SF00262
Waveform 5. Data set-up time and hold times
SF00264
Waveform 7. 3-State output enable time to LOW level
and output disable time from LOW level
OEn
V
V
M
M
V
-0.3V
OH
t
t
PHZ
PZH
Qn, Qn
V
M
0V
SF00263
Waveform 6. 3-State output enable time to HIGH level
and output disable time from HIGH level
TEST CIRCUIT AND WAVEFORMS
SWITCH POSITION
t
w
AMP (V)
0V
TEST
SWITCH
closed
open
90%
90%
7.0V
V
CC
NEGATIVE
PULSE
t
, t
PLZ PZL
V
V
M
M
All other
10%
10%
R
L
V
V
OUT
IN
t
t )
t
t )
THL ( f
TLH ( r
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
TLH ( r
THL ( f
R
C
R
L
AMP (V)
0V
T
L
90%
M
90%
POSITIVE
PULSE
V
V
M
Test circuit for 3-state outputs
DEFINITIONS:
10%
10%
t
w
Input pulse definition
R
C
Load resistor; see AC electrical characteristics for value.
L =
L =
INPUT PULSE REQUIREMENTS
V
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
family
rep. rate
t
t
t
THL
amplitude
M
w
TLH
R
T =
Termination resistance should be equal to Z
generators.
of pulse
OUT
74F
3.0V
1.5V
1MHz
500ns 2.5ns
2.5ns
SF00265
8
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
9
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
10
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
11
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
REVISION HISTORY
Rev
Date
Description
_3
20021120
Product data; third version (9397 750 10758). Supersedes 74F373_374_2 dated 1994 Dec 05
(9397 750 05119).
Engineering Change Notice 853–0369 29206 (date: 20021115).
Modifications:
• Corrected ordering information table (from ‘N74374DB’ to ‘74F374DB’).
• Add SSOP20 (SOT339-1) package outline drawing.
_2
19941205
Product data; second version (9397 750 05119).
Engineering Change Notice 853–0369 14383 (date: 19941205).
12
2002 Nov 20
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 11-02
9397 750 10758
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号：
N74F377AD-T
IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOL-20, FF/Latch
NXP
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