N74F395N [NXP]
4-bit cascadable shift register 3-State; 4位可级联移位寄存器三态
| 型号： | N74F395N |
| 厂家： | 
NXP |
| 描述： | 4-bit cascadable shift register 3-State |
| 文件： | 总7页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
FEATURES
PIN CONFIGURATION
• 4-bit parallel load shift register
MR
Ds
D0
D1
D2
1
2
3
4
5
16
V
CC
• Independent 3-State buffer outputs, Q0–Q3
• Separate Qs output for serial expansion
• Asynchronous Master Reset
15 Q0
14 Q1
13 Q2
12 Q3
11 Qs
10 CP
D3
6
DESCRIPTION
The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0! Q1! Q2! Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.
PE
7
8
GND
9
OE
SF00940
TYPICAL SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F395
120MHz
32mA
ORDERING INFORMATION
The Master Reset (MR) is an asynchronous active-Low input. When
Low, the MR overrides the clock and all other inputs and clears the
register.
COMMERCIAL RANGE
DESCRIPTION
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
The 3-state output buffers are designed to drive heavily loaded
3-State buses, or large capacitive loads.
16-pin plastic DIP
16-pin plastic SO
N74F395N
N74F395D
The active-Low Output Enable (OE) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
LOAD VALUE
74F (U.L.)
HIGH/LOW
PINS
DESCRIPTION
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
3.0mA/24mA
D0 – D3
Ds
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
Serial data input
Parallel Enable input
PE
MR
Master Reset input (active Low)
Output Enable input (active Low)
Clock Pulse input (active falling edge)
Serial expansion output
OE
CP
Qs
Q0–Q3
Data outputs (3-State)
150/40
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1
1990 Oct 23
853–0370 00780
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
LOGIC SYMBOL
IEC/IEEE SYMBOL (IEEE/IEC)
1
SRG4
R
2
3
4
5
6
9
EN4
7
M1[LOAD]
M2[SHIFT]
Ds D0 D1
D2
D3
PE
7
10
C3/2!
CP
OE
10
9
Qs
11
2
3
2,3D
1,3D
15
4
4
MR
1
Q0
15
Q1
14
Q2
Q3
1,3D
14
13
4
5
6
13 12
12
11
V
=
=
Pin 16
Pin 8
CC
GND
SF00941
SF00942
LOGIC DIAGRAM
9
OE
10
CP
1
MR
7
PE
2
Q
Ds
CP
R
3
D0
15
14
13
S
Q
Q0
Q1
Q2
CLR
CLR
CLR
Q
Q
CP
R
S
4
D1
Q
Q
CP
R
S
5
D2
Q
Q
CP
R
S
6
D3
12
11
Q3
Qs
CLR
V
= Pin 16
CC
SF00943
GND = Pin 8
2
1990 Oct 23
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
MODE SELECT–FUNCTION TABLE
H = High voltage level
REGISTER
OPERATING
MODES
INPUTS
OUTPUTS
h
=
High voltage level one set-up time prior to the High-to-Low
clock transition
MR CP PE Ds Dn Q0 Q1 Q2 Q3
L
l
=
=
Low voltage level
Low voltage level one set-up time prior to the High-to-Low
clock transition
L
X
X
l
X
l
X
X
X
l
L
L
L
L
L
Reset (clear)
Shift right
qn = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the High-to-Low clock
transition
H
H
H
H
q0 q1 q2
q0 q1 q2
l
h
X
X
H
L
X
Z
=
=
=
Don’t care
High impedance “OFF” state
High-to-Low clock transition
h
h
L
L
L
Parallel load
h
H
H
H
H
3-STATE BUFFER
OPERATING
MODES
INPUTS
OUTPUTS
OE Qn (Register) Q0, Q1, Q2, Q3 Qs
L
L
L
H
L
L
H
Z
Z
L
H
L
Read
H
H
Disable buffers
H
H
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +5.5
40
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
Voltage applied to output in High output state
Qs
mA
mA
°C
°C
I
Current applied to output in Low output state
OUT
Q0–Q3
48
T
amb
Operating free-air temperature range
Storage temperature range
0 to +70
–65 to +150
T
stg
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
NOM
MAX
V
Supply voltage
4.5
2.0
5.0
5.5
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
–1
V
I
IK
mA
mA
mA
mA
mA
°C
Qs
I
High-level output current
Low-level output current
OH
OL
Q0–Q3
Qs
–3
20
I
Q0–Q3
24
T
amb
Operating free-air temperature range
0
70
3
1990 Oct 23
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
2
MIN
2.5
2.7
2.4
2.7
TYP
±10%V
V
V
V
V
CC
Qs
I
=–1mA
=–3mA
OH
V
V
V
= MIN,
CC
IL
±5%V
3.4
CC
= MAX,
=MIN
V
OH
High-level output voltage
±10%V
CC
CC
IH
Q0–Q3
I
OH
±5%V
V
V
V
= MIN,
= MAX,
= MIN,
±10%V
±5%V
0.35
0.35
0.50
0.50
V
V
CC
IL
CC
V
V
Low-level output voltage
Input clamp voltage
I
= MAX
OL
OL
IH
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
–0.73
–1.2
100
20
V
IK
I
IK
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
µA
µA
mA
I
I
= MAX, V = 2.7V
IH
IL
I
Low-level input current
= MAX, V = 0.5V
–0.6
I
Off-state output current High
level of voltage applied
Q0–Q3
only
I
V
CC
= MAX, V = 2.7V
50
µA
OZH
O
Off-state output current Low
level of voltage applied
Q0–Q3
only
I
I
V
V
= MAX, V = 0.5V
–50
–150
48
µA
mA
mA
OZL
CC
O
3
Short-circuit output current
= MAX
–60
OS
CC
MR=PE=Dn=Ds=4.5V,
OE=GND, CP=
I
33
35
32
CCH
MR=OE=Dn=Ds=GND,
PE=4.5V, CP=
I
Supply current (total)
V
CC
= MAX
I
50
46
mA
mA
CC
CCL
MR=Dn=Ds=GND,
OE=4.5V
I
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4
1990 Oct 23
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
amb
= +5V
= +25°C
V
amb
= +5V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
105
120
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
3.5
5.0
6.0
8.0
8.5
11.0
3.5
5.0
9.5
11.5
PLH
PHL
t
t
Propagation delay
CP to Qs
4.5
5.5
6.0
7.5
8.5
10.0
4.0
5.0
9.5
10.5
PLH
PHL
Waveform 1
Waveform 2
Waveform 2
ns
ns
ns
ns
ns
Propagation delay
MR to Qn
t
t
5.0
4.5
7.5
7.0
10.0
9.0
5.0
4.5
10.5
9.5
PHL
Propagation delay
MR to Qs
PHL
t
t
Output Enable time
to High or Low level
Waveform 4
Waveform 5
4.0
3.5
6.5
6.0
9.0
8.0
4.0
3.5
10.0
8.5
PZH
PZL
t
t
Output Disable time
from High or Low level
Waveform 4
Waveform 5
1.0
1.0
2.5
3.5
4.5
5.5
1.0
1.0
5.5
6.5
PHZ
PLZ
AC SETUP REQUIREMENTS
LIMITS
V
amb
= +5V
= +25°C
V
amb
= +5V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
2.5
1.5
3.0
2.0
s
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 1
Waveform 2
Waveform 2
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
1.5
1.5
1.5
1.5
h
t (L)
h
t (H)
Setup time, High or Low
PE to CP
6.5
6.0
7.0
6.5
s
t (L)
s
t (H)
Hold time, High or Low
PE to CP
0
0
0
0
h
t (L)
h
t (H)
CP Pulse width
High or Low
5.0
4.0
5.5
4.5
W
t (L)
W
MR Pulse width
Low
t (L)
W
2.5
6.0
3.0
7.0
Recovery time
MR to CP
t
REC
5
1990 Oct 23
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
MR
V
V
M
M
CP
V
t
V
t
M
M
t
(L)
t
REC
w
t
(L)
t (H)
w
w
V
CP
M
PHL
PLH
t
PHL
Qn, Qs
V
V
V
Qn, Qs
M
M
M
SF00944
SF00945
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Widths, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
STABLE
M
Dn
Ds
V
V
M
V
V
M
M
OE
Qn
t
t
h
s
V
-0.3V
0V
OH
t
t
PHZ
PZH
STABLE
M
V
V
M
V
M
t
s
t
h
SF00343
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
PE
CP
V
V
V
t
V
M
M
M
M
t
t
h
t
h
s
s
V
V
M
M
V
t
V
M
M
OE
Qn
SF00946
t
PZL
PLZ
Waveform 3. Parallel Enable and
Data Setup Time and Hold Time
V
M
V
+0.3V
OL
SF00344
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
6
1990 Oct 23
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs and
Totem-Pole Output (Qs)
10%
10%
0V
t
w
SWITCH POSITION
TEST
Input Pulse Definition
SWITCH
closed
closed
open
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
family
V
M
rep. rate
t
t
t
amplitude
w
TLH
THL
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00957
7
1990 Oct 23
相关型号：
N74F398N
IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-20, FF/Latch
NXP
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