N74F410N [NXP]
Register stack . 16】4 RAM 3-State output register; 寄存器堆栈。 16 】 4 RAM三态输出寄存器
| 型号： | N74F410N |
| 厂家： | 
NXP |
| 描述： | Register stack . 16】4 RAM 3-State output register |
| 文件： | 总5页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Product specification
Register stack – 16×4 RAM 3-State output register
74F410
The 74F410 is fully compatible with all TTL
families.
while WE, CS, and CP are low, the contents
of the selected memory location follow these
changes provided setup and hold time criteria
are met.
FEATURES
• Edge triggered output register
• ypical access time of 19.5ns
TYPICAL
TYPICAL
ACCESS
TIME
SUPPLY
CURRENT
( TOTAL)
Read operation – When CS is low, WE is
high, and CP goes from low–to–high, the
contents of the memory location selected by
the address inputs (A0–A3) are edge–
triggered into the output register.
• Optimize for register stack operation
• 3–state outputs
TYPE
74F410
19.5ns
45mA
• 18–pin package
When WE is low, CS is low, CP goes from
low–to–high, the data at the data inputs is
edge–triggered into the output register. The
OE input controls the output buffers. When
OE is high the four outputs (Q0–Q3) are in a
high impedance or off state; when OE is low,
the outputs are determined by the state of the
FUNCTIONAL DESCRIPTION
Write operation – When the three control
inputs, write enable (WE), chip select (CS),
and clock (CP), are low the information on
the data inputs (D0–D3) is written into the
memory location selected by the address
inputs (A0–A3). If the input data changes
DESCRIPTION
The 74F410 is a register oriented high speed
64–bit read/write memory organized as
16–words by 4–bits. An edge–triggered 4–bit
output register allows new input data to be
written while previous data is held. 3–state
outputs are provided for maximum versatility.
output register.
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
DESCRIPTION
V
CC
amb
18–pin plastic DIP (300mil)
N74F410N
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
LOAD VALUE
HIGH/LOW
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
1.0/1.0
1.0/1.0
150/40
D0 – D3
A0 – A3
CP
Data inputs
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
3mA/24mA
Address inputs
Clock pulse input (active rising edge)
Chip select input (active low)
Output enable input (active low)
Write enable input (active low)
Data outputs
CS
OE
WE
Q0 – Q3
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
LOGIC SYMBOL
IEC/IEEE SYMBOL
3
17
15 13 11
0
4
0
15
5
6
1
2
3
4
5
18
V
CS
A
CC
D0 D1 D2 D3
17 D0
16 Q0
1
WE
3
4
5
6
1
2
7
8
A0
A1
A2
A3
CS
WE
CP
OE
2
A0
&
1
7
G1
G2
15
14
13
A1
A2
A3
D1
Q1
1C
&
6
7
8
D2
8
EN3
A1,2D
Q0 Q1 Q2 Q3
12 Q2
CP
OE
17
15
13
11
16
14
12
10
A3
11
10
D3
Q3
16 14 12 10
9
GND
V
= Pin 18
GND = Pin 9
CC
1
January 8, 1990
853-1310 98498
Philips Semiconductors FAST Products
Product specification
Register stack – 16×4 RAM 3-State output register
74F410
LOGIC DIAGRAM
8
OE
3
A0
4
A1
A2
A3
RAM
Address
decoder
16
5
6
17
4
D0
D1
D2
D3
16
14
12
10
15
13
11
Q0
Q1
Q2
Q3
Data
inputs
16
Register
15
13
11
WE
CS
CP
V
= pin
CC
18
GND = pin 9
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Storage temperature range
–0.5 to V
V
OUT
CC
48
mA
°C
°C
OUT
T
amb
0 to +70
T
stg
–65 to +150
2
January 8, 1990
Philips Semiconductors FAST Products
Product specification
Register stack – 16×4 RAM 3-State output register
74F410
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
UNIT
MAX
MIN
4.5
V
Supply voltage
5.5
V
V
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
0.8
–18
–3
V
I
I
I
mA
mA
mA
Ik
High–level output current
Low–level output current
OH
OL
24
T
amb
Operating free air temperature range
0
+70
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
1
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
2
MIN
2.4
TYP
MAX
V
High-level output voltage
V
V
V
V
= MIN, V = MAX
V
V
V
V
±10%V
±5%V
OH
CC
IL
CC
= MIN, I = MAX
2.7
IH
OH
CC
V
OL
Low-level output voltage
= MIN, V = MAX
0.35
0.35
-0.73
0.50
0.50
±10%V
CC
IL
CC
CC
= MIN, I = MAX
±5%V
IH
OL
V
IK
Input clamp voltage
V
V
= MIN, I = I
IK
-1.2
100
V
CC
I
µA
I
I
Input current at maximum input voltage
= MAX, V = 7.0V
I
CC
µA
mA
mA
I
I
High–level input current
V
V
= MAX, V = 2.7V
20
IH
CC
I
Low–level input current
others
= MAX, V = 0.5V
-0.6
-1.2
IL
CC
I
CP, CS
Offset–output current,
high–level voltage applied
I
I
V
V
= MAX, V = 2.7V
50
µA
µA
OZH
CC
I
Offset–output current,
low–level voltage applied
= MAX, V = 0.5V
–50
OZL
CC
I
3
I
I
Short-circuit output current
V
V
= MAX
= MAX
-60
-150
70
mA
mA
OS
CC
Supply current (total)
45
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
3
January 8, 1990
Philips Semiconductors FAST Products
Product specification
Register stack – 16×4 RAM 3-State output register
74F410
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation dealy
CP to Qn
4.0
4.5
6.5
6.5
8.5
9.0
3.5
4.0
9.5
10.0
PLH
PHL
Waveform 1
Waveform 3, 4
Waveform 3, 4
ns
ns
ns
t
t
Output enable time
OE to Qn
3.0
4.5
4.5
6.0
7.5
9.0
2.5
3.5
8.5
9.5
PZH
PZL
t
t
Output disable time
OE to Qn
2.0
2.0
3.5
3.5
6.0
6.5
1.5
2.0
6.5
7.0
PHZ
PHL
AC SETUP REQUIREMENTS FOR READ MODE
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
1
t
(L)
Setup time, low, CS to CP
Waveform 1
Waveform 1
4.0
3.5
4.5
4.5
ns
ns
su
1
t (L)
h
Hold time, low, CS to CP
t
t
(H)
(L)
Setup time, high or low
An to CP
13.0
13.0
15.0
15.0
su
su
Waveform 1
Waveform 1
ns
ns
1
t (H)
Hold time, high or low
0
0
0
0
h
1
t (L)
h
An to CP
1
t
(H)
Setup time, high, WE to CP
Waveform 1
Waveform 1
Waveform 1
13.0
0
15.0
0
ns
ns
ns
su
1
t (H)
h
Hold time, high, WE to CP
t (L)
w
CP pulse width, low
5.0
6.0
NOTE:
1. Low–to–high clock transition.
AC SETUP REQUIREMENTS FOR WRITE MODE
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
An to WE, CS, CP
0
0
0
0
su
su
Waveform 2
Waveform 2
Waveform 2
Waveform 2
ns
ns
ns
ns
t (H)
Hold time, high or low
An to WE, CS, CP
0
0
0
0
h
t (L)
h
t
su
t
su
(H)
(L)
Setup time, high or low
Dn to WE, CS, CP
6.0
6.0
8.0
8.0
t (H)
Hold time, high or low
Dn to WE, CS, CP
0
0
0
0
h
t (L)
h
t (L)
WE pulse width, low
CS pulse width, low
CP pulse width, low
Waveform 2
Waveform 2
Waveform 2
7.0
6.0
7.0
8.0
7.0
8.0
ns
ns
ns
w
t (L)
w
t (L)
w
4
January 8, 1990
Philips Semiconductors FAST Products
Product specification
Register stack – 16×4 RAM 3-State output register
74F410
AC WAVEFORMS
V
CS
V
V
V
M
M
M
M
M
OE
Qn
V
V
M
M
t
(L)
(H)
t
t
(L)
h
h
t
(L)
t
t
(L)
V
-0.3V
0V
su
su
OH
t
t
PHZ
PZH
WE
V
V
V
V
M
M
M
V
M
t
(H)
M
h
h
(H)
su
t
(H)
M
su
Waveform 3. 3-State output enable time to high level
and output disable time from high level
An
V
V
V
V
M
M
t
(H)
t
(L)
h
h
t
(L)
t
(H)
su
su
OE
V
V
M
M
CP
Qn
V
V
M
V
t
M
M
t
t
PLZ
PZL
t
(H)
w
t
PHL
PLH
V
Qn
M
V
V
M
M
V
+0.3V
OL
Waveform 1. Read cycle timing
Waveform 4. 3-State output enable time to low level
and output disable time from low level
An,
Dn
V
V
V
V
M
M
M
M
t
(L)
h
t
(L)
t
(H)
t
(H)
su
su
h
t
(L)
w
CS
WE
CP
V
V
V
V
M
M
M
M
Waveform 2. Write cycle timing
NOTES:
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORM
t
AMP (V)
0V
W
V
CC
90%
90%
NEGATIVE
PULSE
7.0V
V
V
M
M
10%
10%
R
L
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
)
)
t
t )
THL ( f
TLH ( r
t
t
R
C
R
t
t )
TLH ( r
T
L
L
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test circuit for 3–state outputs
SWITCH POSITION
10%
10%
t
W
TEST
SWITCH
closed
open
t
, t
Input pulse definition
INPUT PULSE REQUIREMENTS
PLZ PZL
All other
family
DEFINITIONS:
V
M
rep. rate
t
t
t
THL
amplitude
W
TLH
R
C
=
=
Load resistor; see AC electrical characteristics for
value.
Load capacitance includes jig and probe
capacitance; see AC electrical characteristics for
value
L
L
74F
3.0V
1.5V
1MHz
500ns 2.5ns
2.5ns
R
T
=
Termination resistance should be equal to Z
pulse generators.
of
OUT
5
January 8, 1990
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