N74F539N [NXP]
Dual 1-of-4 decoder 3-State; 1 -的-4双解码器三态
| 型号： | N74F539N |
| 厂家： | 
NXP |
| 描述： | Dual 1-of-4 decoder 3-State |
| 文件： | 总5页 (文件大小：47K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Dual 1-of-4 decoder (3-State)
74F539
DESCRIPTION
PIN CONFIGURATION
The 74F539 contains two independent decoders. Each accepts two
address (A0 - A1) input signals and decodes them to select one of
four mutually exclusive outputs. A Polarity control (P) input
determines whether the outputs are active Low (P=H) or active High
(P=L). An active-Low Enable (E) is available for data demultiplexing.
Data is routed to the selected output in non-inverted or inverted form
in the active-Low mode or inverted form in the active-High mode. A
High signal on the Output Enable (OEn) input forces the 3-State
outputs to the high impedance state.
Q2b
Q1b
Q0b
Pb
V
1
2
3
4
5
20
19
18
17
16
CC
Q3b
A1b
A0b
Eb
OEb
A0a
A1a
Q3a
Q2a
Ea
6
7
8
9
15
14
13
OEa
Pa
TYPICAL SUPPLY
TYPICAL
PROPAGATION DELAY
CURRENT
(TOTAL)
TYPE
12 Q0a
74F539
7.5ns
40mA
Q1a
GND 10
11
SF01013
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
20-Pin Plastic DIP
20-Pin Plastic SOL
N74F539N
N74F539D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
LOAD VALUE
PINS
A0a - A1a
DESCRIPTION
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
150/40
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
3.0mA/24mA
Decoder A Address inputs
Decoder B Address inputs
Enable inputs (active Low)
A0b - A1b
Ea, Eb
OEa, OEb
Pa, Pb
Output Enable inputs (active Low)
Polarity control inputs
Q0a–Q3a
Q0b–Q3b
Decoder A Data outputs
Decoder A Data outputs
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
6
7
17
18
DMUX
4
5
N4
EN
3
2
A0a
A1a
A0b
A1b
0,4
1,4
2,4
3,4
Pa
Ea
13
15
17
18
0
1
0
3
14
4
OEa
Pb
G
1
19
16
13
16
5
Eb
12
11
9
14
6
OEb
Q0a Q1a Q2a Q3a Q0b Q1b
Q2b Q3b
7
8
15
V
= Pin 20
CC
12
11
9
8
3
2
1
19
GND = Pin 10
SF01014
SF01015
1
1990 Feb 23
853–1274 98905
Philips Semiconductors
Product specification
Dual 1-of-4 decoder (3-State)
74F539
LOGIC DIAGRAM
7, 18
A1n
6, 17
A0n
15, 16
En
13, 4
Pn
14, 5
OEn
12, 3
Q0n
11, 2
Q1n
9, 1
Q2n
8, 19
Q3n
V
=
=
Pin 20
Pin 10
CC
GND
SF01016
FUNCTION TABLE
INPUTS
A1n
OUTPUTS
Q1n Q2n
OPERATING MODE
OE
H
En
X
A0n
X
Q0n
Q3n
n
X
X
Z
Z
Z
Z
High Impedance
Disable
L
H
X
Qn=P
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
Active High output
(P = L)
H
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
Active Low output
(P = H)
H
H
H = High voltage level
= Low voltage level
X = Don’t care
Z = High impedance “off” state
L
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
V
Supply voltage
Input voltage
Input current
CC
V
IN
I
IN
mA
V
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
48
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
2
1990 Feb 23
Philips Semiconductors
Product specification
Dual 1-of-4 decoder (3-State)
74F539
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
SYMBOL
PARAMETER
UNIT
MAX
MIN
4.5
V
CC
V
IH
V
IL
Supply voltage
5.0
5.5
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–3
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature range
OH
OL
24
T
amb
0
70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.4
TYP
MAX
±10%V
V
V
V
V
V
CC
V
V
= MIN, V = MAX,
IL
CC
IH
V
OH
High-level output voltage
= MIN, I = MAX
OH
±5%V
2.7
3.4
0.35
0.35
–0.73
CC
±10%V
0.50
0.50
–1.2
CC
CC
V
CC
= MIN, V = MAX,
IL
V
V
Low-level output voltage
Input clamp voltage
OL
V
= MIN, I = MAX
IH
OL
±5%V
V
CC
= MIN, I = I
I IK
IK
Input current at maximum input
voltage
I
I
V
CC
= MAX, V = 7.0V
100
µA
I
I
I
High-level input current
Low-level input current
V
V
= MAX, V = 2.7V
20
µA
IH
CC
I
= MAX, V = 0.5V
–0.6
mA
IL
CC
I
Off-state output current
High-level voltage applied
I
V
= MAX, V = 2.7V
50
µA
µA
OZH
CC
CC
O
Off-state output current
Low-level voltage applied
I
I
V
= MAX, V = 0.5V
–50
OZL
O
3
Short-circuit output current
V
CC
= MAX
–60
–150
50
mA
mA
mA
mA
OS
I
I
35
40
40
CCH
I
Supply current
I
V
CC
= MAX
55
CC
CCL
60
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I should be performed last.
OS
3
1990 Feb 23
Philips Semiconductors
Product specification
Dual 1-of-4 decoder (3-State)
74F539
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
An to Qn
4.5
3.0
8.5
8.0
12.5
12.5
4.0
3.0
13.5
13.0
ns
ns
PLH
PHL
Waveform 1
Waveform 2
Waveform 1
Waveform 2
t
t
Propagation delay
En to Qn
5.0
3.0
7.5
7.0
11.0
11.0
4.5
3.0
12.0
11.5
ns
ns
PLH
PHL
t
t
Propagation delay
Pn to Qn
4.0
3.5
6.5
5.5
9.5
9.0
3.5
3.0
10.5
9.5
ns
ns
PLH
PHL
t
t
Propagation delay
Pn to Qn (INV)
6.0
4.0
11.5
6.0
14.5
9.0
5.0
4.0
15.5
9.5
ns
ns
PLH
PHL
t
t
Output Enable time
OEn to Qn
Waveform 3
Waveform 4
2.5
5.5
4.0
7.0
7.5
10.5
2.0
5.0
8.5
11.5
ns
ns
PZH
PZL
t
t
Output Disable time
OEn to Qn
Waveform 3
Waveform 4
1.5
2.0
3.0
4.0
6.0
8.0
1.0
1.5
6.5
8.5
ns
ns
PHZ
PLZ
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
En, Pn
V
V
M
M
An, Pn
Qn
V
V
M
M
t
t
PLH
PHL
t
t
PHL
PLH
Qn
V
V
M
M
V
V
M
M
SF01017
SF01018
Waveform 1. Propagation Delay for
Non-Inverting Outputs
Waveform 2. Propagation Delay for
Inverting Outputs
OEn
Qn
V
V
OEn
Qn
V
V
M
M
t
M
t
M
t
V
-0.3V
0V
OH
t
PZL
PLZ
PZH
PHZ
V
V
M
M
V
+0.3V
OL
SF01020
SF01019
Waveform 3. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
4
1990 Feb 23
Philips Semiconductors
Product specification
Dual 1-of-4 decoder (3-State)
74F539
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
M
R
L
M
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
0V
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
t
t
amplitude
w
TLH
THL
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00777
5
1990 Feb 23
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