N74F543DB [NXP]
Octal latched transceiver with dual enable; 3-state; 八进制锁存收发器采用双能;三态
| 型号： | N74F543DB |
| 厂家： | 
NXP |
| 描述： | Octal latched transceiver with dual enable; 3-state |
| 文件： | 总15页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74F543
Octal latched transceiver with dual enable; 3-state
Rev. 04 — 26 January 2010
Product data sheet
1. General description
The 74F543 octal latched transceiver contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output
enable (OEAB, OEBA) inputs are provided for each register to permit independent control
of data transfer in either direction. The A outputs are guaranteed to sink 24 mA while the B
outputs are rated for 64 mA.
2. Features
I Combines 74F245 and 74F373 type functions in one device
I 8-bit octal transceiver with D-type latch
I Back-to-back registers for storage
I Separate controls for data flow in each direction
I A output capability: +20 mA to −3 mA
I B output capability: +64 mA to −15 mA
I 3-state outputs for bus-oriented applications
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
N74F543D
0 °C to +70 °C
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
N74F543DB
0 °C to +70 °C
SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
4. Functional diagram
2
1EN3 (BA)
23
G1
1
1C5
3
4
5
6
7
8
9
10
13
2EN4 (AB)
11
G2
14
A0 A1 A2 A3 A4 A5 A6 A7
EAB
2C6
11
23
14
1
3
22
EBA
OEAB
OEBA
13
2
3
5D
4
5
21
20
19
18
17
16
15
LEAB
LEBA
2
6D
6
B0 B1 B2 B3 B4 B5 B6 B7
7
22 21 20 19 18 17 16 15
8
001aae900
9
10
001aae901
Fig 1. Logic symbol
Fig 2. IEC logic symbol
2
OEBA
13
OEAB
23
1
EBA
11
14
LEBA
EAB
LEAB
DETAIL A
22
D
Q
B0
LE
3
A0
Q
D
LE
4
5
21
20
19
18
17
16
15
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
6
7
DETAIL A × 7
8
9
10
001aae902
Fig 3. Logic diagram
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
2 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
5. Pinning information
5.1 Pinning
74F543
1
2
24
23
22
21
20
19
18
17
16
15
14
13
LEBA
OEBA
A0
V
CC
EBA
B0
3
4
A1
B1
5
A2
B2
6
A3
B3
7
A4
B4
8
A5
B5
9
A6
B6
10
11
12
A7
B7
EAB
GND
LEAB
OEAB
001aal173
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
Unit load
HIGH/LOW
Load value[1]
HIGH/LOW
LEBA
1
2
B-to-A latch enable input (active LOW)
B-to-A output enable input (active LOW)
1.0/1.0
1.0/1.0
20 µA/0.6 mA
20 µA/0.6 mA
OEBA
A0 to A7
3, 4, 5, 6, 7, 8, 9, data input or output
10
inputs 3.5/1.0;
outputs 150/40
inputs 70 µA/0.6 mA;
outputs 3.0 mA/24 mA
EAB
11
12
13
14
A-to-B enable input (active LOW)
1.0/2.0
20 µA/1.2 mA
GND
ground (0 V)
OEAB
LEAB
B0 to B7
A-to-B output enable input (active LOW)
A-to-B latch enable input (active LOW)
data input or output
1.0/1.0
20 µA/0.6 mA
1.0/1.0
20 µA/0.6 mA
22, 21, 20, 19,
18, 17, 16, 15
inputs 3.5/1.0;
outputs 750/106.7 outputs 15 mA/64 mA
inputs 70 µA/0.6 mA;
EBA
VCC
23
24
B-to-A enable input (active LOW)
positive supply voltage
1.0/2.0 20 µA/1.2 mA
[1] One FAST Unit Load (UL) is defined as 20 µA in HIGH state, 0.6 µA in LOW state.
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
3 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
6. Functional description
6.1 Function table
Table 3.
Function selection[1]
Input
Output
Status
OEXX
EXX
X
LEXX
An or Bn
Bn or An
H
X
L
X
X
L
X
X
h
l
Z
disabled
H
Z
↑
Z
disabled + latch
latch + display
transparent
hold
Z
L
L
L
L
L
L
↑
h
l
H
L
L
H
H
L
X
H
L
NC
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
6.2 Description
The 74F543 contains two sets of eight D-type latches, with separate control pins for each
set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output latch enable (OEAB) are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
4 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−30
Max
+7.0
+7.0
+5.5
+5
Unit
V
supply voltage
input voltage
[1]
[1]
V
VO
output voltage
input clamping current
output current
output in HIGH-state
VI < 0 V
V
IIK
mA
IO
output in LOW-state
pins A0 to A7
pins B0 to B7
in free air
-
48
mA
mA
°C
-
128
70
[2]
Tamb
Tstg
ambient temperature
storage temperature
0
−65
+150
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
4.5
2.0
-
Typ
Max
5.5
-
Unit
V
supply voltage
5.0
VIH
HIGH-level input voltage
LOW-level input voltage
input clamping current
HIGH-level output current
-
-
-
-
-
-
-
V
VIL
0.8
−18
-
V
IIK
-
mA
mA
mA
mA
mA
IOH
pins A0 to A7
pins B0 to B7
pins A0 to A7
pins B0 to B7
−3
−15
-
-
IOL
LOW-level output current
24
64
-
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
5 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
Conditions
25 °C
0 °C to 70 °C Unit
Min Typ[1] Max Min
Max
VIK
input clamping voltage
VCC = 4.5 V; IIK = −18 mA
VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V
pins A0 to A7; IOH = −3 mA
VCC = ±10 %
−1.2 −0.73
-
−1.2
-
V
VOH
HIGH-level output
voltage
-
-
-
-
-
2.4
2.7
-
-
V
V
VCC = ±5 %
3.4
pins B0 to B7; IOH = −15 mA
VCC = ±10 %
-
-
-
-
-
-
2.0
2.0
-
-
V
V
VCC = ±5 %
VOL
LOW-level output
voltage
VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V
pins A0 to A7; IOL = 24 mA
VCC = ±10 %
-
-
0.35
0.35
-
-
-
-
0.5
0.5
V
V
VCC = ±5 %
pins B0 to B7; IOL = 64 mA
VCC = ±10 %
-
-
-
-
-
-
-
0.55
0.55
V
V
VCC = ±5 %
0.42
II
input leakage current
VCC = 5.5 V
pins OEAB, OEBA, EAB;
VI = 7.0 V
-
-
-
-
100 µA
mA
other pins; VI = 5.5 V
-
-
-
-
-
-
-
-
1
IIH
IIL
HIGH-level input current VCC = 5.5 V; VI = 2.7 V
LOW-level input current VCC = 5.5 V; VI = 0.5 V
pins EAB, EBA
20 µA
-
-
-
-
-
-
-
-
−1.2 mA
−0.6 mA
other pins
IOZ
OFF-state output current VCC = 5.5 V
VO = 2.7 V; VI = 2.0 V
-
-
-
-
-
-
-
-
70 µA
VO = 0.5 V; VI = 0.8 V
−600 µA
[2]
IO
output current
supply current
VCC = 5.5 V
pins A0 to A7
-
-
−60
-
-
-
-
−150 mA
−225 mA
pins B0 to B7
−100
ICC
VCC = 5.5 V
outputs HIGH-state
outputs LOW-state
outputs OFF-state
-
-
-
70
95
95
-
-
-
-
-
-
105 mA
135 mA
135 mA
[1] All typical values are measured at VCC = 5 V.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
6 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter
Conditions
25 °C; VCC = 5.0 V
0 °C to 70 °C;
Unit
V
CC = 5.0 V ± 0.5 V
Min Typ Max
Min
3.0
2.5
4.5
5.5
2.5
2.5
4.0
4.0
1.5
4.0
3.0
4.5
1.0
2.0
1.0
3.0
0.0
1.5
3.0
3.0
0.0
0.0
2.0
2.0
4.5
Max
9.0
7.5
11.0
12.5
8.5
8.0
9.5
10.0
8.0
11.5
9.0
11.0
7.5
9.5
8.5
12.0
-
tPLH
LOW to HIGH
propagation delay
An to Bn; see Figure 5
Bn to An; see Figure 5
LEBA to An; see Figure 6
LEAB to Bn; see Figure 6
An to Bn; see Figure 5
Bn to An; see Figure 5
LEBA to An; see Figure 6
LEAB to Bn; see Figure 6
3.5
2.5
5.0
6.0
3.0
2.5
4.0
4.5
2.0
4.5
3.5
5.0
1.0
2.5
1.5
4.5
0.0
1.0
2.5
2.5
0.0
0.0
1.5
1.5
4.0
5.5
4.0
8.5
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.0 10.0
8.5 11.5
tPHL
HIGH to LOW
propagation delay
5.0
4.5
6.0
6.5
4.0
8.0
7.5
9.0
9.5
7.5
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWL
OFF-state to HIGH OEBA to An, OEAB to Bn; see Figure 7
propagation delay
EBA to An, EAB to Bn; see Figure 7
7.0 10.5
5.0 8.5
7.0 10.5
OFF-state to LOW OEBA to An, OEAB to Bn; see Figure 8
propagation delay
EBA to An, EAB to Bn; see Figure 8
HIGH to OFF-state OEBA to An, OEAB to Bn; see Figure 7
propagation delay
3.0
5.0
4.0
6.5
8.5
7.5
EBA to An, EAB to Bn; see Figure 7
LOW to OFF-state OEBA to An, OEAB to Bn; see Figure 8
propagation delay
EBA to An, EAB to Bn; see Figure 8
7.0 11.0
set-up time HIGH
set-up time LOW
hold time HIGH
hold time LOW
pulse width LOW
An to LEAB, Bn to LEBA; see Figure 9
An to EAB, Bn to EBA; see Figure 9
An to LEAB, Bn to LEBA; see Figure 9
An to EAB, Bn to EBA; see Figure 9
An to LEAB, Bn to LEBA; see Figure 9
An to EAB, Bn to EBA; see Figure 9
An to LEAB, Bn to LEBA; see Figure 9
An to EAB, Bn to EBA; see Figure 9
latch enable; see Figure 9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
7 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
11. Waveforms
V
I
An or Bn
GND
V
V
M
M
t
t
PHL
PLH
V
OH
Bn or An
V
V
M
M
V
OL
001aae904
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (An, Bn) to output (Bn, An)
V
I
V
V
M
LEBA, LEAB
GND
M
t
t
PHL
PLH
V
OH
V
M
V
M
An, Bn
V
OL
001aac761
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn)
V
I
OEAB, OEBA,
EAB, EBA
V
V
M
M
GND
t
t
PHZ
PZH
V
OH
V
− 0.3 V
OH
An, Bn
GND
V
M
001aae907
VM = 1.5 V
VOH is a typical voltage output level that occurs with the output load.
Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
8 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
V
I
OEAB, OEBA,
EAB, EBA
V
V
M
M
GND
t
t
PLZ
PZL
3.5 V
An, Bn
V
M
V
+ 0.3 V
OL
V
OL
001aae906
VM = 1.5 V
VOL is a typical voltage output level that occurs with the output load.
Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level
V
I
V
V
V
V
M
An, Bn
GND
M
M
M
t
t
t
t
h(L)
su(H)
h(H)
su(L)
t
WL
V
I
LEAB, LEBA,
V
V
M
M
EAB, EBA
GND
001aae905
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times and latch enable pulse width
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
9 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
EXT
V
V
M
M
V
CC
10 %
10 %
0 V
R
L
V
V
O
I
t
t
r
f
G
DUT
t
t
f
r
V
I
R
T
C
L
R
L
90 %
90 %
positive
pulse
V
M
V
M
mna616
10 %
10 %
0 V
t
W
001aai298
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Load circuitry for switching times
Table 8.
Input
VI
Test data
Load
CL
VEXT
fI
tW
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
tPZL, tPLZ
7.0 V
3.0 V
1 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
open
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
10 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 11. Package outline SOT137-1 (SO24)
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
11 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
Fig 12. Package outline SOT340-1 (SSOP24)
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
12 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
13. Abbreviations
Table 9.
Acronym
BiCMOS
DUT
Abbreviations
Description
Bipolar Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10. Revision history
Document ID
74F543_4
Release date
20100126
Data sheet status
Change notice
Supersedes
Product data sheet
-
74F543_3
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and.Section
12 “Package outline”
74F543_3
20040722
19941205
Product specification
Product specification
-
-
74F543_544_2
-
74F543_544_2
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
13 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74F543_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
14 of 15
74F543
NXP Semiconductors
Octal latched transceiver with dual enable; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 January 2010
Document identifier: 74F543_4
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