N74F646AD-T [NXP]
IC F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, Bus Driver/Transceiver;
| 型号： | N74F646AD-T |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, Bus Driver/Transceiver 输入元件 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总14页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648A
Octal transceiver/register, inverting
(3-State)
Product data
2003 Feb 04
Replaces 74F646/646A/74F648/648A dated 1990 Sep 25
Philips
Semiconductors
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
74F646A: Octal transceiver/register, non-inverting (3-State)
74F648A: Octal transceiver/register, inverting (3-State)
FEATURES
DESCRIPTION
The 74F646A and 74F648A transceivers/registers consist of bus
transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from
the input bus or the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes HIGH.
Output enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the
high impedance port may be stored in either the A or B register or
both.
• Combines 74F245 and two 74F374 type functions in one chip
• High impedance base inputs for reduced loading (70 µA in HIGH
and LOW states)
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of non-inverting and inverting data paths
• Controlled ramp outputs for 74F646A/74F648A
• 3-state outputs
The select pins (SAB, SBA) determine whether data is stored or
transferred through the device in real-time. The DIR determines
which bus will receive data when the OE is active LOW. In the
isolation mode (OE = HIGH), data from bus A may be stored in the
B register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
• 300 mil wide 24-pin slim DIP package
TYPE
TYPICAL f
TYPICAL SUPPLY CURRENT (TOTAL)
max
74F646A, 74F648A
185 MHz
105 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
PKG DWG #
V
CC
= 5 V ±10%, T
= 0 °C to +70 °C
amb
24-pin plastic slim DIP (300 mil)
24-pin plastic SOL
N74F646AN, N74F648AN
N74F646AD, N74F648AD
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH / LOW
PINS
DESCRIPTION
A0-A7, B0-B7
CPAB
A and B inputs
3.5 / 0.116
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
750 / 80
70 µA / 70 µA
20 µA / 20 µA
20 µA / 20 µA
20 µA / 20 µA
20 µA / 20 µA
20 µA / 20 µA
20 µA / 20 µA
15 mA / 48 mA
A-to-B clock input
B-to-A clock input
A-to-B select input
B-to-A select input
CPBA
SAB
SBA
DIR
Data flow directional control enable input
Output enable input
OE
A0 - A7, B0 - B7
A, B outputs for N74F646A/N74F648A
NOTE: One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
2
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
PIN CONFIGURATION
IEC/IEEE SYMBOL
74/646A
74F646A
21
3
G3
1
2
3
4
5
24
23
22
21
20
CPAB
SAB
DIR
A0
V
CC
3 EN1 [BA]
3 EN2 [AB]
CPBA
SBA
OE
B0
23
22
1
C4
G5
A1
C6
G7
2
6
7
19
18
17
16
15
14
13
B1
A2
B2
A3
20
1
1
5
5
4D
4
8
B3
A4
1
9
B4
A5
7
7
1
6D
2
1
10
11
12
B5
A6
5
19
B6
6
A7
18
17
16
15
14
13
7
B7
GND
8
SF00386
9
/
10
11
LOGIC SYMBOL
SF00388
74F646A
4
5
6
7
8
9
10 11
LOGIC DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7
74F646A
21
OE
1
2
CPAB
SAB
3
DIR
3
DIR
23
CPBA
22
23
CPBA
SBA
1
22
21
SBA
CPAB
OE
2
SAB
B0 B1 B2 B3 B4 B5 B6 B7
I of 8 channels
1D
C1
20 19 18 17 16 15 14 13
SF00387
V
= Pin 24
CC
GND = Pin 12
4
20
A0
B0
1D
C1
V
= Pin 24
CC
to 7 other channels
SF00393
GND = Pin 12
3
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
PIN CONFIGURATION
IEC/IEEE SYMBOL
74F648A
74F648A
21
3
G3
CPAB
SAB
DIR
A0
1
2
3
4
5
24 V
CC
3 EN1 [BA]
3 EN2 [AB]
23 CPBA
22 SBA
21 OE
23
22
1
C4
G5
A1
20 B0
C6
G7
2
A2
A3
A4
A5
6
7
8
9
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
20
1
1
5
5
4D
4
1
1
7
7
6D
2
1
A6 10
A7 11
5
19
6
18
17
16
15
14
13
7
GND 12
8
SF00389
9
10
11
LOGIC SYMBOL
SF00391
74F648A
4
5
6
7
8
9
10 11
LOGIC DIAGRAM
74F648A
21
A0 A1 A2 A3 A4 A5 A6 A7
OE
CPAB
SAB
DIR
1
2
3
DIR
23
CPBA
22
3
CPBA
SBA
OE
23
22
21
SBA
1
CPAB
2
SAB
B0 B1 B2 B3 B4 B5 B6 B7
I of 8 channels
1D
C1
20 19 18 17 16 15 14 13
SF00390
V
= Pin 24
CC
GND = Pin 12
4
20
A0
B0
1D
C1
to 7 other channels
SF00400
4
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
74F646A 74F648A
OE
X
DIR
X
CPAB CPBA SAB
SBA
X
An
Input
Bn
↑
X
↑
X
↑
X
X
X
X
X
X
L
Unspecified*
Input
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
X
X
X
Unspecified*
Input
H
H
L
X
↑
X
Input
X
H or L H or L
X
Input
Input
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
L
X
X
X
H or L
X
L
Output
Output
Input
Input
L
L
H
Input
L
H
H
X
X
Output
Output
L
H or L
X
H
X
Input
NOTES:
1. H = High-voltage level
2. L
3. X
4. ↑
5. *
=
=
=
=
Low-voltage level
Don’t care
LOW-to-HIGH clock transition
The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in HIGH output state
Current applied to output in LOW output state
Operating free air temperature range
Storage temperature range
–0.5 to V
72
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
LIMITS
UNIT
MIN
4.5
2.0
–
NOM
MAX
5.5
–
V
Supply voltage
5.0
–
V
V
CC
IH
IL
V
V
HIGH-level input voltage
LOW-level input voltage
Input clamp current
–
0.8
–18
–15
48
V
I
I
I
–
–
mA
mA
mA
°C
Ik
HIGH-level output current
LOW-level output current
–
–
OH
OL
–
–
T
amb
Operating free air temperature range
0
–
+70
5
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the 74F646A
and 74F648A. The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
BUS MANAGEMENT FUNCTIONS
STORAGE FROM
A, B, OR A AND B
REAL TIME BUS TRANSFER
BUS A TO BUS B
TRANSFER STORED DATA
TO A AND/OR B
REAL TIME BUS TRANSFER
BUS B TO BUS A
BUS A
BUS A
BUS A
BUS B
BUS B
BUS A
BUS B
BUS B
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
X
X
H
X
X
X
↑
X
↑
X
↑
↑
X
X
X
X
X
X
L
L
L
H
X
H or L
X
X
H
H
X
L
L
X
X
X
L
H or L
SF00392
6
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN
2.4
2.7
2.0
TYP
MAX
±10%V
±5%V
–
3.4
–
–
–
–
V
V
V
CC
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
I
= –3 mA
OH
V
OH
HIGH-level output voltage
CC
IH
I
= –15 mA ±10%V
OH
CC
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
V
LOW-level output voltage
Input clamp voltage
I
OL
= 48 mA ±10%V
–
0.38
0.55
V
OL
CC
IH
V
IK
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–
–
–
–
–
–0.73
–1.2
100
1
V
I
others
= 0.0 V, V = 7.0 V
–
–
–
–
µA
mA
µA
µA
I
Input current at maximum
input voltage
I
I
A0-A7, B0-B7
= MAX, V = 5.5 V
I
I
I
HIGH-level input current
LOW-level input current
= MAX, V = 2.7 V
20
IH
I
OE, DIR, CPAB,
CPBA, SAB, SBA
= MAX, V = 0.5 V
–20
IL
I
Off-state output current,
HIGH-level voltage applied
I
+ I
V
= MAX, V = 2.7 V
–
–
–
–
70
µA
µA
OZH
IH
CC
O
A0-A7, B0-B7
Off-state output current,
LOW-level voltage applied
I
I
+ I
V
V
= MAX, V = 0.5 V
–70
OZL
IL
CC
O
3
Output current
= MAX, V = 2.25 V
–60
–
–
–150
145
155
155
mA
mA
mA
mA
O
CC
O
I
I
100
110
105
CCH
I
Supply current (total)
I
V
CC
= MAX
–
CC
CCL
–
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, V = V for all test conditions.
X
CC
2. All typical values are at V = 5 V, T
= 25 °C.
CC
amb
3. I is tested under conditions that produce current approximately one half of the true short-circuit output current (I ).
O
OS
7
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
AC ELECTRICAL CHARACTERISTICS FOR 74F646A
LIMITS
T
= +25 °C
T
= 0 °C to +70 °C
= +5.0 V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
= +5.0 V
UNIT
CC
CC
C = 50 pF, R = 500 Ω
C = 50 pF, R = 500 Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
165
185
150
MHz
ns
max
t
t
Propagation delay
CPAB or CPBA to An or Bn
5.5
4.5
7.0
7.0
10.5
9.5
4.5
4.0
11.0
10.0
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
4.0
2.0
6.0
5.0
9.0
8.0
3.5
2.0
10.0
8.0
PLH
PHL
Waveform 2
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB or SBA to An or Bn
4.5
3.5
6.5
8.0
9.5
10.0
4.0
3.0
10.0
11.5
PLH
PHL
Waveform 2, 3
t
t
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.0
3.0
5.5
5.5
9.0
10.0
2.5
2.5
10.0
10.5
PZH
PZL
t
t
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.0
3.5
5.0
6.0
8.0
8.5
3.0
3.0
8.5
9.5
PZH
PZL
t
t
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
1.5
2.5
4.0
5.5
6.5
8.0
1.0
2.0
8.0
9.5
PHZ
PLZ
t
t
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.0
3.0
4.5
5.0
7.5
8.0
1.5
2.0
8.5
8.5
PHZ
PLZ
AC SET-UP REQUIREMENTS FOR 74F646A
LIMITS
T
= +25°C
= +5.0 V
T
= 0°C to +70°C
= +5.0 V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
UNIT
CC
CC
C = 50 pF, R = 500 Ω
C = 50 pF, R = 500 Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Set-up time, HIGH or LOW
An or Bn to CPAB or CPBA
3.5
4.0
4.0
4.5
su
su
Waveform 4
Waveform 4
Waveform 1
ns
ns
ns
t (H)
Hold time, HIGH or LOW
An or Bn to CPAB or CPBA
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
Pulse width, HIGH or LOW
CPAB or CPBA
3.5
3.5
4.5
4.0
8
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
AC ELECTRICAL CHARACTERISTICS FOR 74F648A
LIMITS
T
= +25°C
T
= 0°C to +70°C
= +5.0 V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
= +5.0 V
UNIT
CC
CC
C = 50 pF, R = 500 Ω
C = 50 pF, R = 500 Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
160
185
135
ns
ns
max
t
t
Propagation delay
CPAB or CPBA to An or Bn
5.0
5.5
7.0
7.5
9.5
10.0
4.5
4.5
10.5
10.5
PLH
PHL
t
t
Propagation delay
An to Bn or Bn to An
2.5
4.0
4.5
6.0
7.5
8.5
2.0
4.0
8.5
9.5
PLH
PHL
Waveform 3
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
SAB or SBA to An or Bn
4.0
4.5
7.0
7.0
9.5
9.5
3.5
4.5
11.5
10.0
PLH
PHL
Waveform 2, 3
t
t
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.5
4.5
6.5
6.5
10.0
10.0
3.5
4.0
11.0
11.5
PZH
PZL
t
t
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.5
4.0
5.5
6.5
8.5
9.5
3.0
4.0
9.0
10.0
PZH
PZL
t
t
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
2.5
4.0
4.0
6.5
6.5
9.0
2.0
3.5
8.0
10.0
PHZ
PLZ
t
t
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.5
2.5
5.0
5.0
8.5
8.0
2.0
3.5
9.0
9.0
PHZ
PLZ
AC SET-UP REQUIREMENTS FOR 74F648A
LIMITS
T
= +25 °C
T
= 0 °C to +70 °C
= +5.0 V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST CONDITION
V
= +5.0 V
UNIT
CC
CC
C = 50 pF, R = 500 Ω
C = 50 pF, R = 500 Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Set-up time, HIGH or LOW
An or Bn to CPAB or CPBA
4.0
4.0
4.5
4.5
su
su
Waveform 4
Waveform 4
Waveform 1
ns
ns
ns
t (H)
Hold time, HIGH or LOW
An or Bn to CPAB or CPBA
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
Pulse width, HIGH or LOW
CPAB or CPBA
3.5
3.5
4.0
3.5
9
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
AC WAVEFORMS
1/f
max
An or Bn
SBA or SAB
V
CPBA
V
M
M
or
CPAB
V
V
t
(H)
M
V
M
t
w
M
t
t
PLH
PHL
t
t
(L)
PLH
PHL
w
V
V
M
M
V
V
M
M
Bn or An
An or Bn
SF00395
An or Bn
SF00394
Waveform 2. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
Waveform 1. Propagation delay for clock input to output clock
pulse width, and maximum clock frequency
SBA or SAB
An or Bn
Bn or An
An or Bn
V
V
M
M
V
V
V
V
M
M
M
M
t
(L)
t (L)
h
t
(H)
t (H)
h
su
t
t
PHL
su
PLH
CPBA
or
CPAB
An or Bn
V
V
V
M
V
M
M
M
SF00397
SF00396
Waveform 3. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
Waveform 4. Data set-up time and hold times
OE
OE
V
V
M
V
t
V
M
M
M
DIR
DIR
V
-0.3V
0V
OH
t
t
PHZ
t
PZH
PZL
PLZ
3.5V
An or Bn
V
V
M
M
An or Bn
V
+0.3V
OL
SF00398
SF00399
Waveform 5. 3-state output enable time to HIGH level and
output disable time from HIGH level
Waveform 6. 3-state output enable time to LOW level and
output disable time from LOW level
NOTES:
1. For all waveforms, V = 1.5 V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
10
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
R
M
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
L
INPUT PULSE REQUIREMENTS
family
C
L
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
R
T
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
11
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
12
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
13
2003 Feb 04
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
REVISION HISTORY
Rev
Date
Description
_4
20030204
74F646A/74F648A Product data (9397 750 05151); ECN 853-1124 29306 of 17 December 2002.
Supersedes 74F646/A/74F648/A_3 of 1990Sep25.
Modifications:
• Delete all references to non-A version specifications. The non-A versions of these devices have been
discontinued.
_3
19900925
74F646/A/74F648/A Product specification (9397 750 05151); ECN 853-1124 00515 of 25 September 1990.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2003
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 02-03
9397 750 11051
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号：
N74F646D-T
Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO24,
YAGEO
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