N74F8965A-T [NXP]
IC F/FAST SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC44, PLASTIC, LCC-44, Bus Driver/Transceiver;
| 型号： | N74F8965A-T |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC44, PLASTIC, LCC-44, Bus Driver/Transceiver |
| 文件： | 总11页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
FEATURES
• 9–bit transceiver (both directions)
• Drives heavily loaded backplanes with
equivalent load impedances down to
10 ohms
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
• Guaranteed skew of less than 2ns
DESCRIPTION
The 74F8965 and 74F8966 are 9–bit
bidirectional latchable transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a precision band
gap references for improved noise margins.
The 74F8965 and 74F8966 A ports have TTL
3–state drivers and TTL receivers.
• High drive (100mA) open collector
drivers on B port
The B ports have standard BTL I/O with
• Reduced voltage swing (1V to 2V)
produces less noise and reduces
power consumption
100mA current sink capability. The B–to–A
path is a simple inverted buffered path. When
going from A–to–B the user may choose be-
tween a buffered path or a latching function.
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
The 74F8966 also has an idle arbitrator/multi-
ple competitors output. The IAMC output
compares, using a wired–OR configuration,
the data on the bus to the latched data pres-
ented to the bus. If the bus data matches the
data presented by the 74F8966 then IAMC is
high. If the data doesn’t match then IAMC
goes low.
The B port interfaces to ’Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
• Compatible with IEEE 896 futurebus
standards and IEEE 1194 BTL stan-
dard
• Built–in precision band–gap reference
provides accurate receiver thresholds
and improved noise immunity
Incident wave switching is employed, there-
fore BTL propagation delays are short. Al-
though the voltage swing is much less for
BTL, so is its receiver threshold region,
therefore noise margins are excellent.
• Controlled output ramp and multiple
GND pins minimize ground bounce
• Glitch–free power up/power down
operation
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8965
74F8966
3.5ns
3.5ns
80mA
80mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
44–pin PLCC
N74F8965A, N74F8966A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
A0 – A8
B0 – B8
TTL data inputs
1.0/0.033
5.0/0.167
20µA/20µA
Data inputs with threshold circuitry
Output enable inputs
100µA/100µA
OEA, OEB0, OEB1
1.0/0.167
20µA/100µA
LS
Latch select (active low) (’F8965)
Idle arbitration request (active low) (’F8965)
Latch enable input (active low)
1.0/0.167
1.0/0.167
1.0/0.167
150/40
20µA/100µA
20µA/100µA
20µA/100µA
3mA/24mA
OC/100mA
IAREQ
LE
A0 – A8
B0 – B8
3–state TTL outputs
Open collector BTL outputs
OC/166.7
Idle arbitration/multiple competitors output (’F8966)
IAMC
OC/80
OC/48mA
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
1
December 19, 1990
853 1526 01320
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
PIN CONFIGURATION PLCC
IEC/IEEE SYMBOL
74F8965
74F8965
LOGIC
BUS
LOGIC
A1 GND A0
BUS
GND B0 GND
BUS
V
V
OEA OEB0OEB1
CC
CC
6
5
4
3
2
1
44
43
42
41
40
23
1
G1/V2
LOGIC GND
A2
B1
7
8
39
&
EN3
44
22
2
BUS GND
B2
2
38
37
36
C4
9
10
11
LOGIC GND
A3
EN5
4
BUS GND
1
41
MUX
3
4D
1
1
LOGIC GND
A4
35 B3
1
6
39
37
35
33
31
29
27
25
BUS GND
12
34
33
8
A5
B4
13
14
10
12
13
15
17
19
LOGIC GND
A6
BUS GND
B5
32
31
15
16
LOGIC GND
BUS GND
B6
30
29
A7 17
18
19
20
21
22
23
24
25
26
27
28
LOGIC
GND
BUS
GND
BUS
GND
LOGIC LOGIC
LS BUS
A8
LE
B8
B7
GND
V
V
CC
CC
PIN CONFIGURATION PLCC
IEC/IEEE SYMBOL
74F8966
74F8966
LOGIC
BUS
LOGIC
A1 GND A0
BUS
GND B0 GND
BUS
V
V
OEA OEB0OEB1
CC
3
CC
6
5
4
2
1
44
43
42
41
40
1
10
11
LOGIC GND
A2
B1
23
1
7
8
39
G1/V2/EN6
12
13
14
15
16
17
18
20
41
&
BUS GND
B2
38
37
36
EN3
44
22
2
2
9
10
11
C4
LOGIC GND
A3
EN5
BUS GND
1
4
LOGIC GND
A4
35 B3
7 Z10
MUX
4D
1
BUS GND
B4
12
34
33
N7
3
1
1
6
39
37
35
33
31
29
27
25
A5
13
14
8
LOGIC GND
A6
BUS GND
B5
32
31
10
12
13
15
17
19
15
16
LOGIC GND
BUS GND
B6
30
29
A7 17
18
19
20
21
22
23
24
25
26
27
28
LOGIC
GND
BUS
GND
BUS
GND
IAMC LOGIC
IREQ BUS
A8
LE
B8
B7
V
V
CC
CC
2
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC SYMBOL
74F8965
74F8966
4
6
8
10 12 13 15 17 19
4
6
8
10 12 13 15 17 19
A0 A1 A2 A3 A4 A5 A6 A7 A8
A0 A1 A2 A3 A4 A5 A6 A7 A8
1
44
23
22
2
OEB0
OEB1
LS
1
44
23
22
2
OEB0
OEB1
IAREQ
LE
LE
OEA
OEA
B0 B1 B2 B3 B4 B5 B6 B7 B8
20
IAMC
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25
41 39 37 35 33 31 29 27 25
Logic V
= Pin 3, 21
Logic V
= Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
CC
CC
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
PIN DESCRIPTION
SYMBOL
PINS
TYPE
NAME AND FUNCTION
A0 – A8
B0 – B8
OEB0
4, 6, 8, 10, 12, 13, 15, 17, 19
I/O
Data inputs/TTL 3–state outputs
41, 39, 37, 35, 33, 31, 29, 27, 25
I/O
Data inputs / open collector outputs, high current drives.
Output enable input. Enables the B outputs when high.
Output enable input. Enables the B outputs when low.
Output enable input. Enables the A outputs when high.
Latch enable input. Enables latch when low.
1
Input
Input
Input
Input
Input
Input
OEB1
44
OEA
2
LE
22
LS
23
Latch select input. Selects latch when low (74F8965).
Idle arbitration request input (74F8966).
IAREQ
IAMC
23
20
26, 28, 30, 32, 34, 36, 38, 40, 42
5, 7, 9, 11, 14, 16, 18, 20 (74F8965)
24, 43
Output Idle arbitration/multiple competitors output (open collector output) (74F8966).
Ground Bus ground (0V)
Bus GND
Logic GND
Ground Logic ground (0V)
Bus V
Power Positive supply voltages
CC
Logic V
3, 21
Power Positive supply voltages
CC
3
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8965
1
OEB0
44
OEB1
23
22
2
LS
LE
OEA
Q
Q
D
E
41
39
37
35
33
31
29
27
25
B0
B1
B2
B3
B4
B5
B6
B7
B8
4
6
8
A0
A1
A2
A3
A4
A5
A6
A7
A8
D
E
Q
Q
D
E
D
E
10
Q
Q
D
E
12
13
15
17
19
BTL levels
TTL levels
D
E
Q
Q
D
E
D
E
Q
D
E
Logic V
= Pin 3, 21
CC
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
4
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8966
1
OEB0
44
OEB1
48mA
open
collector
20
23
IAMC
IAREQ
TTL level
22
LE
2
OEA
Q
D
E
41
B0
B1
B2
B3
B4
B5
B6
B7
B8
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
Q
D
E
39
37
35
33
31
29
27
25
6
Q
Q
Q
Q
Q
D
E
8
D
E
10
12
13
15
17
19
D
E
BTL levels
TTL levels
D
E
D
E
Q
Q
D
E
D
E
Logic V
= Pin 3, 21
CC
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
5
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
FUNCTION TABLE FOR 74F8965
INPUTS
LATCH
OUTPUTS
OPERATING MODE
AIn Bn*
OEB0
H
OEB1
LS
H
H
L
OEA
L
LE
X
X
L
STATE
An
input
input
input
input
input
input
L
Bn
H**
L
L
H
L
H
l
–
–
–
–
–
–
–
–
–
X
X
L
H
X
L
L
X
X
An to Bn bypass latch
H
L
H
L
L
H
L
H**
L
An to Bn transparent latch
An to Bn latch and read
H
L
L
L
L
H
L
L
L
↑
H
L
H**
L
h
–
–
X
X
X
–
–
–
H
L
L
L
↑
H
L
L
H
H
L
H
H
H
X
X
X
X
X
H
L
H**
L
An to Bn outputs latched and read
(preconditioned latch)
An to Bn hold
H
L
L
H
H
L
L
NC
X
input
X
L
L
X
H
H
H
X
X
H
H
H
X
X
X
H
H
L
H**
H**
Disable Bn outputs
X
X
X
L
X
H
input Bn to An
input
L
X
L
X
X
Z
X
Disable An outputs
Notes to function table for 74F8965
1. H
2. h
3. L
4. l
=
=
=
=
High voltage level
High voltage level one setup time prior to the low–to–high LE transition
Low voltage level
Low voltage level one setup time prior to the low–to–high LE transition
5. NC= No change
6. X
7. Z
8. –
9. ↑
=
=
=
=
Don’t care
High impedance ”off’ state
Input not externally driven
Low–to–high transition
10.H**= Goes to level of pullup voltage.
11. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8966
INPUTS
LATCH
OUTPUTS
Bn
H**
L
OPERATING MODE
AIn Bn* OEB0 OEB1 IAREQ
LS
H
H
L
OEA
L
LE
X
X
L
STATE
An
input
input
input
input
input
input
L
IAMC
H**
H**
H**
H**
H**
H**
H**
H**
H**
H**
H**
H**
H**
L
L
H
L
H
l
–
–
H
H
H
H
H
H
H
H
H
L
L
L
L
L
X
X
An to Bn bypass latch
L
–
L
L
L
H
H**
L
An to Bn transparent latch
An to Bn latch and read
–
L
L
L
L
L
L
–
L
L
L
L
↑
H
H**
L
h
–
–
X
X
X
–
–
–
–
–
–
L
L
L
L
↑
L
–
L
L
L
H
H
L
H
H
H
X
X
X
X
H
H
X
H
H**
L
An to Bn outputs latched and read
(preconditioned latch)
An to Bn hold
–
L
L
L
L
H
–
L
L
L
NC
X
input
X
NC
H**
H**
input
input
Bn
X
X
L
X
H
H
H
H
H
X
X
H
H
H
H
H
X
X
H
H
H
↓*
↓*
X
X
X
H
H
H
H
L
Disable Bn outputs
X
L
X
X
X
H
Bn to An
H
Bn
Bn
X
L
X
L
L
Bn
Bn
X
Z
Latch Bn data idle arbitration request
(preconditioned latch)
L
Z
Bn
H**
X
X
Z
X
Disable An outputs
6
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
Notes to function table for 74F8966
1. H
2. h
3. L
4. l
=
=
=
=
High voltage level
High voltage level one setup time prior to the low–to–high LE transition
Low voltage level
Low voltage level one setup time prior to the low–to–high LE transition
5. NC= No change
6. X
7. Z
8. –
9. ↑
=
=
=
=
Don’t care
High impedance ”off’ state
Input not externally driven
Low–to–high transition
10.↓* = High–to–low transition, latch must be preconditioned before IAREQ
11. H**= Goes to level of pullup voltage.
12.B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +5.5
–40 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
OEB0, OEB1, LEA, LE
A0 – A8, B0 – B8
V
V
I
IN
Input current
mA
V
OUT
Voltage applied to output in high output state
–0.5 to V
V
CC
A0 – A8
IAMC (74F8966 only)
B0 – B8
48
96
mA
mA
mA
I
Current applied to output in low output
OUT
200
T
Operating free air temperature range
Storage temperature range
0 to +70
°C
°C
amb
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
V
Supply voltage
4.5
5.0
5.5
CC
IH
V
High–level input voltage
Low–level input voltage
Except B0 – B8
2.0
V
B0 – B8
Except B0 – B8
B0 – B8
1.625
1.55
V
V
IL
0.8
1.475
–18
–3
V
V
I
I
Input clamp current
mA
mA
V
Ik
High–level output current
High–level output voltage
A0 – A8
IAMC (74F8966 only)
A0 – A8
OH
V
OH
4.5
24
48
mA
mA
mA
I
OL
Low–level output current
IAMC (74F8966 only)
B0 – B8
100
+70
T
amb
Operating free air temperature
0
°C
7
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
100
100
100
100
I
High–level output current
Power–off output current
High-level output voltage
Low-level output voltage
Input clamp voltage
B0 – B8
V
V
V
V
V
V
V
V
V
= MAX, V = MAX, V = MIN, V = 2.1V
µA
µA
µA
µA
V
OH
CC
CC
CC
CC
CC
CC
IL
IH
OH
IAMC (74F8966)
B0 – B8
= MAX, V = MAX, V = MIN, V = 4.5V
IL IH OH
I
= 0.0V, V = MAX, V = MIN, V = 2.1V
OFF
IL
IH
OH
IAMC (74F8966)
= 0.0V, V = MAX, V = MIN, V = 4.5V
IL IH OH
4
V
V
V
A0 – A8
= MAX, V = MAX, V = MIN, I = –3mA
2.4
V
CC
OH
OL
IK
IL
IH
OH
4
A0 – A8
= MIN,
I
OL
I
OL
= 24mA
0.50
0.50
1.10
-1.2
V
IAMC (74F8966)
B0 – B8
= MAX
= MIN
= 48mA
V
IL
I
OL
= 100mA
0.75
1.0
V
IH
CC
= MIN, I = I
V
I
IK
OEB0, OEB1,
OEA, LE, LS,
IAREQ
I
I
V
CC
= MAX, V = 7.0V
100
µA
Input current at
maximum input voltage
I
A0 – A8, B0 –
B8
V
V
= MAX, V = 5.5V
1
mA
CC
I
OEB0, OEB1,
OEA, LE, LS,
IAREQ
= MAX, V = 2.7V
20
µA
CC
I
I
I
High–level input current
Low–level input current
IH
B0 – B8
V
CC
V
CC
= MAX, V = 2.1V
100
µA
µA
I
OEB0, OEB1,
OEA, LE, LS,
IAREQ
= MAX, V = 0.5V
–100
I
IL
B0 – B8
V
V
= MAX, V = 0.3V
–100
50
µA
µA
CC
I
Off–state output current,
high–level voltage applied
I
IH
+ I
OZH
A0 – A8
= MAX, V = 2.7V
O
CC
Off–state output current,
low–level voltage applied
µA
I
+ I
V
V
= MAX, V = 0.5V
–50
IL
OZL
CC
I
Short circuit output
I
A0 – A8 only
AO8
= MAX
= MAX
-60
-150
mA
OS
3
CC
current
I
V
V
80
85
75
140
145
100
mA
mA
mA
CCH
CC
I
Supply current (total)
I
= MAX, V = 0.5V
IL
CC
CCL
CCZ
CC
I
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold tech-
OS
niques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a
high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence
of parameter tests, I tests should be performed last.
OS
4. Due to test equipment limitations, actual test conditions are for V =1.8V and V = 1.3V.
IH
IL
8
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Bn to An
3.0
2.5
5.0
4.5
8.0
7.5
2.5
2.5
8.5
8.0
PLH
PHL
Waveform 2
ns
ns
t
t
Output enable time to high or low,
OEA to An
7.5
9.0
9.0
11.0
12.0
13.5
6.0
7.5
14.0
16.0
PZH
PZL
Waveform 5, 6
t
t
Output disable from high or low,
OEA to An
3.0
4.0
5.0
6.0
8.0
9.0
2.5
4.0
9.0
10.0
PHZ
PLZ
Waveform 5, 6
Waveform 4
ns
ns
t
Skew between receivers in same package
0.5
1.0
1.0
sk(o)
B PORT LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C
= 30pF, R = 9Ω
C = 30pF, R = 9Ω
D U
D
U
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
An to Bn (transparent latch)
2.5
3.0
4.0
5.0
7.0
7.5
2.0
2.5
8.0
9.0
PLH
PHL
Waveform 2
Waveform 2
Waveform 1, 2
Waveform 2
Waveform 1
Waveform 1, 2
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to Bn (bypass latch)
1.0
1.5
3.0
3.0
5.5
5.5
1.0
1.0
6.0
6.5
PLH
PHL
t
t
Propagation delay
LE to Bn
3.0
4.0
5.0
5.5
8.0
8.5
3.0
3.5
8.5
9.5
PLH
PHL
t
t
Output enable/disable time,
OEB0 to Bn
4.0
5.0
6.0
6.5
8.5
9.5
3.5
3.5
10.0
11.5
PLH
PHL
t
t
Output enable/disable time,
OEB1 to Bn
5.5
3.0
7.5
5.0
10.0
8.0
5.0
2.5
11.0
8.5
PLH
PHL
t
t
Propagation delay
IAREQ or LS to Bn
4.5
2.0
7.5
6.5
10.0
9.5
4.0
2.0
11.0
11.0
PLH
PHL
t
t
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
2.0
2.0
1.0
1.0
3.0
3.0
TLH
THL
ns
ns
t
Skew between drivers in same package
Waveform 4
1.0
2.0
2.0
sk(o)
IAMC PORT LIMITS (74F8966 only)
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
An to IAMC (latches preset)
10.5
7.0
14.5
12.0
18.0
15.0
9.5
6.0
20.0
17.5
PLH
PHL
Waveform 2
Waveform 2
ns
ns
t
t
Propagation delay
IAREQ to IAMC
6.5
2.5
8.0
4.5
11.0
7.0
6.0
2.0
11.5
8.0
PLH
PHL
9
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time, high or low
An to LE
2.5
0.0
3.0
0.0
Waveform 3
ns
th(H)
th(L)
Hold time, high or low
An to LE
4.0
2.5
5.0
3.0
Waveform 3
Waveform 3
ns
ns
t (L)
w
LE pulse width, low
4.0
4.5
AC WAVEFORMS
Bn, LS, LE,
OEB1, IAREQ
An, Bn, LS, LE,
OEB0, IAREQ
V
M
V
V
M
V
M
M
t
t
t
t
PHL
PLH
PLH
PHL
Bn, IAMC
V
M
V
V
An, Bn. IAMC
V
M
M
M
Waveform 2. Propagation delay for data or
output enable to output
Waveform 1. Propagation delay for data or
output enable to output
An, Bn
V
M
An, Bn
V
V
V
t
V
M
M
M
M
t
sk(o)
t
(L)
t (H)
h
(H)
h
su
t
(L)
t (L)
su
w
V
An, Bn
V
V
V
M
M
LE
M
M
Waveform 4. Output skew
Waveform 3. Data setup and hold times and LE pulse width
OEA
An
V
V
V
V
M
OEA
An
M
M
M
V
-0.3V
0V
OH
t
t
t
t
PLZ
PZH
PHZ
PZL
V
V
M
M
V
+0.3V
OL
Waveform 5. 3–state output enable time to high level
and output disable time from high level
Waveform 6. 3-state output enable time to low level
and output disable time from low level
Notes to AC waveforms
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
10
December 19, 1990
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
t
w
AMP (V)
90%
90%
TEST
SWITCH
closed
open
NEGATIVE
PULSE
V
CC
V
V
M
M
t
, t
PLZ PZL
10%
10%
7.0V
All other
Low V
R
t
t
)
)
t
t )
L
THL ( f
TLH ( r
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
t
t )
TLH ( r
THL ( f
AMP (V)
Low V
R
C
R
L
90%
M
90%
T
L
POSITIVE
PULSE
V
V
M
10%
10%
Test circuit for 3–state outputs on A port
t
w
V
7.0V
CC
Input pulse definition
INPUT PULSE REQUIREMENTS
R
U
V
V
OUT
IN
family
PULSE
GENERATOR
D.U.T.
V
Low V
74F amplitude
rep. rate
1MHz
t
t
t
M
w
TLH
THL
A port
B port
3.0V
3.0V
0.0V 1.5V
1.0V 1.5V
500ns 2.5ns 2.5ns
500ns 4.0ns 4.0ns
R
C
D
T
1MHz
Test circuit for outputs on B port
DEFINITIONS:
R
C
R
C
R
=
=
=
=
=
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
L
L
U
D
T
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to Z
of pulse generators.
OUT
11
December 19, 1990
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