NE5020 [NXP]
10-Bit mP-compatible D/A converter; 10位MP-兼容的D / A转换器
| 型号： | NE5020 |
| 厂家： | 
NXP |
| 描述： | 10-Bit mP-compatible D/A converter |
| 文件： | 总10页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
DESCRIPTION
PIN CONFIGURATION
The NE5020 is a microprocessor-compatible monolithic 10-bit
digital-to-analog converter subsystem. This device offers 10-bit
resolution and ±0.1% accuracy and monotonicity guaranteed over
full operating temperature range.
F, N Packages
1
2
24
23
22
21
20
19
18
17
16
15
14
13
ANALOG GND
AMP COMP
DIGITAL GND
DB0(LSB)
Low loading latches, adjustable logic thresholds, and addressing
capability allow the NE5020 to directly interface with most
microprocessor- and logic-controlled systems.
3
DB1
DB2
DB3
SUM MODE
4
V
CC+
5
V
OUT
6
DB4
DB5
V
The NE5020 contains internal voltage reference, DAC switches and
resistor ladder. Also, the input buffer and output summing amplifier
are included. In addition, the matched application resistors for
scaling either unipolar or bipolar output values are included on a
single monolithic chip.
CC–
7
BIPOLAR OFFSET R
DB6
8
+V
–V
IN
IN
REF
REF
DB7(MSB)
9
10
11
12
NC
V
OUT
REF
V
ADJ
REF
LE
The result is a near minimum component count 10-bit resolution
DAC system.
LE
1
2
FEATURES
• 10-bit resolution
APPLICATIONS
• Guaranteed monotonicity over operating range
• ±0.1% relative accuracy
• Precision 10-bit D/A converters
• 10-bit analog-to-digital converters
• Programmable power supplies
• Test equipment
• Unipolar (0V to +10V) and bipolar (± 5V) output range
• Logic bus compatible
• 5µs settling time
• Measurement instruments
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
0 to 70°C
ORDER CODE
NE5020F
DWG #
0588B
0412A
24-Pin Ceramic Dual In-Line Package (CERDIP)
24-Pin Plastic Dual In-Line Package (DIP)
0 to 70°C
NE5020N
757
August 31, 1994
853-0392 13721
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
BLOCK DIAGRAM
(11)
DB9
(10)
DB8
(9)
DB7
(8)
DB6
(4)
DB2
(3)
DB1
(2)
DB0
(7)
DB5
(6)
DB4
(5)
DB3
LSB
MSB
(13)
(12)
LE
2
LE
1
LATCHES AND
SWITCH DRIVERS
SUM
(22)
NODE
R
(1) DIGITAL GND
fb
(21)
(15)
+V
CC
DAC OUTPUT CURRENT
–
+
V
V
REF
OUT
(20)
(23)
OUT
INT
V
REF
V
ADJ
REF
AMP
COMP
(14)
+V
DAC SWITCHES
R
R
(24)
REF
ANALOG
GND
(17) REF
IN
R
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
BIP
R
9
8
7
6
5
4
3
2
1
BIPOLAR
OFFSET
Q
(18)
T
+
–
–V
(16) REF
IN
R
–V
CC
(19)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
18
UNIT
V
+
V
V
V
V
V
V
Positive supply voltage
Negative supply voltage
Logic input voltage
CC
CC
IN
-
-18
V
0 to 18
12
V
Voltage at +V
input
V
REF IN
REF ADJ
SUM
REF
Voltage at V
adjust
0 to V
12
V
REF
REF
Voltage at sum node
Short-circuit current to ground at V
V
I
I
Continuous
Continuous
REFSC
OUTSC
REF OUT
Short-circuit current to ground or either supply at V
OUT
1
P
D
Maximum power dissipation T =25°C, (still-air)
A
F package
2150
2150
mW
mW
°C
N package
T
A
Operating temperature range NE5020
Storage temperature range
0 to +70
-65 to +150
T
STG
°C
Lead soldering temperature
(10 sec. max)
T
SOLD
300
°C
NOTES:
1. Derate above 25°C at the following rates:
F package at 17.2mW/°C
N package at 17.2mW/°C
758
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
DC ELECTRICAL CHARACTERISTICS
1
V
+=+15V, V -=-15V, 0 ≤ T ≤70°C, unless otherwise specified. Typical values are specified at 25°C.
CC
CC
A
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Max
Min
Resolution
Monotonicity
10
10
Bits
Bits
Relative accuracy
±0.1
%FS
V
CC+
V
CC-
Positive supply voltage
Negative supply voltage
11.4
-11.4
15
-15
16.5
-16.5
V
V
V
IN(1)
V
IN(0)
Logic “1” input voltage
Logic “0” input voltage
Pin 1=0V
Pin 1=0V
V
V
2.0
0.8
I
I
Logic “1” input current
Logic “0” input current
Pin 1=0V, 2<V <18V
0.1
-2.0
10
-10
µA
µA
IN(1)
IN(0)
IN
Pin 1=0V, -5V<V <0.8V
IN
Unipolar mode, V
=5.000V, all bits high,
REF
V
FS
Full-scale output
9.5
10.5
V
T =25°C
A
+V
Full-scale output
Bipolar mode, V
=5.000V, all bits high, T =25°C
4.75
5.25
V
V
FS
REF
A
-V
FS
Negative full-scale
Bipolar mode, V
=5.000V, all bits low, T =25°C
-5.25
-4.75
REF
A
NOTES:
1. Refer to Figure 1.
759
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
DC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
Unipolar mode, V =5.000V, all bits low, T =25°C
UNIT
Max
Min
V
ZS
Zero-scale output
-30
+30
mV
mA
REF
A
I
Output short-circuit current
T =25°C
±15
0.001
0.001
20
±40
OS
A
V =0V
OUT
PSR+
Output power supply rejection (+)
Output power supply rejection (-)
Full-scale temperature coefficient
V-=-15V, 13.5V≤V+≤16.5V, external
=5.000V
0.01
0.01
%FS/
%VS
(OUT)
V
REF IN
PSR-
V+=15V, -13.5V≤V-≤-16.5V, external
%FS/
%VS
(OUT)
V
=5.000V
REF IN
TC
V
=5.000V
ppmFS
FS
REF IN
/°C
TC
Zero-scale temperature coefficient
Reference output current
5
ppmFS/°C
mA
ZS
2
I
I
3
REF
Reference short circuit current
T =25°C
A
15
30
mA
REF SC
V =0V
REF OUT
PSR+
Reference power supply rejection
(+)
V-=-15V, 13.5V≤V+≤16.5V, I
=1.0mA
.003
.003
.01
.01
%VR/
%VS
REF
REF
PSR-
Reference power supply rejection
(-)
V+=15V, -13.5V≤V-≤16.5V,
%VR/
%VS
REF
V
Reference voltage
I
=1.0mA, T =25°C
4.9
5.0
60
5.25
V
REF
REF
A
TC
Reference voltage temperature co-
efficient
I
=1.0mA
ppm/°C
REF
REF
Z
DAC V
input impedance
I
=1.0mA
5.0
7
kΩ
mA
mA
mW
IN
REF IN
REF
I
I
+
-
Positive supply current
Negative supply current
Power dissipation
V
+=15V
-=-15V
14
-15
435
CC
CC
CC
V
-10
255
CC
P
I
=1.0mA, V =±15V
REF CC
D
NOTES:
1. Refer to Figure 1.
2. For I
greater than 3mA, an external buffer is required.
REF OUT
1
AC ELECTRICAL CHARACTERISTICS
V
= +15V, T = 25°C.
CC
A
LIMITS
SYMBOL
PARAMETER
Settling time
TO
FROM
TEST CONDITIONS
UNIT
Min
Typ
5
Max
2
t
±1/2LSB
±1/2LSB
Output
Output
Output
Output
Output
LE
Input
Input
Input
Input
Input
LE
All bits low-to-high
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
SLH
SHL
PLH
PHL
PLSB
PLH
PHL
S
3
t
Settling time
All bits high-to-low
All bits switched low-to-high
5
2
t
t
t
t
t
t
t
t
Propagation delay
Propagation delay
Propagation delay
Propagation delay
Propagation delay
Set-up time
30
3
All bits switched high-to-low
150
150
300
150
2,3
1 LSB change
4
Low-to-high transition
5
LE
High-to-low transition
1,6
1,6
1,6
Input
LE
100
50
Hold time
Input
H
Latch enable pulse width
150
PW
NOTES:
1. Refer to Figure 2.
2. See Figure 5.
3. See Figure 6.
4. See Figure 7.
5. See Figure 8.
6. See Figure 9.
760
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
V
CC+
0.47µF
MSB
LSB
V
CC+
LE2 LE1
MSB
LSB
LE2 LE1
0.47µF
1110 9 8 7 6 5 4 3 2
21
DIG GND 1
1110 9 8 7 6 5 4 3 2
12
21
12
13
17
5.000V
DIG GND 1
ANA GND
24
13
ANA GND
V
V
IN
17
15
24
REF
REF
15
–V
IN
16
20
REF
V
OUT
5020
OUTPUT
–V
IN
16
20
14
REF
V
5020
OUTPUT
30pF
OUT
SUM
14
30pF
5k
OUT
SUM
22
23
22
23
AMP
COMP
5k
AMP
COMP
19
18
100pF
19
18
100pF
0.1µF
0.1µF
V
CC–
V
CC–
Figure 1. DC Parametric Test Configuration
Figure 2. AC Parametric Test Configuration
V
CC+
0.47µF
MSB
LSB
LE2 LE1
1110 9 8 7 6 5 4 3 2
21
12
DIG GND 1
13
ANA GND
V
V
V
IN
17
15
24
REF
REF
REF
OUT
ADJ
–V
IN
16
20
REF
V
5020
10k
10T
OUTPUT
30pF
14
OUT
SUM
80k
22
23
5k
AMP
COMP
FULL SCALE
ADJUST
19
18
100pF
V
CC+
20k
0.1µF
1M
V
CC–
ZERO SCALE
ADJUST
10T
V
CC–
Figure 3. Full-/Zero-Scale Adjust — Unipolar Output (0–10V)
V
CC+
MSB
LSB
LE2 LE1
0.47µF
11 10 9 8 7 6 5 4 3 2
21
12
DIG GND 1
13
ANA GND
V
V
V
IN
17
15
24
REF
REF
REF
OUT
ADJ
–V
IN
16
20
REF
V
5020
10k
10T
OUTPUT
5k
30pF
14
OUT
SUM
80k
22
23
AMP
COMP
BIP OFF
18
19
100pF
1M
V
CC+
0.1µF
20k
10T
CC–
V
CC–
FULL SCALE
ADJUST
V
Figure 4. Bipolar Output Operation (–5 to +5V)
761
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
DATA
DATA
t
SLH
t
PHL
10V
1LSB
LE
t
PLH
OUTPUT
t
PHL
10V
0V
LE = LOW
OUTPUT
0V
Figure 5. Settling Time and Propagation Delay,
Low-to-High Data
Figure 8. Propagation Delay, Latch Enable to Output
DATA
t
MIN
t
SHL
LE
t
PHL
10V
t
t
h
S
OUTPUT
DATA
0V
1LSB
LE = LOW
Figure 6. Settling Time and Propagation Delay,
High-to-Low Data
Figure 9. Latch Enable Pulse Width, Setup and Hold Times
DATA
LE
t
PLH
10V
OUTPUT
0V
Figure 7. Propagation Delay, Latch Enable to Output
762
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
TTL,
= +1.4V
PMOS
V = 0V
TH
V
= V
+ 1.4V
TH
PIN1
+15V CMOS, HTL, HNIL
DTL V
TH
V
= +7.6V
TH
+15V
+12V TO +15V
NE5020
9.1kΩ
10kΩ
IN4148
PIN 1
PIN 1
0.1µF
DIG GND (PIN 1)
PIN 1
6.2kΩ
6.2V
ZENER
10kΩ
–5V TO –10V
NOTE: DO NOT EXCEED NEGATIVE
LOGIC INPUT RANGE OF DAC
+5V CMOS
= +2.8V
+10V CMOS
10k ECL
V
V
= +9.0V
V
≥ –1.29V
TH
TH
+5V
TH
+10V
1.3kΩ
3.9kΩ
6.2kΩ
3.6kΩ
PIN 1
2N3904
IN4148
PIN 1
PIN 1
0.1µF
3.6kΩ
IN4148
1kΩ
Figure 10.
10 details several bias schemes used to provide the proper
threshold voltage levels for various logic families.
CIRCUIT DESCRIPTION
The NE5020 provides ten data latches, an internal voltage
reference, application resistors, and a scaled output voltage in
addition to the basic DAC components (see Block Diagram).
To be compatible with a bus-oriented system, the DAC should
respond in as short a period as possible to insure full utilization of
the microprocessor, controller and I/O control lines. Figure 9 shows
the typical timing requirements of the latch and data lines. This
figure indicates that data on the data bus should be stable for at
least 50ns after LE is changed to a high state.
Latch Circuit
Digital interface with the NE5020 is readily accomplished through
the use of two latch enable ports (LE and LE ) and ten data input
1
2
latches. LE controls the two most significant bits of data (DB9 and
2
The independent LE (LE and LE ) lines allow for direct interface
DB8) while LE controls the eight lesser significant bits (DB through
1
2
1
7
from an 8-bit bus (see Figure 11). Data for the two MSBs is supplied
DB ). Both the latch enable ports (LE) and the data inputs are
0
and stored when LE is activated low and returned high according to
static- and threshold-sensitive. When the latch enable ports (LE)
are high (Logic ‘1’) the data inputs become very high impedances
and essentially disappear from the data bus. Addressing the LE
with a low static (Logic ‘0’), the latches become active and adapt the
logic states present on the data bus. During this state, the output of
the DAC will change to the value proportional to the data bus value.
When the latch enable returns to a high state, the selected set of
data inputs (i.e., depending on which LE goes high) ‘memorizes’ the
data bus logic states and the output changes to the unique output
value corresponding to the binary word in the latch.
2
the NE5020 timing requirements. Then LE is activated low and the
1
remaining eight LSBs of data are transferred into the DAC. With
LE returning high, the loading of 10-bit data word from an 8-bit data
1
bus is complete.
Occasionally the analog output must change to its data value within
one data address operation. This is no problem using the NE5020
on a 16-bit bus or any other data bus with 10 or greater data bits.
This can be accomplished from an 8-bit data bus by utilizing an
external latch circuit to pre-load the two MSB data values. Figure 12
shows the circuit configuration.
The data inputs are inactive and high impedance (typically requiring
–2µA for low (0.8V max) or 0.1µA for high (2.0V min) when the LE is
high. Any changes on the data bus with LE high will have no effect
on the DAC output.
After pre-loading (via LE pre-load) the external latch with the two
MSB values, LE is activated low and the eight LSBs and the two
2
MSBs are concurrently loaded into the DAC in one address
operation. This permits the DAC output to make its appropriate
change at one time.
The digital logic inputs (LE and DB) for the NE5020 utilize a
differential input logic system with a threshold level of +1.4V with
respect to the voltage level on the digital ground pin (Pin 1). Figure
763
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
B0
DATA BUS
B6
B7
DB
9
8
7
6
5
4
3
2
1
0
MSB
LSB
LATCHES
LE
2
LE
LATCHES
1
OUTPUT
DAC
Figure 11. NE5020 µP Interface 8-Bit Data Bus Example
8-BIT DATA BUS
+5V
1
2
4
10
13
74LS74
11
12
9
3
5
LE PRE-LOAD
LE LOAD
INVERTER
11
MSB
10
9
8
7
6
5
4
3
2
LSB
12
13
20
NE5020
Figure 12. Pre-loading the 2 MSBs to Provide a Single-Step Output
764
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
5k
V
IN
REF
(17)
+
–
I
5k
REF
To R-2R Ladder
(16)
BIPOLAR
DAC
AMP
OFFSET (18)
JUMPER FOR
BIPOLAR OPERATION
SUM
NODE (22)
V
CC
(I )
I
D REF
5k
I
D
DAC
CURRENT
–
+
FROM
CURRENT
SWITCHES
OUTPUT
AMP
Figure 13. Bipolar Output
2VREF
RREF
Reference Interface
DB9
2
DB8
4
DB7
8
ǒ
IOUT
+
)
)
)
)
)
The NE5020 contains an internal bandgap voltage reference which
is designed to have a very low temperature coefficient and excellent
long-term stability characteristics.
DB6
DB5
32
DB3
128
DB4
64
)
)
)
)
16
The internal bandgap reference (1.23V) is buffered and amplified to
provide the 5V reference output. Providing a V
allows trimming of the reference output. Utilization of the adjust
DB0
1024
DB2
256
DB1
512
(Pin 14)
REF ADJ
circuit shown in Figure 15 performs not only V
also full-scale output adjust. Notice that the V
essentially the sum node of an op amp and is sensitive to excessive
node capacitance. Any capacitance on the node can be minimized
adjustment, but
REF
Because of the fixed internal compensation of the reference amp,
the slew rate is limited to typically 0.7V/µs and source impedance at
pin is
REF ADJ
the V
greater than 5kΩ should be avoided to maintain
REF INPUT
stability.
by placing the external resistors as close as possible to the V
REF
The –V
pin is uncommitted to allow utilization of negative
pin and observing good layout
REF INPUT
ADJ
polarity reference voltages. In this mode +V
and the negative reference is tied directly to the –V
is grounded
REF INPUT
practices.
REF INPUT
contains a 5kΩ resistor that matches a like resistor in the +V
The V
node can drive loads greater than the DAC V
REF
REF
REF OUT
to reduce voltage offset caused by op amp input bias currents.
input requirements and can be used as an excellent system voltage
reference. However, to minimize load effects on the DAC system
accuracy, it is recommended that a buffer amplifier be used.
INPUT
Output Amplifier and Interface
The NE5020 provides an on-chip output op amp to eliminate the
need for additional external active circuits. Its two-stage design with
feed-forward compensation allows it to slew at 15V/µs and settle to
within ±1/2LSB in 5µs. These times are typical when driving the
rated loads of R ≥ 5k and C 50pF with recommended values of
Input Amplifier
The DAC reference amplifier is a high gain internally-compensated
op amp used to convert the input reference voltage to a precision
bias current for the DAC ladder network.
L
L
C
= 1nF and C = 30pF. Typical input offset voltages of 5mV
FB
FF
The Block Diagram details the input reference amplifier and current
ladder. The voltage-to-current converter of the DAC amp will
and 50kΩ open-loop gain insure that an accurate current-to-voltage
conversion is performed when using the on-chip R resistor. R
is matched to R
operating conditions. The diode shown from ground to sum node
prevents the DAC current switches from saturating the op amp
during large signal transitions which would otherwise increase the
settling time.
FB
FB
generate a 1mA reference current through QR with a 5V V
. This
REF
and R
to maintain accurate voltage gain over
REF
BIP
current sets the input bias to the ladder network. Data bit 9
(DB9)(Q9), when turned on, will mirror this current and will
contribute 1mA to the output. DB8 (Q8) will contribute 1/2 of that
value or 0.5mA, and so on. These current values act as current
sinks and will add at the sum node to produce a DAC ladder to sum
node function of:
The output op amp also incorporates output short circuit protection
for both positive and negative excursions. During this fault condition
I
will limit at ±15mA typical. Recovery from this condition to
OUT
rated accuracy will be determined by duration of short-circuit and die
temperature stabilization.
765
August 31, 1994
Philips Semiconductors Linear Products
Product specification
10-Bit µP-compatible D/A converter
NE5020
R
V
= 20K, 10T POTENTIOMETER
–V
1
CC
CC
R
= 1MΩ
2
(22)
SUM
NODE
(OPTIONAL)
5k
DAC
CURRENT OUTPUT
–
(20)
V
C
OUT
FF
+
AMP
COMP
(23)
5k
(24)
C
C
Figure 14. Zero-Scale Adjustment
INT
REF
+
–
V
OUT
(15)
REF
V
OUT
REF
15k
5k
R
= 80k
V
ADJ
3
REF
R
3
= 10k
(14)
10T POT
Figure 15. Reference Adjust Circuit
potentiometer R until V
equals 0.000V in the unipolar mode or
OUT
Bipolar Output Voltage
1
–5.000V in the bipolar mode (see bipolar section accomplishes this
trim.
The NE5020 includes a thermally matched resistor, R , to offset
the output voltage by 5V to obtain –5V to +5V output voltage range
operation. This is accomplished by shorting Pins 18 and 22 (see
BIP
Full-Scale Adjustment
A recommended full-scale adjustment circuit, when using the
internal voltage reference, is shown in Figure 15. Potentiometer R
Figure 13). This connection produces a current equal to (V
REFIN –
) ÷ R
(1mA nominal), which is injected into the sum
node. Since full-scale current out is approximately 2mA
(1.9980mA), (2mA – 1mA)5kΩ = 5V will appear at the output. For
zero DAC output currents, 1mA is still injected into sum node and
= –(5kΩ) (1mA) = –5V. Zero-scale adjust and full-scale adjust
are performed as described below, noting that full-scale voltage is
now approximately +5V. Zero-scale adjust may be used to trim
SUM NODE
BIP
3
is adjusted until V
equals 9.99023V. In many applications where
OUT
the absolute accuracy of full-scale is of low importance when
compared to the other system accuracy factors this adjustment
circuit is optional.
V
OUT
As resistors R , R , and R
REF FB
shown in the Block Diagram are
BIP
V
OUT
= 0.00 with the MSB high or V
= –5.0V with all bits off.
OUT
integrated in close proximity, they match and track in value closely
over wide ambient temperature variations. Typical matching is less
than ±0.3% which implies that typical full-scale (or gain) error is less
than ±0.3% of ideal full-scale value.
Zero-Scale Adjustment
The method of trimming the small offset error that may exist when all
data bits are low is
shown in Figure 14. The trim is the result of injecting a current from
resistor R that counteracts the error current. Adjusting
2
766
August 31, 1994
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