NE56611-39GW [NXP]
Family of devices designed to generate a reset signal for a variety of microprocessor and logic systems; 家庭设备的设计，以产生一个复位信号，适用于各种微处理器和逻辑系统的
| 型号： | NE56611-39GW |
| 厂家： | 
NXP |
| 描述： | Family of devices designed to generate a reset signal for a variety of microprocessor and logic systems |
| 文件： | 总9页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NE56610/11/12 Series
System Reset
Rev 0
February, 2001
Preliminary Product Specification
General Description
The NE56610/11/12 series is a family of devices designed to generate a reset signal for a
variety of microprocessor and logic systems. Accurate reset signals are generated during
momentary power interruptions or when ever power supply voltages sag to intolerable levels.
The NE56610/11/12 incorporates an internal timer to provide reset delay and ensure proper
operating voltage has been attained. In addition, a manual reset pin is available. An Open
Collector output topology is incorporated to provide adaptability for a wide variety of logic and
microprocessor systems.
5
1
2
VCC
M/R
SUB
4
3
GND
VOUT
TSSOP5
NE56610/11/12 is available in the TSSOP5 surface mount package.
Features
• 12V DC Maximum Operating Voltage
• Low Operating Voltage (0.65 V)
• Internal Reset Delay Timer
• NE56610 (50 mS Typical)
• Offered in Reset Thresholds of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2,
4.3, 4.4, 4.5, 4.7 V DC
• Available in SSOP5 Surface Mount Package
• Manual Reset Input
• NE56611 (100mS Typical)
• NE56612 (200mS Typical)
Applications
• Micro-Computer Systems
• Logic Systems
• Battery Monitoring Systems
• Back-Up Power Supply Circuits
• Voltage Detection Circuits
• Mechanical Reset Circuits
Simplified Device Diagram
5
VCC
NE56610/11/12
VOUT
4
Reset
Delay
+
3
GND
VREF
1
M/R
2
SUB
Ordering Information
Description
Temperature Range
Order Code
DWG#
5-pin SOT23 (TSSOP5) plastic surface mount
-20 - +75 °C
-20 - +75 °C
-20 - +75 °C
NE56610-xxGW
NE56611-xxGW
NE56612-xxGW
TSSOP5
TSSOP5
TSSOP5
System Reset (100mS Typical Internal Reset Delay)
System Reset (200mS Typical Internal Reset Delay)
Note: Each device has 6 (six) detection voltage options, indicated by the -xx on the order code:
XX
Detect Voltage (Typ.)
XX
Detect Voltage (Typ.)
-25
-27
-29
2.5
2.7
2.9
-39
-42
-45
3.9
4.2
4.5
Philips Semiconductors
NE56610/11/12 Series
System Reset
Pin Designation and Description
Pin Designation
Pin No
Pin Name
Function
1
2
3
4
5
M/R
SUB
GND
VOUT
VCC
Manual Reset input. Connect to ground when not using.
Substrate Pin. Connect to ground.
Ground
5
1
2
3
Reset High Output pin
4
Positive Power Supply Input
Maximum Ratings
Parameter
Symbol
Rating
Unit
Storage Temperature Range
Ambient Operating Temperature Range
Power Supply Voltage
TSTG
TA
-40 - +125
-20 - +75
-0.3 - +12
-0.3 - +12
150
°C
°C
V
VCC max.
VRES max
Pd
Manual Reset Input Voltage
Power Dissipation
V
mW
Recommended Operating Conditions
Parameter
Symbol
Rating
Unit
Ambient Operating Temperature Range
Power Supply Voltage
TA
-20 - +75
-0.3 - +12
°C
VCC max.
V
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Philips Semiconductors
NE56610/11/12 Series
System Reset
DC ELECTRICAL CHARACTERISTICS
TA = 25°C, unless otherwise specified.
Note 1: Unless otherwise stated, M/R pin should always be connected to ground.
Test
Circuit
Parameter
Symbol
Part#
Min
Typ
Max
Unit
Threshold Detection
VS
1
-45
-42
-39
-29
-27
-25
All
4.3
4.0
4.5
4.2
4.7
4.4
V
VCC Falling
RL = 470Ω,
VOL ≤ 0.4V
3.7
3.9
4.1
2.75
2.55
2.35
30
2.90
2.70
2.50
50
3.05
2.85
2.65
100
Hysteresis Voltage
∆VS
1
mV
VCC = Rising then Falling (∆VS = VSH-VSL)
RL = 470Ω
Threshold Temperature Coefficient
TC / VS
VOL
1
1
1
1
1
2
All
All
All
All
All
±0.01
0.1
% / °C
V
RL = 470Ω, TA = -20°C - +75°C
Low-level Output Voltage
0.4
±0.1
500
25
VCC = VS min. -0.05V, RL = 470Ω
Output Leakage Current
VCC = 10V
IOH
µA
Circuit ON Current
ICCL
300
15
µA
VCC = VS min. -0.05V, RL = ∞
Circuit OFF Current
ICCH
TDLH
µA
VCC = VS typ./0.85V, RL = ∞
Reset Delay Time High (see note 1)
RL = 4.7kΩ
NE56610
NE56611
NE56612
All
30
60
50
100
200
20
75
mS
150
300
CL = 100pF
120
Reset Delay Time Low (see note 2)
TPHL
VOPL
IOL1
IOL2
2
1
1
1
mS
V
RL = 4.7kΩ, CL = 100pF
Operating Supply Voltage
All
All
All
0.65
0.85
RL = 4.7kΩ, VOL ≤ 0.4V
Output ON Current 1
8
6
mA
mA
VCC = VS min. -0.05V, RL = 0
Output On Current 2
VCC = VS min. -0.05V, RL = 0
TA = -20°C - +75°C
M/R Threshold High
VM/RH
IM/RH
All
All
2.0
V
M/R Threshold High
VM/RH = 2.0v
10
60
µA
M/R Threshold Low
VM/RL
All
-0.3
0.8
V
NOTES:
2. TDLH measured with VCC = (VS typ. -0.4V) and abruptly transitioning to (VS typ. +0.4)V. TDLH is duration from VCC transition high
to output transition high.
3. TDHL measured with VCC ≥ (VS typ. +0.4V) and abruptly transitioning to (VS typ. -0.4)V. TDHL is duration from VCC transition low
to output transition low.
4. Ramp M/R voltage until Output Reset goes low.
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Typical Performance Curves
Figure 1. Normalized Detection versus Temperature
Figure 2. Circuit ON Current versus Temperature
0.10
500
400
300
200
100
VCC = VS min. -0.05V
RL = ∞
Threshold Normalized to 25°C
RL (Pull-Up to VCC) 470Ω
VOL ≤ 0.4V
0.05
0.00
-0.05
-0.10
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
Figure 3.Detection Hysteresis versus Temperature
Figure 4. Circuit OFF Current versus Temperature
30
80
∆VS = VSH - VSL
VCC = VS typ. +0.85V
RL (Pull-Up to VCC) = 470Ω
RL = ∞
25
70
60
50
40
20
15
10
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
Figure 5. Low-Level Output Voltage versus Temperature
Figure 6. Operating Supply Voltage versus Temperature
900
120
VCC = VS min. -0.05V
RL (Pull-Up to VCC) 470Ω
VOL ≤ 0.4V
RL4.7kΩ
800
100
80
700
600
500
400
60
40
-50
-50
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Typical Performance Curves (continued)
Figure 7. Output ON Current versus Temperature
Figure 8. M/R Input High Current versus Temperature
70
25
VCC = 5.0V
VM/RH = 2.0V
VCC = VS min. -0.05V
RL
= 0
20
60
50
40
30
15
10
5.0
125
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
Figure 9. Reset Delay Time High versus Temperature
Figure 10. M/R Threshold High versus Temperature
250
1.6
VCC = 5.0V
225
SA56612
1.4
200
175
RL4.7kΩ
CL = 100pF
1.2
1.0
0.8
0.6
150
125
SA56611
100
75
SA56610
50
25
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TA, TEMPERATURE (°C)
TA, TEMPERATURE (°C)
Figure 11. Reset Delay Time Low versus Temperature
Figure 12. Icc and Vout versus Supply Voltage
14
500
5.0
4.0
3.0
2.0
1.0
RL4.7kΩ
CL = 100pF
VOUT
RL = 470Ω
TA = 25°C
400
300
200
100
0
13
12
11
10
∆VS
ICC
0
-50
-25
0
25
50
75
100 125
0
1.0
2.0
3.0
4.0
5.0
VCC, SUPPLY VOLTAGE (V)
TA, TEMPERATURE (°C)
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Typical Performance Curves (continued)
Figure 13. Output Sink Current versus Output Voltage
40
VCC = VS min. -0.05V
RL
= 0
35
30
25
20
15
10
5
TA = 25°C
0
0
0.2
0.4
0.6
0.8
1.0
VOUT, OUTPUT VOLTAGE (V)
Technical Discussion
Figure 14. Functional Schematic
VCC
5
delay
OSC
T
Q
VOUT Reset
R
4
GND
SUB
3
2
M/R
1
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Philips Semiconductors
TIMING DIAGRAM
NE56610/11/12 Series
System Reset
The Timing Diagram shown in Figure 15 depicts the operation
of the device. Letters indicate events on the Time axis.
E-F: Between "E" and "F", VCC recovers and starts
increasing.
A: At start-up, event "A", the VCC and Reset voltages begin to
rise. Also the Reset voltage initially rises but then abruptly
returns to a low state. This is due to VCC reaching the level
(approximately 0.8V) that activates the internal bias circuitry.
F: At "F", VCC reaches the VSH upper threshold. Once again,
the "H" transport delay time (TPLH) is initiated.
G: At "G", VCC is above the undervoltage detect threshold
and the "H" transport delay time (TPLH) has elapsed. At this point
B: At event "B", the "H" transport delay time (TPLH) is initiated. the device removes the hold on the VOUT reset. VOUT Reset
This is caused by and coincident to VCC reaching the threshold
level of VSH. At this level the device is in full operation. The
Reset output remains off as VCC rises above VSH. This is
normal.
goes high.
H-J: At event "H", VCC is normal, but a manual reset signal
from the logic device is applied at the M/R pin. With the falling
edge of the manual reset signal, the "H" transport delay time
(TPLH) is initiated. At "J", transport delay time (TPLH) has
elapsed and the Vout reset goes high.
C: At event "C" VCC is above the undervoltage detect
threshold and the "H" transport delay time (TPLH) has elapsed.
At this point the device removes the hold on the VOUT reset.
VOUT Reset goes high.
K: At event "K" VCC sags to the point where the VSL
undervoltage threshold point is reached and at that level VOUT
reset goes low.
In a microprocessor based system these events remove the
reset from the microprocessor, allowing it to function normally.
L: At event "L" the VCC voltage has deteriorated to a level
where normal internal circuit bias is no longer able to maintain a
VOUT reset and as a result may exhibit a slight rise to something
less than 0.8V. As VCC decays even further, VOUT reset also
decreases to zero.
D-E: At "D", VCC begins to ramp down causing VOUT to follow
it. VCC continues to sag until the VSL undervoltage threshold is
reached at "E". At that time, reset signal is generated (VOUT
Reset goes low).
Figure 15. Timing Diagram
V
B
C
D
F
H
K
L
∆VS
VSH
VSL
VS
VCC
V
V
VOUT
TPLH
TPLH
TPLH
A
B
C
E
G
J
K
L
M/R
VRES
H
TIME
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Application Information
When the manual reset is not needed, the M/R, manual reset
The second example, shown in Figure 17 - Manual Reset
pin is connected to ground as shown in Figure 16 - Typical Hard Circuit, incorporates a manual reset switch from the M/R pin to
Reset Circuit. A capacitor connected from VCC to ground is
recommended when the VCC supply impedance is appreciably
high. This may be the situation with a poor quality or aged
battery.
VCC. When the manual switch is closed, VOUT reset is logic
high. Conversely, when it is opened, VOUT reset is logic low. As
a precaution a clamp diode is placed from the M/R pin to ground
to insure that the pin does not go below - 0.3V.
Figure 16. Typical Hard Reset Circuit
Figure 17. Manual Reset Circuit
To CPU
Reset Pin
To VCC
To VCC
To CPU
Reset Pin
RL
RL
Manual
Switch
5
4
5
4
VCC
VOUT
VCC
VOUT
M/R
1
SUB GND
M/R
1
SUB GND
2
3
2
3
Clamp
Diode
Test Circuits
Figure 16. Test Circuit 1
Figure 17. Test Circuit 2
A2
RL
A1
10µF
/ 10V
5
RL
4
10µF
5
4
/ 10V
VOUT
VCC
VOUT
VCC
Input
5.0 V
Pulse
GND
M/R SUB
GND
M/R SUB
V2
VCC
V1
2
1
3
2
1
3
CRT
VRES
CL = 100pF
CRT = Oscilliscope
A - DC Ammeter
V = DC Voltmeter
Input Pulse
VS typ
+0.4V
-0.4V
VS typ
0V
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Philips Semiconductors
NE56610/11/12 Series
System Reset
Packing Method
The NE56610/11/12 is packed in reels, as shown here
Guard
Band
Tape Detail
Tape
Cover
Tape
Reel
Assembly
Carrier
Tape
Barcode
Label
Box
LEGAL DISCLAIMER GOES HERE
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